2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
24 #include <asm/errno.h>
27 #include <asm/arch/cpu.h>
29 #define BITMASK(bits) (BIT(bits) - 1)
31 #define PHY_REG_MASK 0x1f
32 #define PHY_ID_MASK 0x1f
33 #define NUM_DESCS (PKTBUFSRX * 2)
35 #define PKT_MAX (1500 + 14 + 4 + 4)
38 /* MAC_CONTROL register bits */
39 #define GIGABITEN BIT(7)
40 #define FULLDUPLEXEN BIT(0)
41 #define MAC_CTRL_CMD_IDLE BIT(11)
44 /* MAC_STATUS register bits */
45 #define MAC_STAT_IDLE BIT(31)
48 #define CPDMA_TXCONTROL 0x004
49 #define CPDMA_RXCONTROL 0x014
50 #define CPDMA_SOFTRESET 0x01c
51 #define CPDMA_DMACONTROL 0x020
52 #define CPDMA_DMASTATUS 0x024
53 #define CPDMA_RXFREE 0x0e0
54 #define CPDMA_TXHDP_VER1 0x100
55 #define CPDMA_TXHDP_VER2 0x200
56 #define CPDMA_RXHDP_VER1 0x120
57 #define CPDMA_RXHDP_VER2 0x220
58 #define CPDMA_TXCP_VER1 0x140
59 #define CPDMA_TXCP_VER2 0x240
60 #define CPDMA_RXCP_VER1 0x160
61 #define CPDMA_RXCP_VER2 0x260
63 #define DMACONTROL_CMD_IDLE BIT(3)
65 #define DMASTATUS_IDLE BIT(31)
67 /* Descriptor mode bits */
68 #define CPDMA_DESC_SOP BIT(31)
69 #define CPDMA_DESC_EOP BIT(30)
70 #define CPDMA_DESC_OWNER BIT(29)
71 #define CPDMA_DESC_EOQ BIT(28)
74 * This timeout definition is a worst-case ultra defensive measure against
75 * unexpected controller lock ups. Ideally, we should never ever hit this
76 * scenario in practice.
78 #define MDIO_TIMEOUT 100 /* msecs */
79 #define CPDMA_TIMEOUT 100 /* msecs */
81 struct cpsw_mdio_regs {
84 #define CONTROL_IDLE BIT(31)
85 #define CONTROL_ENABLE BIT(30)
101 #define USERACCESS_GO BIT(31)
102 #define USERACCESS_WRITE BIT(30)
103 #define USERACCESS_ACK BIT(29)
104 #define USERACCESS_READ 0
105 #define USERACCESS_DATA 0xffff
117 struct cpsw_slave_regs {
125 #elif defined(CONFIG_TI814X)
134 struct cpsw_host_regs {
140 u32 cpdma_tx_pri_map;
141 u32 cpdma_rx_chan_map;
144 struct cpsw_sliver_regs {
157 #define ALE_ENTRY_BITS 68
158 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
161 #define ALE_CONTROL 0x08
162 #define ALE_UNKNOWNVLAN 0x18
163 #define ALE_TABLE_CONTROL 0x20
164 #define ALE_TABLE 0x34
165 #define ALE_PORTCTL 0x40
167 #define ALE_TABLE_WRITE BIT(31)
169 #define ALE_TYPE_FREE 0
170 #define ALE_TYPE_ADDR 1
171 #define ALE_TYPE_VLAN 2
172 #define ALE_TYPE_VLAN_ADDR 3
174 #define ALE_UCAST_PERSISTANT 0
175 #define ALE_UCAST_UNTOUCHED 1
176 #define ALE_UCAST_OUI 2
177 #define ALE_UCAST_TOUCHED 3
179 #define ALE_MCAST_FWD 0
180 #define ALE_MCAST_BLOCK_LEARN_FWD 1
181 #define ALE_MCAST_FWD_LEARN 2
182 #define ALE_MCAST_FWD_2 3
184 enum cpsw_ale_port_state {
185 ALE_PORT_STATE_DISABLE = 0x00,
186 ALE_PORT_STATE_BLOCK = 0x01,
187 ALE_PORT_STATE_LEARN = 0x02,
188 ALE_PORT_STATE_FORWARD = 0x03,
191 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
193 #define ALE_BLOCKED 2
196 struct cpsw_slave_regs *regs;
197 struct cpsw_sliver_regs *sliver;
200 struct cpsw_slave_data *data;
204 /* hardware fields */
209 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
213 struct cpsw_desc *next;
214 struct cpdma_desc *dma_desc;
218 struct cpsw_desc *head, *tail;
219 void *hdp, *cp, *rxfree;
222 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->dma_desc->fld)
223 #define desc_read(desc, fld) __raw_readl(&(desc)->dma_desc->fld)
224 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->dma_desc->fld))
226 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
227 #define chan_read(chan, fld) __raw_readl((chan)->fld)
228 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
230 #define for_active_slave(slave, priv) \
231 slave = (priv)->slaves + (priv)->data->active_slave; if (slave)
232 #define for_each_slave(slave, priv) \
233 for (slave = (priv)->slaves; slave != (priv)->slaves + \
234 (priv)->data->slaves; slave++)
237 struct eth_device *dev;
238 struct cpsw_platform_data *data;
241 struct cpsw_regs *regs;
243 struct cpsw_host_regs *host_port_regs;
246 struct cpsw_desc descs[NUM_DESCS];
247 struct cpsw_desc *desc_free;
248 struct cpdma_chan rx_chan, tx_chan;
250 struct cpsw_slave *slaves;
251 struct phy_device *phydev;
257 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
263 idx = 2 - idx; /* flip */
264 return (ale_entry[idx] >> start) & BITMASK(bits);
267 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
272 value &= BITMASK(bits);
275 idx = 2 - idx; /* flip */
276 ale_entry[idx] &= ~(BITMASK(bits) << start);
277 ale_entry[idx] |= (value << start);
280 #define DEFINE_ALE_FIELD(name, start, bits) \
281 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
283 return cpsw_ale_get_field(ale_entry, start, bits); \
285 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
287 cpsw_ale_set_field(ale_entry, start, bits, value); \
290 DEFINE_ALE_FIELD(entry_type, 60, 2)
291 DEFINE_ALE_FIELD(mcast_state, 62, 2)
292 DEFINE_ALE_FIELD(port_mask, 66, 3)
293 DEFINE_ALE_FIELD(ucast_type, 62, 2)
294 DEFINE_ALE_FIELD(port_num, 66, 2)
295 DEFINE_ALE_FIELD(blocked, 65, 1)
296 DEFINE_ALE_FIELD(secure, 64, 1)
297 DEFINE_ALE_FIELD(mcast, 40, 1)
299 /* The MAC address field in the ALE entry cannot be macroized as above */
300 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
304 for (i = 0; i < 6; i++)
305 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
308 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
312 for (i = 0; i < 6; i++)
313 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
316 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
320 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
322 for (i = 0; i < ALE_ENTRY_WORDS; i++)
323 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
328 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
332 for (i = 0; i < ALE_ENTRY_WORDS; i++)
333 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
335 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
340 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
342 u32 ale_entry[ALE_ENTRY_WORDS];
345 for (idx = 0; idx < priv->data->ale_entries; idx++) {
348 cpsw_ale_read(priv, idx, ale_entry);
349 type = cpsw_ale_get_entry_type(ale_entry);
350 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
352 cpsw_ale_get_addr(ale_entry, entry_addr);
353 if (memcmp(entry_addr, addr, 6) == 0)
359 static int cpsw_ale_match_free(struct cpsw_priv *priv)
361 u32 ale_entry[ALE_ENTRY_WORDS];
364 for (idx = 0; idx < priv->data->ale_entries; idx++) {
365 cpsw_ale_read(priv, idx, ale_entry);
366 type = cpsw_ale_get_entry_type(ale_entry);
367 if (type == ALE_TYPE_FREE)
373 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
375 u32 ale_entry[ALE_ENTRY_WORDS];
378 for (idx = 0; idx < priv->data->ale_entries; idx++) {
379 cpsw_ale_read(priv, idx, ale_entry);
380 type = cpsw_ale_get_entry_type(ale_entry);
381 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
383 if (cpsw_ale_get_mcast(ale_entry))
385 type = cpsw_ale_get_ucast_type(ale_entry);
386 if (type != ALE_UCAST_PERSISTANT &&
387 type != ALE_UCAST_OUI)
393 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
396 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
399 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
400 cpsw_ale_set_addr(ale_entry, addr);
401 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
402 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
403 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
404 cpsw_ale_set_port_num(ale_entry, port);
406 idx = cpsw_ale_match_addr(priv, addr);
408 idx = cpsw_ale_match_free(priv);
410 idx = cpsw_ale_find_ageable(priv);
414 cpsw_ale_write(priv, idx, ale_entry);
418 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
421 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
424 idx = cpsw_ale_match_addr(priv, addr);
426 cpsw_ale_read(priv, idx, ale_entry);
428 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
429 cpsw_ale_set_addr(ale_entry, addr);
430 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
432 mask = cpsw_ale_get_port_mask(ale_entry);
434 cpsw_ale_set_port_mask(ale_entry, port_mask);
437 idx = cpsw_ale_match_free(priv);
439 idx = cpsw_ale_find_ageable(priv);
443 cpsw_ale_write(priv, idx, ale_entry);
447 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
449 u32 tmp, mask = BIT(bit);
451 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
453 tmp |= val ? mask : 0;
454 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
457 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
458 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
459 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
461 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
464 int offset = ALE_PORTCTL + 4 * port;
467 tmp = __raw_readl(priv->ale_regs + offset);
470 __raw_writel(tmp, priv->ale_regs + offset);
473 static struct cpsw_mdio_regs *mdio_regs;
475 /* wait until hardware is ready for another user access */
476 static inline u32 wait_for_user_access(void)
478 int timeout = MDIO_TIMEOUT;
481 while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
483 if (--timeout <= 0) {
484 printf("TIMEOUT waiting for USERACCESS_GO\n");
492 /* wait until hardware state machine is idle */
493 static inline void wait_for_idle(void)
495 int timeout = MDIO_TIMEOUT;
497 while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
498 if (--timeout <= 0) {
499 printf("TIMEOUT waiting for state machine idle\n");
506 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
507 int dev_addr, int phy_reg)
512 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
515 if (wait_for_user_access() & USERACCESS_GO)
516 /* promote error from previous access */
519 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
521 __raw_writel(reg, &mdio_regs->user[0].access);
522 reg = wait_for_user_access();
523 if (reg & USERACCESS_GO)
526 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
530 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
531 int phy_reg, u16 data)
535 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
538 if (wait_for_user_access() & USERACCESS_GO)
539 /* promote error from previous access */
542 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
543 (phy_id << 16) | (data & USERACCESS_DATA));
544 __raw_writel(reg, &mdio_regs->user[0].access);
545 if (wait_for_user_access() & USERACCESS_GO)
551 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
553 struct mii_dev *bus = mdio_alloc();
555 mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
557 /* set enable and clock divider */
558 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
561 * wait for scan logic to settle:
562 * the scan time consists of (a) a large fixed component, and (b) a
563 * small component that varies with the mii bus frequency. These
564 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
565 * silicon. Since the effect of (b) was found to be largely
566 * negligible, we keep things simple here.
570 bus->read = cpsw_mdio_read;
571 bus->write = cpsw_mdio_write;
572 sprintf(bus->name, name);
577 /* Set a self-clearing bit in a register, and wait for it to clear */
578 static inline void setbit_and_wait_for_clear32(void *addr)
582 __raw_writel(CLEAR_BIT, addr);
583 while (__raw_readl(addr) & CLEAR_BIT)
585 debug("%s: reset finished after %u loops\n", __func__, loops);
588 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
589 ((mac)[2] << 16) | ((mac)[3] << 24))
590 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
592 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
593 struct cpsw_priv *priv)
595 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
596 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
600 static void cpsw_slave_update_link(struct cpsw_slave *slave,
601 struct cpsw_priv *priv, int *link)
603 struct phy_device *phy = priv->phydev;
605 int retries = NUM_TRIES;
611 if (*link) { /* link up */
612 mac_control = priv->data->mac_control;
613 if (phy->speed == 1000)
614 mac_control |= GIGABITEN;
615 if (phy->duplex == DUPLEX_FULL)
616 mac_control |= FULLDUPLEXEN;
617 if (phy->speed == 100)
618 mac_control |= MIIEN;
622 } while (!*link && retries-- > 0);
623 debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
624 slave->mac_control, mac_control, NUM_TRIES - retries);
626 if (mac_control == slave->mac_control)
630 printf("link up on port %d, speed %d, %s duplex\n",
631 slave->slave_num, phy->speed,
632 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
634 printf("link down on port %d\n", slave->slave_num);
637 __raw_writel(mac_control, &slave->sliver->mac_control);
638 slave->mac_control = mac_control;
641 static int cpsw_update_link(struct cpsw_priv *priv)
644 struct cpsw_slave *slave;
646 for_active_slave(slave, priv)
647 cpsw_slave_update_link(slave, priv, &link);
652 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
654 if (priv->host_port == 0)
655 return slave_num + 1;
660 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
664 debug("%s\n", __func__);
665 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
667 /* setup priority mapping */
668 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
669 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
671 /* setup max packet size, and mac address */
672 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
673 cpsw_set_slave_mac(slave, priv);
675 slave->mac_control = 0; /* no link yet */
677 /* enable forwarding */
678 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
679 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
681 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
683 priv->phy_mask |= 1 << slave->data->phy_addr;
686 static void cpdma_desc_get(struct cpsw_desc *desc)
688 invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
691 static void cpdma_desc_put(struct cpsw_desc *desc)
693 flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
696 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
698 struct cpsw_desc *desc = priv->desc_free;
701 cpdma_desc_get(desc);
702 priv->desc_free = desc->next;
707 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
710 desc_write(desc, hw_next, priv->desc_free->dma_desc);
711 cpdma_desc_put(desc);
712 desc->next = priv->desc_free;
713 priv->desc_free = desc;
717 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
718 void *buffer, int len)
720 struct cpsw_desc *desc, *prev;
724 printf("ERROR: %s() NULL buffer\n", __func__);
728 flush_dcache_range((u32)buffer, (u32)buffer + len);
730 desc = cpdma_desc_alloc(priv);
734 debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
735 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
739 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
742 desc_write(desc, hw_next, 0);
743 desc_write(desc, hw_buffer, buffer);
744 desc_write(desc, hw_len, len);
745 desc_write(desc, hw_mode, mode | len);
747 desc->sw_buffer = buffer;
749 cpdma_desc_put(desc);
751 /* simple case - first packet enqueued */
754 chan_write(chan, hdp, desc->dma_desc);
758 /* not the first packet - enqueue at the tail */
762 cpdma_desc_get(prev);
763 desc_write(prev, hw_next, desc->dma_desc);
764 cpdma_desc_put(prev);
768 /* next check if EOQ has been triggered already */
769 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
770 chan_write(chan, hdp, desc->dma_desc);
774 chan_write(chan, rxfree, 1);
775 debug("%s@%d\n", __func__, __LINE__);
779 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
780 void **buffer, int *len)
782 struct cpsw_desc *desc = chan->head;
788 cpdma_desc_get(desc);
790 status = desc_read(desc, hw_mode);
791 if (status & CPDMA_DESC_OWNER)
795 *len = status & 0x7ff;
798 *buffer = desc->sw_buffer;
799 debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
801 chan->head = desc->next;
802 chan_write(chan, cp, desc->dma_desc);
804 cpdma_desc_free(priv, desc);
808 static int cpsw_init(struct eth_device *dev, bd_t *bis)
810 struct cpsw_priv *priv = dev->priv;
811 struct cpsw_slave *slave;
814 debug("%s\n", __func__);
815 /* soft reset the controller and initialize priv */
816 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
818 /* initialize and reset the address lookup engine */
819 cpsw_ale_enable(priv, 1);
820 cpsw_ale_clear(priv, 1);
821 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
823 /* setup host port priority mapping */
824 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
825 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
827 /* disable priority elevation and enable statistics on all ports */
828 __raw_writel(0, &priv->regs->ptype);
830 /* enable statistics collection only on the host port */
831 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
832 __raw_writel(0x7, &priv->regs->stat_port_en);
834 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
836 cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
838 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
840 for_active_slave(slave, priv)
841 cpsw_slave_init(slave, priv);
843 cpsw_update_link(priv);
845 /* init descriptor pool */
846 for (i = 0; i < NUM_DESCS; i++) {
847 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
848 &priv->descs[i + 1] : NULL;
850 priv->descs[i].next = next_desc;
851 desc_write(&priv->descs[i], hw_next,
852 next_desc ? next_desc->dma_desc : 0);
853 cpdma_desc_put(&priv->descs[i]);
855 priv->desc_free = &priv->descs[0];
857 /* initialize channels */
858 if (priv->data->version == CPSW_CTRL_VERSION_2) {
859 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
860 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
861 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
862 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
864 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
865 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
866 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
868 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
869 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
870 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
871 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
873 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
874 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
875 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
878 /* clear dma state */
879 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
881 if (priv->data->version == CPSW_CTRL_VERSION_2) {
882 for (i = 0; i < priv->data->channels; i++) {
883 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
884 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
885 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
886 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
887 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
890 for (i = 0; i < priv->data->channels; i++) {
891 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
892 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
893 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
894 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
895 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
900 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
901 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
903 /* submit rx descs */
904 for (i = 0; i < PKTBUFSRX; i++) {
905 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
908 printf("error %d submitting rx desc\n", ret);
916 static void cpsw_halt(struct eth_device *dev)
918 struct cpsw_priv *priv = dev->priv;
919 struct cpsw_slave *slave;
921 int timeout = 1000000;
923 __raw_writel(DMACONTROL_CMD_IDLE, priv->dma_regs + CPDMA_DMACONTROL);
924 while (!(__raw_readl(priv->dma_regs + CPDMA_DMASTATUS) &
925 DMASTATUS_IDLE) && (--timeout >= 0))
931 for_each_slave(slave, priv) {
932 if (!(__raw_readl(&slave->sliver->mac_status) &
938 if (idle || --timeout < 0)
943 printf("CPSW: Aborting DMA transfers; packets may be lost\n");
945 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
946 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
948 /* soft reset the controller and initialize priv */
949 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
951 /* clear dma state */
952 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
954 debug("%s\n", __func__);
955 priv->data->control(0);
958 static int cpsw_send(struct eth_device *dev, void *packet, int length)
960 struct cpsw_priv *priv = dev->priv;
965 /* first reap completed packets */
966 while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
969 return cpdma_submit(priv, &priv->tx_chan, packet, length);
972 static int cpsw_recv(struct eth_device *dev)
974 struct cpsw_priv *priv = dev->priv;
978 while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
980 net_process_received_packet(buffer, len);
981 cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
983 printf("NULL buffer returned from cpdma_process\n");
991 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
992 struct cpsw_priv *priv)
994 void *regs = priv->regs;
995 struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
997 debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
999 slave->slave_num = slave_num;
1001 slave->regs = regs + data->slave_reg_ofs;
1002 slave->sliver = regs + data->sliver_reg_ofs;
1005 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
1007 struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
1008 struct phy_device *phydev;
1009 u32 supported = PHY_GBIT_FEATURES;
1011 if (slave->data->phy_addr < 0) {
1014 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
1015 debug("Trying to connect to PHY @ addr %02x\n",
1017 phydev = phy_connect(priv->bus, phy_addr,
1018 dev, slave->data->phy_if);
1023 phydev = phy_connect(priv->bus,
1024 slave->data->phy_addr,
1026 slave->data->phy_if);
1029 printf("Failed to connect to PHY\n");
1036 phydev->supported &= supported;
1037 phydev->advertising = phydev->supported;
1039 priv->phydev = phydev;
1045 int cpsw_register(struct cpsw_platform_data *data)
1048 struct cpsw_priv *priv;
1049 struct cpsw_slave *slave;
1050 void *regs = (void *)data->cpsw_base;
1051 struct eth_device *dev;
1054 debug("%s@%d\n", __func__, __LINE__);
1056 dev = calloc(sizeof(*dev), 1);
1060 priv = calloc(sizeof(*priv), 1);
1069 priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
1070 if (!priv->slaves) {
1076 priv->host_port = data->host_port_num;
1078 priv->host_port_regs = regs + data->host_port_reg_ofs;
1079 priv->dma_regs = regs + data->cpdma_reg_ofs;
1080 priv->ale_regs = regs + data->ale_reg_ofs;
1082 for_each_slave(slave, priv) {
1083 cpsw_slave_setup(slave, idx, priv);
1087 strcpy(dev->name, "cpsw");
1089 dev->init = cpsw_init;
1090 dev->halt = cpsw_halt;
1091 dev->send = cpsw_send;
1092 dev->recv = cpsw_recv;
1097 cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1098 priv->bus = miiphy_get_dev_by_name(dev->name);
1099 for_active_slave(slave, priv)
1100 ret = cpsw_phy_init(dev, slave);