2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
23 #include <asm/errno.h>
26 #include <asm/arch/cpu.h>
28 #define BITMASK(bits) (BIT(bits) - 1)
30 #define PHY_REG_MASK 0x1f
31 #define PHY_ID_MASK 0x1f
32 #define NUM_DESCS (PKTBUFSRX * 2)
34 #define PKT_MAX (1500 + 14 + 4 + 4)
37 /* MAC_CONTROL register bits */
38 #define GIGABITEN BIT(7)
39 #define FULLDUPLEXEN BIT(0)
40 #define MAC_CTRL_CMD_IDLE BIT(11)
43 /* MAC_STATUS register bits */
44 #define MAC_STAT_IDLE BIT(31)
47 #define CPDMA_TXCONTROL 0x004
48 #define CPDMA_RXCONTROL 0x014
49 #define CPDMA_SOFTRESET 0x01c
50 #define CPDMA_DMACONTROL 0x020
51 #define CPDMA_DMASTATUS 0x024
52 #define CPDMA_RXFREE 0x0e0
53 #define CPDMA_TXHDP_VER1 0x100
54 #define CPDMA_TXHDP_VER2 0x200
55 #define CPDMA_RXHDP_VER1 0x120
56 #define CPDMA_RXHDP_VER2 0x220
57 #define CPDMA_TXCP_VER1 0x140
58 #define CPDMA_TXCP_VER2 0x240
59 #define CPDMA_RXCP_VER1 0x160
60 #define CPDMA_RXCP_VER2 0x260
62 #define DMACONTROL_CMD_IDLE BIT(3)
64 #define DMASTATUS_IDLE BIT(31)
66 /* Descriptor mode bits */
67 #define CPDMA_DESC_SOP BIT(31)
68 #define CPDMA_DESC_EOP BIT(30)
69 #define CPDMA_DESC_OWNER BIT(29)
70 #define CPDMA_DESC_EOQ BIT(28)
73 * This timeout definition is a worst-case ultra defensive measure against
74 * unexpected controller lock ups. Ideally, we should never ever hit this
75 * scenario in practice.
77 #define MDIO_TIMEOUT 100 /* msecs */
78 #define CPDMA_TIMEOUT 100 /* msecs */
80 struct cpsw_mdio_regs {
83 #define CONTROL_IDLE BIT(31)
84 #define CONTROL_ENABLE BIT(30)
100 #define USERACCESS_GO BIT(31)
101 #define USERACCESS_WRITE BIT(30)
102 #define USERACCESS_ACK BIT(29)
103 #define USERACCESS_READ 0
104 #define USERACCESS_DATA 0xffff
116 struct cpsw_slave_regs {
124 #elif defined(CONFIG_TI814X)
133 struct cpsw_host_regs {
139 u32 cpdma_tx_pri_map;
140 u32 cpdma_rx_chan_map;
143 struct cpsw_sliver_regs {
156 #define ALE_ENTRY_BITS 68
157 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
160 #define ALE_CONTROL 0x08
161 #define ALE_UNKNOWNVLAN 0x18
162 #define ALE_TABLE_CONTROL 0x20
163 #define ALE_TABLE 0x34
164 #define ALE_PORTCTL 0x40
166 #define ALE_TABLE_WRITE BIT(31)
168 #define ALE_TYPE_FREE 0
169 #define ALE_TYPE_ADDR 1
170 #define ALE_TYPE_VLAN 2
171 #define ALE_TYPE_VLAN_ADDR 3
173 #define ALE_UCAST_PERSISTANT 0
174 #define ALE_UCAST_UNTOUCHED 1
175 #define ALE_UCAST_OUI 2
176 #define ALE_UCAST_TOUCHED 3
178 #define ALE_MCAST_FWD 0
179 #define ALE_MCAST_BLOCK_LEARN_FWD 1
180 #define ALE_MCAST_FWD_LEARN 2
181 #define ALE_MCAST_FWD_2 3
183 enum cpsw_ale_port_state {
184 ALE_PORT_STATE_DISABLE = 0x00,
185 ALE_PORT_STATE_BLOCK = 0x01,
186 ALE_PORT_STATE_LEARN = 0x02,
187 ALE_PORT_STATE_FORWARD = 0x03,
190 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
192 #define ALE_BLOCKED 2
195 struct cpsw_slave_regs *regs;
196 struct cpsw_sliver_regs *sliver;
199 struct cpsw_slave_data *data;
203 /* hardware fields */
208 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
212 struct cpsw_desc *next;
213 struct cpdma_desc *dma_desc;
217 struct cpsw_desc *head, *tail;
218 void *hdp, *cp, *rxfree;
221 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->dma_desc->fld)
222 #define desc_read(desc, fld) __raw_readl(&(desc)->dma_desc->fld)
223 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->dma_desc->fld))
225 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
226 #define chan_read(chan, fld) __raw_readl((chan)->fld)
227 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
229 #define for_active_slave(slave, priv) \
230 slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
231 #define for_each_slave(slave, priv) \
232 for (slave = (priv)->slaves; slave != (priv)->slaves + \
233 (priv)->data->slaves; slave++)
236 struct eth_device *dev;
237 struct cpsw_platform_data *data;
240 struct cpsw_regs *regs;
242 struct cpsw_host_regs *host_port_regs;
245 struct cpsw_desc descs[NUM_DESCS];
246 struct cpsw_desc *desc_free;
247 struct cpdma_chan rx_chan, tx_chan;
249 struct cpsw_slave *slaves;
250 struct phy_device *phydev;
256 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
262 idx = 2 - idx; /* flip */
263 return (ale_entry[idx] >> start) & BITMASK(bits);
266 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
271 value &= BITMASK(bits);
274 idx = 2 - idx; /* flip */
275 ale_entry[idx] &= ~(BITMASK(bits) << start);
276 ale_entry[idx] |= (value << start);
279 #define DEFINE_ALE_FIELD(name, start, bits) \
280 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
282 return cpsw_ale_get_field(ale_entry, start, bits); \
284 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
286 cpsw_ale_set_field(ale_entry, start, bits, value); \
289 DEFINE_ALE_FIELD(entry_type, 60, 2)
290 DEFINE_ALE_FIELD(mcast_state, 62, 2)
291 DEFINE_ALE_FIELD(port_mask, 66, 3)
292 DEFINE_ALE_FIELD(ucast_type, 62, 2)
293 DEFINE_ALE_FIELD(port_num, 66, 2)
294 DEFINE_ALE_FIELD(blocked, 65, 1)
295 DEFINE_ALE_FIELD(secure, 64, 1)
296 DEFINE_ALE_FIELD(mcast, 40, 1)
298 /* The MAC address field in the ALE entry cannot be macroized as above */
299 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
303 for (i = 0; i < 6; i++)
304 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
307 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
311 for (i = 0; i < 6; i++)
312 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
315 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
319 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
321 for (i = 0; i < ALE_ENTRY_WORDS; i++)
322 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
327 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
331 for (i = 0; i < ALE_ENTRY_WORDS; i++)
332 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
334 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
339 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
341 u32 ale_entry[ALE_ENTRY_WORDS];
344 for (idx = 0; idx < priv->data->ale_entries; idx++) {
347 cpsw_ale_read(priv, idx, ale_entry);
348 type = cpsw_ale_get_entry_type(ale_entry);
349 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
351 cpsw_ale_get_addr(ale_entry, entry_addr);
352 if (memcmp(entry_addr, addr, 6) == 0)
358 static int cpsw_ale_match_free(struct cpsw_priv *priv)
360 u32 ale_entry[ALE_ENTRY_WORDS];
363 for (idx = 0; idx < priv->data->ale_entries; idx++) {
364 cpsw_ale_read(priv, idx, ale_entry);
365 type = cpsw_ale_get_entry_type(ale_entry);
366 if (type == ALE_TYPE_FREE)
372 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
374 u32 ale_entry[ALE_ENTRY_WORDS];
377 for (idx = 0; idx < priv->data->ale_entries; idx++) {
378 cpsw_ale_read(priv, idx, ale_entry);
379 type = cpsw_ale_get_entry_type(ale_entry);
380 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
382 if (cpsw_ale_get_mcast(ale_entry))
384 type = cpsw_ale_get_ucast_type(ale_entry);
385 if (type != ALE_UCAST_PERSISTANT &&
386 type != ALE_UCAST_OUI)
392 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
395 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
398 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
399 cpsw_ale_set_addr(ale_entry, addr);
400 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
401 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
402 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
403 cpsw_ale_set_port_num(ale_entry, port);
405 idx = cpsw_ale_match_addr(priv, addr);
407 idx = cpsw_ale_match_free(priv);
409 idx = cpsw_ale_find_ageable(priv);
413 cpsw_ale_write(priv, idx, ale_entry);
417 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
420 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
423 idx = cpsw_ale_match_addr(priv, addr);
425 cpsw_ale_read(priv, idx, ale_entry);
427 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
428 cpsw_ale_set_addr(ale_entry, addr);
429 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
431 mask = cpsw_ale_get_port_mask(ale_entry);
433 cpsw_ale_set_port_mask(ale_entry, port_mask);
436 idx = cpsw_ale_match_free(priv);
438 idx = cpsw_ale_find_ageable(priv);
442 cpsw_ale_write(priv, idx, ale_entry);
446 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
448 u32 tmp, mask = BIT(bit);
450 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
452 tmp |= val ? mask : 0;
453 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
456 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
457 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
458 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
460 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
463 int offset = ALE_PORTCTL + 4 * port;
466 tmp = __raw_readl(priv->ale_regs + offset);
469 __raw_writel(tmp, priv->ale_regs + offset);
472 static struct cpsw_mdio_regs *mdio_regs;
474 /* wait until hardware is ready for another user access */
475 static inline u32 wait_for_user_access(void)
477 int timeout = MDIO_TIMEOUT;
480 while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
482 if (--timeout <= 0) {
483 printf("TIMEOUT waiting for USERACCESS_GO\n");
491 /* wait until hardware state machine is idle */
492 static inline void wait_for_idle(void)
494 int timeout = MDIO_TIMEOUT;
496 while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
497 if (--timeout <= 0) {
498 printf("TIMEOUT waiting for state machine idle\n");
505 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
506 int dev_addr, int phy_reg)
511 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
514 if (wait_for_user_access() & USERACCESS_GO)
515 /* promote error from previous access */
518 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
520 __raw_writel(reg, &mdio_regs->user[0].access);
521 reg = wait_for_user_access();
522 if (reg & USERACCESS_GO)
525 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
529 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
530 int phy_reg, u16 data)
534 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
537 if (wait_for_user_access() & USERACCESS_GO)
538 /* promote error from previous access */
541 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
542 (phy_id << 16) | (data & USERACCESS_DATA));
543 __raw_writel(reg, &mdio_regs->user[0].access);
544 if (wait_for_user_access() & USERACCESS_GO)
550 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
552 struct mii_dev *bus = mdio_alloc();
554 mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
556 /* set enable and clock divider */
557 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
560 * wait for scan logic to settle:
561 * the scan time consists of (a) a large fixed component, and (b) a
562 * small component that varies with the mii bus frequency. These
563 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
564 * silicon. Since the effect of (b) was found to be largely
565 * negligible, we keep things simple here.
569 bus->read = cpsw_mdio_read;
570 bus->write = cpsw_mdio_write;
571 sprintf(bus->name, name);
576 /* Set a self-clearing bit in a register, and wait for it to clear */
577 static inline void setbit_and_wait_for_clear32(void *addr)
581 __raw_writel(CLEAR_BIT, addr);
582 while (__raw_readl(addr) & CLEAR_BIT)
584 debug("%s: reset finished after %u loops\n", __func__, loops);
587 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
588 ((mac)[2] << 16) | ((mac)[3] << 24))
589 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
591 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
592 struct cpsw_priv *priv)
594 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
595 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
599 static void cpsw_slave_update_link(struct cpsw_slave *slave,
600 struct cpsw_priv *priv, int *link)
602 struct phy_device *phy;
604 int retries = NUM_TRIES;
610 if (*link) { /* link up */
611 mac_control = priv->data->mac_control;
612 if (phy->speed == 1000)
613 mac_control |= GIGABITEN;
614 if (phy->duplex == DUPLEX_FULL)
615 mac_control |= FULLDUPLEXEN;
616 if (phy->speed == 100)
617 mac_control |= MIIEN;
621 } while (!*link && retries-- > 0);
622 debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
623 slave->mac_control, mac_control, NUM_TRIES - retries);
625 if (mac_control == slave->mac_control)
629 printf("link up on port %d, speed %d, %s duplex\n",
630 slave->slave_num, phy->speed,
631 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
633 printf("link down on port %d\n", slave->slave_num);
636 __raw_writel(mac_control, &slave->sliver->mac_control);
637 slave->mac_control = mac_control;
640 static int cpsw_update_link(struct cpsw_priv *priv)
643 struct cpsw_slave *slave;
645 for_active_slave(slave, priv)
646 cpsw_slave_update_link(slave, priv, &link);
651 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
653 if (priv->host_port == 0)
654 return slave_num + 1;
659 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
663 debug("%s\n", __func__);
664 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
666 /* setup priority mapping */
667 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
668 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
670 /* setup max packet size, and mac address */
671 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
672 cpsw_set_slave_mac(slave, priv);
674 slave->mac_control = 0; /* no link yet */
676 /* enable forwarding */
677 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
678 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
680 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
682 priv->phy_mask |= 1 << slave->data->phy_addr;
685 static void cpdma_desc_get(struct cpsw_desc *desc)
687 invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
690 static void cpdma_desc_put(struct cpsw_desc *desc)
692 flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
695 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
697 struct cpsw_desc *desc = priv->desc_free;
700 cpdma_desc_get(desc);
701 priv->desc_free = desc->next;
706 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
709 desc_write(desc, hw_next, priv->desc_free->dma_desc);
710 cpdma_desc_put(desc);
711 desc->next = priv->desc_free;
712 priv->desc_free = desc;
716 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
717 void *buffer, int len)
719 struct cpsw_desc *desc, *prev;
723 printf("ERROR: %s() NULL buffer\n", __func__);
727 flush_dcache_range((u32)buffer, (u32)buffer + len);
729 desc = cpdma_desc_alloc(priv);
733 debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
734 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
738 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
741 desc_write(desc, hw_next, 0);
742 desc_write(desc, hw_buffer, buffer);
743 desc_write(desc, hw_len, len);
744 desc_write(desc, hw_mode, mode | len);
746 desc->sw_buffer = buffer;
748 cpdma_desc_put(desc);
750 /* simple case - first packet enqueued */
753 chan_write(chan, hdp, desc->dma_desc);
757 /* not the first packet - enqueue at the tail */
761 cpdma_desc_get(prev);
762 desc_write(prev, hw_next, desc->dma_desc);
763 cpdma_desc_put(prev);
767 /* next check if EOQ has been triggered already */
768 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
769 chan_write(chan, hdp, desc->dma_desc);
773 chan_write(chan, rxfree, 1);
774 debug("%s@%d\n", __func__, __LINE__);
778 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
779 void **buffer, int *len)
781 struct cpsw_desc *desc = chan->head;
787 cpdma_desc_get(desc);
789 status = desc_read(desc, hw_mode);
790 if (status & CPDMA_DESC_OWNER)
794 *len = status & 0x7ff;
797 *buffer = desc->sw_buffer;
798 debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
800 chan->head = desc->next;
801 chan_write(chan, cp, desc->dma_desc);
803 cpdma_desc_free(priv, desc);
807 static int cpsw_init(struct eth_device *dev, bd_t *bis)
809 struct cpsw_priv *priv = dev->priv;
810 struct cpsw_slave *slave;
813 debug("%s\n", __func__);
814 /* soft reset the controller and initialize priv */
815 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
817 /* initialize and reset the address lookup engine */
818 cpsw_ale_enable(priv, 1);
819 cpsw_ale_clear(priv, 1);
820 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
822 /* setup host port priority mapping */
823 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
824 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
826 /* disable priority elevation and enable statistics on all ports */
827 __raw_writel(0, &priv->regs->ptype);
829 /* enable statistics collection only on the host port */
830 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
831 __raw_writel(0x7, &priv->regs->stat_port_en);
833 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
835 cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
837 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
839 for_active_slave(slave, priv)
840 cpsw_slave_init(slave, priv);
842 cpsw_update_link(priv);
844 /* init descriptor pool */
845 for (i = 0; i < NUM_DESCS; i++) {
846 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
847 &priv->descs[i + 1] : NULL;
849 priv->descs[i].next = next_desc;
850 desc_write(&priv->descs[i], hw_next,
851 next_desc ? next_desc->dma_desc : 0);
852 cpdma_desc_put(&priv->descs[i]);
854 priv->desc_free = &priv->descs[0];
856 /* initialize channels */
857 if (priv->data->version == CPSW_CTRL_VERSION_2) {
858 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
859 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
860 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
861 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
863 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
864 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
865 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
867 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
868 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
869 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
870 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
872 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
873 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
874 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
877 /* clear dma state */
878 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
880 if (priv->data->version == CPSW_CTRL_VERSION_2) {
881 for (i = 0; i < priv->data->channels; i++) {
882 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
883 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
884 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
885 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
886 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
889 for (i = 0; i < priv->data->channels; i++) {
890 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
891 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
892 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
893 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
894 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
899 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
900 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
902 /* submit rx descs */
903 for (i = 0; i < PKTBUFSRX; i++) {
904 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
907 printf("error %d submitting rx desc\n", ret);
915 static void cpsw_halt(struct eth_device *dev)
917 struct cpsw_priv *priv = dev->priv;
918 struct cpsw_slave *slave;
920 int timeout = 1000000;
922 __raw_writel(DMACONTROL_CMD_IDLE, priv->dma_regs + CPDMA_DMACONTROL);
923 while (!(__raw_readl(priv->dma_regs + CPDMA_DMASTATUS) &
924 DMASTATUS_IDLE) && (--timeout >= 0))
930 for_each_slave(slave, priv) {
931 if (!(__raw_readl(&slave->sliver->mac_status) &
937 if (idle || --timeout < 0)
942 printf("CPSW: Aborting DMA transfers; packets may be lost\n");
944 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
945 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
947 /* soft reset the controller and initialize priv */
948 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
950 /* clear dma state */
951 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
953 debug("%s\n", __func__);
954 priv->data->control(0);
957 static int cpsw_send(struct eth_device *dev, void *packet, int length)
959 struct cpsw_priv *priv = dev->priv;
964 /* first reap completed packets */
965 while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
968 return cpdma_submit(priv, &priv->tx_chan, packet, length);
971 static int cpsw_recv(struct eth_device *dev)
973 struct cpsw_priv *priv = dev->priv;
977 while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
979 net_process_received_packet(buffer, len);
980 cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
982 printf("NULL buffer returned from cpdma_process\n");
990 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
991 struct cpsw_priv *priv)
993 void *regs = priv->regs;
994 struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
996 debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
998 slave->slave_num = slave_num;
1000 slave->regs = regs + data->slave_reg_ofs;
1001 slave->sliver = regs + data->sliver_reg_ofs;
1004 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
1006 struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
1007 struct phy_device *phydev;
1008 u32 supported = PHY_GBIT_FEATURES;
1010 if (slave->data->phy_id < 0) {
1013 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
1014 debug("Trying to connect to PHY @ addr %02x\n",
1016 phydev = phy_connect(priv->bus, phy_addr,
1017 dev, slave->data->phy_if);
1022 phydev = phy_connect(priv->bus,
1023 slave->data->phy_id,
1025 slave->data->phy_if);
1028 printf("Failed to connect to PHY\n");
1035 phydev->supported &= supported;
1036 phydev->advertising = phydev->supported;
1038 priv->phydev = phydev;
1044 int cpsw_register(struct cpsw_platform_data *data)
1047 struct cpsw_priv *priv;
1048 struct cpsw_slave *slave;
1049 void *regs = (void *)data->cpsw_base;
1050 struct eth_device *dev;
1054 debug("%s@%d\n", __func__, __LINE__);
1056 dev = calloc(sizeof(*dev), 1);
1060 priv = calloc(sizeof(*priv), 1);
1069 priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
1070 if (!priv->slaves) {
1076 priv->host_port = data->host_port_num;
1078 priv->host_port_regs = regs + data->host_port_reg_ofs;
1079 priv->dma_regs = regs + data->cpdma_reg_ofs;
1080 priv->ale_regs = regs + data->ale_reg_ofs;
1081 priv->descs = (void *)regs + data->bd_ram_ofs;
1083 for_each_slave(slave, priv) {
1084 cpsw_slave_setup(slave, idx, priv);
1088 strcpy(dev->name, "cpsw");
1090 dev->init = cpsw_init;
1091 dev->halt = cpsw_halt;
1092 dev->send = cpsw_send;
1093 dev->recv = cpsw_recv;
1098 cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1099 priv->bus = miiphy_get_dev_by_name(dev->name);
1100 for_active_slave(slave, priv) {
1101 ret = cpsw_phy_init(dev, slave);