2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
23 #include <asm/errno.h>
26 #include <asm/arch/cpu.h>
28 #define BITMASK(bits) (BIT(bits) - 1)
30 #define PHY_REG_MASK 0x1f
31 #define PHY_ID_MASK 0x1f
32 #define NUM_DESCS (PKTBUFSRX * 2)
34 #define PKT_MAX (1500 + 14 + 4 + 4)
37 /* MAC_CONTROL register bits */
38 #define GIGABITEN BIT(7)
39 #define FULLDUPLEXEN BIT(0)
40 #define MAC_CTRL_CMD_IDLE BIT(11)
43 /* MAC_STATUS register bits */
44 #define MAC_STAT_IDLE BIT(31)
47 #define CPDMA_TXCONTROL 0x004
48 #define CPDMA_RXCONTROL 0x014
49 #define CPDMA_SOFTRESET 0x01c
50 #define CPDMA_DMACONTROL 0x020
51 #define CPDMA_DMASTATUS 0x024
52 #define CPDMA_RXFREE 0x0e0
53 #define CPDMA_TXHDP_VER1 0x100
54 #define CPDMA_TXHDP_VER2 0x200
55 #define CPDMA_RXHDP_VER1 0x120
56 #define CPDMA_RXHDP_VER2 0x220
57 #define CPDMA_TXCP_VER1 0x140
58 #define CPDMA_TXCP_VER2 0x240
59 #define CPDMA_RXCP_VER1 0x160
60 #define CPDMA_RXCP_VER2 0x260
62 #define DMACONTROL_CMD_IDLE BIT(3)
64 #define DMASTATUS_IDLE BIT(31)
66 #define CPDMA_RAM_ADDR 0x4a102000
68 /* Descriptor mode bits */
69 #define CPDMA_DESC_SOP BIT(31)
70 #define CPDMA_DESC_EOP BIT(30)
71 #define CPDMA_DESC_OWNER BIT(29)
72 #define CPDMA_DESC_EOQ BIT(28)
75 * This timeout definition is a worst-case ultra defensive measure against
76 * unexpected controller lock ups. Ideally, we should never ever hit this
77 * scenario in practice.
79 #define MDIO_TIMEOUT 100 /* msecs */
80 #define CPDMA_TIMEOUT 100 /* msecs */
82 struct cpsw_mdio_regs {
85 #define CONTROL_IDLE BIT(31)
86 #define CONTROL_ENABLE BIT(30)
102 #define USERACCESS_GO BIT(31)
103 #define USERACCESS_WRITE BIT(30)
104 #define USERACCESS_ACK BIT(29)
105 #define USERACCESS_READ 0
106 #define USERACCESS_DATA 0xffff
118 struct cpsw_slave_regs {
126 #elif defined(CONFIG_TI814X)
135 struct cpsw_host_regs {
141 u32 cpdma_tx_pri_map;
142 u32 cpdma_rx_chan_map;
145 struct cpsw_sliver_regs {
158 #define ALE_ENTRY_BITS 68
159 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
162 #define ALE_CONTROL 0x08
163 #define ALE_UNKNOWNVLAN 0x18
164 #define ALE_TABLE_CONTROL 0x20
165 #define ALE_TABLE 0x34
166 #define ALE_PORTCTL 0x40
168 #define ALE_TABLE_WRITE BIT(31)
170 #define ALE_TYPE_FREE 0
171 #define ALE_TYPE_ADDR 1
172 #define ALE_TYPE_VLAN 2
173 #define ALE_TYPE_VLAN_ADDR 3
175 #define ALE_UCAST_PERSISTANT 0
176 #define ALE_UCAST_UNTOUCHED 1
177 #define ALE_UCAST_OUI 2
178 #define ALE_UCAST_TOUCHED 3
180 #define ALE_MCAST_FWD 0
181 #define ALE_MCAST_BLOCK_LEARN_FWD 1
182 #define ALE_MCAST_FWD_LEARN 2
183 #define ALE_MCAST_FWD_2 3
185 enum cpsw_ale_port_state {
186 ALE_PORT_STATE_DISABLE = 0x00,
187 ALE_PORT_STATE_BLOCK = 0x01,
188 ALE_PORT_STATE_LEARN = 0x02,
189 ALE_PORT_STATE_FORWARD = 0x03,
192 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
194 #define ALE_BLOCKED 2
197 struct cpsw_slave_regs *regs;
198 struct cpsw_sliver_regs *sliver;
201 struct cpsw_slave_data *data;
205 /* hardware fields */
210 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
214 struct cpsw_desc *next;
215 struct cpdma_desc *dma_desc;
219 struct cpsw_desc *head, *tail;
220 void *hdp, *cp, *rxfree;
223 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->dma_desc->fld)
224 #define desc_read(desc, fld) __raw_readl(&(desc)->dma_desc->fld)
225 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->dma_desc->fld))
227 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
228 #define chan_read(chan, fld) __raw_readl((chan)->fld)
229 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
231 #define for_each_slave(slave, priv) \
232 for (slave = (priv)->slaves; slave != (priv)->slaves + \
233 (priv)->data->slaves; slave++)
236 struct eth_device *dev;
237 struct cpsw_platform_data *data;
240 struct cpsw_regs *regs;
242 struct cpsw_host_regs *host_port_regs;
245 struct cpsw_desc descs[NUM_DESCS];
246 struct cpsw_desc *desc_free;
247 struct cpdma_chan rx_chan, tx_chan;
249 struct cpsw_slave *slaves;
250 struct phy_device *phydev;
257 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
263 idx = 2 - idx; /* flip */
264 return (ale_entry[idx] >> start) & BITMASK(bits);
267 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
272 value &= BITMASK(bits);
275 idx = 2 - idx; /* flip */
276 ale_entry[idx] &= ~(BITMASK(bits) << start);
277 ale_entry[idx] |= (value << start);
280 #define DEFINE_ALE_FIELD(name, start, bits) \
281 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
283 return cpsw_ale_get_field(ale_entry, start, bits); \
285 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
287 cpsw_ale_set_field(ale_entry, start, bits, value); \
290 DEFINE_ALE_FIELD(entry_type, 60, 2)
291 DEFINE_ALE_FIELD(mcast_state, 62, 2)
292 DEFINE_ALE_FIELD(port_mask, 66, 3)
293 DEFINE_ALE_FIELD(ucast_type, 62, 2)
294 DEFINE_ALE_FIELD(port_num, 66, 2)
295 DEFINE_ALE_FIELD(blocked, 65, 1)
296 DEFINE_ALE_FIELD(secure, 64, 1)
297 DEFINE_ALE_FIELD(mcast, 40, 1)
299 /* The MAC address field in the ALE entry cannot be macroized as above */
300 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
304 for (i = 0; i < 6; i++)
305 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
308 static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
312 for (i = 0; i < 6; i++)
313 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
316 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
320 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
322 for (i = 0; i < ALE_ENTRY_WORDS; i++)
323 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
328 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
332 for (i = 0; i < ALE_ENTRY_WORDS; i++)
333 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
335 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
340 static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
342 u32 ale_entry[ALE_ENTRY_WORDS];
345 for (idx = 0; idx < priv->data->ale_entries; idx++) {
348 cpsw_ale_read(priv, idx, ale_entry);
349 type = cpsw_ale_get_entry_type(ale_entry);
350 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
352 cpsw_ale_get_addr(ale_entry, entry_addr);
353 if (memcmp(entry_addr, addr, 6) == 0)
359 static int cpsw_ale_match_free(struct cpsw_priv *priv)
361 u32 ale_entry[ALE_ENTRY_WORDS];
364 for (idx = 0; idx < priv->data->ale_entries; idx++) {
365 cpsw_ale_read(priv, idx, ale_entry);
366 type = cpsw_ale_get_entry_type(ale_entry);
367 if (type == ALE_TYPE_FREE)
373 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
375 u32 ale_entry[ALE_ENTRY_WORDS];
378 for (idx = 0; idx < priv->data->ale_entries; idx++) {
379 cpsw_ale_read(priv, idx, ale_entry);
380 type = cpsw_ale_get_entry_type(ale_entry);
381 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
383 if (cpsw_ale_get_mcast(ale_entry))
385 type = cpsw_ale_get_ucast_type(ale_entry);
386 if (type != ALE_UCAST_PERSISTANT &&
387 type != ALE_UCAST_OUI)
393 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
396 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
399 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
400 cpsw_ale_set_addr(ale_entry, addr);
401 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
402 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
403 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
404 cpsw_ale_set_port_num(ale_entry, port);
406 idx = cpsw_ale_match_addr(priv, addr);
408 idx = cpsw_ale_match_free(priv);
410 idx = cpsw_ale_find_ageable(priv);
414 cpsw_ale_write(priv, idx, ale_entry);
418 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
420 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
423 idx = cpsw_ale_match_addr(priv, addr);
425 cpsw_ale_read(priv, idx, ale_entry);
427 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
428 cpsw_ale_set_addr(ale_entry, addr);
429 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
431 mask = cpsw_ale_get_port_mask(ale_entry);
433 cpsw_ale_set_port_mask(ale_entry, port_mask);
436 idx = cpsw_ale_match_free(priv);
438 idx = cpsw_ale_find_ageable(priv);
442 cpsw_ale_write(priv, idx, ale_entry);
446 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
448 u32 tmp, mask = BIT(bit);
450 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
452 tmp |= val ? mask : 0;
453 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
456 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
457 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
458 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
460 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
463 int offset = ALE_PORTCTL + 4 * port;
466 tmp = __raw_readl(priv->ale_regs + offset);
469 __raw_writel(tmp, priv->ale_regs + offset);
472 static struct cpsw_mdio_regs *mdio_regs;
474 /* wait until hardware is ready for another user access */
475 static inline u32 wait_for_user_access(void)
477 int timeout = MDIO_TIMEOUT;
480 while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
482 if (--timeout <= 0) {
483 printf("TIMEOUT waiting for USERACCESS_GO\n");
491 /* wait until hardware state machine is idle */
492 static inline void wait_for_idle(void)
494 int timeout = MDIO_TIMEOUT;
496 while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
497 if (--timeout <= 0) {
498 printf("TIMEOUT waiting for state machine idle\n");
505 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
506 int dev_addr, int phy_reg)
511 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
514 if (wait_for_user_access() & USERACCESS_GO)
515 /* promote error from previous access */
518 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
520 __raw_writel(reg, &mdio_regs->user[0].access);
521 reg = wait_for_user_access();
522 if (reg & USERACCESS_GO)
525 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
529 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
530 int phy_reg, u16 data)
534 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
537 if (wait_for_user_access() & USERACCESS_GO)
538 /* promote error from previous access */
541 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
542 (phy_id << 16) | (data & USERACCESS_DATA));
543 __raw_writel(reg, &mdio_regs->user[0].access);
544 if (wait_for_user_access() & USERACCESS_GO)
550 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
552 struct mii_dev *bus = mdio_alloc();
554 mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
556 /* set enable and clock divider */
557 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
560 * wait for scan logic to settle:
561 * the scan time consists of (a) a large fixed component, and (b) a
562 * small component that varies with the mii bus frequency. These
563 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
564 * silicon. Since the effect of (b) was found to be largely
565 * negligible, we keep things simple here.
569 bus->read = cpsw_mdio_read;
570 bus->write = cpsw_mdio_write;
571 sprintf(bus->name, name);
576 /* Set a self-clearing bit in a register, and wait for it to clear */
577 static inline void setbit_and_wait_for_clear32(void *addr)
581 __raw_writel(CLEAR_BIT, addr);
582 while (__raw_readl(addr) & CLEAR_BIT)
584 debug("%s: reset finished after %u loops\n", __func__, loops);
587 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
588 ((mac)[2] << 16) | ((mac)[3] << 24))
589 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
591 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
592 struct cpsw_priv *priv)
594 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
595 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
599 static void cpsw_slave_update_link(struct cpsw_slave *slave,
600 struct cpsw_priv *priv, int *link)
602 struct phy_device *phy = priv->phydev;
604 int retries = NUM_TRIES;
610 if (*link) { /* link up */
611 mac_control = priv->data->mac_control;
612 if (phy->speed == 1000)
613 mac_control |= GIGABITEN;
614 if (phy->duplex == DUPLEX_FULL)
615 mac_control |= FULLDUPLEXEN;
616 if (phy->speed == 100)
617 mac_control |= MIIEN;
621 } while (!*link && retries-- > 0);
622 debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
623 slave->mac_control, mac_control, NUM_TRIES - retries);
625 if (mac_control == slave->mac_control)
629 printf("link up on port %d, speed %d, %s duplex\n",
630 slave->slave_num, phy->speed,
631 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
633 printf("link down on port %d\n", slave->slave_num);
636 __raw_writel(mac_control, &slave->sliver->mac_control);
637 slave->mac_control = mac_control;
640 static int cpsw_update_link(struct cpsw_priv *priv)
643 struct cpsw_slave *slave;
645 for_each_slave(slave, priv)
646 cpsw_slave_update_link(slave, priv, &link);
647 priv->mdio_link = readl(&mdio_regs->link);
651 static int cpsw_check_link(struct cpsw_priv *priv)
655 link = __raw_readl(&mdio_regs->link) & priv->phy_mask;
656 if (link && (link == priv->mdio_link))
659 return cpsw_update_link(priv);
662 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
664 if (priv->host_port == 0)
665 return slave_num + 1;
670 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
674 debug("%s\n", __func__);
675 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
677 /* setup priority mapping */
678 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
679 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
681 /* setup max packet size, and mac address */
682 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
683 cpsw_set_slave_mac(slave, priv);
685 slave->mac_control = 0; /* no link yet */
687 /* enable forwarding */
688 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
689 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
691 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
693 priv->phy_mask |= 1 << slave->data->phy_id;
696 static void cpdma_desc_get(struct cpsw_desc *desc)
698 invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
701 static void cpdma_desc_put(struct cpsw_desc *desc)
703 flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
706 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
708 struct cpsw_desc *desc = priv->desc_free;
711 cpdma_desc_get(desc);
712 priv->desc_free = desc->next;
717 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
720 desc_write(desc, hw_next, priv->desc_free->dma_desc);
721 cpdma_desc_put(desc);
722 desc->next = priv->desc_free;
723 priv->desc_free = desc;
727 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
728 void *buffer, int len)
730 struct cpsw_desc *desc, *prev;
734 printf("ERROR: %s() NULL buffer\n", __func__);
738 flush_dcache_range((u32)buffer, (u32)buffer + len);
740 desc = cpdma_desc_alloc(priv);
744 debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
745 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
749 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
752 desc_write(desc, hw_next, 0);
753 desc_write(desc, hw_buffer, buffer);
754 desc_write(desc, hw_len, len);
755 desc_write(desc, hw_mode, mode | len);
757 desc->sw_buffer = buffer;
759 cpdma_desc_put(desc);
761 /* simple case - first packet enqueued */
764 chan_write(chan, hdp, desc->dma_desc);
768 /* not the first packet - enqueue at the tail */
772 cpdma_desc_get(prev);
773 desc_write(prev, hw_next, desc->dma_desc);
774 cpdma_desc_put(prev);
778 /* next check if EOQ has been triggered already */
779 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
780 chan_write(chan, hdp, desc->dma_desc);
784 chan_write(chan, rxfree, 1);
785 debug("%s@%d\n", __func__, __LINE__);
789 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
790 void **buffer, int *len)
792 struct cpsw_desc *desc = chan->head;
798 cpdma_desc_get(desc);
800 status = desc_read(desc, hw_mode);
801 if (status & CPDMA_DESC_OWNER)
805 *len = status & 0x7ff;
808 *buffer = desc->sw_buffer;
809 debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
811 chan->head = desc->next;
812 chan_write(chan, cp, desc->dma_desc);
814 cpdma_desc_free(priv, desc);
818 static int cpsw_init(struct eth_device *dev, bd_t *bis)
820 struct cpsw_priv *priv = dev->priv;
821 struct cpsw_slave *slave;
824 debug("%s\n", __func__);
825 /* soft reset the controller and initialize priv */
826 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
828 /* initialize and reset the address lookup engine */
829 cpsw_ale_enable(priv, 1);
830 cpsw_ale_clear(priv, 1);
831 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
833 /* setup host port priority mapping */
834 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
835 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
837 /* disable priority elevation and enable statistics on all ports */
838 __raw_writel(0, &priv->regs->ptype);
840 /* enable statistics collection only on the host port */
841 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
843 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
845 cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
847 cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
849 for_each_slave(slave, priv)
850 cpsw_slave_init(slave, priv);
852 cpsw_update_link(priv);
854 /* init descriptor pool */
855 for (i = 0; i < NUM_DESCS; i++) {
856 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
857 &priv->descs[i + 1] : NULL;
859 priv->descs[i].next = next_desc;
860 desc_write(&priv->descs[i], hw_next,
861 next_desc ? next_desc->dma_desc : 0);
862 cpdma_desc_put(&priv->descs[i]);
864 priv->desc_free = &priv->descs[0];
866 /* initialize channels */
867 if (priv->data->version == CPSW_CTRL_VERSION_2) {
868 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
869 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
870 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
871 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
873 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
874 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
875 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
877 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
878 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
879 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
880 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
882 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
883 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
884 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
887 /* clear dma state */
888 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
890 if (priv->data->version == CPSW_CTRL_VERSION_2) {
891 for (i = 0; i < priv->data->channels; i++) {
892 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
893 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
894 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
895 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
896 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
899 for (i = 0; i < priv->data->channels; i++) {
900 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
901 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
902 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
903 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
904 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
909 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
910 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
912 /* submit rx descs */
913 for (i = 0; i < PKTBUFSRX; i++) {
914 ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
917 printf("error %d submitting rx desc\n", ret);
925 static void cpsw_halt(struct eth_device *dev)
927 struct cpsw_priv *priv = dev->priv;
928 struct cpsw_slave *slave;
930 int timeout = 1000000;
932 __raw_writel(DMACONTROL_CMD_IDLE, priv->dma_regs + CPDMA_DMACONTROL);
933 while (!(__raw_readl(priv->dma_regs + CPDMA_DMASTATUS) &
934 DMASTATUS_IDLE) && (--timeout >= 0))
940 for_each_slave(slave, priv) {
941 if (!(__raw_readl(&slave->sliver->mac_status) &
947 if (idle || --timeout < 0)
952 printf("CPSW: Aborting DMA transfers; packets may be lost\n");
954 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
955 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
957 /* soft reset the controller and initialize priv */
958 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
960 /* clear dma state */
961 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
963 debug("%s\n", __func__);
964 priv->data->control(0);
967 static int cpsw_send(struct eth_device *dev, void *packet, int length)
969 struct cpsw_priv *priv = dev->priv;
973 if (!priv->data->mac_control && !cpsw_check_link(priv)) {
974 printf("%s: Cannot send packet; link is down\n", __func__);
978 /* first reap completed packets */
979 while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
982 return cpdma_submit(priv, &priv->tx_chan, packet, length);
985 static int cpsw_recv(struct eth_device *dev)
987 struct cpsw_priv *priv = dev->priv;
991 while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
993 NetReceive(buffer, len);
994 cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
996 printf("NULL buffer returned from cpdma_process\n");
1004 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
1005 struct cpsw_priv *priv)
1007 void *regs = priv->regs;
1008 struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
1010 debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
1012 slave->slave_num = slave_num;
1014 slave->regs = regs + data->slave_reg_ofs;
1015 slave->sliver = regs + data->sliver_reg_ofs;
1018 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
1020 struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
1021 struct phy_device *phydev;
1022 u32 supported = (SUPPORTED_10baseT_Half |
1023 SUPPORTED_10baseT_Full |
1024 SUPPORTED_100baseT_Half |
1025 SUPPORTED_100baseT_Full |
1026 SUPPORTED_1000baseT_Full);
1028 if (slave->data->phy_id < 0) {
1031 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
1032 debug("Trying to connect to PHY @ addr %02x\n",
1034 phydev = phy_connect(priv->bus, phy_addr,
1035 dev, slave->data->phy_if);
1040 phydev = phy_connect(priv->bus,
1041 slave->data->phy_id,
1043 slave->data->phy_if);
1046 printf("Failed to connect to PHY\n");
1050 phydev->supported &= supported;
1051 phydev->advertising = phydev->supported;
1053 priv->phydev = phydev;
1059 int cpsw_register(struct cpsw_platform_data *data)
1062 struct cpsw_priv *priv;
1063 struct cpsw_slave *slave;
1064 void *regs = (void *)data->cpsw_base;
1065 struct eth_device *dev;
1069 debug("%s@%d\n", __func__, __LINE__);
1071 dev = calloc(sizeof(*dev), 1);
1075 priv = calloc(sizeof(*priv), 1);
1084 priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
1085 if (!priv->slaves) {
1091 for (i = 0; i < NUM_DESCS; i++) {
1092 priv->descs[i].dma_desc = memalign(CONFIG_SYS_CACHELINE_SIZE,
1093 sizeof(struct cpsw_desc) * NUM_DESCS);
1094 if (!priv->descs[i].dma_desc) {
1096 free(priv->descs[i].dma_desc);
1103 debug("DMA desc[%d] allocated @ %p desc_size %u\n",
1104 i, priv->descs[i].dma_desc,
1105 sizeof(*priv->descs[i].dma_desc));
1108 priv->host_port = data->host_port_num;
1110 priv->host_port_regs = regs + data->host_port_reg_ofs;
1111 priv->dma_regs = regs + data->cpdma_reg_ofs;
1112 priv->ale_regs = regs + data->ale_reg_ofs;
1114 for_each_slave(slave, priv) {
1115 cpsw_slave_setup(slave, idx, priv);
1119 strcpy(dev->name, "cpsw");
1121 dev->init = cpsw_init;
1122 dev->halt = cpsw_halt;
1123 dev->send = cpsw_send;
1124 dev->recv = cpsw_recv;
1129 cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1130 priv->bus = miiphy_get_dev_by_name(dev->name);
1131 for_each_slave(slave, priv) {
1132 ret = cpsw_phy_init(dev, slave);