2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
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18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
45 #include "t4vf_common.h"
46 #include "t4vf_defs.h"
48 #include "../cxgb4/t4_regs.h"
49 #include "../cxgb4/t4fw_api.h"
50 #include "../cxgb4/t4_msg.h"
53 * Decoded Adapter Parameters.
55 static u32 FL_PG_ORDER; /* large page allocation size */
56 static u32 STAT_LEN; /* length of status page at ring end */
57 static u32 PKTSHIFT; /* padding between CPL and packet data */
58 static u32 FL_ALIGN; /* response queue message alignment */
65 * Egress Queue sizes, producer and consumer indices are all in units
66 * of Egress Context Units bytes. Note that as far as the hardware is
67 * concerned, the free list is an Egress Queue (the host produces free
68 * buffers which the hardware consumes) and free list entries are
69 * 64-bit PCI DMA addresses.
71 EQ_UNIT = SGE_EQ_IDXSIZE,
72 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
73 TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
76 * Max number of TX descriptors we clean up at a time. Should be
77 * modest as freeing skbs isn't cheap and it happens while holding
78 * locks. We just need to free packets faster than they arrive, we
79 * eventually catch up and keep the amortized cost reasonable.
84 * Max number of Rx buffers we replenish at a time. Again keep this
85 * modest, allocating buffers isn't cheap either.
90 * Period of the Rx queue check timer. This timer is infrequent as it
91 * has something to do only when the system experiences severe memory
94 RX_QCHECK_PERIOD = (HZ / 2),
97 * Period of the TX queue check timer and the maximum number of TX
98 * descriptors to be reclaimed by the TX timer.
100 TX_QCHECK_PERIOD = (HZ / 2),
101 MAX_TIMER_TX_RECLAIM = 100,
104 * An FL with <= FL_STARVE_THRES buffers is starving and a periodic
105 * timer will attempt to refill it.
110 * Suspend an Ethernet TX queue with fewer available descriptors than
111 * this. We always want to have room for a maximum sized packet:
112 * inline immediate data + MAX_SKB_FRAGS. This is the same as
113 * calc_tx_flits() for a TSO packet with nr_frags == MAX_SKB_FRAGS
114 * (see that function and its helpers for a description of the
117 ETHTXQ_MAX_FRAGS = MAX_SKB_FRAGS + 1,
118 ETHTXQ_MAX_SGL_LEN = ((3 * (ETHTXQ_MAX_FRAGS-1))/2 +
119 ((ETHTXQ_MAX_FRAGS-1) & 1) +
121 ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) +
122 sizeof(struct cpl_tx_pkt_lso_core) +
123 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64),
124 ETHTXQ_MAX_FLITS = ETHTXQ_MAX_SGL_LEN + ETHTXQ_MAX_HDR,
126 ETHTXQ_STOP_THRES = 1 + DIV_ROUND_UP(ETHTXQ_MAX_FLITS, TXD_PER_EQ_UNIT),
129 * Max TX descriptor space we allow for an Ethernet packet to be
130 * inlined into a WR. This is limited by the maximum value which
131 * we can specify for immediate data in the firmware Ethernet TX
134 MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_MASK,
137 * Max size of a WR sent through a control TX queue.
139 MAX_CTRL_WR_LEN = 256,
142 * Maximum amount of data which we'll ever need to inline into a
143 * TX ring: max(MAX_IMM_TX_PKT_LEN, MAX_CTRL_WR_LEN).
145 MAX_IMM_TX_LEN = (MAX_IMM_TX_PKT_LEN > MAX_CTRL_WR_LEN
150 * For incoming packets less than RX_COPY_THRES, we copy the data into
151 * an skb rather than referencing the data. We allocate enough
152 * in-line room in skb's to accommodate pulling in RX_PULL_LEN bytes
153 * of the data (header).
160 * Can't define this in the above enum because PKTSHIFT isn't a constant in
163 #define RX_PKT_PULL_LEN (RX_PULL_LEN + PKTSHIFT)
166 * Software state per TX descriptor.
169 struct sk_buff *skb; /* socket buffer of TX data source */
170 struct ulptx_sgl *sgl; /* scatter/gather list in TX Queue */
174 * Software state per RX Free List descriptor. We keep track of the allocated
175 * FL page, its size, and its PCI DMA address (if the page is mapped). The FL
176 * page size and its PCI DMA mapped state are stored in the low bits of the
177 * PCI DMA address as per below.
180 struct page *page; /* Free List page buffer */
181 dma_addr_t dma_addr; /* PCI DMA address (if mapped) */
182 /* and flags (see below) */
186 * The low bits of rx_sw_desc.dma_addr have special meaning. Note that the
187 * SGE also uses the low 4 bits to determine the size of the buffer. It uses
188 * those bits to index into the SGE_FL_BUFFER_SIZE[index] register array.
189 * Since we only use SGE_FL_BUFFER_SIZE0 and SGE_FL_BUFFER_SIZE1, these low 4
190 * bits can only contain a 0 or a 1 to indicate which size buffer we're giving
191 * to the SGE. Thus, our software state of "is the buffer mapped for DMA" is
192 * maintained in an inverse sense so the hardware never sees that bit high.
195 RX_LARGE_BUF = 1 << 0, /* buffer is SGE_FL_BUFFER_SIZE[1] */
196 RX_UNMAPPED_BUF = 1 << 1, /* buffer is not mapped */
200 * get_buf_addr - return DMA buffer address of software descriptor
201 * @sdesc: pointer to the software buffer descriptor
203 * Return the DMA buffer address of a software descriptor (stripping out
204 * our low-order flag bits).
206 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *sdesc)
208 return sdesc->dma_addr & ~(dma_addr_t)(RX_LARGE_BUF | RX_UNMAPPED_BUF);
212 * is_buf_mapped - is buffer mapped for DMA?
213 * @sdesc: pointer to the software buffer descriptor
215 * Determine whether the buffer associated with a software descriptor in
216 * mapped for DMA or not.
218 static inline bool is_buf_mapped(const struct rx_sw_desc *sdesc)
220 return !(sdesc->dma_addr & RX_UNMAPPED_BUF);
224 * need_skb_unmap - does the platform need unmapping of sk_buffs?
226 * Returns true if the platfrom needs sk_buff unmapping. The compiler
227 * optimizes away unecessary code if this returns true.
229 static inline int need_skb_unmap(void)
231 #ifdef CONFIG_NEED_DMA_MAP_STATE
239 * txq_avail - return the number of available slots in a TX queue
242 * Returns the number of available descriptors in a TX queue.
244 static inline unsigned int txq_avail(const struct sge_txq *tq)
246 return tq->size - 1 - tq->in_use;
250 * fl_cap - return the capacity of a Free List
253 * Returns the capacity of a Free List. The capacity is less than the
254 * size because an Egress Queue Index Unit worth of descriptors needs to
255 * be left unpopulated, otherwise the Producer and Consumer indices PIDX
256 * and CIDX will match and the hardware will think the FL is empty.
258 static inline unsigned int fl_cap(const struct sge_fl *fl)
260 return fl->size - FL_PER_EQ_UNIT;
264 * fl_starving - return whether a Free List is starving.
267 * Tests specified Free List to see whether the number of buffers
268 * available to the hardware has falled below our "starvation"
271 static inline bool fl_starving(const struct sge_fl *fl)
273 return fl->avail - fl->pend_cred <= FL_STARVE_THRES;
277 * map_skb - map an skb for DMA to the device
278 * @dev: the egress net device
279 * @skb: the packet to map
280 * @addr: a pointer to the base of the DMA mapping array
282 * Map an skb for DMA to the device and return an array of DMA addresses.
284 static int map_skb(struct device *dev, const struct sk_buff *skb,
287 const skb_frag_t *fp, *end;
288 const struct skb_shared_info *si;
290 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
291 if (dma_mapping_error(dev, *addr))
294 si = skb_shinfo(skb);
295 end = &si->frags[si->nr_frags];
296 for (fp = si->frags; fp < end; fp++) {
297 *++addr = dma_map_page(dev, fp->page, fp->page_offset, fp->size,
299 if (dma_mapping_error(dev, *addr))
305 while (fp-- > si->frags)
306 dma_unmap_page(dev, *--addr, fp->size, DMA_TO_DEVICE);
307 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
313 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
314 const struct ulptx_sgl *sgl, const struct sge_txq *tq)
316 const struct ulptx_sge_pair *p;
317 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
319 if (likely(skb_headlen(skb)))
320 dma_unmap_single(dev, be64_to_cpu(sgl->addr0),
321 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
323 dma_unmap_page(dev, be64_to_cpu(sgl->addr0),
324 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
329 * the complexity below is because of the possibility of a wrap-around
330 * in the middle of an SGL
332 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
333 if (likely((u8 *)(p + 1) <= (u8 *)tq->stat)) {
335 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
336 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
337 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
338 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
340 } else if ((u8 *)p == (u8 *)tq->stat) {
341 p = (const struct ulptx_sge_pair *)tq->desc;
343 } else if ((u8 *)p + 8 == (u8 *)tq->stat) {
344 const __be64 *addr = (const __be64 *)tq->desc;
346 dma_unmap_page(dev, be64_to_cpu(addr[0]),
347 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
348 dma_unmap_page(dev, be64_to_cpu(addr[1]),
349 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
350 p = (const struct ulptx_sge_pair *)&addr[2];
352 const __be64 *addr = (const __be64 *)tq->desc;
354 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
355 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
356 dma_unmap_page(dev, be64_to_cpu(addr[0]),
357 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
358 p = (const struct ulptx_sge_pair *)&addr[1];
364 if ((u8 *)p == (u8 *)tq->stat)
365 p = (const struct ulptx_sge_pair *)tq->desc;
366 addr = ((u8 *)p + 16 <= (u8 *)tq->stat
368 : *(const __be64 *)tq->desc);
369 dma_unmap_page(dev, be64_to_cpu(addr), be32_to_cpu(p->len[0]),
375 * free_tx_desc - reclaims TX descriptors and their buffers
376 * @adapter: the adapter
377 * @tq: the TX queue to reclaim descriptors from
378 * @n: the number of descriptors to reclaim
379 * @unmap: whether the buffers should be unmapped for DMA
381 * Reclaims TX descriptors from an SGE TX queue and frees the associated
382 * TX buffers. Called with the TX queue lock held.
384 static void free_tx_desc(struct adapter *adapter, struct sge_txq *tq,
385 unsigned int n, bool unmap)
387 struct tx_sw_desc *sdesc;
388 unsigned int cidx = tq->cidx;
389 struct device *dev = adapter->pdev_dev;
391 const int need_unmap = need_skb_unmap() && unmap;
393 sdesc = &tq->sdesc[cidx];
396 * If we kept a reference to the original TX skb, we need to
397 * unmap it from PCI DMA space (if required) and free it.
401 unmap_sgl(dev, sdesc->skb, sdesc->sgl, tq);
402 kfree_skb(sdesc->skb);
407 if (++cidx == tq->size) {
416 * Return the number of reclaimable descriptors in a TX queue.
418 static inline int reclaimable(const struct sge_txq *tq)
420 int hw_cidx = be16_to_cpu(tq->stat->cidx);
421 int reclaimable = hw_cidx - tq->cidx;
423 reclaimable += tq->size;
428 * reclaim_completed_tx - reclaims completed TX descriptors
429 * @adapter: the adapter
430 * @tq: the TX queue to reclaim completed descriptors from
431 * @unmap: whether the buffers should be unmapped for DMA
433 * Reclaims TX descriptors that the SGE has indicated it has processed,
434 * and frees the associated buffers if possible. Called with the TX
437 static inline void reclaim_completed_tx(struct adapter *adapter,
441 int avail = reclaimable(tq);
445 * Limit the amount of clean up work we do at a time to keep
446 * the TX lock hold time O(1).
448 if (avail > MAX_TX_RECLAIM)
449 avail = MAX_TX_RECLAIM;
451 free_tx_desc(adapter, tq, avail, unmap);
457 * get_buf_size - return the size of an RX Free List buffer.
458 * @sdesc: pointer to the software buffer descriptor
460 static inline int get_buf_size(const struct rx_sw_desc *sdesc)
462 return FL_PG_ORDER > 0 && (sdesc->dma_addr & RX_LARGE_BUF)
463 ? (PAGE_SIZE << FL_PG_ORDER)
468 * free_rx_bufs - free RX buffers on an SGE Free List
469 * @adapter: the adapter
470 * @fl: the SGE Free List to free buffers from
471 * @n: how many buffers to free
473 * Release the next @n buffers on an SGE Free List RX queue. The
474 * buffers must be made inaccessible to hardware before calling this
477 static void free_rx_bufs(struct adapter *adapter, struct sge_fl *fl, int n)
480 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
482 if (is_buf_mapped(sdesc))
483 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
484 get_buf_size(sdesc), PCI_DMA_FROMDEVICE);
485 put_page(sdesc->page);
487 if (++fl->cidx == fl->size)
494 * unmap_rx_buf - unmap the current RX buffer on an SGE Free List
495 * @adapter: the adapter
496 * @fl: the SGE Free List
498 * Unmap the current buffer on an SGE Free List RX queue. The
499 * buffer must be made inaccessible to HW before calling this function.
501 * This is similar to @free_rx_bufs above but does not free the buffer.
502 * Do note that the FL still loses any further access to the buffer.
503 * This is used predominantly to "transfer ownership" of an FL buffer
504 * to another entity (typically an skb's fragment list).
506 static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
508 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
510 if (is_buf_mapped(sdesc))
511 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
512 get_buf_size(sdesc), PCI_DMA_FROMDEVICE);
514 if (++fl->cidx == fl->size)
520 * ring_fl_db - righ doorbell on free list
521 * @adapter: the adapter
522 * @fl: the Free List whose doorbell should be rung ...
524 * Tell the Scatter Gather Engine that there are new free list entries
527 static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
530 * The SGE keeps track of its Producer and Consumer Indices in terms
531 * of Egress Queue Units so we can only tell it about integral numbers
532 * of multiples of Free List Entries per Egress Queue Units ...
534 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
536 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
539 PIDX(fl->pend_cred / FL_PER_EQ_UNIT));
540 fl->pend_cred %= FL_PER_EQ_UNIT;
545 * set_rx_sw_desc - initialize software RX buffer descriptor
546 * @sdesc: pointer to the softwore RX buffer descriptor
547 * @page: pointer to the page data structure backing the RX buffer
548 * @dma_addr: PCI DMA address (possibly with low-bit flags)
550 static inline void set_rx_sw_desc(struct rx_sw_desc *sdesc, struct page *page,
554 sdesc->dma_addr = dma_addr;
558 * Support for poisoning RX buffers ...
560 #define POISON_BUF_VAL -1
562 static inline void poison_buf(struct page *page, size_t sz)
564 #if POISON_BUF_VAL >= 0
565 memset(page_address(page), POISON_BUF_VAL, sz);
570 * refill_fl - refill an SGE RX buffer ring
571 * @adapter: the adapter
572 * @fl: the Free List ring to refill
573 * @n: the number of new buffers to allocate
574 * @gfp: the gfp flags for the allocations
576 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
577 * allocated with the supplied gfp flags. The caller must assure that
578 * @n does not exceed the queue's capacity -- i.e. (cidx == pidx) _IN
579 * EGRESS QUEUE UNITS_ indicates an empty Free List! Returns the number
580 * of buffers allocated. If afterwards the queue is found critically low,
581 * mark it as starving in the bitmap of starving FLs.
583 static unsigned int refill_fl(struct adapter *adapter, struct sge_fl *fl,
588 unsigned int cred = fl->avail;
589 __be64 *d = &fl->desc[fl->pidx];
590 struct rx_sw_desc *sdesc = &fl->sdesc[fl->pidx];
593 * Sanity: ensure that the result of adding n Free List buffers
594 * won't result in wrapping the SGE's Producer Index around to
595 * it's Consumer Index thereby indicating an empty Free List ...
597 BUG_ON(fl->avail + n > fl->size - FL_PER_EQ_UNIT);
600 * If we support large pages, prefer large buffers and fail over to
601 * small pages if we can't allocate large pages to satisfy the refill.
602 * If we don't support large pages, drop directly into the small page
605 if (FL_PG_ORDER == 0)
606 goto alloc_small_pages;
609 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
611 if (unlikely(!page)) {
613 * We've failed inour attempt to allocate a "large
614 * page". Fail over to the "small page" allocation
617 fl->large_alloc_failed++;
620 poison_buf(page, PAGE_SIZE << FL_PG_ORDER);
622 dma_addr = dma_map_page(adapter->pdev_dev, page, 0,
623 PAGE_SIZE << FL_PG_ORDER,
625 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
627 * We've run out of DMA mapping space. Free up the
628 * buffer and return with what we've managed to put
629 * into the free list. We don't want to fail over to
630 * the small page allocation below in this case
631 * because DMA mapping resources are typically
632 * critical resources once they become scarse.
634 __free_pages(page, FL_PG_ORDER);
637 dma_addr |= RX_LARGE_BUF;
638 *d++ = cpu_to_be64(dma_addr);
640 set_rx_sw_desc(sdesc, page, dma_addr);
644 if (++fl->pidx == fl->size) {
654 page = __netdev_alloc_page(adapter->port[0],
656 if (unlikely(!page)) {
660 poison_buf(page, PAGE_SIZE);
662 dma_addr = dma_map_page(adapter->pdev_dev, page, 0, PAGE_SIZE,
664 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
665 netdev_free_page(adapter->port[0], page);
668 *d++ = cpu_to_be64(dma_addr);
670 set_rx_sw_desc(sdesc, page, dma_addr);
674 if (++fl->pidx == fl->size) {
683 * Update our accounting state to incorporate the new Free List
684 * buffers, tell the hardware about them and return the number of
685 * bufers which we were able to allocate.
687 cred = fl->avail - cred;
688 fl->pend_cred += cred;
689 ring_fl_db(adapter, fl);
691 if (unlikely(fl_starving(fl))) {
693 set_bit(fl->cntxt_id, adapter->sge.starving_fl);
700 * Refill a Free List to its capacity or the Maximum Refill Increment,
701 * whichever is smaller ...
703 static inline void __refill_fl(struct adapter *adapter, struct sge_fl *fl)
705 refill_fl(adapter, fl,
706 min((unsigned int)MAX_RX_REFILL, fl_cap(fl) - fl->avail),
711 * alloc_ring - allocate resources for an SGE descriptor ring
712 * @dev: the PCI device's core device
713 * @nelem: the number of descriptors
714 * @hwsize: the size of each hardware descriptor
715 * @swsize: the size of each software descriptor
716 * @busaddrp: the physical PCI bus address of the allocated ring
717 * @swringp: return address pointer for software ring
718 * @stat_size: extra space in hardware ring for status information
720 * Allocates resources for an SGE descriptor ring, such as TX queues,
721 * free buffer lists, response queues, etc. Each SGE ring requires
722 * space for its hardware descriptors plus, optionally, space for software
723 * state associated with each hardware entry (the metadata). The function
724 * returns three values: the virtual address for the hardware ring (the
725 * return value of the function), the PCI bus address of the hardware
726 * ring (in *busaddrp), and the address of the software ring (in swringp).
727 * Both the hardware and software rings are returned zeroed out.
729 static void *alloc_ring(struct device *dev, size_t nelem, size_t hwsize,
730 size_t swsize, dma_addr_t *busaddrp, void *swringp,
734 * Allocate the hardware ring and PCI DMA bus address space for said.
736 size_t hwlen = nelem * hwsize + stat_size;
737 void *hwring = dma_alloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL);
743 * If the caller wants a software ring, allocate it and return a
744 * pointer to it in *swringp.
746 BUG_ON((swsize != 0) != (swringp != NULL));
748 void *swring = kcalloc(nelem, swsize, GFP_KERNEL);
751 dma_free_coherent(dev, hwlen, hwring, *busaddrp);
754 *(void **)swringp = swring;
758 * Zero out the hardware ring and return its address as our function
761 memset(hwring, 0, hwlen);
766 * sgl_len - calculates the size of an SGL of the given capacity
767 * @n: the number of SGL entries
769 * Calculates the number of flits (8-byte units) needed for a Direct
770 * Scatter/Gather List that can hold the given number of entries.
772 static inline unsigned int sgl_len(unsigned int n)
775 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
776 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
777 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
778 * repeated sequences of { Length[i], Length[i+1], Address[i],
779 * Address[i+1] } (this ensures that all addresses are on 64-bit
780 * boundaries). If N is even, then Length[N+1] should be set to 0 and
781 * Address[N+1] is omitted.
783 * The following calculation incorporates all of the above. It's
784 * somewhat hard to follow but, briefly: the "+2" accounts for the
785 * first two flits which include the DSGL header, Length0 and
786 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
787 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
788 * finally the "+((n-1)&1)" adds the one remaining flit needed if
792 return (3 * n) / 2 + (n & 1) + 2;
796 * flits_to_desc - returns the num of TX descriptors for the given flits
797 * @flits: the number of flits
799 * Returns the number of TX descriptors needed for the supplied number
802 static inline unsigned int flits_to_desc(unsigned int flits)
804 BUG_ON(flits > SGE_MAX_WR_LEN / sizeof(__be64));
805 return DIV_ROUND_UP(flits, TXD_PER_EQ_UNIT);
809 * is_eth_imm - can an Ethernet packet be sent as immediate data?
812 * Returns whether an Ethernet packet is small enough to fit completely as
815 static inline int is_eth_imm(const struct sk_buff *skb)
818 * The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request
819 * which does not accommodate immediate data. We could dike out all
820 * of the support code for immediate data but that would tie our hands
821 * too much if we ever want to enhace the firmware. It would also
822 * create more differences between the PF and VF Drivers.
828 * calc_tx_flits - calculate the number of flits for a packet TX WR
831 * Returns the number of flits needed for a TX Work Request for the
832 * given Ethernet packet, including the needed WR and CPL headers.
834 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
839 * If the skb is small enough, we can pump it out as a work request
840 * with only immediate data. In that case we just have to have the
841 * TX Packet header plus the skb data in the Work Request.
844 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt),
848 * Otherwise, we're going to have to construct a Scatter gather list
849 * of the skb body and fragments. We also include the flits necessary
850 * for the TX Packet Work Request and CPL. We always have a firmware
851 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
852 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
853 * message or, if we're doing a Large Send Offload, an LSO CPL message
854 * with an embeded TX Packet Write CPL message.
856 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
857 if (skb_shinfo(skb)->gso_size)
858 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
859 sizeof(struct cpl_tx_pkt_lso_core) +
860 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
862 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
863 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
868 * write_sgl - populate a Scatter/Gather List for a packet
870 * @tq: the TX queue we are writing into
871 * @sgl: starting location for writing the SGL
872 * @end: points right after the end of the SGL
873 * @start: start offset into skb main-body data to include in the SGL
874 * @addr: the list of DMA bus addresses for the SGL elements
876 * Generates a Scatter/Gather List for the buffers that make up a packet.
877 * The caller must provide adequate space for the SGL that will be written.
878 * The SGL includes all of the packet's page fragments and the data in its
879 * main body except for the first @start bytes. @pos must be 16-byte
880 * aligned and within a TX descriptor with available space. @end points
881 * write after the end of the SGL but does not account for any potential
882 * wrap around, i.e., @end > @tq->stat.
884 static void write_sgl(const struct sk_buff *skb, struct sge_txq *tq,
885 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
886 const dma_addr_t *addr)
889 struct ulptx_sge_pair *to;
890 const struct skb_shared_info *si = skb_shinfo(skb);
891 unsigned int nfrags = si->nr_frags;
892 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
894 len = skb_headlen(skb) - start;
896 sgl->len0 = htonl(len);
897 sgl->addr0 = cpu_to_be64(addr[0] + start);
900 sgl->len0 = htonl(si->frags[0].size);
901 sgl->addr0 = cpu_to_be64(addr[1]);
904 sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) |
906 if (likely(--nfrags == 0))
909 * Most of the complexity below deals with the possibility we hit the
910 * end of the queue in the middle of writing the SGL. For this case
911 * only we create the SGL in a temporary buffer and then copy it.
913 to = (u8 *)end > (u8 *)tq->stat ? buf : sgl->sge;
915 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
916 to->len[0] = cpu_to_be32(si->frags[i].size);
917 to->len[1] = cpu_to_be32(si->frags[++i].size);
918 to->addr[0] = cpu_to_be64(addr[i]);
919 to->addr[1] = cpu_to_be64(addr[++i]);
922 to->len[0] = cpu_to_be32(si->frags[i].size);
923 to->len[1] = cpu_to_be32(0);
924 to->addr[0] = cpu_to_be64(addr[i + 1]);
926 if (unlikely((u8 *)end > (u8 *)tq->stat)) {
927 unsigned int part0 = (u8 *)tq->stat - (u8 *)sgl->sge, part1;
930 memcpy(sgl->sge, buf, part0);
931 part1 = (u8 *)end - (u8 *)tq->stat;
932 memcpy(tq->desc, (u8 *)buf + part0, part1);
933 end = (void *)tq->desc + part1;
935 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
940 * check_ring_tx_db - check and potentially ring a TX queue's doorbell
941 * @adapter: the adapter
943 * @n: number of new descriptors to give to HW
945 * Ring the doorbel for a TX queue.
947 static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
951 * Warn if we write doorbells with the wrong priority and write
952 * descriptors before telling HW.
954 WARN_ON((QID(tq->cntxt_id) | PIDX(n)) & DBPRIO);
956 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
957 QID(tq->cntxt_id) | PIDX(n));
961 * inline_tx_skb - inline a packet's data into TX descriptors
963 * @tq: the TX queue where the packet will be inlined
964 * @pos: starting position in the TX queue to inline the packet
966 * Inline a packet's contents directly into TX descriptors, starting at
967 * the given position within the TX DMA ring.
968 * Most of the complexity of this operation is dealing with wrap arounds
969 * in the middle of the packet we want to inline.
971 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
975 int left = (void *)tq->stat - pos;
977 if (likely(skb->len <= left)) {
978 if (likely(!skb->data_len))
979 skb_copy_from_linear_data(skb, pos, skb->len);
981 skb_copy_bits(skb, 0, pos, skb->len);
984 skb_copy_bits(skb, 0, pos, left);
985 skb_copy_bits(skb, left, tq->desc, skb->len - left);
986 pos = (void *)tq->desc + (skb->len - left);
989 /* 0-pad to multiple of 16 */
990 p = PTR_ALIGN(pos, 8);
991 if ((uintptr_t)p & 8)
996 * Figure out what HW csum a packet wants and return the appropriate control
999 static u64 hwcsum(const struct sk_buff *skb)
1002 const struct iphdr *iph = ip_hdr(skb);
1004 if (iph->version == 4) {
1005 if (iph->protocol == IPPROTO_TCP)
1006 csum_type = TX_CSUM_TCPIP;
1007 else if (iph->protocol == IPPROTO_UDP)
1008 csum_type = TX_CSUM_UDPIP;
1012 * unknown protocol, disable HW csum
1013 * and hope a bad packet is detected
1015 return TXPKT_L4CSUM_DIS;
1019 * this doesn't work with extension headers
1021 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1023 if (ip6h->nexthdr == IPPROTO_TCP)
1024 csum_type = TX_CSUM_TCPIP6;
1025 else if (ip6h->nexthdr == IPPROTO_UDP)
1026 csum_type = TX_CSUM_UDPIP6;
1031 if (likely(csum_type >= TX_CSUM_TCPIP))
1032 return TXPKT_CSUM_TYPE(csum_type) |
1033 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
1034 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
1036 int start = skb_transport_offset(skb);
1038 return TXPKT_CSUM_TYPE(csum_type) |
1039 TXPKT_CSUM_START(start) |
1040 TXPKT_CSUM_LOC(start + skb->csum_offset);
1045 * Stop an Ethernet TX queue and record that state change.
1047 static void txq_stop(struct sge_eth_txq *txq)
1049 netif_tx_stop_queue(txq->txq);
1054 * Advance our software state for a TX queue by adding n in use descriptors.
1056 static inline void txq_advance(struct sge_txq *tq, unsigned int n)
1060 if (tq->pidx >= tq->size)
1061 tq->pidx -= tq->size;
1065 * t4vf_eth_xmit - add a packet to an Ethernet TX queue
1067 * @dev: the egress net device
1069 * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled.
1071 int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1076 unsigned int flits, ndesc;
1077 struct adapter *adapter;
1078 struct sge_eth_txq *txq;
1079 const struct port_info *pi;
1080 struct fw_eth_tx_pkt_vm_wr *wr;
1081 struct cpl_tx_pkt_core *cpl;
1082 const struct skb_shared_info *ssi;
1083 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1084 const size_t fw_hdr_copy_len = (sizeof(wr->ethmacdst) +
1085 sizeof(wr->ethmacsrc) +
1086 sizeof(wr->ethtype) +
1087 sizeof(wr->vlantci));
1090 * The chip minimum packet length is 10 octets but the firmware
1091 * command that we are using requires that we copy the Ethernet header
1092 * (including the VLAN tag) into the header so we reject anything
1093 * smaller than that ...
1095 if (unlikely(skb->len < fw_hdr_copy_len))
1099 * Figure out which TX Queue we're going to use.
1101 pi = netdev_priv(dev);
1102 adapter = pi->adapter;
1103 qidx = skb_get_queue_mapping(skb);
1104 BUG_ON(qidx >= pi->nqsets);
1105 txq = &adapter->sge.ethtxq[pi->first_qset + qidx];
1108 * Take this opportunity to reclaim any TX Descriptors whose DMA
1109 * transfers have completed.
1111 reclaim_completed_tx(adapter, &txq->q, true);
1114 * Calculate the number of flits and TX Descriptors we're going to
1115 * need along with how many TX Descriptors will be left over after
1116 * we inject our Work Request.
1118 flits = calc_tx_flits(skb);
1119 ndesc = flits_to_desc(flits);
1120 credits = txq_avail(&txq->q) - ndesc;
1122 if (unlikely(credits < 0)) {
1124 * Not enough room for this packet's Work Request. Stop the
1125 * TX Queue and return a "busy" condition. The queue will get
1126 * started later on when the firmware informs us that space
1130 dev_err(adapter->pdev_dev,
1131 "%s: TX ring %u full while queue awake!\n",
1133 return NETDEV_TX_BUSY;
1136 if (!is_eth_imm(skb) &&
1137 unlikely(map_skb(adapter->pdev_dev, skb, addr) < 0)) {
1139 * We need to map the skb into PCI DMA space (because it can't
1140 * be in-lined directly into the Work Request) and the mapping
1141 * operation failed. Record the error and drop the packet.
1147 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
1148 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1150 * After we're done injecting the Work Request for this
1151 * packet, we'll be below our "stop threshhold" so stop the TX
1152 * Queue now and schedule a request for an SGE Egress Queue
1153 * Update message. The queue will get started later on when
1154 * the firmware processes this Work Request and sends us an
1155 * Egress Queue Status Update message indicating that space
1159 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ;
1163 * Start filling in our Work Request. Note that we do _not_ handle
1164 * the WR Header wrapping around the TX Descriptor Ring. If our
1165 * maximum header size ever exceeds one TX Descriptor, we'll need to
1166 * do something else here.
1168 BUG_ON(DIV_ROUND_UP(ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
1169 wr = (void *)&txq->q.desc[txq->q.pidx];
1170 wr->equiq_to_len16 = cpu_to_be32(wr_mid);
1171 wr->r3[0] = cpu_to_be64(0);
1172 wr->r3[1] = cpu_to_be64(0);
1173 skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
1174 end = (u64 *)wr + flits;
1177 * If this is a Large Send Offload packet we'll put in an LSO CPL
1178 * message with an encapsulated TX Packet CPL message. Otherwise we
1179 * just use a TX Packet CPL message.
1181 ssi = skb_shinfo(skb);
1182 if (ssi->gso_size) {
1183 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1184 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1185 int l3hdr_len = skb_network_header_len(skb);
1186 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1189 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1190 FW_WR_IMMDLEN(sizeof(*lso) +
1193 * Fill in the LSO CPL message.
1196 cpu_to_be32(LSO_OPCODE(CPL_TX_PKT_LSO) |
1200 LSO_ETHHDR_LEN(eth_xtra_len/4) |
1201 LSO_IPHDR_LEN(l3hdr_len/4) |
1202 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
1203 lso->ipid_ofst = cpu_to_be16(0);
1204 lso->mss = cpu_to_be16(ssi->gso_size);
1205 lso->seqno_offset = cpu_to_be32(0);
1206 lso->len = cpu_to_be32(skb->len);
1209 * Set up TX Packet CPL pointer, control word and perform
1212 cpl = (void *)(lso + 1);
1213 cntrl = (TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1214 TXPKT_IPHDR_LEN(l3hdr_len) |
1215 TXPKT_ETHHDR_LEN(eth_xtra_len));
1217 txq->tx_cso += ssi->gso_segs;
1221 len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
1223 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1224 FW_WR_IMMDLEN(len));
1227 * Set up TX Packet CPL pointer, control word and perform
1230 cpl = (void *)(wr + 1);
1231 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1232 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
1235 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
1239 * If there's a VLAN tag present, add that to the list of things to
1240 * do in this Work Request.
1242 if (vlan_tx_tag_present(skb)) {
1244 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb));
1248 * Fill in the TX Packet CPL message header.
1250 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE(CPL_TX_PKT_XT) |
1251 TXPKT_INTF(pi->port_id) |
1253 cpl->pack = cpu_to_be16(0);
1254 cpl->len = cpu_to_be16(skb->len);
1255 cpl->ctrl1 = cpu_to_be64(cntrl);
1258 T4_TRACE5(adapter->tb[txq->q.cntxt_id & 7],
1259 "eth_xmit: ndesc %u, credits %u, pidx %u, len %u, frags %u",
1260 ndesc, credits, txq->q.pidx, skb->len, ssi->nr_frags);
1264 * Fill in the body of the TX Packet CPL message with either in-lined
1265 * data or a Scatter/Gather List.
1267 if (is_eth_imm(skb)) {
1269 * In-line the packet's data and free the skb since we don't
1270 * need it any longer.
1272 inline_tx_skb(skb, &txq->q, cpl + 1);
1276 * Write the skb's Scatter/Gather list into the TX Packet CPL
1277 * message and retain a pointer to the skb so we can free it
1278 * later when its DMA completes. (We store the skb pointer
1279 * in the Software Descriptor corresponding to the last TX
1280 * Descriptor used by the Work Request.)
1282 * The retained skb will be freed when the corresponding TX
1283 * Descriptors are reclaimed after their DMAs complete.
1284 * However, this could take quite a while since, in general,
1285 * the hardware is set up to be lazy about sending DMA
1286 * completion notifications to us and we mostly perform TX
1287 * reclaims in the transmit routine.
1289 * This is good for performamce but means that we rely on new
1290 * TX packets arriving to run the destructors of completed
1291 * packets, which open up space in their sockets' send queues.
1292 * Sometimes we do not get such new packets causing TX to
1293 * stall. A single UDP transmitter is a good example of this
1294 * situation. We have a clean up timer that periodically
1295 * reclaims completed packets but it doesn't run often enough
1296 * (nor do we want it to) to prevent lengthy stalls. A
1297 * solution to this problem is to run the destructor early,
1298 * after the packet is queued but before it's DMAd. A con is
1299 * that we lie to socket memory accounting, but the amount of
1300 * extra memory is reasonable (limited by the number of TX
1301 * descriptors), the packets do actually get freed quickly by
1302 * new packets almost always, and for protocols like TCP that
1303 * wait for acks to really free up the data the extra memory
1304 * is even less. On the positive side we run the destructors
1305 * on the sending CPU rather than on a potentially different
1306 * completing CPU, usually a good thing.
1308 * Run the destructor before telling the DMA engine about the
1309 * packet to make sure it doesn't complete and get freed
1312 struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1);
1313 struct sge_txq *tq = &txq->q;
1317 * If the Work Request header was an exact multiple of our TX
1318 * Descriptor length, then it's possible that the starting SGL
1319 * pointer lines up exactly with the end of our TX Descriptor
1320 * ring. If that's the case, wrap around to the beginning
1323 if (unlikely((void *)sgl == (void *)tq->stat)) {
1324 sgl = (void *)tq->desc;
1325 end = (void *)((void *)tq->desc +
1326 ((void *)end - (void *)tq->stat));
1329 write_sgl(skb, tq, sgl, end, 0, addr);
1332 last_desc = tq->pidx + ndesc - 1;
1333 if (last_desc >= tq->size)
1334 last_desc -= tq->size;
1335 tq->sdesc[last_desc].skb = skb;
1336 tq->sdesc[last_desc].sgl = sgl;
1340 * Advance our internal TX Queue state, tell the hardware about
1341 * the new TX descriptors and return success.
1343 txq_advance(&txq->q, ndesc);
1344 dev->trans_start = jiffies;
1345 ring_tx_db(adapter, &txq->q, ndesc);
1346 return NETDEV_TX_OK;
1350 * An error of some sort happened. Free the TX skb and tell the
1351 * OS that we've "dealt" with the packet ...
1354 return NETDEV_TX_OK;
1358 * t4vf_pktgl_free - free a packet gather list
1359 * @gl: the gather list
1361 * Releases the pages of a packet gather list. We do not own the last
1362 * page on the list and do not free it.
1364 void t4vf_pktgl_free(const struct pkt_gl *gl)
1368 frag = gl->nfrags - 1;
1370 put_page(gl->frags[frag].page);
1374 * copy_frags - copy fragments from gather list into skb_shared_info
1375 * @si: destination skb shared info structure
1376 * @gl: source internal packet gather list
1377 * @offset: packet start offset in first page
1379 * Copy an internal packet gather list into a Linux skb_shared_info
1382 static inline void copy_frags(struct skb_shared_info *si,
1383 const struct pkt_gl *gl,
1384 unsigned int offset)
1388 /* usually there's just one frag */
1389 si->frags[0].page = gl->frags[0].page;
1390 si->frags[0].page_offset = gl->frags[0].page_offset + offset;
1391 si->frags[0].size = gl->frags[0].size - offset;
1392 si->nr_frags = gl->nfrags;
1396 memcpy(&si->frags[1], &gl->frags[1], n * sizeof(skb_frag_t));
1398 /* get a reference to the last page, we don't own it */
1399 get_page(gl->frags[n].page);
1403 * do_gro - perform Generic Receive Offload ingress packet processing
1404 * @rxq: ingress RX Ethernet Queue
1405 * @gl: gather list for ingress packet
1406 * @pkt: CPL header for last packet fragment
1408 * Perform Generic Receive Offload (GRO) ingress packet processing.
1409 * We use the standard Linux GRO interfaces for this.
1411 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1412 const struct cpl_rx_pkt *pkt)
1415 struct sk_buff *skb;
1417 skb = napi_get_frags(&rxq->rspq.napi);
1418 if (unlikely(!skb)) {
1419 t4vf_pktgl_free(gl);
1420 rxq->stats.rx_drops++;
1424 copy_frags(skb_shinfo(skb), gl, PKTSHIFT);
1425 skb->len = gl->tot_len - PKTSHIFT;
1426 skb->data_len = skb->len;
1427 skb->truesize += skb->data_len;
1428 skb->ip_summed = CHECKSUM_UNNECESSARY;
1429 skb_record_rx_queue(skb, rxq->rspq.idx);
1431 if (unlikely(pkt->vlan_ex)) {
1432 struct port_info *pi = netdev_priv(rxq->rspq.netdev);
1433 struct vlan_group *grp = pi->vlan_grp;
1435 rxq->stats.vlan_ex++;
1437 ret = vlan_gro_frags(&rxq->rspq.napi, grp,
1438 be16_to_cpu(pkt->vlan));
1442 ret = napi_gro_frags(&rxq->rspq.napi);
1445 if (ret == GRO_HELD)
1446 rxq->stats.lro_pkts++;
1447 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1448 rxq->stats.lro_merged++;
1450 rxq->stats.rx_cso++;
1454 * t4vf_ethrx_handler - process an ingress ethernet packet
1455 * @rspq: the response queue that received the packet
1456 * @rsp: the response queue descriptor holding the RX_PKT message
1457 * @gl: the gather list of packet fragments
1459 * Process an ingress ethernet packet and deliver it to the stack.
1461 int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp,
1462 const struct pkt_gl *gl)
1464 struct sk_buff *skb;
1465 struct port_info *pi;
1466 struct skb_shared_info *ssi;
1467 const struct cpl_rx_pkt *pkt = (void *)&rsp[1];
1468 bool csum_ok = pkt->csum_calc && !pkt->err_vec;
1469 unsigned int len = be16_to_cpu(pkt->len);
1470 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1473 * If this is a good TCP packet and we have Generic Receive Offload
1474 * enabled, handle the packet in the GRO path.
1476 if ((pkt->l2info & cpu_to_be32(RXF_TCP)) &&
1477 (rspq->netdev->features & NETIF_F_GRO) && csum_ok &&
1479 do_gro(rxq, gl, pkt);
1484 * If the ingress packet is small enough, allocate an skb large enough
1485 * for all of the data and copy it inline. Otherwise, allocate an skb
1486 * with enough room to pull in the header and reference the rest of
1487 * the data via the skb fragment list.
1489 if (len <= RX_COPY_THRES) {
1490 /* small packets have only one fragment */
1491 skb = alloc_skb(gl->frags[0].size, GFP_ATOMIC);
1494 __skb_put(skb, gl->frags[0].size);
1495 skb_copy_to_linear_data(skb, gl->va, gl->frags[0].size);
1497 skb = alloc_skb(RX_PKT_PULL_LEN, GFP_ATOMIC);
1500 __skb_put(skb, RX_PKT_PULL_LEN);
1501 skb_copy_to_linear_data(skb, gl->va, RX_PKT_PULL_LEN);
1503 ssi = skb_shinfo(skb);
1504 ssi->frags[0].page = gl->frags[0].page;
1505 ssi->frags[0].page_offset = (gl->frags[0].page_offset +
1507 ssi->frags[0].size = gl->frags[0].size - RX_PKT_PULL_LEN;
1509 memcpy(&ssi->frags[1], &gl->frags[1],
1510 (gl->nfrags-1) * sizeof(skb_frag_t));
1511 ssi->nr_frags = gl->nfrags;
1512 skb->len = len + PKTSHIFT;
1513 skb->data_len = skb->len - RX_PKT_PULL_LEN;
1514 skb->truesize += skb->data_len;
1516 /* Get a reference for the last page, we don't own it */
1517 get_page(gl->frags[gl->nfrags - 1].page);
1520 __skb_pull(skb, PKTSHIFT);
1521 skb->protocol = eth_type_trans(skb, rspq->netdev);
1522 skb_record_rx_queue(skb, rspq->idx);
1523 skb->dev->last_rx = jiffies; /* XXX removed 2.6.29 */
1524 pi = netdev_priv(skb->dev);
1527 if (csum_ok && (pi->rx_offload & RX_CSO) && !pkt->err_vec &&
1528 (be32_to_cpu(pkt->l2info) & (RXF_UDP|RXF_TCP))) {
1530 skb->ip_summed = CHECKSUM_UNNECESSARY;
1532 __sum16 c = (__force __sum16)pkt->csum;
1533 skb->csum = csum_unfold(c);
1534 skb->ip_summed = CHECKSUM_COMPLETE;
1536 rxq->stats.rx_cso++;
1538 skb->ip_summed = CHECKSUM_NONE;
1540 if (unlikely(pkt->vlan_ex)) {
1541 struct vlan_group *grp = pi->vlan_grp;
1543 rxq->stats.vlan_ex++;
1545 vlan_hwaccel_receive_skb(skb, grp,
1546 be16_to_cpu(pkt->vlan));
1548 dev_kfree_skb_any(skb);
1550 netif_receive_skb(skb);
1555 t4vf_pktgl_free(gl);
1556 rxq->stats.rx_drops++;
1561 * is_new_response - check if a response is newly written
1562 * @rc: the response control descriptor
1563 * @rspq: the response queue
1565 * Returns true if a response descriptor contains a yet unprocessed
1568 static inline bool is_new_response(const struct rsp_ctrl *rc,
1569 const struct sge_rspq *rspq)
1571 return RSPD_GEN(rc->type_gen) == rspq->gen;
1575 * restore_rx_bufs - put back a packet's RX buffers
1576 * @gl: the packet gather list
1577 * @fl: the SGE Free List
1578 * @nfrags: how many fragments in @si
1580 * Called when we find out that the current packet, @si, can't be
1581 * processed right away for some reason. This is a very rare event and
1582 * there's no effort to make this suspension/resumption process
1583 * particularly efficient.
1585 * We implement the suspension by putting all of the RX buffers associated
1586 * with the current packet back on the original Free List. The buffers
1587 * have already been unmapped and are left unmapped, we mark them as
1588 * unmapped in order to prevent further unmapping attempts. (Effectively
1589 * this function undoes the series of @unmap_rx_buf calls which were done
1590 * to create the current packet's gather list.) This leaves us ready to
1591 * restart processing of the packet the next time we start processing the
1594 static void restore_rx_bufs(const struct pkt_gl *gl, struct sge_fl *fl,
1597 struct rx_sw_desc *sdesc;
1601 fl->cidx = fl->size - 1;
1604 sdesc = &fl->sdesc[fl->cidx];
1605 sdesc->page = gl->frags[frags].page;
1606 sdesc->dma_addr |= RX_UNMAPPED_BUF;
1612 * rspq_next - advance to the next entry in a response queue
1615 * Updates the state of a response queue to advance it to the next entry.
1617 static inline void rspq_next(struct sge_rspq *rspq)
1619 rspq->cur_desc = (void *)rspq->cur_desc + rspq->iqe_len;
1620 if (unlikely(++rspq->cidx == rspq->size)) {
1623 rspq->cur_desc = rspq->desc;
1628 * process_responses - process responses from an SGE response queue
1629 * @rspq: the ingress response queue to process
1630 * @budget: how many responses can be processed in this round
1632 * Process responses from a Scatter Gather Engine response queue up to
1633 * the supplied budget. Responses include received packets as well as
1634 * control messages from firmware or hardware.
1636 * Additionally choose the interrupt holdoff time for the next interrupt
1637 * on this queue. If the system is under memory shortage use a fairly
1638 * long delay to help recovery.
1640 int process_responses(struct sge_rspq *rspq, int budget)
1642 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1643 int budget_left = budget;
1645 while (likely(budget_left)) {
1647 const struct rsp_ctrl *rc;
1649 rc = (void *)rspq->cur_desc + (rspq->iqe_len - sizeof(*rc));
1650 if (!is_new_response(rc, rspq))
1654 * Figure out what kind of response we've received from the
1658 rsp_type = RSPD_TYPE(rc->type_gen);
1659 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1662 const struct rx_sw_desc *sdesc;
1664 u32 len = be32_to_cpu(rc->pldbuflen_qid);
1667 * If we get a "new buffer" message from the SGE we
1668 * need to move on to the next Free List buffer.
1670 if (len & RSPD_NEWBUF) {
1672 * We get one "new buffer" message when we
1673 * first start up a queue so we need to ignore
1674 * it when our offset into the buffer is 0.
1676 if (likely(rspq->offset > 0)) {
1677 free_rx_bufs(rspq->adapter, &rxq->fl,
1681 len = RSPD_LEN(len);
1685 * Gather packet fragments.
1687 for (frag = 0, fp = gl.frags; /**/; frag++, fp++) {
1688 BUG_ON(frag >= MAX_SKB_FRAGS);
1689 BUG_ON(rxq->fl.avail == 0);
1690 sdesc = &rxq->fl.sdesc[rxq->fl.cidx];
1691 bufsz = get_buf_size(sdesc);
1692 fp->page = sdesc->page;
1693 fp->page_offset = rspq->offset;
1694 fp->size = min(bufsz, len);
1698 unmap_rx_buf(rspq->adapter, &rxq->fl);
1703 * Last buffer remains mapped so explicitly make it
1704 * coherent for CPU access and start preloading first
1707 dma_sync_single_for_cpu(rspq->adapter->pdev_dev,
1708 get_buf_addr(sdesc),
1709 fp->size, DMA_FROM_DEVICE);
1710 gl.va = (page_address(gl.frags[0].page) +
1711 gl.frags[0].page_offset);
1715 * Hand the new ingress packet to the handler for
1716 * this Response Queue.
1718 ret = rspq->handler(rspq, rspq->cur_desc, &gl);
1719 if (likely(ret == 0))
1720 rspq->offset += ALIGN(fp->size, FL_ALIGN);
1722 restore_rx_bufs(&gl, &rxq->fl, frag);
1723 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
1724 ret = rspq->handler(rspq, rspq->cur_desc, NULL);
1726 WARN_ON(rsp_type > RSP_TYPE_CPL);
1730 if (unlikely(ret)) {
1732 * Couldn't process descriptor, back off for recovery.
1733 * We use the SGE's last timer which has the longest
1734 * interrupt coalescing value ...
1736 const int NOMEM_TIMER_IDX = SGE_NTIMERS-1;
1737 rspq->next_intr_params =
1738 QINTR_TIMER_IDX(NOMEM_TIMER_IDX);
1747 * If this is a Response Queue with an associated Free List and
1748 * at least two Egress Queue units available in the Free List
1749 * for new buffer pointers, refill the Free List.
1751 if (rspq->offset >= 0 &&
1752 rxq->fl.size - rxq->fl.avail >= 2*FL_PER_EQ_UNIT)
1753 __refill_fl(rspq->adapter, &rxq->fl);
1754 return budget - budget_left;
1758 * napi_rx_handler - the NAPI handler for RX processing
1759 * @napi: the napi instance
1760 * @budget: how many packets we can process in this round
1762 * Handler for new data events when using NAPI. This does not need any
1763 * locking or protection from interrupts as data interrupts are off at
1764 * this point and other adapter interrupts do not interfere (the latter
1765 * in not a concern at all with MSI-X as non-data interrupts then have
1766 * a separate handler).
1768 static int napi_rx_handler(struct napi_struct *napi, int budget)
1770 unsigned int intr_params;
1771 struct sge_rspq *rspq = container_of(napi, struct sge_rspq, napi);
1772 int work_done = process_responses(rspq, budget);
1774 if (likely(work_done < budget)) {
1775 napi_complete(napi);
1776 intr_params = rspq->next_intr_params;
1777 rspq->next_intr_params = rspq->intr_params;
1779 intr_params = QINTR_TIMER_IDX(SGE_TIMER_UPD_CIDX);
1781 if (unlikely(work_done == 0))
1782 rspq->unhandled_irqs++;
1784 t4_write_reg(rspq->adapter,
1785 T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1786 CIDXINC(work_done) |
1787 INGRESSQID((u32)rspq->cntxt_id) |
1788 SEINTARM(intr_params));
1793 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
1794 * (i.e., response queue serviced by NAPI polling).
1796 irqreturn_t t4vf_sge_intr_msix(int irq, void *cookie)
1798 struct sge_rspq *rspq = cookie;
1800 napi_schedule(&rspq->napi);
1805 * Process the indirect interrupt entries in the interrupt queue and kick off
1806 * NAPI for each queue that has generated an entry.
1808 static unsigned int process_intrq(struct adapter *adapter)
1810 struct sge *s = &adapter->sge;
1811 struct sge_rspq *intrq = &s->intrq;
1812 unsigned int work_done;
1814 spin_lock(&adapter->sge.intrq_lock);
1815 for (work_done = 0; ; work_done++) {
1816 const struct rsp_ctrl *rc;
1817 unsigned int qid, iq_idx;
1818 struct sge_rspq *rspq;
1821 * Grab the next response from the interrupt queue and bail
1822 * out if it's not a new response.
1824 rc = (void *)intrq->cur_desc + (intrq->iqe_len - sizeof(*rc));
1825 if (!is_new_response(rc, intrq))
1829 * If the response isn't a forwarded interrupt message issue a
1830 * error and go on to the next response message. This should
1834 if (unlikely(RSPD_TYPE(rc->type_gen) != RSP_TYPE_INTR)) {
1835 dev_err(adapter->pdev_dev,
1836 "Unexpected INTRQ response type %d\n",
1837 RSPD_TYPE(rc->type_gen));
1842 * Extract the Queue ID from the interrupt message and perform
1843 * sanity checking to make sure it really refers to one of our
1844 * Ingress Queues which is active and matches the queue's ID.
1845 * None of these error conditions should ever happen so we may
1846 * want to either make them fatal and/or conditionalized under
1849 qid = RSPD_QID(be32_to_cpu(rc->pldbuflen_qid));
1850 iq_idx = IQ_IDX(s, qid);
1851 if (unlikely(iq_idx >= MAX_INGQ)) {
1852 dev_err(adapter->pdev_dev,
1853 "Ingress QID %d out of range\n", qid);
1856 rspq = s->ingr_map[iq_idx];
1857 if (unlikely(rspq == NULL)) {
1858 dev_err(adapter->pdev_dev,
1859 "Ingress QID %d RSPQ=NULL\n", qid);
1862 if (unlikely(rspq->abs_id != qid)) {
1863 dev_err(adapter->pdev_dev,
1864 "Ingress QID %d refers to RSPQ %d\n",
1870 * Schedule NAPI processing on the indicated Response Queue
1871 * and move on to the next entry in the Forwarded Interrupt
1874 napi_schedule(&rspq->napi);
1878 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1879 CIDXINC(work_done) |
1880 INGRESSQID(intrq->cntxt_id) |
1881 SEINTARM(intrq->intr_params));
1883 spin_unlock(&adapter->sge.intrq_lock);
1889 * The MSI interrupt handler handles data events from SGE response queues as
1890 * well as error and other async events as they all use the same MSI vector.
1892 irqreturn_t t4vf_intr_msi(int irq, void *cookie)
1894 struct adapter *adapter = cookie;
1896 process_intrq(adapter);
1901 * t4vf_intr_handler - select the top-level interrupt handler
1902 * @adapter: the adapter
1904 * Selects the top-level interrupt handler based on the type of interrupts
1907 irq_handler_t t4vf_intr_handler(struct adapter *adapter)
1909 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
1910 if (adapter->flags & USING_MSIX)
1911 return t4vf_sge_intr_msix;
1913 return t4vf_intr_msi;
1917 * sge_rx_timer_cb - perform periodic maintenance of SGE RX queues
1918 * @data: the adapter
1920 * Runs periodically from a timer to perform maintenance of SGE RX queues.
1922 * a) Replenishes RX queues that have run out due to memory shortage.
1923 * Normally new RX buffers are added when existing ones are consumed but
1924 * when out of memory a queue can become empty. We schedule NAPI to do
1925 * the actual refill.
1927 static void sge_rx_timer_cb(unsigned long data)
1929 struct adapter *adapter = (struct adapter *)data;
1930 struct sge *s = &adapter->sge;
1934 * Scan the "Starving Free Lists" flag array looking for any Free
1935 * Lists in need of more free buffers. If we find one and it's not
1936 * being actively polled, then bump its "starving" counter and attempt
1937 * to refill it. If we're successful in adding enough buffers to push
1938 * the Free List over the starving threshold, then we can clear its
1939 * "starving" status.
1941 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) {
1944 for (m = s->starving_fl[i]; m; m &= m - 1) {
1945 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
1946 struct sge_fl *fl = s->egr_map[id];
1948 clear_bit(id, s->starving_fl);
1949 smp_mb__after_clear_bit();
1952 * Since we are accessing fl without a lock there's a
1953 * small probability of a false positive where we
1954 * schedule napi but the FL is no longer starving.
1957 if (fl_starving(fl)) {
1958 struct sge_eth_rxq *rxq;
1960 rxq = container_of(fl, struct sge_eth_rxq, fl);
1961 if (napi_reschedule(&rxq->rspq.napi))
1964 set_bit(id, s->starving_fl);
1970 * Reschedule the next scan for starving Free Lists ...
1972 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
1976 * sge_tx_timer_cb - perform periodic maintenance of SGE Tx queues
1977 * @data: the adapter
1979 * Runs periodically from a timer to perform maintenance of SGE TX queues.
1981 * b) Reclaims completed Tx packets for the Ethernet queues. Normally
1982 * packets are cleaned up by new Tx packets, this timer cleans up packets
1983 * when no new packets are being submitted. This is essential for pktgen,
1986 static void sge_tx_timer_cb(unsigned long data)
1988 struct adapter *adapter = (struct adapter *)data;
1989 struct sge *s = &adapter->sge;
1990 unsigned int i, budget;
1992 budget = MAX_TIMER_TX_RECLAIM;
1993 i = s->ethtxq_rover;
1995 struct sge_eth_txq *txq = &s->ethtxq[i];
1997 if (reclaimable(&txq->q) && __netif_tx_trylock(txq->txq)) {
1998 int avail = reclaimable(&txq->q);
2003 free_tx_desc(adapter, &txq->q, avail, true);
2004 txq->q.in_use -= avail;
2005 __netif_tx_unlock(txq->txq);
2013 if (i >= s->ethqsets)
2015 } while (i != s->ethtxq_rover);
2016 s->ethtxq_rover = i;
2019 * If we found too many reclaimable packets schedule a timer in the
2020 * near future to continue where we left off. Otherwise the next timer
2021 * will be at its normal interval.
2023 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2027 * t4vf_sge_alloc_rxq - allocate an SGE RX Queue
2028 * @adapter: the adapter
2029 * @rspq: pointer to to the new rxq's Response Queue to be filled in
2030 * @iqasynch: if 0, a normal rspq; if 1, an asynchronous event queue
2031 * @dev: the network device associated with the new rspq
2032 * @intr_dest: MSI-X vector index (overriden in MSI mode)
2033 * @fl: pointer to the new rxq's Free List to be filled in
2034 * @hnd: the interrupt handler to invoke for the rspq
2036 int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2037 bool iqasynch, struct net_device *dev,
2039 struct sge_fl *fl, rspq_handler_t hnd)
2041 struct port_info *pi = netdev_priv(dev);
2042 struct fw_iq_cmd cmd, rpl;
2043 int ret, iqandst, flsz = 0;
2046 * If we're using MSI interrupts and we're not initializing the
2047 * Forwarded Interrupt Queue itself, then set up this queue for
2048 * indirect interrupts to the Forwarded Interrupt Queue. Obviously
2049 * the Forwarded Interrupt Queue must be set up before any other
2052 if ((adapter->flags & USING_MSI) && rspq != &adapter->sge.intrq) {
2053 iqandst = SGE_INTRDST_IQ;
2054 intr_dest = adapter->sge.intrq.abs_id;
2056 iqandst = SGE_INTRDST_PCI;
2059 * Allocate the hardware ring for the Response Queue. The size needs
2060 * to be a multiple of 16 which includes the mandatory status entry
2061 * (regardless of whether the Status Page capabilities are enabled or
2064 rspq->size = roundup(rspq->size, 16);
2065 rspq->desc = alloc_ring(adapter->pdev_dev, rspq->size, rspq->iqe_len,
2066 0, &rspq->phys_addr, NULL, 0);
2071 * Fill in the Ingress Queue Command. Note: Ideally this code would
2072 * be in t4vf_hw.c but there are so many parameters and dependencies
2073 * on our Linux SGE state that we would end up having to pass tons of
2074 * parameters. We'll have to think about how this might be migrated
2075 * into OS-independent common code ...
2077 memset(&cmd, 0, sizeof(cmd));
2078 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_IQ_CMD) |
2082 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC |
2083 FW_IQ_CMD_IQSTART(1) |
2085 cmd.type_to_iqandstindex =
2086 cpu_to_be32(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2087 FW_IQ_CMD_IQASYNCH(iqasynch) |
2088 FW_IQ_CMD_VIID(pi->viid) |
2089 FW_IQ_CMD_IQANDST(iqandst) |
2090 FW_IQ_CMD_IQANUS(1) |
2091 FW_IQ_CMD_IQANUD(SGE_UPDATEDEL_INTR) |
2092 FW_IQ_CMD_IQANDSTINDEX(intr_dest));
2093 cmd.iqdroprss_to_iqesize =
2094 cpu_to_be16(FW_IQ_CMD_IQPCIECH(pi->port_id) |
2095 FW_IQ_CMD_IQGTSMODE |
2096 FW_IQ_CMD_IQINTCNTTHRESH(rspq->pktcnt_idx) |
2097 FW_IQ_CMD_IQESIZE(ilog2(rspq->iqe_len) - 4));
2098 cmd.iqsize = cpu_to_be16(rspq->size);
2099 cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
2103 * Allocate the ring for the hardware free list (with space
2104 * for its status page) along with the associated software
2105 * descriptor ring. The free list size needs to be a multiple
2106 * of the Egress Queue Unit.
2108 fl->size = roundup(fl->size, FL_PER_EQ_UNIT);
2109 fl->desc = alloc_ring(adapter->pdev_dev, fl->size,
2110 sizeof(__be64), sizeof(struct rx_sw_desc),
2111 &fl->addr, &fl->sdesc, STAT_LEN);
2118 * Calculate the size of the hardware free list ring plus
2119 * status page (which the SGE will place at the end of the
2120 * free list ring) in Egress Queue Units.
2122 flsz = (fl->size / FL_PER_EQ_UNIT +
2123 STAT_LEN / EQ_UNIT);
2126 * Fill in all the relevant firmware Ingress Queue Command
2127 * fields for the free list.
2129 cmd.iqns_to_fl0congen =
2131 FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) |
2132 FW_IQ_CMD_FL0PACKEN |
2133 FW_IQ_CMD_FL0PADEN);
2134 cmd.fl0dcaen_to_fl0cidxfthresh =
2136 FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) |
2137 FW_IQ_CMD_FL0FBMAX(SGE_FETCHBURSTMAX_512B));
2138 cmd.fl0size = cpu_to_be16(flsz);
2139 cmd.fl0addr = cpu_to_be64(fl->addr);
2143 * Issue the firmware Ingress Queue Command and extract the results if
2144 * it completes successfully.
2146 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2150 netif_napi_add(dev, &rspq->napi, napi_rx_handler, 64);
2151 rspq->cur_desc = rspq->desc;
2154 rspq->next_intr_params = rspq->intr_params;
2155 rspq->cntxt_id = be16_to_cpu(rpl.iqid);
2156 rspq->abs_id = be16_to_cpu(rpl.physiqid);
2157 rspq->size--; /* subtract status entry */
2158 rspq->adapter = adapter;
2160 rspq->handler = hnd;
2162 /* set offset to -1 to distinguish ingress queues without FL */
2163 rspq->offset = fl ? 0 : -1;
2166 fl->cntxt_id = be16_to_cpu(rpl.fl0id);
2171 fl->alloc_failed = 0;
2172 fl->large_alloc_failed = 0;
2174 refill_fl(adapter, fl, fl_cap(fl), GFP_KERNEL);
2181 * An error occurred. Clean up our partial allocation state and
2185 dma_free_coherent(adapter->pdev_dev, rspq->size * rspq->iqe_len,
2186 rspq->desc, rspq->phys_addr);
2189 if (fl && fl->desc) {
2192 dma_free_coherent(adapter->pdev_dev, flsz * EQ_UNIT,
2193 fl->desc, fl->addr);
2200 * t4vf_sge_alloc_eth_txq - allocate an SGE Ethernet TX Queue
2201 * @adapter: the adapter
2202 * @txq: pointer to the new txq to be filled in
2203 * @devq: the network TX queue associated with the new txq
2204 * @iqid: the relative ingress queue ID to which events relating to
2205 * the new txq should be directed
2207 int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
2208 struct net_device *dev, struct netdev_queue *devq,
2212 struct fw_eq_eth_cmd cmd, rpl;
2213 struct port_info *pi = netdev_priv(dev);
2216 * Calculate the size of the hardware TX Queue (including the
2217 * status age on the end) in units of TX Descriptors.
2219 nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
2222 * Allocate the hardware ring for the TX ring (with space for its
2223 * status page) along with the associated software descriptor ring.
2225 txq->q.desc = alloc_ring(adapter->pdev_dev, txq->q.size,
2226 sizeof(struct tx_desc),
2227 sizeof(struct tx_sw_desc),
2228 &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
2233 * Fill in the Egress Queue Command. Note: As with the direct use of
2234 * the firmware Ingress Queue COmmand above in our RXQ allocation
2235 * routine, ideally, this code would be in t4vf_hw.c. Again, we'll
2236 * have to see if there's some reasonable way to parameterize it
2237 * into the common code ...
2239 memset(&cmd, 0, sizeof(cmd));
2240 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_EQ_ETH_CMD) |
2244 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC |
2245 FW_EQ_ETH_CMD_EQSTART |
2247 cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_VIID(pi->viid));
2248 cmd.fetchszm_to_iqid =
2249 cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE(SGE_HOSTFCMODE_STPG) |
2250 FW_EQ_ETH_CMD_PCIECHN(pi->port_id) |
2251 FW_EQ_ETH_CMD_IQID(iqid));
2252 cmd.dcaen_to_eqsize =
2253 cpu_to_be32(FW_EQ_ETH_CMD_FBMIN(SGE_FETCHBURSTMIN_64B) |
2254 FW_EQ_ETH_CMD_FBMAX(SGE_FETCHBURSTMAX_512B) |
2255 FW_EQ_ETH_CMD_CIDXFTHRESH(SGE_CIDXFLUSHTHRESH_32) |
2256 FW_EQ_ETH_CMD_EQSIZE(nentries));
2257 cmd.eqaddr = cpu_to_be64(txq->q.phys_addr);
2260 * Issue the firmware Egress Queue Command and extract the results if
2261 * it completes successfully.
2263 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2266 * The girmware Ingress Queue Command failed for some reason.
2267 * Free up our partial allocation state and return the error.
2269 kfree(txq->q.sdesc);
2270 txq->q.sdesc = NULL;
2271 dma_free_coherent(adapter->pdev_dev,
2272 nentries * sizeof(struct tx_desc),
2273 txq->q.desc, txq->q.phys_addr);
2281 txq->q.stat = (void *)&txq->q.desc[txq->q.size];
2282 txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_GET(be32_to_cpu(rpl.eqid_pkd));
2284 FW_EQ_ETH_CMD_PHYSEQID_GET(be32_to_cpu(rpl.physeqid_pkd));
2290 txq->q.restarts = 0;
2291 txq->mapping_err = 0;
2296 * Free the DMA map resources associated with a TX queue.
2298 static void free_txq(struct adapter *adapter, struct sge_txq *tq)
2300 dma_free_coherent(adapter->pdev_dev,
2301 tq->size * sizeof(*tq->desc) + STAT_LEN,
2302 tq->desc, tq->phys_addr);
2309 * Free the resources associated with a response queue (possibly including a
2312 static void free_rspq_fl(struct adapter *adapter, struct sge_rspq *rspq,
2315 unsigned int flid = fl ? fl->cntxt_id : 0xffff;
2317 t4vf_iq_free(adapter, FW_IQ_TYPE_FL_INT_CAP,
2318 rspq->cntxt_id, flid, 0xffff);
2319 dma_free_coherent(adapter->pdev_dev, (rspq->size + 1) * rspq->iqe_len,
2320 rspq->desc, rspq->phys_addr);
2321 netif_napi_del(&rspq->napi);
2322 rspq->netdev = NULL;
2328 free_rx_bufs(adapter, fl, fl->avail);
2329 dma_free_coherent(adapter->pdev_dev,
2330 fl->size * sizeof(*fl->desc) + STAT_LEN,
2331 fl->desc, fl->addr);
2340 * t4vf_free_sge_resources - free SGE resources
2341 * @adapter: the adapter
2343 * Frees resources used by the SGE queue sets.
2345 void t4vf_free_sge_resources(struct adapter *adapter)
2347 struct sge *s = &adapter->sge;
2348 struct sge_eth_rxq *rxq = s->ethrxq;
2349 struct sge_eth_txq *txq = s->ethtxq;
2350 struct sge_rspq *evtq = &s->fw_evtq;
2351 struct sge_rspq *intrq = &s->intrq;
2354 for (qs = 0; qs < adapter->sge.ethqsets; qs++, rxq++, txq++) {
2356 free_rspq_fl(adapter, &rxq->rspq, &rxq->fl);
2358 t4vf_eth_eq_free(adapter, txq->q.cntxt_id);
2359 free_tx_desc(adapter, &txq->q, txq->q.in_use, true);
2360 kfree(txq->q.sdesc);
2361 free_txq(adapter, &txq->q);
2365 free_rspq_fl(adapter, evtq, NULL);
2367 free_rspq_fl(adapter, intrq, NULL);
2371 * t4vf_sge_start - enable SGE operation
2372 * @adapter: the adapter
2374 * Start tasklets and timers associated with the DMA engine.
2376 void t4vf_sge_start(struct adapter *adapter)
2378 adapter->sge.ethtxq_rover = 0;
2379 mod_timer(&adapter->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2380 mod_timer(&adapter->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2384 * t4vf_sge_stop - disable SGE operation
2385 * @adapter: the adapter
2387 * Stop tasklets and timers associated with the DMA engine. Note that
2388 * this is effective only if measures have been taken to disable any HW
2389 * events that may restart them.
2391 void t4vf_sge_stop(struct adapter *adapter)
2393 struct sge *s = &adapter->sge;
2395 if (s->rx_timer.function)
2396 del_timer_sync(&s->rx_timer);
2397 if (s->tx_timer.function)
2398 del_timer_sync(&s->tx_timer);
2402 * t4vf_sge_init - initialize SGE
2403 * @adapter: the adapter
2405 * Performs SGE initialization needed every time after a chip reset.
2406 * We do not initialize any of the queue sets here, instead the driver
2407 * top-level must request those individually. We also do not enable DMA
2408 * here, that should be done after the queues have been set up.
2410 int t4vf_sge_init(struct adapter *adapter)
2412 struct sge_params *sge_params = &adapter->params.sge;
2413 u32 fl0 = sge_params->sge_fl_buffer_size[0];
2414 u32 fl1 = sge_params->sge_fl_buffer_size[1];
2415 struct sge *s = &adapter->sge;
2418 * Start by vetting the basic SGE parameters which have been set up by
2419 * the Physical Function Driver. Ideally we should be able to deal
2420 * with _any_ configuration. Practice is different ...
2422 if (fl0 != PAGE_SIZE || (fl1 != 0 && fl1 <= fl0)) {
2423 dev_err(adapter->pdev_dev, "bad SGE FL buffer sizes [%d, %d]\n",
2427 if ((sge_params->sge_control & RXPKTCPLMODE) == 0) {
2428 dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
2433 * Now translate the adapter parameters into our internal forms.
2436 FL_PG_ORDER = ilog2(fl1) - PAGE_SHIFT;
2437 STAT_LEN = ((sge_params->sge_control & EGRSTATUSPAGESIZE) ? 128 : 64);
2438 PKTSHIFT = PKTSHIFT_GET(sge_params->sge_control);
2439 FL_ALIGN = 1 << (INGPADBOUNDARY_GET(sge_params->sge_control) +
2440 SGE_INGPADBOUNDARY_SHIFT);
2443 * Set up tasklet timers.
2445 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adapter);
2446 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adapter);
2449 * Initialize Forwarded Interrupt Queue lock.
2451 spin_lock_init(&s->intrq_lock);