2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
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21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
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24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
45 #include "t4vf_common.h"
46 #include "t4vf_defs.h"
48 #include "../cxgb4/t4_regs.h"
49 #include "../cxgb4/t4fw_api.h"
50 #include "../cxgb4/t4_msg.h"
53 * Decoded Adapter Parameters.
55 static u32 FL_PG_ORDER; /* large page allocation size */
56 static u32 STAT_LEN; /* length of status page at ring end */
57 static u32 PKTSHIFT; /* padding between CPL and packet data */
58 static u32 FL_ALIGN; /* response queue message alignment */
65 * Egress Queue sizes, producer and consumer indices are all in units
66 * of Egress Context Units bytes. Note that as far as the hardware is
67 * concerned, the free list is an Egress Queue (the host produces free
68 * buffers which the hardware consumes) and free list entries are
69 * 64-bit PCI DMA addresses.
71 EQ_UNIT = SGE_EQ_IDXSIZE,
72 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
73 TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
76 * Max number of TX descriptors we clean up at a time. Should be
77 * modest as freeing skbs isn't cheap and it happens while holding
78 * locks. We just need to free packets faster than they arrive, we
79 * eventually catch up and keep the amortized cost reasonable.
84 * Max number of Rx buffers we replenish at a time. Again keep this
85 * modest, allocating buffers isn't cheap either.
90 * Period of the Rx queue check timer. This timer is infrequent as it
91 * has something to do only when the system experiences severe memory
94 RX_QCHECK_PERIOD = (HZ / 2),
97 * Period of the TX queue check timer and the maximum number of TX
98 * descriptors to be reclaimed by the TX timer.
100 TX_QCHECK_PERIOD = (HZ / 2),
101 MAX_TIMER_TX_RECLAIM = 100,
104 * An FL with <= FL_STARVE_THRES buffers is starving and a periodic
105 * timer will attempt to refill it.
110 * Suspend an Ethernet TX queue with fewer available descriptors than
111 * this. We always want to have room for a maximum sized packet:
112 * inline immediate data + MAX_SKB_FRAGS. This is the same as
113 * calc_tx_flits() for a TSO packet with nr_frags == MAX_SKB_FRAGS
114 * (see that function and its helpers for a description of the
117 ETHTXQ_MAX_FRAGS = MAX_SKB_FRAGS + 1,
118 ETHTXQ_MAX_SGL_LEN = ((3 * (ETHTXQ_MAX_FRAGS-1))/2 +
119 ((ETHTXQ_MAX_FRAGS-1) & 1) +
121 ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) +
122 sizeof(struct cpl_tx_pkt_lso_core) +
123 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64),
124 ETHTXQ_MAX_FLITS = ETHTXQ_MAX_SGL_LEN + ETHTXQ_MAX_HDR,
126 ETHTXQ_STOP_THRES = 1 + DIV_ROUND_UP(ETHTXQ_MAX_FLITS, TXD_PER_EQ_UNIT),
129 * Max TX descriptor space we allow for an Ethernet packet to be
130 * inlined into a WR. This is limited by the maximum value which
131 * we can specify for immediate data in the firmware Ethernet TX
134 MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_MASK,
137 * Max size of a WR sent through a control TX queue.
139 MAX_CTRL_WR_LEN = 256,
142 * Maximum amount of data which we'll ever need to inline into a
143 * TX ring: max(MAX_IMM_TX_PKT_LEN, MAX_CTRL_WR_LEN).
145 MAX_IMM_TX_LEN = (MAX_IMM_TX_PKT_LEN > MAX_CTRL_WR_LEN
150 * For incoming packets less than RX_COPY_THRES, we copy the data into
151 * an skb rather than referencing the data. We allocate enough
152 * in-line room in skb's to accommodate pulling in RX_PULL_LEN bytes
153 * of the data (header).
160 * Can't define this in the above enum because PKTSHIFT isn't a constant in
163 #define RX_PKT_PULL_LEN (RX_PULL_LEN + PKTSHIFT)
166 * Software state per TX descriptor.
169 struct sk_buff *skb; /* socket buffer of TX data source */
170 struct ulptx_sgl *sgl; /* scatter/gather list in TX Queue */
174 * Software state per RX Free List descriptor. We keep track of the allocated
175 * FL page, its size, and its PCI DMA address (if the page is mapped). The FL
176 * page size and its PCI DMA mapped state are stored in the low bits of the
177 * PCI DMA address as per below.
180 struct page *page; /* Free List page buffer */
181 dma_addr_t dma_addr; /* PCI DMA address (if mapped) */
182 /* and flags (see below) */
186 * The low bits of rx_sw_desc.dma_addr have special meaning. Note that the
187 * SGE also uses the low 4 bits to determine the size of the buffer. It uses
188 * those bits to index into the SGE_FL_BUFFER_SIZE[index] register array.
189 * Since we only use SGE_FL_BUFFER_SIZE0 and SGE_FL_BUFFER_SIZE1, these low 4
190 * bits can only contain a 0 or a 1 to indicate which size buffer we're giving
191 * to the SGE. Thus, our software state of "is the buffer mapped for DMA" is
192 * maintained in an inverse sense so the hardware never sees that bit high.
195 RX_LARGE_BUF = 1 << 0, /* buffer is SGE_FL_BUFFER_SIZE[1] */
196 RX_UNMAPPED_BUF = 1 << 1, /* buffer is not mapped */
200 * get_buf_addr - return DMA buffer address of software descriptor
201 * @sdesc: pointer to the software buffer descriptor
203 * Return the DMA buffer address of a software descriptor (stripping out
204 * our low-order flag bits).
206 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *sdesc)
208 return sdesc->dma_addr & ~(dma_addr_t)(RX_LARGE_BUF | RX_UNMAPPED_BUF);
212 * is_buf_mapped - is buffer mapped for DMA?
213 * @sdesc: pointer to the software buffer descriptor
215 * Determine whether the buffer associated with a software descriptor in
216 * mapped for DMA or not.
218 static inline bool is_buf_mapped(const struct rx_sw_desc *sdesc)
220 return !(sdesc->dma_addr & RX_UNMAPPED_BUF);
224 * need_skb_unmap - does the platform need unmapping of sk_buffs?
226 * Returns true if the platfrom needs sk_buff unmapping. The compiler
227 * optimizes away unecessary code if this returns true.
229 static inline int need_skb_unmap(void)
232 * This structure is used to tell if the platfrom needs buffer
233 * unmapping by checking if DECLARE_PCI_UNMAP_ADDR defines anything.
236 DECLARE_PCI_UNMAP_ADDR(addr);
239 return sizeof(struct dummy) != 0;
243 * txq_avail - return the number of available slots in a TX queue
246 * Returns the number of available descriptors in a TX queue.
248 static inline unsigned int txq_avail(const struct sge_txq *tq)
250 return tq->size - 1 - tq->in_use;
254 * fl_cap - return the capacity of a Free List
257 * Returns the capacity of a Free List. The capacity is less than the
258 * size because an Egress Queue Index Unit worth of descriptors needs to
259 * be left unpopulated, otherwise the Producer and Consumer indices PIDX
260 * and CIDX will match and the hardware will think the FL is empty.
262 static inline unsigned int fl_cap(const struct sge_fl *fl)
264 return fl->size - FL_PER_EQ_UNIT;
268 * fl_starving - return whether a Free List is starving.
271 * Tests specified Free List to see whether the number of buffers
272 * available to the hardware has falled below our "starvation"
275 static inline bool fl_starving(const struct sge_fl *fl)
277 return fl->avail - fl->pend_cred <= FL_STARVE_THRES;
281 * map_skb - map an skb for DMA to the device
282 * @dev: the egress net device
283 * @skb: the packet to map
284 * @addr: a pointer to the base of the DMA mapping array
286 * Map an skb for DMA to the device and return an array of DMA addresses.
288 static int map_skb(struct device *dev, const struct sk_buff *skb,
291 const skb_frag_t *fp, *end;
292 const struct skb_shared_info *si;
294 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
295 if (dma_mapping_error(dev, *addr))
298 si = skb_shinfo(skb);
299 end = &si->frags[si->nr_frags];
300 for (fp = si->frags; fp < end; fp++) {
301 *++addr = dma_map_page(dev, fp->page, fp->page_offset, fp->size,
303 if (dma_mapping_error(dev, *addr))
309 while (fp-- > si->frags)
310 dma_unmap_page(dev, *--addr, fp->size, DMA_TO_DEVICE);
311 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
317 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
318 const struct ulptx_sgl *sgl, const struct sge_txq *tq)
320 const struct ulptx_sge_pair *p;
321 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
323 if (likely(skb_headlen(skb)))
324 dma_unmap_single(dev, be64_to_cpu(sgl->addr0),
325 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
327 dma_unmap_page(dev, be64_to_cpu(sgl->addr0),
328 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
333 * the complexity below is because of the possibility of a wrap-around
334 * in the middle of an SGL
336 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
337 if (likely((u8 *)(p + 1) <= (u8 *)tq->stat)) {
339 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
340 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
341 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
342 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
344 } else if ((u8 *)p == (u8 *)tq->stat) {
345 p = (const struct ulptx_sge_pair *)tq->desc;
347 } else if ((u8 *)p + 8 == (u8 *)tq->stat) {
348 const __be64 *addr = (const __be64 *)tq->desc;
350 dma_unmap_page(dev, be64_to_cpu(addr[0]),
351 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
352 dma_unmap_page(dev, be64_to_cpu(addr[1]),
353 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
354 p = (const struct ulptx_sge_pair *)&addr[2];
356 const __be64 *addr = (const __be64 *)tq->desc;
358 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
359 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
360 dma_unmap_page(dev, be64_to_cpu(addr[0]),
361 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
362 p = (const struct ulptx_sge_pair *)&addr[1];
368 if ((u8 *)p == (u8 *)tq->stat)
369 p = (const struct ulptx_sge_pair *)tq->desc;
370 addr = ((u8 *)p + 16 <= (u8 *)tq->stat
372 : *(const __be64 *)tq->desc);
373 dma_unmap_page(dev, be64_to_cpu(addr), be32_to_cpu(p->len[0]),
379 * free_tx_desc - reclaims TX descriptors and their buffers
380 * @adapter: the adapter
381 * @tq: the TX queue to reclaim descriptors from
382 * @n: the number of descriptors to reclaim
383 * @unmap: whether the buffers should be unmapped for DMA
385 * Reclaims TX descriptors from an SGE TX queue and frees the associated
386 * TX buffers. Called with the TX queue lock held.
388 static void free_tx_desc(struct adapter *adapter, struct sge_txq *tq,
389 unsigned int n, bool unmap)
391 struct tx_sw_desc *sdesc;
392 unsigned int cidx = tq->cidx;
393 struct device *dev = adapter->pdev_dev;
395 const int need_unmap = need_skb_unmap() && unmap;
397 sdesc = &tq->sdesc[cidx];
400 * If we kept a reference to the original TX skb, we need to
401 * unmap it from PCI DMA space (if required) and free it.
405 unmap_sgl(dev, sdesc->skb, sdesc->sgl, tq);
406 kfree_skb(sdesc->skb);
411 if (++cidx == tq->size) {
420 * Return the number of reclaimable descriptors in a TX queue.
422 static inline int reclaimable(const struct sge_txq *tq)
424 int hw_cidx = be16_to_cpu(tq->stat->cidx);
425 int reclaimable = hw_cidx - tq->cidx;
427 reclaimable += tq->size;
432 * reclaim_completed_tx - reclaims completed TX descriptors
433 * @adapter: the adapter
434 * @tq: the TX queue to reclaim completed descriptors from
435 * @unmap: whether the buffers should be unmapped for DMA
437 * Reclaims TX descriptors that the SGE has indicated it has processed,
438 * and frees the associated buffers if possible. Called with the TX
441 static inline void reclaim_completed_tx(struct adapter *adapter,
445 int avail = reclaimable(tq);
449 * Limit the amount of clean up work we do at a time to keep
450 * the TX lock hold time O(1).
452 if (avail > MAX_TX_RECLAIM)
453 avail = MAX_TX_RECLAIM;
455 free_tx_desc(adapter, tq, avail, unmap);
461 * get_buf_size - return the size of an RX Free List buffer.
462 * @sdesc: pointer to the software buffer descriptor
464 static inline int get_buf_size(const struct rx_sw_desc *sdesc)
466 return FL_PG_ORDER > 0 && (sdesc->dma_addr & RX_LARGE_BUF)
467 ? (PAGE_SIZE << FL_PG_ORDER)
472 * free_rx_bufs - free RX buffers on an SGE Free List
473 * @adapter: the adapter
474 * @fl: the SGE Free List to free buffers from
475 * @n: how many buffers to free
477 * Release the next @n buffers on an SGE Free List RX queue. The
478 * buffers must be made inaccessible to hardware before calling this
481 static void free_rx_bufs(struct adapter *adapter, struct sge_fl *fl, int n)
484 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
486 if (is_buf_mapped(sdesc))
487 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
488 get_buf_size(sdesc), PCI_DMA_FROMDEVICE);
489 put_page(sdesc->page);
491 if (++fl->cidx == fl->size)
498 * unmap_rx_buf - unmap the current RX buffer on an SGE Free List
499 * @adapter: the adapter
500 * @fl: the SGE Free List
502 * Unmap the current buffer on an SGE Free List RX queue. The
503 * buffer must be made inaccessible to HW before calling this function.
505 * This is similar to @free_rx_bufs above but does not free the buffer.
506 * Do note that the FL still loses any further access to the buffer.
507 * This is used predominantly to "transfer ownership" of an FL buffer
508 * to another entity (typically an skb's fragment list).
510 static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
512 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
514 if (is_buf_mapped(sdesc))
515 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
516 get_buf_size(sdesc), PCI_DMA_FROMDEVICE);
518 if (++fl->cidx == fl->size)
524 * ring_fl_db - righ doorbell on free list
525 * @adapter: the adapter
526 * @fl: the Free List whose doorbell should be rung ...
528 * Tell the Scatter Gather Engine that there are new free list entries
531 static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
534 * The SGE keeps track of its Producer and Consumer Indices in terms
535 * of Egress Queue Units so we can only tell it about integral numbers
536 * of multiples of Free List Entries per Egress Queue Units ...
538 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
540 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
543 PIDX(fl->pend_cred / FL_PER_EQ_UNIT));
544 fl->pend_cred %= FL_PER_EQ_UNIT;
549 * set_rx_sw_desc - initialize software RX buffer descriptor
550 * @sdesc: pointer to the softwore RX buffer descriptor
551 * @page: pointer to the page data structure backing the RX buffer
552 * @dma_addr: PCI DMA address (possibly with low-bit flags)
554 static inline void set_rx_sw_desc(struct rx_sw_desc *sdesc, struct page *page,
558 sdesc->dma_addr = dma_addr;
562 * Support for poisoning RX buffers ...
564 #define POISON_BUF_VAL -1
566 static inline void poison_buf(struct page *page, size_t sz)
568 #if POISON_BUF_VAL >= 0
569 memset(page_address(page), POISON_BUF_VAL, sz);
574 * refill_fl - refill an SGE RX buffer ring
575 * @adapter: the adapter
576 * @fl: the Free List ring to refill
577 * @n: the number of new buffers to allocate
578 * @gfp: the gfp flags for the allocations
580 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
581 * allocated with the supplied gfp flags. The caller must assure that
582 * @n does not exceed the queue's capacity -- i.e. (cidx == pidx) _IN
583 * EGRESS QUEUE UNITS_ indicates an empty Free List! Returns the number
584 * of buffers allocated. If afterwards the queue is found critically low,
585 * mark it as starving in the bitmap of starving FLs.
587 static unsigned int refill_fl(struct adapter *adapter, struct sge_fl *fl,
592 unsigned int cred = fl->avail;
593 __be64 *d = &fl->desc[fl->pidx];
594 struct rx_sw_desc *sdesc = &fl->sdesc[fl->pidx];
597 * Sanity: ensure that the result of adding n Free List buffers
598 * won't result in wrapping the SGE's Producer Index around to
599 * it's Consumer Index thereby indicating an empty Free List ...
601 BUG_ON(fl->avail + n > fl->size - FL_PER_EQ_UNIT);
604 * If we support large pages, prefer large buffers and fail over to
605 * small pages if we can't allocate large pages to satisfy the refill.
606 * If we don't support large pages, drop directly into the small page
609 if (FL_PG_ORDER == 0)
610 goto alloc_small_pages;
613 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
615 if (unlikely(!page)) {
617 * We've failed inour attempt to allocate a "large
618 * page". Fail over to the "small page" allocation
621 fl->large_alloc_failed++;
624 poison_buf(page, PAGE_SIZE << FL_PG_ORDER);
626 dma_addr = dma_map_page(adapter->pdev_dev, page, 0,
627 PAGE_SIZE << FL_PG_ORDER,
629 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
631 * We've run out of DMA mapping space. Free up the
632 * buffer and return with what we've managed to put
633 * into the free list. We don't want to fail over to
634 * the small page allocation below in this case
635 * because DMA mapping resources are typically
636 * critical resources once they become scarse.
638 __free_pages(page, FL_PG_ORDER);
641 dma_addr |= RX_LARGE_BUF;
642 *d++ = cpu_to_be64(dma_addr);
644 set_rx_sw_desc(sdesc, page, dma_addr);
648 if (++fl->pidx == fl->size) {
658 page = __netdev_alloc_page(adapter->port[0],
660 if (unlikely(!page)) {
664 poison_buf(page, PAGE_SIZE);
666 dma_addr = dma_map_page(adapter->pdev_dev, page, 0, PAGE_SIZE,
668 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
669 netdev_free_page(adapter->port[0], page);
672 *d++ = cpu_to_be64(dma_addr);
674 set_rx_sw_desc(sdesc, page, dma_addr);
678 if (++fl->pidx == fl->size) {
687 * Update our accounting state to incorporate the new Free List
688 * buffers, tell the hardware about them and return the number of
689 * bufers which we were able to allocate.
691 cred = fl->avail - cred;
692 fl->pend_cred += cred;
693 ring_fl_db(adapter, fl);
695 if (unlikely(fl_starving(fl))) {
697 set_bit(fl->cntxt_id, adapter->sge.starving_fl);
704 * Refill a Free List to its capacity or the Maximum Refill Increment,
705 * whichever is smaller ...
707 static inline void __refill_fl(struct adapter *adapter, struct sge_fl *fl)
709 refill_fl(adapter, fl,
710 min((unsigned int)MAX_RX_REFILL, fl_cap(fl) - fl->avail),
715 * alloc_ring - allocate resources for an SGE descriptor ring
716 * @dev: the PCI device's core device
717 * @nelem: the number of descriptors
718 * @hwsize: the size of each hardware descriptor
719 * @swsize: the size of each software descriptor
720 * @busaddrp: the physical PCI bus address of the allocated ring
721 * @swringp: return address pointer for software ring
722 * @stat_size: extra space in hardware ring for status information
724 * Allocates resources for an SGE descriptor ring, such as TX queues,
725 * free buffer lists, response queues, etc. Each SGE ring requires
726 * space for its hardware descriptors plus, optionally, space for software
727 * state associated with each hardware entry (the metadata). The function
728 * returns three values: the virtual address for the hardware ring (the
729 * return value of the function), the PCI bus address of the hardware
730 * ring (in *busaddrp), and the address of the software ring (in swringp).
731 * Both the hardware and software rings are returned zeroed out.
733 static void *alloc_ring(struct device *dev, size_t nelem, size_t hwsize,
734 size_t swsize, dma_addr_t *busaddrp, void *swringp,
738 * Allocate the hardware ring and PCI DMA bus address space for said.
740 size_t hwlen = nelem * hwsize + stat_size;
741 void *hwring = dma_alloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL);
747 * If the caller wants a software ring, allocate it and return a
748 * pointer to it in *swringp.
750 BUG_ON((swsize != 0) != (swringp != NULL));
752 void *swring = kcalloc(nelem, swsize, GFP_KERNEL);
755 dma_free_coherent(dev, hwlen, hwring, *busaddrp);
758 *(void **)swringp = swring;
762 * Zero out the hardware ring and return its address as our function
765 memset(hwring, 0, hwlen);
770 * sgl_len - calculates the size of an SGL of the given capacity
771 * @n: the number of SGL entries
773 * Calculates the number of flits (8-byte units) needed for a Direct
774 * Scatter/Gather List that can hold the given number of entries.
776 static inline unsigned int sgl_len(unsigned int n)
779 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
780 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
781 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
782 * repeated sequences of { Length[i], Length[i+1], Address[i],
783 * Address[i+1] } (this ensures that all addresses are on 64-bit
784 * boundaries). If N is even, then Length[N+1] should be set to 0 and
785 * Address[N+1] is omitted.
787 * The following calculation incorporates all of the above. It's
788 * somewhat hard to follow but, briefly: the "+2" accounts for the
789 * first two flits which include the DSGL header, Length0 and
790 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
791 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
792 * finally the "+((n-1)&1)" adds the one remaining flit needed if
796 return (3 * n) / 2 + (n & 1) + 2;
800 * flits_to_desc - returns the num of TX descriptors for the given flits
801 * @flits: the number of flits
803 * Returns the number of TX descriptors needed for the supplied number
806 static inline unsigned int flits_to_desc(unsigned int flits)
808 BUG_ON(flits > SGE_MAX_WR_LEN / sizeof(__be64));
809 return DIV_ROUND_UP(flits, TXD_PER_EQ_UNIT);
813 * is_eth_imm - can an Ethernet packet be sent as immediate data?
816 * Returns whether an Ethernet packet is small enough to fit completely as
819 static inline int is_eth_imm(const struct sk_buff *skb)
822 * The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request
823 * which does not accommodate immediate data. We could dike out all
824 * of the support code for immediate data but that would tie our hands
825 * too much if we ever want to enhace the firmware. It would also
826 * create more differences between the PF and VF Drivers.
832 * calc_tx_flits - calculate the number of flits for a packet TX WR
835 * Returns the number of flits needed for a TX Work Request for the
836 * given Ethernet packet, including the needed WR and CPL headers.
838 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
843 * If the skb is small enough, we can pump it out as a work request
844 * with only immediate data. In that case we just have to have the
845 * TX Packet header plus the skb data in the Work Request.
848 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt),
852 * Otherwise, we're going to have to construct a Scatter gather list
853 * of the skb body and fragments. We also include the flits necessary
854 * for the TX Packet Work Request and CPL. We always have a firmware
855 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
856 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
857 * message or, if we're doing a Large Send Offload, an LSO CPL message
858 * with an embeded TX Packet Write CPL message.
860 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
861 if (skb_shinfo(skb)->gso_size)
862 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
863 sizeof(struct cpl_tx_pkt_lso_core) +
864 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
866 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
867 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
872 * write_sgl - populate a Scatter/Gather List for a packet
874 * @tq: the TX queue we are writing into
875 * @sgl: starting location for writing the SGL
876 * @end: points right after the end of the SGL
877 * @start: start offset into skb main-body data to include in the SGL
878 * @addr: the list of DMA bus addresses for the SGL elements
880 * Generates a Scatter/Gather List for the buffers that make up a packet.
881 * The caller must provide adequate space for the SGL that will be written.
882 * The SGL includes all of the packet's page fragments and the data in its
883 * main body except for the first @start bytes. @pos must be 16-byte
884 * aligned and within a TX descriptor with available space. @end points
885 * write after the end of the SGL but does not account for any potential
886 * wrap around, i.e., @end > @tq->stat.
888 static void write_sgl(const struct sk_buff *skb, struct sge_txq *tq,
889 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
890 const dma_addr_t *addr)
893 struct ulptx_sge_pair *to;
894 const struct skb_shared_info *si = skb_shinfo(skb);
895 unsigned int nfrags = si->nr_frags;
896 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
898 len = skb_headlen(skb) - start;
900 sgl->len0 = htonl(len);
901 sgl->addr0 = cpu_to_be64(addr[0] + start);
904 sgl->len0 = htonl(si->frags[0].size);
905 sgl->addr0 = cpu_to_be64(addr[1]);
908 sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) |
910 if (likely(--nfrags == 0))
913 * Most of the complexity below deals with the possibility we hit the
914 * end of the queue in the middle of writing the SGL. For this case
915 * only we create the SGL in a temporary buffer and then copy it.
917 to = (u8 *)end > (u8 *)tq->stat ? buf : sgl->sge;
919 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
920 to->len[0] = cpu_to_be32(si->frags[i].size);
921 to->len[1] = cpu_to_be32(si->frags[++i].size);
922 to->addr[0] = cpu_to_be64(addr[i]);
923 to->addr[1] = cpu_to_be64(addr[++i]);
926 to->len[0] = cpu_to_be32(si->frags[i].size);
927 to->len[1] = cpu_to_be32(0);
928 to->addr[0] = cpu_to_be64(addr[i + 1]);
930 if (unlikely((u8 *)end > (u8 *)tq->stat)) {
931 unsigned int part0 = (u8 *)tq->stat - (u8 *)sgl->sge, part1;
934 memcpy(sgl->sge, buf, part0);
935 part1 = (u8 *)end - (u8 *)tq->stat;
936 memcpy(tq->desc, (u8 *)buf + part0, part1);
937 end = (void *)tq->desc + part1;
939 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
944 * check_ring_tx_db - check and potentially ring a TX queue's doorbell
945 * @adapter: the adapter
947 * @n: number of new descriptors to give to HW
949 * Ring the doorbel for a TX queue.
951 static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
955 * Warn if we write doorbells with the wrong priority and write
956 * descriptors before telling HW.
958 WARN_ON((QID(tq->cntxt_id) | PIDX(n)) & DBPRIO);
960 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
961 QID(tq->cntxt_id) | PIDX(n));
965 * inline_tx_skb - inline a packet's data into TX descriptors
967 * @tq: the TX queue where the packet will be inlined
968 * @pos: starting position in the TX queue to inline the packet
970 * Inline a packet's contents directly into TX descriptors, starting at
971 * the given position within the TX DMA ring.
972 * Most of the complexity of this operation is dealing with wrap arounds
973 * in the middle of the packet we want to inline.
975 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
979 int left = (void *)tq->stat - pos;
981 if (likely(skb->len <= left)) {
982 if (likely(!skb->data_len))
983 skb_copy_from_linear_data(skb, pos, skb->len);
985 skb_copy_bits(skb, 0, pos, skb->len);
988 skb_copy_bits(skb, 0, pos, left);
989 skb_copy_bits(skb, left, tq->desc, skb->len - left);
990 pos = (void *)tq->desc + (skb->len - left);
993 /* 0-pad to multiple of 16 */
994 p = PTR_ALIGN(pos, 8);
995 if ((uintptr_t)p & 8)
1000 * Figure out what HW csum a packet wants and return the appropriate control
1003 static u64 hwcsum(const struct sk_buff *skb)
1006 const struct iphdr *iph = ip_hdr(skb);
1008 if (iph->version == 4) {
1009 if (iph->protocol == IPPROTO_TCP)
1010 csum_type = TX_CSUM_TCPIP;
1011 else if (iph->protocol == IPPROTO_UDP)
1012 csum_type = TX_CSUM_UDPIP;
1016 * unknown protocol, disable HW csum
1017 * and hope a bad packet is detected
1019 return TXPKT_L4CSUM_DIS;
1023 * this doesn't work with extension headers
1025 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1027 if (ip6h->nexthdr == IPPROTO_TCP)
1028 csum_type = TX_CSUM_TCPIP6;
1029 else if (ip6h->nexthdr == IPPROTO_UDP)
1030 csum_type = TX_CSUM_UDPIP6;
1035 if (likely(csum_type >= TX_CSUM_TCPIP))
1036 return TXPKT_CSUM_TYPE(csum_type) |
1037 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
1038 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
1040 int start = skb_transport_offset(skb);
1042 return TXPKT_CSUM_TYPE(csum_type) |
1043 TXPKT_CSUM_START(start) |
1044 TXPKT_CSUM_LOC(start + skb->csum_offset);
1049 * Stop an Ethernet TX queue and record that state change.
1051 static void txq_stop(struct sge_eth_txq *txq)
1053 netif_tx_stop_queue(txq->txq);
1058 * Advance our software state for a TX queue by adding n in use descriptors.
1060 static inline void txq_advance(struct sge_txq *tq, unsigned int n)
1064 if (tq->pidx >= tq->size)
1065 tq->pidx -= tq->size;
1069 * t4vf_eth_xmit - add a packet to an Ethernet TX queue
1071 * @dev: the egress net device
1073 * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled.
1075 int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1079 unsigned int flits, ndesc;
1080 struct adapter *adapter;
1081 struct sge_eth_txq *txq;
1082 const struct port_info *pi;
1083 struct fw_eth_tx_pkt_vm_wr *wr;
1084 struct cpl_tx_pkt_core *cpl;
1085 const struct skb_shared_info *ssi;
1086 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1087 const size_t fw_hdr_copy_len = (sizeof(wr->ethmacdst) +
1088 sizeof(wr->ethmacsrc) +
1089 sizeof(wr->ethtype) +
1090 sizeof(wr->vlantci));
1093 * The chip minimum packet length is 10 octets but the firmware
1094 * command that we are using requires that we copy the Ethernet header
1095 * (including the VLAN tag) into the header so we reject anything
1096 * smaller than that ...
1098 if (unlikely(skb->len < fw_hdr_copy_len))
1102 * Figure out which TX Queue we're going to use.
1104 pi = netdev_priv(dev);
1105 adapter = pi->adapter;
1106 qidx = skb_get_queue_mapping(skb);
1107 BUG_ON(qidx >= pi->nqsets);
1108 txq = &adapter->sge.ethtxq[pi->first_qset + qidx];
1111 * Take this opportunity to reclaim any TX Descriptors whose DMA
1112 * transfers have completed.
1114 reclaim_completed_tx(adapter, &txq->q, true);
1117 * Calculate the number of flits and TX Descriptors we're going to
1118 * need along with how many TX Descriptors will be left over after
1119 * we inject our Work Request.
1121 flits = calc_tx_flits(skb);
1122 ndesc = flits_to_desc(flits);
1123 credits = txq_avail(&txq->q) - ndesc;
1125 if (unlikely(credits < 0)) {
1127 * Not enough room for this packet's Work Request. Stop the
1128 * TX Queue and return a "busy" condition. The queue will get
1129 * started later on when the firmware informs us that space
1133 dev_err(adapter->pdev_dev,
1134 "%s: TX ring %u full while queue awake!\n",
1136 return NETDEV_TX_BUSY;
1139 if (!is_eth_imm(skb) &&
1140 unlikely(map_skb(adapter->pdev_dev, skb, addr) < 0)) {
1142 * We need to map the skb into PCI DMA space (because it can't
1143 * be in-lined directly into the Work Request) and the mapping
1144 * operation failed. Record the error and drop the packet.
1150 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1152 * After we're done injecting the Work Request for this
1153 * packet, we'll be below our "stop threshhold" so stop the TX
1154 * Queue now. The queue will get started later on when the
1155 * firmware informs us that space has opened up.
1161 * Start filling in our Work Request. Note that we do _not_ handle
1162 * the WR Header wrapping around the TX Descriptor Ring. If our
1163 * maximum header size ever exceeds one TX Descriptor, we'll need to
1164 * do something else here.
1166 BUG_ON(DIV_ROUND_UP(ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
1167 wr = (void *)&txq->q.desc[txq->q.pidx];
1168 wr->equiq_to_len16 = cpu_to_be32(FW_WR_LEN16(DIV_ROUND_UP(flits, 2)));
1169 wr->r3[0] = cpu_to_be64(0);
1170 wr->r3[1] = cpu_to_be64(0);
1171 skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
1172 end = (u64 *)wr + flits;
1175 * If this is a Large Send Offload packet we'll put in an LSO CPL
1176 * message with an encapsulated TX Packet CPL message. Otherwise we
1177 * just use a TX Packet CPL message.
1179 ssi = skb_shinfo(skb);
1180 if (ssi->gso_size) {
1181 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1182 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1183 int l3hdr_len = skb_network_header_len(skb);
1184 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1187 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1188 FW_WR_IMMDLEN(sizeof(*lso) +
1191 * Fill in the LSO CPL message.
1194 cpu_to_be32(LSO_OPCODE(CPL_TX_PKT_LSO) |
1198 LSO_ETHHDR_LEN(eth_xtra_len/4) |
1199 LSO_IPHDR_LEN(l3hdr_len/4) |
1200 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
1201 lso->ipid_ofst = cpu_to_be16(0);
1202 lso->mss = cpu_to_be16(ssi->gso_size);
1203 lso->seqno_offset = cpu_to_be32(0);
1204 lso->len = cpu_to_be32(skb->len);
1207 * Set up TX Packet CPL pointer, control word and perform
1210 cpl = (void *)(lso + 1);
1211 cntrl = (TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1212 TXPKT_IPHDR_LEN(l3hdr_len) |
1213 TXPKT_ETHHDR_LEN(eth_xtra_len));
1215 txq->tx_cso += ssi->gso_segs;
1219 len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
1221 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1222 FW_WR_IMMDLEN(len));
1225 * Set up TX Packet CPL pointer, control word and perform
1228 cpl = (void *)(wr + 1);
1229 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1230 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
1233 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
1237 * If there's a VLAN tag present, add that to the list of things to
1238 * do in this Work Request.
1240 if (vlan_tx_tag_present(skb)) {
1242 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb));
1246 * Fill in the TX Packet CPL message header.
1248 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE(CPL_TX_PKT_XT) |
1249 TXPKT_INTF(pi->port_id) |
1251 cpl->pack = cpu_to_be16(0);
1252 cpl->len = cpu_to_be16(skb->len);
1253 cpl->ctrl1 = cpu_to_be64(cntrl);
1256 T4_TRACE5(adapter->tb[txq->q.cntxt_id & 7],
1257 "eth_xmit: ndesc %u, credits %u, pidx %u, len %u, frags %u",
1258 ndesc, credits, txq->q.pidx, skb->len, ssi->nr_frags);
1262 * Fill in the body of the TX Packet CPL message with either in-lined
1263 * data or a Scatter/Gather List.
1265 if (is_eth_imm(skb)) {
1267 * In-line the packet's data and free the skb since we don't
1268 * need it any longer.
1270 inline_tx_skb(skb, &txq->q, cpl + 1);
1274 * Write the skb's Scatter/Gather list into the TX Packet CPL
1275 * message and retain a pointer to the skb so we can free it
1276 * later when its DMA completes. (We store the skb pointer
1277 * in the Software Descriptor corresponding to the last TX
1278 * Descriptor used by the Work Request.)
1280 * The retained skb will be freed when the corresponding TX
1281 * Descriptors are reclaimed after their DMAs complete.
1282 * However, this could take quite a while since, in general,
1283 * the hardware is set up to be lazy about sending DMA
1284 * completion notifications to us and we mostly perform TX
1285 * reclaims in the transmit routine.
1287 * This is good for performamce but means that we rely on new
1288 * TX packets arriving to run the destructors of completed
1289 * packets, which open up space in their sockets' send queues.
1290 * Sometimes we do not get such new packets causing TX to
1291 * stall. A single UDP transmitter is a good example of this
1292 * situation. We have a clean up timer that periodically
1293 * reclaims completed packets but it doesn't run often enough
1294 * (nor do we want it to) to prevent lengthy stalls. A
1295 * solution to this problem is to run the destructor early,
1296 * after the packet is queued but before it's DMAd. A con is
1297 * that we lie to socket memory accounting, but the amount of
1298 * extra memory is reasonable (limited by the number of TX
1299 * descriptors), the packets do actually get freed quickly by
1300 * new packets almost always, and for protocols like TCP that
1301 * wait for acks to really free up the data the extra memory
1302 * is even less. On the positive side we run the destructors
1303 * on the sending CPU rather than on a potentially different
1304 * completing CPU, usually a good thing.
1306 * Run the destructor before telling the DMA engine about the
1307 * packet to make sure it doesn't complete and get freed
1310 struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1);
1311 struct sge_txq *tq = &txq->q;
1315 * If the Work Request header was an exact multiple of our TX
1316 * Descriptor length, then it's possible that the starting SGL
1317 * pointer lines up exactly with the end of our TX Descriptor
1318 * ring. If that's the case, wrap around to the beginning
1321 if (unlikely((void *)sgl == (void *)tq->stat)) {
1322 sgl = (void *)tq->desc;
1323 end = (void *)((void *)tq->desc +
1324 ((void *)end - (void *)tq->stat));
1327 write_sgl(skb, tq, sgl, end, 0, addr);
1330 last_desc = tq->pidx + ndesc - 1;
1331 if (last_desc >= tq->size)
1332 last_desc -= tq->size;
1333 tq->sdesc[last_desc].skb = skb;
1334 tq->sdesc[last_desc].sgl = sgl;
1338 * Advance our internal TX Queue state, tell the hardware about
1339 * the new TX descriptors and return success.
1341 txq_advance(&txq->q, ndesc);
1342 dev->trans_start = jiffies;
1343 ring_tx_db(adapter, &txq->q, ndesc);
1344 return NETDEV_TX_OK;
1348 * An error of some sort happened. Free the TX skb and tell the
1349 * OS that we've "dealt" with the packet ...
1352 return NETDEV_TX_OK;
1356 * t4vf_pktgl_free - free a packet gather list
1357 * @gl: the gather list
1359 * Releases the pages of a packet gather list. We do not own the last
1360 * page on the list and do not free it.
1362 void t4vf_pktgl_free(const struct pkt_gl *gl)
1366 frag = gl->nfrags - 1;
1368 put_page(gl->frags[frag].page);
1372 * copy_frags - copy fragments from gather list into skb_shared_info
1373 * @si: destination skb shared info structure
1374 * @gl: source internal packet gather list
1375 * @offset: packet start offset in first page
1377 * Copy an internal packet gather list into a Linux skb_shared_info
1380 static inline void copy_frags(struct skb_shared_info *si,
1381 const struct pkt_gl *gl,
1382 unsigned int offset)
1386 /* usually there's just one frag */
1387 si->frags[0].page = gl->frags[0].page;
1388 si->frags[0].page_offset = gl->frags[0].page_offset + offset;
1389 si->frags[0].size = gl->frags[0].size - offset;
1390 si->nr_frags = gl->nfrags;
1394 memcpy(&si->frags[1], &gl->frags[1], n * sizeof(skb_frag_t));
1396 /* get a reference to the last page, we don't own it */
1397 get_page(gl->frags[n].page);
1401 * do_gro - perform Generic Receive Offload ingress packet processing
1402 * @rxq: ingress RX Ethernet Queue
1403 * @gl: gather list for ingress packet
1404 * @pkt: CPL header for last packet fragment
1406 * Perform Generic Receive Offload (GRO) ingress packet processing.
1407 * We use the standard Linux GRO interfaces for this.
1409 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1410 const struct cpl_rx_pkt *pkt)
1413 struct sk_buff *skb;
1415 skb = napi_get_frags(&rxq->rspq.napi);
1416 if (unlikely(!skb)) {
1417 t4vf_pktgl_free(gl);
1418 rxq->stats.rx_drops++;
1422 copy_frags(skb_shinfo(skb), gl, PKTSHIFT);
1423 skb->len = gl->tot_len - PKTSHIFT;
1424 skb->data_len = skb->len;
1425 skb->truesize += skb->data_len;
1426 skb->ip_summed = CHECKSUM_UNNECESSARY;
1427 skb_record_rx_queue(skb, rxq->rspq.idx);
1429 if (unlikely(pkt->vlan_ex)) {
1430 struct port_info *pi = netdev_priv(rxq->rspq.netdev);
1431 struct vlan_group *grp = pi->vlan_grp;
1433 rxq->stats.vlan_ex++;
1435 ret = vlan_gro_frags(&rxq->rspq.napi, grp,
1436 be16_to_cpu(pkt->vlan));
1440 ret = napi_gro_frags(&rxq->rspq.napi);
1443 if (ret == GRO_HELD)
1444 rxq->stats.lro_pkts++;
1445 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1446 rxq->stats.lro_merged++;
1448 rxq->stats.rx_cso++;
1452 * t4vf_ethrx_handler - process an ingress ethernet packet
1453 * @rspq: the response queue that received the packet
1454 * @rsp: the response queue descriptor holding the RX_PKT message
1455 * @gl: the gather list of packet fragments
1457 * Process an ingress ethernet packet and deliver it to the stack.
1459 int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp,
1460 const struct pkt_gl *gl)
1462 struct sk_buff *skb;
1463 struct port_info *pi;
1464 struct skb_shared_info *ssi;
1465 const struct cpl_rx_pkt *pkt = (void *)&rsp[1];
1466 bool csum_ok = pkt->csum_calc && !pkt->err_vec;
1467 unsigned int len = be16_to_cpu(pkt->len);
1468 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1471 * If this is a good TCP packet and we have Generic Receive Offload
1472 * enabled, handle the packet in the GRO path.
1474 if ((pkt->l2info & cpu_to_be32(RXF_TCP)) &&
1475 (rspq->netdev->features & NETIF_F_GRO) && csum_ok &&
1477 do_gro(rxq, gl, pkt);
1482 * If the ingress packet is small enough, allocate an skb large enough
1483 * for all of the data and copy it inline. Otherwise, allocate an skb
1484 * with enough room to pull in the header and reference the rest of
1485 * the data via the skb fragment list.
1487 if (len <= RX_COPY_THRES) {
1488 /* small packets have only one fragment */
1489 skb = alloc_skb(gl->frags[0].size, GFP_ATOMIC);
1492 __skb_put(skb, gl->frags[0].size);
1493 skb_copy_to_linear_data(skb, gl->va, gl->frags[0].size);
1495 skb = alloc_skb(RX_PKT_PULL_LEN, GFP_ATOMIC);
1498 __skb_put(skb, RX_PKT_PULL_LEN);
1499 skb_copy_to_linear_data(skb, gl->va, RX_PKT_PULL_LEN);
1501 ssi = skb_shinfo(skb);
1502 ssi->frags[0].page = gl->frags[0].page;
1503 ssi->frags[0].page_offset = (gl->frags[0].page_offset +
1505 ssi->frags[0].size = gl->frags[0].size - RX_PKT_PULL_LEN;
1507 memcpy(&ssi->frags[1], &gl->frags[1],
1508 (gl->nfrags-1) * sizeof(skb_frag_t));
1509 ssi->nr_frags = gl->nfrags;
1510 skb->len = len + PKTSHIFT;
1511 skb->data_len = skb->len - RX_PKT_PULL_LEN;
1512 skb->truesize += skb->data_len;
1514 /* Get a reference for the last page, we don't own it */
1515 get_page(gl->frags[gl->nfrags - 1].page);
1518 __skb_pull(skb, PKTSHIFT);
1519 skb->protocol = eth_type_trans(skb, rspq->netdev);
1520 skb_record_rx_queue(skb, rspq->idx);
1521 skb->dev->last_rx = jiffies; /* XXX removed 2.6.29 */
1522 pi = netdev_priv(skb->dev);
1525 if (csum_ok && (pi->rx_offload & RX_CSO) && !pkt->err_vec &&
1526 (be32_to_cpu(pkt->l2info) & (RXF_UDP|RXF_TCP))) {
1528 skb->ip_summed = CHECKSUM_UNNECESSARY;
1530 __sum16 c = (__force __sum16)pkt->csum;
1531 skb->csum = csum_unfold(c);
1532 skb->ip_summed = CHECKSUM_COMPLETE;
1534 rxq->stats.rx_cso++;
1536 skb->ip_summed = CHECKSUM_NONE;
1538 if (unlikely(pkt->vlan_ex)) {
1539 struct vlan_group *grp = pi->vlan_grp;
1541 rxq->stats.vlan_ex++;
1543 vlan_hwaccel_receive_skb(skb, grp,
1544 be16_to_cpu(pkt->vlan));
1546 dev_kfree_skb_any(skb);
1548 netif_receive_skb(skb);
1553 t4vf_pktgl_free(gl);
1554 rxq->stats.rx_drops++;
1559 * is_new_response - check if a response is newly written
1560 * @rc: the response control descriptor
1561 * @rspq: the response queue
1563 * Returns true if a response descriptor contains a yet unprocessed
1566 static inline bool is_new_response(const struct rsp_ctrl *rc,
1567 const struct sge_rspq *rspq)
1569 return RSPD_GEN(rc->type_gen) == rspq->gen;
1573 * restore_rx_bufs - put back a packet's RX buffers
1574 * @gl: the packet gather list
1575 * @fl: the SGE Free List
1576 * @nfrags: how many fragments in @si
1578 * Called when we find out that the current packet, @si, can't be
1579 * processed right away for some reason. This is a very rare event and
1580 * there's no effort to make this suspension/resumption process
1581 * particularly efficient.
1583 * We implement the suspension by putting all of the RX buffers associated
1584 * with the current packet back on the original Free List. The buffers
1585 * have already been unmapped and are left unmapped, we mark them as
1586 * unmapped in order to prevent further unmapping attempts. (Effectively
1587 * this function undoes the series of @unmap_rx_buf calls which were done
1588 * to create the current packet's gather list.) This leaves us ready to
1589 * restart processing of the packet the next time we start processing the
1592 static void restore_rx_bufs(const struct pkt_gl *gl, struct sge_fl *fl,
1595 struct rx_sw_desc *sdesc;
1599 fl->cidx = fl->size - 1;
1602 sdesc = &fl->sdesc[fl->cidx];
1603 sdesc->page = gl->frags[frags].page;
1604 sdesc->dma_addr |= RX_UNMAPPED_BUF;
1610 * rspq_next - advance to the next entry in a response queue
1613 * Updates the state of a response queue to advance it to the next entry.
1615 static inline void rspq_next(struct sge_rspq *rspq)
1617 rspq->cur_desc = (void *)rspq->cur_desc + rspq->iqe_len;
1618 if (unlikely(++rspq->cidx == rspq->size)) {
1621 rspq->cur_desc = rspq->desc;
1626 * process_responses - process responses from an SGE response queue
1627 * @rspq: the ingress response queue to process
1628 * @budget: how many responses can be processed in this round
1630 * Process responses from a Scatter Gather Engine response queue up to
1631 * the supplied budget. Responses include received packets as well as
1632 * control messages from firmware or hardware.
1634 * Additionally choose the interrupt holdoff time for the next interrupt
1635 * on this queue. If the system is under memory shortage use a fairly
1636 * long delay to help recovery.
1638 int process_responses(struct sge_rspq *rspq, int budget)
1640 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1641 int budget_left = budget;
1643 while (likely(budget_left)) {
1645 const struct rsp_ctrl *rc;
1647 rc = (void *)rspq->cur_desc + (rspq->iqe_len - sizeof(*rc));
1648 if (!is_new_response(rc, rspq))
1652 * Figure out what kind of response we've received from the
1656 rsp_type = RSPD_TYPE(rc->type_gen);
1657 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1660 const struct rx_sw_desc *sdesc;
1662 u32 len = be32_to_cpu(rc->pldbuflen_qid);
1665 * If we get a "new buffer" message from the SGE we
1666 * need to move on to the next Free List buffer.
1668 if (len & RSPD_NEWBUF) {
1670 * We get one "new buffer" message when we
1671 * first start up a queue so we need to ignore
1672 * it when our offset into the buffer is 0.
1674 if (likely(rspq->offset > 0)) {
1675 free_rx_bufs(rspq->adapter, &rxq->fl,
1679 len = RSPD_LEN(len);
1683 * Gather packet fragments.
1685 for (frag = 0, fp = gl.frags; /**/; frag++, fp++) {
1686 BUG_ON(frag >= MAX_SKB_FRAGS);
1687 BUG_ON(rxq->fl.avail == 0);
1688 sdesc = &rxq->fl.sdesc[rxq->fl.cidx];
1689 bufsz = get_buf_size(sdesc);
1690 fp->page = sdesc->page;
1691 fp->page_offset = rspq->offset;
1692 fp->size = min(bufsz, len);
1696 unmap_rx_buf(rspq->adapter, &rxq->fl);
1701 * Last buffer remains mapped so explicitly make it
1702 * coherent for CPU access and start preloading first
1705 dma_sync_single_for_cpu(rspq->adapter->pdev_dev,
1706 get_buf_addr(sdesc),
1707 fp->size, DMA_FROM_DEVICE);
1708 gl.va = (page_address(gl.frags[0].page) +
1709 gl.frags[0].page_offset);
1713 * Hand the new ingress packet to the handler for
1714 * this Response Queue.
1716 ret = rspq->handler(rspq, rspq->cur_desc, &gl);
1717 if (likely(ret == 0))
1718 rspq->offset += ALIGN(fp->size, FL_ALIGN);
1720 restore_rx_bufs(&gl, &rxq->fl, frag);
1721 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
1722 ret = rspq->handler(rspq, rspq->cur_desc, NULL);
1724 WARN_ON(rsp_type > RSP_TYPE_CPL);
1728 if (unlikely(ret)) {
1730 * Couldn't process descriptor, back off for recovery.
1731 * We use the SGE's last timer which has the longest
1732 * interrupt coalescing value ...
1734 const int NOMEM_TIMER_IDX = SGE_NTIMERS-1;
1735 rspq->next_intr_params =
1736 QINTR_TIMER_IDX(NOMEM_TIMER_IDX);
1745 * If this is a Response Queue with an associated Free List and
1746 * at least two Egress Queue units available in the Free List
1747 * for new buffer pointers, refill the Free List.
1749 if (rspq->offset >= 0 &&
1750 rxq->fl.size - rxq->fl.avail >= 2*FL_PER_EQ_UNIT)
1751 __refill_fl(rspq->adapter, &rxq->fl);
1752 return budget - budget_left;
1756 * napi_rx_handler - the NAPI handler for RX processing
1757 * @napi: the napi instance
1758 * @budget: how many packets we can process in this round
1760 * Handler for new data events when using NAPI. This does not need any
1761 * locking or protection from interrupts as data interrupts are off at
1762 * this point and other adapter interrupts do not interfere (the latter
1763 * in not a concern at all with MSI-X as non-data interrupts then have
1764 * a separate handler).
1766 static int napi_rx_handler(struct napi_struct *napi, int budget)
1768 unsigned int intr_params;
1769 struct sge_rspq *rspq = container_of(napi, struct sge_rspq, napi);
1770 int work_done = process_responses(rspq, budget);
1772 if (likely(work_done < budget)) {
1773 napi_complete(napi);
1774 intr_params = rspq->next_intr_params;
1775 rspq->next_intr_params = rspq->intr_params;
1777 intr_params = QINTR_TIMER_IDX(SGE_TIMER_UPD_CIDX);
1779 t4_write_reg(rspq->adapter,
1780 T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1781 CIDXINC(work_done) |
1782 INGRESSQID((u32)rspq->cntxt_id) |
1783 SEINTARM(intr_params));
1788 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
1789 * (i.e., response queue serviced by NAPI polling).
1791 irqreturn_t t4vf_sge_intr_msix(int irq, void *cookie)
1793 struct sge_rspq *rspq = cookie;
1795 napi_schedule(&rspq->napi);
1800 * Process the indirect interrupt entries in the interrupt queue and kick off
1801 * NAPI for each queue that has generated an entry.
1803 static unsigned int process_intrq(struct adapter *adapter)
1805 struct sge *s = &adapter->sge;
1806 struct sge_rspq *intrq = &s->intrq;
1807 unsigned int work_done;
1809 spin_lock(&adapter->sge.intrq_lock);
1810 for (work_done = 0; ; work_done++) {
1811 const struct rsp_ctrl *rc;
1812 unsigned int qid, iq_idx;
1813 struct sge_rspq *rspq;
1816 * Grab the next response from the interrupt queue and bail
1817 * out if it's not a new response.
1819 rc = (void *)intrq->cur_desc + (intrq->iqe_len - sizeof(*rc));
1820 if (!is_new_response(rc, intrq))
1824 * If the response isn't a forwarded interrupt message issue a
1825 * error and go on to the next response message. This should
1829 if (unlikely(RSPD_TYPE(rc->type_gen) != RSP_TYPE_INTR)) {
1830 dev_err(adapter->pdev_dev,
1831 "Unexpected INTRQ response type %d\n",
1832 RSPD_TYPE(rc->type_gen));
1837 * Extract the Queue ID from the interrupt message and perform
1838 * sanity checking to make sure it really refers to one of our
1839 * Ingress Queues which is active and matches the queue's ID.
1840 * None of these error conditions should ever happen so we may
1841 * want to either make them fatal and/or conditionalized under
1844 qid = RSPD_QID(be32_to_cpu(rc->pldbuflen_qid));
1845 iq_idx = IQ_IDX(s, qid);
1846 if (unlikely(iq_idx >= MAX_INGQ)) {
1847 dev_err(adapter->pdev_dev,
1848 "Ingress QID %d out of range\n", qid);
1851 rspq = s->ingr_map[iq_idx];
1852 if (unlikely(rspq == NULL)) {
1853 dev_err(adapter->pdev_dev,
1854 "Ingress QID %d RSPQ=NULL\n", qid);
1857 if (unlikely(rspq->abs_id != qid)) {
1858 dev_err(adapter->pdev_dev,
1859 "Ingress QID %d refers to RSPQ %d\n",
1865 * Schedule NAPI processing on the indicated Response Queue
1866 * and move on to the next entry in the Forwarded Interrupt
1869 napi_schedule(&rspq->napi);
1873 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1874 CIDXINC(work_done) |
1875 INGRESSQID(intrq->cntxt_id) |
1876 SEINTARM(intrq->intr_params));
1878 spin_unlock(&adapter->sge.intrq_lock);
1884 * The MSI interrupt handler handles data events from SGE response queues as
1885 * well as error and other async events as they all use the same MSI vector.
1887 irqreturn_t t4vf_intr_msi(int irq, void *cookie)
1889 struct adapter *adapter = cookie;
1891 process_intrq(adapter);
1896 * t4vf_intr_handler - select the top-level interrupt handler
1897 * @adapter: the adapter
1899 * Selects the top-level interrupt handler based on the type of interrupts
1902 irq_handler_t t4vf_intr_handler(struct adapter *adapter)
1904 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
1905 if (adapter->flags & USING_MSIX)
1906 return t4vf_sge_intr_msix;
1908 return t4vf_intr_msi;
1912 * sge_rx_timer_cb - perform periodic maintenance of SGE RX queues
1913 * @data: the adapter
1915 * Runs periodically from a timer to perform maintenance of SGE RX queues.
1917 * a) Replenishes RX queues that have run out due to memory shortage.
1918 * Normally new RX buffers are added when existing ones are consumed but
1919 * when out of memory a queue can become empty. We schedule NAPI to do
1920 * the actual refill.
1922 static void sge_rx_timer_cb(unsigned long data)
1924 struct adapter *adapter = (struct adapter *)data;
1925 struct sge *s = &adapter->sge;
1929 * Scan the "Starving Free Lists" flag array looking for any Free
1930 * Lists in need of more free buffers. If we find one and it's not
1931 * being actively polled, then bump its "starving" counter and attempt
1932 * to refill it. If we're successful in adding enough buffers to push
1933 * the Free List over the starving threshold, then we can clear its
1934 * "starving" status.
1936 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) {
1939 for (m = s->starving_fl[i]; m; m &= m - 1) {
1940 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
1941 struct sge_fl *fl = s->egr_map[id];
1943 clear_bit(id, s->starving_fl);
1944 smp_mb__after_clear_bit();
1947 * Since we are accessing fl without a lock there's a
1948 * small probability of a false positive where we
1949 * schedule napi but the FL is no longer starving.
1952 if (fl_starving(fl)) {
1953 struct sge_eth_rxq *rxq;
1955 rxq = container_of(fl, struct sge_eth_rxq, fl);
1956 if (napi_reschedule(&rxq->rspq.napi))
1959 set_bit(id, s->starving_fl);
1965 * Reschedule the next scan for starving Free Lists ...
1967 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
1971 * sge_tx_timer_cb - perform periodic maintenance of SGE Tx queues
1972 * @data: the adapter
1974 * Runs periodically from a timer to perform maintenance of SGE TX queues.
1976 * b) Reclaims completed Tx packets for the Ethernet queues. Normally
1977 * packets are cleaned up by new Tx packets, this timer cleans up packets
1978 * when no new packets are being submitted. This is essential for pktgen,
1981 static void sge_tx_timer_cb(unsigned long data)
1983 struct adapter *adapter = (struct adapter *)data;
1984 struct sge *s = &adapter->sge;
1985 unsigned int i, budget;
1987 budget = MAX_TIMER_TX_RECLAIM;
1988 i = s->ethtxq_rover;
1990 struct sge_eth_txq *txq = &s->ethtxq[i];
1992 if (reclaimable(&txq->q) && __netif_tx_trylock(txq->txq)) {
1993 int avail = reclaimable(&txq->q);
1998 free_tx_desc(adapter, &txq->q, avail, true);
1999 txq->q.in_use -= avail;
2000 __netif_tx_unlock(txq->txq);
2008 if (i >= s->ethqsets)
2010 } while (i != s->ethtxq_rover);
2011 s->ethtxq_rover = i;
2014 * If we found too many reclaimable packets schedule a timer in the
2015 * near future to continue where we left off. Otherwise the next timer
2016 * will be at its normal interval.
2018 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2022 * t4vf_sge_alloc_rxq - allocate an SGE RX Queue
2023 * @adapter: the adapter
2024 * @rspq: pointer to to the new rxq's Response Queue to be filled in
2025 * @iqasynch: if 0, a normal rspq; if 1, an asynchronous event queue
2026 * @dev: the network device associated with the new rspq
2027 * @intr_dest: MSI-X vector index (overriden in MSI mode)
2028 * @fl: pointer to the new rxq's Free List to be filled in
2029 * @hnd: the interrupt handler to invoke for the rspq
2031 int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2032 bool iqasynch, struct net_device *dev,
2034 struct sge_fl *fl, rspq_handler_t hnd)
2036 struct port_info *pi = netdev_priv(dev);
2037 struct fw_iq_cmd cmd, rpl;
2038 int ret, iqandst, flsz = 0;
2041 * If we're using MSI interrupts and we're not initializing the
2042 * Forwarded Interrupt Queue itself, then set up this queue for
2043 * indirect interrupts to the Forwarded Interrupt Queue. Obviously
2044 * the Forwarded Interrupt Queue must be set up before any other
2047 if ((adapter->flags & USING_MSI) && rspq != &adapter->sge.intrq) {
2048 iqandst = SGE_INTRDST_IQ;
2049 intr_dest = adapter->sge.intrq.abs_id;
2051 iqandst = SGE_INTRDST_PCI;
2054 * Allocate the hardware ring for the Response Queue. The size needs
2055 * to be a multiple of 16 which includes the mandatory status entry
2056 * (regardless of whether the Status Page capabilities are enabled or
2059 rspq->size = roundup(rspq->size, 16);
2060 rspq->desc = alloc_ring(adapter->pdev_dev, rspq->size, rspq->iqe_len,
2061 0, &rspq->phys_addr, NULL, 0);
2066 * Fill in the Ingress Queue Command. Note: Ideally this code would
2067 * be in t4vf_hw.c but there are so many parameters and dependencies
2068 * on our Linux SGE state that we would end up having to pass tons of
2069 * parameters. We'll have to think about how this might be migrated
2070 * into OS-independent common code ...
2072 memset(&cmd, 0, sizeof(cmd));
2073 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_IQ_CMD) |
2077 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC |
2078 FW_IQ_CMD_IQSTART(1) |
2080 cmd.type_to_iqandstindex =
2081 cpu_to_be32(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2082 FW_IQ_CMD_IQASYNCH(iqasynch) |
2083 FW_IQ_CMD_VIID(pi->viid) |
2084 FW_IQ_CMD_IQANDST(iqandst) |
2085 FW_IQ_CMD_IQANUS(1) |
2086 FW_IQ_CMD_IQANUD(SGE_UPDATEDEL_INTR) |
2087 FW_IQ_CMD_IQANDSTINDEX(intr_dest));
2088 cmd.iqdroprss_to_iqesize =
2089 cpu_to_be16(FW_IQ_CMD_IQPCIECH(pi->port_id) |
2090 FW_IQ_CMD_IQGTSMODE |
2091 FW_IQ_CMD_IQINTCNTTHRESH(rspq->pktcnt_idx) |
2092 FW_IQ_CMD_IQESIZE(ilog2(rspq->iqe_len) - 4));
2093 cmd.iqsize = cpu_to_be16(rspq->size);
2094 cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
2098 * Allocate the ring for the hardware free list (with space
2099 * for its status page) along with the associated software
2100 * descriptor ring. The free list size needs to be a multiple
2101 * of the Egress Queue Unit.
2103 fl->size = roundup(fl->size, FL_PER_EQ_UNIT);
2104 fl->desc = alloc_ring(adapter->pdev_dev, fl->size,
2105 sizeof(__be64), sizeof(struct rx_sw_desc),
2106 &fl->addr, &fl->sdesc, STAT_LEN);
2113 * Calculate the size of the hardware free list ring plus
2114 * status page (which the SGE will place at the end of the
2115 * free list ring) in Egress Queue Units.
2117 flsz = (fl->size / FL_PER_EQ_UNIT +
2118 STAT_LEN / EQ_UNIT);
2121 * Fill in all the relevant firmware Ingress Queue Command
2122 * fields for the free list.
2124 cmd.iqns_to_fl0congen =
2126 FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) |
2127 FW_IQ_CMD_FL0PACKEN |
2128 FW_IQ_CMD_FL0PADEN);
2129 cmd.fl0dcaen_to_fl0cidxfthresh =
2131 FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) |
2132 FW_IQ_CMD_FL0FBMAX(SGE_FETCHBURSTMAX_512B));
2133 cmd.fl0size = cpu_to_be16(flsz);
2134 cmd.fl0addr = cpu_to_be64(fl->addr);
2138 * Issue the firmware Ingress Queue Command and extract the results if
2139 * it completes successfully.
2141 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2145 netif_napi_add(dev, &rspq->napi, napi_rx_handler, 64);
2146 rspq->cur_desc = rspq->desc;
2149 rspq->next_intr_params = rspq->intr_params;
2150 rspq->cntxt_id = be16_to_cpu(rpl.iqid);
2151 rspq->abs_id = be16_to_cpu(rpl.physiqid);
2152 rspq->size--; /* subtract status entry */
2153 rspq->adapter = adapter;
2155 rspq->handler = hnd;
2157 /* set offset to -1 to distinguish ingress queues without FL */
2158 rspq->offset = fl ? 0 : -1;
2161 fl->cntxt_id = be16_to_cpu(rpl.fl0id);
2166 fl->alloc_failed = 0;
2167 fl->large_alloc_failed = 0;
2169 refill_fl(adapter, fl, fl_cap(fl), GFP_KERNEL);
2176 * An error occurred. Clean up our partial allocation state and
2180 dma_free_coherent(adapter->pdev_dev, rspq->size * rspq->iqe_len,
2181 rspq->desc, rspq->phys_addr);
2184 if (fl && fl->desc) {
2187 dma_free_coherent(adapter->pdev_dev, flsz * EQ_UNIT,
2188 fl->desc, fl->addr);
2195 * t4vf_sge_alloc_eth_txq - allocate an SGE Ethernet TX Queue
2196 * @adapter: the adapter
2197 * @txq: pointer to the new txq to be filled in
2198 * @devq: the network TX queue associated with the new txq
2199 * @iqid: the relative ingress queue ID to which events relating to
2200 * the new txq should be directed
2202 int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
2203 struct net_device *dev, struct netdev_queue *devq,
2207 struct fw_eq_eth_cmd cmd, rpl;
2208 struct port_info *pi = netdev_priv(dev);
2211 * Calculate the size of the hardware TX Queue (including the
2212 * status age on the end) in units of TX Descriptors.
2214 nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
2217 * Allocate the hardware ring for the TX ring (with space for its
2218 * status page) along with the associated software descriptor ring.
2220 txq->q.desc = alloc_ring(adapter->pdev_dev, txq->q.size,
2221 sizeof(struct tx_desc),
2222 sizeof(struct tx_sw_desc),
2223 &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
2228 * Fill in the Egress Queue Command. Note: As with the direct use of
2229 * the firmware Ingress Queue COmmand above in our RXQ allocation
2230 * routine, ideally, this code would be in t4vf_hw.c. Again, we'll
2231 * have to see if there's some reasonable way to parameterize it
2232 * into the common code ...
2234 memset(&cmd, 0, sizeof(cmd));
2235 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_EQ_ETH_CMD) |
2239 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC |
2240 FW_EQ_ETH_CMD_EQSTART |
2242 cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_VIID(pi->viid));
2243 cmd.fetchszm_to_iqid =
2244 cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE(SGE_HOSTFCMODE_STPG) |
2245 FW_EQ_ETH_CMD_PCIECHN(pi->port_id) |
2246 FW_EQ_ETH_CMD_IQID(iqid));
2247 cmd.dcaen_to_eqsize =
2248 cpu_to_be32(FW_EQ_ETH_CMD_FBMIN(SGE_FETCHBURSTMIN_64B) |
2249 FW_EQ_ETH_CMD_FBMAX(SGE_FETCHBURSTMAX_512B) |
2250 FW_EQ_ETH_CMD_CIDXFTHRESH(SGE_CIDXFLUSHTHRESH_32) |
2251 FW_EQ_ETH_CMD_EQSIZE(nentries));
2252 cmd.eqaddr = cpu_to_be64(txq->q.phys_addr);
2255 * Issue the firmware Egress Queue Command and extract the results if
2256 * it completes successfully.
2258 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2261 * The girmware Ingress Queue Command failed for some reason.
2262 * Free up our partial allocation state and return the error.
2264 kfree(txq->q.sdesc);
2265 txq->q.sdesc = NULL;
2266 dma_free_coherent(adapter->pdev_dev,
2267 nentries * sizeof(struct tx_desc),
2268 txq->q.desc, txq->q.phys_addr);
2276 txq->q.stat = (void *)&txq->q.desc[txq->q.size];
2277 txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_GET(be32_to_cpu(rpl.eqid_pkd));
2279 FW_EQ_ETH_CMD_PHYSEQID_GET(be32_to_cpu(rpl.physeqid_pkd));
2285 txq->q.restarts = 0;
2286 txq->mapping_err = 0;
2291 * Free the DMA map resources associated with a TX queue.
2293 static void free_txq(struct adapter *adapter, struct sge_txq *tq)
2295 dma_free_coherent(adapter->pdev_dev,
2296 tq->size * sizeof(*tq->desc) + STAT_LEN,
2297 tq->desc, tq->phys_addr);
2304 * Free the resources associated with a response queue (possibly including a
2307 static void free_rspq_fl(struct adapter *adapter, struct sge_rspq *rspq,
2310 unsigned int flid = fl ? fl->cntxt_id : 0xffff;
2312 t4vf_iq_free(adapter, FW_IQ_TYPE_FL_INT_CAP,
2313 rspq->cntxt_id, flid, 0xffff);
2314 dma_free_coherent(adapter->pdev_dev, (rspq->size + 1) * rspq->iqe_len,
2315 rspq->desc, rspq->phys_addr);
2316 netif_napi_del(&rspq->napi);
2317 rspq->netdev = NULL;
2323 free_rx_bufs(adapter, fl, fl->avail);
2324 dma_free_coherent(adapter->pdev_dev,
2325 fl->size * sizeof(*fl->desc) + STAT_LEN,
2326 fl->desc, fl->addr);
2335 * t4vf_free_sge_resources - free SGE resources
2336 * @adapter: the adapter
2338 * Frees resources used by the SGE queue sets.
2340 void t4vf_free_sge_resources(struct adapter *adapter)
2342 struct sge *s = &adapter->sge;
2343 struct sge_eth_rxq *rxq = s->ethrxq;
2344 struct sge_eth_txq *txq = s->ethtxq;
2345 struct sge_rspq *evtq = &s->fw_evtq;
2346 struct sge_rspq *intrq = &s->intrq;
2349 for (qs = 0; qs < adapter->sge.ethqsets; qs++) {
2351 free_rspq_fl(adapter, &rxq->rspq, &rxq->fl);
2353 t4vf_eth_eq_free(adapter, txq->q.cntxt_id);
2354 free_tx_desc(adapter, &txq->q, txq->q.in_use, true);
2355 kfree(txq->q.sdesc);
2356 free_txq(adapter, &txq->q);
2360 free_rspq_fl(adapter, evtq, NULL);
2362 free_rspq_fl(adapter, intrq, NULL);
2366 * t4vf_sge_start - enable SGE operation
2367 * @adapter: the adapter
2369 * Start tasklets and timers associated with the DMA engine.
2371 void t4vf_sge_start(struct adapter *adapter)
2373 adapter->sge.ethtxq_rover = 0;
2374 mod_timer(&adapter->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2375 mod_timer(&adapter->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2379 * t4vf_sge_stop - disable SGE operation
2380 * @adapter: the adapter
2382 * Stop tasklets and timers associated with the DMA engine. Note that
2383 * this is effective only if measures have been taken to disable any HW
2384 * events that may restart them.
2386 void t4vf_sge_stop(struct adapter *adapter)
2388 struct sge *s = &adapter->sge;
2390 if (s->rx_timer.function)
2391 del_timer_sync(&s->rx_timer);
2392 if (s->tx_timer.function)
2393 del_timer_sync(&s->tx_timer);
2397 * t4vf_sge_init - initialize SGE
2398 * @adapter: the adapter
2400 * Performs SGE initialization needed every time after a chip reset.
2401 * We do not initialize any of the queue sets here, instead the driver
2402 * top-level must request those individually. We also do not enable DMA
2403 * here, that should be done after the queues have been set up.
2405 int t4vf_sge_init(struct adapter *adapter)
2407 struct sge_params *sge_params = &adapter->params.sge;
2408 u32 fl0 = sge_params->sge_fl_buffer_size[0];
2409 u32 fl1 = sge_params->sge_fl_buffer_size[1];
2410 struct sge *s = &adapter->sge;
2413 * Start by vetting the basic SGE parameters which have been set up by
2414 * the Physical Function Driver. Ideally we should be able to deal
2415 * with _any_ configuration. Practice is different ...
2417 if (fl0 != PAGE_SIZE || (fl1 != 0 && fl1 <= fl0)) {
2418 dev_err(adapter->pdev_dev, "bad SGE FL buffer sizes [%d, %d]\n",
2422 if ((sge_params->sge_control & RXPKTCPLMODE) == 0) {
2423 dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
2428 * Now translate the adapter parameters into our internal forms.
2431 FL_PG_ORDER = ilog2(fl1) - PAGE_SHIFT;
2432 STAT_LEN = ((sge_params->sge_control & EGRSTATUSPAGESIZE) ? 128 : 64);
2433 PKTSHIFT = PKTSHIFT_GET(sge_params->sge_control);
2434 FL_ALIGN = 1 << (INGPADBOUNDARY_GET(sge_params->sge_control) +
2435 SGE_INGPADBOUNDARY_SHIFT);
2438 * Set up tasklet timers.
2440 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adapter);
2441 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adapter);
2444 * Initialize Forwarded Interrupt Queue lock.
2446 spin_lock_init(&s->intrq_lock);