2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/version.h>
52 #include <linux/spinlock.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/clk.h>
55 #include <linux/platform_device.h>
56 #include <linux/semaphore.h>
57 #include <linux/phy.h>
58 #include <linux/bitops.h>
60 #include <linux/uaccess.h>
61 #include <linux/davinci_emac.h>
66 static int debug_level;
67 module_param(debug_level, int, 0);
68 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
70 /* Netif debug messages possible */
71 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
79 NETIF_MSG_TX_QUEUED | \
82 NETIF_MSG_RX_STATUS | \
88 #define EMAC_MAJOR_VERSION 6
89 #define EMAC_MINOR_VERSION 1
90 #define EMAC_MODULE_VERSION "6.1"
91 MODULE_VERSION(EMAC_MODULE_VERSION);
92 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
94 /* Configuration items */
95 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
96 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
97 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
98 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
99 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
100 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
101 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
102 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
103 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
104 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
105 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
106 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
108 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
109 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
111 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
112 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
113 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
114 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
115 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
116 #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
117 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
118 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
119 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
121 /* Buffer descriptor parameters */
122 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
123 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
125 /* EMAC register related defines */
126 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
127 #define EMAC_NUM_MULTICAST_BITS (64)
128 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
129 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
130 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
131 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
132 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
133 #define EMAC_INT_MASK_CLEAR (0xFF)
135 /* RX MBP register bit positions */
136 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
137 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
138 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
139 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
140 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
141 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
142 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
143 #define EMAC_RXMBP_PROMCH_SHIFT (16)
144 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
145 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
146 #define EMAC_RXMBP_BROADCH_SHIFT (8)
147 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
148 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
149 #define EMAC_RXMBP_MULTICH_SHIFT (0)
150 #define EMAC_RXMBP_MULTICH_MASK (0x7)
151 #define EMAC_RXMBP_CHMASK (0x7)
153 /* EMAC register definitions/bit maps used */
154 # define EMAC_MBP_RXPROMISC (0x00200000)
155 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
156 # define EMAC_MBP_RXBCAST (0x00002000)
157 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
158 # define EMAC_MBP_RXMCAST (0x00000020)
159 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
161 /* EMAC mac_control register */
162 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
163 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
164 #define EMAC_MACCONTROL_GMIIEN BIT(5)
165 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
166 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
167 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
169 /* GIGABIT MODE related bits */
170 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
171 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
173 /* EMAC mac_status register */
174 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
175 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
176 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
177 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
178 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
179 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
180 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
181 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
183 /* EMAC RX register masks */
184 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
185 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
187 /* MAC_IN_VECTOR (0x180) register bit fields */
188 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
189 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
190 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
191 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
193 /** NOTE:: For DM646x the IN_VECTOR has changed */
194 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
195 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
196 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
197 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
199 /* CPPI bit positions */
200 #define EMAC_CPPI_SOP_BIT BIT(31)
201 #define EMAC_CPPI_EOP_BIT BIT(30)
202 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
203 #define EMAC_CPPI_EOQ_BIT BIT(28)
204 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
205 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
206 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
207 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
208 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
210 /* Max hardware defines */
211 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
212 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
214 /* EMAC Peripheral Device Register Memory Layout structure */
215 #define EMAC_TXIDVER 0x0
216 #define EMAC_TXCONTROL 0x4
217 #define EMAC_TXTEARDOWN 0x8
218 #define EMAC_RXIDVER 0x10
219 #define EMAC_RXCONTROL 0x14
220 #define EMAC_RXTEARDOWN 0x18
221 #define EMAC_TXINTSTATRAW 0x80
222 #define EMAC_TXINTSTATMASKED 0x84
223 #define EMAC_TXINTMASKSET 0x88
224 #define EMAC_TXINTMASKCLEAR 0x8C
225 #define EMAC_MACINVECTOR 0x90
227 #define EMAC_DM646X_MACEOIVECTOR 0x94
229 #define EMAC_RXINTSTATRAW 0xA0
230 #define EMAC_RXINTSTATMASKED 0xA4
231 #define EMAC_RXINTMASKSET 0xA8
232 #define EMAC_RXINTMASKCLEAR 0xAC
233 #define EMAC_MACINTSTATRAW 0xB0
234 #define EMAC_MACINTSTATMASKED 0xB4
235 #define EMAC_MACINTMASKSET 0xB8
236 #define EMAC_MACINTMASKCLEAR 0xBC
238 #define EMAC_RXMBPENABLE 0x100
239 #define EMAC_RXUNICASTSET 0x104
240 #define EMAC_RXUNICASTCLEAR 0x108
241 #define EMAC_RXMAXLEN 0x10C
242 #define EMAC_RXBUFFEROFFSET 0x110
243 #define EMAC_RXFILTERLOWTHRESH 0x114
245 #define EMAC_MACCONTROL 0x160
246 #define EMAC_MACSTATUS 0x164
247 #define EMAC_EMCONTROL 0x168
248 #define EMAC_FIFOCONTROL 0x16C
249 #define EMAC_MACCONFIG 0x170
250 #define EMAC_SOFTRESET 0x174
251 #define EMAC_MACSRCADDRLO 0x1D0
252 #define EMAC_MACSRCADDRHI 0x1D4
253 #define EMAC_MACHASH1 0x1D8
254 #define EMAC_MACHASH2 0x1DC
255 #define EMAC_MACADDRLO 0x500
256 #define EMAC_MACADDRHI 0x504
257 #define EMAC_MACINDEX 0x508
259 /* EMAC HDP and Completion registors */
260 #define EMAC_TXHDP(ch) (0x600 + (ch * 4))
261 #define EMAC_RXHDP(ch) (0x620 + (ch * 4))
262 #define EMAC_TXCP(ch) (0x640 + (ch * 4))
263 #define EMAC_RXCP(ch) (0x660 + (ch * 4))
265 /* EMAC statistics registers */
266 #define EMAC_RXGOODFRAMES 0x200
267 #define EMAC_RXBCASTFRAMES 0x204
268 #define EMAC_RXMCASTFRAMES 0x208
269 #define EMAC_RXPAUSEFRAMES 0x20C
270 #define EMAC_RXCRCERRORS 0x210
271 #define EMAC_RXALIGNCODEERRORS 0x214
272 #define EMAC_RXOVERSIZED 0x218
273 #define EMAC_RXJABBER 0x21C
274 #define EMAC_RXUNDERSIZED 0x220
275 #define EMAC_RXFRAGMENTS 0x224
276 #define EMAC_RXFILTERED 0x228
277 #define EMAC_RXQOSFILTERED 0x22C
278 #define EMAC_RXOCTETS 0x230
279 #define EMAC_TXGOODFRAMES 0x234
280 #define EMAC_TXBCASTFRAMES 0x238
281 #define EMAC_TXMCASTFRAMES 0x23C
282 #define EMAC_TXPAUSEFRAMES 0x240
283 #define EMAC_TXDEFERRED 0x244
284 #define EMAC_TXCOLLISION 0x248
285 #define EMAC_TXSINGLECOLL 0x24C
286 #define EMAC_TXMULTICOLL 0x250
287 #define EMAC_TXEXCESSIVECOLL 0x254
288 #define EMAC_TXLATECOLL 0x258
289 #define EMAC_TXUNDERRUN 0x25C
290 #define EMAC_TXCARRIERSENSE 0x260
291 #define EMAC_TXOCTETS 0x264
292 #define EMAC_NETOCTETS 0x280
293 #define EMAC_RXSOFOVERRUNS 0x284
294 #define EMAC_RXMOFOVERRUNS 0x288
295 #define EMAC_RXDMAOVERRUNS 0x28C
297 /* EMAC DM644x control registers */
298 #define EMAC_CTRL_EWCTL (0x4)
299 #define EMAC_CTRL_EWINTTCNT (0x8)
301 /* EMAC DM644x control module masks */
302 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
303 #define EMAC_DM644X_INTMIN_INTVL 0x1
304 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
306 /* EMAC MDIO related */
307 /* Mask & Control defines */
308 #define MDIO_CONTROL_CLKDIV (0xFF)
309 #define MDIO_CONTROL_ENABLE BIT(30)
310 #define MDIO_USERACCESS_GO BIT(31)
311 #define MDIO_USERACCESS_WRITE BIT(30)
312 #define MDIO_USERACCESS_READ (0)
313 #define MDIO_USERACCESS_REGADR (0x1F << 21)
314 #define MDIO_USERACCESS_PHYADR (0x1F << 16)
315 #define MDIO_USERACCESS_DATA (0xFFFF)
316 #define MDIO_USERPHYSEL_LINKSEL BIT(7)
317 #define MDIO_VER_MODID (0xFFFF << 16)
318 #define MDIO_VER_REVMAJ (0xFF << 8)
319 #define MDIO_VER_REVMIN (0xFF)
321 #define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
322 #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
323 #define MDIO_CONTROL (0x04)
325 /* EMAC DM646X control module registers */
326 #define EMAC_DM646X_CMINTCTRL 0x0C
327 #define EMAC_DM646X_CMRXINTEN 0x14
328 #define EMAC_DM646X_CMTXINTEN 0x18
329 #define EMAC_DM646X_CMRXINTMAX 0x70
330 #define EMAC_DM646X_CMTXINTMAX 0x74
332 /* EMAC DM646X control module masks */
333 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
334 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
335 #define EMAC_DM646X_CMINTMAX_CNT 63
336 #define EMAC_DM646X_CMINTMIN_CNT 2
337 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
338 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
341 /* EMAC EOI codes for C0 */
342 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
343 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
345 /* EMAC Stats Clear Mask */
346 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
348 /** net_buf_obj: EMAC network bufferdata structure
350 * EMAC network buffer data structure
352 struct emac_netbufobj {
358 /** net_pkt_obj: EMAC network packet data structure
360 * EMAC network packet data structure - supports buffer list (for future)
362 struct emac_netpktobj {
363 void *pkt_token; /* data token may hold tx/rx chan id */
364 struct emac_netbufobj *buf_list; /* array of network buffer objects */
369 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
371 * EMAC TX Buffer descriptor data structure
377 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
378 struct emac_tx_bd __iomem *next;
382 /** emac_txch: EMAC TX Channel data structure
384 * EMAC TX Channel data structure
393 void __iomem *bd_mem;
394 struct emac_tx_bd __iomem *bd_pool_head;
395 struct emac_tx_bd __iomem *active_queue_head;
396 struct emac_tx_bd __iomem *active_queue_tail;
397 struct emac_tx_bd __iomem *last_hw_bdprocessed;
399 u32 teardown_pending;
403 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
404 u32 mis_queued_packets;
406 u32 end_of_queue_add;
408 u32 no_active_pkts; /* IRQ when there were no packets to process */
409 u32 active_queue_count;
412 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
414 * EMAC RX Buffer descriptor data structure
421 struct emac_rx_bd __iomem *next;
426 /** emac_rxch: EMAC RX Channel data structure
428 * EMAC RX Channel data structure
431 /* configuration info */
439 void __iomem *bd_mem;
440 struct emac_rx_bd __iomem *bd_pool_head;
441 struct emac_rx_bd __iomem *active_queue_head;
442 struct emac_rx_bd __iomem *active_queue_tail;
444 u32 teardown_pending;
446 /* packet and buffer objects */
447 struct emac_netpktobj pkt_queue;
448 struct emac_netbufobj buf_queue;
451 u32 proc_count; /* number of times emac_rx_bdproc is called */
455 u32 out_of_rx_buffers;
457 u32 end_of_queue_add;
459 u32 mis_queued_packets;
462 /* emac_priv: EMAC private data structure
464 * EMAC adapter private data structure
468 struct net_device *ndev;
469 struct platform_device *pdev;
470 struct napi_struct napi;
474 void __iomem *remap_addr;
476 void __iomem *emac_base;
477 void __iomem *ctrl_base;
478 void __iomem *emac_ctrl_ram;
481 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
482 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
483 u32 link; /* 1=link on, 0=link off */
484 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
485 u32 duplex; /* Link duplex: 0=Half, 1=Full */
494 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
496 /* periodic timer required for MDIO polling */
497 struct timer_list periodic_timer;
501 /* mii_bus,phy members */
502 struct mii_bus *mii_bus;
503 struct phy_device *phydev;
505 /*platform specific members*/
506 void (*int_enable) (void);
507 void (*int_disable) (void);
510 /* clock frequency for EMAC */
511 static struct clk *emac_clk;
512 static unsigned long emac_bus_frequency;
513 static unsigned long mdio_max_freq;
515 #define emac_virt_to_phys(addr, priv) \
516 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
519 /* Cache macros - Packet buffers would be from skb pool which is cached */
520 #define EMAC_VIRT_NOCACHE(addr) (addr)
522 /* DM644x does not have BD's in cached memory - so no cache functions */
523 #define BD_CACHE_INVALIDATE(addr, size)
524 #define BD_CACHE_WRITEBACK(addr, size)
525 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
527 /* EMAC TX Host Error description strings */
528 static char *emac_txhost_errcodes[16] = {
529 "No error", "SOP error", "Ownership bit not set in SOP buffer",
530 "Zero Next Buffer Descriptor Pointer Without EOP",
531 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
532 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
533 "Reserved", "Reserved", "Reserved", "Reserved"
536 /* EMAC RX Host Error description strings */
537 static char *emac_rxhost_errcodes[16] = {
538 "No error", "Reserved", "Ownership bit not set in input buffer",
539 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
540 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
541 "Reserved", "Reserved", "Reserved", "Reserved"
545 #define emac_read(reg) ioread32(priv->emac_base + (reg))
546 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
548 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
549 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
551 #define emac_mdio_read(reg) ioread32(bus->priv + (reg))
552 #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
555 * emac_dump_regs: Dump important EMAC registers to debug terminal
556 * @priv: The DaVinci EMAC private adapter structure
558 * Executes ethtool set cmd & sets phy mode
561 static void emac_dump_regs(struct emac_priv *priv)
563 struct device *emac_dev = &priv->ndev->dev;
565 /* Print important registers in EMAC */
566 dev_info(emac_dev, "EMAC Basic registers\n");
567 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
568 emac_ctrl_read(EMAC_CTRL_EWCTL),
569 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
570 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
571 emac_read(EMAC_TXIDVER),
572 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
573 emac_read(EMAC_RXIDVER),
574 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
575 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
576 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
577 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
578 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
579 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
580 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
581 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
582 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
583 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
584 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
585 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
586 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
587 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
588 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
589 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
590 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
591 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
592 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
593 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
594 dev_info(emac_dev, "EMAC Statistics\n");
595 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
596 emac_read(EMAC_RXGOODFRAMES));
597 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
598 emac_read(EMAC_RXBCASTFRAMES));
599 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
600 emac_read(EMAC_RXMCASTFRAMES));
601 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
602 emac_read(EMAC_RXPAUSEFRAMES));
603 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
604 emac_read(EMAC_RXCRCERRORS));
605 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
606 emac_read(EMAC_RXALIGNCODEERRORS));
607 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
608 emac_read(EMAC_RXOVERSIZED));
609 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
610 emac_read(EMAC_RXJABBER));
611 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
612 emac_read(EMAC_RXUNDERSIZED));
613 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
614 emac_read(EMAC_RXFRAGMENTS));
615 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
616 emac_read(EMAC_RXFILTERED));
617 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
618 emac_read(EMAC_RXQOSFILTERED));
619 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
620 emac_read(EMAC_RXOCTETS));
621 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
622 emac_read(EMAC_TXGOODFRAMES));
623 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
624 emac_read(EMAC_TXBCASTFRAMES));
625 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
626 emac_read(EMAC_TXMCASTFRAMES));
627 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
628 emac_read(EMAC_TXPAUSEFRAMES));
629 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
630 emac_read(EMAC_TXDEFERRED));
631 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
632 emac_read(EMAC_TXCOLLISION));
633 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
634 emac_read(EMAC_TXSINGLECOLL));
635 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
636 emac_read(EMAC_TXMULTICOLL));
637 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
638 emac_read(EMAC_TXEXCESSIVECOLL));
639 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
640 emac_read(EMAC_TXLATECOLL));
641 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
642 emac_read(EMAC_TXUNDERRUN));
643 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
644 emac_read(EMAC_TXCARRIERSENSE));
645 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
646 emac_read(EMAC_TXOCTETS));
647 dev_info(emac_dev, "EMAC: net_octets:%d\n",
648 emac_read(EMAC_NETOCTETS));
649 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
650 emac_read(EMAC_RXSOFOVERRUNS));
651 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
652 emac_read(EMAC_RXMOFOVERRUNS));
653 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
654 emac_read(EMAC_RXDMAOVERRUNS));
657 /*************************************************************************
658 * EMAC MDIO/Phy Functionality
659 *************************************************************************/
661 * emac_get_drvinfo: Get EMAC driver information
662 * @ndev: The DaVinci EMAC network adapter
663 * @info: ethtool info structure containing name and version
665 * Returns EMAC driver information (name and version)
668 static void emac_get_drvinfo(struct net_device *ndev,
669 struct ethtool_drvinfo *info)
671 strcpy(info->driver, emac_version_string);
672 strcpy(info->version, EMAC_MODULE_VERSION);
676 * emac_get_settings: Get EMAC settings
677 * @ndev: The DaVinci EMAC network adapter
678 * @ecmd: ethtool command
680 * Executes ethool get command
683 static int emac_get_settings(struct net_device *ndev,
684 struct ethtool_cmd *ecmd)
686 struct emac_priv *priv = netdev_priv(ndev);
688 return phy_ethtool_gset(priv->phydev, ecmd);
695 * emac_set_settings: Set EMAC settings
696 * @ndev: The DaVinci EMAC network adapter
697 * @ecmd: ethtool command
699 * Executes ethool set command
702 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
704 struct emac_priv *priv = netdev_priv(ndev);
706 return phy_ethtool_sset(priv->phydev, ecmd);
713 * emac_get_coalesce : Get interrupt coalesce settings for this device
714 * @ndev : The DaVinci EMAC network adapter
715 * @coal : ethtool coalesce settings structure
717 * Fetch the current interrupt coalesce settings
720 static int emac_get_coalesce(struct net_device *ndev,
721 struct ethtool_coalesce *coal)
723 struct emac_priv *priv = netdev_priv(ndev);
725 coal->rx_coalesce_usecs = priv->coal_intvl;
731 * emac_set_coalesce : Set interrupt coalesce settings for this device
732 * @ndev : The DaVinci EMAC network adapter
733 * @coal : ethtool coalesce settings structure
735 * Set interrupt coalesce parameters
738 static int emac_set_coalesce(struct net_device *ndev,
739 struct ethtool_coalesce *coal)
741 struct emac_priv *priv = netdev_priv(ndev);
742 u32 int_ctrl, num_interrupts = 0;
743 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
745 if (!coal->rx_coalesce_usecs)
748 coal_intvl = coal->rx_coalesce_usecs;
750 switch (priv->version) {
752 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
753 prescale = priv->bus_freq_mhz * 4;
755 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
756 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
758 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
760 * Interrupt pacer works with 4us Pulse, we can
761 * throttle further by dilating the 4us pulse.
763 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
765 if (addnl_dvdr > 1) {
766 prescale *= addnl_dvdr;
767 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
769 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
773 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
777 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
779 int_ctrl |= EMAC_DM646X_INTPACEEN;
780 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
781 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
782 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
784 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
785 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
789 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
790 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
791 prescale = coal_intvl * priv->bus_freq_mhz;
792 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
793 prescale = EMAC_DM644X_EWINTCNT_MASK;
794 coal_intvl = prescale / priv->bus_freq_mhz;
796 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
801 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
802 priv->coal_intvl = coal_intvl;
810 * ethtool_ops: DaVinci EMAC Ethtool structure
812 * Ethtool support for EMAC adapter
815 static const struct ethtool_ops ethtool_ops = {
816 .get_drvinfo = emac_get_drvinfo,
817 .get_settings = emac_get_settings,
818 .set_settings = emac_set_settings,
819 .get_link = ethtool_op_get_link,
820 .get_coalesce = emac_get_coalesce,
821 .set_coalesce = emac_set_coalesce,
825 * emac_update_phystatus: Update Phy status
826 * @priv: The DaVinci EMAC private adapter structure
828 * Updates phy status and takes action for network queue if required
829 * based upon link status
832 static void emac_update_phystatus(struct emac_priv *priv)
837 struct net_device *ndev = priv->ndev;
839 mac_control = emac_read(EMAC_MACCONTROL);
840 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
841 DUPLEX_FULL : DUPLEX_HALF;
843 new_duplex = priv->phydev->duplex;
845 new_duplex = DUPLEX_FULL;
847 /* We get called only if link has changed (speed/duplex/status) */
848 if ((priv->link) && (new_duplex != cur_duplex)) {
849 priv->duplex = new_duplex;
850 if (DUPLEX_FULL == priv->duplex)
851 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
853 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
856 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
857 mac_control = emac_read(EMAC_MACCONTROL);
858 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
859 EMAC_DM646X_MACCONTORL_GIGFORCE);
861 /* Clear the GIG bit and GIGFORCE bit */
862 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
863 EMAC_DM646X_MACCONTORL_GIG);
865 if (priv->rmii_en && (priv->speed == SPEED_100))
866 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
868 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
871 /* Update mac_control if changed */
872 emac_write(EMAC_MACCONTROL, mac_control);
876 if (!netif_carrier_ok(ndev))
877 netif_carrier_on(ndev);
878 /* reactivate the transmit queue if it is stopped */
879 if (netif_running(ndev) && netif_queue_stopped(ndev))
880 netif_wake_queue(ndev);
883 if (netif_carrier_ok(ndev))
884 netif_carrier_off(ndev);
885 if (!netif_queue_stopped(ndev))
886 netif_stop_queue(ndev);
891 * hash_get: Calculate hash value from mac address
892 * @addr: mac address to delete from hash table
894 * Calculates hash value from mac address
897 static u32 hash_get(u8 *addr)
904 for (cnt = 0; cnt < 2; cnt++) {
906 hash ^= (tmpval >> 2) ^ (tmpval << 4);
908 hash ^= (tmpval >> 4) ^ (tmpval << 2);
910 hash ^= (tmpval >> 6) ^ (tmpval);
917 * hash_add: Hash function to add mac addr from hash table
918 * @priv: The DaVinci EMAC private adapter structure
919 * mac_addr: mac address to delete from hash table
921 * Adds mac address to the internal hash table
924 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
926 struct device *emac_dev = &priv->ndev->dev;
929 u32 hash_value = hash_get(mac_addr);
931 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
932 if (netif_msg_drv(priv)) {
933 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
934 "Hash %08x, should not be greater than %08x",
935 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
940 /* set the hash bit only if not previously set */
941 if (priv->multicast_hash_cnt[hash_value] == 0) {
942 rc = 1; /* hash value changed */
943 if (hash_value < 32) {
944 hash_bit = BIT(hash_value);
945 priv->mac_hash1 |= hash_bit;
947 hash_bit = BIT((hash_value - 32));
948 priv->mac_hash2 |= hash_bit;
952 /* incr counter for num of mcast addr's mapped to "this" hash bit */
953 ++priv->multicast_hash_cnt[hash_value];
959 * hash_del: Hash function to delete mac addr from hash table
960 * @priv: The DaVinci EMAC private adapter structure
961 * mac_addr: mac address to delete from hash table
963 * Removes mac address from the internal hash table
966 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
971 hash_value = hash_get(mac_addr);
972 if (priv->multicast_hash_cnt[hash_value] > 0) {
973 /* dec cntr for num of mcast addr's mapped to this hash bit */
974 --priv->multicast_hash_cnt[hash_value];
977 /* if counter still > 0, at least one multicast address refers
978 * to this hash bit. so return 0 */
979 if (priv->multicast_hash_cnt[hash_value] > 0)
982 if (hash_value < 32) {
983 hash_bit = BIT(hash_value);
984 priv->mac_hash1 &= ~hash_bit;
986 hash_bit = BIT((hash_value - 32));
987 priv->mac_hash2 &= ~hash_bit;
990 /* return 1 to indicate change in mac_hash registers reqd */
994 /* EMAC multicast operation */
995 #define EMAC_MULTICAST_ADD 0
996 #define EMAC_MULTICAST_DEL 1
997 #define EMAC_ALL_MULTI_SET 2
998 #define EMAC_ALL_MULTI_CLR 3
1001 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
1002 * @priv: The DaVinci EMAC private adapter structure
1003 * @action: multicast operation to perform
1004 * mac_addr: mac address to set
1006 * Set multicast addresses in EMAC adapter - internal function
1009 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
1011 struct device *emac_dev = &priv->ndev->dev;
1015 case EMAC_MULTICAST_ADD:
1016 update = hash_add(priv, mac_addr);
1018 case EMAC_MULTICAST_DEL:
1019 update = hash_del(priv, mac_addr);
1021 case EMAC_ALL_MULTI_SET:
1023 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
1024 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
1026 case EMAC_ALL_MULTI_CLR:
1028 priv->mac_hash1 = 0;
1029 priv->mac_hash2 = 0;
1030 memset(&(priv->multicast_hash_cnt[0]), 0,
1031 sizeof(priv->multicast_hash_cnt[0]) *
1032 EMAC_NUM_MULTICAST_BITS);
1035 if (netif_msg_drv(priv))
1036 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
1037 ": bad operation %d", action);
1041 /* write to the hardware only if the register status chances */
1043 emac_write(EMAC_MACHASH1, priv->mac_hash1);
1044 emac_write(EMAC_MACHASH2, priv->mac_hash2);
1049 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
1050 * @ndev: The DaVinci EMAC network adapter
1052 * Set multicast addresses in EMAC adapter
1055 static void emac_dev_mcast_set(struct net_device *ndev)
1058 struct emac_priv *priv = netdev_priv(ndev);
1060 mbp_enable = emac_read(EMAC_RXMBPENABLE);
1061 if (ndev->flags & IFF_PROMISC) {
1062 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
1063 mbp_enable |= (EMAC_MBP_RXPROMISC);
1065 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
1066 if ((ndev->flags & IFF_ALLMULTI) ||
1067 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
1068 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
1069 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
1071 if (!netdev_mc_empty(ndev)) {
1072 struct netdev_hw_addr *ha;
1074 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
1075 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
1076 /* program multicast address list into EMAC hardware */
1077 netdev_for_each_mc_addr(ha, ndev) {
1078 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
1082 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
1083 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
1086 /* Set mbp config register */
1087 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1090 /*************************************************************************
1091 * EMAC Hardware manipulation
1092 *************************************************************************/
1095 * emac_int_disable: Disable EMAC module interrupt (from adapter)
1096 * @priv: The DaVinci EMAC private adapter structure
1098 * Disable EMAC interrupt on the adapter
1101 static void emac_int_disable(struct emac_priv *priv)
1103 if (priv->version == EMAC_VERSION_2) {
1104 unsigned long flags;
1106 local_irq_save(flags);
1108 /* Program C0_Int_En to zero to turn off
1109 * interrupts to the CPU */
1110 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1111 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1112 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1113 if (priv->int_disable)
1114 priv->int_disable();
1116 local_irq_restore(flags);
1119 /* Set DM644x control registers for interrupt control */
1120 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1125 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1126 * @priv: The DaVinci EMAC private adapter structure
1128 * Enable EMAC interrupt on the adapter
1131 static void emac_int_enable(struct emac_priv *priv)
1133 if (priv->version == EMAC_VERSION_2) {
1134 if (priv->int_enable)
1137 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1138 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1140 /* In addition to turning on interrupt Enable, we need
1141 * ack by writing appropriate values to the EOI
1144 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1146 /* ack rxen only then a new pulse will be generated */
1147 emac_write(EMAC_DM646X_MACEOIVECTOR,
1148 EMAC_DM646X_MAC_EOI_C0_RXEN);
1150 /* ack txen- only then a new pulse will be generated */
1151 emac_write(EMAC_DM646X_MACEOIVECTOR,
1152 EMAC_DM646X_MAC_EOI_C0_TXEN);
1155 /* Set DM644x control registers for interrupt control */
1156 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1161 * emac_irq: EMAC interrupt handler
1162 * @irq: interrupt number
1163 * @dev_id: EMAC network adapter data structure ptr
1165 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1166 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1168 * Returns interrupt handled condition
1170 static irqreturn_t emac_irq(int irq, void *dev_id)
1172 struct net_device *ndev = (struct net_device *)dev_id;
1173 struct emac_priv *priv = netdev_priv(ndev);
1176 if (likely(netif_running(priv->ndev))) {
1177 emac_int_disable(priv);
1178 napi_schedule(&priv->napi);
1180 /* we are closing down, so dont process anything */
1185 /** EMAC on-chip buffer descriptor memory
1187 * WARNING: Please note that the on chip memory is used for both TX and RX
1188 * buffer descriptor queues and is equally divided between TX and RX desc's
1189 * If the number of TX or RX descriptors change this memory pointers need
1190 * to be adjusted. If external memory is allocated then these pointers can
1191 * pointer to the memory
1194 #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1195 #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1196 (((priv)->ctrl_ram_size) >> 1))
1199 * emac_init_txch: TX channel initialization
1200 * @priv: The DaVinci EMAC private adapter structure
1201 * @ch: RX channel number
1203 * Called during device init to setup a TX channel (allocate buffer desc
1204 * create free pool and keep ready for transmission
1206 * Returns success(0) or mem alloc failures error code
1208 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1210 struct device *emac_dev = &priv->ndev->dev;
1213 struct emac_tx_bd __iomem *curr_bd;
1214 struct emac_txch *txch = NULL;
1216 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1218 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1221 priv->txch[ch] = txch;
1222 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1223 txch->active_queue_head = NULL;
1224 txch->active_queue_tail = NULL;
1225 txch->queue_active = 0;
1226 txch->teardown_pending = 0;
1228 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1229 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1231 if (NULL == txch->tx_complete) {
1232 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1237 /* allocate buffer descriptor pool align every BD on four word
1238 * boundry for future requirements */
1239 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1240 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1241 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1243 /* alloc TX BD memory */
1244 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1245 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1247 /* initialize the BD linked list */
1248 mem = (void __force __iomem *)
1249 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1250 txch->bd_pool_head = NULL;
1251 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1252 curr_bd = mem + (cnt * bd_size);
1253 curr_bd->next = txch->bd_pool_head;
1254 txch->bd_pool_head = curr_bd;
1257 /* reset statistics counters */
1258 txch->out_of_tx_bd = 0;
1259 txch->no_active_pkts = 0;
1260 txch->active_queue_count = 0;
1266 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1267 * @priv: The DaVinci EMAC private adapter structure
1268 * @ch: TX channel number
1270 * Called to clean up TX channel resources
1273 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1275 struct emac_txch *txch = priv->txch[ch];
1279 txch->bd_mem = NULL;
1280 kfree(txch->tx_complete);
1282 priv->txch[ch] = NULL;
1287 * emac_net_tx_complete: TX packet completion function
1288 * @priv: The DaVinci EMAC private adapter structure
1289 * @net_data_tokens: packet token - skb pointer
1290 * @num_tokens: number of skb's to free
1291 * @ch: TX channel number
1293 * Frees the skb once packet is transmitted
1296 static int emac_net_tx_complete(struct emac_priv *priv,
1297 void **net_data_tokens,
1298 int num_tokens, u32 ch)
1300 struct net_device *ndev = priv->ndev;
1303 if (unlikely(num_tokens && netif_queue_stopped(dev)))
1304 netif_start_queue(dev);
1305 for (cnt = 0; cnt < num_tokens; cnt++) {
1306 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1309 ndev->stats.tx_packets++;
1310 ndev->stats.tx_bytes += skb->len;
1311 dev_kfree_skb_any(skb);
1317 * emac_txch_teardown: TX channel teardown
1318 * @priv: The DaVinci EMAC private adapter structure
1319 * @ch: TX channel number
1321 * Called to teardown TX channel
1324 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1326 struct device *emac_dev = &priv->ndev->dev;
1327 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1328 struct emac_txch *txch = priv->txch[ch];
1329 struct emac_tx_bd __iomem *curr_bd;
1331 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1332 EMAC_TEARDOWN_VALUE) {
1333 /* wait till tx teardown complete */
1334 cpu_relax(); /* TODO: check if this helps ... */
1336 if (0 == teardown_cnt) {
1337 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1341 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1343 /* process sent packets and return skb's to upper layer */
1344 if (1 == txch->queue_active) {
1345 curr_bd = txch->active_queue_head;
1346 while (curr_bd != NULL) {
1347 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1348 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1351 emac_net_tx_complete(priv, (void __force *)
1352 &curr_bd->buf_token, 1, ch);
1353 if (curr_bd != txch->active_queue_tail)
1354 curr_bd = curr_bd->next;
1358 txch->bd_pool_head = txch->active_queue_head;
1359 txch->active_queue_head =
1360 txch->active_queue_tail = NULL;
1365 * emac_stop_txch: Stop TX channel operation
1366 * @priv: The DaVinci EMAC private adapter structure
1367 * @ch: TX channel number
1369 * Called to stop TX channel operation
1372 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1374 struct emac_txch *txch = priv->txch[ch];
1377 txch->teardown_pending = 1;
1378 emac_write(EMAC_TXTEARDOWN, 0);
1379 emac_txch_teardown(priv, ch);
1380 txch->teardown_pending = 0;
1381 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1386 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1387 * @priv: The DaVinci EMAC private adapter structure
1388 * @ch: TX channel number to process buffer descriptors for
1389 * @budget: number of packets allowed to process
1390 * @pending: indication to caller that packets are pending to process
1392 * Processes TX buffer descriptors after packets are transmitted - checks
1393 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1394 * the SKB buffer. Only "budget" number of packets are processed and
1395 * indication of pending packets provided to the caller
1397 * Returns number of packets processed
1399 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1401 struct device *emac_dev = &priv->ndev->dev;
1402 unsigned long flags;
1404 u32 pkts_processed = 0;
1405 u32 tx_complete_cnt = 0;
1406 struct emac_tx_bd __iomem *curr_bd;
1407 struct emac_txch *txch = priv->txch[ch];
1408 u32 *tx_complete_ptr = txch->tx_complete;
1410 if (unlikely(1 == txch->teardown_pending)) {
1411 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1412 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1413 "teardown pending\n");
1415 return 0; /* dont handle any pkt completions */
1419 spin_lock_irqsave(&priv->tx_lock, flags);
1420 curr_bd = txch->active_queue_head;
1421 if (NULL == curr_bd) {
1422 emac_write(EMAC_TXCP(ch),
1423 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1424 txch->no_active_pkts++;
1425 spin_unlock_irqrestore(&priv->tx_lock, flags);
1428 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1429 frame_status = curr_bd->mode;
1431 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1432 (pkts_processed < budget)) {
1433 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1434 txch->active_queue_head = curr_bd->next;
1435 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1436 if (curr_bd->next) { /* misqueued packet */
1437 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1438 ++txch->mis_queued_packets;
1440 txch->queue_active = 0; /* end of queue */
1444 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1445 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1448 *tx_complete_ptr = (u32) curr_bd->buf_token;
1451 curr_bd->next = txch->bd_pool_head;
1452 txch->bd_pool_head = curr_bd;
1453 --txch->active_queue_count;
1455 txch->last_hw_bdprocessed = curr_bd;
1456 curr_bd = txch->active_queue_head;
1458 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1459 frame_status = curr_bd->mode;
1461 } /* end of pkt processing loop */
1463 emac_net_tx_complete(priv,
1464 (void *)&txch->tx_complete[0],
1465 tx_complete_cnt, ch);
1466 spin_unlock_irqrestore(&priv->tx_lock, flags);
1467 return pkts_processed;
1470 #define EMAC_ERR_TX_OUT_OF_BD -1
1473 * emac_send: EMAC Transmit function (internal)
1474 * @priv: The DaVinci EMAC private adapter structure
1475 * @pkt: packet pointer (contains skb ptr)
1476 * @ch: TX channel number
1478 * Called by the transmit function to queue the packet in EMAC hardware queue
1480 * Returns success(0) or error code (typically out of desc's)
1482 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1484 unsigned long flags;
1485 struct emac_tx_bd __iomem *curr_bd;
1486 struct emac_txch *txch;
1487 struct emac_netbufobj *buf_list;
1489 txch = priv->txch[ch];
1490 buf_list = pkt->buf_list; /* get handle to the buffer array */
1492 /* check packet size and pad if short */
1493 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1494 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1495 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1498 spin_lock_irqsave(&priv->tx_lock, flags);
1499 curr_bd = txch->bd_pool_head;
1500 if (curr_bd == NULL) {
1501 txch->out_of_tx_bd++;
1502 spin_unlock_irqrestore(&priv->tx_lock, flags);
1503 return EMAC_ERR_TX_OUT_OF_BD;
1506 txch->bd_pool_head = curr_bd->next;
1507 curr_bd->buf_token = buf_list->buf_token;
1508 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr,
1509 buf_list->length, DMA_TO_DEVICE);
1510 curr_bd->off_b_len = buf_list->length;
1511 curr_bd->h_next = 0;
1512 curr_bd->next = NULL;
1513 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1514 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1516 /* flush the packet from cache if write back cache is present */
1517 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1519 /* send the packet */
1520 if (txch->active_queue_head == NULL) {
1521 txch->active_queue_head = curr_bd;
1522 txch->active_queue_tail = curr_bd;
1523 if (1 != txch->queue_active) {
1524 emac_write(EMAC_TXHDP(ch),
1525 emac_virt_to_phys(curr_bd, priv));
1526 txch->queue_active = 1;
1528 ++txch->queue_reinit;
1530 register struct emac_tx_bd __iomem *tail_bd;
1531 register u32 frame_status;
1533 tail_bd = txch->active_queue_tail;
1534 tail_bd->next = curr_bd;
1535 txch->active_queue_tail = curr_bd;
1536 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1537 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1538 frame_status = tail_bd->mode;
1539 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1540 emac_write(EMAC_TXHDP(ch),
1541 emac_virt_to_phys(curr_bd, priv));
1542 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1543 tail_bd->mode = frame_status;
1544 ++txch->end_of_queue_add;
1547 txch->active_queue_count++;
1548 spin_unlock_irqrestore(&priv->tx_lock, flags);
1553 * emac_dev_xmit: EMAC Transmit function
1555 * @ndev: The DaVinci EMAC network adapter
1557 * Called by the system to transmit a packet - we queue the packet in
1558 * EMAC hardware transmit queue
1560 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1562 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1564 struct device *emac_dev = &ndev->dev;
1566 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1567 struct emac_netpktobj tx_packet; /* packet object */
1568 struct emac_priv *priv = netdev_priv(ndev);
1570 /* If no link, return */
1571 if (unlikely(!priv->link)) {
1572 if (netif_msg_tx_err(priv) && net_ratelimit())
1573 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1574 return NETDEV_TX_BUSY;
1577 /* Build the buffer and packet objects - Since only single fragment is
1578 * supported, need not set length and token in both packet & object.
1579 * Doing so for completeness sake & to show that this needs to be done
1580 * in multifragment case
1582 tx_packet.buf_list = &tx_buf;
1583 tx_packet.num_bufs = 1; /* only single fragment supported */
1584 tx_packet.pkt_length = skb->len;
1585 tx_packet.pkt_token = (void *)skb;
1586 tx_buf.length = skb->len;
1587 tx_buf.buf_token = (void *)skb;
1588 tx_buf.data_ptr = skb->data;
1589 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1590 if (unlikely(ret_code != 0)) {
1591 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1592 if (netif_msg_tx_err(priv) && net_ratelimit())
1593 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1594 " err. Out of TX BD's");
1595 netif_stop_queue(priv->ndev);
1597 ndev->stats.tx_dropped++;
1598 return NETDEV_TX_BUSY;
1601 return NETDEV_TX_OK;
1605 * emac_dev_tx_timeout: EMAC Transmit timeout function
1606 * @ndev: The DaVinci EMAC network adapter
1608 * Called when system detects that a skb timeout period has expired
1609 * potentially due to a fault in the adapter in not being able to send
1610 * it out on the wire. We teardown the TX channel assuming a hardware
1611 * error and re-initialize the TX channel for hardware operation
1614 static void emac_dev_tx_timeout(struct net_device *ndev)
1616 struct emac_priv *priv = netdev_priv(ndev);
1617 struct device *emac_dev = &ndev->dev;
1619 if (netif_msg_tx_err(priv))
1620 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1622 ndev->stats.tx_errors++;
1623 emac_int_disable(priv);
1624 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1625 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1626 emac_init_txch(priv, EMAC_DEF_TX_CH);
1627 emac_write(EMAC_TXHDP(0), 0);
1628 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1629 emac_int_enable(priv);
1633 * emac_net_alloc_rx_buf: Allocate a skb for RX
1634 * @priv: The DaVinci EMAC private adapter structure
1635 * @buf_size: size of SKB data buffer to allocate
1636 * @data_token: data token returned (skb handle for storing in buffer desc)
1637 * @ch: RX channel number
1639 * Called during RX channel setup - allocates skb buffer of required size
1640 * and provides the skb handle and allocated buffer data pointer to caller
1642 * Returns skb data pointer or 0 on failure to alloc skb
1644 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1645 void **data_token, u32 ch)
1647 struct net_device *ndev = priv->ndev;
1648 struct device *emac_dev = &ndev->dev;
1649 struct sk_buff *p_skb;
1651 p_skb = dev_alloc_skb(buf_size);
1652 if (unlikely(NULL == p_skb)) {
1653 if (netif_msg_rx_err(priv) && net_ratelimit())
1654 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1658 /* set device pointer in skb and reserve space for extra bytes */
1660 skb_reserve(p_skb, NET_IP_ALIGN);
1661 *data_token = (void *) p_skb;
1666 * emac_init_rxch: RX channel initialization
1667 * @priv: The DaVinci EMAC private adapter structure
1668 * @ch: RX channel number
1669 * @param: mac address for RX channel
1671 * Called during device init to setup a RX channel (allocate buffers and
1672 * buffer descriptors, create queue and keep ready for reception
1674 * Returns success(0) or mem alloc failures error code
1676 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1678 struct device *emac_dev = &priv->ndev->dev;
1681 struct emac_rx_bd __iomem *curr_bd;
1682 struct emac_rxch *rxch = NULL;
1684 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1686 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1689 priv->rxch[ch] = rxch;
1690 rxch->buf_size = priv->rx_buf_size;
1691 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1692 rxch->queue_active = 0;
1693 rxch->teardown_pending = 0;
1695 /* save mac address */
1696 for (cnt = 0; cnt < 6; cnt++)
1697 rxch->mac_addr[cnt] = param[cnt];
1699 /* allocate buffer descriptor pool align every BD on four word
1700 * boundry for future requirements */
1701 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1702 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1703 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1704 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1705 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1706 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1708 /* allocate RX buffer and initialize the BD linked list */
1709 mem = (void __force __iomem *)
1710 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1711 rxch->active_queue_head = NULL;
1712 rxch->active_queue_tail = mem;
1713 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1714 curr_bd = mem + (cnt * bd_size);
1715 /* for future use the last parameter contains the BD ptr */
1716 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1718 (void __force **)&curr_bd->buf_token,
1720 if (curr_bd->data_ptr == NULL) {
1721 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1722 "failed for ch %d\n", ch);
1727 /* populate the hardware descriptor */
1728 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1730 curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr,
1731 rxch->buf_size, DMA_FROM_DEVICE);
1732 curr_bd->off_b_len = rxch->buf_size;
1733 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1735 /* write back to hardware memory */
1736 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1737 EMAC_BD_LENGTH_FOR_CACHE);
1738 curr_bd->next = rxch->active_queue_head;
1739 rxch->active_queue_head = curr_bd;
1742 /* At this point rxCppi->activeQueueHead points to the first
1743 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1744 points to the last RX BD
1750 * emac_rxch_teardown: RX channel teardown
1751 * @priv: The DaVinci EMAC private adapter structure
1752 * @ch: RX channel number
1754 * Called during device stop to teardown RX channel
1757 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1759 struct device *emac_dev = &priv->ndev->dev;
1760 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1762 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1763 EMAC_TEARDOWN_VALUE) {
1764 /* wait till tx teardown complete */
1765 cpu_relax(); /* TODO: check if this helps ... */
1767 if (0 == teardown_cnt) {
1768 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1772 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1776 * emac_stop_rxch: Stop RX channel operation
1777 * @priv: The DaVinci EMAC private adapter structure
1778 * @ch: RX channel number
1780 * Called during device stop to stop RX channel operation
1783 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1785 struct emac_rxch *rxch = priv->rxch[ch];
1788 rxch->teardown_pending = 1;
1789 emac_write(EMAC_RXTEARDOWN, ch);
1790 /* wait for teardown complete */
1791 emac_rxch_teardown(priv, ch);
1792 rxch->teardown_pending = 0;
1793 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1798 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1799 * @priv: The DaVinci EMAC private adapter structure
1800 * @ch: RX channel number
1802 * Called during device stop to clean up RX channel resources
1805 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1807 struct emac_rxch *rxch = priv->rxch[ch];
1808 struct emac_rx_bd __iomem *curr_bd;
1811 /* free the receive buffers previously allocated */
1812 curr_bd = rxch->active_queue_head;
1814 if (curr_bd->buf_token) {
1815 dma_unmap_single(&priv->ndev->dev,
1818 & EMAC_RX_BD_BUF_SIZE,
1821 dev_kfree_skb_any((struct sk_buff *)\
1822 curr_bd->buf_token);
1824 curr_bd = curr_bd->next;
1827 rxch->bd_mem = NULL;
1829 priv->rxch[ch] = NULL;
1834 * emac_set_type0addr: Set EMAC Type0 mac address
1835 * @priv: The DaVinci EMAC private adapter structure
1836 * @ch: RX channel number
1837 * @mac_addr: MAC address to set in device
1839 * Called internally to set Type0 mac address of the adapter (Device)
1841 * Returns success (0) or appropriate error code (none as of now)
1843 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1846 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1847 emac_write(EMAC_MACSRCADDRLO, val);
1849 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1850 (mac_addr[1] << 8) | (mac_addr[0]));
1851 emac_write(EMAC_MACSRCADDRHI, val);
1852 val = emac_read(EMAC_RXUNICASTSET);
1854 emac_write(EMAC_RXUNICASTSET, val);
1855 val = emac_read(EMAC_RXUNICASTCLEAR);
1857 emac_write(EMAC_RXUNICASTCLEAR, val);
1861 * emac_set_type1addr: Set EMAC Type1 mac address
1862 * @priv: The DaVinci EMAC private adapter structure
1863 * @ch: RX channel number
1864 * @mac_addr: MAC address to set in device
1866 * Called internally to set Type1 mac address of the adapter (Device)
1868 * Returns success (0) or appropriate error code (none as of now)
1870 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1873 emac_write(EMAC_MACINDEX, ch);
1874 val = ((mac_addr[5] << 8) | mac_addr[4]);
1875 emac_write(EMAC_MACADDRLO, val);
1876 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1877 (mac_addr[1] << 8) | (mac_addr[0]));
1878 emac_write(EMAC_MACADDRHI, val);
1879 emac_set_type0addr(priv, ch, mac_addr);
1883 * emac_set_type2addr: Set EMAC Type2 mac address
1884 * @priv: The DaVinci EMAC private adapter structure
1885 * @ch: RX channel number
1886 * @mac_addr: MAC address to set in device
1887 * @index: index into RX address entries
1888 * @match: match parameter for RX address matching logic
1890 * Called internally to set Type2 mac address of the adapter (Device)
1892 * Returns success (0) or appropriate error code (none as of now)
1894 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1895 char *mac_addr, int index, int match)
1898 emac_write(EMAC_MACINDEX, index);
1899 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1900 (mac_addr[1] << 8) | (mac_addr[0]));
1901 emac_write(EMAC_MACADDRHI, val);
1902 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1903 (match << 19) | BIT(20));
1904 emac_write(EMAC_MACADDRLO, val);
1905 emac_set_type0addr(priv, ch, mac_addr);
1909 * emac_setmac: Set mac address in the adapter (internal function)
1910 * @priv: The DaVinci EMAC private adapter structure
1911 * @ch: RX channel number
1912 * @mac_addr: MAC address to set in device
1914 * Called internally to set the mac address of the adapter (Device)
1916 * Returns success (0) or appropriate error code (none as of now)
1918 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1920 struct device *emac_dev = &priv->ndev->dev;
1922 if (priv->rx_addr_type == 0) {
1923 emac_set_type0addr(priv, ch, mac_addr);
1924 } else if (priv->rx_addr_type == 1) {
1926 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1927 emac_set_type1addr(priv, ch, mac_addr);
1928 } else if (priv->rx_addr_type == 2) {
1929 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1930 emac_set_type0addr(priv, ch, mac_addr);
1932 if (netif_msg_drv(priv))
1933 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1938 * emac_dev_setmac_addr: Set mac address in the adapter
1939 * @ndev: The DaVinci EMAC network adapter
1940 * @addr: MAC address to set in device
1942 * Called by the system to set the mac address of the adapter (Device)
1944 * Returns success (0) or appropriate error code (none as of now)
1946 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1948 struct emac_priv *priv = netdev_priv(ndev);
1949 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1950 struct device *emac_dev = &priv->ndev->dev;
1951 struct sockaddr *sa = addr;
1953 if (!is_valid_ether_addr(sa->sa_data))
1956 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1957 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1958 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1960 /* If the interface is down - rxch is NULL. */
1961 /* MAC address is configured only after the interface is enabled. */
1962 if (netif_running(ndev)) {
1963 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1964 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1967 if (netif_msg_drv(priv))
1968 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1975 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1976 * @priv: The DaVinci EMAC private adapter structure
1977 * @ch: RX channel number to process buffer descriptors for
1978 * @curr_bd: current buffer descriptor
1979 * @buffer: buffer pointer for descriptor
1980 * @buf_token: buffer token (stores skb information)
1982 * Prepares the recycled buffer descriptor and addes it to hardware
1983 * receive queue - if queue empty this descriptor becomes the head
1984 * else addes the descriptor to end of queue
1987 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1988 struct emac_rx_bd __iomem *curr_bd,
1989 char *buffer, void *buf_token)
1991 struct emac_rxch *rxch = priv->rxch[ch];
1993 /* populate the hardware descriptor */
1994 curr_bd->h_next = 0;
1995 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer,
1996 rxch->buf_size, DMA_FROM_DEVICE);
1997 curr_bd->off_b_len = rxch->buf_size;
1998 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1999 curr_bd->next = NULL;
2000 curr_bd->data_ptr = buffer;
2001 curr_bd->buf_token = buf_token;
2004 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2005 if (rxch->active_queue_head == NULL) {
2006 rxch->active_queue_head = curr_bd;
2007 rxch->active_queue_tail = curr_bd;
2008 if (0 != rxch->queue_active) {
2009 emac_write(EMAC_RXHDP(ch),
2010 emac_virt_to_phys(rxch->active_queue_head, priv));
2011 rxch->queue_active = 1;
2014 struct emac_rx_bd __iomem *tail_bd;
2017 tail_bd = rxch->active_queue_tail;
2018 rxch->active_queue_tail = curr_bd;
2019 tail_bd->next = curr_bd;
2020 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
2021 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
2022 frame_status = tail_bd->mode;
2023 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2024 emac_write(EMAC_RXHDP(ch),
2025 emac_virt_to_phys(curr_bd, priv));
2026 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
2027 tail_bd->mode = frame_status;
2028 ++rxch->end_of_queue_add;
2031 ++rxch->recycled_bd;
2035 * emac_net_rx_cb: Prepares packet and sends to upper layer
2036 * @priv: The DaVinci EMAC private adapter structure
2037 * @net_pkt_list: Network packet list (received packets)
2039 * Invalidates packet buffer memory and sends the received packet to upper
2042 * Returns success or appropriate error code (none as of now)
2044 static int emac_net_rx_cb(struct emac_priv *priv,
2045 struct emac_netpktobj *net_pkt_list)
2047 struct net_device *ndev = priv->ndev;
2048 struct sk_buff *p_skb = net_pkt_list->pkt_token;
2049 /* set length of packet */
2050 skb_put(p_skb, net_pkt_list->pkt_length);
2051 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
2052 netif_receive_skb(p_skb);
2053 ndev->stats.rx_bytes += net_pkt_list->pkt_length;
2054 ndev->stats.rx_packets++;
2059 * emac_rx_bdproc: RX buffer descriptor (packet) processing
2060 * @priv: The DaVinci EMAC private adapter structure
2061 * @ch: RX channel number to process buffer descriptors for
2062 * @budget: number of packets allowed to process
2063 * @pending: indication to caller that packets are pending to process
2065 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
2066 * descriptor, sends the receive packet to upper layer, allocates a new SKB
2067 * and recycles the buffer descriptor (requeues it in hardware RX queue).
2068 * Only "budget" number of packets are processed and indication of pending
2069 * packets provided to the caller.
2071 * Returns number of packets processed (and indication of pending packets)
2073 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
2075 unsigned long flags;
2077 u32 pkts_processed = 0;
2079 struct emac_rx_bd __iomem *curr_bd;
2080 struct emac_rx_bd __iomem *last_bd;
2081 struct emac_netpktobj *curr_pkt, pkt_obj;
2082 struct emac_netbufobj buf_obj;
2083 struct emac_netbufobj *rx_buf_obj;
2084 void *new_buf_token;
2085 struct emac_rxch *rxch = priv->rxch[ch];
2087 if (unlikely(1 == rxch->teardown_pending))
2090 spin_lock_irqsave(&priv->rx_lock, flags);
2091 pkt_obj.buf_list = &buf_obj;
2092 curr_pkt = &pkt_obj;
2093 curr_bd = rxch->active_queue_head;
2094 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2095 frame_status = curr_bd->mode;
2098 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
2099 (pkts_processed < budget)) {
2101 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
2102 &new_buf_token, EMAC_DEF_RX_CH);
2103 if (unlikely(NULL == new_buffer)) {
2104 ++rxch->out_of_rx_buffers;
2105 goto end_emac_rx_bdproc;
2108 /* populate received packet data structure */
2109 rx_buf_obj = &curr_pkt->buf_list[0];
2110 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
2111 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
2112 rx_buf_obj->buf_token = curr_bd->buf_token;
2114 dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr,
2115 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
2118 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
2119 curr_pkt->num_bufs = 1;
2120 curr_pkt->pkt_length =
2121 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
2122 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
2123 ++rxch->processed_bd;
2125 curr_bd = last_bd->next;
2126 rxch->active_queue_head = curr_bd;
2128 /* check if end of RX queue ? */
2129 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2131 ++rxch->mis_queued_packets;
2132 emac_write(EMAC_RXHDP(ch),
2133 emac_virt_to_phys(curr_bd, priv));
2135 ++rxch->end_of_queue;
2136 rxch->queue_active = 0;
2141 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2144 /* return the packet to the user - BD ptr passed in
2145 * last parameter for potential *future* use */
2146 spin_unlock_irqrestore(&priv->rx_lock, flags);
2147 emac_net_rx_cb(priv, curr_pkt);
2148 spin_lock_irqsave(&priv->rx_lock, flags);
2149 curr_bd = rxch->active_queue_head;
2151 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2152 frame_status = curr_bd->mode;
2158 spin_unlock_irqrestore(&priv->rx_lock, flags);
2159 return pkts_processed;
2163 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2164 * @priv: The DaVinci EMAC private adapter structure
2166 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2167 * for packet reception and enables device interrupts and then NAPI
2169 * Returns success (0) or appropriate error code (none right now)
2171 static int emac_hw_enable(struct emac_priv *priv)
2173 u32 ch, val, mbp_enable, mac_control;
2176 emac_write(EMAC_SOFTRESET, 1);
2177 while (emac_read(EMAC_SOFTRESET))
2180 /* Disable interrupt & Set pacing for more interrupts initially */
2181 emac_int_disable(priv);
2183 /* Full duplex enable bit set when auto negotiation happens */
2185 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2186 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2187 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2188 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2189 emac_write(EMAC_MACCONTROL, mac_control);
2192 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2193 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2194 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2195 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2196 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2197 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2198 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2199 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2200 EMAC_RXMBP_PROMCH_SHIFT) |
2201 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2202 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2203 EMAC_RXMBP_BROADCH_SHIFT) |
2204 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2205 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2206 EMAC_RXMBP_MULTICH_SHIFT));
2207 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2208 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2209 EMAC_RX_MAX_LEN_MASK));
2210 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2211 EMAC_RX_BUFFER_OFFSET_MASK));
2212 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2213 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2214 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2216 val = emac_read(EMAC_TXCONTROL);
2217 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2218 emac_write(EMAC_TXCONTROL, val);
2219 val = emac_read(EMAC_RXCONTROL);
2220 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2221 emac_write(EMAC_RXCONTROL, val);
2222 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2224 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2225 emac_write(EMAC_TXHDP(ch), 0);
2226 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2228 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2229 struct emac_rxch *rxch = priv->rxch[ch];
2230 emac_setmac(priv, ch, rxch->mac_addr);
2231 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2232 rxch->queue_active = 1;
2233 emac_write(EMAC_RXHDP(ch),
2234 emac_virt_to_phys(rxch->active_queue_head, priv));
2238 val = emac_read(EMAC_MACCONTROL);
2239 val |= (EMAC_MACCONTROL_GMIIEN);
2240 emac_write(EMAC_MACCONTROL, val);
2242 /* Enable NAPI and interrupts */
2243 napi_enable(&priv->napi);
2244 emac_int_enable(priv);
2250 * emac_poll: EMAC NAPI Poll function
2251 * @ndev: The DaVinci EMAC network adapter
2252 * @budget: Number of receive packets to process (as told by NAPI layer)
2254 * NAPI Poll function implemented to process packets as per budget. We check
2255 * the type of interrupt on the device and accordingly call the TX or RX
2256 * packet processing functions. We follow the budget for RX processing and
2257 * also put a cap on number of TX pkts processed through config param. The
2258 * NAPI schedule function is called if more packets pending.
2260 * Returns number of packets received (in most cases; else TX pkts - rarely)
2262 static int emac_poll(struct napi_struct *napi, int budget)
2265 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2266 struct net_device *ndev = priv->ndev;
2267 struct device *emac_dev = &ndev->dev;
2271 /* Check interrupt vectors and call packet processing */
2272 status = emac_read(EMAC_MACINVECTOR);
2274 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2276 if (priv->version == EMAC_VERSION_2)
2277 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2279 if (status & mask) {
2280 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2281 EMAC_DEF_TX_MAX_SERVICE);
2282 } /* TX processing */
2287 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2289 if (priv->version == EMAC_VERSION_2)
2290 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2292 if (status & mask) {
2293 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2294 } /* RX processing */
2296 if (num_pkts < budget) {
2297 napi_complete(napi);
2298 emac_int_enable(priv);
2301 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2302 if (priv->version == EMAC_VERSION_2)
2303 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2305 if (unlikely(status & mask)) {
2307 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2308 netif_stop_queue(ndev);
2309 napi_disable(&priv->napi);
2311 status = emac_read(EMAC_MACSTATUS);
2312 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2313 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2315 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2316 EMAC_MACSTATUS_TXERRCH_SHIFT);
2317 if (net_ratelimit()) {
2318 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2319 &emac_txhost_errcodes[cause][0], ch);
2322 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2323 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2325 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2326 EMAC_MACSTATUS_RXERRCH_SHIFT);
2327 if (netif_msg_hw(priv) && net_ratelimit())
2328 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2329 &emac_rxhost_errcodes[cause][0], ch);
2331 } /* Host error processing */
2336 #ifdef CONFIG_NET_POLL_CONTROLLER
2338 * emac_poll_controller: EMAC Poll controller function
2339 * @ndev: The DaVinci EMAC network adapter
2341 * Polled functionality used by netconsole and others in non interrupt mode
2344 void emac_poll_controller(struct net_device *ndev)
2346 struct emac_priv *priv = netdev_priv(ndev);
2348 emac_int_disable(priv);
2349 emac_irq(ndev->irq, ndev);
2350 emac_int_enable(priv);
2354 /* PHY/MII bus related */
2356 /* Wait until mdio is ready for next command */
2357 #define MDIO_WAIT_FOR_USER_ACCESS\
2358 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2359 MDIO_USERACCESS_GO) != 0)
2361 static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2363 unsigned int phy_data = 0;
2364 unsigned int phy_control;
2366 /* Wait until mdio is ready for next command */
2367 MDIO_WAIT_FOR_USER_ACCESS;
2369 phy_control = (MDIO_USERACCESS_GO |
2370 MDIO_USERACCESS_READ |
2371 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2372 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2373 (phy_data & MDIO_USERACCESS_DATA));
2374 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2376 /* Wait until mdio is ready for next command */
2377 MDIO_WAIT_FOR_USER_ACCESS;
2379 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2383 static int emac_mii_write(struct mii_bus *bus, int phy_id,
2384 int phy_reg, u16 phy_data)
2387 unsigned int control;
2389 /* until mdio is ready for next command */
2390 MDIO_WAIT_FOR_USER_ACCESS;
2392 control = (MDIO_USERACCESS_GO |
2393 MDIO_USERACCESS_WRITE |
2394 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2395 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2396 (phy_data & MDIO_USERACCESS_DATA));
2397 emac_mdio_write(MDIO_USERACCESS(0), control);
2402 static int emac_mii_reset(struct mii_bus *bus)
2404 unsigned int clk_div;
2405 int mdio_bus_freq = emac_bus_frequency;
2407 if (mdio_max_freq && mdio_bus_freq)
2408 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2412 clk_div &= MDIO_CONTROL_CLKDIV;
2414 /* Set enable and clock divider in MDIOControl */
2415 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2421 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2423 /* emac_driver: EMAC MII bus structure */
2425 static struct mii_bus *emac_mii;
2427 static void emac_adjust_link(struct net_device *ndev)
2429 struct emac_priv *priv = netdev_priv(ndev);
2430 struct phy_device *phydev = priv->phydev;
2431 unsigned long flags;
2434 spin_lock_irqsave(&priv->lock, flags);
2437 /* check the mode of operation - full/half duplex */
2438 if (phydev->duplex != priv->duplex) {
2440 priv->duplex = phydev->duplex;
2442 if (phydev->speed != priv->speed) {
2444 priv->speed = phydev->speed;
2451 } else if (priv->link) {
2458 emac_update_phystatus(priv);
2459 phy_print_status(priv->phydev);
2462 spin_unlock_irqrestore(&priv->lock, flags);
2465 /*************************************************************************
2466 * Linux Driver Model
2467 *************************************************************************/
2470 * emac_devioctl: EMAC adapter ioctl
2471 * @ndev: The DaVinci EMAC network adapter
2472 * @ifrq: request parameter
2473 * @cmd: command parameter
2475 * EMAC driver ioctl function
2477 * Returns success(0) or appropriate error code
2479 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2481 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2483 if (!(netif_running(ndev)))
2486 /* TODO: Add phy read and write and private statistics get feature */
2492 * emac_dev_open: EMAC device open
2493 * @ndev: The DaVinci EMAC network adapter
2495 * Called when system wants to start the interface. We init TX/RX channels
2496 * and enable the hardware for packet reception/transmission and start the
2499 * Returns 0 for a successful open, or appropriate error code
2501 static int emac_dev_open(struct net_device *ndev)
2503 struct device *emac_dev = &ndev->dev;
2506 struct resource *res;
2510 struct emac_priv *priv = netdev_priv(ndev);
2512 netif_carrier_off(ndev);
2513 for (cnt = 0; cnt < ETH_ALEN; cnt++)
2514 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2516 /* Configuration items */
2517 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2519 /* Clear basic hardware */
2520 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2521 emac_write(EMAC_TXHDP(ch), 0);
2522 emac_write(EMAC_RXHDP(ch), 0);
2523 emac_write(EMAC_RXHDP(ch), 0);
2524 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2525 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2527 priv->mac_hash1 = 0;
2528 priv->mac_hash2 = 0;
2529 emac_write(EMAC_MACHASH1, 0);
2530 emac_write(EMAC_MACHASH2, 0);
2532 /* multi ch not supported - open 1 TX, 1RX ch by default */
2533 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2535 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2538 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2540 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2546 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2547 for (i = res->start; i <= res->end; i++) {
2548 if (request_irq(i, emac_irq, IRQF_DISABLED,
2555 /* Start/Enable EMAC hardware */
2556 emac_hw_enable(priv);
2558 /* Enable Interrupt pacing if configured */
2559 if (priv->coal_intvl != 0) {
2560 struct ethtool_coalesce coal;
2562 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
2563 emac_set_coalesce(ndev, &coal);
2566 /* find the first phy */
2567 priv->phydev = NULL;
2568 if (priv->phy_mask) {
2569 emac_mii_reset(priv->mii_bus);
2570 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2571 if (priv->mii_bus->phy_map[phy_addr]) {
2572 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2577 if (!priv->phydev) {
2578 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2582 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2583 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2585 if (IS_ERR(priv->phydev)) {
2586 printk(KERN_ERR "%s: Could not attach to PHY\n",
2588 return PTR_ERR(priv->phydev);
2595 printk(KERN_INFO "%s: attached PHY driver [%s] "
2596 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2597 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2598 priv->phydev->phy_id);
2600 /* No PHY , fix the link, speed and duplex settings */
2602 priv->speed = SPEED_100;
2603 priv->duplex = DUPLEX_FULL;
2604 emac_update_phystatus(priv);
2607 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2608 emac_dump_regs(priv);
2610 if (netif_msg_drv(priv))
2611 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2614 phy_start(priv->phydev);
2620 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2622 for (q = k; k >= 0; k--) {
2623 for (m = i; m >= res->start; m--)
2625 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2632 * emac_dev_stop: EMAC device stop
2633 * @ndev: The DaVinci EMAC network adapter
2635 * Called when system wants to stop or down the interface. We stop the network
2636 * queue, disable interrupts and cleanup TX/RX channels.
2638 * We return the statistics in net_device_stats structure pulled from emac
2640 static int emac_dev_stop(struct net_device *ndev)
2642 struct resource *res;
2645 struct emac_priv *priv = netdev_priv(ndev);
2646 struct device *emac_dev = &ndev->dev;
2648 /* inform the upper layers. */
2649 netif_stop_queue(ndev);
2650 napi_disable(&priv->napi);
2652 netif_carrier_off(ndev);
2653 emac_int_disable(priv);
2654 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2655 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2656 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2657 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2658 emac_write(EMAC_SOFTRESET, 1);
2661 phy_disconnect(priv->phydev);
2664 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2665 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2666 free_irq(irq_num, priv->ndev);
2670 if (netif_msg_drv(priv))
2671 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2677 * emac_dev_getnetstats: EMAC get statistics function
2678 * @ndev: The DaVinci EMAC network adapter
2680 * Called when system wants to get statistics from the device.
2682 * We return the statistics in net_device_stats structure pulled from emac
2684 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2686 struct emac_priv *priv = netdev_priv(ndev);
2688 u32 stats_clear_mask;
2690 /* update emac hardware stats and reset the registers*/
2692 mac_control = emac_read(EMAC_MACCONTROL);
2694 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2695 stats_clear_mask = EMAC_STATS_CLR_MASK;
2697 stats_clear_mask = 0;
2699 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2700 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2702 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2703 emac_read(EMAC_TXSINGLECOLL) +
2704 emac_read(EMAC_TXMULTICOLL));
2705 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2706 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2707 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2709 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2710 emac_read(EMAC_RXJABBER) +
2711 emac_read(EMAC_RXUNDERSIZED));
2712 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2713 emac_write(EMAC_RXJABBER, stats_clear_mask);
2714 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2716 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2717 emac_read(EMAC_RXMOFOVERRUNS));
2718 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2719 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2721 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2722 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2724 ndev->stats.tx_carrier_errors +=
2725 emac_read(EMAC_TXCARRIERSENSE);
2726 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2728 ndev->stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2729 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2731 return &ndev->stats;
2734 static const struct net_device_ops emac_netdev_ops = {
2735 .ndo_open = emac_dev_open,
2736 .ndo_stop = emac_dev_stop,
2737 .ndo_start_xmit = emac_dev_xmit,
2738 .ndo_set_multicast_list = emac_dev_mcast_set,
2739 .ndo_set_mac_address = emac_dev_setmac_addr,
2740 .ndo_do_ioctl = emac_devioctl,
2741 .ndo_tx_timeout = emac_dev_tx_timeout,
2742 .ndo_get_stats = emac_dev_getnetstats,
2743 #ifdef CONFIG_NET_POLL_CONTROLLER
2744 .ndo_poll_controller = emac_poll_controller,
2749 * davinci_emac_probe: EMAC device probe
2750 * @pdev: The DaVinci EMAC device that we are removing
2752 * Called when probing for emac devicesr. We get details of instances and
2753 * resource information from platform init and register a network device
2754 * and allocate resources necessary for driver to perform
2756 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2759 struct resource *res;
2760 struct net_device *ndev;
2761 struct emac_priv *priv;
2763 struct emac_platform_data *pdata;
2764 struct device *emac_dev;
2766 /* obtain emac clock from kernel */
2767 emac_clk = clk_get(&pdev->dev, NULL);
2768 if (IS_ERR(emac_clk)) {
2769 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2772 emac_bus_frequency = clk_get_rate(emac_clk);
2773 /* TODO: Probe PHY here if possible */
2775 ndev = alloc_etherdev(sizeof(struct emac_priv));
2777 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2782 platform_set_drvdata(pdev, ndev);
2783 priv = netdev_priv(ndev);
2786 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2788 spin_lock_init(&priv->tx_lock);
2789 spin_lock_init(&priv->rx_lock);
2790 spin_lock_init(&priv->lock);
2792 pdata = pdev->dev.platform_data;
2794 printk(KERN_ERR "DaVinci EMAC: No platform data\n");
2798 /* MAC addr and PHY mask , RMII enable info from platform_data */
2799 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2800 priv->phy_mask = pdata->phy_mask;
2801 priv->rmii_en = pdata->rmii_en;
2802 priv->version = pdata->version;
2803 priv->int_enable = pdata->interrupt_enable;
2804 priv->int_disable = pdata->interrupt_disable;
2806 priv->coal_intvl = 0;
2807 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
2809 emac_dev = &ndev->dev;
2810 /* Get EMAC platform data */
2811 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2813 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2818 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2819 size = res->end - res->start + 1;
2820 if (!request_mem_region(res->start, size, ndev->name)) {
2821 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n");
2826 priv->remap_addr = ioremap(res->start, size);
2827 if (!priv->remap_addr) {
2828 dev_err(emac_dev, "Unable to map IO\n");
2830 release_mem_region(res->start, size);
2833 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2834 ndev->base_addr = (unsigned long)priv->remap_addr;
2836 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2837 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2838 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2840 if (pdata->hw_ram_addr)
2841 priv->hw_ram_addr = pdata->hw_ram_addr;
2843 priv->hw_ram_addr = (u32 __force)res->start +
2844 pdata->ctrl_ram_offset;
2846 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2848 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2852 ndev->irq = res->start;
2854 if (!is_valid_ether_addr(priv->mac_addr)) {
2855 /* Use random MAC if none passed */
2856 random_ether_addr(priv->mac_addr);
2857 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2858 __func__, priv->mac_addr);
2861 ndev->netdev_ops = &emac_netdev_ops;
2862 SET_ETHTOOL_OPS(ndev, ðtool_ops);
2863 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2865 clk_enable(emac_clk);
2867 /* register the network device */
2868 SET_NETDEV_DEV(ndev, &pdev->dev);
2869 rc = register_netdev(ndev);
2871 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2873 goto netdev_reg_err;
2877 /* MII/Phy intialisation, mdio bus registration */
2878 emac_mii = mdiobus_alloc();
2879 if (emac_mii == NULL) {
2880 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2882 goto mdio_alloc_err;
2885 priv->mii_bus = emac_mii;
2886 emac_mii->name = "emac-mii",
2887 emac_mii->read = emac_mii_read,
2888 emac_mii->write = emac_mii_write,
2889 emac_mii->reset = emac_mii_reset,
2890 emac_mii->irq = mii_irqs,
2891 emac_mii->phy_mask = ~(priv->phy_mask);
2892 emac_mii->parent = &pdev->dev;
2893 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2894 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2895 mdio_max_freq = pdata->mdio_max_freq;
2896 emac_mii->reset(emac_mii);
2898 /* Register the MII bus */
2899 rc = mdiobus_register(emac_mii);
2903 if (netif_msg_probe(priv)) {
2904 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2905 "(regs: %p, irq: %d)\n",
2906 (void *)priv->emac_base_phys, ndev->irq);
2911 mdiobus_free(emac_mii);
2915 clk_disable(emac_clk);
2917 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2918 release_mem_region(res->start, res->end - res->start + 1);
2919 iounmap(priv->remap_addr);
2928 * davinci_emac_remove: EMAC device remove
2929 * @pdev: The DaVinci EMAC device that we are removing
2931 * Called when removing the device driver. We disable clock usage and release
2932 * the resources taken up by the driver and unregister network device
2934 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2936 struct resource *res;
2937 struct net_device *ndev = platform_get_drvdata(pdev);
2938 struct emac_priv *priv = netdev_priv(ndev);
2940 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2942 platform_set_drvdata(pdev, NULL);
2943 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2944 mdiobus_unregister(priv->mii_bus);
2945 mdiobus_free(priv->mii_bus);
2947 release_mem_region(res->start, res->end - res->start + 1);
2949 unregister_netdev(ndev);
2951 iounmap(priv->remap_addr);
2953 clk_disable(emac_clk);
2959 static int davinci_emac_suspend(struct device *dev)
2961 struct platform_device *pdev = to_platform_device(dev);
2962 struct net_device *ndev = platform_get_drvdata(pdev);
2964 if (netif_running(ndev))
2965 emac_dev_stop(ndev);
2967 clk_disable(emac_clk);
2972 static int davinci_emac_resume(struct device *dev)
2974 struct platform_device *pdev = to_platform_device(dev);
2975 struct net_device *ndev = platform_get_drvdata(pdev);
2977 clk_enable(emac_clk);
2979 if (netif_running(ndev))
2980 emac_dev_open(ndev);
2985 static const struct dev_pm_ops davinci_emac_pm_ops = {
2986 .suspend = davinci_emac_suspend,
2987 .resume = davinci_emac_resume,
2991 * davinci_emac_driver: EMAC platform driver structure
2993 static struct platform_driver davinci_emac_driver = {
2995 .name = "davinci_emac",
2996 .owner = THIS_MODULE,
2997 .pm = &davinci_emac_pm_ops,
2999 .probe = davinci_emac_probe,
3000 .remove = __devexit_p(davinci_emac_remove),
3004 * davinci_emac_init: EMAC driver module init
3006 * Called when initializing the driver. We register the driver with
3009 static int __init davinci_emac_init(void)
3011 return platform_driver_register(&davinci_emac_driver);
3013 late_initcall(davinci_emac_init);
3016 * davinci_emac_exit: EMAC driver module exit
3018 * Called when exiting the driver completely. We unregister the driver with
3019 * the platform and exit
3021 static void __exit davinci_emac_exit(void)
3023 platform_driver_unregister(&davinci_emac_driver);
3025 module_exit(davinci_emac_exit);
3027 MODULE_LICENSE("GPL");
3028 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
3029 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
3030 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");