2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 /** Pending Items in this driver:
33 * 1. Use Linux cache infrastcture for DMA'ed memory (dma_xxx functions)
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
43 #include <linux/ioport.h>
44 #include <linux/slab.h>
46 #include <linux/interrupt.h>
47 #include <linux/init.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/ethtool.h>
52 #include <linux/highmem.h>
53 #include <linux/proc_fs.h>
54 #include <linux/ctype.h>
55 #include <linux/version.h>
56 #include <linux/spinlock.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/clk.h>
59 #include <linux/platform_device.h>
60 #include <linux/semaphore.h>
61 #include <linux/phy.h>
62 #include <linux/bitops.h>
64 #include <linux/uaccess.h>
65 #include <linux/davinci_emac.h>
70 static int debug_level;
71 module_param(debug_level, int, 0);
72 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
74 /* Netif debug messages possible */
75 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
83 NETIF_MSG_TX_QUEUED | \
86 NETIF_MSG_RX_STATUS | \
92 #define EMAC_MAJOR_VERSION 6
93 #define EMAC_MINOR_VERSION 1
94 #define EMAC_MODULE_VERSION "6.1"
95 MODULE_VERSION(EMAC_MODULE_VERSION);
96 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
98 /* Configuration items */
99 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
100 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
101 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
102 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
103 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
104 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
105 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
106 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
107 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
108 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
109 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
110 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
112 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
113 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
115 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
116 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
117 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
118 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
119 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
120 #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
121 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
122 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
123 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
125 /* Buffer descriptor parameters */
126 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
127 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
129 /* EMAC register related defines */
130 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
131 #define EMAC_NUM_MULTICAST_BITS (64)
132 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
133 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
134 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
135 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
136 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
137 #define EMAC_INT_MASK_CLEAR (0xFF)
139 /* RX MBP register bit positions */
140 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
141 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
142 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
143 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
144 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
145 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
146 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
147 #define EMAC_RXMBP_PROMCH_SHIFT (16)
148 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
149 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
150 #define EMAC_RXMBP_BROADCH_SHIFT (8)
151 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
152 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
153 #define EMAC_RXMBP_MULTICH_SHIFT (0)
154 #define EMAC_RXMBP_MULTICH_MASK (0x7)
155 #define EMAC_RXMBP_CHMASK (0x7)
157 /* EMAC register definitions/bit maps used */
158 # define EMAC_MBP_RXPROMISC (0x00200000)
159 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
160 # define EMAC_MBP_RXBCAST (0x00002000)
161 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
162 # define EMAC_MBP_RXMCAST (0x00000020)
163 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
165 /* EMAC mac_control register */
166 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
167 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
168 #define EMAC_MACCONTROL_GMIIEN BIT(5)
169 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
170 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
171 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
173 /* GIGABIT MODE related bits */
174 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
175 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
177 /* EMAC mac_status register */
178 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
179 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
180 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
181 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
182 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
183 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
184 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
185 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
187 /* EMAC RX register masks */
188 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
189 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
191 /* MAC_IN_VECTOR (0x180) register bit fields */
192 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
193 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
194 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
195 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
197 /** NOTE:: For DM646x the IN_VECTOR has changed */
198 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
199 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
200 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
201 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
203 /* CPPI bit positions */
204 #define EMAC_CPPI_SOP_BIT BIT(31)
205 #define EMAC_CPPI_EOP_BIT BIT(30)
206 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
207 #define EMAC_CPPI_EOQ_BIT BIT(28)
208 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
209 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
210 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
211 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
212 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
214 /* Max hardware defines */
215 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
216 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
218 /* EMAC Peripheral Device Register Memory Layout structure */
219 #define EMAC_TXIDVER 0x0
220 #define EMAC_TXCONTROL 0x4
221 #define EMAC_TXTEARDOWN 0x8
222 #define EMAC_RXIDVER 0x10
223 #define EMAC_RXCONTROL 0x14
224 #define EMAC_RXTEARDOWN 0x18
225 #define EMAC_TXINTSTATRAW 0x80
226 #define EMAC_TXINTSTATMASKED 0x84
227 #define EMAC_TXINTMASKSET 0x88
228 #define EMAC_TXINTMASKCLEAR 0x8C
229 #define EMAC_MACINVECTOR 0x90
231 #define EMAC_DM646X_MACEOIVECTOR 0x94
233 #define EMAC_RXINTSTATRAW 0xA0
234 #define EMAC_RXINTSTATMASKED 0xA4
235 #define EMAC_RXINTMASKSET 0xA8
236 #define EMAC_RXINTMASKCLEAR 0xAC
237 #define EMAC_MACINTSTATRAW 0xB0
238 #define EMAC_MACINTSTATMASKED 0xB4
239 #define EMAC_MACINTMASKSET 0xB8
240 #define EMAC_MACINTMASKCLEAR 0xBC
242 #define EMAC_RXMBPENABLE 0x100
243 #define EMAC_RXUNICASTSET 0x104
244 #define EMAC_RXUNICASTCLEAR 0x108
245 #define EMAC_RXMAXLEN 0x10C
246 #define EMAC_RXBUFFEROFFSET 0x110
247 #define EMAC_RXFILTERLOWTHRESH 0x114
249 #define EMAC_MACCONTROL 0x160
250 #define EMAC_MACSTATUS 0x164
251 #define EMAC_EMCONTROL 0x168
252 #define EMAC_FIFOCONTROL 0x16C
253 #define EMAC_MACCONFIG 0x170
254 #define EMAC_SOFTRESET 0x174
255 #define EMAC_MACSRCADDRLO 0x1D0
256 #define EMAC_MACSRCADDRHI 0x1D4
257 #define EMAC_MACHASH1 0x1D8
258 #define EMAC_MACHASH2 0x1DC
259 #define EMAC_MACADDRLO 0x500
260 #define EMAC_MACADDRHI 0x504
261 #define EMAC_MACINDEX 0x508
263 /* EMAC HDP and Completion registors */
264 #define EMAC_TXHDP(ch) (0x600 + (ch * 4))
265 #define EMAC_RXHDP(ch) (0x620 + (ch * 4))
266 #define EMAC_TXCP(ch) (0x640 + (ch * 4))
267 #define EMAC_RXCP(ch) (0x660 + (ch * 4))
269 /* EMAC statistics registers */
270 #define EMAC_RXGOODFRAMES 0x200
271 #define EMAC_RXBCASTFRAMES 0x204
272 #define EMAC_RXMCASTFRAMES 0x208
273 #define EMAC_RXPAUSEFRAMES 0x20C
274 #define EMAC_RXCRCERRORS 0x210
275 #define EMAC_RXALIGNCODEERRORS 0x214
276 #define EMAC_RXOVERSIZED 0x218
277 #define EMAC_RXJABBER 0x21C
278 #define EMAC_RXUNDERSIZED 0x220
279 #define EMAC_RXFRAGMENTS 0x224
280 #define EMAC_RXFILTERED 0x228
281 #define EMAC_RXQOSFILTERED 0x22C
282 #define EMAC_RXOCTETS 0x230
283 #define EMAC_TXGOODFRAMES 0x234
284 #define EMAC_TXBCASTFRAMES 0x238
285 #define EMAC_TXMCASTFRAMES 0x23C
286 #define EMAC_TXPAUSEFRAMES 0x240
287 #define EMAC_TXDEFERRED 0x244
288 #define EMAC_TXCOLLISION 0x248
289 #define EMAC_TXSINGLECOLL 0x24C
290 #define EMAC_TXMULTICOLL 0x250
291 #define EMAC_TXEXCESSIVECOLL 0x254
292 #define EMAC_TXLATECOLL 0x258
293 #define EMAC_TXUNDERRUN 0x25C
294 #define EMAC_TXCARRIERSENSE 0x260
295 #define EMAC_TXOCTETS 0x264
296 #define EMAC_NETOCTETS 0x280
297 #define EMAC_RXSOFOVERRUNS 0x284
298 #define EMAC_RXMOFOVERRUNS 0x288
299 #define EMAC_RXDMAOVERRUNS 0x28C
301 /* EMAC DM644x control registers */
302 #define EMAC_CTRL_EWCTL (0x4)
303 #define EMAC_CTRL_EWINTTCNT (0x8)
305 /* EMAC MDIO related */
306 /* Mask & Control defines */
307 #define MDIO_CONTROL_CLKDIV (0xFF)
308 #define MDIO_CONTROL_ENABLE BIT(30)
309 #define MDIO_USERACCESS_GO BIT(31)
310 #define MDIO_USERACCESS_WRITE BIT(30)
311 #define MDIO_USERACCESS_READ (0)
312 #define MDIO_USERACCESS_REGADR (0x1F << 21)
313 #define MDIO_USERACCESS_PHYADR (0x1F << 16)
314 #define MDIO_USERACCESS_DATA (0xFFFF)
315 #define MDIO_USERPHYSEL_LINKSEL BIT(7)
316 #define MDIO_VER_MODID (0xFFFF << 16)
317 #define MDIO_VER_REVMAJ (0xFF << 8)
318 #define MDIO_VER_REVMIN (0xFF)
320 #define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
321 #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
322 #define MDIO_CONTROL (0x04)
324 /* EMAC DM646X control module registers */
325 #define EMAC_DM646X_CMRXINTEN (0x14)
326 #define EMAC_DM646X_CMTXINTEN (0x18)
328 /* EMAC EOI codes for C0 */
329 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
330 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
332 /* EMAC Stats Clear Mask */
333 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
335 /** net_buf_obj: EMAC network bufferdata structure
337 * EMAC network buffer data structure
339 struct emac_netbufobj {
345 /** net_pkt_obj: EMAC network packet data structure
347 * EMAC network packet data structure - supports buffer list (for future)
349 struct emac_netpktobj {
350 void *pkt_token; /* data token may hold tx/rx chan id */
351 struct emac_netbufobj *buf_list; /* array of network buffer objects */
356 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
358 * EMAC TX Buffer descriptor data structure
364 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
365 struct emac_tx_bd __iomem *next;
369 /** emac_txch: EMAC TX Channel data structure
371 * EMAC TX Channel data structure
380 void __iomem *bd_mem;
381 struct emac_tx_bd __iomem *bd_pool_head;
382 struct emac_tx_bd __iomem *active_queue_head;
383 struct emac_tx_bd __iomem *active_queue_tail;
384 struct emac_tx_bd __iomem *last_hw_bdprocessed;
386 u32 teardown_pending;
390 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
391 u32 mis_queued_packets;
393 u32 end_of_queue_add;
395 u32 no_active_pkts; /* IRQ when there were no packets to process */
396 u32 active_queue_count;
399 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
401 * EMAC RX Buffer descriptor data structure
408 struct emac_rx_bd __iomem *next;
413 /** emac_rxch: EMAC RX Channel data structure
415 * EMAC RX Channel data structure
418 /* configuration info */
426 void __iomem *bd_mem;
427 struct emac_rx_bd __iomem *bd_pool_head;
428 struct emac_rx_bd __iomem *active_queue_head;
429 struct emac_rx_bd __iomem *active_queue_tail;
431 u32 teardown_pending;
433 /* packet and buffer objects */
434 struct emac_netpktobj pkt_queue;
435 struct emac_netbufobj buf_queue;
438 u32 proc_count; /* number of times emac_rx_bdproc is called */
442 u32 out_of_rx_buffers;
444 u32 end_of_queue_add;
446 u32 mis_queued_packets;
449 /* emac_priv: EMAC private data structure
451 * EMAC adapter private data structure
455 struct net_device *ndev;
456 struct platform_device *pdev;
457 struct napi_struct napi;
461 void __iomem *remap_addr;
463 void __iomem *emac_base;
464 void __iomem *ctrl_base;
465 void __iomem *emac_ctrl_ram;
467 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
468 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
469 u32 link; /* 1=link on, 0=link off */
470 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
471 u32 duplex; /* Link duplex: 0=Half, 1=Full */
476 struct net_device_stats net_dev_stats;
479 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
481 /* periodic timer required for MDIO polling */
482 struct timer_list periodic_timer;
486 /* mii_bus,phy members */
487 struct mii_bus *mii_bus;
488 struct phy_device *phydev;
492 /* clock frequency for EMAC */
493 static struct clk *emac_clk;
494 static unsigned long emac_bus_frequency;
495 static unsigned long mdio_max_freq;
497 /* EMAC internal utility function */
498 static inline u32 emac_virt_to_phys(void __iomem *addr)
500 return (u32 __force) io_v2p(addr);
503 /* Cache macros - Packet buffers would be from skb pool which is cached */
504 #define EMAC_VIRT_NOCACHE(addr) (addr)
505 #define EMAC_CACHE_INVALIDATE(addr, size) \
506 dma_cache_maint((void *)addr, size, DMA_FROM_DEVICE)
507 #define EMAC_CACHE_WRITEBACK(addr, size) \
508 dma_cache_maint((void *)addr, size, DMA_TO_DEVICE)
509 #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
510 dma_cache_maint((void *)addr, size, DMA_BIDIRECTIONAL)
512 /* DM644x does not have BD's in cached memory - so no cache functions */
513 #define BD_CACHE_INVALIDATE(addr, size)
514 #define BD_CACHE_WRITEBACK(addr, size)
515 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
517 /* EMAC TX Host Error description strings */
518 static char *emac_txhost_errcodes[16] = {
519 "No error", "SOP error", "Ownership bit not set in SOP buffer",
520 "Zero Next Buffer Descriptor Pointer Without EOP",
521 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
522 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
523 "Reserved", "Reserved", "Reserved", "Reserved"
526 /* EMAC RX Host Error description strings */
527 static char *emac_rxhost_errcodes[16] = {
528 "No error", "Reserved", "Ownership bit not set in input buffer",
529 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
530 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
531 "Reserved", "Reserved", "Reserved", "Reserved"
535 #define emac_read(reg) ioread32(priv->emac_base + (reg))
536 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
538 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
539 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
541 #define emac_mdio_read(reg) ioread32(bus->priv + (reg))
542 #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
545 * emac_dump_regs: Dump important EMAC registers to debug terminal
546 * @priv: The DaVinci EMAC private adapter structure
548 * Executes ethtool set cmd & sets phy mode
551 static void emac_dump_regs(struct emac_priv *priv)
553 struct device *emac_dev = &priv->ndev->dev;
555 /* Print important registers in EMAC */
556 dev_info(emac_dev, "EMAC Basic registers\n");
557 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
558 emac_ctrl_read(EMAC_CTRL_EWCTL),
559 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
560 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
561 emac_read(EMAC_TXIDVER),
562 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
563 emac_read(EMAC_RXIDVER),
564 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
565 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
566 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
567 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
568 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
569 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
570 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
571 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
572 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
573 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
574 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
575 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
576 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
577 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
578 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
579 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
580 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
581 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
582 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
583 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
584 dev_info(emac_dev, "EMAC Statistics\n");
585 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
586 emac_read(EMAC_RXGOODFRAMES));
587 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
588 emac_read(EMAC_RXBCASTFRAMES));
589 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
590 emac_read(EMAC_RXMCASTFRAMES));
591 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
592 emac_read(EMAC_RXPAUSEFRAMES));
593 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
594 emac_read(EMAC_RXCRCERRORS));
595 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
596 emac_read(EMAC_RXALIGNCODEERRORS));
597 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
598 emac_read(EMAC_RXOVERSIZED));
599 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
600 emac_read(EMAC_RXJABBER));
601 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
602 emac_read(EMAC_RXUNDERSIZED));
603 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
604 emac_read(EMAC_RXFRAGMENTS));
605 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
606 emac_read(EMAC_RXFILTERED));
607 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
608 emac_read(EMAC_RXQOSFILTERED));
609 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
610 emac_read(EMAC_RXOCTETS));
611 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
612 emac_read(EMAC_TXGOODFRAMES));
613 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
614 emac_read(EMAC_TXBCASTFRAMES));
615 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
616 emac_read(EMAC_TXMCASTFRAMES));
617 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
618 emac_read(EMAC_TXPAUSEFRAMES));
619 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
620 emac_read(EMAC_TXDEFERRED));
621 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
622 emac_read(EMAC_TXCOLLISION));
623 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
624 emac_read(EMAC_TXSINGLECOLL));
625 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
626 emac_read(EMAC_TXMULTICOLL));
627 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
628 emac_read(EMAC_TXEXCESSIVECOLL));
629 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
630 emac_read(EMAC_TXLATECOLL));
631 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
632 emac_read(EMAC_TXUNDERRUN));
633 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
634 emac_read(EMAC_TXCARRIERSENSE));
635 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
636 emac_read(EMAC_TXOCTETS));
637 dev_info(emac_dev, "EMAC: net_octets:%d\n",
638 emac_read(EMAC_NETOCTETS));
639 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
640 emac_read(EMAC_RXSOFOVERRUNS));
641 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
642 emac_read(EMAC_RXMOFOVERRUNS));
643 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
644 emac_read(EMAC_RXDMAOVERRUNS));
647 /*************************************************************************
648 * EMAC MDIO/Phy Functionality
649 *************************************************************************/
651 * emac_get_drvinfo: Get EMAC driver information
652 * @ndev: The DaVinci EMAC network adapter
653 * @info: ethtool info structure containing name and version
655 * Returns EMAC driver information (name and version)
658 static void emac_get_drvinfo(struct net_device *ndev,
659 struct ethtool_drvinfo *info)
661 strcpy(info->driver, emac_version_string);
662 strcpy(info->version, EMAC_MODULE_VERSION);
666 * emac_get_settings: Get EMAC settings
667 * @ndev: The DaVinci EMAC network adapter
668 * @ecmd: ethtool command
670 * Executes ethool get command
673 static int emac_get_settings(struct net_device *ndev,
674 struct ethtool_cmd *ecmd)
676 struct emac_priv *priv = netdev_priv(ndev);
678 return phy_ethtool_gset(priv->phydev, ecmd);
685 * emac_set_settings: Set EMAC settings
686 * @ndev: The DaVinci EMAC network adapter
687 * @ecmd: ethtool command
689 * Executes ethool set command
692 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
694 struct emac_priv *priv = netdev_priv(ndev);
696 return phy_ethtool_sset(priv->phydev, ecmd);
703 * ethtool_ops: DaVinci EMAC Ethtool structure
705 * Ethtool support for EMAC adapter
708 static const struct ethtool_ops ethtool_ops = {
709 .get_drvinfo = emac_get_drvinfo,
710 .get_settings = emac_get_settings,
711 .set_settings = emac_set_settings,
712 .get_link = ethtool_op_get_link,
716 * emac_update_phystatus: Update Phy status
717 * @priv: The DaVinci EMAC private adapter structure
719 * Updates phy status and takes action for network queue if required
720 * based upon link status
723 static void emac_update_phystatus(struct emac_priv *priv)
728 struct net_device *ndev = priv->ndev;
730 mac_control = emac_read(EMAC_MACCONTROL);
731 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
732 DUPLEX_FULL : DUPLEX_HALF;
734 new_duplex = priv->phydev->duplex;
736 new_duplex = DUPLEX_FULL;
738 /* We get called only if link has changed (speed/duplex/status) */
739 if ((priv->link) && (new_duplex != cur_duplex)) {
740 priv->duplex = new_duplex;
741 if (DUPLEX_FULL == priv->duplex)
742 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
744 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
747 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
748 mac_control = emac_read(EMAC_MACCONTROL);
749 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
750 EMAC_DM646X_MACCONTORL_GIGFORCE);
752 /* Clear the GIG bit and GIGFORCE bit */
753 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
754 EMAC_DM646X_MACCONTORL_GIG);
756 if (priv->rmii_en && (priv->speed == SPEED_100))
757 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
759 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
762 /* Update mac_control if changed */
763 emac_write(EMAC_MACCONTROL, mac_control);
767 if (!netif_carrier_ok(ndev))
768 netif_carrier_on(ndev);
769 /* reactivate the transmit queue if it is stopped */
770 if (netif_running(ndev) && netif_queue_stopped(ndev))
771 netif_wake_queue(ndev);
774 if (netif_carrier_ok(ndev))
775 netif_carrier_off(ndev);
776 if (!netif_queue_stopped(ndev))
777 netif_stop_queue(ndev);
782 * hash_get: Calculate hash value from mac address
783 * @addr: mac address to delete from hash table
785 * Calculates hash value from mac address
788 static u32 hash_get(u8 *addr)
795 for (cnt = 0; cnt < 2; cnt++) {
797 hash ^= (tmpval >> 2) ^ (tmpval << 4);
799 hash ^= (tmpval >> 4) ^ (tmpval << 2);
801 hash ^= (tmpval >> 6) ^ (tmpval);
808 * hash_add: Hash function to add mac addr from hash table
809 * @priv: The DaVinci EMAC private adapter structure
810 * mac_addr: mac address to delete from hash table
812 * Adds mac address to the internal hash table
815 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
817 struct device *emac_dev = &priv->ndev->dev;
820 u32 hash_value = hash_get(mac_addr);
822 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
823 if (netif_msg_drv(priv)) {
824 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
825 "Hash %08x, should not be greater than %08x",
826 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
831 /* set the hash bit only if not previously set */
832 if (priv->multicast_hash_cnt[hash_value] == 0) {
833 rc = 1; /* hash value changed */
834 if (hash_value < 32) {
835 hash_bit = BIT(hash_value);
836 priv->mac_hash1 |= hash_bit;
838 hash_bit = BIT((hash_value - 32));
839 priv->mac_hash2 |= hash_bit;
843 /* incr counter for num of mcast addr's mapped to "this" hash bit */
844 ++priv->multicast_hash_cnt[hash_value];
850 * hash_del: Hash function to delete mac addr from hash table
851 * @priv: The DaVinci EMAC private adapter structure
852 * mac_addr: mac address to delete from hash table
854 * Removes mac address from the internal hash table
857 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
862 hash_value = hash_get(mac_addr);
863 if (priv->multicast_hash_cnt[hash_value] > 0) {
864 /* dec cntr for num of mcast addr's mapped to this hash bit */
865 --priv->multicast_hash_cnt[hash_value];
868 /* if counter still > 0, at least one multicast address refers
869 * to this hash bit. so return 0 */
870 if (priv->multicast_hash_cnt[hash_value] > 0)
873 if (hash_value < 32) {
874 hash_bit = BIT(hash_value);
875 priv->mac_hash1 &= ~hash_bit;
877 hash_bit = BIT((hash_value - 32));
878 priv->mac_hash2 &= ~hash_bit;
881 /* return 1 to indicate change in mac_hash registers reqd */
885 /* EMAC multicast operation */
886 #define EMAC_MULTICAST_ADD 0
887 #define EMAC_MULTICAST_DEL 1
888 #define EMAC_ALL_MULTI_SET 2
889 #define EMAC_ALL_MULTI_CLR 3
892 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
893 * @priv: The DaVinci EMAC private adapter structure
894 * @action: multicast operation to perform
895 * mac_addr: mac address to set
897 * Set multicast addresses in EMAC adapter - internal function
900 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
902 struct device *emac_dev = &priv->ndev->dev;
906 case EMAC_MULTICAST_ADD:
907 update = hash_add(priv, mac_addr);
909 case EMAC_MULTICAST_DEL:
910 update = hash_del(priv, mac_addr);
912 case EMAC_ALL_MULTI_SET:
914 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
915 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
917 case EMAC_ALL_MULTI_CLR:
921 memset(&(priv->multicast_hash_cnt[0]), 0,
922 sizeof(priv->multicast_hash_cnt[0]) *
923 EMAC_NUM_MULTICAST_BITS);
926 if (netif_msg_drv(priv))
927 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
928 ": bad operation %d", action);
932 /* write to the hardware only if the register status chances */
934 emac_write(EMAC_MACHASH1, priv->mac_hash1);
935 emac_write(EMAC_MACHASH2, priv->mac_hash2);
940 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
941 * @ndev: The DaVinci EMAC network adapter
943 * Set multicast addresses in EMAC adapter
946 static void emac_dev_mcast_set(struct net_device *ndev)
949 struct emac_priv *priv = netdev_priv(ndev);
951 mbp_enable = emac_read(EMAC_RXMBPENABLE);
952 if (ndev->flags & IFF_PROMISC) {
953 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
954 mbp_enable |= (EMAC_MBP_RXPROMISC);
956 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
957 if ((ndev->flags & IFF_ALLMULTI) ||
958 (ndev->mc_count > EMAC_DEF_MAX_MULTICAST_ADDRESSES)) {
959 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
960 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
962 if (ndev->mc_count > 0) {
963 struct dev_mc_list *mc_ptr;
964 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
965 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
966 /* program multicast address list into EMAC hardware */
967 for (mc_ptr = ndev->mc_list; mc_ptr;
968 mc_ptr = mc_ptr->next) {
969 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
970 (u8 *)mc_ptr->dmi_addr);
973 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
974 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
977 /* Set mbp config register */
978 emac_write(EMAC_RXMBPENABLE, mbp_enable);
981 /*************************************************************************
982 * EMAC Hardware manipulation
983 *************************************************************************/
986 * emac_int_disable: Disable EMAC module interrupt (from adapter)
987 * @priv: The DaVinci EMAC private adapter structure
989 * Disable EMAC interrupt on the adapter
992 static void emac_int_disable(struct emac_priv *priv)
994 if (priv->version == EMAC_VERSION_2) {
997 local_irq_save(flags);
999 /* Program C0_Int_En to zero to turn off
1000 * interrupts to the CPU */
1001 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1002 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1003 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1005 local_irq_restore(flags);
1008 /* Set DM644x control registers for interrupt control */
1009 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1014 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1015 * @priv: The DaVinci EMAC private adapter structure
1017 * Enable EMAC interrupt on the adapter
1020 static void emac_int_enable(struct emac_priv *priv)
1022 if (priv->version == EMAC_VERSION_2) {
1023 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1024 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1026 /* In addition to turning on interrupt Enable, we need
1027 * ack by writing appropriate values to the EOI
1030 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1032 /* ack rxen only then a new pulse will be generated */
1033 emac_write(EMAC_DM646X_MACEOIVECTOR,
1034 EMAC_DM646X_MAC_EOI_C0_RXEN);
1036 /* ack txen- only then a new pulse will be generated */
1037 emac_write(EMAC_DM646X_MACEOIVECTOR,
1038 EMAC_DM646X_MAC_EOI_C0_TXEN);
1041 /* Set DM644x control registers for interrupt control */
1042 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1047 * emac_irq: EMAC interrupt handler
1048 * @irq: interrupt number
1049 * @dev_id: EMAC network adapter data structure ptr
1051 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1052 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1054 * Returns interrupt handled condition
1056 static irqreturn_t emac_irq(int irq, void *dev_id)
1058 struct net_device *ndev = (struct net_device *)dev_id;
1059 struct emac_priv *priv = netdev_priv(ndev);
1062 if (likely(netif_running(priv->ndev))) {
1063 emac_int_disable(priv);
1064 napi_schedule(&priv->napi);
1066 /* we are closing down, so dont process anything */
1071 /** EMAC on-chip buffer descriptor memory
1073 * WARNING: Please note that the on chip memory is used for both TX and RX
1074 * buffer descriptor queues and is equally divided between TX and RX desc's
1075 * If the number of TX or RX descriptors change this memory pointers need
1076 * to be adjusted. If external memory is allocated then these pointers can
1077 * pointer to the memory
1080 #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1081 #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1082 (((priv)->ctrl_ram_size) >> 1))
1085 * emac_init_txch: TX channel initialization
1086 * @priv: The DaVinci EMAC private adapter structure
1087 * @ch: RX channel number
1089 * Called during device init to setup a TX channel (allocate buffer desc
1090 * create free pool and keep ready for transmission
1092 * Returns success(0) or mem alloc failures error code
1094 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1096 struct device *emac_dev = &priv->ndev->dev;
1099 struct emac_tx_bd __iomem *curr_bd;
1100 struct emac_txch *txch = NULL;
1102 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1104 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1107 priv->txch[ch] = txch;
1108 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1109 txch->active_queue_head = NULL;
1110 txch->active_queue_tail = NULL;
1111 txch->queue_active = 0;
1112 txch->teardown_pending = 0;
1114 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1115 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1117 if (NULL == txch->tx_complete) {
1118 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1123 /* allocate buffer descriptor pool align every BD on four word
1124 * boundry for future requirements */
1125 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1126 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1127 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1129 /* alloc TX BD memory */
1130 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1131 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1133 /* initialize the BD linked list */
1134 mem = (void __force __iomem *)
1135 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1136 txch->bd_pool_head = NULL;
1137 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1138 curr_bd = mem + (cnt * bd_size);
1139 curr_bd->next = txch->bd_pool_head;
1140 txch->bd_pool_head = curr_bd;
1143 /* reset statistics counters */
1144 txch->out_of_tx_bd = 0;
1145 txch->no_active_pkts = 0;
1146 txch->active_queue_count = 0;
1152 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1153 * @priv: The DaVinci EMAC private adapter structure
1154 * @ch: TX channel number
1156 * Called to clean up TX channel resources
1159 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1161 struct emac_txch *txch = priv->txch[ch];
1165 txch->bd_mem = NULL;
1166 kfree(txch->tx_complete);
1168 priv->txch[ch] = NULL;
1173 * emac_net_tx_complete: TX packet completion function
1174 * @priv: The DaVinci EMAC private adapter structure
1175 * @net_data_tokens: packet token - skb pointer
1176 * @num_tokens: number of skb's to free
1177 * @ch: TX channel number
1179 * Frees the skb once packet is transmitted
1182 static int emac_net_tx_complete(struct emac_priv *priv,
1183 void **net_data_tokens,
1184 int num_tokens, u32 ch)
1188 if (unlikely(num_tokens && netif_queue_stopped(priv->ndev)))
1189 netif_start_queue(priv->ndev);
1190 for (cnt = 0; cnt < num_tokens; cnt++) {
1191 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1194 priv->net_dev_stats.tx_packets++;
1195 priv->net_dev_stats.tx_bytes += skb->len;
1196 dev_kfree_skb_any(skb);
1202 * emac_txch_teardown: TX channel teardown
1203 * @priv: The DaVinci EMAC private adapter structure
1204 * @ch: TX channel number
1206 * Called to teardown TX channel
1209 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1211 struct device *emac_dev = &priv->ndev->dev;
1212 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1213 struct emac_txch *txch = priv->txch[ch];
1214 struct emac_tx_bd __iomem *curr_bd;
1216 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1217 EMAC_TEARDOWN_VALUE) {
1218 /* wait till tx teardown complete */
1219 cpu_relax(); /* TODO: check if this helps ... */
1221 if (0 == teardown_cnt) {
1222 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1226 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1228 /* process sent packets and return skb's to upper layer */
1229 if (1 == txch->queue_active) {
1230 curr_bd = txch->active_queue_head;
1231 while (curr_bd != NULL) {
1232 emac_net_tx_complete(priv, (void __force *)
1233 &curr_bd->buf_token, 1, ch);
1234 if (curr_bd != txch->active_queue_tail)
1235 curr_bd = curr_bd->next;
1239 txch->bd_pool_head = txch->active_queue_head;
1240 txch->active_queue_head =
1241 txch->active_queue_tail = NULL;
1246 * emac_stop_txch: Stop TX channel operation
1247 * @priv: The DaVinci EMAC private adapter structure
1248 * @ch: TX channel number
1250 * Called to stop TX channel operation
1253 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1255 struct emac_txch *txch = priv->txch[ch];
1258 txch->teardown_pending = 1;
1259 emac_write(EMAC_TXTEARDOWN, 0);
1260 emac_txch_teardown(priv, ch);
1261 txch->teardown_pending = 0;
1262 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1267 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1268 * @priv: The DaVinci EMAC private adapter structure
1269 * @ch: TX channel number to process buffer descriptors for
1270 * @budget: number of packets allowed to process
1271 * @pending: indication to caller that packets are pending to process
1273 * Processes TX buffer descriptors after packets are transmitted - checks
1274 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1275 * the SKB buffer. Only "budget" number of packets are processed and
1276 * indication of pending packets provided to the caller
1278 * Returns number of packets processed
1280 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1282 struct device *emac_dev = &priv->ndev->dev;
1283 unsigned long flags;
1285 u32 pkts_processed = 0;
1286 u32 tx_complete_cnt = 0;
1287 struct emac_tx_bd __iomem *curr_bd;
1288 struct emac_txch *txch = priv->txch[ch];
1289 u32 *tx_complete_ptr = txch->tx_complete;
1291 if (unlikely(1 == txch->teardown_pending)) {
1292 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1293 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1294 "teardown pending\n");
1296 return 0; /* dont handle any pkt completions */
1300 spin_lock_irqsave(&priv->tx_lock, flags);
1301 curr_bd = txch->active_queue_head;
1302 if (NULL == curr_bd) {
1303 emac_write(EMAC_TXCP(ch),
1304 emac_virt_to_phys(txch->last_hw_bdprocessed));
1305 txch->no_active_pkts++;
1306 spin_unlock_irqrestore(&priv->tx_lock, flags);
1309 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1310 frame_status = curr_bd->mode;
1312 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1313 (pkts_processed < budget)) {
1314 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd));
1315 txch->active_queue_head = curr_bd->next;
1316 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1317 if (curr_bd->next) { /* misqueued packet */
1318 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1319 ++txch->mis_queued_packets;
1321 txch->queue_active = 0; /* end of queue */
1324 *tx_complete_ptr = (u32) curr_bd->buf_token;
1327 curr_bd->next = txch->bd_pool_head;
1328 txch->bd_pool_head = curr_bd;
1329 --txch->active_queue_count;
1331 txch->last_hw_bdprocessed = curr_bd;
1332 curr_bd = txch->active_queue_head;
1334 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1335 frame_status = curr_bd->mode;
1337 } /* end of pkt processing loop */
1339 emac_net_tx_complete(priv,
1340 (void *)&txch->tx_complete[0],
1341 tx_complete_cnt, ch);
1342 spin_unlock_irqrestore(&priv->tx_lock, flags);
1343 return pkts_processed;
1346 #define EMAC_ERR_TX_OUT_OF_BD -1
1349 * emac_send: EMAC Transmit function (internal)
1350 * @priv: The DaVinci EMAC private adapter structure
1351 * @pkt: packet pointer (contains skb ptr)
1352 * @ch: TX channel number
1354 * Called by the transmit function to queue the packet in EMAC hardware queue
1356 * Returns success(0) or error code (typically out of desc's)
1358 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1360 unsigned long flags;
1361 struct emac_tx_bd __iomem *curr_bd;
1362 struct emac_txch *txch;
1363 struct emac_netbufobj *buf_list;
1365 txch = priv->txch[ch];
1366 buf_list = pkt->buf_list; /* get handle to the buffer array */
1368 /* check packet size and pad if short */
1369 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1370 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1371 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1374 spin_lock_irqsave(&priv->tx_lock, flags);
1375 curr_bd = txch->bd_pool_head;
1376 if (curr_bd == NULL) {
1377 txch->out_of_tx_bd++;
1378 spin_unlock_irqrestore(&priv->tx_lock, flags);
1379 return EMAC_ERR_TX_OUT_OF_BD;
1382 txch->bd_pool_head = curr_bd->next;
1383 curr_bd->buf_token = buf_list->buf_token;
1384 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1385 curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
1386 curr_bd->off_b_len = buf_list->length;
1387 curr_bd->h_next = 0;
1388 curr_bd->next = NULL;
1389 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1390 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1392 /* flush the packet from cache if write back cache is present */
1393 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1395 /* send the packet */
1396 if (txch->active_queue_head == NULL) {
1397 txch->active_queue_head = curr_bd;
1398 txch->active_queue_tail = curr_bd;
1399 if (1 != txch->queue_active) {
1400 emac_write(EMAC_TXHDP(ch),
1401 emac_virt_to_phys(curr_bd));
1402 txch->queue_active = 1;
1404 ++txch->queue_reinit;
1406 register struct emac_tx_bd __iomem *tail_bd;
1407 register u32 frame_status;
1409 tail_bd = txch->active_queue_tail;
1410 tail_bd->next = curr_bd;
1411 txch->active_queue_tail = curr_bd;
1412 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1413 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd);
1414 frame_status = tail_bd->mode;
1415 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1416 emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd));
1417 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1418 tail_bd->mode = frame_status;
1419 ++txch->end_of_queue_add;
1422 txch->active_queue_count++;
1423 spin_unlock_irqrestore(&priv->tx_lock, flags);
1428 * emac_dev_xmit: EMAC Transmit function
1430 * @ndev: The DaVinci EMAC network adapter
1432 * Called by the system to transmit a packet - we queue the packet in
1433 * EMAC hardware transmit queue
1435 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1437 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1439 struct device *emac_dev = &ndev->dev;
1441 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1442 struct emac_netpktobj tx_packet; /* packet object */
1443 struct emac_priv *priv = netdev_priv(ndev);
1445 /* If no link, return */
1446 if (unlikely(!priv->link)) {
1447 if (netif_msg_tx_err(priv) && net_ratelimit())
1448 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1449 return NETDEV_TX_BUSY;
1452 /* Build the buffer and packet objects - Since only single fragment is
1453 * supported, need not set length and token in both packet & object.
1454 * Doing so for completeness sake & to show that this needs to be done
1455 * in multifragment case
1457 tx_packet.buf_list = &tx_buf;
1458 tx_packet.num_bufs = 1; /* only single fragment supported */
1459 tx_packet.pkt_length = skb->len;
1460 tx_packet.pkt_token = (void *)skb;
1461 tx_buf.length = skb->len;
1462 tx_buf.buf_token = (void *)skb;
1463 tx_buf.data_ptr = skb->data;
1464 EMAC_CACHE_WRITEBACK((unsigned long)skb->data, skb->len);
1465 ndev->trans_start = jiffies;
1466 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1467 if (unlikely(ret_code != 0)) {
1468 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1469 if (netif_msg_tx_err(priv) && net_ratelimit())
1470 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1471 " err. Out of TX BD's");
1472 netif_stop_queue(priv->ndev);
1474 priv->net_dev_stats.tx_dropped++;
1475 return NETDEV_TX_BUSY;
1478 return NETDEV_TX_OK;
1482 * emac_dev_tx_timeout: EMAC Transmit timeout function
1483 * @ndev: The DaVinci EMAC network adapter
1485 * Called when system detects that a skb timeout period has expired
1486 * potentially due to a fault in the adapter in not being able to send
1487 * it out on the wire. We teardown the TX channel assuming a hardware
1488 * error and re-initialize the TX channel for hardware operation
1491 static void emac_dev_tx_timeout(struct net_device *ndev)
1493 struct emac_priv *priv = netdev_priv(ndev);
1494 struct device *emac_dev = &ndev->dev;
1496 if (netif_msg_tx_err(priv))
1497 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1499 priv->net_dev_stats.tx_errors++;
1500 emac_int_disable(priv);
1501 emac_stop_txch(priv, EMAC_DEF_TX_CH);
1502 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1503 emac_init_txch(priv, EMAC_DEF_TX_CH);
1504 emac_write(EMAC_TXHDP(0), 0);
1505 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1506 emac_int_enable(priv);
1510 * emac_net_alloc_rx_buf: Allocate a skb for RX
1511 * @priv: The DaVinci EMAC private adapter structure
1512 * @buf_size: size of SKB data buffer to allocate
1513 * @data_token: data token returned (skb handle for storing in buffer desc)
1514 * @ch: RX channel number
1516 * Called during RX channel setup - allocates skb buffer of required size
1517 * and provides the skb handle and allocated buffer data pointer to caller
1519 * Returns skb data pointer or 0 on failure to alloc skb
1521 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1522 void **data_token, u32 ch)
1524 struct net_device *ndev = priv->ndev;
1525 struct device *emac_dev = &ndev->dev;
1526 struct sk_buff *p_skb;
1528 p_skb = dev_alloc_skb(buf_size);
1529 if (unlikely(NULL == p_skb)) {
1530 if (netif_msg_rx_err(priv) && net_ratelimit())
1531 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1535 /* set device pointer in skb and reserve space for extra bytes */
1537 skb_reserve(p_skb, NET_IP_ALIGN);
1538 *data_token = (void *) p_skb;
1539 EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p_skb->data, buf_size);
1544 * emac_init_rxch: RX channel initialization
1545 * @priv: The DaVinci EMAC private adapter structure
1546 * @ch: RX channel number
1547 * @param: mac address for RX channel
1549 * Called during device init to setup a RX channel (allocate buffers and
1550 * buffer descriptors, create queue and keep ready for reception
1552 * Returns success(0) or mem alloc failures error code
1554 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1556 struct device *emac_dev = &priv->ndev->dev;
1559 struct emac_rx_bd __iomem *curr_bd;
1560 struct emac_rxch *rxch = NULL;
1562 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1564 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1567 priv->rxch[ch] = rxch;
1568 rxch->buf_size = priv->rx_buf_size;
1569 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1570 rxch->queue_active = 0;
1571 rxch->teardown_pending = 0;
1573 /* save mac address */
1574 for (cnt = 0; cnt < 6; cnt++)
1575 rxch->mac_addr[cnt] = param[cnt];
1577 /* allocate buffer descriptor pool align every BD on four word
1578 * boundry for future requirements */
1579 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1580 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1581 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1582 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1583 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1584 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1586 /* allocate RX buffer and initialize the BD linked list */
1587 mem = (void __force __iomem *)
1588 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1589 rxch->active_queue_head = NULL;
1590 rxch->active_queue_tail = mem;
1591 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1592 curr_bd = mem + (cnt * bd_size);
1593 /* for future use the last parameter contains the BD ptr */
1594 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1596 (void __force **)&curr_bd->buf_token,
1598 if (curr_bd->data_ptr == NULL) {
1599 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1600 "failed for ch %d\n", ch);
1605 /* populate the hardware descriptor */
1606 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head);
1607 /* FIXME buff_ptr = dma_map_single(... data_ptr ...) */
1608 curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
1609 curr_bd->off_b_len = rxch->buf_size;
1610 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1612 /* write back to hardware memory */
1613 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1614 EMAC_BD_LENGTH_FOR_CACHE);
1615 curr_bd->next = rxch->active_queue_head;
1616 rxch->active_queue_head = curr_bd;
1619 /* At this point rxCppi->activeQueueHead points to the first
1620 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1621 points to the last RX BD
1627 * emac_rxch_teardown: RX channel teardown
1628 * @priv: The DaVinci EMAC private adapter structure
1629 * @ch: RX channel number
1631 * Called during device stop to teardown RX channel
1634 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1636 struct device *emac_dev = &priv->ndev->dev;
1637 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1639 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1640 EMAC_TEARDOWN_VALUE) {
1641 /* wait till tx teardown complete */
1642 cpu_relax(); /* TODO: check if this helps ... */
1644 if (0 == teardown_cnt) {
1645 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1649 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1653 * emac_stop_rxch: Stop RX channel operation
1654 * @priv: The DaVinci EMAC private adapter structure
1655 * @ch: RX channel number
1657 * Called during device stop to stop RX channel operation
1660 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1662 struct emac_rxch *rxch = priv->rxch[ch];
1665 rxch->teardown_pending = 1;
1666 emac_write(EMAC_RXTEARDOWN, ch);
1667 /* wait for teardown complete */
1668 emac_rxch_teardown(priv, ch);
1669 rxch->teardown_pending = 0;
1670 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1675 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1676 * @priv: The DaVinci EMAC private adapter structure
1677 * @ch: RX channel number
1679 * Called during device stop to clean up RX channel resources
1682 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1684 struct emac_rxch *rxch = priv->rxch[ch];
1685 struct emac_rx_bd __iomem *curr_bd;
1688 /* free the receive buffers previously allocated */
1689 curr_bd = rxch->active_queue_head;
1691 if (curr_bd->buf_token) {
1692 dev_kfree_skb_any((struct sk_buff *)\
1693 curr_bd->buf_token);
1695 curr_bd = curr_bd->next;
1698 rxch->bd_mem = NULL;
1700 priv->rxch[ch] = NULL;
1705 * emac_set_type0addr: Set EMAC Type0 mac address
1706 * @priv: The DaVinci EMAC private adapter structure
1707 * @ch: RX channel number
1708 * @mac_addr: MAC address to set in device
1710 * Called internally to set Type0 mac address of the adapter (Device)
1712 * Returns success (0) or appropriate error code (none as of now)
1714 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1717 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1718 emac_write(EMAC_MACSRCADDRLO, val);
1720 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1721 (mac_addr[1] << 8) | (mac_addr[0]));
1722 emac_write(EMAC_MACSRCADDRHI, val);
1723 val = emac_read(EMAC_RXUNICASTSET);
1725 emac_write(EMAC_RXUNICASTSET, val);
1726 val = emac_read(EMAC_RXUNICASTCLEAR);
1728 emac_write(EMAC_RXUNICASTCLEAR, val);
1732 * emac_set_type1addr: Set EMAC Type1 mac address
1733 * @priv: The DaVinci EMAC private adapter structure
1734 * @ch: RX channel number
1735 * @mac_addr: MAC address to set in device
1737 * Called internally to set Type1 mac address of the adapter (Device)
1739 * Returns success (0) or appropriate error code (none as of now)
1741 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1744 emac_write(EMAC_MACINDEX, ch);
1745 val = ((mac_addr[5] << 8) | mac_addr[4]);
1746 emac_write(EMAC_MACADDRLO, val);
1747 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1748 (mac_addr[1] << 8) | (mac_addr[0]));
1749 emac_write(EMAC_MACADDRHI, val);
1750 emac_set_type0addr(priv, ch, mac_addr);
1754 * emac_set_type2addr: Set EMAC Type2 mac address
1755 * @priv: The DaVinci EMAC private adapter structure
1756 * @ch: RX channel number
1757 * @mac_addr: MAC address to set in device
1758 * @index: index into RX address entries
1759 * @match: match parameter for RX address matching logic
1761 * Called internally to set Type2 mac address of the adapter (Device)
1763 * Returns success (0) or appropriate error code (none as of now)
1765 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1766 char *mac_addr, int index, int match)
1769 emac_write(EMAC_MACINDEX, index);
1770 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1771 (mac_addr[1] << 8) | (mac_addr[0]));
1772 emac_write(EMAC_MACADDRHI, val);
1773 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1774 (match << 19) | BIT(20));
1775 emac_write(EMAC_MACADDRLO, val);
1776 emac_set_type0addr(priv, ch, mac_addr);
1780 * emac_setmac: Set mac address in the adapter (internal function)
1781 * @priv: The DaVinci EMAC private adapter structure
1782 * @ch: RX channel number
1783 * @mac_addr: MAC address to set in device
1785 * Called internally to set the mac address of the adapter (Device)
1787 * Returns success (0) or appropriate error code (none as of now)
1789 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1791 struct device *emac_dev = &priv->ndev->dev;
1793 if (priv->rx_addr_type == 0) {
1794 emac_set_type0addr(priv, ch, mac_addr);
1795 } else if (priv->rx_addr_type == 1) {
1797 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1798 emac_set_type1addr(priv, ch, mac_addr);
1799 } else if (priv->rx_addr_type == 2) {
1800 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1801 emac_set_type0addr(priv, ch, mac_addr);
1803 if (netif_msg_drv(priv))
1804 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1809 * emac_dev_setmac_addr: Set mac address in the adapter
1810 * @ndev: The DaVinci EMAC network adapter
1811 * @addr: MAC address to set in device
1813 * Called by the system to set the mac address of the adapter (Device)
1815 * Returns success (0) or appropriate error code (none as of now)
1817 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1819 struct emac_priv *priv = netdev_priv(ndev);
1820 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1821 struct device *emac_dev = &priv->ndev->dev;
1822 struct sockaddr *sa = addr;
1824 if (!is_valid_ether_addr(sa->sa_data))
1827 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1828 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1829 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1831 /* If the interface is down - rxch is NULL. */
1832 /* MAC address is configured only after the interface is enabled. */
1833 if (netif_running(ndev)) {
1834 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1835 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1838 if (netif_msg_drv(priv))
1839 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1846 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1847 * @priv: The DaVinci EMAC private adapter structure
1848 * @ch: RX channel number to process buffer descriptors for
1849 * @curr_bd: current buffer descriptor
1850 * @buffer: buffer pointer for descriptor
1851 * @buf_token: buffer token (stores skb information)
1853 * Prepares the recycled buffer descriptor and addes it to hardware
1854 * receive queue - if queue empty this descriptor becomes the head
1855 * else addes the descriptor to end of queue
1858 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1859 struct emac_rx_bd __iomem *curr_bd,
1860 char *buffer, void *buf_token)
1862 struct emac_rxch *rxch = priv->rxch[ch];
1864 /* populate the hardware descriptor */
1865 curr_bd->h_next = 0;
1866 /* FIXME buff_ptr = dma_map_single(... buffer ...) */
1867 curr_bd->buff_ptr = virt_to_phys(buffer);
1868 curr_bd->off_b_len = rxch->buf_size;
1869 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1870 curr_bd->next = NULL;
1871 curr_bd->data_ptr = buffer;
1872 curr_bd->buf_token = buf_token;
1875 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1876 if (rxch->active_queue_head == NULL) {
1877 rxch->active_queue_head = curr_bd;
1878 rxch->active_queue_tail = curr_bd;
1879 if (0 != rxch->queue_active) {
1880 emac_write(EMAC_RXHDP(ch),
1881 emac_virt_to_phys(rxch->active_queue_head));
1882 rxch->queue_active = 1;
1885 struct emac_rx_bd __iomem *tail_bd;
1888 tail_bd = rxch->active_queue_tail;
1889 rxch->active_queue_tail = curr_bd;
1890 tail_bd->next = curr_bd;
1891 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1892 tail_bd->h_next = emac_virt_to_phys(curr_bd);
1893 frame_status = tail_bd->mode;
1894 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1895 emac_write(EMAC_RXHDP(ch),
1896 emac_virt_to_phys(curr_bd));
1897 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1898 tail_bd->mode = frame_status;
1899 ++rxch->end_of_queue_add;
1902 ++rxch->recycled_bd;
1906 * emac_net_rx_cb: Prepares packet and sends to upper layer
1907 * @priv: The DaVinci EMAC private adapter structure
1908 * @net_pkt_list: Network packet list (received packets)
1910 * Invalidates packet buffer memory and sends the received packet to upper
1913 * Returns success or appropriate error code (none as of now)
1915 static int emac_net_rx_cb(struct emac_priv *priv,
1916 struct emac_netpktobj *net_pkt_list)
1918 struct sk_buff *p_skb;
1919 p_skb = (struct sk_buff *)net_pkt_list->pkt_token;
1920 /* set length of packet */
1921 skb_put(p_skb, net_pkt_list->pkt_length);
1922 EMAC_CACHE_INVALIDATE((unsigned long)p_skb->data, p_skb->len);
1923 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
1924 netif_receive_skb(p_skb);
1925 priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
1926 priv->net_dev_stats.rx_packets++;
1931 * emac_rx_bdproc: RX buffer descriptor (packet) processing
1932 * @priv: The DaVinci EMAC private adapter structure
1933 * @ch: RX channel number to process buffer descriptors for
1934 * @budget: number of packets allowed to process
1935 * @pending: indication to caller that packets are pending to process
1937 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
1938 * descriptor, sends the receive packet to upper layer, allocates a new SKB
1939 * and recycles the buffer descriptor (requeues it in hardware RX queue).
1940 * Only "budget" number of packets are processed and indication of pending
1941 * packets provided to the caller.
1943 * Returns number of packets processed (and indication of pending packets)
1945 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1947 unsigned long flags;
1949 u32 pkts_processed = 0;
1951 struct emac_rx_bd __iomem *curr_bd;
1952 struct emac_rx_bd __iomem *last_bd;
1953 struct emac_netpktobj *curr_pkt, pkt_obj;
1954 struct emac_netbufobj buf_obj;
1955 struct emac_netbufobj *rx_buf_obj;
1956 void *new_buf_token;
1957 struct emac_rxch *rxch = priv->rxch[ch];
1959 if (unlikely(1 == rxch->teardown_pending))
1962 spin_lock_irqsave(&priv->rx_lock, flags);
1963 pkt_obj.buf_list = &buf_obj;
1964 curr_pkt = &pkt_obj;
1965 curr_bd = rxch->active_queue_head;
1966 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1967 frame_status = curr_bd->mode;
1970 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1971 (pkts_processed < budget)) {
1973 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
1974 &new_buf_token, EMAC_DEF_RX_CH);
1975 if (unlikely(NULL == new_buffer)) {
1976 ++rxch->out_of_rx_buffers;
1977 goto end_emac_rx_bdproc;
1980 /* populate received packet data structure */
1981 rx_buf_obj = &curr_pkt->buf_list[0];
1982 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
1983 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
1984 rx_buf_obj->buf_token = curr_bd->buf_token;
1985 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
1986 curr_pkt->num_bufs = 1;
1987 curr_pkt->pkt_length =
1988 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
1989 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd));
1990 ++rxch->processed_bd;
1992 curr_bd = last_bd->next;
1993 rxch->active_queue_head = curr_bd;
1995 /* check if end of RX queue ? */
1996 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1998 ++rxch->mis_queued_packets;
1999 emac_write(EMAC_RXHDP(ch),
2000 emac_virt_to_phys(curr_bd));
2002 ++rxch->end_of_queue;
2003 rxch->queue_active = 0;
2008 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2011 /* return the packet to the user - BD ptr passed in
2012 * last parameter for potential *future* use */
2013 spin_unlock_irqrestore(&priv->rx_lock, flags);
2014 emac_net_rx_cb(priv, curr_pkt);
2015 spin_lock_irqsave(&priv->rx_lock, flags);
2016 curr_bd = rxch->active_queue_head;
2018 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2019 frame_status = curr_bd->mode;
2025 spin_unlock_irqrestore(&priv->rx_lock, flags);
2026 return pkts_processed;
2030 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2031 * @priv: The DaVinci EMAC private adapter structure
2033 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2034 * for packet reception and enables device interrupts and then NAPI
2036 * Returns success (0) or appropriate error code (none right now)
2038 static int emac_hw_enable(struct emac_priv *priv)
2040 u32 ch, val, mbp_enable, mac_control;
2043 emac_write(EMAC_SOFTRESET, 1);
2044 while (emac_read(EMAC_SOFTRESET))
2047 /* Disable interrupt & Set pacing for more interrupts initially */
2048 emac_int_disable(priv);
2050 /* Full duplex enable bit set when auto negotiation happens */
2052 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2053 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2054 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2055 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2056 emac_write(EMAC_MACCONTROL, mac_control);
2059 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2060 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2061 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2062 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2063 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2064 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2065 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2066 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2067 EMAC_RXMBP_PROMCH_SHIFT) |
2068 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2069 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2070 EMAC_RXMBP_BROADCH_SHIFT) |
2071 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2072 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2073 EMAC_RXMBP_MULTICH_SHIFT));
2074 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2075 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2076 EMAC_RX_MAX_LEN_MASK));
2077 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2078 EMAC_RX_BUFFER_OFFSET_MASK));
2079 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2080 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2081 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2083 val = emac_read(EMAC_TXCONTROL);
2084 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2085 emac_write(EMAC_TXCONTROL, val);
2086 val = emac_read(EMAC_RXCONTROL);
2087 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2088 emac_write(EMAC_RXCONTROL, val);
2089 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2091 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2092 emac_write(EMAC_TXHDP(ch), 0);
2093 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2095 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2096 struct emac_rxch *rxch = priv->rxch[ch];
2097 emac_setmac(priv, ch, rxch->mac_addr);
2098 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2099 rxch->queue_active = 1;
2100 emac_write(EMAC_RXHDP(ch),
2101 emac_virt_to_phys(rxch->active_queue_head));
2105 val = emac_read(EMAC_MACCONTROL);
2106 val |= (EMAC_MACCONTROL_GMIIEN);
2107 emac_write(EMAC_MACCONTROL, val);
2109 /* Enable NAPI and interrupts */
2110 napi_enable(&priv->napi);
2111 emac_int_enable(priv);
2117 * emac_poll: EMAC NAPI Poll function
2118 * @ndev: The DaVinci EMAC network adapter
2119 * @budget: Number of receive packets to process (as told by NAPI layer)
2121 * NAPI Poll function implemented to process packets as per budget. We check
2122 * the type of interrupt on the device and accordingly call the TX or RX
2123 * packet processing functions. We follow the budget for RX processing and
2124 * also put a cap on number of TX pkts processed through config param. The
2125 * NAPI schedule function is called if more packets pending.
2127 * Returns number of packets received (in most cases; else TX pkts - rarely)
2129 static int emac_poll(struct napi_struct *napi, int budget)
2132 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2133 struct net_device *ndev = priv->ndev;
2134 struct device *emac_dev = &ndev->dev;
2138 /* Check interrupt vectors and call packet processing */
2139 status = emac_read(EMAC_MACINVECTOR);
2141 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2143 if (priv->version == EMAC_VERSION_2)
2144 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2146 if (status & mask) {
2147 num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2148 EMAC_DEF_TX_MAX_SERVICE);
2149 } /* TX processing */
2154 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2156 if (priv->version == EMAC_VERSION_2)
2157 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2159 if (status & mask) {
2160 num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2161 } /* RX processing */
2163 if (num_pkts < budget) {
2164 napi_complete(napi);
2165 emac_int_enable(priv);
2168 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2169 if (priv->version == EMAC_VERSION_2)
2170 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2172 if (unlikely(status & mask)) {
2174 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2175 netif_stop_queue(ndev);
2176 napi_disable(&priv->napi);
2178 status = emac_read(EMAC_MACSTATUS);
2179 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2180 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2182 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2183 EMAC_MACSTATUS_TXERRCH_SHIFT);
2184 if (net_ratelimit()) {
2185 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2186 &emac_txhost_errcodes[cause][0], ch);
2189 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2190 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2192 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2193 EMAC_MACSTATUS_RXERRCH_SHIFT);
2194 if (netif_msg_hw(priv) && net_ratelimit())
2195 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2196 &emac_rxhost_errcodes[cause][0], ch);
2198 } /* Host error processing */
2203 #ifdef CONFIG_NET_POLL_CONTROLLER
2205 * emac_poll_controller: EMAC Poll controller function
2206 * @ndev: The DaVinci EMAC network adapter
2208 * Polled functionality used by netconsole and others in non interrupt mode
2211 void emac_poll_controller(struct net_device *ndev)
2213 struct emac_priv *priv = netdev_priv(ndev);
2215 emac_int_disable(priv);
2216 emac_irq(ndev->irq, ndev);
2217 emac_int_enable(priv);
2221 /* PHY/MII bus related */
2223 /* Wait until mdio is ready for next command */
2224 #define MDIO_WAIT_FOR_USER_ACCESS\
2225 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2226 MDIO_USERACCESS_GO) != 0)
2228 static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2230 unsigned int phy_data = 0;
2231 unsigned int phy_control;
2233 /* Wait until mdio is ready for next command */
2234 MDIO_WAIT_FOR_USER_ACCESS;
2236 phy_control = (MDIO_USERACCESS_GO |
2237 MDIO_USERACCESS_READ |
2238 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2239 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2240 (phy_data & MDIO_USERACCESS_DATA));
2241 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2243 /* Wait until mdio is ready for next command */
2244 MDIO_WAIT_FOR_USER_ACCESS;
2246 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2250 static int emac_mii_write(struct mii_bus *bus, int phy_id,
2251 int phy_reg, u16 phy_data)
2254 unsigned int control;
2256 /* until mdio is ready for next command */
2257 MDIO_WAIT_FOR_USER_ACCESS;
2259 control = (MDIO_USERACCESS_GO |
2260 MDIO_USERACCESS_WRITE |
2261 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2262 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2263 (phy_data & MDIO_USERACCESS_DATA));
2264 emac_mdio_write(MDIO_USERACCESS(0), control);
2269 static int emac_mii_reset(struct mii_bus *bus)
2271 unsigned int clk_div;
2272 int mdio_bus_freq = emac_bus_frequency;
2274 if (mdio_max_freq && mdio_bus_freq)
2275 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2279 clk_div &= MDIO_CONTROL_CLKDIV;
2281 /* Set enable and clock divider in MDIOControl */
2282 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2288 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2290 /* emac_driver: EMAC MII bus structure */
2292 static struct mii_bus *emac_mii;
2294 static void emac_adjust_link(struct net_device *ndev)
2296 struct emac_priv *priv = netdev_priv(ndev);
2297 struct phy_device *phydev = priv->phydev;
2298 unsigned long flags;
2301 spin_lock_irqsave(&priv->lock, flags);
2304 /* check the mode of operation - full/half duplex */
2305 if (phydev->duplex != priv->duplex) {
2307 priv->duplex = phydev->duplex;
2309 if (phydev->speed != priv->speed) {
2311 priv->speed = phydev->speed;
2318 } else if (priv->link) {
2325 emac_update_phystatus(priv);
2326 phy_print_status(priv->phydev);
2329 spin_unlock_irqrestore(&priv->lock, flags);
2332 /*************************************************************************
2333 * Linux Driver Model
2334 *************************************************************************/
2337 * emac_devioctl: EMAC adapter ioctl
2338 * @ndev: The DaVinci EMAC network adapter
2339 * @ifrq: request parameter
2340 * @cmd: command parameter
2342 * EMAC driver ioctl function
2344 * Returns success(0) or appropriate error code
2346 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2348 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2350 if (!(netif_running(ndev)))
2353 /* TODO: Add phy read and write and private statistics get feature */
2359 * emac_dev_open: EMAC device open
2360 * @ndev: The DaVinci EMAC network adapter
2362 * Called when system wants to start the interface. We init TX/RX channels
2363 * and enable the hardware for packet reception/transmission and start the
2366 * Returns 0 for a successful open, or appropriate error code
2368 static int emac_dev_open(struct net_device *ndev)
2370 struct device *emac_dev = &ndev->dev;
2373 struct resource *res;
2377 struct emac_priv *priv = netdev_priv(ndev);
2379 netif_carrier_off(ndev);
2380 for (cnt = 0; cnt <= ETH_ALEN; cnt++)
2381 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2383 /* Configuration items */
2384 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2386 /* Clear basic hardware */
2387 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2388 emac_write(EMAC_TXHDP(ch), 0);
2389 emac_write(EMAC_RXHDP(ch), 0);
2390 emac_write(EMAC_RXHDP(ch), 0);
2391 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2392 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2394 priv->mac_hash1 = 0;
2395 priv->mac_hash2 = 0;
2396 emac_write(EMAC_MACHASH1, 0);
2397 emac_write(EMAC_MACHASH2, 0);
2399 /* multi ch not supported - open 1 TX, 1RX ch by default */
2400 rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2402 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2405 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2407 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2413 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2414 for (i = res->start; i <= res->end; i++) {
2415 if (request_irq(i, emac_irq, IRQF_DISABLED,
2422 /* Start/Enable EMAC hardware */
2423 emac_hw_enable(priv);
2425 /* find the first phy */
2426 priv->phydev = NULL;
2427 if (priv->phy_mask) {
2428 emac_mii_reset(priv->mii_bus);
2429 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2430 if (priv->mii_bus->phy_map[phy_addr]) {
2431 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2436 if (!priv->phydev) {
2437 printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2441 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2442 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2444 if (IS_ERR(priv->phydev)) {
2445 printk(KERN_ERR "%s: Could not attach to PHY\n",
2447 return PTR_ERR(priv->phydev);
2454 printk(KERN_INFO "%s: attached PHY driver [%s] "
2455 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2456 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2457 priv->phydev->phy_id);
2459 /* No PHY , fix the link, speed and duplex settings */
2461 priv->speed = SPEED_100;
2462 priv->duplex = DUPLEX_FULL;
2463 emac_update_phystatus(priv);
2466 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2467 emac_dump_regs(priv);
2469 if (netif_msg_drv(priv))
2470 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2473 phy_start(priv->phydev);
2479 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2481 for (q = k; k >= 0; k--) {
2482 for (m = i; m >= res->start; m--)
2484 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2491 * emac_dev_stop: EMAC device stop
2492 * @ndev: The DaVinci EMAC network adapter
2494 * Called when system wants to stop or down the interface. We stop the network
2495 * queue, disable interrupts and cleanup TX/RX channels.
2497 * We return the statistics in net_device_stats structure pulled from emac
2499 static int emac_dev_stop(struct net_device *ndev)
2501 struct resource *res;
2504 struct emac_priv *priv = netdev_priv(ndev);
2505 struct device *emac_dev = &ndev->dev;
2507 /* inform the upper layers. */
2508 netif_stop_queue(ndev);
2509 napi_disable(&priv->napi);
2511 netif_carrier_off(ndev);
2512 emac_int_disable(priv);
2513 emac_stop_txch(priv, EMAC_DEF_TX_CH);
2514 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2515 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2516 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2517 emac_write(EMAC_SOFTRESET, 1);
2520 phy_disconnect(priv->phydev);
2523 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2524 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2525 free_irq(irq_num, priv->ndev);
2529 if (netif_msg_drv(priv))
2530 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2536 * emac_dev_getnetstats: EMAC get statistics function
2537 * @ndev: The DaVinci EMAC network adapter
2539 * Called when system wants to get statistics from the device.
2541 * We return the statistics in net_device_stats structure pulled from emac
2543 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2545 struct emac_priv *priv = netdev_priv(ndev);
2547 u32 stats_clear_mask;
2549 /* update emac hardware stats and reset the registers*/
2551 mac_control = emac_read(EMAC_MACCONTROL);
2553 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2554 stats_clear_mask = EMAC_STATS_CLR_MASK;
2556 stats_clear_mask = 0;
2558 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2559 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2561 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2562 emac_read(EMAC_TXSINGLECOLL) +
2563 emac_read(EMAC_TXMULTICOLL));
2564 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2565 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2566 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2568 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2569 emac_read(EMAC_RXJABBER) +
2570 emac_read(EMAC_RXUNDERSIZED));
2571 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2572 emac_write(EMAC_RXJABBER, stats_clear_mask);
2573 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2575 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2576 emac_read(EMAC_RXMOFOVERRUNS));
2577 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2578 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2580 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2581 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2583 priv->net_dev_stats.tx_carrier_errors +=
2584 emac_read(EMAC_TXCARRIERSENSE);
2585 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2587 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2588 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2590 return &priv->net_dev_stats;
2593 static const struct net_device_ops emac_netdev_ops = {
2594 .ndo_open = emac_dev_open,
2595 .ndo_stop = emac_dev_stop,
2596 .ndo_start_xmit = emac_dev_xmit,
2597 .ndo_set_multicast_list = emac_dev_mcast_set,
2598 .ndo_set_mac_address = emac_dev_setmac_addr,
2599 .ndo_do_ioctl = emac_devioctl,
2600 .ndo_tx_timeout = emac_dev_tx_timeout,
2601 .ndo_get_stats = emac_dev_getnetstats,
2602 #ifdef CONFIG_NET_POLL_CONTROLLER
2603 .ndo_poll_controller = emac_poll_controller,
2608 * davinci_emac_probe: EMAC device probe
2609 * @pdev: The DaVinci EMAC device that we are removing
2611 * Called when probing for emac devicesr. We get details of instances and
2612 * resource information from platform init and register a network device
2613 * and allocate resources necessary for driver to perform
2615 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2618 struct resource *res;
2619 struct net_device *ndev;
2620 struct emac_priv *priv;
2622 struct emac_platform_data *pdata;
2623 struct device *emac_dev;
2625 /* obtain emac clock from kernel */
2626 emac_clk = clk_get(&pdev->dev, NULL);
2627 if (IS_ERR(emac_clk)) {
2628 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2631 emac_bus_frequency = clk_get_rate(emac_clk);
2632 /* TODO: Probe PHY here if possible */
2634 ndev = alloc_etherdev(sizeof(struct emac_priv));
2636 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2641 platform_set_drvdata(pdev, ndev);
2642 priv = netdev_priv(ndev);
2645 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2647 spin_lock_init(&priv->tx_lock);
2648 spin_lock_init(&priv->rx_lock);
2649 spin_lock_init(&priv->lock);
2651 pdata = pdev->dev.platform_data;
2653 printk(KERN_ERR "DaVinci EMAC: No platfrom data\n");
2657 /* MAC addr and PHY mask , RMII enable info from platform_data */
2658 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2659 priv->phy_mask = pdata->phy_mask;
2660 priv->rmii_en = pdata->rmii_en;
2661 priv->version = pdata->version;
2662 emac_dev = &ndev->dev;
2663 /* Get EMAC platform data */
2664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2666 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2671 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2672 size = res->end - res->start + 1;
2673 if (!request_mem_region(res->start, size, ndev->name)) {
2674 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() \
2680 priv->remap_addr = ioremap(res->start, size);
2681 if (!priv->remap_addr) {
2682 dev_err(emac_dev, "Unable to map IO\n");
2684 release_mem_region(res->start, size);
2687 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2688 ndev->base_addr = (unsigned long)priv->remap_addr;
2690 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2691 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2692 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2694 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2696 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2700 ndev->irq = res->start;
2702 if (!is_valid_ether_addr(priv->mac_addr)) {
2703 /* Use random MAC if none passed */
2704 random_ether_addr(priv->mac_addr);
2705 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2706 __func__, priv->mac_addr);
2709 ndev->netdev_ops = &emac_netdev_ops;
2710 SET_ETHTOOL_OPS(ndev, ðtool_ops);
2711 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2713 clk_enable(emac_clk);
2715 /* register the network device */
2716 SET_NETDEV_DEV(ndev, &pdev->dev);
2717 rc = register_netdev(ndev);
2719 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2721 goto netdev_reg_err;
2725 /* MII/Phy intialisation, mdio bus registration */
2726 emac_mii = mdiobus_alloc();
2727 if (emac_mii == NULL) {
2728 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2730 goto mdio_alloc_err;
2733 priv->mii_bus = emac_mii;
2734 emac_mii->name = "emac-mii",
2735 emac_mii->read = emac_mii_read,
2736 emac_mii->write = emac_mii_write,
2737 emac_mii->reset = emac_mii_reset,
2738 emac_mii->irq = mii_irqs,
2739 emac_mii->phy_mask = ~(priv->phy_mask);
2740 emac_mii->parent = &pdev->dev;
2741 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2742 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2743 mdio_max_freq = pdata->mdio_max_freq;
2744 emac_mii->reset(emac_mii);
2746 /* Register the MII bus */
2747 rc = mdiobus_register(emac_mii);
2751 if (netif_msg_probe(priv)) {
2752 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2753 "(regs: %p, irq: %d)\n",
2754 (void *)priv->emac_base_phys, ndev->irq);
2759 mdiobus_free(emac_mii);
2763 clk_disable(emac_clk);
2765 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2766 release_mem_region(res->start, res->end - res->start + 1);
2767 iounmap(priv->remap_addr);
2776 * davinci_emac_remove: EMAC device remove
2777 * @pdev: The DaVinci EMAC device that we are removing
2779 * Called when removing the device driver. We disable clock usage and release
2780 * the resources taken up by the driver and unregister network device
2782 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2784 struct resource *res;
2785 struct net_device *ndev = platform_get_drvdata(pdev);
2786 struct emac_priv *priv = netdev_priv(ndev);
2788 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2790 platform_set_drvdata(pdev, NULL);
2791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2792 mdiobus_unregister(priv->mii_bus);
2793 mdiobus_free(priv->mii_bus);
2795 release_mem_region(res->start, res->end - res->start + 1);
2797 unregister_netdev(ndev);
2799 iounmap(priv->remap_addr);
2801 clk_disable(emac_clk);
2808 int davinci_emac_suspend(struct platform_device *pdev, pm_message_t state)
2810 struct net_device *dev = platform_get_drvdata(pdev);
2812 if (netif_running(dev))
2815 clk_disable(emac_clk);
2820 static int davinci_emac_resume(struct platform_device *pdev)
2822 struct net_device *dev = platform_get_drvdata(pdev);
2824 clk_enable(emac_clk);
2826 if (netif_running(dev))
2833 * davinci_emac_driver: EMAC platform driver structure
2835 static struct platform_driver davinci_emac_driver = {
2837 .name = "davinci_emac",
2838 .owner = THIS_MODULE,
2840 .probe = davinci_emac_probe,
2841 .remove = __devexit_p(davinci_emac_remove),
2842 .suspend = davinci_emac_suspend,
2843 .resume = davinci_emac_resume,
2847 * davinci_emac_init: EMAC driver module init
2849 * Called when initializing the driver. We register the driver with
2852 static int __init davinci_emac_init(void)
2854 return platform_driver_register(&davinci_emac_driver);
2856 late_initcall(davinci_emac_init);
2859 * davinci_emac_exit: EMAC driver module exit
2861 * Called when exiting the driver completely. We unregister the driver with
2862 * the platform and exit
2864 static void __exit davinci_emac_exit(void)
2866 platform_driver_unregister(&davinci_emac_driver);
2868 module_exit(davinci_emac_exit);
2870 MODULE_LICENSE("GPL");
2871 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2872 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2873 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");