2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
4 * Based on: mach-davinci/emac_defs.h
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #ifndef _DAVINCI_EMAC_H_
23 #define _DAVINCI_EMAC_H_
24 /* Ethernet Min/Max packet size */
25 #define EMAC_MIN_ETHERNET_PKT_SIZE 60
26 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518
27 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
28 #define EMAC_PKT_ALIGN 18
30 /* Number of RX packet buffers
31 * NOTE: Only 1 buffer supported as of now
33 #define EMAC_MAX_RX_BUFFERS 10
36 /***********************************************
37 ******** Internally used macros ***************
38 ***********************************************/
43 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and
44 * reserve space for 64 descriptors max
46 #define EMAC_RX_DESC_BASE 0x0
47 #define EMAC_TX_DESC_BASE 0x1000
49 /* EMAC Teardown value */
50 #define EMAC_TEARDOWN_VALUE 0xfffffffc
52 /* MII Status Register */
53 #define MII_STATUS_REG 1
55 /* Number of statistics registers */
56 #define EMAC_NUM_STATS 36
60 typedef volatile struct _emac_desc
62 u_int32_t next; /* Pointer to next descriptor
64 u_int8_t *buffer; /* Pointer to data buffer */
65 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
66 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
69 /* CPPI bit positions */
70 #define EMAC_CPPI_SOP_BIT (0x80000000)
71 #define EMAC_CPPI_EOP_BIT (0x40000000)
72 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
73 #define EMAC_CPPI_EOQ_BIT (0x10000000)
74 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
75 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
77 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
79 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
80 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
81 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
82 #define EMAC_MACCONTROL_GIGFORCE (1 << 17)
83 #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
85 #define EMAC_MAC_ADDR_MATCH (1 << 19)
86 #define EMAC_MAC_ADDR_IS_VALID (1 << 20)
88 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
89 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
92 #define MDIO_CONTROL_IDLE (0x80000000)
93 #define MDIO_CONTROL_ENABLE (0x40000000)
94 #define MDIO_CONTROL_FAULT_ENABLE (0x40000)
95 #define MDIO_CONTROL_FAULT (0x80000)
96 #define MDIO_USERACCESS0_GO (0x80000000)
97 #define MDIO_USERACCESS0_WRITE_READ (0x0)
98 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
99 #define MDIO_USERACCESS0_ACK (0x20000000)
101 /* Ethernet MAC Registers Structure */
112 dv_reg TXINTSTATMASKED;
114 dv_reg TXINTMASKCLEAR;
118 dv_reg RXINTSTATMASKED;
120 dv_reg RXINTMASKCLEAR;
121 dv_reg MACINTSTATRAW;
122 dv_reg MACINTSTATMASKED;
123 dv_reg MACINTMASKSET;
124 dv_reg MACINTMASKCLEAR;
128 dv_reg RXUNICASTCLEAR;
130 dv_reg RXBUFFEROFFSET;
131 dv_reg RXFILTERLOWTHRESH;
133 dv_reg RX0FLOWTHRESH;
134 dv_reg RX1FLOWTHRESH;
135 dv_reg RX2FLOWTHRESH;
136 dv_reg RX3FLOWTHRESH;
137 dv_reg RX4FLOWTHRESH;
138 dv_reg RX5FLOWTHRESH;
139 dv_reg RX6FLOWTHRESH;
140 dv_reg RX7FLOWTHRESH;
141 dv_reg RX0FREEBUFFER;
142 dv_reg RX1FREEBUFFER;
143 dv_reg RX2FREEBUFFER;
144 dv_reg RX3FREEBUFFER;
145 dv_reg RX4FREEBUFFER;
146 dv_reg RX5FREEBUFFER;
147 dv_reg RX6FREEBUFFER;
148 dv_reg RX7FREEBUFFER;
166 dv_reg RXBCASTFRAMES;
167 dv_reg RXMCASTFRAMES;
168 dv_reg RXPAUSEFRAMES;
170 dv_reg RXALIGNCODEERRORS;
176 dv_reg RXQOSFILTERED;
179 dv_reg TXBCASTFRAMES;
180 dv_reg TXMCASTFRAMES;
181 dv_reg TXPAUSEFRAMES;
186 dv_reg TXEXCESSIVECOLL;
189 dv_reg TXCARRIERSENSE;
195 dv_reg FRAME512T1023;
198 dv_reg RXSOFOVERRUNS;
199 dv_reg RXMOFOVERRUNS;
200 dv_reg RXDMAOVERRUNS;
240 /* EMAC Wrapper Registers Structure */
242 #ifdef DAVINCI_EMAC_VERSION2
258 dv_reg c0rxthreshstat;
262 dv_reg c1rxthreshstat;
266 dv_reg c2rxthreshstat;
277 u_int8_t RSVD0[4100];
283 /* EMAC MDIO Registers Structure */
290 dv_reg LINKINTMASKED;
293 dv_reg USERINTMASKED;
294 dv_reg USERINTMASKSET;
295 dv_reg USERINTMASKCLEAR;
303 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
304 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
308 int (*init)(int phy_addr);
309 int (*is_phy_connected)(int phy_addr);
310 int (*get_link_speed)(int phy_addr);
311 int (*auto_negotiate)(int phy_addr);
314 #endif /* _DAVINCI_EMAC_H_ */