2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
32 #include <net/switchdev.h>
43 /* BCM5365 MIB counters */
44 static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
81 /* BCM63xx MIB counters */
82 static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
130 static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
170 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
174 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
176 for (i = 0; i < 10; i++) {
179 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
180 if (!(vta & VTA_START_CMD))
183 usleep_range(100, 200);
189 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
190 struct b53_vlan *vlan)
196 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
197 VA_UNTAG_S_25) | vlan->members;
198 if (dev->core_rev >= 3)
199 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
201 entry |= VA_VALID_25;
204 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
205 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
206 VTA_RW_STATE_WR | VTA_RW_OP_EN);
207 } else if (is5365(dev)) {
211 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
212 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
214 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
215 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
216 VTA_RW_STATE_WR | VTA_RW_OP_EN);
218 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
219 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
220 (vlan->untag << VTE_UNTAG_S) | vlan->members);
222 b53_do_vlan_op(dev, VTA_CMD_WRITE);
225 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
226 vid, vlan->members, vlan->untag);
229 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
230 struct b53_vlan *vlan)
235 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
236 VTA_RW_STATE_RD | VTA_RW_OP_EN);
237 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
239 if (dev->core_rev >= 3)
240 vlan->valid = !!(entry & VA_VALID_25_R4);
242 vlan->valid = !!(entry & VA_VALID_25);
243 vlan->members = entry & VA_MEMBER_MASK;
244 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
246 } else if (is5365(dev)) {
249 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
250 VTA_RW_STATE_WR | VTA_RW_OP_EN);
251 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
253 vlan->valid = !!(entry & VA_VALID_65);
254 vlan->members = entry & VA_MEMBER_MASK;
255 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
259 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
260 b53_do_vlan_op(dev, VTA_CMD_READ);
261 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
262 vlan->members = entry & VTE_MEMBERS;
263 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
268 static void b53_set_forwarding(struct b53_device *dev, int enable)
272 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
275 mgmt |= SM_SW_FWD_EN;
277 mgmt &= ~SM_SW_FWD_EN;
279 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
282 static void b53_enable_vlan(struct b53_device *dev, bool enable)
284 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
286 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
287 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
288 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
290 if (is5325(dev) || is5365(dev)) {
291 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
292 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
293 } else if (is63xx(dev)) {
294 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
295 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
297 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
298 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
301 mgmt &= ~SM_SW_FWD_MODE;
304 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
305 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
306 vc4 &= ~VC4_ING_VID_CHECK_MASK;
307 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
308 vc5 |= VC5_DROP_VTABLE_MISS;
311 vc0 &= ~VC0_RESERVED_1;
313 if (is5325(dev) || is5365(dev))
314 vc1 |= VC1_RX_MCST_TAG_EN;
317 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
318 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
319 vc4 &= ~VC4_ING_VID_CHECK_MASK;
320 vc5 &= ~VC5_DROP_VTABLE_MISS;
322 if (is5325(dev) || is5365(dev))
323 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
325 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
327 if (is5325(dev) || is5365(dev))
328 vc1 &= ~VC1_RX_MCST_TAG_EN;
331 if (!is5325(dev) && !is5365(dev))
332 vc5 &= ~VC5_VID_FFF_EN;
334 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
335 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
337 if (is5325(dev) || is5365(dev)) {
338 /* enable the high 8 bit vid check on 5325 */
339 if (is5325(dev) && enable)
340 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
343 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
345 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
346 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
347 } else if (is63xx(dev)) {
348 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
349 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
350 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
352 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
353 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
354 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
357 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
360 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
363 u16 max_size = JMS_MIN_SIZE;
365 if (is5325(dev) || is5365(dev))
369 port_mask = dev->enabled_ports;
370 max_size = JMS_MAX_SIZE;
372 port_mask |= JPM_10_100_JUMBO_EN;
375 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
376 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
379 static int b53_flush_arl(struct b53_device *dev, u8 mask)
383 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
384 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
386 for (i = 0; i < 10; i++) {
389 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
392 if (!(fast_age_ctrl & FAST_AGE_DONE))
400 /* Only age dynamic entries (default behavior) */
401 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
405 static int b53_fast_age_port(struct b53_device *dev, int port)
407 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
409 return b53_flush_arl(dev, FAST_AGE_PORT);
412 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
414 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
416 return b53_flush_arl(dev, FAST_AGE_VLAN);
419 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
421 struct b53_device *dev = ds_to_priv(ds);
425 /* Enable the IMP port to be in the same VLAN as the other ports
426 * on a per-port basis such that we only have Port i and IMP in
429 b53_for_each_port(dev, i) {
430 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
431 pvlan |= BIT(cpu_port);
432 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
436 static int b53_enable_port(struct dsa_switch *ds, int port,
437 struct phy_device *phy)
439 struct b53_device *dev = ds_to_priv(ds);
440 unsigned int cpu_port = dev->cpu_port;
443 /* Clear the Rx and Tx disable bits and set to no spanning tree */
444 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
446 /* Set this port, and only this one to be in the default VLAN,
447 * if member of a bridge, restore its membership prior to
448 * bringing down this port.
450 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
453 pvlan |= dev->ports[port].vlan_ctl_mask;
454 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
456 b53_imp_vlan_setup(ds, cpu_port);
461 static void b53_disable_port(struct dsa_switch *ds, int port,
462 struct phy_device *phy)
464 struct b53_device *dev = ds_to_priv(ds);
467 /* Disable Tx/Rx for the port */
468 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
469 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
470 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
473 static void b53_enable_cpu_port(struct b53_device *dev)
475 unsigned int cpu_port = dev->cpu_port;
478 /* BCM5325 CPU port is at 8 */
479 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
480 cpu_port = B53_CPU_PORT;
482 port_ctrl = PORT_CTRL_RX_BCST_EN |
483 PORT_CTRL_RX_MCST_EN |
484 PORT_CTRL_RX_UCST_EN;
485 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
488 static void b53_enable_mib(struct b53_device *dev)
492 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
493 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
494 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
497 static int b53_configure_vlan(struct b53_device *dev)
499 struct b53_vlan vl = { 0 };
502 /* clear all vlan entries */
503 if (is5325(dev) || is5365(dev)) {
504 for (i = 1; i < dev->num_vlans; i++)
505 b53_set_vlan_entry(dev, i, &vl);
507 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
510 b53_enable_vlan(dev, false);
512 b53_for_each_port(dev, i)
513 b53_write16(dev, B53_VLAN_PAGE,
514 B53_VLAN_PORT_DEF_TAG(i), 1);
516 if (!is5325(dev) && !is5365(dev))
517 b53_set_jumbo(dev, dev->enable_jumbo, false);
522 static void b53_switch_reset_gpio(struct b53_device *dev)
524 int gpio = dev->reset_gpio;
529 /* Reset sequence: RESET low(50ms)->high(20ms)
531 gpio_set_value(gpio, 0);
534 gpio_set_value(gpio, 1);
537 dev->current_page = 0xff;
540 static int b53_switch_reset(struct b53_device *dev)
544 b53_switch_reset_gpio(dev);
547 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
548 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
551 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
553 if (!(mgmt & SM_SW_FWD_EN)) {
554 mgmt &= ~SM_SW_FWD_MODE;
555 mgmt |= SM_SW_FWD_EN;
557 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
558 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
560 if (!(mgmt & SM_SW_FWD_EN)) {
561 dev_err(dev->dev, "Failed to enable switch!\n");
568 return b53_flush_arl(dev, FAST_AGE_STATIC);
571 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
573 struct b53_device *priv = ds_to_priv(ds);
577 if (priv->ops->phy_read16)
578 ret = priv->ops->phy_read16(priv, addr, reg, &value);
580 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
583 return ret ? ret : value;
586 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
588 struct b53_device *priv = ds_to_priv(ds);
590 if (priv->ops->phy_write16)
591 return priv->ops->phy_write16(priv, addr, reg, val);
593 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
596 static int b53_reset_switch(struct b53_device *priv)
599 priv->enable_jumbo = false;
601 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
602 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
604 return b53_switch_reset(priv);
607 static int b53_apply_config(struct b53_device *priv)
609 /* disable switching */
610 b53_set_forwarding(priv, 0);
612 b53_configure_vlan(priv);
614 /* enable switching */
615 b53_set_forwarding(priv, 1);
620 static void b53_reset_mib(struct b53_device *priv)
624 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
626 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
628 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
632 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
636 else if (is63xx(dev))
637 return b53_mibs_63xx;
642 static unsigned int b53_get_mib_size(struct b53_device *dev)
645 return B53_MIBS_65_SIZE;
646 else if (is63xx(dev))
647 return B53_MIBS_63XX_SIZE;
649 return B53_MIBS_SIZE;
652 static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
654 struct b53_device *dev = ds_to_priv(ds);
655 const struct b53_mib_desc *mibs = b53_get_mib(dev);
656 unsigned int mib_size = b53_get_mib_size(dev);
659 for (i = 0; i < mib_size; i++)
660 memcpy(data + i * ETH_GSTRING_LEN,
661 mibs[i].name, ETH_GSTRING_LEN);
664 static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
667 struct b53_device *dev = ds_to_priv(ds);
668 const struct b53_mib_desc *mibs = b53_get_mib(dev);
669 unsigned int mib_size = b53_get_mib_size(dev);
670 const struct b53_mib_desc *s;
674 if (is5365(dev) && port == 5)
677 mutex_lock(&dev->stats_mutex);
679 for (i = 0; i < mib_size; i++) {
683 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
687 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
694 mutex_unlock(&dev->stats_mutex);
697 static int b53_get_sset_count(struct dsa_switch *ds)
699 struct b53_device *dev = ds_to_priv(ds);
701 return b53_get_mib_size(dev);
704 static int b53_set_addr(struct dsa_switch *ds, u8 *addr)
709 static int b53_setup(struct dsa_switch *ds)
711 struct b53_device *dev = ds_to_priv(ds);
715 ret = b53_reset_switch(dev);
717 dev_err(ds->dev, "failed to reset switch\n");
723 ret = b53_apply_config(dev);
725 dev_err(ds->dev, "failed to apply configuration\n");
727 for (port = 0; port < dev->num_ports; port++) {
728 if (BIT(port) & ds->enabled_port_mask)
729 b53_enable_port(ds, port, NULL);
730 else if (dsa_is_cpu_port(ds, port))
731 b53_enable_cpu_port(dev);
733 b53_disable_port(ds, port, NULL);
739 static void b53_adjust_link(struct dsa_switch *ds, int port,
740 struct phy_device *phydev)
742 struct b53_device *dev = ds_to_priv(ds);
743 u8 rgmii_ctrl = 0, reg = 0, off;
745 if (!phy_is_pseudo_fixed_link(phydev))
748 /* Override the port settings */
749 if (port == dev->cpu_port) {
750 off = B53_PORT_OVERRIDE_CTRL;
751 reg = PORT_OVERRIDE_EN;
753 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
757 /* Set the link UP */
759 reg |= PORT_OVERRIDE_LINK;
761 if (phydev->duplex == DUPLEX_FULL)
762 reg |= PORT_OVERRIDE_FULL_DUPLEX;
764 switch (phydev->speed) {
766 reg |= PORT_OVERRIDE_SPEED_2000M;
769 reg |= PORT_OVERRIDE_SPEED_1000M;
772 reg |= PORT_OVERRIDE_SPEED_100M;
775 reg |= PORT_OVERRIDE_SPEED_10M;
778 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
782 /* Enable flow control on BCM5301x's CPU port */
783 if (is5301x(dev) && port == dev->cpu_port)
784 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
787 if (phydev->asym_pause)
788 reg |= PORT_OVERRIDE_TX_FLOW;
789 reg |= PORT_OVERRIDE_RX_FLOW;
792 b53_write8(dev, B53_CTRL_PAGE, off, reg);
794 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
796 off = B53_RGMII_CTRL_IMP;
798 off = B53_RGMII_CTRL_P(port);
800 /* Configure the port RGMII clock delay by DLL disabled and
801 * tx_clk aligned timing (restoring to reset defaults)
803 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
804 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
805 RGMII_CTRL_TIMING_SEL);
807 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
808 * sure that we enable the port TX clock internal delay to
809 * account for this internal delay that is inserted, otherwise
810 * the switch won't be able to receive correctly.
812 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
813 * any delay neither on transmission nor reception, so the
814 * BCM53125 must also be configured accordingly to account for
815 * the lack of delay and introduce
817 * The BCM53125 switch has its RX clock and TX clock control
818 * swapped, hence the reason why we modify the TX clock path in
821 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
822 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
823 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
824 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
825 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
826 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
828 dev_info(ds->dev, "Configured port %d for %s\n", port,
829 phy_modes(phydev->interface));
832 /* configure MII port if necessary */
834 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
837 /* reverse mii needs to be enabled */
838 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
839 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
840 reg | PORT_OVERRIDE_RV_MII_25);
841 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
844 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
846 "Failed to enable reverse MII mode\n");
850 } else if (is5301x(dev)) {
851 if (port != dev->cpu_port) {
852 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
855 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
856 gmii_po |= GMII_PO_LINK |
861 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
866 static int b53_vlan_filtering(struct dsa_switch *ds, int port,
872 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
873 const struct switchdev_obj_port_vlan *vlan,
874 struct switchdev_trans *trans)
876 struct b53_device *dev = ds_to_priv(ds);
878 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
881 if (vlan->vid_end > dev->num_vlans)
884 b53_enable_vlan(dev, true);
889 static void b53_vlan_add(struct dsa_switch *ds, int port,
890 const struct switchdev_obj_port_vlan *vlan,
891 struct switchdev_trans *trans)
893 struct b53_device *dev = ds_to_priv(ds);
894 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
895 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
896 unsigned int cpu_port = dev->cpu_port;
900 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
901 vl = &dev->vlans[vid];
903 b53_get_vlan_entry(dev, vid, vl);
905 vl->members |= BIT(port) | BIT(cpu_port);
907 vl->untag |= BIT(port) | BIT(cpu_port);
909 vl->untag &= ~(BIT(port) | BIT(cpu_port));
911 b53_set_vlan_entry(dev, vid, vl);
912 b53_fast_age_vlan(dev, vid);
916 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
918 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port),
920 b53_fast_age_vlan(dev, vid);
924 static int b53_vlan_del(struct dsa_switch *ds, int port,
925 const struct switchdev_obj_port_vlan *vlan)
927 struct b53_device *dev = ds_to_priv(ds);
928 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
929 unsigned int cpu_port = dev->cpu_port;
934 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
936 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
937 vl = &dev->vlans[vid];
939 b53_get_vlan_entry(dev, vid, vl);
941 vl->members &= ~BIT(port);
942 if ((vl->members & BIT(cpu_port)) == BIT(cpu_port))
946 if (is5325(dev) || is5365(dev))
953 vl->untag &= ~(BIT(port));
954 if ((vl->untag & BIT(cpu_port)) == BIT(cpu_port))
958 b53_set_vlan_entry(dev, vid, vl);
959 b53_fast_age_vlan(dev, vid);
962 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
963 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), pvid);
964 b53_fast_age_vlan(dev, pvid);
969 static int b53_vlan_dump(struct dsa_switch *ds, int port,
970 struct switchdev_obj_port_vlan *vlan,
971 int (*cb)(struct switchdev_obj *obj))
973 struct b53_device *dev = ds_to_priv(ds);
974 u16 vid, vid_start = 0, pvid;
978 if (is5325(dev) || is5365(dev))
981 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
983 /* Use our software cache for dumps, since we do not have any HW
984 * operation returning only the used/valid VLANs
986 for (vid = vid_start; vid < dev->num_vlans; vid++) {
987 vl = &dev->vlans[vid];
992 if (!(vl->members & BIT(port)))
995 vlan->vid_begin = vlan->vid_end = vid;
998 if (vl->untag & BIT(port))
999 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1001 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1003 err = cb(&vlan->obj);
1011 /* Address Resolution Logic routines */
1012 static int b53_arl_op_wait(struct b53_device *dev)
1014 unsigned int timeout = 10;
1018 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1019 if (!(reg & ARLTBL_START_DONE))
1022 usleep_range(1000, 2000);
1023 } while (timeout--);
1025 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1030 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1037 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1038 reg |= ARLTBL_START_DONE;
1043 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1045 return b53_arl_op_wait(dev);
1048 static int b53_arl_read(struct b53_device *dev, u64 mac,
1049 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1055 ret = b53_arl_op_wait(dev);
1060 for (i = 0; i < dev->num_arl_entries; i++) {
1064 b53_read64(dev, B53_ARLIO_PAGE,
1065 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1066 b53_read32(dev, B53_ARLIO_PAGE,
1067 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1068 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1070 if (!(fwd_entry & ARLTBL_VALID))
1072 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1080 static int b53_arl_op(struct b53_device *dev, int op, int port,
1081 const unsigned char *addr, u16 vid, bool is_valid)
1083 struct b53_arl_entry ent;
1085 u64 mac, mac_vid = 0;
1089 /* Convert the array into a 64-bit MAC */
1090 mac = b53_mac_to_u64(addr);
1092 /* Perform a read for the given MAC and VID */
1093 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1094 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1096 /* Issue a read operation for this MAC */
1097 ret = b53_arl_rw_op(dev, 1);
1101 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1102 /* If this is a read, just finish now */
1106 /* We could not find a matching MAC, so reset to a new entry */
1112 memset(&ent, 0, sizeof(ent));
1114 ent.is_valid = is_valid;
1116 ent.is_static = true;
1117 memcpy(ent.mac, addr, ETH_ALEN);
1118 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1120 b53_write64(dev, B53_ARLIO_PAGE,
1121 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1122 b53_write32(dev, B53_ARLIO_PAGE,
1123 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1125 return b53_arl_rw_op(dev, 0);
1128 static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1129 const struct switchdev_obj_port_fdb *fdb,
1130 struct switchdev_trans *trans)
1132 struct b53_device *priv = ds_to_priv(ds);
1134 /* 5325 and 5365 require some more massaging, but could
1135 * be supported eventually
1137 if (is5325(priv) || is5365(priv))
1143 static void b53_fdb_add(struct dsa_switch *ds, int port,
1144 const struct switchdev_obj_port_fdb *fdb,
1145 struct switchdev_trans *trans)
1147 struct b53_device *priv = ds_to_priv(ds);
1149 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1150 pr_err("%s: failed to add MAC address\n", __func__);
1153 static int b53_fdb_del(struct dsa_switch *ds, int port,
1154 const struct switchdev_obj_port_fdb *fdb)
1156 struct b53_device *priv = ds_to_priv(ds);
1158 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1161 static int b53_arl_search_wait(struct b53_device *dev)
1163 unsigned int timeout = 1000;
1167 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1168 if (!(reg & ARL_SRCH_STDN))
1171 if (reg & ARL_SRCH_VLID)
1174 usleep_range(1000, 2000);
1175 } while (timeout--);
1180 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1181 struct b53_arl_entry *ent)
1186 b53_read64(dev, B53_ARLIO_PAGE,
1187 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1188 b53_read32(dev, B53_ARLIO_PAGE,
1189 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1190 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1193 static int b53_fdb_copy(struct net_device *dev, int port,
1194 const struct b53_arl_entry *ent,
1195 struct switchdev_obj_port_fdb *fdb,
1196 int (*cb)(struct switchdev_obj *obj))
1201 if (port != ent->port)
1204 ether_addr_copy(fdb->addr, ent->mac);
1205 fdb->vid = ent->vid;
1206 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1208 return cb(&fdb->obj);
1211 static int b53_fdb_dump(struct dsa_switch *ds, int port,
1212 struct switchdev_obj_port_fdb *fdb,
1213 int (*cb)(struct switchdev_obj *obj))
1215 struct b53_device *priv = ds_to_priv(ds);
1216 struct net_device *dev = ds->ports[port].netdev;
1217 struct b53_arl_entry results[2];
1218 unsigned int count = 0;
1222 /* Start search operation */
1223 reg = ARL_SRCH_STDN;
1224 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1227 ret = b53_arl_search_wait(priv);
1231 b53_arl_search_rd(priv, 0, &results[0]);
1232 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1236 if (priv->num_arl_entries > 2) {
1237 b53_arl_search_rd(priv, 1, &results[1]);
1238 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1242 if (!results[0].is_valid && !results[1].is_valid)
1246 } while (count++ < 1024);
1251 static int b53_br_join(struct dsa_switch *ds, int port,
1252 struct net_device *bridge)
1254 struct b53_device *dev = ds_to_priv(ds);
1258 dev->ports[port].bridge_dev = bridge;
1259 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1261 b53_for_each_port(dev, i) {
1262 if (dev->ports[i].bridge_dev != bridge)
1265 /* Add this local port to the remote port VLAN control
1266 * membership and update the remote port bitmask
1268 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1270 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1271 dev->ports[i].vlan_ctl_mask = reg;
1276 /* Configure the local port VLAN control membership to include
1277 * remote ports and update the local port bitmask
1279 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1280 dev->ports[port].vlan_ctl_mask = pvlan;
1285 static void b53_br_leave(struct dsa_switch *ds, int port)
1287 struct b53_device *dev = ds_to_priv(ds);
1288 struct net_device *bridge = dev->ports[port].bridge_dev;
1289 struct b53_vlan *vl = &dev->vlans[0];
1291 u16 pvlan, reg, pvid;
1293 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1295 b53_for_each_port(dev, i) {
1296 /* Don't touch the remaining ports */
1297 if (dev->ports[i].bridge_dev != bridge)
1300 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1302 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1303 dev->ports[port].vlan_ctl_mask = reg;
1305 /* Prevent self removal to preserve isolation */
1310 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1311 dev->ports[port].vlan_ctl_mask = pvlan;
1312 dev->ports[port].bridge_dev = NULL;
1314 if (is5325(dev) || is5365(dev))
1319 b53_get_vlan_entry(dev, pvid, vl);
1320 vl->members |= BIT(port) | BIT(dev->cpu_port);
1321 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1322 b53_set_vlan_entry(dev, pvid, vl);
1325 static void b53_br_set_stp_state(struct dsa_switch *ds, int port,
1328 struct b53_device *dev = ds_to_priv(ds);
1329 u8 hw_state, cur_hw_state;
1332 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1333 cur_hw_state = reg & PORT_CTRL_STP_STATE_MASK;
1336 case BR_STATE_DISABLED:
1337 hw_state = PORT_CTRL_DIS_STATE;
1339 case BR_STATE_LISTENING:
1340 hw_state = PORT_CTRL_LISTEN_STATE;
1342 case BR_STATE_LEARNING:
1343 hw_state = PORT_CTRL_LEARN_STATE;
1345 case BR_STATE_FORWARDING:
1346 hw_state = PORT_CTRL_FWD_STATE;
1348 case BR_STATE_BLOCKING:
1349 hw_state = PORT_CTRL_BLOCK_STATE;
1352 dev_err(ds->dev, "invalid STP state: %d\n", state);
1356 /* Fast-age ARL entries if we are moving a port from Learning or
1357 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
1360 if (cur_hw_state != hw_state) {
1361 if (cur_hw_state >= PORT_CTRL_LEARN_STATE &&
1362 hw_state <= PORT_CTRL_LISTEN_STATE) {
1363 if (b53_fast_age_port(dev, port)) {
1364 dev_err(ds->dev, "fast ageing failed\n");
1370 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1371 reg &= ~PORT_CTRL_STP_STATE_MASK;
1373 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1376 static struct dsa_switch_driver b53_switch_ops = {
1377 .tag_protocol = DSA_TAG_PROTO_NONE,
1379 .set_addr = b53_set_addr,
1380 .get_strings = b53_get_strings,
1381 .get_ethtool_stats = b53_get_ethtool_stats,
1382 .get_sset_count = b53_get_sset_count,
1383 .phy_read = b53_phy_read16,
1384 .phy_write = b53_phy_write16,
1385 .adjust_link = b53_adjust_link,
1386 .port_enable = b53_enable_port,
1387 .port_disable = b53_disable_port,
1388 .port_bridge_join = b53_br_join,
1389 .port_bridge_leave = b53_br_leave,
1390 .port_stp_state_set = b53_br_set_stp_state,
1391 .port_vlan_filtering = b53_vlan_filtering,
1392 .port_vlan_prepare = b53_vlan_prepare,
1393 .port_vlan_add = b53_vlan_add,
1394 .port_vlan_del = b53_vlan_del,
1395 .port_vlan_dump = b53_vlan_dump,
1396 .port_fdb_prepare = b53_fdb_prepare,
1397 .port_fdb_dump = b53_fdb_dump,
1398 .port_fdb_add = b53_fdb_add,
1399 .port_fdb_del = b53_fdb_del,
1402 struct b53_chip_data {
1404 const char *dev_name;
1415 #define B53_VTA_REGS \
1416 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1417 #define B53_VTA_REGS_9798 \
1418 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1419 #define B53_VTA_REGS_63XX \
1420 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1422 static const struct b53_chip_data b53_switch_chips[] = {
1424 .chip_id = BCM5325_DEVICE_ID,
1425 .dev_name = "BCM5325",
1427 .enabled_ports = 0x1f,
1429 .cpu_port = B53_CPU_PORT_25,
1430 .duplex_reg = B53_DUPLEX_STAT_FE,
1433 .chip_id = BCM5365_DEVICE_ID,
1434 .dev_name = "BCM5365",
1436 .enabled_ports = 0x1f,
1438 .cpu_port = B53_CPU_PORT_25,
1439 .duplex_reg = B53_DUPLEX_STAT_FE,
1442 .chip_id = BCM5395_DEVICE_ID,
1443 .dev_name = "BCM5395",
1445 .enabled_ports = 0x1f,
1447 .cpu_port = B53_CPU_PORT,
1448 .vta_regs = B53_VTA_REGS,
1449 .duplex_reg = B53_DUPLEX_STAT_GE,
1450 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1451 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1454 .chip_id = BCM5397_DEVICE_ID,
1455 .dev_name = "BCM5397",
1457 .enabled_ports = 0x1f,
1459 .cpu_port = B53_CPU_PORT,
1460 .vta_regs = B53_VTA_REGS_9798,
1461 .duplex_reg = B53_DUPLEX_STAT_GE,
1462 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1463 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1466 .chip_id = BCM5398_DEVICE_ID,
1467 .dev_name = "BCM5398",
1469 .enabled_ports = 0x7f,
1471 .cpu_port = B53_CPU_PORT,
1472 .vta_regs = B53_VTA_REGS_9798,
1473 .duplex_reg = B53_DUPLEX_STAT_GE,
1474 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1475 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1478 .chip_id = BCM53115_DEVICE_ID,
1479 .dev_name = "BCM53115",
1481 .enabled_ports = 0x1f,
1483 .vta_regs = B53_VTA_REGS,
1484 .cpu_port = B53_CPU_PORT,
1485 .duplex_reg = B53_DUPLEX_STAT_GE,
1486 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1487 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1490 .chip_id = BCM53125_DEVICE_ID,
1491 .dev_name = "BCM53125",
1493 .enabled_ports = 0xff,
1494 .cpu_port = B53_CPU_PORT,
1495 .vta_regs = B53_VTA_REGS,
1496 .duplex_reg = B53_DUPLEX_STAT_GE,
1497 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1498 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1501 .chip_id = BCM53128_DEVICE_ID,
1502 .dev_name = "BCM53128",
1504 .enabled_ports = 0x1ff,
1506 .cpu_port = B53_CPU_PORT,
1507 .vta_regs = B53_VTA_REGS,
1508 .duplex_reg = B53_DUPLEX_STAT_GE,
1509 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1510 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1513 .chip_id = BCM63XX_DEVICE_ID,
1514 .dev_name = "BCM63xx",
1516 .enabled_ports = 0, /* pdata must provide them */
1518 .cpu_port = B53_CPU_PORT,
1519 .vta_regs = B53_VTA_REGS_63XX,
1520 .duplex_reg = B53_DUPLEX_STAT_63XX,
1521 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1522 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1525 .chip_id = BCM53010_DEVICE_ID,
1526 .dev_name = "BCM53010",
1528 .enabled_ports = 0x1f,
1530 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1531 .vta_regs = B53_VTA_REGS,
1532 .duplex_reg = B53_DUPLEX_STAT_GE,
1533 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1534 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1537 .chip_id = BCM53011_DEVICE_ID,
1538 .dev_name = "BCM53011",
1540 .enabled_ports = 0x1bf,
1542 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1543 .vta_regs = B53_VTA_REGS,
1544 .duplex_reg = B53_DUPLEX_STAT_GE,
1545 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1546 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1549 .chip_id = BCM53012_DEVICE_ID,
1550 .dev_name = "BCM53012",
1552 .enabled_ports = 0x1bf,
1554 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1555 .vta_regs = B53_VTA_REGS,
1556 .duplex_reg = B53_DUPLEX_STAT_GE,
1557 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1558 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1561 .chip_id = BCM53018_DEVICE_ID,
1562 .dev_name = "BCM53018",
1564 .enabled_ports = 0x1f,
1566 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1567 .vta_regs = B53_VTA_REGS,
1568 .duplex_reg = B53_DUPLEX_STAT_GE,
1569 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1570 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1573 .chip_id = BCM53019_DEVICE_ID,
1574 .dev_name = "BCM53019",
1576 .enabled_ports = 0x1f,
1578 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1579 .vta_regs = B53_VTA_REGS,
1580 .duplex_reg = B53_DUPLEX_STAT_GE,
1581 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1582 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1586 static int b53_switch_init(struct b53_device *dev)
1588 struct dsa_switch *ds = dev->ds;
1592 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1593 const struct b53_chip_data *chip = &b53_switch_chips[i];
1595 if (chip->chip_id == dev->chip_id) {
1596 if (!dev->enabled_ports)
1597 dev->enabled_ports = chip->enabled_ports;
1598 dev->name = chip->dev_name;
1599 dev->duplex_reg = chip->duplex_reg;
1600 dev->vta_regs[0] = chip->vta_regs[0];
1601 dev->vta_regs[1] = chip->vta_regs[1];
1602 dev->vta_regs[2] = chip->vta_regs[2];
1603 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1604 ds->drv = &b53_switch_ops;
1605 dev->cpu_port = chip->cpu_port;
1606 dev->num_vlans = chip->vlans;
1607 dev->num_arl_entries = chip->arl_entries;
1612 /* check which BCM5325x version we have */
1616 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1618 /* check reserved bits */
1624 /* BCM5325F - do not use port 4 */
1625 dev->enabled_ports &= ~BIT(4);
1628 /* On the BCM47XX SoCs this is the supported internal switch.*/
1629 #ifndef CONFIG_BCM47XX
1636 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1639 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1640 /* use second IMP port if GMII is enabled */
1641 if (strap_value & SV_GMII_CTRL_115)
1645 /* cpu port is always last */
1646 dev->num_ports = dev->cpu_port + 1;
1647 dev->enabled_ports |= BIT(dev->cpu_port);
1649 dev->ports = devm_kzalloc(dev->dev,
1650 sizeof(struct b53_port) * dev->num_ports,
1655 dev->vlans = devm_kzalloc(dev->dev,
1656 sizeof(struct b53_vlan) * dev->num_vlans,
1661 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1662 if (dev->reset_gpio >= 0) {
1663 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1664 GPIOF_OUT_INIT_HIGH, "robo_reset");
1672 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1675 struct dsa_switch *ds;
1676 struct b53_device *dev;
1678 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1682 dev = (struct b53_device *)(ds + 1);
1691 mutex_init(&dev->reg_mutex);
1692 mutex_init(&dev->stats_mutex);
1696 EXPORT_SYMBOL(b53_switch_alloc);
1698 int b53_switch_detect(struct b53_device *dev)
1705 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1711 /* BCM5325 and BCM5365 do not have this register so reads
1712 * return 0. But the read operation did succeed, so assume this
1715 * Next check if we can write to the 5325's VTA register; for
1716 * 5365 it is read only.
1718 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1719 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1722 dev->chip_id = BCM5325_DEVICE_ID;
1724 dev->chip_id = BCM5365_DEVICE_ID;
1726 case BCM5395_DEVICE_ID:
1727 case BCM5397_DEVICE_ID:
1728 case BCM5398_DEVICE_ID:
1732 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1737 case BCM53115_DEVICE_ID:
1738 case BCM53125_DEVICE_ID:
1739 case BCM53128_DEVICE_ID:
1740 case BCM53010_DEVICE_ID:
1741 case BCM53011_DEVICE_ID:
1742 case BCM53012_DEVICE_ID:
1743 case BCM53018_DEVICE_ID:
1744 case BCM53019_DEVICE_ID:
1745 dev->chip_id = id32;
1748 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1754 if (dev->chip_id == BCM5325_DEVICE_ID)
1755 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1758 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1761 EXPORT_SYMBOL(b53_switch_detect);
1763 int b53_switch_register(struct b53_device *dev)
1768 dev->chip_id = dev->pdata->chip_id;
1769 dev->enabled_ports = dev->pdata->enabled_ports;
1772 if (!dev->chip_id && b53_switch_detect(dev))
1775 ret = b53_switch_init(dev);
1779 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1781 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1783 EXPORT_SYMBOL(b53_switch_register);
1785 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1786 MODULE_DESCRIPTION("B53 switch library");
1787 MODULE_LICENSE("Dual BSD/GPL");