drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/if_bridge.h>
  31 #include <net/dsa.h>
  32 #include <net/switchdev.h>
  33
  34 #include "b53_regs.h"
  35 #include "b53_priv.h"
  36
  37 struct b53_mib_desc {
  38         u8 size;
  39         u8 offset;
  40         const char *name;
  41 };
  42
  43 /* BCM5365 MIB counters */
  44 static const struct b53_mib_desc b53_mibs_65[] = {
  45         { 8, 0x00, "TxOctets" },
  46         { 4, 0x08, "TxDropPkts" },
  47         { 4, 0x10, "TxBroadcastPkts" },
  48         { 4, 0x14, "TxMulticastPkts" },
  49         { 4, 0x18, "TxUnicastPkts" },
  50         { 4, 0x1c, "TxCollisions" },
  51         { 4, 0x20, "TxSingleCollision" },
  52         { 4, 0x24, "TxMultipleCollision" },
  53         { 4, 0x28, "TxDeferredTransmit" },
  54         { 4, 0x2c, "TxLateCollision" },
  55         { 4, 0x30, "TxExcessiveCollision" },
  56         { 4, 0x38, "TxPausePkts" },
  57         { 8, 0x44, "RxOctets" },
  58         { 4, 0x4c, "RxUndersizePkts" },
  59         { 4, 0x50, "RxPausePkts" },
  60         { 4, 0x54, "Pkts64Octets" },
  61         { 4, 0x58, "Pkts65to127Octets" },
  62         { 4, 0x5c, "Pkts128to255Octets" },
  63         { 4, 0x60, "Pkts256to511Octets" },
  64         { 4, 0x64, "Pkts512to1023Octets" },
  65         { 4, 0x68, "Pkts1024to1522Octets" },
  66         { 4, 0x6c, "RxOversizePkts" },
  67         { 4, 0x70, "RxJabbers" },
  68         { 4, 0x74, "RxAlignmentErrors" },
  69         { 4, 0x78, "RxFCSErrors" },
  70         { 8, 0x7c, "RxGoodOctets" },
  71         { 4, 0x84, "RxDropPkts" },
  72         { 4, 0x88, "RxUnicastPkts" },
  73         { 4, 0x8c, "RxMulticastPkts" },
  74         { 4, 0x90, "RxBroadcastPkts" },
  75         { 4, 0x94, "RxSAChanges" },
  76         { 4, 0x98, "RxFragments" },
  77 };
  78
  79 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  80
  81 /* BCM63xx MIB counters */
  82 static const struct b53_mib_desc b53_mibs_63xx[] = {
  83         { 8, 0x00, "TxOctets" },
  84         { 4, 0x08, "TxDropPkts" },
  85         { 4, 0x0c, "TxQoSPkts" },
  86         { 4, 0x10, "TxBroadcastPkts" },
  87         { 4, 0x14, "TxMulticastPkts" },
  88         { 4, 0x18, "TxUnicastPkts" },
  89         { 4, 0x1c, "TxCollisions" },
  90         { 4, 0x20, "TxSingleCollision" },
  91         { 4, 0x24, "TxMultipleCollision" },
  92         { 4, 0x28, "TxDeferredTransmit" },
  93         { 4, 0x2c, "TxLateCollision" },
  94         { 4, 0x30, "TxExcessiveCollision" },
  95         { 4, 0x38, "TxPausePkts" },
  96         { 8, 0x3c, "TxQoSOctets" },
  97         { 8, 0x44, "RxOctets" },
  98         { 4, 0x4c, "RxUndersizePkts" },
  99         { 4, 0x50, "RxPausePkts" },
 100         { 4, 0x54, "Pkts64Octets" },
 101         { 4, 0x58, "Pkts65to127Octets" },
 102         { 4, 0x5c, "Pkts128to255Octets" },
 103         { 4, 0x60, "Pkts256to511Octets" },
 104         { 4, 0x64, "Pkts512to1023Octets" },
 105         { 4, 0x68, "Pkts1024to1522Octets" },
 106         { 4, 0x6c, "RxOversizePkts" },
 107         { 4, 0x70, "RxJabbers" },
 108         { 4, 0x74, "RxAlignmentErrors" },
 109         { 4, 0x78, "RxFCSErrors" },
 110         { 8, 0x7c, "RxGoodOctets" },
 111         { 4, 0x84, "RxDropPkts" },
 112         { 4, 0x88, "RxUnicastPkts" },
 113         { 4, 0x8c, "RxMulticastPkts" },
 114         { 4, 0x90, "RxBroadcastPkts" },
 115         { 4, 0x94, "RxSAChanges" },
 116         { 4, 0x98, "RxFragments" },
 117         { 4, 0xa0, "RxSymbolErrors" },
 118         { 4, 0xa4, "RxQoSPkts" },
 119         { 8, 0xa8, "RxQoSOctets" },
 120         { 4, 0xb0, "Pkts1523to2047Octets" },
 121         { 4, 0xb4, "Pkts2048to4095Octets" },
 122         { 4, 0xb8, "Pkts4096to8191Octets" },
 123         { 4, 0xbc, "Pkts8192to9728Octets" },
 124         { 4, 0xc0, "RxDiscarded" },
 125 };
 126
 127 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 128
 129 /* MIB counters */
 130 static const struct b53_mib_desc b53_mibs[] = {
 131         { 8, 0x00, "TxOctets" },
 132         { 4, 0x08, "TxDropPkts" },
 133         { 4, 0x10, "TxBroadcastPkts" },
 134         { 4, 0x14, "TxMulticastPkts" },
 135         { 4, 0x18, "TxUnicastPkts" },
 136         { 4, 0x1c, "TxCollisions" },
 137         { 4, 0x20, "TxSingleCollision" },
 138         { 4, 0x24, "TxMultipleCollision" },
 139         { 4, 0x28, "TxDeferredTransmit" },
 140         { 4, 0x2c, "TxLateCollision" },
 141         { 4, 0x30, "TxExcessiveCollision" },
 142         { 4, 0x38, "TxPausePkts" },
 143         { 8, 0x50, "RxOctets" },
 144         { 4, 0x58, "RxUndersizePkts" },
 145         { 4, 0x5c, "RxPausePkts" },
 146         { 4, 0x60, "Pkts64Octets" },
 147         { 4, 0x64, "Pkts65to127Octets" },
 148         { 4, 0x68, "Pkts128to255Octets" },
 149         { 4, 0x6c, "Pkts256to511Octets" },
 150         { 4, 0x70, "Pkts512to1023Octets" },
 151         { 4, 0x74, "Pkts1024to1522Octets" },
 152         { 4, 0x78, "RxOversizePkts" },
 153         { 4, 0x7c, "RxJabbers" },
 154         { 4, 0x80, "RxAlignmentErrors" },
 155         { 4, 0x84, "RxFCSErrors" },
 156         { 8, 0x88, "RxGoodOctets" },
 157         { 4, 0x90, "RxDropPkts" },
 158         { 4, 0x94, "RxUnicastPkts" },
 159         { 4, 0x98, "RxMulticastPkts" },
 160         { 4, 0x9c, "RxBroadcastPkts" },
 161         { 4, 0xa0, "RxSAChanges" },
 162         { 4, 0xa4, "RxFragments" },
 163         { 4, 0xa8, "RxJumboPkts" },
 164         { 4, 0xac, "RxSymbolErrors" },
 165         { 4, 0xc0, "RxDiscarded" },
 166 };
 167
 168 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 169
 170 static const struct b53_mib_desc b53_mibs_58xx[] = {
 171         { 8, 0x00, "TxOctets" },
 172         { 4, 0x08, "TxDropPkts" },
 173         { 4, 0x0c, "TxQPKTQ0" },
 174         { 4, 0x10, "TxBroadcastPkts" },
 175         { 4, 0x14, "TxMulticastPkts" },
 176         { 4, 0x18, "TxUnicastPKts" },
 177         { 4, 0x1c, "TxCollisions" },
 178         { 4, 0x20, "TxSingleCollision" },
 179         { 4, 0x24, "TxMultipleCollision" },
 180         { 4, 0x28, "TxDeferredCollision" },
 181         { 4, 0x2c, "TxLateCollision" },
 182         { 4, 0x30, "TxExcessiveCollision" },
 183         { 4, 0x34, "TxFrameInDisc" },
 184         { 4, 0x38, "TxPausePkts" },
 185         { 4, 0x3c, "TxQPKTQ1" },
 186         { 4, 0x40, "TxQPKTQ2" },
 187         { 4, 0x44, "TxQPKTQ3" },
 188         { 4, 0x48, "TxQPKTQ4" },
 189         { 4, 0x4c, "TxQPKTQ5" },
 190         { 8, 0x50, "RxOctets" },
 191         { 4, 0x58, "RxUndersizePkts" },
 192         { 4, 0x5c, "RxPausePkts" },
 193         { 4, 0x60, "RxPkts64Octets" },
 194         { 4, 0x64, "RxPkts65to127Octets" },
 195         { 4, 0x68, "RxPkts128to255Octets" },
 196         { 4, 0x6c, "RxPkts256to511Octets" },
 197         { 4, 0x70, "RxPkts512to1023Octets" },
 198         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 199         { 4, 0x78, "RxOversizePkts" },
 200         { 4, 0x7c, "RxJabbers" },
 201         { 4, 0x80, "RxAlignmentErrors" },
 202         { 4, 0x84, "RxFCSErrors" },
 203         { 8, 0x88, "RxGoodOctets" },
 204         { 4, 0x90, "RxDropPkts" },
 205         { 4, 0x94, "RxUnicastPkts" },
 206         { 4, 0x98, "RxMulticastPkts" },
 207         { 4, 0x9c, "RxBroadcastPkts" },
 208         { 4, 0xa0, "RxSAChanges" },
 209         { 4, 0xa4, "RxFragments" },
 210         { 4, 0xa8, "RxJumboPkt" },
 211         { 4, 0xac, "RxSymblErr" },
 212         { 4, 0xb0, "InRangeErrCount" },
 213         { 4, 0xb4, "OutRangeErrCount" },
 214         { 4, 0xb8, "EEELpiEvent" },
 215         { 4, 0xbc, "EEELpiDuration" },
 216         { 4, 0xc0, "RxDiscard" },
 217         { 4, 0xc8, "TxQPKTQ6" },
 218         { 4, 0xcc, "TxQPKTQ7" },
 219         { 4, 0xd0, "TxPkts64Octets" },
 220         { 4, 0xd4, "TxPkts65to127Octets" },
 221         { 4, 0xd8, "TxPkts128to255Octets" },
 222         { 4, 0xdc, "TxPkts256to511Ocets" },
 223         { 4, 0xe0, "TxPkts512to1023Ocets" },
 224         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 225 };
 226
 227 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 228
 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 230 {
 231         unsigned int i;
 232
 233         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 234
 235         for (i = 0; i < 10; i++) {
 236                 u8 vta;
 237
 238                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 239                 if (!(vta & VTA_START_CMD))
 240                         return 0;
 241
 242                 usleep_range(100, 200);
 243         }
 244
 245         return -EIO;
 246 }
 247
 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 249                                struct b53_vlan *vlan)
 250 {
 251         if (is5325(dev)) {
 252                 u32 entry = 0;
 253
 254                 if (vlan->members) {
 255                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 256                                  VA_UNTAG_S_25) | vlan->members;
 257                         if (dev->core_rev >= 3)
 258                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 259                         else
 260                                 entry |= VA_VALID_25;
 261                 }
 262
 263                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 264                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 265                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 266         } else if (is5365(dev)) {
 267                 u16 entry = 0;
 268
 269                 if (vlan->members)
 270                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 271                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 272
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 274                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 275                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 276         } else {
 277                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 278                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 279                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 280
 281                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 282         }
 283
 284         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 285                 vid, vlan->members, vlan->untag);
 286 }
 287
 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 289                                struct b53_vlan *vlan)
 290 {
 291         if (is5325(dev)) {
 292                 u32 entry = 0;
 293
 294                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 295                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 296                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 297
 298                 if (dev->core_rev >= 3)
 299                         vlan->valid = !!(entry & VA_VALID_25_R4);
 300                 else
 301                         vlan->valid = !!(entry & VA_VALID_25);
 302                 vlan->members = entry & VA_MEMBER_MASK;
 303                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 304
 305         } else if (is5365(dev)) {
 306                 u16 entry = 0;
 307
 308                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 309                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 311
 312                 vlan->valid = !!(entry & VA_VALID_65);
 313                 vlan->members = entry & VA_MEMBER_MASK;
 314                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 315         } else {
 316                 u32 entry = 0;
 317
 318                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 319                 b53_do_vlan_op(dev, VTA_CMD_READ);
 320                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 321                 vlan->members = entry & VTE_MEMBERS;
 322                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 323                 vlan->valid = true;
 324         }
 325 }
 326
 327 static void b53_set_forwarding(struct b53_device *dev, int enable)
 328 {
 329         struct dsa_switch *ds = dev->ds;
 330         u8 mgmt;
 331
 332         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 333
 334         if (enable)
 335                 mgmt |= SM_SW_FWD_EN;
 336         else
 337                 mgmt &= ~SM_SW_FWD_EN;
 338
 339         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 340
 341         /* Include IMP port in dumb forwarding mode when no tagging protocol is
 342          * set
 343          */
 344         if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
 345                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 346                 mgmt |= B53_MII_DUMB_FWDG_EN;
 347                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 348         }
 349 }
 350
 351 static void b53_enable_vlan(struct b53_device *dev, bool enable)
 352 {
 353         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 354
 355         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 356         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 357         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 358
 359         if (is5325(dev) || is5365(dev)) {
 360                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 361                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 362         } else if (is63xx(dev)) {
 363                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 364                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 365         } else {
 366                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 367                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 368         }
 369
 370         mgmt &= ~SM_SW_FWD_MODE;
 371
 372         if (enable) {
 373                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 374                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 375                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 376                 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 377                 vc5 |= VC5_DROP_VTABLE_MISS;
 378
 379                 if (is5325(dev))
 380                         vc0 &= ~VC0_RESERVED_1;
 381
 382                 if (is5325(dev) || is5365(dev))
 383                         vc1 |= VC1_RX_MCST_TAG_EN;
 384
 385         } else {
 386                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 387                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 388                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 389                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 390
 391                 if (is5325(dev) || is5365(dev))
 392                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 393                 else
 394                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 395
 396                 if (is5325(dev) || is5365(dev))
 397                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 398         }
 399
 400         if (!is5325(dev) && !is5365(dev))
 401                 vc5 &= ~VC5_VID_FFF_EN;
 402
 403         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 404         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 405
 406         if (is5325(dev) || is5365(dev)) {
 407                 /* enable the high 8 bit vid check on 5325 */
 408                 if (is5325(dev) && enable)
 409                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 410                                    VC3_HIGH_8BIT_EN);
 411                 else
 412                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 413
 414                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 415                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 416         } else if (is63xx(dev)) {
 417                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 418                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 419                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 420         } else {
 421                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 422                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 423                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 424         }
 425
 426         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 427 }
 428
 429 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 430 {
 431         u32 port_mask = 0;
 432         u16 max_size = JMS_MIN_SIZE;
 433
 434         if (is5325(dev) || is5365(dev))
 435                 return -EINVAL;
 436
 437         if (enable) {
 438                 port_mask = dev->enabled_ports;
 439                 max_size = JMS_MAX_SIZE;
 440                 if (allow_10_100)
 441                         port_mask |= JPM_10_100_JUMBO_EN;
 442         }
 443
 444         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 445         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 446 }
 447
 448 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 449 {
 450         unsigned int i;
 451
 452         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 453                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 454
 455         for (i = 0; i < 10; i++) {
 456                 u8 fast_age_ctrl;
 457
 458                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 459                           &fast_age_ctrl);
 460
 461                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 462                         goto out;
 463
 464                 msleep(1);
 465         }
 466
 467         return -ETIMEDOUT;
 468 out:
 469         /* Only age dynamic entries (default behavior) */
 470         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 471         return 0;
 472 }
 473
 474 static int b53_fast_age_port(struct b53_device *dev, int port)
 475 {
 476         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 477
 478         return b53_flush_arl(dev, FAST_AGE_PORT);
 479 }
 480
 481 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 482 {
 483         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 484
 485         return b53_flush_arl(dev, FAST_AGE_VLAN);
 486 }
 487
 488 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 489 {
 490         struct b53_device *dev = ds->priv;
 491         unsigned int i;
 492         u16 pvlan;
 493
 494         /* Enable the IMP port to be in the same VLAN as the other ports
 495          * on a per-port basis such that we only have Port i and IMP in
 496          * the same VLAN.
 497          */
 498         b53_for_each_port(dev, i) {
 499                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 500                 pvlan |= BIT(cpu_port);
 501                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 502         }
 503 }
 504
 505 static int b53_enable_port(struct dsa_switch *ds, int port,
 506                            struct phy_device *phy)
 507 {
 508         struct b53_device *dev = ds->priv;
 509         unsigned int cpu_port = dev->cpu_port;
 510         u16 pvlan;
 511
 512         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 513         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 514
 515         /* Set this port, and only this one to be in the default VLAN,
 516          * if member of a bridge, restore its membership prior to
 517          * bringing down this port.
 518          */
 519         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 520         pvlan &= ~0x1ff;
 521         pvlan |= BIT(port);
 522         pvlan |= dev->ports[port].vlan_ctl_mask;
 523         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 524
 525         b53_imp_vlan_setup(ds, cpu_port);
 526
 527         return 0;
 528 }
 529
 530 static void b53_disable_port(struct dsa_switch *ds, int port,
 531                              struct phy_device *phy)
 532 {
 533         struct b53_device *dev = ds->priv;
 534         u8 reg;
 535
 536         /* Disable Tx/Rx for the port */
 537         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 538         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 539         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 540 }
 541
 542 static void b53_enable_cpu_port(struct b53_device *dev)
 543 {
 544         unsigned int cpu_port = dev->cpu_port;
 545         u8 port_ctrl;
 546
 547         /* BCM5325 CPU port is at 8 */
 548         if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
 549                 cpu_port = B53_CPU_PORT;
 550
 551         port_ctrl = PORT_CTRL_RX_BCST_EN |
 552                     PORT_CTRL_RX_MCST_EN |
 553                     PORT_CTRL_RX_UCST_EN;
 554         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
 555 }
 556
 557 static void b53_enable_mib(struct b53_device *dev)
 558 {
 559         u8 gc;
 560
 561         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 562         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 563         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 564 }
 565
 566 static int b53_configure_vlan(struct b53_device *dev)
 567 {
 568         struct b53_vlan vl = { 0 };
 569         int i;
 570
 571         /* clear all vlan entries */
 572         if (is5325(dev) || is5365(dev)) {
 573                 for (i = 1; i < dev->num_vlans; i++)
 574                         b53_set_vlan_entry(dev, i, &vl);
 575         } else {
 576                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 577         }
 578
 579         b53_enable_vlan(dev, false);
 580
 581         b53_for_each_port(dev, i)
 582                 b53_write16(dev, B53_VLAN_PAGE,
 583                             B53_VLAN_PORT_DEF_TAG(i), 1);
 584
 585         if (!is5325(dev) && !is5365(dev))
 586                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 587
 588         return 0;
 589 }
 590
 591 static void b53_switch_reset_gpio(struct b53_device *dev)
 592 {
 593         int gpio = dev->reset_gpio;
 594
 595         if (gpio < 0)
 596                 return;
 597
 598         /* Reset sequence: RESET low(50ms)->high(20ms)
 599          */
 600         gpio_set_value(gpio, 0);
 601         mdelay(50);
 602
 603         gpio_set_value(gpio, 1);
 604         mdelay(20);
 605
 606         dev->current_page = 0xff;
 607 }
 608
 609 static int b53_switch_reset(struct b53_device *dev)
 610 {
 611         unsigned int timeout = 1000;
 612         u8 mgmt, reg;
 613
 614         b53_switch_reset_gpio(dev);
 615
 616         if (is539x(dev)) {
 617                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 618                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 619         }
 620
 621         /* This is specific to 58xx devices here, do not use is58xx() which
 622          * covers the larger Starfigther 2 family, including 7445/7278 which
 623          * still use this driver as a library and need to perform the reset
 624          * earlier.
 625          */
 626         if (dev->chip_id == BCM58XX_DEVICE_ID) {
 627                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 628                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 629                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 630
 631                 do {
 632                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 633                         if (!(reg & SW_RST))
 634                                 break;
 635
 636                         usleep_range(1000, 2000);
 637                 } while (timeout-- > 0);
 638
 639                 if (timeout == 0)
 640                         return -ETIMEDOUT;
 641         }
 642
 643         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 644
 645         if (!(mgmt & SM_SW_FWD_EN)) {
 646                 mgmt &= ~SM_SW_FWD_MODE;
 647                 mgmt |= SM_SW_FWD_EN;
 648
 649                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 650                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 651
 652                 if (!(mgmt & SM_SW_FWD_EN)) {
 653                         dev_err(dev->dev, "Failed to enable switch!\n");
 654                         return -EINVAL;
 655                 }
 656         }
 657
 658         b53_enable_mib(dev);
 659
 660         return b53_flush_arl(dev, FAST_AGE_STATIC);
 661 }
 662
 663 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 664 {
 665         struct b53_device *priv = ds->priv;
 666         u16 value = 0;
 667         int ret;
 668
 669         if (priv->ops->phy_read16)
 670                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 671         else
 672                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 673                                  reg * 2, &value);
 674
 675         return ret ? ret : value;
 676 }
 677
 678 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 679 {
 680         struct b53_device *priv = ds->priv;
 681
 682         if (priv->ops->phy_write16)
 683                 return priv->ops->phy_write16(priv, addr, reg, val);
 684
 685         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 686 }
 687
 688 static int b53_reset_switch(struct b53_device *priv)
 689 {
 690         /* reset vlans */
 691         priv->enable_jumbo = false;
 692
 693         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 694         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 695
 696         return b53_switch_reset(priv);
 697 }
 698
 699 static int b53_apply_config(struct b53_device *priv)
 700 {
 701         /* disable switching */
 702         b53_set_forwarding(priv, 0);
 703
 704         b53_configure_vlan(priv);
 705
 706         /* enable switching */
 707         b53_set_forwarding(priv, 1);
 708
 709         return 0;
 710 }
 711
 712 static void b53_reset_mib(struct b53_device *priv)
 713 {
 714         u8 gc;
 715
 716         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 717
 718         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 719         msleep(1);
 720         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 721         msleep(1);
 722 }
 723
 724 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 725 {
 726         if (is5365(dev))
 727                 return b53_mibs_65;
 728         else if (is63xx(dev))
 729                 return b53_mibs_63xx;
 730         else if (is58xx(dev))
 731                 return b53_mibs_58xx;
 732         else
 733                 return b53_mibs;
 734 }
 735
 736 static unsigned int b53_get_mib_size(struct b53_device *dev)
 737 {
 738         if (is5365(dev))
 739                 return B53_MIBS_65_SIZE;
 740         else if (is63xx(dev))
 741                 return B53_MIBS_63XX_SIZE;
 742         else if (is58xx(dev))
 743                 return B53_MIBS_58XX_SIZE;
 744         else
 745                 return B53_MIBS_SIZE;
 746 }
 747
 748 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 749 {
 750         struct b53_device *dev = ds->priv;
 751         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 752         unsigned int mib_size = b53_get_mib_size(dev);
 753         unsigned int i;
 754
 755         for (i = 0; i < mib_size; i++)
 756                 memcpy(data + i * ETH_GSTRING_LEN,
 757                        mibs[i].name, ETH_GSTRING_LEN);
 758 }
 759 EXPORT_SYMBOL(b53_get_strings);
 760
 761 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 762 {
 763         struct b53_device *dev = ds->priv;
 764         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 765         unsigned int mib_size = b53_get_mib_size(dev);
 766         const struct b53_mib_desc *s;
 767         unsigned int i;
 768         u64 val = 0;
 769
 770         if (is5365(dev) && port == 5)
 771                 port = 8;
 772
 773         mutex_lock(&dev->stats_mutex);
 774
 775         for (i = 0; i < mib_size; i++) {
 776                 s = &mibs[i];
 777
 778                 if (s->size == 8) {
 779                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 780                 } else {
 781                         u32 val32;
 782
 783                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 784                                    &val32);
 785                         val = val32;
 786                 }
 787                 data[i] = (u64)val;
 788         }
 789
 790         mutex_unlock(&dev->stats_mutex);
 791 }
 792 EXPORT_SYMBOL(b53_get_ethtool_stats);
 793
 794 int b53_get_sset_count(struct dsa_switch *ds)
 795 {
 796         struct b53_device *dev = ds->priv;
 797
 798         return b53_get_mib_size(dev);
 799 }
 800 EXPORT_SYMBOL(b53_get_sset_count);
 801
 802 static int b53_setup(struct dsa_switch *ds)
 803 {
 804         struct b53_device *dev = ds->priv;
 805         unsigned int port;
 806         int ret;
 807
 808         ret = b53_reset_switch(dev);
 809         if (ret) {
 810                 dev_err(ds->dev, "failed to reset switch\n");
 811                 return ret;
 812         }
 813
 814         b53_reset_mib(dev);
 815
 816         ret = b53_apply_config(dev);
 817         if (ret)
 818                 dev_err(ds->dev, "failed to apply configuration\n");
 819
 820         for (port = 0; port < dev->num_ports; port++) {
 821                 if (BIT(port) & ds->enabled_port_mask)
 822                         b53_enable_port(ds, port, NULL);
 823                 else if (dsa_is_cpu_port(ds, port))
 824                         b53_enable_cpu_port(dev);
 825                 else
 826                         b53_disable_port(ds, port, NULL);
 827         }
 828
 829         return ret;
 830 }
 831
 832 static void b53_adjust_link(struct dsa_switch *ds, int port,
 833                             struct phy_device *phydev)
 834 {
 835         struct b53_device *dev = ds->priv;
 836         u8 rgmii_ctrl = 0, reg = 0, off;
 837
 838         if (!phy_is_pseudo_fixed_link(phydev))
 839                 return;
 840
 841         /* Override the port settings */
 842         if (port == dev->cpu_port) {
 843                 off = B53_PORT_OVERRIDE_CTRL;
 844                 reg = PORT_OVERRIDE_EN;
 845         } else {
 846                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 847                 reg = GMII_PO_EN;
 848         }
 849
 850         /* Set the link UP */
 851         if (phydev->link)
 852                 reg |= PORT_OVERRIDE_LINK;
 853
 854         if (phydev->duplex == DUPLEX_FULL)
 855                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
 856
 857         switch (phydev->speed) {
 858         case 2000:
 859                 reg |= PORT_OVERRIDE_SPEED_2000M;
 860                 /* fallthrough */
 861         case SPEED_1000:
 862                 reg |= PORT_OVERRIDE_SPEED_1000M;
 863                 break;
 864         case SPEED_100:
 865                 reg |= PORT_OVERRIDE_SPEED_100M;
 866                 break;
 867         case SPEED_10:
 868                 reg |= PORT_OVERRIDE_SPEED_10M;
 869                 break;
 870         default:
 871                 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
 872                 return;
 873         }
 874
 875         /* Enable flow control on BCM5301x's CPU port */
 876         if (is5301x(dev) && port == dev->cpu_port)
 877                 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
 878
 879         if (phydev->pause) {
 880                 if (phydev->asym_pause)
 881                         reg |= PORT_OVERRIDE_TX_FLOW;
 882                 reg |= PORT_OVERRIDE_RX_FLOW;
 883         }
 884
 885         b53_write8(dev, B53_CTRL_PAGE, off, reg);
 886
 887         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
 888                 if (port == 8)
 889                         off = B53_RGMII_CTRL_IMP;
 890                 else
 891                         off = B53_RGMII_CTRL_P(port);
 892
 893                 /* Configure the port RGMII clock delay by DLL disabled and
 894                  * tx_clk aligned timing (restoring to reset defaults)
 895                  */
 896                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
 897                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
 898                                 RGMII_CTRL_TIMING_SEL);
 899
 900                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
 901                  * sure that we enable the port TX clock internal delay to
 902                  * account for this internal delay that is inserted, otherwise
 903                  * the switch won't be able to receive correctly.
 904                  *
 905                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
 906                  * any delay neither on transmission nor reception, so the
 907                  * BCM53125 must also be configured accordingly to account for
 908                  * the lack of delay and introduce
 909                  *
 910                  * The BCM53125 switch has its RX clock and TX clock control
 911                  * swapped, hence the reason why we modify the TX clock path in
 912                  * the "RGMII" case
 913                  */
 914                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 915                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
 916                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 917                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
 918                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
 919                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
 920
 921                 dev_info(ds->dev, "Configured port %d for %s\n", port,
 922                          phy_modes(phydev->interface));
 923         }
 924
 925         /* configure MII port if necessary */
 926         if (is5325(dev)) {
 927                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 928                           &reg);
 929
 930                 /* reverse mii needs to be enabled */
 931                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
 932                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 933                                    reg | PORT_OVERRIDE_RV_MII_25);
 934                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 935                                   &reg);
 936
 937                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
 938                                 dev_err(ds->dev,
 939                                         "Failed to enable reverse MII mode\n");
 940                                 return;
 941                         }
 942                 }
 943         } else if (is5301x(dev)) {
 944                 if (port != dev->cpu_port) {
 945                         u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
 946                         u8 gmii_po;
 947
 948                         b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
 949                         gmii_po |= GMII_PO_LINK |
 950                                    GMII_PO_RX_FLOW |
 951                                    GMII_PO_TX_FLOW |
 952                                    GMII_PO_EN |
 953                                    GMII_PO_SPEED_2000M;
 954                         b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
 955                 }
 956         }
 957 }
 958
 959 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
 960 {
 961         return 0;
 962 }
 963 EXPORT_SYMBOL(b53_vlan_filtering);
 964
 965 int b53_vlan_prepare(struct dsa_switch *ds, int port,
 966                      const struct switchdev_obj_port_vlan *vlan,
 967                      struct switchdev_trans *trans)
 968 {
 969         struct b53_device *dev = ds->priv;
 970
 971         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
 972                 return -EOPNOTSUPP;
 973
 974         if (vlan->vid_end > dev->num_vlans)
 975                 return -ERANGE;
 976
 977         b53_enable_vlan(dev, true);
 978
 979         return 0;
 980 }
 981 EXPORT_SYMBOL(b53_vlan_prepare);
 982
 983 void b53_vlan_add(struct dsa_switch *ds, int port,
 984                   const struct switchdev_obj_port_vlan *vlan,
 985                   struct switchdev_trans *trans)
 986 {
 987         struct b53_device *dev = ds->priv;
 988         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 989         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
 990         unsigned int cpu_port = dev->cpu_port;
 991         struct b53_vlan *vl;
 992         u16 vid;
 993
 994         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
 995                 vl = &dev->vlans[vid];
 996
 997                 b53_get_vlan_entry(dev, vid, vl);
 998
 999                 vl->members |= BIT(port) | BIT(cpu_port);
1000                 if (untagged)
1001                         vl->untag |= BIT(port);
1002                 else
1003                         vl->untag &= ~BIT(port);
1004                 vl->untag &= ~BIT(cpu_port);
1005
1006                 b53_set_vlan_entry(dev, vid, vl);
1007                 b53_fast_age_vlan(dev, vid);
1008         }
1009
1010         if (pvid) {
1011                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1012                             vlan->vid_end);
1013                 b53_fast_age_vlan(dev, vid);
1014         }
1015 }
1016 EXPORT_SYMBOL(b53_vlan_add);
1017
1018 int b53_vlan_del(struct dsa_switch *ds, int port,
1019                  const struct switchdev_obj_port_vlan *vlan)
1020 {
1021         struct b53_device *dev = ds->priv;
1022         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1023         struct b53_vlan *vl;
1024         u16 vid;
1025         u16 pvid;
1026
1027         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1028
1029         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1030                 vl = &dev->vlans[vid];
1031
1032                 b53_get_vlan_entry(dev, vid, vl);
1033
1034                 vl->members &= ~BIT(port);
1035
1036                 if (pvid == vid) {
1037                         if (is5325(dev) || is5365(dev))
1038                                 pvid = 1;
1039                         else
1040                                 pvid = 0;
1041                 }
1042
1043                 if (untagged)
1044                         vl->untag &= ~(BIT(port));
1045
1046                 b53_set_vlan_entry(dev, vid, vl);
1047                 b53_fast_age_vlan(dev, vid);
1048         }
1049
1050         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1051         b53_fast_age_vlan(dev, pvid);
1052
1053         return 0;
1054 }
1055 EXPORT_SYMBOL(b53_vlan_del);
1056
1057 int b53_vlan_dump(struct dsa_switch *ds, int port,
1058                   struct switchdev_obj_port_vlan *vlan,
1059                   int (*cb)(struct switchdev_obj *obj))
1060 {
1061         struct b53_device *dev = ds->priv;
1062         u16 vid, vid_start = 0, pvid;
1063         struct b53_vlan *vl;
1064         int err = 0;
1065
1066         if (is5325(dev) || is5365(dev))
1067                 vid_start = 1;
1068
1069         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1070
1071         /* Use our software cache for dumps, since we do not have any HW
1072          * operation returning only the used/valid VLANs
1073          */
1074         for (vid = vid_start; vid < dev->num_vlans; vid++) {
1075                 vl = &dev->vlans[vid];
1076
1077                 if (!vl->valid)
1078                         continue;
1079
1080                 if (!(vl->members & BIT(port)))
1081                         continue;
1082
1083                 vlan->vid_begin = vlan->vid_end = vid;
1084                 vlan->flags = 0;
1085
1086                 if (vl->untag & BIT(port))
1087                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1088                 if (pvid == vid)
1089                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1090
1091                 err = cb(&vlan->obj);
1092                 if (err)
1093                         break;
1094         }
1095
1096         return err;
1097 }
1098 EXPORT_SYMBOL(b53_vlan_dump);
1099
1100 /* Address Resolution Logic routines */
1101 static int b53_arl_op_wait(struct b53_device *dev)
1102 {
1103         unsigned int timeout = 10;
1104         u8 reg;
1105
1106         do {
1107                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1108                 if (!(reg & ARLTBL_START_DONE))
1109                         return 0;
1110
1111                 usleep_range(1000, 2000);
1112         } while (timeout--);
1113
1114         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1115
1116         return -ETIMEDOUT;
1117 }
1118
1119 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1120 {
1121         u8 reg;
1122
1123         if (op > ARLTBL_RW)
1124                 return -EINVAL;
1125
1126         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1127         reg |= ARLTBL_START_DONE;
1128         if (op)
1129                 reg |= ARLTBL_RW;
1130         else
1131                 reg &= ~ARLTBL_RW;
1132         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1133
1134         return b53_arl_op_wait(dev);
1135 }
1136
1137 static int b53_arl_read(struct b53_device *dev, u64 mac,
1138                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1139                         bool is_valid)
1140 {
1141         unsigned int i;
1142         int ret;
1143
1144         ret = b53_arl_op_wait(dev);
1145         if (ret)
1146                 return ret;
1147
1148         /* Read the bins */
1149         for (i = 0; i < dev->num_arl_entries; i++) {
1150                 u64 mac_vid;
1151                 u32 fwd_entry;
1152
1153                 b53_read64(dev, B53_ARLIO_PAGE,
1154                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1155                 b53_read32(dev, B53_ARLIO_PAGE,
1156                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1157                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1158
1159                 if (!(fwd_entry & ARLTBL_VALID))
1160                         continue;
1161                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1162                         continue;
1163                 *idx = i;
1164         }
1165
1166         return -ENOENT;
1167 }
1168
1169 static int b53_arl_op(struct b53_device *dev, int op, int port,
1170                       const unsigned char *addr, u16 vid, bool is_valid)
1171 {
1172         struct b53_arl_entry ent;
1173         u32 fwd_entry;
1174         u64 mac, mac_vid = 0;
1175         u8 idx = 0;
1176         int ret;
1177
1178         /* Convert the array into a 64-bit MAC */
1179         mac = ether_addr_to_u64(addr);
1180
1181         /* Perform a read for the given MAC and VID */
1182         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1183         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1184
1185         /* Issue a read operation for this MAC */
1186         ret = b53_arl_rw_op(dev, 1);
1187         if (ret)
1188                 return ret;
1189
1190         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1191         /* If this is a read, just finish now */
1192         if (op)
1193                 return ret;
1194
1195         /* We could not find a matching MAC, so reset to a new entry */
1196         if (ret) {
1197                 fwd_entry = 0;
1198                 idx = 1;
1199         }
1200
1201         memset(&ent, 0, sizeof(ent));
1202         ent.port = port;
1203         ent.is_valid = is_valid;
1204         ent.vid = vid;
1205         ent.is_static = true;
1206         memcpy(ent.mac, addr, ETH_ALEN);
1207         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1208
1209         b53_write64(dev, B53_ARLIO_PAGE,
1210                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1211         b53_write32(dev, B53_ARLIO_PAGE,
1212                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1213
1214         return b53_arl_rw_op(dev, 0);
1215 }
1216
1217 int b53_fdb_prepare(struct dsa_switch *ds, int port,
1218                     const struct switchdev_obj_port_fdb *fdb,
1219                     struct switchdev_trans *trans)
1220 {
1221         struct b53_device *priv = ds->priv;
1222
1223         /* 5325 and 5365 require some more massaging, but could
1224          * be supported eventually
1225          */
1226         if (is5325(priv) || is5365(priv))
1227                 return -EOPNOTSUPP;
1228
1229         return 0;
1230 }
1231 EXPORT_SYMBOL(b53_fdb_prepare);
1232
1233 void b53_fdb_add(struct dsa_switch *ds, int port,
1234                  const struct switchdev_obj_port_fdb *fdb,
1235                  struct switchdev_trans *trans)
1236 {
1237         struct b53_device *priv = ds->priv;
1238
1239         if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1240                 pr_err("%s: failed to add MAC address\n", __func__);
1241 }
1242 EXPORT_SYMBOL(b53_fdb_add);
1243
1244 int b53_fdb_del(struct dsa_switch *ds, int port,
1245                 const struct switchdev_obj_port_fdb *fdb)
1246 {
1247         struct b53_device *priv = ds->priv;
1248
1249         return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1250 }
1251 EXPORT_SYMBOL(b53_fdb_del);
1252
1253 static int b53_arl_search_wait(struct b53_device *dev)
1254 {
1255         unsigned int timeout = 1000;
1256         u8 reg;
1257
1258         do {
1259                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1260                 if (!(reg & ARL_SRCH_STDN))
1261                         return 0;
1262
1263                 if (reg & ARL_SRCH_VLID)
1264                         return 0;
1265
1266                 usleep_range(1000, 2000);
1267         } while (timeout--);
1268
1269         return -ETIMEDOUT;
1270 }
1271
1272 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1273                               struct b53_arl_entry *ent)
1274 {
1275         u64 mac_vid;
1276         u32 fwd_entry;
1277
1278         b53_read64(dev, B53_ARLIO_PAGE,
1279                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1280         b53_read32(dev, B53_ARLIO_PAGE,
1281                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1282         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1283 }
1284
1285 static int b53_fdb_copy(struct net_device *dev, int port,
1286                         const struct b53_arl_entry *ent,
1287                         struct switchdev_obj_port_fdb *fdb,
1288                         int (*cb)(struct switchdev_obj *obj))
1289 {
1290         if (!ent->is_valid)
1291                 return 0;
1292
1293         if (port != ent->port)
1294                 return 0;
1295
1296         ether_addr_copy(fdb->addr, ent->mac);
1297         fdb->vid = ent->vid;
1298         fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1299
1300         return cb(&fdb->obj);
1301 }
1302
1303 int b53_fdb_dump(struct dsa_switch *ds, int port,
1304                  struct switchdev_obj_port_fdb *fdb,
1305                  int (*cb)(struct switchdev_obj *obj))
1306 {
1307         struct b53_device *priv = ds->priv;
1308         struct net_device *dev = ds->ports[port].netdev;
1309         struct b53_arl_entry results[2];
1310         unsigned int count = 0;
1311         int ret;
1312         u8 reg;
1313
1314         /* Start search operation */
1315         reg = ARL_SRCH_STDN;
1316         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1317
1318         do {
1319                 ret = b53_arl_search_wait(priv);
1320                 if (ret)
1321                         return ret;
1322
1323                 b53_arl_search_rd(priv, 0, &results[0]);
1324                 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1325                 if (ret)
1326                         return ret;
1327
1328                 if (priv->num_arl_entries > 2) {
1329                         b53_arl_search_rd(priv, 1, &results[1]);
1330                         ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1331                         if (ret)
1332                                 return ret;
1333
1334                         if (!results[0].is_valid && !results[1].is_valid)
1335                                 break;
1336                 }
1337
1338         } while (count++ < 1024);
1339
1340         return 0;
1341 }
1342 EXPORT_SYMBOL(b53_fdb_dump);
1343
1344 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1345 {
1346         struct b53_device *dev = ds->priv;
1347         s8 cpu_port = ds->dst->cpu_port;
1348         u16 pvlan, reg;
1349         unsigned int i;
1350
1351         /* Make this port leave the all VLANs join since we will have proper
1352          * VLAN entries from now on
1353          */
1354         if (is58xx(dev)) {
1355                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1356                 reg &= ~BIT(port);
1357                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1358                         reg &= ~BIT(cpu_port);
1359                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1360         }
1361
1362         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1363
1364         b53_for_each_port(dev, i) {
1365                 if (ds->ports[i].bridge_dev != br)
1366                         continue;
1367
1368                 /* Add this local port to the remote port VLAN control
1369                  * membership and update the remote port bitmask
1370                  */
1371                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1372                 reg |= BIT(port);
1373                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1374                 dev->ports[i].vlan_ctl_mask = reg;
1375
1376                 pvlan |= BIT(i);
1377         }
1378
1379         /* Configure the local port VLAN control membership to include
1380          * remote ports and update the local port bitmask
1381          */
1382         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1383         dev->ports[port].vlan_ctl_mask = pvlan;
1384
1385         return 0;
1386 }
1387 EXPORT_SYMBOL(b53_br_join);
1388
1389 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1390 {
1391         struct b53_device *dev = ds->priv;
1392         struct b53_vlan *vl = &dev->vlans[0];
1393         s8 cpu_port = ds->dst->cpu_port;
1394         unsigned int i;
1395         u16 pvlan, reg, pvid;
1396
1397         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1398
1399         b53_for_each_port(dev, i) {
1400                 /* Don't touch the remaining ports */
1401                 if (ds->ports[i].bridge_dev != br)
1402                         continue;
1403
1404                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1405                 reg &= ~BIT(port);
1406                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1407                 dev->ports[port].vlan_ctl_mask = reg;
1408
1409                 /* Prevent self removal to preserve isolation */
1410                 if (port != i)
1411                         pvlan &= ~BIT(i);
1412         }
1413
1414         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1415         dev->ports[port].vlan_ctl_mask = pvlan;
1416
1417         if (is5325(dev) || is5365(dev))
1418                 pvid = 1;
1419         else
1420                 pvid = 0;
1421
1422         /* Make this port join all VLANs without VLAN entries */
1423         if (is58xx(dev)) {
1424                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1425                 reg |= BIT(port);
1426                 if (!(reg & BIT(cpu_port)))
1427                         reg |= BIT(cpu_port);
1428                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1429         } else {
1430                 b53_get_vlan_entry(dev, pvid, vl);
1431                 vl->members |= BIT(port) | BIT(dev->cpu_port);
1432                 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1433                 b53_set_vlan_entry(dev, pvid, vl);
1434         }
1435 }
1436 EXPORT_SYMBOL(b53_br_leave);
1437
1438 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1439 {
1440         struct b53_device *dev = ds->priv;
1441         u8 hw_state;
1442         u8 reg;
1443
1444         switch (state) {
1445         case BR_STATE_DISABLED:
1446                 hw_state = PORT_CTRL_DIS_STATE;
1447                 break;
1448         case BR_STATE_LISTENING:
1449                 hw_state = PORT_CTRL_LISTEN_STATE;
1450                 break;
1451         case BR_STATE_LEARNING:
1452                 hw_state = PORT_CTRL_LEARN_STATE;
1453                 break;
1454         case BR_STATE_FORWARDING:
1455                 hw_state = PORT_CTRL_FWD_STATE;
1456                 break;
1457         case BR_STATE_BLOCKING:
1458                 hw_state = PORT_CTRL_BLOCK_STATE;
1459                 break;
1460         default:
1461                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1462                 return;
1463         }
1464
1465         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1466         reg &= ~PORT_CTRL_STP_STATE_MASK;
1467         reg |= hw_state;
1468         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1469 }
1470 EXPORT_SYMBOL(b53_br_set_stp_state);
1471
1472 void b53_br_fast_age(struct dsa_switch *ds, int port)
1473 {
1474         struct b53_device *dev = ds->priv;
1475
1476         if (b53_fast_age_port(dev, port))
1477                 dev_err(ds->dev, "fast ageing failed\n");
1478 }
1479 EXPORT_SYMBOL(b53_br_fast_age);
1480
1481 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1482 {
1483         return DSA_TAG_PROTO_NONE;
1484 }
1485
1486 int b53_mirror_add(struct dsa_switch *ds, int port,
1487                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1488 {
1489         struct b53_device *dev = ds->priv;
1490         u16 reg, loc;
1491
1492         if (ingress)
1493                 loc = B53_IG_MIR_CTL;
1494         else
1495                 loc = B53_EG_MIR_CTL;
1496
1497         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1498         reg &= ~MIRROR_MASK;
1499         reg |= BIT(port);
1500         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1501
1502         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1503         reg &= ~CAP_PORT_MASK;
1504         reg |= mirror->to_local_port;
1505         reg |= MIRROR_EN;
1506         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1507
1508         return 0;
1509 }
1510 EXPORT_SYMBOL(b53_mirror_add);
1511
1512 void b53_mirror_del(struct dsa_switch *ds, int port,
1513                     struct dsa_mall_mirror_tc_entry *mirror)
1514 {
1515         struct b53_device *dev = ds->priv;
1516         bool loc_disable = false, other_loc_disable = false;
1517         u16 reg, loc;
1518
1519         if (mirror->ingress)
1520                 loc = B53_IG_MIR_CTL;
1521         else
1522                 loc = B53_EG_MIR_CTL;
1523
1524         /* Update the desired ingress/egress register */
1525         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1526         reg &= ~BIT(port);
1527         if (!(reg & MIRROR_MASK))
1528                 loc_disable = true;
1529         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1530
1531         /* Now look at the other one to know if we can disable mirroring
1532          * entirely
1533          */
1534         if (mirror->ingress)
1535                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1536         else
1537                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1538         if (!(reg & MIRROR_MASK))
1539                 other_loc_disable = true;
1540
1541         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1542         /* Both no longer have ports, let's disable mirroring */
1543         if (loc_disable && other_loc_disable) {
1544                 reg &= ~MIRROR_EN;
1545                 reg &= ~mirror->to_local_port;
1546         }
1547         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1548 }
1549 EXPORT_SYMBOL(b53_mirror_del);
1550
1551 static const struct dsa_switch_ops b53_switch_ops = {
1552         .get_tag_protocol       = b53_get_tag_protocol,
1553         .setup                  = b53_setup,
1554         .get_strings            = b53_get_strings,
1555         .get_ethtool_stats      = b53_get_ethtool_stats,
1556         .get_sset_count         = b53_get_sset_count,
1557         .phy_read               = b53_phy_read16,
1558         .phy_write              = b53_phy_write16,
1559         .adjust_link            = b53_adjust_link,
1560         .port_enable            = b53_enable_port,
1561         .port_disable           = b53_disable_port,
1562         .port_bridge_join       = b53_br_join,
1563         .port_bridge_leave      = b53_br_leave,
1564         .port_stp_state_set     = b53_br_set_stp_state,
1565         .port_fast_age          = b53_br_fast_age,
1566         .port_vlan_filtering    = b53_vlan_filtering,
1567         .port_vlan_prepare      = b53_vlan_prepare,
1568         .port_vlan_add          = b53_vlan_add,
1569         .port_vlan_del          = b53_vlan_del,
1570         .port_vlan_dump         = b53_vlan_dump,
1571         .port_fdb_prepare       = b53_fdb_prepare,
1572         .port_fdb_dump          = b53_fdb_dump,
1573         .port_fdb_add           = b53_fdb_add,
1574         .port_fdb_del           = b53_fdb_del,
1575         .port_mirror_add        = b53_mirror_add,
1576         .port_mirror_del        = b53_mirror_del,
1577 };
1578
1579 struct b53_chip_data {
1580         u32 chip_id;
1581         const char *dev_name;
1582         u16 vlans;
1583         u16 enabled_ports;
1584         u8 cpu_port;
1585         u8 vta_regs[3];
1586         u8 arl_entries;
1587         u8 duplex_reg;
1588         u8 jumbo_pm_reg;
1589         u8 jumbo_size_reg;
1590 };
1591
1592 #define B53_VTA_REGS    \
1593         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1594 #define B53_VTA_REGS_9798 \
1595         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1596 #define B53_VTA_REGS_63XX \
1597         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1598
1599 static const struct b53_chip_data b53_switch_chips[] = {
1600         {
1601                 .chip_id = BCM5325_DEVICE_ID,
1602                 .dev_name = "BCM5325",
1603                 .vlans = 16,
1604                 .enabled_ports = 0x1f,
1605                 .arl_entries = 2,
1606                 .cpu_port = B53_CPU_PORT_25,
1607                 .duplex_reg = B53_DUPLEX_STAT_FE,
1608         },
1609         {
1610                 .chip_id = BCM5365_DEVICE_ID,
1611                 .dev_name = "BCM5365",
1612                 .vlans = 256,
1613                 .enabled_ports = 0x1f,
1614                 .arl_entries = 2,
1615                 .cpu_port = B53_CPU_PORT_25,
1616                 .duplex_reg = B53_DUPLEX_STAT_FE,
1617         },
1618         {
1619                 .chip_id = BCM5395_DEVICE_ID,
1620                 .dev_name = "BCM5395",
1621                 .vlans = 4096,
1622                 .enabled_ports = 0x1f,
1623                 .arl_entries = 4,
1624                 .cpu_port = B53_CPU_PORT,
1625                 .vta_regs = B53_VTA_REGS,
1626                 .duplex_reg = B53_DUPLEX_STAT_GE,
1627                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1628                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1629         },
1630         {
1631                 .chip_id = BCM5397_DEVICE_ID,
1632                 .dev_name = "BCM5397",
1633                 .vlans = 4096,
1634                 .enabled_ports = 0x1f,
1635                 .arl_entries = 4,
1636                 .cpu_port = B53_CPU_PORT,
1637                 .vta_regs = B53_VTA_REGS_9798,
1638                 .duplex_reg = B53_DUPLEX_STAT_GE,
1639                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1640                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1641         },
1642         {
1643                 .chip_id = BCM5398_DEVICE_ID,
1644                 .dev_name = "BCM5398",
1645                 .vlans = 4096,
1646                 .enabled_ports = 0x7f,
1647                 .arl_entries = 4,
1648                 .cpu_port = B53_CPU_PORT,
1649                 .vta_regs = B53_VTA_REGS_9798,
1650                 .duplex_reg = B53_DUPLEX_STAT_GE,
1651                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1652                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1653         },
1654         {
1655                 .chip_id = BCM53115_DEVICE_ID,
1656                 .dev_name = "BCM53115",
1657                 .vlans = 4096,
1658                 .enabled_ports = 0x1f,
1659                 .arl_entries = 4,
1660                 .vta_regs = B53_VTA_REGS,
1661                 .cpu_port = B53_CPU_PORT,
1662                 .duplex_reg = B53_DUPLEX_STAT_GE,
1663                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1664                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1665         },
1666         {
1667                 .chip_id = BCM53125_DEVICE_ID,
1668                 .dev_name = "BCM53125",
1669                 .vlans = 4096,
1670                 .enabled_ports = 0xff,
1671                 .cpu_port = B53_CPU_PORT,
1672                 .vta_regs = B53_VTA_REGS,
1673                 .duplex_reg = B53_DUPLEX_STAT_GE,
1674                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1675                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1676         },
1677         {
1678                 .chip_id = BCM53128_DEVICE_ID,
1679                 .dev_name = "BCM53128",
1680                 .vlans = 4096,
1681                 .enabled_ports = 0x1ff,
1682                 .arl_entries = 4,
1683                 .cpu_port = B53_CPU_PORT,
1684                 .vta_regs = B53_VTA_REGS,
1685                 .duplex_reg = B53_DUPLEX_STAT_GE,
1686                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1687                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1688         },
1689         {
1690                 .chip_id = BCM63XX_DEVICE_ID,
1691                 .dev_name = "BCM63xx",
1692                 .vlans = 4096,
1693                 .enabled_ports = 0, /* pdata must provide them */
1694                 .arl_entries = 4,
1695                 .cpu_port = B53_CPU_PORT,
1696                 .vta_regs = B53_VTA_REGS_63XX,
1697                 .duplex_reg = B53_DUPLEX_STAT_63XX,
1698                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1699                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1700         },
1701         {
1702                 .chip_id = BCM53010_DEVICE_ID,
1703                 .dev_name = "BCM53010",
1704                 .vlans = 4096,
1705                 .enabled_ports = 0x1f,
1706                 .arl_entries = 4,
1707                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1708                 .vta_regs = B53_VTA_REGS,
1709                 .duplex_reg = B53_DUPLEX_STAT_GE,
1710                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1711                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1712         },
1713         {
1714                 .chip_id = BCM53011_DEVICE_ID,
1715                 .dev_name = "BCM53011",
1716                 .vlans = 4096,
1717                 .enabled_ports = 0x1bf,
1718                 .arl_entries = 4,
1719                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1720                 .vta_regs = B53_VTA_REGS,
1721                 .duplex_reg = B53_DUPLEX_STAT_GE,
1722                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1723                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1724         },
1725         {
1726                 .chip_id = BCM53012_DEVICE_ID,
1727                 .dev_name = "BCM53012",
1728                 .vlans = 4096,
1729                 .enabled_ports = 0x1bf,
1730                 .arl_entries = 4,
1731                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1732                 .vta_regs = B53_VTA_REGS,
1733                 .duplex_reg = B53_DUPLEX_STAT_GE,
1734                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1735                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1736         },
1737         {
1738                 .chip_id = BCM53018_DEVICE_ID,
1739                 .dev_name = "BCM53018",
1740                 .vlans = 4096,
1741                 .enabled_ports = 0x1f,
1742                 .arl_entries = 4,
1743                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1744                 .vta_regs = B53_VTA_REGS,
1745                 .duplex_reg = B53_DUPLEX_STAT_GE,
1746                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1747                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1748         },
1749         {
1750                 .chip_id = BCM53019_DEVICE_ID,
1751                 .dev_name = "BCM53019",
1752                 .vlans = 4096,
1753                 .enabled_ports = 0x1f,
1754                 .arl_entries = 4,
1755                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1756                 .vta_regs = B53_VTA_REGS,
1757                 .duplex_reg = B53_DUPLEX_STAT_GE,
1758                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1759                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1760         },
1761         {
1762                 .chip_id = BCM58XX_DEVICE_ID,
1763                 .dev_name = "BCM585xx/586xx/88312",
1764                 .vlans  = 4096,
1765                 .enabled_ports = 0x1ff,
1766                 .arl_entries = 4,
1767                 .cpu_port = B53_CPU_PORT,
1768                 .vta_regs = B53_VTA_REGS,
1769                 .duplex_reg = B53_DUPLEX_STAT_GE,
1770                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1771                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1772         },
1773         {
1774                 .chip_id = BCM7445_DEVICE_ID,
1775                 .dev_name = "BCM7445",
1776                 .vlans  = 4096,
1777                 .enabled_ports = 0x1ff,
1778                 .arl_entries = 4,
1779                 .cpu_port = B53_CPU_PORT,
1780                 .vta_regs = B53_VTA_REGS,
1781                 .duplex_reg = B53_DUPLEX_STAT_GE,
1782                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1783                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1784         },
1785         {
1786                 .chip_id = BCM7278_DEVICE_ID,
1787                 .dev_name = "BCM7278",
1788                 .vlans = 4096,
1789                 .enabled_ports = 0x1ff,
1790                 .arl_entries= 4,
1791                 .cpu_port = B53_CPU_PORT,
1792                 .vta_regs = B53_VTA_REGS,
1793                 .duplex_reg = B53_DUPLEX_STAT_GE,
1794                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1795                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1796         },
1797 };
1798
1799 static int b53_switch_init(struct b53_device *dev)
1800 {
1801         unsigned int i;
1802         int ret;
1803
1804         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1805                 const struct b53_chip_data *chip = &b53_switch_chips[i];
1806
1807                 if (chip->chip_id == dev->chip_id) {
1808                         if (!dev->enabled_ports)
1809                                 dev->enabled_ports = chip->enabled_ports;
1810                         dev->name = chip->dev_name;
1811                         dev->duplex_reg = chip->duplex_reg;
1812                         dev->vta_regs[0] = chip->vta_regs[0];
1813                         dev->vta_regs[1] = chip->vta_regs[1];
1814                         dev->vta_regs[2] = chip->vta_regs[2];
1815                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1816                         dev->cpu_port = chip->cpu_port;
1817                         dev->num_vlans = chip->vlans;
1818                         dev->num_arl_entries = chip->arl_entries;
1819                         break;
1820                 }
1821         }
1822
1823         /* check which BCM5325x version we have */
1824         if (is5325(dev)) {
1825                 u8 vc4;
1826
1827                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1828
1829                 /* check reserved bits */
1830                 switch (vc4 & 3) {
1831                 case 1:
1832                         /* BCM5325E */
1833                         break;
1834                 case 3:
1835                         /* BCM5325F - do not use port 4 */
1836                         dev->enabled_ports &= ~BIT(4);
1837                         break;
1838                 default:
1839 /* On the BCM47XX SoCs this is the supported internal switch.*/
1840 #ifndef CONFIG_BCM47XX
1841                         /* BCM5325M */
1842                         return -EINVAL;
1843 #else
1844                         break;
1845 #endif
1846                 }
1847         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1848                 u64 strap_value;
1849
1850                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1851                 /* use second IMP port if GMII is enabled */
1852                 if (strap_value & SV_GMII_CTRL_115)
1853                         dev->cpu_port = 5;
1854         }
1855
1856         /* cpu port is always last */
1857         dev->num_ports = dev->cpu_port + 1;
1858         dev->enabled_ports |= BIT(dev->cpu_port);
1859
1860         dev->ports = devm_kzalloc(dev->dev,
1861                                   sizeof(struct b53_port) * dev->num_ports,
1862                                   GFP_KERNEL);
1863         if (!dev->ports)
1864                 return -ENOMEM;
1865
1866         dev->vlans = devm_kzalloc(dev->dev,
1867                                   sizeof(struct b53_vlan) * dev->num_vlans,
1868                                   GFP_KERNEL);
1869         if (!dev->vlans)
1870                 return -ENOMEM;
1871
1872         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1873         if (dev->reset_gpio >= 0) {
1874                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1875                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
1876                 if (ret)
1877                         return ret;
1878         }
1879
1880         return 0;
1881 }
1882
1883 struct b53_device *b53_switch_alloc(struct device *base,
1884                                     const struct b53_io_ops *ops,
1885                                     void *priv)
1886 {
1887         struct dsa_switch *ds;
1888         struct b53_device *dev;
1889
1890         ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
1891         if (!ds)
1892                 return NULL;
1893
1894         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1895         if (!dev)
1896                 return NULL;
1897
1898         ds->priv = dev;
1899         dev->dev = base;
1900
1901         dev->ds = ds;
1902         dev->priv = priv;
1903         dev->ops = ops;
1904         ds->ops = &b53_switch_ops;
1905         mutex_init(&dev->reg_mutex);
1906         mutex_init(&dev->stats_mutex);
1907
1908         return dev;
1909 }
1910 EXPORT_SYMBOL(b53_switch_alloc);
1911
1912 int b53_switch_detect(struct b53_device *dev)
1913 {
1914         u32 id32;
1915         u16 tmp;
1916         u8 id8;
1917         int ret;
1918
1919         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1920         if (ret)
1921                 return ret;
1922
1923         switch (id8) {
1924         case 0:
1925                 /* BCM5325 and BCM5365 do not have this register so reads
1926                  * return 0. But the read operation did succeed, so assume this
1927                  * is one of them.
1928                  *
1929                  * Next check if we can write to the 5325's VTA register; for
1930                  * 5365 it is read only.
1931                  */
1932                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1933                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1934
1935                 if (tmp == 0xf)
1936                         dev->chip_id = BCM5325_DEVICE_ID;
1937                 else
1938                         dev->chip_id = BCM5365_DEVICE_ID;
1939                 break;
1940         case BCM5395_DEVICE_ID:
1941         case BCM5397_DEVICE_ID:
1942         case BCM5398_DEVICE_ID:
1943                 dev->chip_id = id8;
1944                 break;
1945         default:
1946                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1947                 if (ret)
1948                         return ret;
1949
1950                 switch (id32) {
1951                 case BCM53115_DEVICE_ID:
1952                 case BCM53125_DEVICE_ID:
1953                 case BCM53128_DEVICE_ID:
1954                 case BCM53010_DEVICE_ID:
1955                 case BCM53011_DEVICE_ID:
1956                 case BCM53012_DEVICE_ID:
1957                 case BCM53018_DEVICE_ID:
1958                 case BCM53019_DEVICE_ID:
1959                         dev->chip_id = id32;
1960                         break;
1961                 default:
1962                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1963                                id8, id32);
1964                         return -ENODEV;
1965                 }
1966         }
1967
1968         if (dev->chip_id == BCM5325_DEVICE_ID)
1969                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1970                                  &dev->core_rev);
1971         else
1972                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1973                                  &dev->core_rev);
1974 }
1975 EXPORT_SYMBOL(b53_switch_detect);
1976
1977 int b53_switch_register(struct b53_device *dev)
1978 {
1979         int ret;
1980
1981         if (dev->pdata) {
1982                 dev->chip_id = dev->pdata->chip_id;
1983                 dev->enabled_ports = dev->pdata->enabled_ports;
1984         }
1985
1986         if (!dev->chip_id && b53_switch_detect(dev))
1987                 return -EINVAL;
1988
1989         ret = b53_switch_init(dev);
1990         if (ret)
1991                 return ret;
1992
1993         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1994
1995         return dsa_register_switch(dev->ds, dev->ds->dev);
1996 }
1997 EXPORT_SYMBOL(b53_switch_register);
1998
1999 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2000 MODULE_DESCRIPTION("B53 switch library");
2001 MODULE_LICENSE("Dual BSD/GPL");