2 * B53 register definitions
4 * Copyright (C) 2004 Broadcom Corporation
5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /* Management Port (SMP) Page offsets */
24 #define B53_CTRL_PAGE 0x00 /* Control */
25 #define B53_STAT_PAGE 0x01 /* Status */
26 #define B53_MGMT_PAGE 0x02 /* Management Mode */
27 #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */
28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
29 #define B53_ARLIO_PAGE 0x05 /* ARL Access */
30 #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */
31 #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */
34 #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */
35 #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
36 #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */
39 #define B53_MIB_PAGE(i) (0x20 + (i))
41 /* Quality of Service (QoS) Registers */
42 #define B53_QOS_PAGE 0x30
45 #define B53_PVLAN_PAGE 0x31
48 #define B53_VLAN_PAGE 0x34
50 /* Jumbo Frame Registers */
51 #define B53_JUMBO_PAGE 0x40
53 /* CFP Configuration Registers Page */
54 #define B53_CFP_PAGE 0xa1
56 /*************************************************************************
57 * Control Page registers
58 *************************************************************************/
60 /* Port Control Register (8 bit) */
61 #define B53_PORT_CTRL(i) (0x00 + (i))
62 #define PORT_CTRL_RX_DISABLE BIT(0)
63 #define PORT_CTRL_TX_DISABLE BIT(1)
64 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
65 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
66 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
67 #define PORT_CTRL_STP_STATE_S 5
68 #define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S)
69 #define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S)
70 #define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S)
71 #define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S)
72 #define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S)
73 #define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S)
74 #define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S)
76 /* SMP Control Register (8 bit) */
77 #define B53_SMP_CTRL 0x0a
79 /* Switch Mode Control Register (8 bit) */
80 #define B53_SWITCH_MODE 0x0b
81 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
82 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
84 /* IMP Port state override register (8 bit) */
85 #define B53_PORT_OVERRIDE_CTRL 0x0e
86 #define PORT_OVERRIDE_LINK BIT(0)
87 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
88 #define PORT_OVERRIDE_SPEED_S 2
89 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
90 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
91 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
92 #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */
93 #define PORT_OVERRIDE_RX_FLOW BIT(4)
94 #define PORT_OVERRIDE_TX_FLOW BIT(5)
95 #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */
96 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
98 /* Power-down mode control */
99 #define B53_PD_MODE_CTRL_25 0x0f
101 /* IP Multicast control (8 bit) */
102 #define B53_IP_MULTICAST_CTRL 0x21
103 #define B53_IPMC_FWD_EN BIT(1)
104 #define B53_UC_FWD_EN BIT(6)
105 #define B53_MC_FWD_EN BIT(7)
107 /* Switch control (8 bit) */
108 #define B53_SWITCH_CTRL 0x22
109 #define B53_MII_DUMB_FWDG_EN BIT(6)
112 #define B53_UC_FLOOD_MASK 0x32
113 #define B53_MC_FLOOD_MASK 0x34
114 #define B53_IPMC_FLOOD_MASK 0x36
117 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
119 * For port 8 still use B53_PORT_OVERRIDE_CTRL
120 * Please note that not all ports are available on every hardware, e.g. BCM5301X
121 * don't include overriding port 6, BCM63xx also have some limitations.
123 #define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i))
124 #define GMII_PO_LINK BIT(0)
125 #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
126 #define GMII_PO_SPEED_S 2
127 #define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S)
128 #define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S)
129 #define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S)
130 #define GMII_PO_RX_FLOW BIT(4)
131 #define GMII_PO_TX_FLOW BIT(5)
132 #define GMII_PO_EN BIT(6) /* Use the register contents */
133 #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */
135 #define B53_RGMII_CTRL_IMP 0x60
136 #define RGMII_CTRL_ENABLE_GMII BIT(7)
137 #define RGMII_CTRL_TIMING_SEL BIT(2)
138 #define RGMII_CTRL_DLL_RXC BIT(1)
139 #define RGMII_CTRL_DLL_TXC BIT(0)
141 #define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i))
143 /* Software reset register (8 bit) */
144 #define B53_SOFTRESET 0x79
145 #define SW_RST BIT(7)
146 #define EN_CH_RST BIT(6)
147 #define EN_SW_RST BIT(4)
149 /* Fast Aging Control register (8 bit) */
150 #define B53_FAST_AGE_CTRL 0x88
151 #define FAST_AGE_STATIC BIT(0)
152 #define FAST_AGE_DYNAMIC BIT(1)
153 #define FAST_AGE_PORT BIT(2)
154 #define FAST_AGE_VLAN BIT(3)
155 #define FAST_AGE_STP BIT(4)
156 #define FAST_AGE_MC BIT(5)
157 #define FAST_AGE_DONE BIT(7)
159 /* Fast Aging Port Control register (8 bit) */
160 #define B53_FAST_AGE_PORT_CTRL 0x89
162 /* Fast Aging VID Control register (16 bit) */
163 #define B53_FAST_AGE_VID_CTRL 0x8a
165 /*************************************************************************
166 * Status Page registers
167 *************************************************************************/
169 /* Link Status Summary Register (16bit) */
170 #define B53_LINK_STAT 0x00
172 /* Link Status Change Register (16 bit) */
173 #define B53_LINK_STAT_CHANGE 0x02
175 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
176 #define B53_SPEED_STAT 0x04
177 #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)
178 #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)
179 #define SPEED_STAT_10M 0
180 #define SPEED_STAT_100M 1
181 #define SPEED_STAT_1000M 2
183 /* Duplex Status Summary (16 bit) */
184 #define B53_DUPLEX_STAT_FE 0x06
185 #define B53_DUPLEX_STAT_GE 0x08
186 #define B53_DUPLEX_STAT_63XX 0x0c
188 /* Revision ID register for BCM5325 */
189 #define B53_REV_ID_25 0x50
191 /* Strap Value (48 bit) */
192 #define B53_STRAP_VALUE 0x70
193 #define SV_GMII_CTRL_115 BIT(27)
195 /*************************************************************************
196 * Management Mode Page Registers
197 *************************************************************************/
199 /* Global Management Config Register (8 bit) */
200 #define B53_GLOBAL_CONFIG 0x00
201 #define GC_RESET_MIB 0x01
202 #define GC_RX_BPDU_EN 0x02
203 #define GC_MIB_AC_HDR_EN 0x10
204 #define GC_MIB_AC_EN 0x20
205 #define GC_FRM_MGMT_PORT_M 0xC0
206 #define GC_FRM_MGMT_PORT_04 0x00
207 #define GC_FRM_MGMT_PORT_MII 0x80
209 /* Broadcom Header control register (8 bit) */
210 #define B53_BRCM_HDR 0x03
211 #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */
212 #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */
214 /* Mirror capture control register (16 bit) */
215 #define B53_MIR_CAP_CTL 0x10
216 #define CAP_PORT_MASK 0xf
217 #define BLK_NOT_MIR BIT(14)
218 #define MIRROR_EN BIT(15)
220 /* Ingress mirror control register (16 bit) */
221 #define B53_IG_MIR_CTL 0x12
222 #define MIRROR_MASK 0x1ff
223 #define DIV_EN BIT(13)
224 #define MIRROR_FILTER_MASK 0x3
225 #define MIRROR_FILTER_SHIFT 14
230 /* Ingress mirror divider register (16 bit) */
231 #define B53_IG_MIR_DIV 0x14
232 #define IN_MIRROR_DIV_MASK 0x3ff
234 /* Ingress mirror MAC address register (48 bit) */
235 #define B53_IG_MIR_MAC 0x16
237 /* Egress mirror control register (16 bit) */
238 #define B53_EG_MIR_CTL 0x1C
240 /* Egress mirror divider register (16 bit) */
241 #define B53_EG_MIR_DIV 0x1E
243 /* Egress mirror MAC address register (48 bit) */
244 #define B53_EG_MIR_MAC 0x20
246 /* Device ID register (8 or 32 bit) */
247 #define B53_DEVICE_ID 0x30
249 /* Revision ID register (8 bit) */
250 #define B53_REV_ID 0x40
252 /*************************************************************************
253 * ARL Access Page Registers
254 *************************************************************************/
256 /* VLAN Table Access Register (8 bit) */
257 #define B53_VT_ACCESS 0x80
258 #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */
259 #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */
260 #define VTA_CMD_WRITE 0
261 #define VTA_CMD_READ 1
262 #define VTA_CMD_CLEAR 2
263 #define VTA_START_CMD BIT(7)
265 /* VLAN Table Index Register (16 bit) */
266 #define B53_VT_INDEX 0x81
267 #define B53_VT_INDEX_9798 0x61
268 #define B53_VT_INDEX_63XX 0x62
270 /* VLAN Table Entry Register (32 bit) */
271 #define B53_VT_ENTRY 0x83
272 #define B53_VT_ENTRY_9798 0x63
273 #define B53_VT_ENTRY_63XX 0x64
274 #define VTE_MEMBERS 0x1ff
275 #define VTE_UNTAG_S 9
276 #define VTE_UNTAG (0x1ff << 9)
278 /*************************************************************************
280 *************************************************************************/
282 /* ARL Table Read/Write Register (8 bit) */
283 #define B53_ARLTBL_RW_CTRL 0x00
284 #define ARLTBL_RW BIT(0)
285 #define ARLTBL_START_DONE BIT(7)
287 /* MAC Address Index Register (48 bit) */
288 #define B53_MAC_ADDR_IDX 0x02
290 /* VLAN ID Index Register (16 bit) */
291 #define B53_VLAN_ID_IDX 0x08
293 /* ARL Table MAC/VID Entry N Registers (64 bit)
295 * BCM5325 and BCM5365 share most definitions below
297 #define B53_ARLTBL_MAC_VID_ENTRY(n) (0x10 * (n))
298 #define ARLTBL_MAC_MASK 0xffffffffffffULL
299 #define ARLTBL_VID_S 48
300 #define ARLTBL_VID_MASK_25 0xff
301 #define ARLTBL_VID_MASK 0xfff
302 #define ARLTBL_DATA_PORT_ID_S_25 48
303 #define ARLTBL_DATA_PORT_ID_MASK_25 0xf
304 #define ARLTBL_AGE_25 BIT(61)
305 #define ARLTBL_STATIC_25 BIT(62)
306 #define ARLTBL_VALID_25 BIT(63)
308 /* ARL Table Data Entry N Registers (32 bit) */
309 #define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x08)
310 #define ARLTBL_DATA_PORT_ID_MASK 0x1ff
311 #define ARLTBL_TC(tc) ((3 & tc) << 11)
312 #define ARLTBL_AGE BIT(14)
313 #define ARLTBL_STATIC BIT(15)
314 #define ARLTBL_VALID BIT(16)
316 /* ARL Search Control Register (8 bit) */
317 #define B53_ARL_SRCH_CTL 0x50
318 #define B53_ARL_SRCH_CTL_25 0x20
319 #define ARL_SRCH_VLID BIT(0)
320 #define ARL_SRCH_STDN BIT(7)
322 /* ARL Search Address Register (16 bit) */
323 #define B53_ARL_SRCH_ADDR 0x51
324 #define B53_ARL_SRCH_ADDR_25 0x22
325 #define B53_ARL_SRCH_ADDR_65 0x24
326 #define ARL_ADDR_MASK GENMASK(14, 0)
328 /* ARL Search MAC/VID Result (64 bit) */
329 #define B53_ARL_SRCH_RSTL_0_MACVID 0x60
331 /* Single register search result on 5325 */
332 #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24
333 /* Single register search result on 5365 */
334 #define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30
336 /* ARL Search Data Result (32 bit) */
337 #define B53_ARL_SRCH_RSTL_0 0x68
339 #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10))
340 #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10))
342 /*************************************************************************
343 * Port VLAN Registers
344 *************************************************************************/
346 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
347 #define B53_PVLAN_PORT_MASK(i) ((i) * 2)
349 /* Join all VLANs register (16 bit) */
350 #define B53_JOIN_ALL_VLAN_EN 0x50
352 /*************************************************************************
353 * 802.1Q Page Registers
354 *************************************************************************/
356 /* Global QoS Control (8 bit) */
357 #define B53_QOS_GLOBAL_CTL 0x00
359 /* Enable 802.1Q for individual Ports (16 bit) */
360 #define B53_802_1P_EN 0x04
362 /*************************************************************************
363 * VLAN Page Registers
364 *************************************************************************/
366 /* VLAN Control 0 (8 bit) */
367 #define B53_VLAN_CTRL0 0x00
368 #define VC0_8021PF_CTRL_MASK 0x3
369 #define VC0_8021PF_CTRL_NONE 0x0
370 #define VC0_8021PF_CTRL_CHANGE_PRI 0x1
371 #define VC0_8021PF_CTRL_CHANGE_VID 0x2
372 #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3
373 #define VC0_8021QF_CTRL_MASK 0xc
374 #define VC0_8021QF_CTRL_CHANGE_PRI 0x1
375 #define VC0_8021QF_CTRL_CHANGE_VID 0x2
376 #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3
377 #define VC0_RESERVED_1 BIT(1)
378 #define VC0_DROP_VID_MISS BIT(4)
379 #define VC0_VID_HASH_VID BIT(5)
380 #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */
381 #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */
383 /* VLAN Control 1 (8 bit) */
384 #define B53_VLAN_CTRL1 0x01
385 #define VC1_RX_MCST_TAG_EN BIT(1)
386 #define VC1_RX_MCST_FWD_EN BIT(2)
387 #define VC1_RX_MCST_UNTAG_EN BIT(3)
389 /* VLAN Control 2 (8 bit) */
390 #define B53_VLAN_CTRL2 0x02
392 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
393 #define B53_VLAN_CTRL3 0x03
394 #define B53_VLAN_CTRL3_63XX 0x04
395 #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */
396 #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */
398 /* VLAN Control 4 (8 bit) */
399 #define B53_VLAN_CTRL4 0x05
400 #define B53_VLAN_CTRL4_25 0x04
401 #define B53_VLAN_CTRL4_63XX 0x06
402 #define VC4_ING_VID_CHECK_S 6
403 #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S)
404 #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */
405 #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */
406 #define VC4_NO_ING_VID_CHK 2 /* do not check */
407 #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */
409 /* VLAN Control 5 (8 bit) */
410 #define B53_VLAN_CTRL5 0x06
411 #define B53_VLAN_CTRL5_25 0x05
412 #define B53_VLAN_CTRL5_63XX 0x07
413 #define VC5_VID_FFF_EN BIT(2)
414 #define VC5_DROP_VTABLE_MISS BIT(3)
416 /* VLAN Control 6 (8 bit) */
417 #define B53_VLAN_CTRL6 0x07
418 #define B53_VLAN_CTRL6_63XX 0x08
420 /* VLAN Table Access Register (16 bit) */
421 #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */
422 #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */
423 #define VTA_VID_LOW_MASK_25 0xf
424 #define VTA_VID_LOW_MASK_65 0xff
425 #define VTA_VID_HIGH_S_25 4
426 #define VTA_VID_HIGH_S_65 8
427 #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E)
428 #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65)
429 #define VTA_RW_STATE BIT(12)
430 #define VTA_RW_STATE_RD 0
431 #define VTA_RW_STATE_WR BIT(12)
432 #define VTA_RW_OP_EN BIT(13)
434 /* VLAN Read/Write Registers for (16/32 bit) */
435 #define B53_VLAN_WRITE_25 0x08
436 #define B53_VLAN_WRITE_65 0x0a
437 #define B53_VLAN_READ 0x0c
438 #define VA_MEMBER_MASK 0x3f
439 #define VA_UNTAG_S_25 6
440 #define VA_UNTAG_MASK_25 0x3f
441 #define VA_UNTAG_S_65 7
442 #define VA_UNTAG_MASK_65 0x1f
443 #define VA_VID_HIGH_S 12
444 #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S)
445 #define VA_VALID_25 BIT(20)
446 #define VA_VALID_25_R4 BIT(24)
447 #define VA_VALID_65 BIT(14)
449 /* VLAN Port Default Tag (16 bit) */
450 #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i))
452 /*************************************************************************
453 * Jumbo Frame Page Registers
454 *************************************************************************/
456 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
457 #define B53_JUMBO_PORT_MASK 0x01
458 #define B53_JUMBO_PORT_MASK_63XX 0x04
459 #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */
461 /* Good Frame Max Size without 802.1Q TAG (16 bit) */
462 #define B53_JUMBO_MAX_SIZE 0x05
463 #define B53_JUMBO_MAX_SIZE_63XX 0x08
464 #define JMS_MIN_SIZE 1518
465 #define JMS_MAX_SIZE 9724
467 /*************************************************************************
468 * CFP Configuration Page Registers
469 *************************************************************************/
471 /* CFP Control Register with ports map (8 bit) */
472 #define B53_CFP_CTRL 0x00
474 #endif /* !__B53_REGS_H */