2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <net/switchdev.h>
32 #include <linux/platform_data/b53.h>
35 #include "bcm_sf2_regs.h"
36 #include "b53/b53_priv.h"
37 #include "b53/b53_regs.h"
39 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
41 return DSA_TAG_PROTO_BRCM;
44 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
46 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
50 /* Enable the IMP Port to be in the same VLAN as the other ports
51 * on a per-port basis such that we only have Port i and IMP in
54 for (i = 0; i < priv->hw_params.num_ports; i++) {
55 if (!((1 << i) & ds->enabled_port_mask))
58 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
59 reg |= (1 << cpu_port);
60 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
64 static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port)
68 /* Resolve which bit controls the Broadcom tag */
84 /* Enable Broadcom tags for IMP port */
85 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
87 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
89 /* Enable reception Broadcom tag for CPU TX (switch RX) to
90 * allow us to tag outgoing frames
92 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
94 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
96 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
97 * allow delivering frames to the per-port net_devices
99 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
101 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
104 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
106 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
109 if (priv->type == BCM7445_DEVICE_ID)
110 offset = CORE_STS_OVERRIDE_IMP;
112 offset = CORE_STS_OVERRIDE_IMP2;
114 /* Enable the port memories */
115 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
116 reg &= ~P_TXQ_PSM_VDD(port);
117 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
119 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
120 reg = core_readl(priv, CORE_IMP_CTL);
121 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
122 reg &= ~(RX_DIS | TX_DIS);
123 core_writel(priv, reg, CORE_IMP_CTL);
125 /* Enable forwarding */
126 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
128 /* Enable IMP port in dumb mode */
129 reg = core_readl(priv, CORE_SWITCH_CTRL);
130 reg |= MII_DUMB_FWDG_EN;
131 core_writel(priv, reg, CORE_SWITCH_CTRL);
133 bcm_sf2_brcm_hdr_setup(priv, port);
135 /* Force link status for IMP port */
136 reg = core_readl(priv, offset);
137 reg |= (MII_SW_OR | LINK_STS);
138 core_writel(priv, reg, offset);
141 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
143 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
146 reg = core_readl(priv, CORE_EEE_EN_CTRL);
151 core_writel(priv, reg, CORE_EEE_EN_CTRL);
154 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
156 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
159 reg = reg_readl(priv, REG_SPHY_CNTRL);
162 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
163 reg_writel(priv, reg, REG_SPHY_CNTRL);
165 reg = reg_readl(priv, REG_SPHY_CNTRL);
168 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
169 reg_writel(priv, reg, REG_SPHY_CNTRL);
173 reg_writel(priv, reg, REG_SPHY_CNTRL);
175 /* Use PHY-driven LED signaling */
177 reg = reg_readl(priv, REG_LED_CNTRL(0));
178 reg |= SPDLNK_SRC_SEL;
179 reg_writel(priv, reg, REG_LED_CNTRL(0));
183 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
193 /* Port 0 interrupts are located on the first bank */
194 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
197 off = P_IRQ_OFF(port);
201 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
204 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
214 /* Port 0 interrupts are located on the first bank */
215 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
216 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
219 off = P_IRQ_OFF(port);
223 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
224 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
227 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
228 struct phy_device *phy)
230 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
231 s8 cpu_port = ds->dst[ds->index].cpu_port;
235 /* Clear the memory power down */
236 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
237 reg &= ~P_TXQ_PSM_VDD(port);
238 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
240 /* Enable Broadcom tags for that port if requested */
241 if (priv->brcm_tag_mask & BIT(port))
242 bcm_sf2_brcm_hdr_setup(priv, port);
244 /* Configure Traffic Class to QoS mapping, allow each priority to map
245 * to a different queue number
247 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
248 for (i = 0; i < 8; i++)
249 reg |= i << (PRT_TO_QID_SHIFT * i);
250 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
252 /* Clear the Rx and Tx disable bits and set to no spanning tree */
253 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
255 /* Re-enable the GPHY and re-apply workarounds */
256 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
257 bcm_sf2_gphy_enable_set(ds, true);
259 /* if phy_stop() has been called before, phy
260 * will be in halted state, and phy_start()
263 * the resume path does not configure back
264 * autoneg settings, and since we hard reset
265 * the phy manually here, we need to reset the
266 * state machine also.
268 phy->state = PHY_READY;
273 /* Enable MoCA port interrupts to get notified */
274 if (port == priv->moca_port)
275 bcm_sf2_port_intr_enable(priv, port);
277 /* Set this port, and only this one to be in the default VLAN,
278 * if member of a bridge, restore its membership prior to
279 * bringing down this port.
281 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
282 reg &= ~PORT_VLAN_CTRL_MASK;
284 reg |= priv->dev->ports[port].vlan_ctl_mask;
285 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
287 bcm_sf2_imp_vlan_setup(ds, cpu_port);
289 /* If EEE was enabled, restore it */
290 if (priv->port_sts[port].eee.eee_enabled)
291 bcm_sf2_eee_enable_set(ds, port, true);
296 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
297 struct phy_device *phy)
299 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
302 if (priv->wol_ports_mask & (1 << port))
305 if (port == priv->moca_port)
306 bcm_sf2_port_intr_disable(priv, port);
308 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
309 bcm_sf2_gphy_enable_set(ds, false);
311 if (dsa_is_cpu_port(ds, port))
314 off = CORE_G_PCTL_PORT(port);
316 reg = core_readl(priv, off);
317 reg |= RX_DIS | TX_DIS;
318 core_writel(priv, reg, off);
320 /* Power down the port memory */
321 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
322 reg |= P_TXQ_PSM_VDD(port);
323 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
326 /* Returns 0 if EEE was not enabled, or 1 otherwise
328 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
329 struct phy_device *phy)
331 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
332 struct ethtool_eee *p = &priv->port_sts[port].eee;
335 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
337 ret = phy_init_eee(phy, 0);
341 bcm_sf2_eee_enable_set(ds, port, true);
346 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
347 struct ethtool_eee *e)
349 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
350 struct ethtool_eee *p = &priv->port_sts[port].eee;
353 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
354 e->eee_enabled = p->eee_enabled;
355 e->eee_active = !!(reg & (1 << port));
360 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
361 struct phy_device *phydev,
362 struct ethtool_eee *e)
364 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
365 struct ethtool_eee *p = &priv->port_sts[port].eee;
367 p->eee_enabled = e->eee_enabled;
369 if (!p->eee_enabled) {
370 bcm_sf2_eee_enable_set(ds, port, false);
372 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
380 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
386 reg = reg_readl(priv, REG_SWITCH_CNTRL);
387 reg |= MDIO_MASTER_SEL;
388 reg_writel(priv, reg, REG_SWITCH_CNTRL);
390 /* Page << 8 | offset */
393 core_writel(priv, addr, reg);
395 /* Page << 8 | offset */
396 reg = 0x80 << 8 | regnum << 1;
400 ret = core_readl(priv, reg);
402 core_writel(priv, val, reg);
404 reg = reg_readl(priv, REG_SWITCH_CNTRL);
405 reg &= ~MDIO_MASTER_SEL;
406 reg_writel(priv, reg, REG_SWITCH_CNTRL);
411 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
413 struct bcm_sf2_priv *priv = bus->priv;
415 /* Intercept reads from Broadcom pseudo-PHY address, else, send
416 * them to our master MDIO bus controller
418 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
419 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
421 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
424 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
427 struct bcm_sf2_priv *priv = bus->priv;
429 /* Intercept writes to the Broadcom pseudo-PHY address, else,
430 * send them to our master MDIO bus controller
432 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
433 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
435 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val);
440 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
442 struct bcm_sf2_priv *priv = dev_id;
444 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
446 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
451 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
453 struct bcm_sf2_priv *priv = dev_id;
455 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
457 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
459 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
460 priv->port_sts[7].link = 1;
461 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
462 priv->port_sts[7].link = 0;
467 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
469 unsigned int timeout = 1000;
472 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
473 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
474 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
477 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
478 if (!(reg & SOFTWARE_RESET))
481 usleep_range(1000, 2000);
482 } while (timeout-- > 0);
490 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
492 intrl2_0_mask_set(priv, 0xffffffff);
493 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
494 intrl2_1_mask_set(priv, 0xffffffff);
495 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
498 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
499 struct device_node *dn)
501 struct device_node *port;
502 const char *phy_mode_str;
504 unsigned int port_num;
507 priv->moca_port = -1;
509 for_each_available_child_of_node(dn, port) {
510 if (of_property_read_u32(port, "reg", &port_num))
513 /* Internal PHYs get assigned a specific 'phy-mode' property
514 * value: "internal" to help flag them before MDIO probing
515 * has completed, since they might be turned off at that
518 mode = of_get_phy_mode(port);
520 ret = of_property_read_string(port, "phy-mode",
525 if (!strcasecmp(phy_mode_str, "internal"))
526 priv->int_phy_mask |= 1 << port_num;
529 if (mode == PHY_INTERFACE_MODE_MOCA)
530 priv->moca_port = port_num;
532 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
533 priv->brcm_tag_mask |= 1 << port_num;
537 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
539 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
540 struct device_node *dn;
544 /* Find our integrated MDIO bus node */
545 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
546 priv->master_mii_bus = of_mdio_find_bus(dn);
547 if (!priv->master_mii_bus)
548 return -EPROBE_DEFER;
550 get_device(&priv->master_mii_bus->dev);
551 priv->master_mii_dn = dn;
553 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
554 if (!priv->slave_mii_bus)
557 priv->slave_mii_bus->priv = priv;
558 priv->slave_mii_bus->name = "sf2 slave mii";
559 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
560 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
561 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
563 priv->slave_mii_bus->dev.of_node = dn;
565 /* Include the pseudo-PHY address to divert reads towards our
566 * workaround. This is only required for 7445D0, since 7445E0
567 * disconnects the internal switch pseudo-PHY such that we can use the
568 * regular SWITCH_MDIO master controller instead.
570 * Here we flag the pseudo PHY as needing special treatment and would
571 * otherwise make all other PHY read/writes go to the master MDIO bus
572 * controller that comes with this switch backed by the "mdio-unimac"
575 if (of_machine_is_compatible("brcm,bcm7445d0"))
576 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
578 priv->indir_phy_mask = 0;
580 ds->phys_mii_mask = priv->indir_phy_mask;
581 ds->slave_mii_bus = priv->slave_mii_bus;
582 priv->slave_mii_bus->parent = ds->dev->parent;
583 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
586 err = of_mdiobus_register(priv->slave_mii_bus, dn);
588 err = mdiobus_register(priv->slave_mii_bus);
596 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
598 mdiobus_unregister(priv->slave_mii_bus);
599 if (priv->master_mii_dn)
600 of_node_put(priv->master_mii_dn);
603 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
605 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
607 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
608 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
609 * the REG_PHY_REVISION register layout is.
612 return priv->hw_params.gphy_rev;
615 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
616 struct phy_device *phydev)
618 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
619 struct ethtool_eee *p = &priv->port_sts[port].eee;
620 u32 id_mode_dis = 0, port_mode;
621 const char *str = NULL;
624 if (priv->type == BCM7445_DEVICE_ID)
625 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
627 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
629 switch (phydev->interface) {
630 case PHY_INTERFACE_MODE_RGMII:
631 str = "RGMII (no delay)";
633 case PHY_INTERFACE_MODE_RGMII_TXID:
635 str = "RGMII (TX delay)";
636 port_mode = EXT_GPHY;
638 case PHY_INTERFACE_MODE_MII:
640 port_mode = EXT_EPHY;
642 case PHY_INTERFACE_MODE_REVMII:
644 port_mode = EXT_REVMII;
647 /* All other PHYs: internal and MoCA */
651 /* If the link is down, just disable the interface to conserve power */
653 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
654 reg &= ~RGMII_MODE_EN;
655 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
659 /* Clear id_mode_dis bit, and the existing port mode, but
660 * make sure we enable the RGMII block for data to pass
662 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
664 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
665 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
667 reg |= port_mode | RGMII_MODE_EN;
672 if (phydev->asym_pause)
677 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
679 pr_info("Port %d configured for %s\n", port, str);
682 /* Force link settings detected from the PHY */
684 switch (phydev->speed) {
686 reg |= SPDSTS_1000 << SPEED_SHIFT;
689 reg |= SPDSTS_100 << SPEED_SHIFT;
695 if (phydev->duplex == DUPLEX_FULL)
698 core_writel(priv, reg, offset);
700 if (!phydev->is_pseudo_fixed_link)
701 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
704 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
705 struct fixed_phy_status *status)
707 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
708 u32 duplex, pause, offset;
711 if (priv->type == BCM7445_DEVICE_ID)
712 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
714 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
716 duplex = core_readl(priv, CORE_DUPSTS);
717 pause = core_readl(priv, CORE_PAUSESTS);
721 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
722 * which means that we need to force the link at the port override
723 * level to get the data to flow. We do use what the interrupt handler
724 * did determine before.
726 * For the other ports, we just force the link status, since this is
727 * a fixed PHY device.
729 if (port == priv->moca_port) {
730 status->link = priv->port_sts[port].link;
731 /* For MoCA interfaces, also force a link down notification
732 * since some version of the user-space daemon (mocad) use
733 * cmd->autoneg to force the link, which messes up the PHY
734 * state machine and make it go in PHY_FORCING state instead.
737 netif_carrier_off(ds->ports[port].netdev);
741 status->duplex = !!(duplex & (1 << port));
744 reg = core_readl(priv, offset);
750 core_writel(priv, reg, offset);
752 if ((pause & (1 << port)) &&
753 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
754 status->asym_pause = 1;
758 if (pause & (1 << port))
762 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
764 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
767 bcm_sf2_intr_disable(priv);
769 /* Disable all ports physically present including the IMP
770 * port, the other ones have already been disabled during
773 for (port = 0; port < DSA_MAX_PORTS; port++) {
774 if ((1 << port) & ds->enabled_port_mask ||
775 dsa_is_cpu_port(ds, port))
776 bcm_sf2_port_disable(ds, port, NULL);
782 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
784 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
788 ret = bcm_sf2_sw_rst(priv);
790 pr_err("%s: failed to software reset switch\n", __func__);
794 if (priv->hw_params.num_gphy == 1)
795 bcm_sf2_gphy_enable_set(ds, true);
797 for (port = 0; port < DSA_MAX_PORTS; port++) {
798 if ((1 << port) & ds->enabled_port_mask)
799 bcm_sf2_port_setup(ds, port, NULL);
800 else if (dsa_is_cpu_port(ds, port))
801 bcm_sf2_imp_setup(ds, port);
807 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
808 struct ethtool_wolinfo *wol)
810 struct net_device *p = ds->dst[ds->index].master_netdev;
811 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
812 struct ethtool_wolinfo pwol;
814 /* Get the parent device WoL settings */
815 p->ethtool_ops->get_wol(p, &pwol);
817 /* Advertise the parent device supported settings */
818 wol->supported = pwol.supported;
819 memset(&wol->sopass, 0, sizeof(wol->sopass));
821 if (pwol.wolopts & WAKE_MAGICSECURE)
822 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
824 if (priv->wol_ports_mask & (1 << port))
825 wol->wolopts = pwol.wolopts;
830 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
831 struct ethtool_wolinfo *wol)
833 struct net_device *p = ds->dst[ds->index].master_netdev;
834 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
835 s8 cpu_port = ds->dst[ds->index].cpu_port;
836 struct ethtool_wolinfo pwol;
838 p->ethtool_ops->get_wol(p, &pwol);
839 if (wol->wolopts & ~pwol.supported)
843 priv->wol_ports_mask |= (1 << port);
845 priv->wol_ports_mask &= ~(1 << port);
847 /* If we have at least one port enabled, make sure the CPU port
848 * is also enabled. If the CPU port is the last one enabled, we disable
849 * it since this configuration does not make sense.
851 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
852 priv->wol_ports_mask |= (1 << cpu_port);
854 priv->wol_ports_mask &= ~(1 << cpu_port);
856 return p->ethtool_ops->set_wol(p, wol);
859 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
861 unsigned int timeout = 10;
865 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
866 if (!(reg & ARLA_VTBL_STDN))
869 usleep_range(1000, 2000);
875 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
877 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
879 return bcm_sf2_vlan_op_wait(priv);
882 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
884 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
887 /* Clear all VLANs */
888 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
890 for (port = 0; port < priv->hw_params.num_ports; port++) {
891 if (!((1 << port) & ds->enabled_port_mask))
894 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
898 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
900 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
903 /* Enable all valid ports and disable those unused */
904 for (port = 0; port < priv->hw_params.num_ports; port++) {
905 /* IMP port receives special treatment */
906 if ((1 << port) & ds->enabled_port_mask)
907 bcm_sf2_port_setup(ds, port, NULL);
908 else if (dsa_is_cpu_port(ds, port))
909 bcm_sf2_imp_setup(ds, port);
911 bcm_sf2_port_disable(ds, port, NULL);
914 bcm_sf2_sw_configure_vlan(ds);
919 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
920 * register basis so we need to translate that into an address that the
921 * bus-glue understands.
923 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
925 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
928 struct bcm_sf2_priv *priv = dev->priv;
930 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
935 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
938 struct bcm_sf2_priv *priv = dev->priv;
940 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
945 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
948 struct bcm_sf2_priv *priv = dev->priv;
950 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
955 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
958 struct bcm_sf2_priv *priv = dev->priv;
960 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
965 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
968 struct bcm_sf2_priv *priv = dev->priv;
970 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
975 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
978 struct bcm_sf2_priv *priv = dev->priv;
980 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
985 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
988 struct bcm_sf2_priv *priv = dev->priv;
990 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
995 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
998 struct bcm_sf2_priv *priv = dev->priv;
1000 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1005 static struct b53_io_ops bcm_sf2_io_ops = {
1006 .read8 = bcm_sf2_core_read8,
1007 .read16 = bcm_sf2_core_read16,
1008 .read32 = bcm_sf2_core_read32,
1009 .read48 = bcm_sf2_core_read64,
1010 .read64 = bcm_sf2_core_read64,
1011 .write8 = bcm_sf2_core_write8,
1012 .write16 = bcm_sf2_core_write16,
1013 .write32 = bcm_sf2_core_write32,
1014 .write48 = bcm_sf2_core_write64,
1015 .write64 = bcm_sf2_core_write64,
1018 static const struct dsa_switch_ops bcm_sf2_ops = {
1019 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol,
1020 .setup = bcm_sf2_sw_setup,
1021 .get_strings = b53_get_strings,
1022 .get_ethtool_stats = b53_get_ethtool_stats,
1023 .get_sset_count = b53_get_sset_count,
1024 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1025 .adjust_link = bcm_sf2_sw_adjust_link,
1026 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1027 .suspend = bcm_sf2_sw_suspend,
1028 .resume = bcm_sf2_sw_resume,
1029 .get_wol = bcm_sf2_sw_get_wol,
1030 .set_wol = bcm_sf2_sw_set_wol,
1031 .port_enable = bcm_sf2_port_setup,
1032 .port_disable = bcm_sf2_port_disable,
1033 .get_eee = bcm_sf2_sw_get_eee,
1034 .set_eee = bcm_sf2_sw_set_eee,
1035 .port_bridge_join = b53_br_join,
1036 .port_bridge_leave = b53_br_leave,
1037 .port_stp_state_set = b53_br_set_stp_state,
1038 .port_fast_age = b53_br_fast_age,
1039 .port_vlan_filtering = b53_vlan_filtering,
1040 .port_vlan_prepare = b53_vlan_prepare,
1041 .port_vlan_add = b53_vlan_add,
1042 .port_vlan_del = b53_vlan_del,
1043 .port_vlan_dump = b53_vlan_dump,
1044 .port_fdb_prepare = b53_fdb_prepare,
1045 .port_fdb_dump = b53_fdb_dump,
1046 .port_fdb_add = b53_fdb_add,
1047 .port_fdb_del = b53_fdb_del,
1048 .get_rxnfc = bcm_sf2_get_rxnfc,
1049 .set_rxnfc = bcm_sf2_set_rxnfc,
1050 .port_mirror_add = b53_mirror_add,
1051 .port_mirror_del = b53_mirror_del,
1054 struct bcm_sf2_of_data {
1056 const u16 *reg_offsets;
1057 unsigned int core_reg_align;
1060 /* Register offsets for the SWITCH_REG_* block */
1061 static const u16 bcm_sf2_7445_reg_offsets[] = {
1062 [REG_SWITCH_CNTRL] = 0x00,
1063 [REG_SWITCH_STATUS] = 0x04,
1064 [REG_DIR_DATA_WRITE] = 0x08,
1065 [REG_DIR_DATA_READ] = 0x0C,
1066 [REG_SWITCH_REVISION] = 0x18,
1067 [REG_PHY_REVISION] = 0x1C,
1068 [REG_SPHY_CNTRL] = 0x2C,
1069 [REG_RGMII_0_CNTRL] = 0x34,
1070 [REG_RGMII_1_CNTRL] = 0x40,
1071 [REG_RGMII_2_CNTRL] = 0x4c,
1072 [REG_LED_0_CNTRL] = 0x90,
1073 [REG_LED_1_CNTRL] = 0x94,
1074 [REG_LED_2_CNTRL] = 0x98,
1077 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1078 .type = BCM7445_DEVICE_ID,
1079 .core_reg_align = 0,
1080 .reg_offsets = bcm_sf2_7445_reg_offsets,
1083 static const u16 bcm_sf2_7278_reg_offsets[] = {
1084 [REG_SWITCH_CNTRL] = 0x00,
1085 [REG_SWITCH_STATUS] = 0x04,
1086 [REG_DIR_DATA_WRITE] = 0x08,
1087 [REG_DIR_DATA_READ] = 0x0c,
1088 [REG_SWITCH_REVISION] = 0x10,
1089 [REG_PHY_REVISION] = 0x14,
1090 [REG_SPHY_CNTRL] = 0x24,
1091 [REG_RGMII_0_CNTRL] = 0xe0,
1092 [REG_RGMII_1_CNTRL] = 0xec,
1093 [REG_RGMII_2_CNTRL] = 0xf8,
1094 [REG_LED_0_CNTRL] = 0x40,
1095 [REG_LED_1_CNTRL] = 0x4c,
1096 [REG_LED_2_CNTRL] = 0x58,
1099 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1100 .type = BCM7278_DEVICE_ID,
1101 .core_reg_align = 1,
1102 .reg_offsets = bcm_sf2_7278_reg_offsets,
1105 static const struct of_device_id bcm_sf2_of_match[] = {
1106 { .compatible = "brcm,bcm7445-switch-v4.0",
1107 .data = &bcm_sf2_7445_data
1109 { .compatible = "brcm,bcm7278-switch-v4.0",
1110 .data = &bcm_sf2_7278_data
1114 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1116 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1118 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1119 struct device_node *dn = pdev->dev.of_node;
1120 const struct of_device_id *of_id = NULL;
1121 const struct bcm_sf2_of_data *data;
1122 struct b53_platform_data *pdata;
1123 struct dsa_switch_ops *ops;
1124 struct bcm_sf2_priv *priv;
1125 struct b53_device *dev;
1126 struct dsa_switch *ds;
1127 void __iomem **base;
1133 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1137 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1141 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1145 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1149 of_id = of_match_node(bcm_sf2_of_match, dn);
1150 if (!of_id || !of_id->data)
1155 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1156 priv->type = data->type;
1157 priv->reg_offsets = data->reg_offsets;
1158 priv->core_reg_align = data->core_reg_align;
1160 /* Auto-detection using standard registers will not work, so
1161 * provide an indication of what kind of device we are for
1162 * b53_common to work with
1164 pdata->chip_id = priv->type;
1169 ds->ops = &bcm_sf2_ops;
1171 dev_set_drvdata(&pdev->dev, priv);
1173 spin_lock_init(&priv->indir_lock);
1174 mutex_init(&priv->stats_mutex);
1175 mutex_init(&priv->cfp.lock);
1177 /* CFP rule #0 cannot be used for specific classifications, flag it as
1180 set_bit(0, priv->cfp.used);
1182 bcm_sf2_identify_ports(priv, dn->child);
1184 priv->irq0 = irq_of_parse_and_map(dn, 0);
1185 priv->irq1 = irq_of_parse_and_map(dn, 1);
1188 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1189 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1190 *base = devm_ioremap_resource(&pdev->dev, r);
1191 if (IS_ERR(*base)) {
1192 pr_err("unable to find register: %s\n", reg_names[i]);
1193 return PTR_ERR(*base);
1198 ret = bcm_sf2_sw_rst(priv);
1200 pr_err("unable to software reset switch: %d\n", ret);
1204 ret = bcm_sf2_mdio_register(ds);
1206 pr_err("failed to register MDIO bus\n");
1210 ret = bcm_sf2_cfp_rst(priv);
1212 pr_err("failed to reset CFP\n");
1216 /* Disable all interrupts and request them */
1217 bcm_sf2_intr_disable(priv);
1219 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1222 pr_err("failed to request switch_0 IRQ\n");
1226 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1229 pr_err("failed to request switch_1 IRQ\n");
1233 /* Reset the MIB counters */
1234 reg = core_readl(priv, CORE_GMNCFGCFG);
1236 core_writel(priv, reg, CORE_GMNCFGCFG);
1237 reg &= ~RST_MIB_CNT;
1238 core_writel(priv, reg, CORE_GMNCFGCFG);
1240 /* Get the maximum number of ports for this switch */
1241 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1242 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1243 priv->hw_params.num_ports = DSA_MAX_PORTS;
1245 /* Assume a single GPHY setup if we can't read that property */
1246 if (of_property_read_u32(dn, "brcm,num-gphy",
1247 &priv->hw_params.num_gphy))
1248 priv->hw_params.num_gphy = 1;
1250 rev = reg_readl(priv, REG_SWITCH_REVISION);
1251 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1252 SWITCH_TOP_REV_MASK;
1253 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1255 rev = reg_readl(priv, REG_PHY_REVISION);
1256 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1258 ret = b53_switch_register(dev);
1262 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1263 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1264 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1265 priv->core, priv->irq0, priv->irq1);
1270 bcm_sf2_mdio_unregister(priv);
1274 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1276 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1278 /* Disable all ports and interrupts */
1279 priv->wol_ports_mask = 0;
1280 bcm_sf2_sw_suspend(priv->dev->ds);
1281 dsa_unregister_switch(priv->dev->ds);
1282 bcm_sf2_mdio_unregister(priv);
1287 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1289 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1291 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1292 * successful MDIO bus scan to occur. If we did turn off the GPHY
1293 * before (e.g: port_disable), this will also power it back on.
1295 * Do not rely on kexec_in_progress, just power the PHY on.
1297 if (priv->hw_params.num_gphy == 1)
1298 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1301 #ifdef CONFIG_PM_SLEEP
1302 static int bcm_sf2_suspend(struct device *dev)
1304 struct platform_device *pdev = to_platform_device(dev);
1305 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1307 return dsa_switch_suspend(priv->dev->ds);
1310 static int bcm_sf2_resume(struct device *dev)
1312 struct platform_device *pdev = to_platform_device(dev);
1313 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1315 return dsa_switch_resume(priv->dev->ds);
1317 #endif /* CONFIG_PM_SLEEP */
1319 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1320 bcm_sf2_suspend, bcm_sf2_resume);
1323 static struct platform_driver bcm_sf2_driver = {
1324 .probe = bcm_sf2_sw_probe,
1325 .remove = bcm_sf2_sw_remove,
1326 .shutdown = bcm_sf2_sw_shutdown,
1329 .of_match_table = bcm_sf2_of_match,
1330 .pm = &bcm_sf2_pm_ops,
1333 module_platform_driver(bcm_sf2_driver);
1335 MODULE_AUTHOR("Broadcom Corporation");
1336 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1337 MODULE_LICENSE("GPL");
1338 MODULE_ALIAS("platform:brcm-sf2");