drivers/net/dsa/bcm_sf2.h

   1 /*
   2  * Broadcom Starfighter2 private context
   3  *
   4  * Copyright (C) 2014, Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #ifndef __BCM_SF2_H
  13 #define __BCM_SF2_H
  14
  15 #include <linux/platform_device.h>
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/mutex.h>
  20 #include <linux/mii.h>
  21 #include <linux/ethtool.h>
  22 #include <linux/types.h>
  23 #include <linux/bitops.h>
  24 #include <linux/if_vlan.h>
  25
  26 #include <net/dsa.h>
  27
  28 #include "bcm_sf2_regs.h"
  29 #include "b53/b53_priv.h"
  30
  31 struct bcm_sf2_hw_params {
  32         u16     top_rev;
  33         u16     core_rev;
  34         u16     gphy_rev;
  35         u32     num_gphy;
  36         u8      num_acb_queue;
  37         u8      num_rgmii;
  38         u8      num_ports;
  39         u8      fcb_pause_override:1;
  40         u8      acb_packets_inflight:1;
  41 };
  42
  43 #define BCM_SF2_REGS_NAME {\
  44         "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
  45 }
  46
  47 #define BCM_SF2_REGS_NUM        6
  48
  49 struct bcm_sf2_port_status {
  50         unsigned int link;
  51
  52         struct ethtool_eee eee;
  53 };
  54
  55 struct bcm_sf2_priv {
  56         /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
  57         void __iomem                    *core;
  58         void __iomem                    *reg;
  59         void __iomem                    *intrl2_0;
  60         void __iomem                    *intrl2_1;
  61         void __iomem                    *fcb;
  62         void __iomem                    *acb;
  63
  64         /* Register offsets indirection tables */
  65         u32                             type;
  66         const u16                       *reg_offsets;
  67         unsigned int                    core_reg_align;
  68
  69         /* spinlock protecting access to the indirect registers */
  70         spinlock_t                      indir_lock;
  71
  72         int                             irq0;
  73         int                             irq1;
  74         u32                             irq0_stat;
  75         u32                             irq0_mask;
  76         u32                             irq1_stat;
  77         u32                             irq1_mask;
  78
  79         /* Backing b53_device */
  80         struct b53_device               *dev;
  81
  82         /* Mutex protecting access to the MIB counters */
  83         struct mutex                    stats_mutex;
  84
  85         struct bcm_sf2_hw_params        hw_params;
  86
  87         struct bcm_sf2_port_status      port_sts[DSA_MAX_PORTS];
  88
  89         /* Mask of ports enabled for Wake-on-LAN */
  90         u32                             wol_ports_mask;
  91
  92         /* MoCA port location */
  93         int                             moca_port;
  94
  95         /* Bitmask of ports having an integrated PHY */
  96         unsigned int                    int_phy_mask;
  97
  98         /* Master and slave MDIO bus controller */
  99         unsigned int                    indir_phy_mask;
 100         struct device_node              *master_mii_dn;
 101         struct mii_bus                  *slave_mii_bus;
 102         struct mii_bus                  *master_mii_bus;
 103
 104         /* Bitmask of ports needing BRCM tags */
 105         unsigned int                    brcm_tag_mask;
 106 };
 107
 108 static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
 109 {
 110         struct b53_device *dev = ds->priv;
 111
 112         return dev->priv;
 113 }
 114
 115 static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
 116 {
 117         return off << priv->core_reg_align;
 118 }
 119
 120 #define SF2_IO_MACRO(name) \
 121 static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off)      \
 122 {                                                                       \
 123         return __raw_readl(priv->name + off);                           \
 124 }                                                                       \
 125 static inline void name##_writel(struct bcm_sf2_priv *priv,             \
 126                                   u32 val, u32 off)                     \
 127 {                                                                       \
 128         __raw_writel(val, priv->name + off);                            \
 129 }                                                                       \
 130
 131 /* Accesses to 64-bits register requires us to latch the hi/lo pairs
 132  * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
 133  * spinlock is automatically grabbed and released to provide relative
 134  * atomiticy with latched reads/writes.
 135  */
 136 #define SF2_IO64_MACRO(name) \
 137 static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off)      \
 138 {                                                                       \
 139         u32 indir, dir;                                                 \
 140         spin_lock(&priv->indir_lock);                                   \
 141         dir = name##_readl(priv, off);                                  \
 142         indir = reg_readl(priv, REG_DIR_DATA_READ);                     \
 143         spin_unlock(&priv->indir_lock);                                 \
 144         return (u64)indir << 32 | dir;                                  \
 145 }                                                                       \
 146 static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val,    \
 147                                                         u32 off)        \
 148 {                                                                       \
 149         spin_lock(&priv->indir_lock);                                   \
 150         reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE);       \
 151         name##_writel(priv, lower_32_bits(val), off);                   \
 152         spin_unlock(&priv->indir_lock);                                 \
 153 }
 154
 155 #define SWITCH_INTR_L2(which)                                           \
 156 static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
 157                                                 u32 mask)               \
 158 {                                                                       \
 159         priv->irq##which##_mask &= ~(mask);                             \
 160         intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);     \
 161 }                                                                       \
 162 static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
 163                                                 u32 mask)               \
 164 {                                                                       \
 165         intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);      \
 166         priv->irq##which##_mask |= (mask);                              \
 167 }                                                                       \
 168
 169 static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
 170 {
 171         u32 tmp = bcm_sf2_mangle_addr(priv, off);
 172         return __raw_readl(priv->core + tmp);
 173 }
 174
 175 static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
 176 {
 177         u32 tmp = bcm_sf2_mangle_addr(priv, off);
 178         __raw_writel(val, priv->core + tmp);
 179 }
 180
 181 static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
 182 {
 183         return __raw_readl(priv->reg + priv->reg_offsets[off]);
 184 }
 185
 186 static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
 187 {
 188         __raw_writel(val, priv->reg + priv->reg_offsets[off]);
 189 }
 190
 191 SF2_IO64_MACRO(core);
 192 SF2_IO_MACRO(intrl2_0);
 193 SF2_IO_MACRO(intrl2_1);
 194 SF2_IO_MACRO(fcb);
 195 SF2_IO_MACRO(acb);
 196
 197 SWITCH_INTR_L2(0);
 198 SWITCH_INTR_L2(1);
 199
 200 #endif /* __BCM_SF2_H */