2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/regmap.h>
18 #include <linux/mutex.h>
19 #include <linux/mii.h>
23 #define LAN9303_CHIP_REV 0x14
24 # define LAN9303_CHIP_ID 0x9303
25 #define LAN9303_IRQ_CFG 0x15
26 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
27 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
28 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
29 #define LAN9303_INT_STS 0x16
30 # define LAN9303_INT_STS_PHY_INT2 BIT(27)
31 # define LAN9303_INT_STS_PHY_INT1 BIT(26)
32 #define LAN9303_INT_EN 0x17
33 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
34 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
35 #define LAN9303_HW_CFG 0x1D
36 # define LAN9303_HW_CFG_READY BIT(27)
37 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
38 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
39 #define LAN9303_PMI_DATA 0x29
40 #define LAN9303_PMI_ACCESS 0x2A
41 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
42 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
43 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
44 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
45 #define LAN9303_MANUAL_FC_1 0x68
46 #define LAN9303_MANUAL_FC_2 0x69
47 #define LAN9303_MANUAL_FC_0 0x6a
48 #define LAN9303_SWITCH_CSR_DATA 0x6b
49 #define LAN9303_SWITCH_CSR_CMD 0x6c
50 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
51 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
52 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
53 #define LAN9303_VIRT_PHY_BASE 0x70
54 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
56 #define LAN9303_SW_DEV_ID 0x0000
57 #define LAN9303_SW_RESET 0x0001
58 #define LAN9303_SW_RESET_RESET BIT(0)
59 #define LAN9303_SW_IMR 0x0004
60 #define LAN9303_SW_IPR 0x0005
61 #define LAN9303_MAC_VER_ID_0 0x0400
62 #define LAN9303_MAC_RX_CFG_0 0x0401
63 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
64 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
65 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
66 #define LAN9303_MAC_RX_64_CNT_0 0x0411
67 #define LAN9303_MAC_RX_127_CNT_0 0x0412
68 #define LAN9303_MAC_RX_255_CNT_0 0x413
69 #define LAN9303_MAC_RX_511_CNT_0 0x0414
70 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
71 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
72 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
73 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
74 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
75 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
76 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
77 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
78 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
79 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
80 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
81 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
82 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
83 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
84 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
86 #define LAN9303_MAC_TX_CFG_0 0x0440
87 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
88 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
89 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
90 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
91 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
92 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
93 #define LAN9303_MAC_TX_64_CNT_0 0x0454
94 #define LAN9303_MAC_TX_127_CNT_0 0x0455
95 #define LAN9303_MAC_TX_255_CNT_0 0x0456
96 #define LAN9303_MAC_TX_511_CNT_0 0x0457
97 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
98 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
99 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
100 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
101 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
102 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
103 #define LAN9303_MAC_TX_LATECOL_0 0x045f
104 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
105 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
106 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
107 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
109 #define LAN9303_MAC_VER_ID_1 0x0800
110 #define LAN9303_MAC_RX_CFG_1 0x0801
111 #define LAN9303_MAC_TX_CFG_1 0x0840
112 #define LAN9303_MAC_VER_ID_2 0x0c00
113 #define LAN9303_MAC_RX_CFG_2 0x0c01
114 #define LAN9303_MAC_TX_CFG_2 0x0c40
115 #define LAN9303_SWE_ALR_CMD 0x1800
116 #define LAN9303_SWE_VLAN_CMD 0x180b
117 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
118 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
119 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
120 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
121 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
122 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
123 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
124 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
125 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
126 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
127 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
128 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
129 #define LAN9303_SWE_PORT_STATE 0x1843
130 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
131 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
132 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
133 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
134 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
135 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
136 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
137 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
138 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
139 #define LAN9303_SWE_PORT_MIRROR 0x1846
140 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
141 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
142 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
143 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
144 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
145 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
146 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
147 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
148 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
149 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
150 #define LAN9303_BM_CFG 0x1c00
151 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
152 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
153 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
154 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
156 #define LAN9303_PORT_0_OFFSET 0x400
157 #define LAN9303_PORT_1_OFFSET 0x800
158 #define LAN9303_PORT_2_OFFSET 0xc00
160 /* the built-in PHYs are of type LAN911X */
161 #define MII_LAN911X_SPECIAL_MODES 0x12
162 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
164 static const struct regmap_range lan9303_valid_regs[] = {
165 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
166 regmap_reg_range(0x19, 0x19), /* endian test */
167 regmap_reg_range(0x1d, 0x1d), /* hardware config */
168 regmap_reg_range(0x23, 0x24), /* general purpose timer */
169 regmap_reg_range(0x27, 0x27), /* counter */
170 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
171 regmap_reg_range(0x68, 0x6a), /* flow control */
172 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
173 regmap_reg_range(0x6d, 0x6f), /* misc */
174 regmap_reg_range(0x70, 0x77), /* virtual phy */
175 regmap_reg_range(0x78, 0x7a), /* GPIO */
176 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
177 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
180 static const struct regmap_range lan9303_reserved_ranges[] = {
181 regmap_reg_range(0x00, 0x13),
182 regmap_reg_range(0x18, 0x18),
183 regmap_reg_range(0x1a, 0x1c),
184 regmap_reg_range(0x1e, 0x22),
185 regmap_reg_range(0x25, 0x26),
186 regmap_reg_range(0x28, 0x28),
187 regmap_reg_range(0x2b, 0x67),
188 regmap_reg_range(0x7b, 0x7b),
189 regmap_reg_range(0x7f, 0x7f),
190 regmap_reg_range(0xb8, 0xff),
193 const struct regmap_access_table lan9303_register_set = {
194 .yes_ranges = lan9303_valid_regs,
195 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
196 .no_ranges = lan9303_reserved_ranges,
197 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
199 EXPORT_SYMBOL(lan9303_register_set);
201 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
205 /* we can lose arbitration for the I2C case, because the device
206 * tries to detect and read an external EEPROM after reset and acts as
207 * a master on the shared I2C bus itself. This conflicts with our
208 * attempts to access the device as a slave at the same moment.
210 for (i = 0; i < 5; i++) {
211 ret = regmap_read(regmap, offset, reg);
222 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
227 if (regnum > MII_EXPANSION)
230 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
237 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
239 if (regnum > MII_EXPANSION)
242 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
245 static int lan9303_port_phy_reg_wait_for_completion(struct lan9303 *chip)
250 for (i = 0; i < 25; i++) {
251 ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®);
254 "Failed to read pmi access status: %d\n", ret);
257 if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY))
265 static int lan9303_port_phy_reg_read(struct lan9303 *chip, int addr, int regnum)
270 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
271 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
273 mutex_lock(&chip->indirect_mutex);
275 ret = lan9303_port_phy_reg_wait_for_completion(chip);
279 /* start the MII read cycle */
280 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
284 ret = lan9303_port_phy_reg_wait_for_completion(chip);
288 /* read the result of this operation */
289 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
293 mutex_unlock(&chip->indirect_mutex);
298 mutex_unlock(&chip->indirect_mutex);
302 static int lan9303_phy_reg_write(struct lan9303 *chip, int addr, int regnum,
308 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
309 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
310 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
312 mutex_lock(&chip->indirect_mutex);
314 ret = lan9303_port_phy_reg_wait_for_completion(chip);
318 /* write the data first... */
319 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
323 /* ...then start the MII write cycle */
324 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
327 mutex_unlock(&chip->indirect_mutex);
331 static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
336 for (i = 0; i < 25; i++) {
337 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®);
340 "Failed to read csr command status: %d\n", ret);
343 if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY))
351 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
357 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
358 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
360 mutex_lock(&chip->indirect_mutex);
362 ret = lan9303_switch_wait_for_completion(chip);
366 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
368 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
373 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
375 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
379 mutex_unlock(&chip->indirect_mutex);
383 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
389 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
390 reg |= LAN9303_SWITCH_CSR_CMD_RW;
391 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
393 mutex_lock(&chip->indirect_mutex);
395 ret = lan9303_switch_wait_for_completion(chip);
400 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
402 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
407 ret = lan9303_switch_wait_for_completion(chip);
411 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
413 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
415 mutex_unlock(&chip->indirect_mutex);
419 static int lan9303_detect_phy_setup(struct lan9303 *chip)
423 /* depending on the 'phy_addr_sel_strap' setting, the three phys are
424 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
425 * 'phy_addr_sel_strap' setting directly, so we need a test, which
426 * configuration is active:
427 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
428 * and the IDs are 0-1-2, else it contains something different from
429 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
431 reg = lan9303_port_phy_reg_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
433 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
438 chip->phy_addr_sel_strap = 1;
440 chip->phy_addr_sel_strap = 0;
442 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
443 chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2");
448 #define LAN9303_MAC_RX_CFG_OFFS (LAN9303_MAC_RX_CFG_0 - LAN9303_PORT_0_OFFSET)
449 #define LAN9303_MAC_TX_CFG_OFFS (LAN9303_MAC_TX_CFG_0 - LAN9303_PORT_0_OFFSET)
451 static int lan9303_disable_packet_processing(struct lan9303 *chip,
456 /* disable RX, but keep register reset default values else */
457 ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_OFFS + port,
458 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
462 /* disable TX, but keep register reset default values else */
463 return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_OFFS + port,
464 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
465 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
468 static int lan9303_enable_packet_processing(struct lan9303 *chip,
473 /* enable RX and keep register reset default values else */
474 ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_OFFS + port,
475 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
476 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
480 /* enable TX and keep register reset default values else */
481 return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_OFFS + port,
482 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
483 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
484 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
487 /* We want a special working switch:
488 * - do not forward packets between port 1 and 2
489 * - forward everything from port 1 to port 0
490 * - forward everything from port 2 to port 0
491 * - forward special tagged packets from port 0 to port 1 *or* port 2
493 static int lan9303_separate_ports(struct lan9303 *chip)
497 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
498 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
499 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
500 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
501 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
502 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
506 /* enable defining the destination port via special VLAN tagging
509 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
514 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
515 * able to discover their source port
517 ret = lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE,
518 LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0);
522 /* prevent port 1 and 2 from forwarding packets by their own */
523 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
524 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
525 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
526 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
529 static int lan9303_handle_reset(struct lan9303 *chip)
531 if (!chip->reset_gpio)
534 if (chip->reset_duration != 0)
535 msleep(chip->reset_duration);
537 /* release (deassert) reset and activate the device */
538 gpiod_set_value_cansleep(chip->reset_gpio, 0);
543 /* stop processing packets for all ports */
544 static int lan9303_disable_processing(struct lan9303 *chip)
548 ret = lan9303_disable_packet_processing(chip, LAN9303_PORT_0_OFFSET);
551 ret = lan9303_disable_packet_processing(chip, LAN9303_PORT_1_OFFSET);
554 return lan9303_disable_packet_processing(chip, LAN9303_PORT_2_OFFSET);
557 static int lan9303_check_device(struct lan9303 *chip)
562 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
564 dev_err(chip->dev, "failed to read chip revision register: %d\n",
566 if (!chip->reset_gpio) {
568 "hint: maybe failed due to missing reset GPIO\n");
573 if ((reg >> 16) != LAN9303_CHIP_ID) {
574 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
579 /* The default state of the LAN9303 device is to forward packets between
580 * all ports (if not configured differently by an external EEPROM).
581 * The initial state of a DSA device must be forwarding packets only
582 * between the external and the internal ports and no forwarding
583 * between the external ports. In preparation we stop packet handling
584 * at all for now until the LAN9303 device is re-programmed accordingly.
586 ret = lan9303_disable_processing(chip);
588 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
590 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
592 ret = lan9303_detect_phy_setup(chip);
595 "failed to discover phy bootstrap setup: %d\n", ret);
602 /* ---------------------------- DSA -----------------------------------*/
604 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds)
606 return DSA_TAG_PROTO_LAN9303;
609 static int lan9303_setup(struct dsa_switch *ds)
611 struct lan9303 *chip = ds->priv;
614 /* Make sure that port 0 is the cpu port */
615 if (!dsa_is_cpu_port(ds, 0)) {
616 dev_err(chip->dev, "port 0 is not the CPU port\n");
620 ret = lan9303_separate_ports(chip);
622 dev_err(chip->dev, "failed to separate ports %d\n", ret);
624 ret = lan9303_enable_packet_processing(chip, LAN9303_PORT_0_OFFSET);
626 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
631 struct lan9303_mib_desc {
632 unsigned int offset; /* offset of first MAC */
636 static const struct lan9303_mib_desc lan9303_mib[] = {
637 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
638 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
639 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
640 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
641 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
642 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
643 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
644 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
645 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
646 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
647 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
648 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
649 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
650 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
651 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
652 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
653 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
654 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
655 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
656 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
657 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
658 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
659 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", },
660 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
661 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
662 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
663 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
664 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
665 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
666 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
667 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
668 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
669 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
670 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
671 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
672 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
673 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
676 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
680 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
681 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
686 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
689 struct lan9303 *chip = ds->priv;
691 unsigned int u, poff;
696 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
697 ret = lan9303_read_switch_reg(chip,
698 lan9303_mib[u].offset + poff,
701 dev_warn(chip->dev, "Reading status reg %u failed\n",
702 lan9303_mib[u].offset + poff);
707 static int lan9303_get_sset_count(struct dsa_switch *ds)
709 return ARRAY_SIZE(lan9303_mib);
712 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
714 struct lan9303 *chip = ds->priv;
715 int phy_base = chip->phy_addr_sel_strap;
718 return lan9303_virt_phy_reg_read(chip, regnum);
719 if (phy > phy_base + 2)
722 return lan9303_port_phy_reg_read(chip, phy, regnum);
725 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
728 struct lan9303 *chip = ds->priv;
729 int phy_base = chip->phy_addr_sel_strap;
732 return lan9303_virt_phy_reg_write(chip, regnum, val);
733 if (phy > phy_base + 2)
736 return lan9303_phy_reg_write(chip, phy, regnum, val);
739 static int lan9303_port_enable(struct dsa_switch *ds, int port,
740 struct phy_device *phy)
742 struct lan9303 *chip = ds->priv;
744 /* enable internal packet processing */
747 return lan9303_enable_packet_processing(chip,
748 LAN9303_PORT_1_OFFSET);
750 return lan9303_enable_packet_processing(chip,
751 LAN9303_PORT_2_OFFSET);
754 "Error: request to power up invalid port %d\n", port);
760 static void lan9303_port_disable(struct dsa_switch *ds, int port,
761 struct phy_device *phy)
763 struct lan9303 *chip = ds->priv;
765 /* disable internal packet processing */
768 lan9303_disable_packet_processing(chip, LAN9303_PORT_1_OFFSET);
769 lan9303_phy_reg_write(chip, chip->phy_addr_sel_strap + 1,
770 MII_BMCR, BMCR_PDOWN);
773 lan9303_disable_packet_processing(chip, LAN9303_PORT_2_OFFSET);
774 lan9303_phy_reg_write(chip, chip->phy_addr_sel_strap + 2,
775 MII_BMCR, BMCR_PDOWN);
779 "Error: request to power down invalid port %d\n", port);
783 static struct dsa_switch_ops lan9303_switch_ops = {
784 .get_tag_protocol = lan9303_get_tag_protocol,
785 .setup = lan9303_setup,
786 .get_strings = lan9303_get_strings,
787 .phy_read = lan9303_phy_read,
788 .phy_write = lan9303_phy_write,
789 .get_ethtool_stats = lan9303_get_ethtool_stats,
790 .get_sset_count = lan9303_get_sset_count,
791 .port_enable = lan9303_port_enable,
792 .port_disable = lan9303_port_disable,
795 static int lan9303_register_switch(struct lan9303 *chip)
797 chip->ds = dsa_switch_alloc(chip->dev, DSA_MAX_PORTS);
801 chip->ds->priv = chip;
802 chip->ds->ops = &lan9303_switch_ops;
803 chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7;
805 return dsa_register_switch(chip->ds, chip->dev);
808 static void lan9303_probe_reset_gpio(struct lan9303 *chip,
809 struct device_node *np)
811 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
814 if (!chip->reset_gpio) {
815 dev_dbg(chip->dev, "No reset GPIO defined\n");
819 chip->reset_duration = 200;
822 of_property_read_u32(np, "reset-duration",
823 &chip->reset_duration);
825 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
828 /* A sane reset duration should not be longer than 1s */
829 if (chip->reset_duration > 1000)
830 chip->reset_duration = 1000;
833 int lan9303_probe(struct lan9303 *chip, struct device_node *np)
837 mutex_init(&chip->indirect_mutex);
839 lan9303_probe_reset_gpio(chip, np);
841 ret = lan9303_handle_reset(chip);
845 ret = lan9303_check_device(chip);
849 ret = lan9303_register_switch(chip);
851 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
857 EXPORT_SYMBOL(lan9303_probe);
859 int lan9303_remove(struct lan9303 *chip)
863 rc = lan9303_disable_processing(chip);
865 dev_warn(chip->dev, "shutting down failed\n");
867 dsa_unregister_switch(chip->ds);
869 /* assert reset to the whole device to prevent it from doing anything */
870 gpiod_set_value_cansleep(chip->reset_gpio, 1);
871 gpiod_unexport(chip->reset_gpio);
875 EXPORT_SYMBOL(lan9303_remove);
877 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
878 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
879 MODULE_LICENSE("GPL v2");