2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <linux/etherdevice.h>
15 #include <linux/if_bridge.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/gpio/consumer.h>
31 #include <net/switchdev.h>
35 /* String, offset, and register size in bytes if different from 4 bytes */
36 static const struct mt7530_mib_desc mt7530_mib[] = {
37 MIB_DESC(1, 0x00, "TxDrop"),
38 MIB_DESC(1, 0x04, "TxCrcErr"),
39 MIB_DESC(1, 0x08, "TxUnicast"),
40 MIB_DESC(1, 0x0c, "TxMulticast"),
41 MIB_DESC(1, 0x10, "TxBroadcast"),
42 MIB_DESC(1, 0x14, "TxCollision"),
43 MIB_DESC(1, 0x18, "TxSingleCollision"),
44 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
45 MIB_DESC(1, 0x20, "TxDeferred"),
46 MIB_DESC(1, 0x24, "TxLateCollision"),
47 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
48 MIB_DESC(1, 0x2c, "TxPause"),
49 MIB_DESC(1, 0x30, "TxPktSz64"),
50 MIB_DESC(1, 0x34, "TxPktSz65To127"),
51 MIB_DESC(1, 0x38, "TxPktSz128To255"),
52 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
53 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
54 MIB_DESC(1, 0x44, "Tx1024ToMax"),
55 MIB_DESC(2, 0x48, "TxBytes"),
56 MIB_DESC(1, 0x60, "RxDrop"),
57 MIB_DESC(1, 0x64, "RxFiltering"),
58 MIB_DESC(1, 0x6c, "RxMulticast"),
59 MIB_DESC(1, 0x70, "RxBroadcast"),
60 MIB_DESC(1, 0x74, "RxAlignErr"),
61 MIB_DESC(1, 0x78, "RxCrcErr"),
62 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
63 MIB_DESC(1, 0x80, "RxFragErr"),
64 MIB_DESC(1, 0x84, "RxOverSzErr"),
65 MIB_DESC(1, 0x88, "RxJabberErr"),
66 MIB_DESC(1, 0x8c, "RxPause"),
67 MIB_DESC(1, 0x90, "RxPktSz64"),
68 MIB_DESC(1, 0x94, "RxPktSz65To127"),
69 MIB_DESC(1, 0x98, "RxPktSz128To255"),
70 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
71 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
72 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
73 MIB_DESC(2, 0xa8, "RxBytes"),
74 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
75 MIB_DESC(1, 0xb4, "RxIngressDrop"),
76 MIB_DESC(1, 0xb8, "RxArlDrop"),
80 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
84 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
87 "failed to priv write register\n");
92 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
97 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
100 "failed to priv read register\n");
108 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
113 val = mt7623_trgmii_read(priv, reg);
116 mt7623_trgmii_write(priv, reg, val);
120 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
122 mt7623_trgmii_rmw(priv, reg, 0, val);
126 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
128 mt7623_trgmii_rmw(priv, reg, val, 0);
132 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
134 struct mii_bus *bus = priv->bus;
137 /* Write the desired MMD Devad */
138 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
142 /* Write the desired MMD register address */
143 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
147 /* Select the Function : DATA with no post increment */
148 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
152 /* Read the content of the MMD's selected register */
153 value = bus->read(bus, 0, MII_MMD_DATA);
157 dev_err(&bus->dev, "failed to read mmd register\n");
163 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
166 struct mii_bus *bus = priv->bus;
169 /* Write the desired MMD Devad */
170 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
174 /* Write the desired MMD register address */
175 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
179 /* Select the Function : DATA with no post increment */
180 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
184 /* Write the data into MMD's selected register */
185 ret = bus->write(bus, 0, MII_MMD_DATA, data);
189 "failed to write mmd register\n");
194 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
196 struct mii_bus *bus = priv->bus;
198 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
200 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
202 mutex_unlock(&bus->mdio_lock);
206 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
208 struct mii_bus *bus = priv->bus;
211 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
213 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
216 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
218 mutex_unlock(&bus->mdio_lock);
222 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
224 core_rmw(priv, reg, 0, val);
228 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
230 core_rmw(priv, reg, val, 0);
234 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
236 struct mii_bus *bus = priv->bus;
240 page = (reg >> 6) & 0x3ff;
241 r = (reg >> 2) & 0xf;
245 /* MT7530 uses 31 as the pseudo port */
246 ret = bus->write(bus, 0x1f, 0x1f, page);
250 ret = bus->write(bus, 0x1f, r, lo);
254 ret = bus->write(bus, 0x1f, 0x10, hi);
258 "failed to write mt7530 register\n");
263 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
265 struct mii_bus *bus = priv->bus;
269 page = (reg >> 6) & 0x3ff;
270 r = (reg >> 2) & 0xf;
272 /* MT7530 uses 31 as the pseudo port */
273 ret = bus->write(bus, 0x1f, 0x1f, page);
276 "failed to read mt7530 register\n");
280 lo = bus->read(bus, 0x1f, r);
281 hi = bus->read(bus, 0x1f, 0x10);
283 return (hi << 16) | (lo & 0xffff);
287 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
289 struct mii_bus *bus = priv->bus;
291 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
293 mt7530_mii_write(priv, reg, val);
295 mutex_unlock(&bus->mdio_lock);
299 _mt7530_read(struct mt7530_dummy_poll *p)
301 struct mii_bus *bus = p->priv->bus;
304 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
306 val = mt7530_mii_read(p->priv, p->reg);
308 mutex_unlock(&bus->mdio_lock);
314 mt7530_read(struct mt7530_priv *priv, u32 reg)
316 struct mt7530_dummy_poll p;
318 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
319 return _mt7530_read(&p);
323 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
326 struct mii_bus *bus = priv->bus;
329 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
331 val = mt7530_mii_read(priv, reg);
334 mt7530_mii_write(priv, reg, val);
336 mutex_unlock(&bus->mdio_lock);
340 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
342 mt7530_rmw(priv, reg, 0, val);
346 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
348 mt7530_rmw(priv, reg, val, 0);
352 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
356 struct mt7530_dummy_poll p;
358 /* Set the command operating upon the MAC address entries */
359 val = ATC_BUSY | ATC_MAT(0) | cmd;
360 mt7530_write(priv, MT7530_ATC, val);
362 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
363 ret = readx_poll_timeout(_mt7530_read, &p, val,
364 !(val & ATC_BUSY), 20, 20000);
366 dev_err(priv->dev, "reset timeout\n");
370 /* Additional sanity for read command if the specified
373 val = mt7530_read(priv, MT7530_ATC);
374 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
384 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
389 /* Read from ARL table into an array */
390 for (i = 0; i < 3; i++) {
391 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
393 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
394 __func__, __LINE__, i, reg[i]);
397 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
398 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
399 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
400 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
401 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
402 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
403 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
404 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
405 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
406 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
410 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
411 u8 port_mask, const u8 *mac,
417 reg[1] |= vid & CVID_MASK;
418 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
419 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
420 /* STATIC_ENT indicate that entry is static wouldn't
421 * be aged out and STATIC_EMP specified as erasing an
424 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
425 reg[1] |= mac[5] << MAC_BYTE_5;
426 reg[1] |= mac[4] << MAC_BYTE_4;
427 reg[0] |= mac[3] << MAC_BYTE_3;
428 reg[0] |= mac[2] << MAC_BYTE_2;
429 reg[0] |= mac[1] << MAC_BYTE_1;
430 reg[0] |= mac[0] << MAC_BYTE_0;
432 /* Write array into the ARL table */
433 for (i = 0; i < 3; i++)
434 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
438 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
440 struct mt7530_priv *priv = ds->priv;
441 u32 ncpo1, ssc_delta, trgint, i;
444 case PHY_INTERFACE_MODE_RGMII:
449 case PHY_INTERFACE_MODE_TRGMII:
455 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
459 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
460 P6_INTF_MODE(trgint));
462 /* Lower Tx Driving for TRGMII path */
463 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
464 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
465 TD_DM_DRVP(8) | TD_DM_DRVN(8));
467 /* Setup core clock for MT7530 */
469 /* Disable MT7530 core clock */
470 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
472 /* Disable PLL, since phy_device has not yet been created
473 * provided for phy_[read,write]_mmd_indirect is called, we
474 * provide our own core_write_mmd_indirect to complete this
477 core_write_mmd_indirect(priv,
482 /* Set core clock into 500Mhz */
483 core_write(priv, CORE_GSWPLL_GRP2,
484 RG_GSWPLL_POSDIV_500M(1) |
485 RG_GSWPLL_FBKDIV_500M(25));
488 core_write(priv, CORE_GSWPLL_GRP1,
490 RG_GSWPLL_POSDIV_200M(2) |
491 RG_GSWPLL_FBKDIV_200M(32));
493 /* Enable MT7530 core clock */
494 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
497 /* Setup the MT7530 TRGMII Tx Clock */
498 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
499 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
500 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
501 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
502 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
503 core_write(priv, CORE_PLL_GROUP4,
504 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
505 RG_SYSPLL_BIAS_LPF_EN);
506 core_write(priv, CORE_PLL_GROUP2,
507 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
508 RG_SYSPLL_POSDIV(1));
509 core_write(priv, CORE_PLL_GROUP7,
510 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
511 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
512 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
513 REG_GSWCK_EN | REG_TRGMIICK_EN);
516 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
517 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
518 RD_TAP_MASK, RD_TAP(16));
520 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
526 mt7623_pad_clk_setup(struct dsa_switch *ds)
528 struct mt7530_priv *priv = ds->priv;
531 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
532 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
533 TD_DM_DRVP(8) | TD_DM_DRVN(8));
535 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
536 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
542 mt7530_mib_reset(struct dsa_switch *ds)
544 struct mt7530_priv *priv = ds->priv;
546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
547 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
551 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
553 u32 mask = PMCR_TX_EN | PMCR_RX_EN;
556 mt7530_set(priv, MT7530_PMCR_P(port), mask);
558 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
561 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
563 struct mt7530_priv *priv = ds->priv;
565 return mdiobus_read_nested(priv->bus, port, regnum);
568 int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
570 struct mt7530_priv *priv = ds->priv;
572 return mdiobus_write_nested(priv->bus, port, regnum, val);
576 mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
580 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
581 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
586 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
589 struct mt7530_priv *priv = ds->priv;
590 const struct mt7530_mib_desc *mib;
594 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
595 mib = &mt7530_mib[i];
596 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
598 data[i] = mt7530_read(priv, reg);
599 if (mib->size == 2) {
600 hi = mt7530_read(priv, reg + 4);
607 mt7530_get_sset_count(struct dsa_switch *ds)
609 return ARRAY_SIZE(mt7530_mib);
612 static void mt7530_adjust_link(struct dsa_switch *ds, int port,
613 struct phy_device *phydev)
615 struct mt7530_priv *priv = ds->priv;
617 if (phy_is_pseudo_fixed_link(phydev)) {
618 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
621 /* Setup TX circuit incluing relevant PAD and driving */
622 mt7530_pad_clk_setup(ds, phydev->interface);
624 /* Setup RX circuit, relevant PAD and driving on the host
625 * which must be placed after the setup on the device side is
628 mt7623_pad_clk_setup(ds);
633 mt7530_cpu_port_enable(struct mt7530_priv *priv,
636 /* Enable Mediatek header mode on the cpu port */
637 mt7530_write(priv, MT7530_PVC_P(port),
640 /* Setup the MAC by default for the cpu port */
641 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
643 /* Disable auto learning on the cpu port */
644 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
646 /* Unknown unicast frame fordwarding to the cpu port */
647 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
649 /* CPU port gets connected to all user ports of
652 mt7530_write(priv, MT7530_PCR_P(port),
653 PCR_MATRIX(priv->ds->enabled_port_mask));
659 mt7530_port_enable(struct dsa_switch *ds, int port,
660 struct phy_device *phy)
662 struct mt7530_priv *priv = ds->priv;
664 mutex_lock(&priv->reg_mutex);
666 /* Setup the MAC for the user port */
667 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
669 /* Allow the user port gets connected to the cpu port and also
670 * restore the port matrix if the port is the member of a certain
673 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
674 priv->ports[port].enable = true;
675 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
676 priv->ports[port].pm);
677 mt7530_port_set_status(priv, port, 1);
679 mutex_unlock(&priv->reg_mutex);
685 mt7530_port_disable(struct dsa_switch *ds, int port,
686 struct phy_device *phy)
688 struct mt7530_priv *priv = ds->priv;
690 mutex_lock(&priv->reg_mutex);
692 /* Clear up all port matrix which could be restored in the next
693 * enablement for the port.
695 priv->ports[port].enable = false;
696 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
698 mt7530_port_set_status(priv, port, 0);
700 mutex_unlock(&priv->reg_mutex);
704 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
706 struct mt7530_priv *priv = ds->priv;
710 case BR_STATE_DISABLED:
711 stp_state = MT7530_STP_DISABLED;
713 case BR_STATE_BLOCKING:
714 stp_state = MT7530_STP_BLOCKING;
716 case BR_STATE_LISTENING:
717 stp_state = MT7530_STP_LISTENING;
719 case BR_STATE_LEARNING:
720 stp_state = MT7530_STP_LEARNING;
722 case BR_STATE_FORWARDING:
724 stp_state = MT7530_STP_FORWARDING;
728 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
732 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
733 struct net_device *bridge)
735 struct mt7530_priv *priv = ds->priv;
736 u32 port_bitmap = BIT(MT7530_CPU_PORT);
739 mutex_lock(&priv->reg_mutex);
741 for (i = 0; i < MT7530_NUM_PORTS; i++) {
742 /* Add this port to the port matrix of the other ports in the
743 * same bridge. If the port is disabled, port matrix is kept
744 * and not being setup until the port becomes enabled.
746 if (ds->enabled_port_mask & BIT(i) && i != port) {
747 if (ds->ports[i].bridge_dev != bridge)
749 if (priv->ports[i].enable)
750 mt7530_set(priv, MT7530_PCR_P(i),
751 PCR_MATRIX(BIT(port)));
752 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
754 port_bitmap |= BIT(i);
758 /* Add the all other ports to this port matrix. */
759 if (priv->ports[port].enable)
760 mt7530_rmw(priv, MT7530_PCR_P(port),
761 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
762 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
764 mutex_unlock(&priv->reg_mutex);
770 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
771 struct net_device *bridge)
773 struct mt7530_priv *priv = ds->priv;
776 mutex_lock(&priv->reg_mutex);
778 for (i = 0; i < MT7530_NUM_PORTS; i++) {
779 /* Remove this port from the port matrix of the other ports
780 * in the same bridge. If the port is disabled, port matrix
781 * is kept and not being setup until the port becomes enabled.
783 if (ds->enabled_port_mask & BIT(i) && i != port) {
784 if (ds->ports[i].bridge_dev != bridge)
786 if (priv->ports[i].enable)
787 mt7530_clear(priv, MT7530_PCR_P(i),
788 PCR_MATRIX(BIT(port)));
789 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
793 /* Set the cpu port to be the only one in the port matrix of
796 if (priv->ports[port].enable)
797 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
798 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
799 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
801 mutex_unlock(&priv->reg_mutex);
805 mt7530_port_fdb_prepare(struct dsa_switch *ds, int port,
806 const struct switchdev_obj_port_fdb *fdb,
807 struct switchdev_trans *trans)
809 struct mt7530_priv *priv = ds->priv;
812 /* Because auto-learned entrie shares the same FDB table.
813 * an entry is reserved with no port_mask to make sure fdb_add
814 * is called while the entry is still available.
816 mutex_lock(&priv->reg_mutex);
817 mt7530_fdb_write(priv, fdb->vid, 0, fdb->addr, -1, STATIC_ENT);
818 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
819 mutex_unlock(&priv->reg_mutex);
825 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
826 const struct switchdev_obj_port_fdb *fdb,
827 struct switchdev_trans *trans)
829 struct mt7530_priv *priv = ds->priv;
830 u8 port_mask = BIT(port);
832 mutex_lock(&priv->reg_mutex);
833 mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_ENT);
834 mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
835 mutex_unlock(&priv->reg_mutex);
839 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
840 const struct switchdev_obj_port_fdb *fdb)
842 struct mt7530_priv *priv = ds->priv;
844 u8 port_mask = BIT(port);
846 mutex_lock(&priv->reg_mutex);
847 mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_EMP);
848 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
849 mutex_unlock(&priv->reg_mutex);
855 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
856 struct switchdev_obj_port_fdb *fdb,
857 int (*cb)(struct switchdev_obj *obj))
859 struct mt7530_priv *priv = ds->priv;
860 struct mt7530_fdb _fdb = { 0 };
861 int cnt = MT7530_NUM_FDB_RECORDS;
865 mutex_lock(&priv->reg_mutex);
867 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
872 if (rsp & ATC_SRCH_HIT) {
873 mt7530_fdb_read(priv, &_fdb);
874 if (_fdb.port_mask & BIT(port)) {
875 ether_addr_copy(fdb->addr, _fdb.mac);
877 fdb->ndm_state = _fdb.noarp ?
878 NUD_NOARP : NUD_REACHABLE;
885 !(rsp & ATC_SRCH_END) &&
886 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
888 mutex_unlock(&priv->reg_mutex);
893 static enum dsa_tag_protocol
894 mtk_get_tag_protocol(struct dsa_switch *ds)
896 struct mt7530_priv *priv = ds->priv;
898 if (!dsa_is_cpu_port(ds, MT7530_CPU_PORT)) {
900 "port not matched with tagging CPU port\n");
901 return DSA_TAG_PROTO_NONE;
903 return DSA_TAG_PROTO_MTK;
908 mt7530_setup(struct dsa_switch *ds)
910 struct mt7530_priv *priv = ds->priv;
913 struct device_node *dn;
914 struct mt7530_dummy_poll p;
916 /* The parent node of master_netdev which holds the common system
917 * controller also is the container for two GMACs nodes representing
918 * as two netdev instances.
920 dn = ds->master_netdev->dev.of_node->parent;
921 priv->ethernet = syscon_node_to_regmap(dn);
922 if (IS_ERR(priv->ethernet))
923 return PTR_ERR(priv->ethernet);
925 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
926 ret = regulator_enable(priv->core_pwr);
929 "Failed to enable core power: %d\n", ret);
933 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
934 ret = regulator_enable(priv->io_pwr);
936 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
941 /* Reset whole chip through gpio pin or memory-mapped registers for
942 * different type of hardware
945 reset_control_assert(priv->rstc);
946 usleep_range(1000, 1100);
947 reset_control_deassert(priv->rstc);
949 gpiod_set_value_cansleep(priv->reset, 0);
950 usleep_range(1000, 1100);
951 gpiod_set_value_cansleep(priv->reset, 1);
954 /* Waiting for MT7530 got to stable */
955 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
956 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
959 dev_err(priv->dev, "reset timeout\n");
963 id = mt7530_read(priv, MT7530_CREV);
964 id >>= CHIP_NAME_SHIFT;
965 if (id != MT7530_ID) {
966 dev_err(priv->dev, "chip %x can't be supported\n", id);
970 /* Reset the switch through internal reset */
971 mt7530_write(priv, MT7530_SYS_CTRL,
972 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
975 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
976 val = mt7530_read(priv, MT7530_MHWTRAP);
977 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
978 val |= MHWTRAP_MANUAL;
979 mt7530_write(priv, MT7530_MHWTRAP, val);
981 /* Enable and reset MIB counters */
982 mt7530_mib_reset(ds);
984 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
986 for (i = 0; i < MT7530_NUM_PORTS; i++) {
987 /* Disable forwarding by default on all ports */
988 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
991 if (dsa_is_cpu_port(ds, i))
992 mt7530_cpu_port_enable(priv, i);
994 mt7530_port_disable(ds, i, NULL);
997 /* Flush the FDB table */
998 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, 0);
1005 static struct dsa_switch_ops mt7530_switch_ops = {
1006 .get_tag_protocol = mtk_get_tag_protocol,
1007 .setup = mt7530_setup,
1008 .get_strings = mt7530_get_strings,
1009 .phy_read = mt7530_phy_read,
1010 .phy_write = mt7530_phy_write,
1011 .get_ethtool_stats = mt7530_get_ethtool_stats,
1012 .get_sset_count = mt7530_get_sset_count,
1013 .adjust_link = mt7530_adjust_link,
1014 .port_enable = mt7530_port_enable,
1015 .port_disable = mt7530_port_disable,
1016 .port_stp_state_set = mt7530_stp_state_set,
1017 .port_bridge_join = mt7530_port_bridge_join,
1018 .port_bridge_leave = mt7530_port_bridge_leave,
1019 .port_fdb_prepare = mt7530_port_fdb_prepare,
1020 .port_fdb_add = mt7530_port_fdb_add,
1021 .port_fdb_del = mt7530_port_fdb_del,
1022 .port_fdb_dump = mt7530_port_fdb_dump,
1026 mt7530_probe(struct mdio_device *mdiodev)
1028 struct mt7530_priv *priv;
1029 struct device_node *dn;
1031 dn = mdiodev->dev.of_node;
1033 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1037 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1041 /* Use medatek,mcm property to distinguish hardware type that would
1042 * casues a little bit differences on power-on sequence.
1044 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1046 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1048 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1049 if (IS_ERR(priv->rstc)) {
1050 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1051 return PTR_ERR(priv->rstc);
1055 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1056 if (IS_ERR(priv->core_pwr))
1057 return PTR_ERR(priv->core_pwr);
1059 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1060 if (IS_ERR(priv->io_pwr))
1061 return PTR_ERR(priv->io_pwr);
1063 /* Not MCM that indicates switch works as the remote standalone
1064 * integrated circuit so the GPIO pin would be used to complete
1065 * the reset, otherwise memory-mapped register accessing used
1066 * through syscon provides in the case of MCM.
1069 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1071 if (IS_ERR(priv->reset)) {
1072 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1073 return PTR_ERR(priv->reset);
1077 priv->bus = mdiodev->bus;
1078 priv->dev = &mdiodev->dev;
1079 priv->ds->priv = priv;
1080 priv->ds->ops = &mt7530_switch_ops;
1081 mutex_init(&priv->reg_mutex);
1082 dev_set_drvdata(&mdiodev->dev, priv);
1084 return dsa_register_switch(priv->ds, &mdiodev->dev);
1088 mt7530_remove(struct mdio_device *mdiodev)
1090 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1093 ret = regulator_disable(priv->core_pwr);
1096 "Failed to disable core power: %d\n", ret);
1098 ret = regulator_disable(priv->io_pwr);
1100 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1103 dsa_unregister_switch(priv->ds);
1104 mutex_destroy(&priv->reg_mutex);
1107 static const struct of_device_id mt7530_of_match[] = {
1108 { .compatible = "mediatek,mt7530" },
1112 static struct mdio_driver mt7530_mdio_driver = {
1113 .probe = mt7530_probe,
1114 .remove = mt7530_remove,
1117 .of_match_table = mt7530_of_match,
1121 mdio_module_driver(mt7530_mdio_driver);
1123 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1124 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1125 MODULE_LICENSE("GPL");
1126 MODULE_ALIAS("platform:mediatek-mt7530");