2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
19 #define REG_PORT(p) (8 + (p))
20 #define REG_GLOBAL 0x0f
22 static int reg_read(struct dsa_switch *ds, int addr, int reg)
24 return mdiobus_read(to_mii_bus(ds->master_dev),
25 ds->pd->sw_addr + addr, reg);
28 #define REG_READ(addr, reg) \
32 __ret = reg_read(ds, addr, reg); \
39 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
41 return mdiobus_write(to_mii_bus(ds->master_dev),
42 ds->pd->sw_addr + addr, reg, val);
45 #define REG_WRITE(addr, reg, val) \
49 __ret = reg_write(ds, addr, reg, val); \
54 static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
56 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
62 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
66 return "Marvell 88E6060";
72 static int mv88e6060_switch_reset(struct dsa_switch *ds)
76 unsigned long timeout;
78 /* Set all ports to the disabled state. */
79 for (i = 0; i < 6; i++) {
80 ret = REG_READ(REG_PORT(i), 0x04);
81 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
84 /* Wait for transmit queues to drain. */
85 usleep_range(2000, 4000);
87 /* Reset the switch. */
88 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
90 /* Wait up to one second for reset to complete. */
91 timeout = jiffies + 1 * HZ;
92 while (time_before(jiffies, timeout)) {
93 ret = REG_READ(REG_GLOBAL, 0x00);
94 if ((ret & 0x8000) == 0x0000)
97 usleep_range(1000, 2000);
99 if (time_after(jiffies, timeout))
105 static int mv88e6060_setup_global(struct dsa_switch *ds)
107 /* Disable discarding of frames with excessive collisions,
108 * set the maximum frame size to 1536 bytes, and mask all
111 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
113 /* Enable automatic address learning, set the address
114 * database size to 1024 entries, and set the default aging
117 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
122 static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
124 int addr = REG_PORT(p);
126 /* Do not force flow control, disable Ingress and Egress
127 * Header tagging, disable VLAN tunneling, and set the port
128 * state to Forwarding. Additionally, if this is the CPU
129 * port, enable Ingress and Egress Trailer tagging mode.
131 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
133 /* Port based VLAN map: give each port its own address
134 * database, allow the CPU port to talk to each of the 'real'
135 * ports, and allow each of the 'real' ports to only talk to
138 REG_WRITE(addr, 0x06,
140 (dsa_is_cpu_port(ds, p) ?
142 (1 << ds->dst->cpu_port)));
144 /* Port Association Vector: when learning source addresses
145 * of packets, add the address to the address database using
146 * a port bitmap that has only the bit for this port set and
147 * the other bits clear.
149 REG_WRITE(addr, 0x0b, 1 << p);
154 static int mv88e6060_setup(struct dsa_switch *ds)
159 ret = mv88e6060_switch_reset(ds);
163 /* @@@ initialise atu */
165 ret = mv88e6060_setup_global(ds);
169 for (i = 0; i < 6; i++) {
170 ret = mv88e6060_setup_port(ds, i);
178 static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
180 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
181 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
182 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
187 static int mv88e6060_port_to_phy_addr(int port)
189 if (port >= 0 && port <= 5)
194 static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
198 addr = mv88e6060_port_to_phy_addr(port);
202 return reg_read(ds, addr, regnum);
206 mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
210 addr = mv88e6060_port_to_phy_addr(port);
214 return reg_write(ds, addr, regnum, val);
217 static void mv88e6060_poll_link(struct dsa_switch *ds)
221 for (i = 0; i < DSA_MAX_PORTS; i++) {
222 struct net_device *dev;
223 int uninitialized_var(port_status);
234 if (dev->flags & IFF_UP) {
235 port_status = reg_read(ds, REG_PORT(i), 0x00);
239 link = !!(port_status & 0x1000);
243 if (netif_carrier_ok(dev)) {
244 netdev_info(dev, "link down\n");
245 netif_carrier_off(dev);
250 speed = (port_status & 0x0100) ? 100 : 10;
251 duplex = (port_status & 0x0200) ? 1 : 0;
252 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
254 if (!netif_carrier_ok(dev)) {
256 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
258 duplex ? "full" : "half",
260 netif_carrier_on(dev);
265 static struct dsa_switch_driver mv88e6060_switch_driver = {
266 .tag_protocol = DSA_TAG_PROTO_TRAILER,
267 .probe = mv88e6060_probe,
268 .setup = mv88e6060_setup,
269 .set_addr = mv88e6060_set_addr,
270 .phy_read = mv88e6060_phy_read,
271 .phy_write = mv88e6060_phy_write,
272 .poll_link = mv88e6060_poll_link,
275 static int __init mv88e6060_init(void)
277 register_switch_driver(&mv88e6060_switch_driver);
280 module_init(mv88e6060_init);
282 static void __exit mv88e6060_cleanup(void)
284 unregister_switch_driver(&mv88e6060_switch_driver);
286 module_exit(mv88e6060_cleanup);
288 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
289 MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
290 MODULE_LICENSE("GPL");
291 MODULE_ALIAS("platform:mv88e6060");