drivers/net/dsa/mv88e6131.c

   1 /*
   2  * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 static const struct mv88e6xxx_switch_id mv88e6131_table[] = {
  21         { PORT_SWITCH_ID_6085, "Marvell 88E6085" },
  22         { PORT_SWITCH_ID_6095, "Marvell 88E6095/88E6095F" },
  23         { PORT_SWITCH_ID_6131, "Marvell 88E6131" },
  24         { PORT_SWITCH_ID_6131_B2, "Marvell 88E6131 (B2)" },
  25         { PORT_SWITCH_ID_6185, "Marvell 88E6185" },
  26 };
  27
  28 static char *mv88e6131_probe(struct device *dsa_dev, struct device *host_dev,
  29                              int sw_addr, void **priv)
  30 {
  31         struct mv88e6xxx_priv_state *ps;
  32         char *name;
  33
  34         name = mv88e6xxx_lookup_name(host_dev, sw_addr, mv88e6131_table,
  35                                      ARRAY_SIZE(mv88e6131_table));
  36         if (name) {
  37                 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
  38                 if (!ps)
  39                         return NULL;
  40                 *priv = ps;
  41         }
  42         return name;
  43 }
  44
  45 static int mv88e6131_setup_global(struct dsa_switch *ds)
  46 {
  47         u32 upstream_port = dsa_upstream_port(ds);
  48         int ret;
  49         u32 reg;
  50
  51         ret = mv88e6xxx_setup_global(ds);
  52         if (ret)
  53                 return ret;
  54
  55         /* Enable the PHY polling unit, don't discard packets with
  56          * excessive collisions, use a weighted fair queueing scheme
  57          * to arbitrate between packet queues, set the maximum frame
  58          * size to 1632, and mask all interrupt sources.
  59          */
  60         REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
  61                   GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632);
  62
  63         /* Set the VLAN ethertype to 0x8100. */
  64         REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
  65
  66         /* Disable ARP mirroring, and configure the upstream port as
  67          * the port to which ingress and egress monitor frames are to
  68          * be sent.
  69          */
  70         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
  71                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
  72                 GLOBAL_MONITOR_CONTROL_ARP_DISABLED;
  73         REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
  74
  75         /* Disable cascade port functionality unless this device
  76          * is used in a cascade configuration, and set the switch's
  77          * DSA device number.
  78          */
  79         if (ds->dst->pd->nr_chips > 1)
  80                 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
  81                           GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
  82                           (ds->index & 0x1f));
  83         else
  84                 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,
  85                           GLOBAL_CONTROL_2_NO_CASCADE |
  86                           (ds->index & 0x1f));
  87
  88         /* Force the priority of IGMP/MLD snoop frames and ARP frames
  89          * to the highest setting.
  90          */
  91         REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
  92                   GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |
  93                   7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |
  94                   GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |
  95                   7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);
  96
  97         return 0;
  98 }
  99
 100 static int mv88e6131_setup(struct dsa_switch *ds)
 101 {
 102         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 103         int ret;
 104
 105         ps->ds = ds;
 106
 107         ret = mv88e6xxx_setup_common(ds);
 108         if (ret < 0)
 109                 return ret;
 110
 111         mv88e6xxx_ppu_state_init(ds);
 112
 113         switch (ps->id) {
 114         case PORT_SWITCH_ID_6085:
 115         case PORT_SWITCH_ID_6185:
 116                 ps->num_ports = 10;
 117                 break;
 118         case PORT_SWITCH_ID_6095:
 119                 ps->num_ports = 11;
 120                 break;
 121         case PORT_SWITCH_ID_6131:
 122         case PORT_SWITCH_ID_6131_B2:
 123                 ps->num_ports = 8;
 124                 break;
 125         default:
 126                 return -ENODEV;
 127         }
 128
 129         ret = mv88e6xxx_switch_reset(ds, false);
 130         if (ret < 0)
 131                 return ret;
 132
 133         ret = mv88e6131_setup_global(ds);
 134         if (ret < 0)
 135                 return ret;
 136
 137         return mv88e6xxx_setup_ports(ds);
 138 }
 139
 140 static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port)
 141 {
 142         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 143
 144         if (port >= 0 && port < ps->num_ports)
 145                 return port;
 146
 147         return -EINVAL;
 148 }
 149
 150 static int
 151 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
 152 {
 153         int addr = mv88e6131_port_to_phy_addr(ds, port);
 154
 155         if (addr < 0)
 156                 return addr;
 157
 158         return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
 159 }
 160
 161 static int
 162 mv88e6131_phy_write(struct dsa_switch *ds,
 163                               int port, int regnum, u16 val)
 164 {
 165         int addr = mv88e6131_port_to_phy_addr(ds, port);
 166
 167         if (addr < 0)
 168                 return addr;
 169
 170         return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
 171 }
 172
 173 struct dsa_switch_driver mv88e6131_switch_driver = {
 174         .tag_protocol           = DSA_TAG_PROTO_DSA,
 175         .probe                  = mv88e6131_probe,
 176         .setup                  = mv88e6131_setup,
 177         .set_addr               = mv88e6xxx_set_addr_direct,
 178         .phy_read               = mv88e6131_phy_read,
 179         .phy_write              = mv88e6131_phy_write,
 180         .get_strings            = mv88e6xxx_get_strings,
 181         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
 182         .get_sset_count         = mv88e6xxx_get_sset_count,
 183         .adjust_link            = mv88e6xxx_adjust_link,
 184         .port_bridge_join       = mv88e6xxx_port_bridge_join,
 185         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
 186         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
 187         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
 188         .port_vlan_add          = mv88e6xxx_port_vlan_add,
 189         .port_vlan_del          = mv88e6xxx_port_vlan_del,
 190         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
 191         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
 192         .port_fdb_add           = mv88e6xxx_port_fdb_add,
 193         .port_fdb_del           = mv88e6xxx_port_fdb_del,
 194         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
 195 };
 196
 197 MODULE_ALIAS("platform:mv88e6085");
 198 MODULE_ALIAS("platform:mv88e6095");
 199 MODULE_ALIAS("platform:mv88e6095f");
 200 MODULE_ALIAS("platform:mv88e6131");