drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
 220                           u16 mask)
 221 {
 222         unsigned long timeout = jiffies + HZ / 10;
 223
 224         while (time_before(jiffies, timeout)) {
 225                 u16 val;
 226                 int err;
 227
 228                 err = mv88e6xxx_read(chip, addr, reg, &val);
 229                 if (err)
 230                         return err;
 231
 232                 if (!(val & mask))
 233                         return 0;
 234
 235                 usleep_range(1000, 2000);
 236         }
 237
 238         return -ETIMEDOUT;
 239 }
 240
 241 /* Indirect write to single pointer-data register with an Update bit */
 242 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 243                             u16 update)
 244 {
 245         u16 val;
 246         int i, err;
 247
 248         /* Wait until the previous operation is completed */
 249         for (i = 0; i < 16; ++i) {
 250                 err = mv88e6xxx_read(chip, addr, reg, &val);
 251                 if (err)
 252                         return err;
 253
 254                 if (!(val & BIT(15)))
 255                         break;
 256         }
 257
 258         if (i == 16)
 259                 return -ETIMEDOUT;
 260
 261         /* Set the Update bit to trigger a write operation */
 262         val = BIT(15) | update;
 263
 264         return mv88e6xxx_write(chip, addr, reg, val);
 265 }
 266
 267 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 268 {
 269         u16 val;
 270         int err;
 271
 272         err = mv88e6xxx_read(chip, addr, reg, &val);
 273         if (err)
 274                 return err;
 275
 276         return val;
 277 }
 278
 279 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 280                                 int reg, u16 val)
 281 {
 282         return mv88e6xxx_write(chip, addr, reg, val);
 283 }
 284
 285 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
 286                                       int addr, int regnum)
 287 {
 288         if (addr >= 0)
 289                 return _mv88e6xxx_reg_read(chip, addr, regnum);
 290         return 0xffff;
 291 }
 292
 293 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
 294                                        int addr, int regnum, u16 val)
 295 {
 296         if (addr >= 0)
 297                 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
 298         return 0;
 299 }
 300
 301 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 302 {
 303         int ret;
 304         unsigned long timeout;
 305
 306         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 307         if (ret < 0)
 308                 return ret;
 309
 310         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 311                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 312         if (ret)
 313                 return ret;
 314
 315         timeout = jiffies + 1 * HZ;
 316         while (time_before(jiffies, timeout)) {
 317                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 318                 if (ret < 0)
 319                         return ret;
 320
 321                 usleep_range(1000, 2000);
 322                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 323                     GLOBAL_STATUS_PPU_POLLING)
 324                         return 0;
 325         }
 326
 327         return -ETIMEDOUT;
 328 }
 329
 330 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 331 {
 332         int ret, err;
 333         unsigned long timeout;
 334
 335         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 336         if (ret < 0)
 337                 return ret;
 338
 339         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 340                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 341         if (err)
 342                 return err;
 343
 344         timeout = jiffies + 1 * HZ;
 345         while (time_before(jiffies, timeout)) {
 346                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 347                 if (ret < 0)
 348                         return ret;
 349
 350                 usleep_range(1000, 2000);
 351                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 352                     GLOBAL_STATUS_PPU_POLLING)
 353                         return 0;
 354         }
 355
 356         return -ETIMEDOUT;
 357 }
 358
 359 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 360 {
 361         struct mv88e6xxx_chip *chip;
 362
 363         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 364
 365         mutex_lock(&chip->reg_lock);
 366
 367         if (mutex_trylock(&chip->ppu_mutex)) {
 368                 if (mv88e6xxx_ppu_enable(chip) == 0)
 369                         chip->ppu_disabled = 0;
 370                 mutex_unlock(&chip->ppu_mutex);
 371         }
 372
 373         mutex_unlock(&chip->reg_lock);
 374 }
 375
 376 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 377 {
 378         struct mv88e6xxx_chip *chip = (void *)_ps;
 379
 380         schedule_work(&chip->ppu_work);
 381 }
 382
 383 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 384 {
 385         int ret;
 386
 387         mutex_lock(&chip->ppu_mutex);
 388
 389         /* If the PHY polling unit is enabled, disable it so that
 390          * we can access the PHY registers.  If it was already
 391          * disabled, cancel the timer that is going to re-enable
 392          * it.
 393          */
 394         if (!chip->ppu_disabled) {
 395                 ret = mv88e6xxx_ppu_disable(chip);
 396                 if (ret < 0) {
 397                         mutex_unlock(&chip->ppu_mutex);
 398                         return ret;
 399                 }
 400                 chip->ppu_disabled = 1;
 401         } else {
 402                 del_timer(&chip->ppu_timer);
 403                 ret = 0;
 404         }
 405
 406         return ret;
 407 }
 408
 409 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 410 {
 411         /* Schedule a timer to re-enable the PHY polling unit. */
 412         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 413         mutex_unlock(&chip->ppu_mutex);
 414 }
 415
 416 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 417 {
 418         mutex_init(&chip->ppu_mutex);
 419         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 420         init_timer(&chip->ppu_timer);
 421         chip->ppu_timer.data = (unsigned long)chip;
 422         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 423 }
 424
 425 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
 426                                    int regnum)
 427 {
 428         int ret;
 429
 430         ret = mv88e6xxx_ppu_access_get(chip);
 431         if (ret >= 0) {
 432                 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
 433                 mv88e6xxx_ppu_access_put(chip);
 434         }
 435
 436         return ret;
 437 }
 438
 439 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
 440                                     int regnum, u16 val)
 441 {
 442         int ret;
 443
 444         ret = mv88e6xxx_ppu_access_get(chip);
 445         if (ret >= 0) {
 446                 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
 447                 mv88e6xxx_ppu_access_put(chip);
 448         }
 449
 450         return ret;
 451 }
 452
 453 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 454 {
 455         return chip->info->family == MV88E6XXX_FAMILY_6065;
 456 }
 457
 458 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 459 {
 460         return chip->info->family == MV88E6XXX_FAMILY_6095;
 461 }
 462
 463 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 464 {
 465         return chip->info->family == MV88E6XXX_FAMILY_6097;
 466 }
 467
 468 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 469 {
 470         return chip->info->family == MV88E6XXX_FAMILY_6165;
 471 }
 472
 473 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 474 {
 475         return chip->info->family == MV88E6XXX_FAMILY_6185;
 476 }
 477
 478 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 479 {
 480         return chip->info->family == MV88E6XXX_FAMILY_6320;
 481 }
 482
 483 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 484 {
 485         return chip->info->family == MV88E6XXX_FAMILY_6351;
 486 }
 487
 488 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 489 {
 490         return chip->info->family == MV88E6XXX_FAMILY_6352;
 491 }
 492
 493 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 494 {
 495         return chip->info->num_databases;
 496 }
 497
 498 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 499 {
 500         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 501         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 502             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 503                 return true;
 504
 505         return false;
 506 }
 507
 508 /* We expect the switch to perform auto negotiation if there is a real
 509  * phy. However, in the case of a fixed link phy, we force the port
 510  * settings from the fixed link settings.
 511  */
 512 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 513                                   struct phy_device *phydev)
 514 {
 515         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 516         u32 reg;
 517         int ret;
 518
 519         if (!phy_is_pseudo_fixed_link(phydev))
 520                 return;
 521
 522         mutex_lock(&chip->reg_lock);
 523
 524         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 525         if (ret < 0)
 526                 goto out;
 527
 528         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 529                       PORT_PCS_CTRL_FORCE_LINK |
 530                       PORT_PCS_CTRL_DUPLEX_FULL |
 531                       PORT_PCS_CTRL_FORCE_DUPLEX |
 532                       PORT_PCS_CTRL_UNFORCED);
 533
 534         reg |= PORT_PCS_CTRL_FORCE_LINK;
 535         if (phydev->link)
 536                 reg |= PORT_PCS_CTRL_LINK_UP;
 537
 538         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 539                 goto out;
 540
 541         switch (phydev->speed) {
 542         case SPEED_1000:
 543                 reg |= PORT_PCS_CTRL_1000;
 544                 break;
 545         case SPEED_100:
 546                 reg |= PORT_PCS_CTRL_100;
 547                 break;
 548         case SPEED_10:
 549                 reg |= PORT_PCS_CTRL_10;
 550                 break;
 551         default:
 552                 pr_info("Unknown speed");
 553                 goto out;
 554         }
 555
 556         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 557         if (phydev->duplex == DUPLEX_FULL)
 558                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 559
 560         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 561             (port >= chip->info->num_ports - 2)) {
 562                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 563                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 564                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 565                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 566                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 567                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 568                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 569         }
 570         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 571
 572 out:
 573         mutex_unlock(&chip->reg_lock);
 574 }
 575
 576 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 577 {
 578         int ret;
 579         int i;
 580
 581         for (i = 0; i < 10; i++) {
 582                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 583                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 584                         return 0;
 585         }
 586
 587         return -ETIMEDOUT;
 588 }
 589
 590 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 591 {
 592         int ret;
 593
 594         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 595                 port = (port + 1) << 5;
 596
 597         /* Snapshot the hardware statistics counters for this port. */
 598         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 599                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 600                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 601         if (ret < 0)
 602                 return ret;
 603
 604         /* Wait for the snapshotting to complete. */
 605         ret = _mv88e6xxx_stats_wait(chip);
 606         if (ret < 0)
 607                 return ret;
 608
 609         return 0;
 610 }
 611
 612 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 613                                   int stat, u32 *val)
 614 {
 615         u32 _val;
 616         int ret;
 617
 618         *val = 0;
 619
 620         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 621                                    GLOBAL_STATS_OP_READ_CAPTURED |
 622                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 623         if (ret < 0)
 624                 return;
 625
 626         ret = _mv88e6xxx_stats_wait(chip);
 627         if (ret < 0)
 628                 return;
 629
 630         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 631         if (ret < 0)
 632                 return;
 633
 634         _val = ret << 16;
 635
 636         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 637         if (ret < 0)
 638                 return;
 639
 640         *val = _val | ret;
 641 }
 642
 643 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 644         { "in_good_octets",     8, 0x00, BANK0, },
 645         { "in_bad_octets",      4, 0x02, BANK0, },
 646         { "in_unicast",         4, 0x04, BANK0, },
 647         { "in_broadcasts",      4, 0x06, BANK0, },
 648         { "in_multicasts",      4, 0x07, BANK0, },
 649         { "in_pause",           4, 0x16, BANK0, },
 650         { "in_undersize",       4, 0x18, BANK0, },
 651         { "in_fragments",       4, 0x19, BANK0, },
 652         { "in_oversize",        4, 0x1a, BANK0, },
 653         { "in_jabber",          4, 0x1b, BANK0, },
 654         { "in_rx_error",        4, 0x1c, BANK0, },
 655         { "in_fcs_error",       4, 0x1d, BANK0, },
 656         { "out_octets",         8, 0x0e, BANK0, },
 657         { "out_unicast",        4, 0x10, BANK0, },
 658         { "out_broadcasts",     4, 0x13, BANK0, },
 659         { "out_multicasts",     4, 0x12, BANK0, },
 660         { "out_pause",          4, 0x15, BANK0, },
 661         { "excessive",          4, 0x11, BANK0, },
 662         { "collisions",         4, 0x1e, BANK0, },
 663         { "deferred",           4, 0x05, BANK0, },
 664         { "single",             4, 0x14, BANK0, },
 665         { "multiple",           4, 0x17, BANK0, },
 666         { "out_fcs_error",      4, 0x03, BANK0, },
 667         { "late",               4, 0x1f, BANK0, },
 668         { "hist_64bytes",       4, 0x08, BANK0, },
 669         { "hist_65_127bytes",   4, 0x09, BANK0, },
 670         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 671         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 672         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 673         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 674         { "sw_in_discards",     4, 0x10, PORT, },
 675         { "sw_in_filtered",     2, 0x12, PORT, },
 676         { "sw_out_filtered",    2, 0x13, PORT, },
 677         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 678         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 679         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 680         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 681         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 682         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 683         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 684         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 685         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 686         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 687         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 688         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 689         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 690         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 691         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 692         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 693         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 694         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 695         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 696         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 697         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 698         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 699         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 700         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 701         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 702         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 703 };
 704
 705 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 706                                struct mv88e6xxx_hw_stat *stat)
 707 {
 708         switch (stat->type) {
 709         case BANK0:
 710                 return true;
 711         case BANK1:
 712                 return mv88e6xxx_6320_family(chip);
 713         case PORT:
 714                 return mv88e6xxx_6095_family(chip) ||
 715                         mv88e6xxx_6185_family(chip) ||
 716                         mv88e6xxx_6097_family(chip) ||
 717                         mv88e6xxx_6165_family(chip) ||
 718                         mv88e6xxx_6351_family(chip) ||
 719                         mv88e6xxx_6352_family(chip);
 720         }
 721         return false;
 722 }
 723
 724 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 725                                             struct mv88e6xxx_hw_stat *s,
 726                                             int port)
 727 {
 728         u32 low;
 729         u32 high = 0;
 730         int ret;
 731         u64 value;
 732
 733         switch (s->type) {
 734         case PORT:
 735                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 736                 if (ret < 0)
 737                         return UINT64_MAX;
 738
 739                 low = ret;
 740                 if (s->sizeof_stat == 4) {
 741                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 742                                                   s->reg + 1);
 743                         if (ret < 0)
 744                                 return UINT64_MAX;
 745                         high = ret;
 746                 }
 747                 break;
 748         case BANK0:
 749         case BANK1:
 750                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 751                 if (s->sizeof_stat == 8)
 752                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 753         }
 754         value = (((u64)high) << 16) | low;
 755         return value;
 756 }
 757
 758 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 759                                   uint8_t *data)
 760 {
 761         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 762         struct mv88e6xxx_hw_stat *stat;
 763         int i, j;
 764
 765         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 766                 stat = &mv88e6xxx_hw_stats[i];
 767                 if (mv88e6xxx_has_stat(chip, stat)) {
 768                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 769                                ETH_GSTRING_LEN);
 770                         j++;
 771                 }
 772         }
 773 }
 774
 775 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 776 {
 777         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 778         struct mv88e6xxx_hw_stat *stat;
 779         int i, j;
 780
 781         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 782                 stat = &mv88e6xxx_hw_stats[i];
 783                 if (mv88e6xxx_has_stat(chip, stat))
 784                         j++;
 785         }
 786         return j;
 787 }
 788
 789 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 790                                         uint64_t *data)
 791 {
 792         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 793         struct mv88e6xxx_hw_stat *stat;
 794         int ret;
 795         int i, j;
 796
 797         mutex_lock(&chip->reg_lock);
 798
 799         ret = _mv88e6xxx_stats_snapshot(chip, port);
 800         if (ret < 0) {
 801                 mutex_unlock(&chip->reg_lock);
 802                 return;
 803         }
 804         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 805                 stat = &mv88e6xxx_hw_stats[i];
 806                 if (mv88e6xxx_has_stat(chip, stat)) {
 807                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 808                         j++;
 809                 }
 810         }
 811
 812         mutex_unlock(&chip->reg_lock);
 813 }
 814
 815 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 816 {
 817         return 32 * sizeof(u16);
 818 }
 819
 820 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 821                                struct ethtool_regs *regs, void *_p)
 822 {
 823         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 824         u16 *p = _p;
 825         int i;
 826
 827         regs->version = 0;
 828
 829         memset(p, 0xff, 32 * sizeof(u16));
 830
 831         mutex_lock(&chip->reg_lock);
 832
 833         for (i = 0; i < 32; i++) {
 834                 int ret;
 835
 836                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 837                 if (ret >= 0)
 838                         p[i] = ret;
 839         }
 840
 841         mutex_unlock(&chip->reg_lock);
 842 }
 843
 844 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
 845 {
 846         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 847                               GLOBAL2_SMI_OP_BUSY);
 848 }
 849
 850 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 851 {
 852         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 853                               GLOBAL_ATU_OP_BUSY);
 854 }
 855
 856 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
 857                                         int addr, int regnum)
 858 {
 859         int ret;
 860
 861         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 862                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
 863                                    regnum);
 864         if (ret < 0)
 865                 return ret;
 866
 867         ret = mv88e6xxx_mdio_wait(chip);
 868         if (ret < 0)
 869                 return ret;
 870
 871         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
 872
 873         return ret;
 874 }
 875
 876 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
 877                                          int addr, int regnum, u16 val)
 878 {
 879         int ret;
 880
 881         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
 882         if (ret < 0)
 883                 return ret;
 884
 885         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 886                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
 887                                    regnum);
 888
 889         return mv88e6xxx_mdio_wait(chip);
 890 }
 891
 892 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 893                              struct ethtool_eee *e)
 894 {
 895         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 896         int reg;
 897
 898         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 899                 return -EOPNOTSUPP;
 900
 901         mutex_lock(&chip->reg_lock);
 902
 903         reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
 904         if (reg < 0)
 905                 goto out;
 906
 907         e->eee_enabled = !!(reg & 0x0200);
 908         e->tx_lpi_enabled = !!(reg & 0x0100);
 909
 910         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
 911         if (reg < 0)
 912                 goto out;
 913
 914         e->eee_active = !!(reg & PORT_STATUS_EEE);
 915         reg = 0;
 916
 917 out:
 918         mutex_unlock(&chip->reg_lock);
 919         return reg;
 920 }
 921
 922 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 923                              struct phy_device *phydev, struct ethtool_eee *e)
 924 {
 925         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 926         int reg;
 927         int ret;
 928
 929         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 930                 return -EOPNOTSUPP;
 931
 932         mutex_lock(&chip->reg_lock);
 933
 934         ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
 935         if (ret < 0)
 936                 goto out;
 937
 938         reg = ret & ~0x0300;
 939         if (e->eee_enabled)
 940                 reg |= 0x0200;
 941         if (e->tx_lpi_enabled)
 942                 reg |= 0x0100;
 943
 944         ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
 945 out:
 946         mutex_unlock(&chip->reg_lock);
 947
 948         return ret;
 949 }
 950
 951 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 952 {
 953         int ret;
 954
 955         if (mv88e6xxx_has_fid_reg(chip)) {
 956                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 957                                            fid);
 958                 if (ret < 0)
 959                         return ret;
 960         } else if (mv88e6xxx_num_databases(chip) == 256) {
 961                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 962                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
 963                 if (ret < 0)
 964                         return ret;
 965
 966                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
 967                                            (ret & 0xfff) |
 968                                            ((fid << 8) & 0xf000));
 969                 if (ret < 0)
 970                         return ret;
 971
 972                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
 973                 cmd |= fid & 0xf;
 974         }
 975
 976         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
 977         if (ret < 0)
 978                 return ret;
 979
 980         return _mv88e6xxx_atu_wait(chip);
 981 }
 982
 983 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
 984                                      struct mv88e6xxx_atu_entry *entry)
 985 {
 986         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
 987
 988         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
 989                 unsigned int mask, shift;
 990
 991                 if (entry->trunk) {
 992                         data |= GLOBAL_ATU_DATA_TRUNK;
 993                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
 994                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
 995                 } else {
 996                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
 997                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
 998                 }
 999
1000                 data |= (entry->portv_trunkid << shift) & mask;
1001         }
1002
1003         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1004 }
1005
1006 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1007                                      struct mv88e6xxx_atu_entry *entry,
1008                                      bool static_too)
1009 {
1010         int op;
1011         int err;
1012
1013         err = _mv88e6xxx_atu_wait(chip);
1014         if (err)
1015                 return err;
1016
1017         err = _mv88e6xxx_atu_data_write(chip, entry);
1018         if (err)
1019                 return err;
1020
1021         if (entry->fid) {
1022                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1023                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1024         } else {
1025                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1026                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1027         }
1028
1029         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1030 }
1031
1032 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1033                                 u16 fid, bool static_too)
1034 {
1035         struct mv88e6xxx_atu_entry entry = {
1036                 .fid = fid,
1037                 .state = 0, /* EntryState bits must be 0 */
1038         };
1039
1040         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1041 }
1042
1043 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1044                                int from_port, int to_port, bool static_too)
1045 {
1046         struct mv88e6xxx_atu_entry entry = {
1047                 .trunk = false,
1048                 .fid = fid,
1049         };
1050
1051         /* EntryState bits must be 0xF */
1052         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1053
1054         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1055         entry.portv_trunkid = (to_port & 0x0f) << 4;
1056         entry.portv_trunkid |= from_port & 0x0f;
1057
1058         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1059 }
1060
1061 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1062                                  int port, bool static_too)
1063 {
1064         /* Destination port 0xF means remove the entries */
1065         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1066 }
1067
1068 static const char * const mv88e6xxx_port_state_names[] = {
1069         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1070         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1071         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1072         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1073 };
1074
1075 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1076                                  u8 state)
1077 {
1078         struct dsa_switch *ds = chip->ds;
1079         int reg, ret = 0;
1080         u8 oldstate;
1081
1082         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1083         if (reg < 0)
1084                 return reg;
1085
1086         oldstate = reg & PORT_CONTROL_STATE_MASK;
1087
1088         if (oldstate != state) {
1089                 /* Flush forwarding database if we're moving a port
1090                  * from Learning or Forwarding state to Disabled or
1091                  * Blocking or Listening state.
1092                  */
1093                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1094                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1095                     (state == PORT_CONTROL_STATE_DISABLED ||
1096                      state == PORT_CONTROL_STATE_BLOCKING)) {
1097                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1098                         if (ret)
1099                                 return ret;
1100                 }
1101
1102                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1103                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1104                                            reg);
1105                 if (ret)
1106                         return ret;
1107
1108                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1109                            mv88e6xxx_port_state_names[state],
1110                            mv88e6xxx_port_state_names[oldstate]);
1111         }
1112
1113         return ret;
1114 }
1115
1116 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1117 {
1118         struct net_device *bridge = chip->ports[port].bridge_dev;
1119         const u16 mask = (1 << chip->info->num_ports) - 1;
1120         struct dsa_switch *ds = chip->ds;
1121         u16 output_ports = 0;
1122         int reg;
1123         int i;
1124
1125         /* allow CPU port or DSA link(s) to send frames to every port */
1126         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1127                 output_ports = mask;
1128         } else {
1129                 for (i = 0; i < chip->info->num_ports; ++i) {
1130                         /* allow sending frames to every group member */
1131                         if (bridge && chip->ports[i].bridge_dev == bridge)
1132                                 output_ports |= BIT(i);
1133
1134                         /* allow sending frames to CPU port and DSA link(s) */
1135                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1136                                 output_ports |= BIT(i);
1137                 }
1138         }
1139
1140         /* prevent frames from going back out of the port they came in on */
1141         output_ports &= ~BIT(port);
1142
1143         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1144         if (reg < 0)
1145                 return reg;
1146
1147         reg &= ~mask;
1148         reg |= output_ports & mask;
1149
1150         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1151 }
1152
1153 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1154                                          u8 state)
1155 {
1156         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1157         int stp_state;
1158         int err;
1159
1160         switch (state) {
1161         case BR_STATE_DISABLED:
1162                 stp_state = PORT_CONTROL_STATE_DISABLED;
1163                 break;
1164         case BR_STATE_BLOCKING:
1165         case BR_STATE_LISTENING:
1166                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1167                 break;
1168         case BR_STATE_LEARNING:
1169                 stp_state = PORT_CONTROL_STATE_LEARNING;
1170                 break;
1171         case BR_STATE_FORWARDING:
1172         default:
1173                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1174                 break;
1175         }
1176
1177         mutex_lock(&chip->reg_lock);
1178         err = _mv88e6xxx_port_state(chip, port, stp_state);
1179         mutex_unlock(&chip->reg_lock);
1180
1181         if (err)
1182                 netdev_err(ds->ports[port].netdev,
1183                            "failed to update state to %s\n",
1184                            mv88e6xxx_port_state_names[stp_state]);
1185 }
1186
1187 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1188                                 u16 *new, u16 *old)
1189 {
1190         struct dsa_switch *ds = chip->ds;
1191         u16 pvid;
1192         int ret;
1193
1194         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1195         if (ret < 0)
1196                 return ret;
1197
1198         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1199
1200         if (new) {
1201                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1202                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1203
1204                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1205                                            PORT_DEFAULT_VLAN, ret);
1206                 if (ret < 0)
1207                         return ret;
1208
1209                 netdev_dbg(ds->ports[port].netdev,
1210                            "DefaultVID %d (was %d)\n", *new, pvid);
1211         }
1212
1213         if (old)
1214                 *old = pvid;
1215
1216         return 0;
1217 }
1218
1219 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1220                                     int port, u16 *pvid)
1221 {
1222         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1223 }
1224
1225 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1226                                     int port, u16 pvid)
1227 {
1228         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1229 }
1230
1231 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1232 {
1233         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1234                               GLOBAL_VTU_OP_BUSY);
1235 }
1236
1237 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1238 {
1239         int ret;
1240
1241         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1242         if (ret < 0)
1243                 return ret;
1244
1245         return _mv88e6xxx_vtu_wait(chip);
1246 }
1247
1248 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1249 {
1250         int ret;
1251
1252         ret = _mv88e6xxx_vtu_wait(chip);
1253         if (ret < 0)
1254                 return ret;
1255
1256         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1257 }
1258
1259 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1260                                         struct mv88e6xxx_vtu_stu_entry *entry,
1261                                         unsigned int nibble_offset)
1262 {
1263         u16 regs[3];
1264         int i;
1265         int ret;
1266
1267         for (i = 0; i < 3; ++i) {
1268                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1269                                           GLOBAL_VTU_DATA_0_3 + i);
1270                 if (ret < 0)
1271                         return ret;
1272
1273                 regs[i] = ret;
1274         }
1275
1276         for (i = 0; i < chip->info->num_ports; ++i) {
1277                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1278                 u16 reg = regs[i / 4];
1279
1280                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1281         }
1282
1283         return 0;
1284 }
1285
1286 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1287                                    struct mv88e6xxx_vtu_stu_entry *entry)
1288 {
1289         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1290 }
1291
1292 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1293                                    struct mv88e6xxx_vtu_stu_entry *entry)
1294 {
1295         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1296 }
1297
1298 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1299                                          struct mv88e6xxx_vtu_stu_entry *entry,
1300                                          unsigned int nibble_offset)
1301 {
1302         u16 regs[3] = { 0 };
1303         int i;
1304         int ret;
1305
1306         for (i = 0; i < chip->info->num_ports; ++i) {
1307                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1308                 u8 data = entry->data[i];
1309
1310                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1311         }
1312
1313         for (i = 0; i < 3; ++i) {
1314                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1315                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1316                 if (ret < 0)
1317                         return ret;
1318         }
1319
1320         return 0;
1321 }
1322
1323 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1324                                     struct mv88e6xxx_vtu_stu_entry *entry)
1325 {
1326         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1327 }
1328
1329 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1330                                     struct mv88e6xxx_vtu_stu_entry *entry)
1331 {
1332         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1333 }
1334
1335 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1336 {
1337         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1338                                     vid & GLOBAL_VTU_VID_MASK);
1339 }
1340
1341 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1342                                   struct mv88e6xxx_vtu_stu_entry *entry)
1343 {
1344         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1345         int ret;
1346
1347         ret = _mv88e6xxx_vtu_wait(chip);
1348         if (ret < 0)
1349                 return ret;
1350
1351         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1352         if (ret < 0)
1353                 return ret;
1354
1355         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1356         if (ret < 0)
1357                 return ret;
1358
1359         next.vid = ret & GLOBAL_VTU_VID_MASK;
1360         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1361
1362         if (next.valid) {
1363                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1364                 if (ret < 0)
1365                         return ret;
1366
1367                 if (mv88e6xxx_has_fid_reg(chip)) {
1368                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1369                                                   GLOBAL_VTU_FID);
1370                         if (ret < 0)
1371                                 return ret;
1372
1373                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1374                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1375                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1376                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1377                          */
1378                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1379                                                   GLOBAL_VTU_OP);
1380                         if (ret < 0)
1381                                 return ret;
1382
1383                         next.fid = (ret & 0xf00) >> 4;
1384                         next.fid |= ret & 0xf;
1385                 }
1386
1387                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1388                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1389                                                   GLOBAL_VTU_SID);
1390                         if (ret < 0)
1391                                 return ret;
1392
1393                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1394                 }
1395         }
1396
1397         *entry = next;
1398         return 0;
1399 }
1400
1401 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1402                                     struct switchdev_obj_port_vlan *vlan,
1403                                     int (*cb)(struct switchdev_obj *obj))
1404 {
1405         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1406         struct mv88e6xxx_vtu_stu_entry next;
1407         u16 pvid;
1408         int err;
1409
1410         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1411                 return -EOPNOTSUPP;
1412
1413         mutex_lock(&chip->reg_lock);
1414
1415         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1416         if (err)
1417                 goto unlock;
1418
1419         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1420         if (err)
1421                 goto unlock;
1422
1423         do {
1424                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1425                 if (err)
1426                         break;
1427
1428                 if (!next.valid)
1429                         break;
1430
1431                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1432                         continue;
1433
1434                 /* reinit and dump this VLAN obj */
1435                 vlan->vid_begin = next.vid;
1436                 vlan->vid_end = next.vid;
1437                 vlan->flags = 0;
1438
1439                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1440                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1441
1442                 if (next.vid == pvid)
1443                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1444
1445                 err = cb(&vlan->obj);
1446                 if (err)
1447                         break;
1448         } while (next.vid < GLOBAL_VTU_VID_MASK);
1449
1450 unlock:
1451         mutex_unlock(&chip->reg_lock);
1452
1453         return err;
1454 }
1455
1456 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1457                                     struct mv88e6xxx_vtu_stu_entry *entry)
1458 {
1459         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1460         u16 reg = 0;
1461         int ret;
1462
1463         ret = _mv88e6xxx_vtu_wait(chip);
1464         if (ret < 0)
1465                 return ret;
1466
1467         if (!entry->valid)
1468                 goto loadpurge;
1469
1470         /* Write port member tags */
1471         ret = mv88e6xxx_vtu_data_write(chip, entry);
1472         if (ret < 0)
1473                 return ret;
1474
1475         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1476                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1477                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1478                                            reg);
1479                 if (ret < 0)
1480                         return ret;
1481         }
1482
1483         if (mv88e6xxx_has_fid_reg(chip)) {
1484                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1485                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1486                                            reg);
1487                 if (ret < 0)
1488                         return ret;
1489         } else if (mv88e6xxx_num_databases(chip) == 256) {
1490                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1491                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1492                  */
1493                 op |= (entry->fid & 0xf0) << 8;
1494                 op |= entry->fid & 0xf;
1495         }
1496
1497         reg = GLOBAL_VTU_VID_VALID;
1498 loadpurge:
1499         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1500         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1501         if (ret < 0)
1502                 return ret;
1503
1504         return _mv88e6xxx_vtu_cmd(chip, op);
1505 }
1506
1507 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1508                                   struct mv88e6xxx_vtu_stu_entry *entry)
1509 {
1510         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1511         int ret;
1512
1513         ret = _mv88e6xxx_vtu_wait(chip);
1514         if (ret < 0)
1515                 return ret;
1516
1517         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1518                                    sid & GLOBAL_VTU_SID_MASK);
1519         if (ret < 0)
1520                 return ret;
1521
1522         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1523         if (ret < 0)
1524                 return ret;
1525
1526         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1527         if (ret < 0)
1528                 return ret;
1529
1530         next.sid = ret & GLOBAL_VTU_SID_MASK;
1531
1532         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1533         if (ret < 0)
1534                 return ret;
1535
1536         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1537
1538         if (next.valid) {
1539                 ret = mv88e6xxx_stu_data_read(chip, &next);
1540                 if (ret < 0)
1541                         return ret;
1542         }
1543
1544         *entry = next;
1545         return 0;
1546 }
1547
1548 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1549                                     struct mv88e6xxx_vtu_stu_entry *entry)
1550 {
1551         u16 reg = 0;
1552         int ret;
1553
1554         ret = _mv88e6xxx_vtu_wait(chip);
1555         if (ret < 0)
1556                 return ret;
1557
1558         if (!entry->valid)
1559                 goto loadpurge;
1560
1561         /* Write port states */
1562         ret = mv88e6xxx_stu_data_write(chip, entry);
1563         if (ret < 0)
1564                 return ret;
1565
1566         reg = GLOBAL_VTU_VID_VALID;
1567 loadpurge:
1568         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1569         if (ret < 0)
1570                 return ret;
1571
1572         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1573         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1574         if (ret < 0)
1575                 return ret;
1576
1577         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1578 }
1579
1580 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1581                                u16 *new, u16 *old)
1582 {
1583         struct dsa_switch *ds = chip->ds;
1584         u16 upper_mask;
1585         u16 fid;
1586         int ret;
1587
1588         if (mv88e6xxx_num_databases(chip) == 4096)
1589                 upper_mask = 0xff;
1590         else if (mv88e6xxx_num_databases(chip) == 256)
1591                 upper_mask = 0xf;
1592         else
1593                 return -EOPNOTSUPP;
1594
1595         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1596         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1597         if (ret < 0)
1598                 return ret;
1599
1600         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1601
1602         if (new) {
1603                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1604                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1605
1606                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1607                                            ret);
1608                 if (ret < 0)
1609                         return ret;
1610         }
1611
1612         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1613         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1614         if (ret < 0)
1615                 return ret;
1616
1617         fid |= (ret & upper_mask) << 4;
1618
1619         if (new) {
1620                 ret &= ~upper_mask;
1621                 ret |= (*new >> 4) & upper_mask;
1622
1623                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1624                                            ret);
1625                 if (ret < 0)
1626                         return ret;
1627
1628                 netdev_dbg(ds->ports[port].netdev,
1629                            "FID %d (was %d)\n", *new, fid);
1630         }
1631
1632         if (old)
1633                 *old = fid;
1634
1635         return 0;
1636 }
1637
1638 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1639                                    int port, u16 *fid)
1640 {
1641         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1642 }
1643
1644 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1645                                    int port, u16 fid)
1646 {
1647         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1648 }
1649
1650 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1651 {
1652         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1653         struct mv88e6xxx_vtu_stu_entry vlan;
1654         int i, err;
1655
1656         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1657
1658         /* Set every FID bit used by the (un)bridged ports */
1659         for (i = 0; i < chip->info->num_ports; ++i) {
1660                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1661                 if (err)
1662                         return err;
1663
1664                 set_bit(*fid, fid_bitmap);
1665         }
1666
1667         /* Set every FID bit used by the VLAN entries */
1668         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1669         if (err)
1670                 return err;
1671
1672         do {
1673                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1674                 if (err)
1675                         return err;
1676
1677                 if (!vlan.valid)
1678                         break;
1679
1680                 set_bit(vlan.fid, fid_bitmap);
1681         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1682
1683         /* The reset value 0x000 is used to indicate that multiple address
1684          * databases are not needed. Return the next positive available.
1685          */
1686         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1687         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1688                 return -ENOSPC;
1689
1690         /* Clear the database */
1691         return _mv88e6xxx_atu_flush(chip, *fid, true);
1692 }
1693
1694 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1695                               struct mv88e6xxx_vtu_stu_entry *entry)
1696 {
1697         struct dsa_switch *ds = chip->ds;
1698         struct mv88e6xxx_vtu_stu_entry vlan = {
1699                 .valid = true,
1700                 .vid = vid,
1701         };
1702         int i, err;
1703
1704         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1705         if (err)
1706                 return err;
1707
1708         /* exclude all ports except the CPU and DSA ports */
1709         for (i = 0; i < chip->info->num_ports; ++i)
1710                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1711                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1712                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1713
1714         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1715             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1716                 struct mv88e6xxx_vtu_stu_entry vstp;
1717
1718                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1719                  * implemented, only one STU entry is needed to cover all VTU
1720                  * entries. Thus, validate the SID 0.
1721                  */
1722                 vlan.sid = 0;
1723                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1724                 if (err)
1725                         return err;
1726
1727                 if (vstp.sid != vlan.sid || !vstp.valid) {
1728                         memset(&vstp, 0, sizeof(vstp));
1729                         vstp.valid = true;
1730                         vstp.sid = vlan.sid;
1731
1732                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1733                         if (err)
1734                                 return err;
1735                 }
1736         }
1737
1738         *entry = vlan;
1739         return 0;
1740 }
1741
1742 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1743                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1744 {
1745         int err;
1746
1747         if (!vid)
1748                 return -EINVAL;
1749
1750         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1751         if (err)
1752                 return err;
1753
1754         err = _mv88e6xxx_vtu_getnext(chip, entry);
1755         if (err)
1756                 return err;
1757
1758         if (entry->vid != vid || !entry->valid) {
1759                 if (!creat)
1760                         return -EOPNOTSUPP;
1761                 /* -ENOENT would've been more appropriate, but switchdev expects
1762                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1763                  */
1764
1765                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1766         }
1767
1768         return err;
1769 }
1770
1771 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1772                                         u16 vid_begin, u16 vid_end)
1773 {
1774         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1775         struct mv88e6xxx_vtu_stu_entry vlan;
1776         int i, err;
1777
1778         if (!vid_begin)
1779                 return -EOPNOTSUPP;
1780
1781         mutex_lock(&chip->reg_lock);
1782
1783         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1784         if (err)
1785                 goto unlock;
1786
1787         do {
1788                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1789                 if (err)
1790                         goto unlock;
1791
1792                 if (!vlan.valid)
1793                         break;
1794
1795                 if (vlan.vid > vid_end)
1796                         break;
1797
1798                 for (i = 0; i < chip->info->num_ports; ++i) {
1799                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1800                                 continue;
1801
1802                         if (vlan.data[i] ==
1803                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1804                                 continue;
1805
1806                         if (chip->ports[i].bridge_dev ==
1807                             chip->ports[port].bridge_dev)
1808                                 break; /* same bridge, check next VLAN */
1809
1810                         netdev_warn(ds->ports[port].netdev,
1811                                     "hardware VLAN %d already used by %s\n",
1812                                     vlan.vid,
1813                                     netdev_name(chip->ports[i].bridge_dev));
1814                         err = -EOPNOTSUPP;
1815                         goto unlock;
1816                 }
1817         } while (vlan.vid < vid_end);
1818
1819 unlock:
1820         mutex_unlock(&chip->reg_lock);
1821
1822         return err;
1823 }
1824
1825 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1826         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1827         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1828         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1829         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1830 };
1831
1832 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1833                                          bool vlan_filtering)
1834 {
1835         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1836         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1837                 PORT_CONTROL_2_8021Q_DISABLED;
1838         int ret;
1839
1840         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1841                 return -EOPNOTSUPP;
1842
1843         mutex_lock(&chip->reg_lock);
1844
1845         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1846         if (ret < 0)
1847                 goto unlock;
1848
1849         old = ret & PORT_CONTROL_2_8021Q_MASK;
1850
1851         if (new != old) {
1852                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1853                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1854
1855                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1856                                            ret);
1857                 if (ret < 0)
1858                         goto unlock;
1859
1860                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1861                            mv88e6xxx_port_8021q_mode_names[new],
1862                            mv88e6xxx_port_8021q_mode_names[old]);
1863         }
1864
1865         ret = 0;
1866 unlock:
1867         mutex_unlock(&chip->reg_lock);
1868
1869         return ret;
1870 }
1871
1872 static int
1873 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1874                             const struct switchdev_obj_port_vlan *vlan,
1875                             struct switchdev_trans *trans)
1876 {
1877         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1878         int err;
1879
1880         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1881                 return -EOPNOTSUPP;
1882
1883         /* If the requested port doesn't belong to the same bridge as the VLAN
1884          * members, do not support it (yet) and fallback to software VLAN.
1885          */
1886         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1887                                            vlan->vid_end);
1888         if (err)
1889                 return err;
1890
1891         /* We don't need any dynamic resource from the kernel (yet),
1892          * so skip the prepare phase.
1893          */
1894         return 0;
1895 }
1896
1897 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1898                                     u16 vid, bool untagged)
1899 {
1900         struct mv88e6xxx_vtu_stu_entry vlan;
1901         int err;
1902
1903         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1904         if (err)
1905                 return err;
1906
1907         vlan.data[port] = untagged ?
1908                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1909                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1910
1911         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1912 }
1913
1914 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1915                                     const struct switchdev_obj_port_vlan *vlan,
1916                                     struct switchdev_trans *trans)
1917 {
1918         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1919         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1920         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1921         u16 vid;
1922
1923         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1924                 return;
1925
1926         mutex_lock(&chip->reg_lock);
1927
1928         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1929                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1930                         netdev_err(ds->ports[port].netdev,
1931                                    "failed to add VLAN %d%c\n",
1932                                    vid, untagged ? 'u' : 't');
1933
1934         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1935                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1936                            vlan->vid_end);
1937
1938         mutex_unlock(&chip->reg_lock);
1939 }
1940
1941 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1942                                     int port, u16 vid)
1943 {
1944         struct dsa_switch *ds = chip->ds;
1945         struct mv88e6xxx_vtu_stu_entry vlan;
1946         int i, err;
1947
1948         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1949         if (err)
1950                 return err;
1951
1952         /* Tell switchdev if this VLAN is handled in software */
1953         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1954                 return -EOPNOTSUPP;
1955
1956         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1957
1958         /* keep the VLAN unless all ports are excluded */
1959         vlan.valid = false;
1960         for (i = 0; i < chip->info->num_ports; ++i) {
1961                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1962                         continue;
1963
1964                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1965                         vlan.valid = true;
1966                         break;
1967                 }
1968         }
1969
1970         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1971         if (err)
1972                 return err;
1973
1974         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1975 }
1976
1977 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1978                                    const struct switchdev_obj_port_vlan *vlan)
1979 {
1980         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1981         u16 pvid, vid;
1982         int err = 0;
1983
1984         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1985                 return -EOPNOTSUPP;
1986
1987         mutex_lock(&chip->reg_lock);
1988
1989         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1990         if (err)
1991                 goto unlock;
1992
1993         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1994                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1995                 if (err)
1996                         goto unlock;
1997
1998                 if (vid == pvid) {
1999                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2000                         if (err)
2001                                 goto unlock;
2002                 }
2003         }
2004
2005 unlock:
2006         mutex_unlock(&chip->reg_lock);
2007
2008         return err;
2009 }
2010
2011 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2012                                     const unsigned char *addr)
2013 {
2014         int i, ret;
2015
2016         for (i = 0; i < 3; i++) {
2017                 ret = _mv88e6xxx_reg_write(
2018                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2019                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2020                 if (ret < 0)
2021                         return ret;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2028                                    unsigned char *addr)
2029 {
2030         int i, ret;
2031
2032         for (i = 0; i < 3; i++) {
2033                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2034                                           GLOBAL_ATU_MAC_01 + i);
2035                 if (ret < 0)
2036                         return ret;
2037                 addr[i * 2] = ret >> 8;
2038                 addr[i * 2 + 1] = ret & 0xff;
2039         }
2040
2041         return 0;
2042 }
2043
2044 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2045                                struct mv88e6xxx_atu_entry *entry)
2046 {
2047         int ret;
2048
2049         ret = _mv88e6xxx_atu_wait(chip);
2050         if (ret < 0)
2051                 return ret;
2052
2053         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2054         if (ret < 0)
2055                 return ret;
2056
2057         ret = _mv88e6xxx_atu_data_write(chip, entry);
2058         if (ret < 0)
2059                 return ret;
2060
2061         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2062 }
2063
2064 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2065                                     const unsigned char *addr, u16 vid,
2066                                     u8 state)
2067 {
2068         struct mv88e6xxx_atu_entry entry = { 0 };
2069         struct mv88e6xxx_vtu_stu_entry vlan;
2070         int err;
2071
2072         /* Null VLAN ID corresponds to the port private database */
2073         if (vid == 0)
2074                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2075         else
2076                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2077         if (err)
2078                 return err;
2079
2080         entry.fid = vlan.fid;
2081         entry.state = state;
2082         ether_addr_copy(entry.mac, addr);
2083         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2084                 entry.trunk = false;
2085                 entry.portv_trunkid = BIT(port);
2086         }
2087
2088         return _mv88e6xxx_atu_load(chip, &entry);
2089 }
2090
2091 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2092                                       const struct switchdev_obj_port_fdb *fdb,
2093                                       struct switchdev_trans *trans)
2094 {
2095         /* We don't need any dynamic resource from the kernel (yet),
2096          * so skip the prepare phase.
2097          */
2098         return 0;
2099 }
2100
2101 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2102                                    const struct switchdev_obj_port_fdb *fdb,
2103                                    struct switchdev_trans *trans)
2104 {
2105         int state = is_multicast_ether_addr(fdb->addr) ?
2106                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2107                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2108         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2109
2110         mutex_lock(&chip->reg_lock);
2111         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2112                 netdev_err(ds->ports[port].netdev,
2113                            "failed to load MAC address\n");
2114         mutex_unlock(&chip->reg_lock);
2115 }
2116
2117 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2118                                   const struct switchdev_obj_port_fdb *fdb)
2119 {
2120         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2121         int ret;
2122
2123         mutex_lock(&chip->reg_lock);
2124         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2125                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2126         mutex_unlock(&chip->reg_lock);
2127
2128         return ret;
2129 }
2130
2131 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2132                                   struct mv88e6xxx_atu_entry *entry)
2133 {
2134         struct mv88e6xxx_atu_entry next = { 0 };
2135         int ret;
2136
2137         next.fid = fid;
2138
2139         ret = _mv88e6xxx_atu_wait(chip);
2140         if (ret < 0)
2141                 return ret;
2142
2143         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2144         if (ret < 0)
2145                 return ret;
2146
2147         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2148         if (ret < 0)
2149                 return ret;
2150
2151         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2152         if (ret < 0)
2153                 return ret;
2154
2155         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2156         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2157                 unsigned int mask, shift;
2158
2159                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2160                         next.trunk = true;
2161                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2162                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2163                 } else {
2164                         next.trunk = false;
2165                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2166                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2167                 }
2168
2169                 next.portv_trunkid = (ret & mask) >> shift;
2170         }
2171
2172         *entry = next;
2173         return 0;
2174 }
2175
2176 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2177                                         u16 fid, u16 vid, int port,
2178                                         struct switchdev_obj_port_fdb *fdb,
2179                                         int (*cb)(struct switchdev_obj *obj))
2180 {
2181         struct mv88e6xxx_atu_entry addr = {
2182                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2183         };
2184         int err;
2185
2186         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2187         if (err)
2188                 return err;
2189
2190         do {
2191                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2192                 if (err)
2193                         break;
2194
2195                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2196                         break;
2197
2198                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2199                         bool is_static = addr.state ==
2200                                 (is_multicast_ether_addr(addr.mac) ?
2201                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2202                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2203
2204                         fdb->vid = vid;
2205                         ether_addr_copy(fdb->addr, addr.mac);
2206                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2207
2208                         err = cb(&fdb->obj);
2209                         if (err)
2210                                 break;
2211                 }
2212         } while (!is_broadcast_ether_addr(addr.mac));
2213
2214         return err;
2215 }
2216
2217 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2218                                    struct switchdev_obj_port_fdb *fdb,
2219                                    int (*cb)(struct switchdev_obj *obj))
2220 {
2221         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2222         struct mv88e6xxx_vtu_stu_entry vlan = {
2223                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2224         };
2225         u16 fid;
2226         int err;
2227
2228         mutex_lock(&chip->reg_lock);
2229
2230         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2231         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2232         if (err)
2233                 goto unlock;
2234
2235         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2236         if (err)
2237                 goto unlock;
2238
2239         /* Dump VLANs' Filtering Information Databases */
2240         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2241         if (err)
2242                 goto unlock;
2243
2244         do {
2245                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2246                 if (err)
2247                         break;
2248
2249                 if (!vlan.valid)
2250                         break;
2251
2252                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2253                                                    port, fdb, cb);
2254                 if (err)
2255                         break;
2256         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2257
2258 unlock:
2259         mutex_unlock(&chip->reg_lock);
2260
2261         return err;
2262 }
2263
2264 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2265                                       struct net_device *bridge)
2266 {
2267         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2268         int i, err = 0;
2269
2270         mutex_lock(&chip->reg_lock);
2271
2272         /* Assign the bridge and remap each port's VLANTable */
2273         chip->ports[port].bridge_dev = bridge;
2274
2275         for (i = 0; i < chip->info->num_ports; ++i) {
2276                 if (chip->ports[i].bridge_dev == bridge) {
2277                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2278                         if (err)
2279                                 break;
2280                 }
2281         }
2282
2283         mutex_unlock(&chip->reg_lock);
2284
2285         return err;
2286 }
2287
2288 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2289 {
2290         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2291         struct net_device *bridge = chip->ports[port].bridge_dev;
2292         int i;
2293
2294         mutex_lock(&chip->reg_lock);
2295
2296         /* Unassign the bridge and remap each port's VLANTable */
2297         chip->ports[port].bridge_dev = NULL;
2298
2299         for (i = 0; i < chip->info->num_ports; ++i)
2300                 if (i == port || chip->ports[i].bridge_dev == bridge)
2301                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2302                                 netdev_warn(ds->ports[i].netdev,
2303                                             "failed to remap\n");
2304
2305         mutex_unlock(&chip->reg_lock);
2306 }
2307
2308 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2309                                       int port, int page, int reg, int val)
2310 {
2311         int ret;
2312
2313         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2314         if (ret < 0)
2315                 goto restore_page_0;
2316
2317         ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2318 restore_page_0:
2319         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2320
2321         return ret;
2322 }
2323
2324 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2325                                      int port, int page, int reg)
2326 {
2327         int ret;
2328
2329         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2330         if (ret < 0)
2331                 goto restore_page_0;
2332
2333         ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2334 restore_page_0:
2335         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2336
2337         return ret;
2338 }
2339
2340 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2341 {
2342         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2343         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2344         struct gpio_desc *gpiod = chip->reset;
2345         unsigned long timeout;
2346         int ret;
2347         int i;
2348
2349         /* Set all ports to the disabled state. */
2350         for (i = 0; i < chip->info->num_ports; i++) {
2351                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2352                 if (ret < 0)
2353                         return ret;
2354
2355                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2356                                            ret & 0xfffc);
2357                 if (ret)
2358                         return ret;
2359         }
2360
2361         /* Wait for transmit queues to drain. */
2362         usleep_range(2000, 4000);
2363
2364         /* If there is a gpio connected to the reset pin, toggle it */
2365         if (gpiod) {
2366                 gpiod_set_value_cansleep(gpiod, 1);
2367                 usleep_range(10000, 20000);
2368                 gpiod_set_value_cansleep(gpiod, 0);
2369                 usleep_range(10000, 20000);
2370         }
2371
2372         /* Reset the switch. Keep the PPU active if requested. The PPU
2373          * needs to be active to support indirect phy register access
2374          * through global registers 0x18 and 0x19.
2375          */
2376         if (ppu_active)
2377                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2378         else
2379                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2380         if (ret)
2381                 return ret;
2382
2383         /* Wait up to one second for reset to complete. */
2384         timeout = jiffies + 1 * HZ;
2385         while (time_before(jiffies, timeout)) {
2386                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2387                 if (ret < 0)
2388                         return ret;
2389
2390                 if ((ret & is_reset) == is_reset)
2391                         break;
2392                 usleep_range(1000, 2000);
2393         }
2394         if (time_after(jiffies, timeout))
2395                 ret = -ETIMEDOUT;
2396         else
2397                 ret = 0;
2398
2399         return ret;
2400 }
2401
2402 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2403 {
2404         int ret;
2405
2406         ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2407                                         PAGE_FIBER_SERDES, MII_BMCR);
2408         if (ret < 0)
2409                 return ret;
2410
2411         if (ret & BMCR_PDOWN) {
2412                 ret &= ~BMCR_PDOWN;
2413                 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2414                                                  PAGE_FIBER_SERDES, MII_BMCR,
2415                                                  ret);
2416         }
2417
2418         return ret;
2419 }
2420
2421 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2422                                int reg, u16 *val)
2423 {
2424         int addr = chip->info->port_base_addr + port;
2425
2426         if (port >= chip->info->num_ports)
2427                 return -EINVAL;
2428
2429         return mv88e6xxx_read(chip, addr, reg, val);
2430 }
2431
2432 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2433 {
2434         struct dsa_switch *ds = chip->ds;
2435         int ret;
2436         u16 reg;
2437
2438         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2439             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2440             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2441             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2442                 /* MAC Forcing register: don't force link, speed,
2443                  * duplex or flow control state to any particular
2444                  * values on physical ports, but force the CPU port
2445                  * and all DSA ports to their maximum bandwidth and
2446                  * full duplex.
2447                  */
2448                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2449                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2450                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2451                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2452                                 PORT_PCS_CTRL_LINK_UP |
2453                                 PORT_PCS_CTRL_DUPLEX_FULL |
2454                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2455                         if (mv88e6xxx_6065_family(chip))
2456                                 reg |= PORT_PCS_CTRL_100;
2457                         else
2458                                 reg |= PORT_PCS_CTRL_1000;
2459                 } else {
2460                         reg |= PORT_PCS_CTRL_UNFORCED;
2461                 }
2462
2463                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2464                                            PORT_PCS_CTRL, reg);
2465                 if (ret)
2466                         return ret;
2467         }
2468
2469         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2470          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2471          * tunneling, determine priority by looking at 802.1p and IP
2472          * priority fields (IP prio has precedence), and set STP state
2473          * to Forwarding.
2474          *
2475          * If this is the CPU link, use DSA or EDSA tagging depending
2476          * on which tagging mode was configured.
2477          *
2478          * If this is a link to another switch, use DSA tagging mode.
2479          *
2480          * If this is the upstream port for this switch, enable
2481          * forwarding of unknown unicasts and multicasts.
2482          */
2483         reg = 0;
2484         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2485             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2486             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2487             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2488                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2489                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2490                 PORT_CONTROL_STATE_FORWARDING;
2491         if (dsa_is_cpu_port(ds, port)) {
2492                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2493                         reg |= PORT_CONTROL_DSA_TAG;
2494                 if (mv88e6xxx_6352_family(chip) ||
2495                     mv88e6xxx_6351_family(chip) ||
2496                     mv88e6xxx_6165_family(chip) ||
2497                     mv88e6xxx_6097_family(chip) ||
2498                     mv88e6xxx_6320_family(chip)) {
2499                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2500                                 PORT_CONTROL_FORWARD_UNKNOWN |
2501                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2502                 }
2503
2504                 if (mv88e6xxx_6352_family(chip) ||
2505                     mv88e6xxx_6351_family(chip) ||
2506                     mv88e6xxx_6165_family(chip) ||
2507                     mv88e6xxx_6097_family(chip) ||
2508                     mv88e6xxx_6095_family(chip) ||
2509                     mv88e6xxx_6065_family(chip) ||
2510                     mv88e6xxx_6185_family(chip) ||
2511                     mv88e6xxx_6320_family(chip)) {
2512                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2513                 }
2514         }
2515         if (dsa_is_dsa_port(ds, port)) {
2516                 if (mv88e6xxx_6095_family(chip) ||
2517                     mv88e6xxx_6185_family(chip))
2518                         reg |= PORT_CONTROL_DSA_TAG;
2519                 if (mv88e6xxx_6352_family(chip) ||
2520                     mv88e6xxx_6351_family(chip) ||
2521                     mv88e6xxx_6165_family(chip) ||
2522                     mv88e6xxx_6097_family(chip) ||
2523                     mv88e6xxx_6320_family(chip)) {
2524                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2525                 }
2526
2527                 if (port == dsa_upstream_port(ds))
2528                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2529                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2530         }
2531         if (reg) {
2532                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2533                                            PORT_CONTROL, reg);
2534                 if (ret)
2535                         return ret;
2536         }
2537
2538         /* If this port is connected to a SerDes, make sure the SerDes is not
2539          * powered down.
2540          */
2541         if (mv88e6xxx_6352_family(chip)) {
2542                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2543                 if (ret < 0)
2544                         return ret;
2545                 ret &= PORT_STATUS_CMODE_MASK;
2546                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2547                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2548                     (ret == PORT_STATUS_CMODE_SGMII)) {
2549                         ret = mv88e6xxx_power_on_serdes(chip);
2550                         if (ret < 0)
2551                                 return ret;
2552                 }
2553         }
2554
2555         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2556          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2557          * untagged frames on this port, do a destination address lookup on all
2558          * received packets as usual, disable ARP mirroring and don't send a
2559          * copy of all transmitted/received frames on this port to the CPU.
2560          */
2561         reg = 0;
2562         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2563             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2564             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2565             mv88e6xxx_6185_family(chip))
2566                 reg = PORT_CONTROL_2_MAP_DA;
2567
2568         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2569             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2570                 reg |= PORT_CONTROL_2_JUMBO_10240;
2571
2572         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2573                 /* Set the upstream port this port should use */
2574                 reg |= dsa_upstream_port(ds);
2575                 /* enable forwarding of unknown multicast addresses to
2576                  * the upstream port
2577                  */
2578                 if (port == dsa_upstream_port(ds))
2579                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2580         }
2581
2582         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2583
2584         if (reg) {
2585                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2586                                            PORT_CONTROL_2, reg);
2587                 if (ret)
2588                         return ret;
2589         }
2590
2591         /* Port Association Vector: when learning source addresses
2592          * of packets, add the address to the address database using
2593          * a port bitmap that has only the bit for this port set and
2594          * the other bits clear.
2595          */
2596         reg = 1 << port;
2597         /* Disable learning for CPU port */
2598         if (dsa_is_cpu_port(ds, port))
2599                 reg = 0;
2600
2601         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2602                                    reg);
2603         if (ret)
2604                 return ret;
2605
2606         /* Egress rate control 2: disable egress rate control. */
2607         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2608                                    0x0000);
2609         if (ret)
2610                 return ret;
2611
2612         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2613             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2614             mv88e6xxx_6320_family(chip)) {
2615                 /* Do not limit the period of time that this port can
2616                  * be paused for by the remote end or the period of
2617                  * time that this port can pause the remote end.
2618                  */
2619                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2620                                            PORT_PAUSE_CTRL, 0x0000);
2621                 if (ret)
2622                         return ret;
2623
2624                 /* Port ATU control: disable limiting the number of
2625                  * address database entries that this port is allowed
2626                  * to use.
2627                  */
2628                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2629                                            PORT_ATU_CONTROL, 0x0000);
2630                 /* Priority Override: disable DA, SA and VTU priority
2631                  * override.
2632                  */
2633                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2634                                            PORT_PRI_OVERRIDE, 0x0000);
2635                 if (ret)
2636                         return ret;
2637
2638                 /* Port Ethertype: use the Ethertype DSA Ethertype
2639                  * value.
2640                  */
2641                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2642                                            PORT_ETH_TYPE, ETH_P_EDSA);
2643                 if (ret)
2644                         return ret;
2645                 /* Tag Remap: use an identity 802.1p prio -> switch
2646                  * prio mapping.
2647                  */
2648                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2649                                            PORT_TAG_REGMAP_0123, 0x3210);
2650                 if (ret)
2651                         return ret;
2652
2653                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2654                  * prio mapping.
2655                  */
2656                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2657                                            PORT_TAG_REGMAP_4567, 0x7654);
2658                 if (ret)
2659                         return ret;
2660         }
2661
2662         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2663             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2664             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2665             mv88e6xxx_6320_family(chip)) {
2666                 /* Rate Control: disable ingress rate limiting. */
2667                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2668                                            PORT_RATE_CONTROL, 0x0001);
2669                 if (ret)
2670                         return ret;
2671         }
2672
2673         /* Port Control 1: disable trunking, disable sending
2674          * learning messages to this port.
2675          */
2676         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2677                                    0x0000);
2678         if (ret)
2679                 return ret;
2680
2681         /* Port based VLAN map: give each port the same default address
2682          * database, and allow bidirectional communication between the
2683          * CPU and DSA port(s), and the other ports.
2684          */
2685         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2686         if (ret)
2687                 return ret;
2688
2689         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2690         if (ret)
2691                 return ret;
2692
2693         /* Default VLAN ID and priority: don't set a default VLAN
2694          * ID, and set the default packet priority to zero.
2695          */
2696         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2697                                    0x0000);
2698         if (ret)
2699                 return ret;
2700
2701         return 0;
2702 }
2703
2704 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2705 {
2706         int err;
2707
2708         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2709                               (addr[0] << 8) | addr[1]);
2710         if (err)
2711                 return err;
2712
2713         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2714                               (addr[2] << 8) | addr[3]);
2715         if (err)
2716                 return err;
2717
2718         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2719                                (addr[4] << 8) | addr[5]);
2720 }
2721
2722 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2723                                      unsigned int msecs)
2724 {
2725         const unsigned int coeff = chip->info->age_time_coeff;
2726         const unsigned int min = 0x01 * coeff;
2727         const unsigned int max = 0xff * coeff;
2728         u8 age_time;
2729         u16 val;
2730         int err;
2731
2732         if (msecs < min || msecs > max)
2733                 return -ERANGE;
2734
2735         /* Round to nearest multiple of coeff */
2736         age_time = (msecs + coeff / 2) / coeff;
2737
2738         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2739         if (err)
2740                 return err;
2741
2742         /* AgeTime is 11:4 bits */
2743         val &= ~0xff0;
2744         val |= age_time << 4;
2745
2746         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2747 }
2748
2749 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2750                                      unsigned int ageing_time)
2751 {
2752         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2753         int err;
2754
2755         mutex_lock(&chip->reg_lock);
2756         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2757         mutex_unlock(&chip->reg_lock);
2758
2759         return err;
2760 }
2761
2762 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2763 {
2764         struct dsa_switch *ds = chip->ds;
2765         u32 upstream_port = dsa_upstream_port(ds);
2766         u16 reg;
2767         int err;
2768
2769         /* Enable the PHY Polling Unit if present, don't discard any packets,
2770          * and mask all interrupt sources.
2771          */
2772         reg = 0;
2773         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2774             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2775                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2776
2777         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2778         if (err)
2779                 return err;
2780
2781         /* Configure the upstream port, and configure it as the port to which
2782          * ingress and egress and ARP monitor frames are to be sent.
2783          */
2784         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2785                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2786                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2787         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2788                                    reg);
2789         if (err)
2790                 return err;
2791
2792         /* Disable remote management, and set the switch's DSA device number. */
2793         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2794                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2795                                    (ds->index & 0x1f));
2796         if (err)
2797                 return err;
2798
2799         /* Clear all the VTU and STU entries */
2800         err = _mv88e6xxx_vtu_stu_flush(chip);
2801         if (err < 0)
2802                 return err;
2803
2804         /* Set the default address aging time to 5 minutes, and
2805          * enable address learn messages to be sent to all message
2806          * ports.
2807          */
2808         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2809                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2810         if (err)
2811                 return err;
2812
2813         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2814         if (err)
2815                 return err;
2816
2817         /* Clear all ATU entries */
2818         err = _mv88e6xxx_atu_flush(chip, 0, true);
2819         if (err)
2820                 return err;
2821
2822         /* Configure the IP ToS mapping registers. */
2823         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2824         if (err)
2825                 return err;
2826         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2827         if (err)
2828                 return err;
2829         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2830         if (err)
2831                 return err;
2832         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2833         if (err)
2834                 return err;
2835         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2836         if (err)
2837                 return err;
2838         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2839         if (err)
2840                 return err;
2841         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2842         if (err)
2843                 return err;
2844         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2845         if (err)
2846                 return err;
2847
2848         /* Configure the IEEE 802.1p priority mapping register. */
2849         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2850         if (err)
2851                 return err;
2852
2853         /* Clear the statistics counters for all ports */
2854         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2855                                    GLOBAL_STATS_OP_FLUSH_ALL);
2856         if (err)
2857                 return err;
2858
2859         /* Wait for the flush to complete. */
2860         err = _mv88e6xxx_stats_wait(chip);
2861         if (err)
2862                 return err;
2863
2864         return 0;
2865 }
2866
2867 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2868                                              int target, int port)
2869 {
2870         u16 val = (target << 8) | (port & 0xf);
2871
2872         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2873 }
2874
2875 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2876 {
2877         int target, port;
2878         int err;
2879
2880         /* Initialize the routing port to the 32 possible target devices */
2881         for (target = 0; target < 32; ++target) {
2882                 port = 0xf;
2883
2884                 if (target < DSA_MAX_SWITCHES) {
2885                         port = chip->ds->rtable[target];
2886                         if (port == DSA_RTABLE_NONE)
2887                                 port = 0xf;
2888                 }
2889
2890                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2891                 if (err)
2892                         break;
2893         }
2894
2895         return err;
2896 }
2897
2898 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2899                                          bool hask, u16 mask)
2900 {
2901         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2902         u16 val = (num << 12) | (mask & port_mask);
2903
2904         if (hask)
2905                 val |= GLOBAL2_TRUNK_MASK_HASK;
2906
2907         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2908 }
2909
2910 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2911                                             u16 map)
2912 {
2913         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2914         u16 val = (id << 11) | (map & port_mask);
2915
2916         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2917 }
2918
2919 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2920 {
2921         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2922         int i, err;
2923
2924         /* Clear all eight possible Trunk Mask vectors */
2925         for (i = 0; i < 8; ++i) {
2926                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2927                 if (err)
2928                         return err;
2929         }
2930
2931         /* Clear all sixteen possible Trunk ID routing vectors */
2932         for (i = 0; i < 16; ++i) {
2933                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2934                 if (err)
2935                         return err;
2936         }
2937
2938         return 0;
2939 }
2940
2941 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2942 {
2943         int port, err;
2944
2945         /* Init all Ingress Rate Limit resources of all ports */
2946         for (port = 0; port < chip->info->num_ports; ++port) {
2947                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2948                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2949                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2950                                       (port << 8));
2951                 if (err)
2952                         break;
2953
2954                 /* Wait for the operation to complete */
2955                 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2956                                      GLOBAL2_IRL_CMD_BUSY);
2957                 if (err)
2958                         break;
2959         }
2960
2961         return err;
2962 }
2963
2964 /* Indirect write to the Switch MAC/WoL/WoF register */
2965 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2966                                          unsigned int pointer, u8 data)
2967 {
2968         u16 val = (pointer << 8) | data;
2969
2970         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2971 }
2972
2973 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2974 {
2975         int i, err;
2976
2977         for (i = 0; i < 6; i++) {
2978                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2979                 if (err)
2980                         break;
2981         }
2982
2983         return err;
2984 }
2985
2986 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2987                                   u8 data)
2988 {
2989         u16 val = (pointer << 8) | (data & 0x7);
2990
2991         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2992 }
2993
2994 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2995 {
2996         int i, err;
2997
2998         /* Clear all sixteen possible Priority Override entries */
2999         for (i = 0; i < 16; i++) {
3000                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3001                 if (err)
3002                         break;
3003         }
3004
3005         return err;
3006 }
3007
3008 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3009 {
3010         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3011                               GLOBAL2_EEPROM_CMD_BUSY |
3012                               GLOBAL2_EEPROM_CMD_RUNNING);
3013 }
3014
3015 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3016 {
3017         int err;
3018
3019         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3020         if (err)
3021                 return err;
3022
3023         return mv88e6xxx_g2_eeprom_wait(chip);
3024 }
3025
3026 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3027                                       u8 addr, u16 *data)
3028 {
3029         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3030         int err;
3031
3032         err = mv88e6xxx_g2_eeprom_wait(chip);
3033         if (err)
3034                 return err;
3035
3036         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3037         if (err)
3038                 return err;
3039
3040         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3041 }
3042
3043 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3044                                        u8 addr, u16 data)
3045 {
3046         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3047         int err;
3048
3049         err = mv88e6xxx_g2_eeprom_wait(chip);
3050         if (err)
3051                 return err;
3052
3053         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3054         if (err)
3055                 return err;
3056
3057         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3058 }
3059
3060 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3061 {
3062         u16 reg;
3063         int err;
3064
3065         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3066                 /* Consider the frames with reserved multicast destination
3067                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3068                  */
3069                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3070                                       0xffff);
3071                 if (err)
3072                         return err;
3073         }
3074
3075         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3076                 /* Consider the frames with reserved multicast destination
3077                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3078                  */
3079                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3080                                       0xffff);
3081                 if (err)
3082                         return err;
3083         }
3084
3085         /* Ignore removed tag data on doubly tagged packets, disable
3086          * flow control messages, force flow control priority to the
3087          * highest, and send all special multicast frames to the CPU
3088          * port at the highest priority.
3089          */
3090         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3091         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3092             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3093                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3094         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3095         if (err)
3096                 return err;
3097
3098         /* Program the DSA routing table. */
3099         err = mv88e6xxx_g2_set_device_mapping(chip);
3100         if (err)
3101                 return err;
3102
3103         /* Clear all trunk masks and mapping. */
3104         err = mv88e6xxx_g2_clear_trunk(chip);
3105         if (err)
3106                 return err;
3107
3108         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3109                 /* Disable ingress rate limiting by resetting all per port
3110                  * ingress rate limit resources to their initial state.
3111                  */
3112                 err = mv88e6xxx_g2_clear_irl(chip);
3113                         if (err)
3114                                 return err;
3115         }
3116
3117         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3118                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3119                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3120                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3121                 if (err)
3122                         return err;
3123         }
3124
3125         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3126                 /* Clear the priority override table. */
3127                 err = mv88e6xxx_g2_clear_pot(chip);
3128                 if (err)
3129                         return err;
3130         }
3131
3132         return 0;
3133 }
3134
3135 static int mv88e6xxx_setup(struct dsa_switch *ds)
3136 {
3137         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3138         int err;
3139         int i;
3140
3141         chip->ds = ds;
3142         ds->slave_mii_bus = chip->mdio_bus;
3143
3144         mutex_lock(&chip->reg_lock);
3145
3146         err = mv88e6xxx_switch_reset(chip);
3147         if (err)
3148                 goto unlock;
3149
3150         /* Setup Switch Port Registers */
3151         for (i = 0; i < chip->info->num_ports; i++) {
3152                 err = mv88e6xxx_setup_port(chip, i);
3153                 if (err)
3154                         goto unlock;
3155         }
3156
3157         /* Setup Switch Global 1 Registers */
3158         err = mv88e6xxx_g1_setup(chip);
3159         if (err)
3160                 goto unlock;
3161
3162         /* Setup Switch Global 2 Registers */
3163         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3164                 err = mv88e6xxx_g2_setup(chip);
3165                 if (err)
3166                         goto unlock;
3167         }
3168
3169 unlock:
3170         mutex_unlock(&chip->reg_lock);
3171
3172         return err;
3173 }
3174
3175 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3176 {
3177         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3178         int err;
3179
3180         mutex_lock(&chip->reg_lock);
3181
3182         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3183         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3184                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3185         else
3186                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3187
3188         mutex_unlock(&chip->reg_lock);
3189
3190         return err;
3191 }
3192
3193 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3194                                     int reg)
3195 {
3196         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3197         int ret;
3198
3199         mutex_lock(&chip->reg_lock);
3200         ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3201         mutex_unlock(&chip->reg_lock);
3202
3203         return ret;
3204 }
3205
3206 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3207                                      int reg, int val)
3208 {
3209         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3210         int ret;
3211
3212         mutex_lock(&chip->reg_lock);
3213         ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3214         mutex_unlock(&chip->reg_lock);
3215
3216         return ret;
3217 }
3218
3219 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3220 {
3221         if (port >= 0 && port < chip->info->num_ports)
3222                 return port;
3223         return -EINVAL;
3224 }
3225
3226 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3227 {
3228         struct mv88e6xxx_chip *chip = bus->priv;
3229         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3230         int ret;
3231
3232         if (addr < 0)
3233                 return 0xffff;
3234
3235         mutex_lock(&chip->reg_lock);
3236
3237         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3238                 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3239         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3240                 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3241         else
3242                 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3243
3244         mutex_unlock(&chip->reg_lock);
3245         return ret;
3246 }
3247
3248 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3249                                 u16 val)
3250 {
3251         struct mv88e6xxx_chip *chip = bus->priv;
3252         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3253         int ret;
3254
3255         if (addr < 0)
3256                 return 0xffff;
3257
3258         mutex_lock(&chip->reg_lock);
3259
3260         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3261                 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3262         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3263                 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3264         else
3265                 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3266
3267         mutex_unlock(&chip->reg_lock);
3268         return ret;
3269 }
3270
3271 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3272                                    struct device_node *np)
3273 {
3274         static int index;
3275         struct mii_bus *bus;
3276         int err;
3277
3278         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3279                 mv88e6xxx_ppu_state_init(chip);
3280
3281         if (np)
3282                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3283
3284         bus = devm_mdiobus_alloc(chip->dev);
3285         if (!bus)
3286                 return -ENOMEM;
3287
3288         bus->priv = (void *)chip;
3289         if (np) {
3290                 bus->name = np->full_name;
3291                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3292         } else {
3293                 bus->name = "mv88e6xxx SMI";
3294                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3295         }
3296
3297         bus->read = mv88e6xxx_mdio_read;
3298         bus->write = mv88e6xxx_mdio_write;
3299         bus->parent = chip->dev;
3300
3301         if (chip->mdio_np)
3302                 err = of_mdiobus_register(bus, chip->mdio_np);
3303         else
3304                 err = mdiobus_register(bus);
3305         if (err) {
3306                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3307                 goto out;
3308         }
3309         chip->mdio_bus = bus;
3310
3311         return 0;
3312
3313 out:
3314         if (chip->mdio_np)
3315                 of_node_put(chip->mdio_np);
3316
3317         return err;
3318 }
3319
3320 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3321
3322 {
3323         struct mii_bus *bus = chip->mdio_bus;
3324
3325         mdiobus_unregister(bus);
3326
3327         if (chip->mdio_np)
3328                 of_node_put(chip->mdio_np);
3329 }
3330
3331 #ifdef CONFIG_NET_DSA_HWMON
3332
3333 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3334 {
3335         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3336         int ret;
3337         int val;
3338
3339         *temp = 0;
3340
3341         mutex_lock(&chip->reg_lock);
3342
3343         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3344         if (ret < 0)
3345                 goto error;
3346
3347         /* Enable temperature sensor */
3348         ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3349         if (ret < 0)
3350                 goto error;
3351
3352         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3353         if (ret < 0)
3354                 goto error;
3355
3356         /* Wait for temperature to stabilize */
3357         usleep_range(10000, 12000);
3358
3359         val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3360         if (val < 0) {
3361                 ret = val;
3362                 goto error;
3363         }
3364
3365         /* Disable temperature sensor */
3366         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3367         if (ret < 0)
3368                 goto error;
3369
3370         *temp = ((val & 0x1f) - 5) * 5;
3371
3372 error:
3373         mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3374         mutex_unlock(&chip->reg_lock);
3375         return ret;
3376 }
3377
3378 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3379 {
3380         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3381         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3382         int ret;
3383
3384         *temp = 0;
3385
3386         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3387         if (ret < 0)
3388                 return ret;
3389
3390         *temp = (ret & 0xff) - 25;
3391
3392         return 0;
3393 }
3394
3395 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3396 {
3397         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3398
3399         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3400                 return -EOPNOTSUPP;
3401
3402         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3403                 return mv88e63xx_get_temp(ds, temp);
3404
3405         return mv88e61xx_get_temp(ds, temp);
3406 }
3407
3408 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3409 {
3410         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3411         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3412         int ret;
3413
3414         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3415                 return -EOPNOTSUPP;
3416
3417         *temp = 0;
3418
3419         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3420         if (ret < 0)
3421                 return ret;
3422
3423         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3424
3425         return 0;
3426 }
3427
3428 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3429 {
3430         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3431         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3432         int ret;
3433
3434         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3435                 return -EOPNOTSUPP;
3436
3437         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3438         if (ret < 0)
3439                 return ret;
3440         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3441         return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3442                                          (ret & 0xe0ff) | (temp << 8));
3443 }
3444
3445 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3446 {
3447         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3448         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3449         int ret;
3450
3451         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3452                 return -EOPNOTSUPP;
3453
3454         *alarm = false;
3455
3456         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3457         if (ret < 0)
3458                 return ret;
3459
3460         *alarm = !!(ret & 0x40);
3461
3462         return 0;
3463 }
3464 #endif /* CONFIG_NET_DSA_HWMON */
3465
3466 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3467 {
3468         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3469
3470         return chip->eeprom_len;
3471 }
3472
3473 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3474                                   struct ethtool_eeprom *eeprom, u8 *data)
3475 {
3476         unsigned int offset = eeprom->offset;
3477         unsigned int len = eeprom->len;
3478         u16 val;
3479         int err;
3480
3481         eeprom->len = 0;
3482
3483         if (offset & 1) {
3484                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3485                 if (err)
3486                         return err;
3487
3488                 *data++ = (val >> 8) & 0xff;
3489
3490                 offset++;
3491                 len--;
3492                 eeprom->len++;
3493         }
3494
3495         while (len >= 2) {
3496                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3497                 if (err)
3498                         return err;
3499
3500                 *data++ = val & 0xff;
3501                 *data++ = (val >> 8) & 0xff;
3502
3503                 offset += 2;
3504                 len -= 2;
3505                 eeprom->len += 2;
3506         }
3507
3508         if (len) {
3509                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3510                 if (err)
3511                         return err;
3512
3513                 *data++ = val & 0xff;
3514
3515                 offset++;
3516                 len--;
3517                 eeprom->len++;
3518         }
3519
3520         return 0;
3521 }
3522
3523 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3524                                 struct ethtool_eeprom *eeprom, u8 *data)
3525 {
3526         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3527         int err;
3528
3529         mutex_lock(&chip->reg_lock);
3530
3531         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3532                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3533         else
3534                 err = -EOPNOTSUPP;
3535
3536         mutex_unlock(&chip->reg_lock);
3537
3538         if (err)
3539                 return err;
3540
3541         eeprom->magic = 0xc3ec4951;
3542
3543         return 0;
3544 }
3545
3546 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3547                                   struct ethtool_eeprom *eeprom, u8 *data)
3548 {
3549         unsigned int offset = eeprom->offset;
3550         unsigned int len = eeprom->len;
3551         u16 val;
3552         int err;
3553
3554         /* Ensure the RO WriteEn bit is set */
3555         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3556         if (err)
3557                 return err;
3558
3559         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3560                 return -EROFS;
3561
3562         eeprom->len = 0;
3563
3564         if (offset & 1) {
3565                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3566                 if (err)
3567                         return err;
3568
3569                 val = (*data++ << 8) | (val & 0xff);
3570
3571                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3572                 if (err)
3573                         return err;
3574
3575                 offset++;
3576                 len--;
3577                 eeprom->len++;
3578         }
3579
3580         while (len >= 2) {
3581                 val = *data++;
3582                 val |= *data++ << 8;
3583
3584                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3585                 if (err)
3586                         return err;
3587
3588                 offset += 2;
3589                 len -= 2;
3590                 eeprom->len += 2;
3591         }
3592
3593         if (len) {
3594                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3595                 if (err)
3596                         return err;
3597
3598                 val = (val & 0xff00) | *data++;
3599
3600                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3601                 if (err)
3602                         return err;
3603
3604                 offset++;
3605                 len--;
3606                 eeprom->len++;
3607         }
3608
3609         return 0;
3610 }
3611
3612 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3613                                 struct ethtool_eeprom *eeprom, u8 *data)
3614 {
3615         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3616         int err;
3617
3618         if (eeprom->magic != 0xc3ec4951)
3619                 return -EINVAL;
3620
3621         mutex_lock(&chip->reg_lock);
3622
3623         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3624                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3625         else
3626                 err = -EOPNOTSUPP;
3627
3628         mutex_unlock(&chip->reg_lock);
3629
3630         return err;
3631 }
3632
3633 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3634         [MV88E6085] = {
3635                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3636                 .family = MV88E6XXX_FAMILY_6097,
3637                 .name = "Marvell 88E6085",
3638                 .num_databases = 4096,
3639                 .num_ports = 10,
3640                 .port_base_addr = 0x10,
3641                 .age_time_coeff = 15000,
3642                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3643         },
3644
3645         [MV88E6095] = {
3646                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3647                 .family = MV88E6XXX_FAMILY_6095,
3648                 .name = "Marvell 88E6095/88E6095F",
3649                 .num_databases = 256,
3650                 .num_ports = 11,
3651                 .port_base_addr = 0x10,
3652                 .age_time_coeff = 15000,
3653                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3654         },
3655
3656         [MV88E6123] = {
3657                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3658                 .family = MV88E6XXX_FAMILY_6165,
3659                 .name = "Marvell 88E6123",
3660                 .num_databases = 4096,
3661                 .num_ports = 3,
3662                 .port_base_addr = 0x10,
3663                 .age_time_coeff = 15000,
3664                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3665         },
3666
3667         [MV88E6131] = {
3668                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3669                 .family = MV88E6XXX_FAMILY_6185,
3670                 .name = "Marvell 88E6131",
3671                 .num_databases = 256,
3672                 .num_ports = 8,
3673                 .port_base_addr = 0x10,
3674                 .age_time_coeff = 15000,
3675                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3676         },
3677
3678         [MV88E6161] = {
3679                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3680                 .family = MV88E6XXX_FAMILY_6165,
3681                 .name = "Marvell 88E6161",
3682                 .num_databases = 4096,
3683                 .num_ports = 6,
3684                 .port_base_addr = 0x10,
3685                 .age_time_coeff = 15000,
3686                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3687         },
3688
3689         [MV88E6165] = {
3690                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3691                 .family = MV88E6XXX_FAMILY_6165,
3692                 .name = "Marvell 88E6165",
3693                 .num_databases = 4096,
3694                 .num_ports = 6,
3695                 .port_base_addr = 0x10,
3696                 .age_time_coeff = 15000,
3697                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3698         },
3699
3700         [MV88E6171] = {
3701                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3702                 .family = MV88E6XXX_FAMILY_6351,
3703                 .name = "Marvell 88E6171",
3704                 .num_databases = 4096,
3705                 .num_ports = 7,
3706                 .port_base_addr = 0x10,
3707                 .age_time_coeff = 15000,
3708                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3709         },
3710
3711         [MV88E6172] = {
3712                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3713                 .family = MV88E6XXX_FAMILY_6352,
3714                 .name = "Marvell 88E6172",
3715                 .num_databases = 4096,
3716                 .num_ports = 7,
3717                 .port_base_addr = 0x10,
3718                 .age_time_coeff = 15000,
3719                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3720         },
3721
3722         [MV88E6175] = {
3723                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3724                 .family = MV88E6XXX_FAMILY_6351,
3725                 .name = "Marvell 88E6175",
3726                 .num_databases = 4096,
3727                 .num_ports = 7,
3728                 .port_base_addr = 0x10,
3729                 .age_time_coeff = 15000,
3730                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3731         },
3732
3733         [MV88E6176] = {
3734                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3735                 .family = MV88E6XXX_FAMILY_6352,
3736                 .name = "Marvell 88E6176",
3737                 .num_databases = 4096,
3738                 .num_ports = 7,
3739                 .port_base_addr = 0x10,
3740                 .age_time_coeff = 15000,
3741                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3742         },
3743
3744         [MV88E6185] = {
3745                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3746                 .family = MV88E6XXX_FAMILY_6185,
3747                 .name = "Marvell 88E6185",
3748                 .num_databases = 256,
3749                 .num_ports = 10,
3750                 .port_base_addr = 0x10,
3751                 .age_time_coeff = 15000,
3752                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3753         },
3754
3755         [MV88E6240] = {
3756                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3757                 .family = MV88E6XXX_FAMILY_6352,
3758                 .name = "Marvell 88E6240",
3759                 .num_databases = 4096,
3760                 .num_ports = 7,
3761                 .port_base_addr = 0x10,
3762                 .age_time_coeff = 15000,
3763                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3764         },
3765
3766         [MV88E6320] = {
3767                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3768                 .family = MV88E6XXX_FAMILY_6320,
3769                 .name = "Marvell 88E6320",
3770                 .num_databases = 4096,
3771                 .num_ports = 7,
3772                 .port_base_addr = 0x10,
3773                 .age_time_coeff = 15000,
3774                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3775         },
3776
3777         [MV88E6321] = {
3778                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3779                 .family = MV88E6XXX_FAMILY_6320,
3780                 .name = "Marvell 88E6321",
3781                 .num_databases = 4096,
3782                 .num_ports = 7,
3783                 .port_base_addr = 0x10,
3784                 .age_time_coeff = 15000,
3785                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3786         },
3787
3788         [MV88E6350] = {
3789                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3790                 .family = MV88E6XXX_FAMILY_6351,
3791                 .name = "Marvell 88E6350",
3792                 .num_databases = 4096,
3793                 .num_ports = 7,
3794                 .port_base_addr = 0x10,
3795                 .age_time_coeff = 15000,
3796                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3797         },
3798
3799         [MV88E6351] = {
3800                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3801                 .family = MV88E6XXX_FAMILY_6351,
3802                 .name = "Marvell 88E6351",
3803                 .num_databases = 4096,
3804                 .num_ports = 7,
3805                 .port_base_addr = 0x10,
3806                 .age_time_coeff = 15000,
3807                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3808         },
3809
3810         [MV88E6352] = {
3811                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3812                 .family = MV88E6XXX_FAMILY_6352,
3813                 .name = "Marvell 88E6352",
3814                 .num_databases = 4096,
3815                 .num_ports = 7,
3816                 .port_base_addr = 0x10,
3817                 .age_time_coeff = 15000,
3818                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3819         },
3820 };
3821
3822 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3823 {
3824         int i;
3825
3826         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3827                 if (mv88e6xxx_table[i].prod_num == prod_num)
3828                         return &mv88e6xxx_table[i];
3829
3830         return NULL;
3831 }
3832
3833 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3834 {
3835         const struct mv88e6xxx_info *info;
3836         unsigned int prod_num, rev;
3837         u16 id;
3838         int err;
3839
3840         mutex_lock(&chip->reg_lock);
3841         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3842         mutex_unlock(&chip->reg_lock);
3843         if (err)
3844                 return err;
3845
3846         prod_num = (id & 0xfff0) >> 4;
3847         rev = id & 0x000f;
3848
3849         info = mv88e6xxx_lookup_info(prod_num);
3850         if (!info)
3851                 return -ENODEV;
3852
3853         /* Update the compatible info with the probed one */
3854         chip->info = info;
3855
3856         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3857                  chip->info->prod_num, chip->info->name, rev);
3858
3859         return 0;
3860 }
3861
3862 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3863 {
3864         struct mv88e6xxx_chip *chip;
3865
3866         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3867         if (!chip)
3868                 return NULL;
3869
3870         chip->dev = dev;
3871
3872         mutex_init(&chip->reg_lock);
3873
3874         return chip;
3875 }
3876
3877 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3878                               struct mii_bus *bus, int sw_addr)
3879 {
3880         /* ADDR[0] pin is unavailable externally and considered zero */
3881         if (sw_addr & 0x1)
3882                 return -EINVAL;
3883
3884         if (sw_addr == 0)
3885                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3886         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3887                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3888         else
3889                 return -EINVAL;
3890
3891         chip->bus = bus;
3892         chip->sw_addr = sw_addr;
3893
3894         return 0;
3895 }
3896
3897 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3898                                        struct device *host_dev, int sw_addr,
3899                                        void **priv)
3900 {
3901         struct mv88e6xxx_chip *chip;
3902         struct mii_bus *bus;
3903         int err;
3904
3905         bus = dsa_host_dev_to_mii_bus(host_dev);
3906         if (!bus)
3907                 return NULL;
3908
3909         chip = mv88e6xxx_alloc_chip(dsa_dev);
3910         if (!chip)
3911                 return NULL;
3912
3913         /* Legacy SMI probing will only support chips similar to 88E6085 */
3914         chip->info = &mv88e6xxx_table[MV88E6085];
3915
3916         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3917         if (err)
3918                 goto free;
3919
3920         err = mv88e6xxx_detect(chip);
3921         if (err)
3922                 goto free;
3923
3924         err = mv88e6xxx_mdio_register(chip, NULL);
3925         if (err)
3926                 goto free;
3927
3928         *priv = chip;
3929
3930         return chip->info->name;
3931 free:
3932         devm_kfree(dsa_dev, chip);
3933
3934         return NULL;
3935 }
3936
3937 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3938         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3939         .probe                  = mv88e6xxx_drv_probe,
3940         .setup                  = mv88e6xxx_setup,
3941         .set_addr               = mv88e6xxx_set_addr,
3942         .adjust_link            = mv88e6xxx_adjust_link,
3943         .get_strings            = mv88e6xxx_get_strings,
3944         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3945         .get_sset_count         = mv88e6xxx_get_sset_count,
3946         .set_eee                = mv88e6xxx_set_eee,
3947         .get_eee                = mv88e6xxx_get_eee,
3948 #ifdef CONFIG_NET_DSA_HWMON
3949         .get_temp               = mv88e6xxx_get_temp,
3950         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3951         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3952         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3953 #endif
3954         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3955         .get_eeprom             = mv88e6xxx_get_eeprom,
3956         .set_eeprom             = mv88e6xxx_set_eeprom,
3957         .get_regs_len           = mv88e6xxx_get_regs_len,
3958         .get_regs               = mv88e6xxx_get_regs,
3959         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3960         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3961         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3962         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3963         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3964         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3965         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3966         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3967         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3968         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
3969         .port_fdb_add           = mv88e6xxx_port_fdb_add,
3970         .port_fdb_del           = mv88e6xxx_port_fdb_del,
3971         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3972 };
3973
3974 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3975                                      struct device_node *np)
3976 {
3977         struct device *dev = chip->dev;
3978         struct dsa_switch *ds;
3979
3980         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3981         if (!ds)
3982                 return -ENOMEM;
3983
3984         ds->dev = dev;
3985         ds->priv = chip;
3986         ds->drv = &mv88e6xxx_switch_driver;
3987
3988         dev_set_drvdata(dev, ds);
3989
3990         return dsa_register_switch(ds, np);
3991 }
3992
3993 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3994 {
3995         dsa_unregister_switch(chip->ds);
3996 }
3997
3998 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3999 {
4000         struct device *dev = &mdiodev->dev;
4001         struct device_node *np = dev->of_node;
4002         const struct mv88e6xxx_info *compat_info;
4003         struct mv88e6xxx_chip *chip;
4004         u32 eeprom_len;
4005         int err;
4006
4007         compat_info = of_device_get_match_data(dev);
4008         if (!compat_info)
4009                 return -EINVAL;
4010
4011         chip = mv88e6xxx_alloc_chip(dev);
4012         if (!chip)
4013                 return -ENOMEM;
4014
4015         chip->info = compat_info;
4016
4017         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4018         if (err)
4019                 return err;
4020
4021         err = mv88e6xxx_detect(chip);
4022         if (err)
4023                 return err;
4024
4025         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4026         if (IS_ERR(chip->reset))
4027                 return PTR_ERR(chip->reset);
4028
4029         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4030             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4031                 chip->eeprom_len = eeprom_len;
4032
4033         err = mv88e6xxx_mdio_register(chip, np);
4034         if (err)
4035                 return err;
4036
4037         err = mv88e6xxx_register_switch(chip, np);
4038         if (err) {
4039                 mv88e6xxx_mdio_unregister(chip);
4040                 return err;
4041         }
4042
4043         return 0;
4044 }
4045
4046 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4047 {
4048         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4049         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4050
4051         mv88e6xxx_unregister_switch(chip);
4052         mv88e6xxx_mdio_unregister(chip);
4053 }
4054
4055 static const struct of_device_id mv88e6xxx_of_match[] = {
4056         {
4057                 .compatible = "marvell,mv88e6085",
4058                 .data = &mv88e6xxx_table[MV88E6085],
4059         },
4060         { /* sentinel */ },
4061 };
4062
4063 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4064
4065 static struct mdio_driver mv88e6xxx_driver = {
4066         .probe  = mv88e6xxx_probe,
4067         .remove = mv88e6xxx_remove,
4068         .mdiodrv.driver = {
4069                 .name = "mv88e6085",
4070                 .of_match_table = mv88e6xxx_of_match,
4071         },
4072 };
4073
4074 static int __init mv88e6xxx_init(void)
4075 {
4076         register_switch_driver(&mv88e6xxx_switch_driver);
4077         return mdio_driver_register(&mv88e6xxx_driver);
4078 }
4079 module_init(mv88e6xxx_init);
4080
4081 static void __exit mv88e6xxx_cleanup(void)
4082 {
4083         mdio_driver_unregister(&mv88e6xxx_driver);
4084         unregister_switch_driver(&mv88e6xxx_switch_driver);
4085 }
4086 module_exit(mv88e6xxx_cleanup);
4087
4088 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4089 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4090 MODULE_LICENSE("GPL");