2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
35 #include <net/switchdev.h>
37 #include "mv88e6xxx.h"
42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
63 int addr, int reg, u16 *val)
68 return chip->smi_ops->read(chip, addr, reg, val);
71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
72 int addr, int reg, u16 val)
77 return chip->smi_ops->write(chip, addr, reg, val);
80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
81 int addr, int reg, u16 *val)
85 ret = mdiobus_read_nested(chip->bus, addr, reg);
94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
95 int addr, int reg, u16 val)
99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
116 for (i = 0; i < 16; i++) {
117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
121 if ((ret & SMI_CMD_BUSY) == 0)
128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
129 int addr, int reg, u16 *val)
133 /* Wait for the bus to become free. */
134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
138 /* Transmit the read command. */
139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
144 /* Wait for the read command to complete. */
145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
160 int addr, int reg, u16 val)
164 /* Wait for the bus to become free. */
165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
169 /* Transmit the data to write. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
174 /* Transmit the write command. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
180 /* Wait for the write command to complete. */
181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
197 assert_reg_lock(chip);
199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
213 assert_reg_lock(chip);
215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
225 static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
227 int addr, int reg, u16 *val)
229 return mv88e6xxx_read(chip, addr, reg, val);
232 static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
234 int addr, int reg, u16 val)
236 return mv88e6xxx_write(chip, addr, reg, val);
239 static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
241 struct mv88e6xxx_mdio_bus *mdio_bus;
243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
248 return mdio_bus->bus;
251 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
254 int addr = phy; /* PHY devices addresses start at 0x0 */
257 bus = mv88e6xxx_default_mdio_bus(chip);
261 if (!chip->info->ops->phy_read)
264 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
267 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
270 int addr = phy; /* PHY devices addresses start at 0x0 */
273 bus = mv88e6xxx_default_mdio_bus(chip);
277 if (!chip->info->ops->phy_write)
280 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
283 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
291 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
303 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
304 u8 page, int reg, u16 *val)
308 /* There is no paging for registers 22 */
312 err = mv88e6xxx_phy_page_get(chip, phy, page);
314 err = mv88e6xxx_phy_read(chip, phy, reg, val);
315 mv88e6xxx_phy_page_put(chip, phy);
321 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
322 u8 page, int reg, u16 val)
326 /* There is no paging for registers 22 */
330 err = mv88e6xxx_phy_page_get(chip, phy, page);
332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
333 mv88e6xxx_phy_page_put(chip, phy);
339 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
345 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
351 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
354 unsigned int n = d->hwirq;
356 chip->g1_irq.masked |= (1 << n);
359 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 unsigned int n = d->hwirq;
364 chip->g1_irq.masked &= ~(1 << n);
367 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
369 struct mv88e6xxx_chip *chip = dev_id;
370 unsigned int nhandled = 0;
371 unsigned int sub_irq;
376 mutex_lock(&chip->reg_lock);
377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
378 mutex_unlock(&chip->reg_lock);
383 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
384 if (reg & (1 << n)) {
385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
386 handle_nested_irq(sub_irq);
391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
394 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
398 mutex_lock(&chip->reg_lock);
401 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
413 reg |= (~chip->g1_irq.masked & mask);
415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
420 mutex_unlock(&chip->reg_lock);
423 static struct irq_chip mv88e6xxx_g1_irq_chip = {
424 .name = "mv88e6xxx-g1",
425 .irq_mask = mv88e6xxx_g1_irq_mask,
426 .irq_unmask = mv88e6xxx_g1_irq_unmask,
427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
431 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
433 irq_hw_number_t hwirq)
435 struct mv88e6xxx_chip *chip = d->host_data;
437 irq_set_chip_data(irq, d->host_data);
438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
439 irq_set_noprobe(irq);
444 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
445 .map = mv88e6xxx_g1_irq_domain_map,
446 .xlate = irq_domain_xlate_twocell,
449 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
455 mask |= GENMASK(chip->g1_irq.nirqs, 0);
456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
458 free_irq(chip->irq, chip);
460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
461 virq = irq_find_mapping(chip->g1_irq.domain, irq);
462 irq_dispose_mapping(virq);
465 irq_domain_remove(chip->g1_irq.domain);
468 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
473 chip->g1_irq.nirqs = chip->info->g1_irqs;
474 chip->g1_irq.domain = irq_domain_add_simple(
475 NULL, chip->g1_irq.nirqs, 0,
476 &mv88e6xxx_g1_irq_domain_ops, chip);
477 if (!chip->g1_irq.domain)
480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
481 irq_create_mapping(chip->g1_irq.domain, irq);
483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
484 chip->g1_irq.masked = ~0;
486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
496 /* Reading the interrupt status clears (most of) them */
497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
501 err = request_threaded_irq(chip->irq, NULL,
502 mv88e6xxx_g1_irq_thread_fn,
503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
504 dev_name(chip->dev), chip);
511 mask |= GENMASK(chip->g1_irq.nirqs, 0);
512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
515 for (irq = 0; irq < 16; irq++) {
516 virq = irq_find_mapping(chip->g1_irq.domain, irq);
517 irq_dispose_mapping(virq);
520 irq_domain_remove(chip->g1_irq.domain);
525 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
529 for (i = 0; i < 16; i++) {
533 err = mv88e6xxx_read(chip, addr, reg, &val);
540 usleep_range(1000, 2000);
543 dev_err(chip->dev, "Timeout while waiting for switch\n");
547 /* Indirect write to single pointer-data register with an Update bit */
548 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
553 /* Wait until the previous operation is completed */
554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
558 /* Set the Update bit to trigger a write operation */
559 val = BIT(15) | update;
561 return mv88e6xxx_write(chip, addr, reg, val);
564 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
566 if (!chip->info->ops->ppu_disable)
569 return chip->info->ops->ppu_disable(chip);
572 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
574 if (!chip->info->ops->ppu_enable)
577 return chip->info->ops->ppu_enable(chip);
580 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
582 struct mv88e6xxx_chip *chip;
584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
586 mutex_lock(&chip->reg_lock);
588 if (mutex_trylock(&chip->ppu_mutex)) {
589 if (mv88e6xxx_ppu_enable(chip) == 0)
590 chip->ppu_disabled = 0;
591 mutex_unlock(&chip->ppu_mutex);
594 mutex_unlock(&chip->reg_lock);
597 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
599 struct mv88e6xxx_chip *chip = (void *)_ps;
601 schedule_work(&chip->ppu_work);
604 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
608 mutex_lock(&chip->ppu_mutex);
610 /* If the PHY polling unit is enabled, disable it so that
611 * we can access the PHY registers. If it was already
612 * disabled, cancel the timer that is going to re-enable
615 if (!chip->ppu_disabled) {
616 ret = mv88e6xxx_ppu_disable(chip);
618 mutex_unlock(&chip->ppu_mutex);
621 chip->ppu_disabled = 1;
623 del_timer(&chip->ppu_timer);
630 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
632 /* Schedule a timer to re-enable the PHY polling unit. */
633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
634 mutex_unlock(&chip->ppu_mutex);
637 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
639 mutex_init(&chip->ppu_mutex);
640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
642 (unsigned long)chip);
645 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
647 del_timer_sync(&chip->ppu_timer);
650 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
652 int addr, int reg, u16 *val)
656 err = mv88e6xxx_ppu_access_get(chip);
658 err = mv88e6xxx_read(chip, addr, reg, val);
659 mv88e6xxx_ppu_access_put(chip);
665 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
667 int addr, int reg, u16 val)
671 err = mv88e6xxx_ppu_access_get(chip);
673 err = mv88e6xxx_write(chip, addr, reg, val);
674 mv88e6xxx_ppu_access_put(chip);
680 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
682 return chip->info->family == MV88E6XXX_FAMILY_6095;
685 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
687 return chip->info->family == MV88E6XXX_FAMILY_6097;
690 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
692 return chip->info->family == MV88E6XXX_FAMILY_6165;
695 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
697 return chip->info->family == MV88E6XXX_FAMILY_6185;
700 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
702 return chip->info->family == MV88E6XXX_FAMILY_6320;
705 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
707 return chip->info->family == MV88E6XXX_FAMILY_6351;
710 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
712 return chip->info->family == MV88E6XXX_FAMILY_6352;
715 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
716 int link, int speed, int duplex,
717 phy_interface_t mode)
721 if (!chip->info->ops->port_set_link)
724 /* Port's MAC control must not be changed unless the link is down */
725 err = chip->info->ops->port_set_link(chip, port, 0);
729 if (chip->info->ops->port_set_speed) {
730 err = chip->info->ops->port_set_speed(chip, port, speed);
731 if (err && err != -EOPNOTSUPP)
735 if (chip->info->ops->port_set_duplex) {
736 err = chip->info->ops->port_set_duplex(chip, port, duplex);
737 if (err && err != -EOPNOTSUPP)
741 if (chip->info->ops->port_set_rgmii_delay) {
742 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
743 if (err && err != -EOPNOTSUPP)
749 if (chip->info->ops->port_set_link(chip, port, link))
750 netdev_err(chip->ds->ports[port].netdev,
751 "failed to restore MAC's link\n");
756 /* We expect the switch to perform auto negotiation if there is a real
757 * phy. However, in the case of a fixed link phy, we force the port
758 * settings from the fixed link settings.
760 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
761 struct phy_device *phydev)
763 struct mv88e6xxx_chip *chip = ds->priv;
766 if (!phy_is_pseudo_fixed_link(phydev))
769 mutex_lock(&chip->reg_lock);
770 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
771 phydev->duplex, phydev->interface);
772 mutex_unlock(&chip->reg_lock);
774 if (err && err != -EOPNOTSUPP)
775 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
778 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
780 if (!chip->info->ops->stats_snapshot)
783 return chip->info->ops->stats_snapshot(chip, port);
786 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
787 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
788 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
789 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
790 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
791 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
792 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
793 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
794 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
795 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
796 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
797 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
798 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
799 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
800 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
801 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
802 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
803 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
804 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
805 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
806 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
807 { "single", 4, 0x14, STATS_TYPE_BANK0, },
808 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
809 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
810 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
811 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
812 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
813 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
814 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
815 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
816 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
817 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
818 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
819 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
820 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
821 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
822 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
823 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
824 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
825 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
826 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
827 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
828 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
829 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
830 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
831 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
832 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
833 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
834 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
835 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
836 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
837 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
838 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
839 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
840 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
841 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
842 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
843 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
844 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
845 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
848 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
849 struct mv88e6xxx_hw_stat *s,
850 int port, u16 bank1_select,
860 case STATS_TYPE_PORT:
861 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
866 if (s->sizeof_stat == 4) {
867 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
873 case STATS_TYPE_BANK1:
876 case STATS_TYPE_BANK0:
877 reg |= s->reg | histogram;
878 mv88e6xxx_g1_stats_read(chip, reg, &low);
879 if (s->sizeof_stat == 8)
880 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
882 value = (((u64)high) << 16) | low;
886 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
887 uint8_t *data, int types)
889 struct mv88e6xxx_hw_stat *stat;
892 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
893 stat = &mv88e6xxx_hw_stats[i];
894 if (stat->type & types) {
895 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
902 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
905 mv88e6xxx_stats_get_strings(chip, data,
906 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
909 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
912 mv88e6xxx_stats_get_strings(chip, data,
913 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
916 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
919 struct mv88e6xxx_chip *chip = ds->priv;
921 if (chip->info->ops->stats_get_strings)
922 chip->info->ops->stats_get_strings(chip, data);
925 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
928 struct mv88e6xxx_hw_stat *stat;
931 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
932 stat = &mv88e6xxx_hw_stats[i];
933 if (stat->type & types)
939 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
941 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
945 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
947 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
951 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
953 struct mv88e6xxx_chip *chip = ds->priv;
955 if (chip->info->ops->stats_get_sset_count)
956 return chip->info->ops->stats_get_sset_count(chip);
961 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
962 uint64_t *data, int types,
963 u16 bank1_select, u16 histogram)
965 struct mv88e6xxx_hw_stat *stat;
968 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
969 stat = &mv88e6xxx_hw_stats[i];
970 if (stat->type & types) {
971 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
979 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
982 return mv88e6xxx_stats_get_stats(chip, port, data,
983 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
984 0, GLOBAL_STATS_OP_HIST_RX_TX);
987 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
990 return mv88e6xxx_stats_get_stats(chip, port, data,
991 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
992 GLOBAL_STATS_OP_BANK_1_BIT_9,
993 GLOBAL_STATS_OP_HIST_RX_TX);
996 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
999 return mv88e6xxx_stats_get_stats(chip, port, data,
1000 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1001 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
1004 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1007 if (chip->info->ops->stats_get_stats)
1008 chip->info->ops->stats_get_stats(chip, port, data);
1011 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1014 struct mv88e6xxx_chip *chip = ds->priv;
1017 mutex_lock(&chip->reg_lock);
1019 ret = mv88e6xxx_stats_snapshot(chip, port);
1021 mutex_unlock(&chip->reg_lock);
1025 mv88e6xxx_get_stats(chip, port, data);
1027 mutex_unlock(&chip->reg_lock);
1030 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1032 if (chip->info->ops->stats_set_histogram)
1033 return chip->info->ops->stats_set_histogram(chip);
1038 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1040 return 32 * sizeof(u16);
1043 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1044 struct ethtool_regs *regs, void *_p)
1046 struct mv88e6xxx_chip *chip = ds->priv;
1054 memset(p, 0xff, 32 * sizeof(u16));
1056 mutex_lock(&chip->reg_lock);
1058 for (i = 0; i < 32; i++) {
1060 err = mv88e6xxx_port_read(chip, port, i, ®);
1065 mutex_unlock(&chip->reg_lock);
1068 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1070 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
1073 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1074 struct ethtool_eee *e)
1076 struct mv88e6xxx_chip *chip = ds->priv;
1080 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1083 mutex_lock(&chip->reg_lock);
1085 err = mv88e6xxx_phy_read(chip, port, 16, ®);
1089 e->eee_enabled = !!(reg & 0x0200);
1090 e->tx_lpi_enabled = !!(reg & 0x0100);
1092 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
1096 e->eee_active = !!(reg & PORT_STATUS_EEE);
1098 mutex_unlock(&chip->reg_lock);
1103 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1104 struct phy_device *phydev, struct ethtool_eee *e)
1106 struct mv88e6xxx_chip *chip = ds->priv;
1110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1113 mutex_lock(&chip->reg_lock);
1115 err = mv88e6xxx_phy_read(chip, port, 16, ®);
1122 if (e->tx_lpi_enabled)
1125 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1127 mutex_unlock(&chip->reg_lock);
1132 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1137 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
1138 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1141 } else if (mv88e6xxx_num_databases(chip) == 256) {
1142 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1143 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1147 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1148 (val & 0xfff) | ((fid << 8) & 0xf000));
1152 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1156 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1160 return _mv88e6xxx_atu_wait(chip);
1163 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1164 struct mv88e6xxx_atu_entry *entry)
1166 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1168 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1169 unsigned int mask, shift;
1172 data |= GLOBAL_ATU_DATA_TRUNK;
1173 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1174 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1176 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1177 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1180 data |= (entry->portv_trunkid << shift) & mask;
1183 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1186 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1187 struct mv88e6xxx_atu_entry *entry,
1193 err = _mv88e6xxx_atu_wait(chip);
1197 err = _mv88e6xxx_atu_data_write(chip, entry);
1202 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1203 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1205 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1206 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1209 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1212 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1213 u16 fid, bool static_too)
1215 struct mv88e6xxx_atu_entry entry = {
1217 .state = 0, /* EntryState bits must be 0 */
1220 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1223 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1224 int from_port, int to_port, bool static_too)
1226 struct mv88e6xxx_atu_entry entry = {
1231 /* EntryState bits must be 0xF */
1232 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1234 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1235 entry.portv_trunkid = (to_port & 0x0f) << 4;
1236 entry.portv_trunkid |= from_port & 0x0f;
1238 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1241 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1242 int port, bool static_too)
1244 /* Destination port 0xF means remove the entries */
1245 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1248 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1250 struct net_device *bridge = chip->ports[port].bridge_dev;
1251 struct dsa_switch *ds = chip->ds;
1252 u16 output_ports = 0;
1255 /* allow CPU port or DSA link(s) to send frames to every port */
1256 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1259 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1260 /* allow sending frames to every group member */
1261 if (bridge && chip->ports[i].bridge_dev == bridge)
1262 output_ports |= BIT(i);
1264 /* allow sending frames to CPU port and DSA link(s) */
1265 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1266 output_ports |= BIT(i);
1270 /* prevent frames from going back out of the port they came in on */
1271 output_ports &= ~BIT(port);
1273 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1276 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1279 struct mv88e6xxx_chip *chip = ds->priv;
1284 case BR_STATE_DISABLED:
1285 stp_state = PORT_CONTROL_STATE_DISABLED;
1287 case BR_STATE_BLOCKING:
1288 case BR_STATE_LISTENING:
1289 stp_state = PORT_CONTROL_STATE_BLOCKING;
1291 case BR_STATE_LEARNING:
1292 stp_state = PORT_CONTROL_STATE_LEARNING;
1294 case BR_STATE_FORWARDING:
1296 stp_state = PORT_CONTROL_STATE_FORWARDING;
1300 mutex_lock(&chip->reg_lock);
1301 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1302 mutex_unlock(&chip->reg_lock);
1305 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1308 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1310 struct mv88e6xxx_chip *chip = ds->priv;
1313 mutex_lock(&chip->reg_lock);
1314 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1315 mutex_unlock(&chip->reg_lock);
1318 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1321 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1323 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1326 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1330 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1334 return _mv88e6xxx_vtu_wait(chip);
1337 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1341 ret = _mv88e6xxx_vtu_wait(chip);
1345 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1348 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1349 struct mv88e6xxx_vtu_entry *entry,
1350 unsigned int nibble_offset)
1355 for (i = 0; i < 3; ++i) {
1356 u16 *reg = ®s[i];
1358 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1363 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1364 unsigned int shift = (i % 4) * 4 + nibble_offset;
1365 u16 reg = regs[i / 4];
1367 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1373 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1374 struct mv88e6xxx_vtu_entry *entry)
1376 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1379 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1380 struct mv88e6xxx_vtu_entry *entry)
1382 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1385 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1386 struct mv88e6xxx_vtu_entry *entry,
1387 unsigned int nibble_offset)
1389 u16 regs[3] = { 0 };
1392 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1393 unsigned int shift = (i % 4) * 4 + nibble_offset;
1394 u8 data = entry->data[i];
1396 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1399 for (i = 0; i < 3; ++i) {
1402 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1410 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1411 struct mv88e6xxx_vtu_entry *entry)
1413 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1416 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1417 struct mv88e6xxx_vtu_entry *entry)
1419 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1422 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1424 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1425 vid & GLOBAL_VTU_VID_MASK);
1428 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1429 struct mv88e6xxx_vtu_entry *entry)
1431 struct mv88e6xxx_vtu_entry next = { 0 };
1435 err = _mv88e6xxx_vtu_wait(chip);
1439 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1443 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1447 next.vid = val & GLOBAL_VTU_VID_MASK;
1448 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1451 err = mv88e6xxx_vtu_data_read(chip, &next);
1455 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1456 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1460 next.fid = val & GLOBAL_VTU_FID_MASK;
1461 } else if (mv88e6xxx_num_databases(chip) == 256) {
1462 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1463 * VTU DBNum[3:0] are located in VTU Operation 3:0
1465 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1469 next.fid = (val & 0xf00) >> 4;
1470 next.fid |= val & 0xf;
1473 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1474 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1478 next.sid = val & GLOBAL_VTU_SID_MASK;
1486 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1487 struct switchdev_obj_port_vlan *vlan,
1488 int (*cb)(struct switchdev_obj *obj))
1490 struct mv88e6xxx_chip *chip = ds->priv;
1491 struct mv88e6xxx_vtu_entry next;
1495 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1498 mutex_lock(&chip->reg_lock);
1500 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1504 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1509 err = _mv88e6xxx_vtu_getnext(chip, &next);
1516 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1519 /* reinit and dump this VLAN obj */
1520 vlan->vid_begin = next.vid;
1521 vlan->vid_end = next.vid;
1524 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1525 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1527 if (next.vid == pvid)
1528 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1530 err = cb(&vlan->obj);
1533 } while (next.vid < GLOBAL_VTU_VID_MASK);
1536 mutex_unlock(&chip->reg_lock);
1541 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1542 struct mv88e6xxx_vtu_entry *entry)
1544 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1548 err = _mv88e6xxx_vtu_wait(chip);
1555 /* Write port member tags */
1556 err = mv88e6xxx_vtu_data_write(chip, entry);
1560 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1561 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1562 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1567 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1568 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1569 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1572 } else if (mv88e6xxx_num_databases(chip) == 256) {
1573 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1574 * VTU DBNum[3:0] are located in VTU Operation 3:0
1576 op |= (entry->fid & 0xf0) << 8;
1577 op |= entry->fid & 0xf;
1580 reg = GLOBAL_VTU_VID_VALID;
1582 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1583 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1587 return _mv88e6xxx_vtu_cmd(chip, op);
1590 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1591 struct mv88e6xxx_vtu_entry *entry)
1593 struct mv88e6xxx_vtu_entry next = { 0 };
1597 err = _mv88e6xxx_vtu_wait(chip);
1601 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1602 sid & GLOBAL_VTU_SID_MASK);
1606 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1610 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1614 next.sid = val & GLOBAL_VTU_SID_MASK;
1616 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1620 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1623 err = mv88e6xxx_stu_data_read(chip, &next);
1632 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1633 struct mv88e6xxx_vtu_entry *entry)
1638 err = _mv88e6xxx_vtu_wait(chip);
1645 /* Write port states */
1646 err = mv88e6xxx_stu_data_write(chip, entry);
1650 reg = GLOBAL_VTU_VID_VALID;
1652 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1656 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1661 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1664 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1666 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1667 struct mv88e6xxx_vtu_entry vlan;
1670 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1672 /* Set every FID bit used by the (un)bridged ports */
1673 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1674 err = mv88e6xxx_port_get_fid(chip, i, fid);
1678 set_bit(*fid, fid_bitmap);
1681 /* Set every FID bit used by the VLAN entries */
1682 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1687 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1694 set_bit(vlan.fid, fid_bitmap);
1695 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1697 /* The reset value 0x000 is used to indicate that multiple address
1698 * databases are not needed. Return the next positive available.
1700 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1701 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1704 /* Clear the database */
1705 return _mv88e6xxx_atu_flush(chip, *fid, true);
1708 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1709 struct mv88e6xxx_vtu_entry *entry)
1711 struct dsa_switch *ds = chip->ds;
1712 struct mv88e6xxx_vtu_entry vlan = {
1718 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1722 /* exclude all ports except the CPU and DSA ports */
1723 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1724 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1725 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1726 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1728 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1729 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1730 struct mv88e6xxx_vtu_entry vstp;
1732 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1733 * implemented, only one STU entry is needed to cover all VTU
1734 * entries. Thus, validate the SID 0.
1737 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1741 if (vstp.sid != vlan.sid || !vstp.valid) {
1742 memset(&vstp, 0, sizeof(vstp));
1744 vstp.sid = vlan.sid;
1746 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1756 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1757 struct mv88e6xxx_vtu_entry *entry, bool creat)
1764 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1768 err = _mv88e6xxx_vtu_getnext(chip, entry);
1772 if (entry->vid != vid || !entry->valid) {
1775 /* -ENOENT would've been more appropriate, but switchdev expects
1776 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1779 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1785 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1786 u16 vid_begin, u16 vid_end)
1788 struct mv88e6xxx_chip *chip = ds->priv;
1789 struct mv88e6xxx_vtu_entry vlan;
1795 mutex_lock(&chip->reg_lock);
1797 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1802 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1809 if (vlan.vid > vid_end)
1812 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1813 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1816 if (!ds->ports[port].netdev)
1820 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1823 if (chip->ports[i].bridge_dev ==
1824 chip->ports[port].bridge_dev)
1825 break; /* same bridge, check next VLAN */
1827 if (!chip->ports[i].bridge_dev)
1830 netdev_warn(ds->ports[port].netdev,
1831 "hardware VLAN %d already used by %s\n",
1833 netdev_name(chip->ports[i].bridge_dev));
1837 } while (vlan.vid < vid_end);
1840 mutex_unlock(&chip->reg_lock);
1845 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1846 bool vlan_filtering)
1848 struct mv88e6xxx_chip *chip = ds->priv;
1849 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1850 PORT_CONTROL_2_8021Q_DISABLED;
1853 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1856 mutex_lock(&chip->reg_lock);
1857 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1858 mutex_unlock(&chip->reg_lock);
1864 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1865 const struct switchdev_obj_port_vlan *vlan,
1866 struct switchdev_trans *trans)
1868 struct mv88e6xxx_chip *chip = ds->priv;
1871 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1874 /* If the requested port doesn't belong to the same bridge as the VLAN
1875 * members, do not support it (yet) and fallback to software VLAN.
1877 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1882 /* We don't need any dynamic resource from the kernel (yet),
1883 * so skip the prepare phase.
1888 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1889 u16 vid, bool untagged)
1891 struct mv88e6xxx_vtu_entry vlan;
1894 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1898 vlan.data[port] = untagged ?
1899 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1900 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1902 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1905 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1906 const struct switchdev_obj_port_vlan *vlan,
1907 struct switchdev_trans *trans)
1909 struct mv88e6xxx_chip *chip = ds->priv;
1910 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1911 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1914 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1917 mutex_lock(&chip->reg_lock);
1919 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1920 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1921 netdev_err(ds->ports[port].netdev,
1922 "failed to add VLAN %d%c\n",
1923 vid, untagged ? 'u' : 't');
1925 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1926 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1929 mutex_unlock(&chip->reg_lock);
1932 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1935 struct dsa_switch *ds = chip->ds;
1936 struct mv88e6xxx_vtu_entry vlan;
1939 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1943 /* Tell switchdev if this VLAN is handled in software */
1944 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1947 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1949 /* keep the VLAN unless all ports are excluded */
1951 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1952 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1955 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1961 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1965 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1968 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1969 const struct switchdev_obj_port_vlan *vlan)
1971 struct mv88e6xxx_chip *chip = ds->priv;
1975 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1978 mutex_lock(&chip->reg_lock);
1980 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1984 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1985 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1990 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1997 mutex_unlock(&chip->reg_lock);
2002 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2003 const unsigned char *addr)
2007 for (i = 0; i < 3; i++) {
2008 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2009 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2017 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2018 unsigned char *addr)
2023 for (i = 0; i < 3; i++) {
2024 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2028 addr[i * 2] = val >> 8;
2029 addr[i * 2 + 1] = val & 0xff;
2035 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2036 struct mv88e6xxx_atu_entry *entry)
2040 ret = _mv88e6xxx_atu_wait(chip);
2044 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2048 ret = _mv88e6xxx_atu_data_write(chip, entry);
2052 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2055 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2056 struct mv88e6xxx_atu_entry *entry);
2058 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2059 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2061 struct mv88e6xxx_atu_entry next;
2064 memcpy(next.mac, addr, ETH_ALEN);
2065 eth_addr_dec(next.mac);
2067 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2072 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2076 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2079 if (ether_addr_equal(next.mac, addr)) {
2083 } while (ether_addr_greater(addr, next.mac));
2085 memset(entry, 0, sizeof(*entry));
2087 ether_addr_copy(entry->mac, addr);
2092 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2093 const unsigned char *addr, u16 vid,
2096 struct mv88e6xxx_vtu_entry vlan;
2097 struct mv88e6xxx_atu_entry entry;
2100 /* Null VLAN ID corresponds to the port private database */
2102 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2104 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2108 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2112 /* Purge the ATU entry only if no port is using it anymore */
2113 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2114 entry.portv_trunkid &= ~BIT(port);
2115 if (!entry.portv_trunkid)
2116 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2118 entry.portv_trunkid |= BIT(port);
2119 entry.state = state;
2122 return _mv88e6xxx_atu_load(chip, &entry);
2125 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2126 const struct switchdev_obj_port_fdb *fdb,
2127 struct switchdev_trans *trans)
2129 /* We don't need any dynamic resource from the kernel (yet),
2130 * so skip the prepare phase.
2135 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2136 const struct switchdev_obj_port_fdb *fdb,
2137 struct switchdev_trans *trans)
2139 struct mv88e6xxx_chip *chip = ds->priv;
2141 mutex_lock(&chip->reg_lock);
2142 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2143 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2144 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2145 mutex_unlock(&chip->reg_lock);
2148 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2149 const struct switchdev_obj_port_fdb *fdb)
2151 struct mv88e6xxx_chip *chip = ds->priv;
2154 mutex_lock(&chip->reg_lock);
2155 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2156 GLOBAL_ATU_DATA_STATE_UNUSED);
2157 mutex_unlock(&chip->reg_lock);
2162 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2163 struct mv88e6xxx_atu_entry *entry)
2165 struct mv88e6xxx_atu_entry next = { 0 };
2171 err = _mv88e6xxx_atu_wait(chip);
2175 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2179 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2183 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2187 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2188 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2189 unsigned int mask, shift;
2191 if (val & GLOBAL_ATU_DATA_TRUNK) {
2193 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2194 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2197 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2198 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2201 next.portv_trunkid = (val & mask) >> shift;
2208 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2209 u16 fid, u16 vid, int port,
2210 struct switchdev_obj *obj,
2211 int (*cb)(struct switchdev_obj *obj))
2213 struct mv88e6xxx_atu_entry addr = {
2214 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2218 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2223 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2227 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2230 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2233 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2234 struct switchdev_obj_port_fdb *fdb;
2236 if (!is_unicast_ether_addr(addr.mac))
2239 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2241 ether_addr_copy(fdb->addr, addr.mac);
2242 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2243 fdb->ndm_state = NUD_NOARP;
2245 fdb->ndm_state = NUD_REACHABLE;
2246 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2247 struct switchdev_obj_port_mdb *mdb;
2249 if (!is_multicast_ether_addr(addr.mac))
2252 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2254 ether_addr_copy(mdb->addr, addr.mac);
2262 } while (!is_broadcast_ether_addr(addr.mac));
2267 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2268 struct switchdev_obj *obj,
2269 int (*cb)(struct switchdev_obj *obj))
2271 struct mv88e6xxx_vtu_entry vlan = {
2272 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2277 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2278 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2282 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2286 /* Dump VLANs' Filtering Information Databases */
2287 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2292 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2299 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2303 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2308 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2309 struct switchdev_obj_port_fdb *fdb,
2310 int (*cb)(struct switchdev_obj *obj))
2312 struct mv88e6xxx_chip *chip = ds->priv;
2315 mutex_lock(&chip->reg_lock);
2316 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2317 mutex_unlock(&chip->reg_lock);
2322 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2323 struct net_device *bridge)
2325 struct mv88e6xxx_chip *chip = ds->priv;
2328 mutex_lock(&chip->reg_lock);
2330 /* Assign the bridge and remap each port's VLANTable */
2331 chip->ports[port].bridge_dev = bridge;
2333 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2334 if (chip->ports[i].bridge_dev == bridge) {
2335 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2341 mutex_unlock(&chip->reg_lock);
2346 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2348 struct mv88e6xxx_chip *chip = ds->priv;
2349 struct net_device *bridge = chip->ports[port].bridge_dev;
2352 mutex_lock(&chip->reg_lock);
2354 /* Unassign the bridge and remap each port's VLANTable */
2355 chip->ports[port].bridge_dev = NULL;
2357 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2358 if (i == port || chip->ports[i].bridge_dev == bridge)
2359 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2360 netdev_warn(ds->ports[i].netdev,
2361 "failed to remap\n");
2363 mutex_unlock(&chip->reg_lock);
2366 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2368 if (chip->info->ops->reset)
2369 return chip->info->ops->reset(chip);
2374 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2376 struct gpio_desc *gpiod = chip->reset;
2378 /* If there is a GPIO connected to the reset pin, toggle it */
2380 gpiod_set_value_cansleep(gpiod, 1);
2381 usleep_range(10000, 20000);
2382 gpiod_set_value_cansleep(gpiod, 0);
2383 usleep_range(10000, 20000);
2387 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2391 /* Set all ports to the Disabled state */
2392 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2393 err = mv88e6xxx_port_set_state(chip, i,
2394 PORT_CONTROL_STATE_DISABLED);
2399 /* Wait for transmit queues to drain,
2400 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2402 usleep_range(2000, 4000);
2407 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2411 err = mv88e6xxx_disable_ports(chip);
2415 mv88e6xxx_hardware_reset(chip);
2417 return mv88e6xxx_software_reset(chip);
2420 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2425 /* Clear Power Down bit */
2426 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2430 if (val & BMCR_PDOWN) {
2432 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2438 static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2443 err = chip->info->ops->port_set_frame_mode(
2444 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2448 return chip->info->ops->port_set_egress_unknowns(
2449 chip, port, port == upstream_port);
2452 static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2456 switch (chip->info->tag_protocol) {
2457 case DSA_TAG_PROTO_EDSA:
2458 err = chip->info->ops->port_set_frame_mode(
2459 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2463 err = mv88e6xxx_port_set_egress_mode(
2464 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2468 if (chip->info->ops->port_set_ether_type)
2469 err = chip->info->ops->port_set_ether_type(
2470 chip, port, ETH_P_EDSA);
2473 case DSA_TAG_PROTO_DSA:
2474 err = chip->info->ops->port_set_frame_mode(
2475 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2479 err = mv88e6xxx_port_set_egress_mode(
2480 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2489 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2492 static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2496 err = chip->info->ops->port_set_frame_mode(
2497 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2501 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2504 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2506 struct dsa_switch *ds = chip->ds;
2510 /* MAC Forcing register: don't force link, speed, duplex or flow control
2511 * state to any particular values on physical ports, but force the CPU
2512 * port and all DSA ports to their maximum bandwidth and full duplex.
2514 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2515 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2516 SPEED_MAX, DUPLEX_FULL,
2517 PHY_INTERFACE_MODE_NA);
2519 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2520 SPEED_UNFORCED, DUPLEX_UNFORCED,
2521 PHY_INTERFACE_MODE_NA);
2525 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2526 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2527 * tunneling, determine priority by looking at 802.1p and IP
2528 * priority fields (IP prio has precedence), and set STP state
2531 * If this is the CPU link, use DSA or EDSA tagging depending
2532 * on which tagging mode was configured.
2534 * If this is a link to another switch, use DSA tagging mode.
2536 * If this is the upstream port for this switch, enable
2537 * forwarding of unknown unicasts and multicasts.
2539 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2540 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2541 PORT_CONTROL_STATE_FORWARDING;
2542 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2546 if (dsa_is_cpu_port(ds, port)) {
2547 err = mv88e6xxx_setup_port_cpu(chip, port);
2548 } else if (dsa_is_dsa_port(ds, port)) {
2549 err = mv88e6xxx_setup_port_dsa(chip, port,
2550 dsa_upstream_port(ds));
2552 err = mv88e6xxx_setup_port_normal(chip, port);
2557 /* If this port is connected to a SerDes, make sure the SerDes is not
2560 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2561 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
2564 reg &= PORT_STATUS_CMODE_MASK;
2565 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2566 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2567 (reg == PORT_STATUS_CMODE_SGMII)) {
2568 err = mv88e6xxx_serdes_power_on(chip);
2574 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2575 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2576 * untagged frames on this port, do a destination address lookup on all
2577 * received packets as usual, disable ARP mirroring and don't send a
2578 * copy of all transmitted/received frames on this port to the CPU.
2581 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2582 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2583 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2584 mv88e6xxx_6185_family(chip))
2585 reg = PORT_CONTROL_2_MAP_DA;
2587 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2588 /* Set the upstream port this port should use */
2589 reg |= dsa_upstream_port(ds);
2590 /* enable forwarding of unknown multicast addresses to
2593 if (port == dsa_upstream_port(ds))
2594 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2597 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2600 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2605 if (chip->info->ops->port_jumbo_config) {
2606 err = chip->info->ops->port_jumbo_config(chip, port);
2611 /* Port Association Vector: when learning source addresses
2612 * of packets, add the address to the address database using
2613 * a port bitmap that has only the bit for this port set and
2614 * the other bits clear.
2617 /* Disable learning for CPU port */
2618 if (dsa_is_cpu_port(ds, port))
2621 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2625 /* Egress rate control 2: disable egress rate control. */
2626 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2630 if (chip->info->ops->port_pause_config) {
2631 err = chip->info->ops->port_pause_config(chip, port);
2636 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2637 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2638 mv88e6xxx_6320_family(chip)) {
2639 /* Port ATU control: disable limiting the number of
2640 * address database entries that this port is allowed
2643 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2645 /* Priority Override: disable DA, SA and VTU priority
2648 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2654 if (chip->info->ops->port_tag_remap) {
2655 err = chip->info->ops->port_tag_remap(chip, port);
2660 if (chip->info->ops->port_egress_rate_limiting) {
2661 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2666 /* Port Control 1: disable trunking, disable sending
2667 * learning messages to this port.
2669 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2673 /* Port based VLAN map: give each port the same default address
2674 * database, and allow bidirectional communication between the
2675 * CPU and DSA port(s), and the other ports.
2677 err = mv88e6xxx_port_set_fid(chip, port, 0);
2681 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2685 /* Default VLAN ID and priority: don't set a default VLAN
2686 * ID, and set the default packet priority to zero.
2688 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2691 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2695 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2699 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2703 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2710 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2713 const unsigned int coeff = chip->info->age_time_coeff;
2714 const unsigned int min = 0x01 * coeff;
2715 const unsigned int max = 0xff * coeff;
2720 if (msecs < min || msecs > max)
2723 /* Round to nearest multiple of coeff */
2724 age_time = (msecs + coeff / 2) / coeff;
2726 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2730 /* AgeTime is 11:4 bits */
2732 val |= age_time << 4;
2734 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2737 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2738 unsigned int ageing_time)
2740 struct mv88e6xxx_chip *chip = ds->priv;
2743 mutex_lock(&chip->reg_lock);
2744 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2745 mutex_unlock(&chip->reg_lock);
2750 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2752 struct dsa_switch *ds = chip->ds;
2753 u32 upstream_port = dsa_upstream_port(ds);
2756 /* Enable the PHY Polling Unit if present, don't discard any packets,
2757 * and mask all interrupt sources.
2759 err = mv88e6xxx_ppu_enable(chip);
2763 if (chip->info->ops->g1_set_cpu_port) {
2764 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2769 if (chip->info->ops->g1_set_egress_port) {
2770 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2775 /* Disable remote management, and set the switch's DSA device number. */
2776 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2777 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2778 (ds->index & 0x1f));
2782 /* Clear all the VTU and STU entries */
2783 err = _mv88e6xxx_vtu_stu_flush(chip);
2787 /* Set the default address aging time to 5 minutes, and
2788 * enable address learn messages to be sent to all message
2791 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2792 GLOBAL_ATU_CONTROL_LEARN2ALL);
2796 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2800 /* Clear all ATU entries */
2801 err = _mv88e6xxx_atu_flush(chip, 0, true);
2805 /* Configure the IP ToS mapping registers. */
2806 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2809 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2812 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2815 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2818 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2821 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2824 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2827 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2831 /* Configure the IEEE 802.1p priority mapping register. */
2832 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2836 /* Initialize the statistics unit */
2837 err = mv88e6xxx_stats_set_histogram(chip);
2841 /* Clear the statistics counters for all ports */
2842 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2843 GLOBAL_STATS_OP_FLUSH_ALL);
2847 /* Wait for the flush to complete. */
2848 err = mv88e6xxx_g1_stats_wait(chip);
2855 static int mv88e6xxx_setup(struct dsa_switch *ds)
2857 struct mv88e6xxx_chip *chip = ds->priv;
2862 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2864 mutex_lock(&chip->reg_lock);
2866 /* Setup Switch Port Registers */
2867 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2868 err = mv88e6xxx_setup_port(chip, i);
2873 /* Setup Switch Global 1 Registers */
2874 err = mv88e6xxx_g1_setup(chip);
2878 /* Setup Switch Global 2 Registers */
2879 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2880 err = mv88e6xxx_g2_setup(chip);
2885 /* Some generations have the configuration of sending reserved
2886 * management frames to the CPU in global2, others in
2887 * global1. Hence it does not fit the two setup functions
2890 if (chip->info->ops->mgmt_rsvd2cpu) {
2891 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2897 mutex_unlock(&chip->reg_lock);
2902 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2904 struct mv88e6xxx_chip *chip = ds->priv;
2907 if (!chip->info->ops->set_switch_mac)
2910 mutex_lock(&chip->reg_lock);
2911 err = chip->info->ops->set_switch_mac(chip, addr);
2912 mutex_unlock(&chip->reg_lock);
2917 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2919 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2920 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2924 if (phy >= mv88e6xxx_num_ports(chip))
2927 if (!chip->info->ops->phy_read)
2930 mutex_lock(&chip->reg_lock);
2931 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2932 mutex_unlock(&chip->reg_lock);
2934 return err ? err : val;
2937 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2939 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2940 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2943 if (phy >= mv88e6xxx_num_ports(chip))
2946 if (!chip->info->ops->phy_write)
2949 mutex_lock(&chip->reg_lock);
2950 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2951 mutex_unlock(&chip->reg_lock);
2956 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2957 struct device_node *np,
2961 struct mv88e6xxx_mdio_bus *mdio_bus;
2962 struct mii_bus *bus;
2965 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2969 mdio_bus = bus->priv;
2970 mdio_bus->bus = bus;
2971 mdio_bus->chip = chip;
2972 INIT_LIST_HEAD(&mdio_bus->list);
2973 mdio_bus->external = external;
2976 bus->name = np->full_name;
2977 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2979 bus->name = "mv88e6xxx SMI";
2980 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2983 bus->read = mv88e6xxx_mdio_read;
2984 bus->write = mv88e6xxx_mdio_write;
2985 bus->parent = chip->dev;
2988 err = of_mdiobus_register(bus, np);
2990 err = mdiobus_register(bus);
2992 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2997 list_add_tail(&mdio_bus->list, &chip->mdios);
2999 list_add(&mdio_bus->list, &chip->mdios);
3004 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
3005 { .compatible = "marvell,mv88e6xxx-mdio-external",
3006 .data = (void *)true },
3010 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3011 struct device_node *np)
3013 const struct of_device_id *match;
3014 struct device_node *child;
3017 /* Always register one mdio bus for the internal/default mdio
3018 * bus. This maybe represented in the device tree, but is
3021 child = of_get_child_by_name(np, "mdio");
3022 err = mv88e6xxx_mdio_register(chip, child, false);
3026 /* Walk the device tree, and see if there are any other nodes
3027 * which say they are compatible with the external mdio
3030 for_each_available_child_of_node(np, child) {
3031 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3033 err = mv88e6xxx_mdio_register(chip, child, true);
3042 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3045 struct mv88e6xxx_mdio_bus *mdio_bus;
3046 struct mii_bus *bus;
3048 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3049 bus = mdio_bus->bus;
3051 mdiobus_unregister(bus);
3055 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3057 struct mv88e6xxx_chip *chip = ds->priv;
3059 return chip->eeprom_len;
3062 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3063 struct ethtool_eeprom *eeprom, u8 *data)
3065 struct mv88e6xxx_chip *chip = ds->priv;
3068 if (!chip->info->ops->get_eeprom)
3071 mutex_lock(&chip->reg_lock);
3072 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3073 mutex_unlock(&chip->reg_lock);
3078 eeprom->magic = 0xc3ec4951;
3083 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3084 struct ethtool_eeprom *eeprom, u8 *data)
3086 struct mv88e6xxx_chip *chip = ds->priv;
3089 if (!chip->info->ops->set_eeprom)
3092 if (eeprom->magic != 0xc3ec4951)
3095 mutex_lock(&chip->reg_lock);
3096 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3097 mutex_unlock(&chip->reg_lock);
3102 static const struct mv88e6xxx_ops mv88e6085_ops = {
3103 /* MV88E6XXX_FAMILY_6097 */
3104 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3105 .phy_read = mv88e6xxx_phy_ppu_read,
3106 .phy_write = mv88e6xxx_phy_ppu_write,
3107 .port_set_link = mv88e6xxx_port_set_link,
3108 .port_set_duplex = mv88e6xxx_port_set_duplex,
3109 .port_set_speed = mv88e6185_port_set_speed,
3110 .port_tag_remap = mv88e6095_port_tag_remap,
3111 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3112 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3113 .port_set_ether_type = mv88e6351_port_set_ether_type,
3114 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3115 .port_pause_config = mv88e6097_port_pause_config,
3116 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3117 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3118 .stats_get_strings = mv88e6095_stats_get_strings,
3119 .stats_get_stats = mv88e6095_stats_get_stats,
3120 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3121 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3122 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3123 .ppu_enable = mv88e6185_g1_ppu_enable,
3124 .ppu_disable = mv88e6185_g1_ppu_disable,
3125 .reset = mv88e6185_g1_reset,
3128 static const struct mv88e6xxx_ops mv88e6095_ops = {
3129 /* MV88E6XXX_FAMILY_6095 */
3130 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3131 .phy_read = mv88e6xxx_phy_ppu_read,
3132 .phy_write = mv88e6xxx_phy_ppu_write,
3133 .port_set_link = mv88e6xxx_port_set_link,
3134 .port_set_duplex = mv88e6xxx_port_set_duplex,
3135 .port_set_speed = mv88e6185_port_set_speed,
3136 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3137 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
3138 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3139 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3140 .stats_get_strings = mv88e6095_stats_get_strings,
3141 .stats_get_stats = mv88e6095_stats_get_stats,
3142 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3143 .ppu_enable = mv88e6185_g1_ppu_enable,
3144 .ppu_disable = mv88e6185_g1_ppu_disable,
3145 .reset = mv88e6185_g1_reset,
3148 static const struct mv88e6xxx_ops mv88e6097_ops = {
3149 /* MV88E6XXX_FAMILY_6097 */
3150 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3151 .phy_read = mv88e6xxx_g2_smi_phy_read,
3152 .phy_write = mv88e6xxx_g2_smi_phy_write,
3153 .port_set_link = mv88e6xxx_port_set_link,
3154 .port_set_duplex = mv88e6xxx_port_set_duplex,
3155 .port_set_speed = mv88e6185_port_set_speed,
3156 .port_tag_remap = mv88e6095_port_tag_remap,
3157 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3158 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3159 .port_set_ether_type = mv88e6351_port_set_ether_type,
3160 .port_jumbo_config = mv88e6165_port_jumbo_config,
3161 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3162 .port_pause_config = mv88e6097_port_pause_config,
3163 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3164 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3165 .stats_get_strings = mv88e6095_stats_get_strings,
3166 .stats_get_stats = mv88e6095_stats_get_stats,
3167 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3168 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3169 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3170 .reset = mv88e6352_g1_reset,
3173 static const struct mv88e6xxx_ops mv88e6123_ops = {
3174 /* MV88E6XXX_FAMILY_6165 */
3175 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3176 .phy_read = mv88e6165_phy_read,
3177 .phy_write = mv88e6165_phy_write,
3178 .port_set_link = mv88e6xxx_port_set_link,
3179 .port_set_duplex = mv88e6xxx_port_set_duplex,
3180 .port_set_speed = mv88e6185_port_set_speed,
3181 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3182 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
3183 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3184 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3185 .stats_get_strings = mv88e6095_stats_get_strings,
3186 .stats_get_stats = mv88e6095_stats_get_stats,
3187 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3188 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3189 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3190 .reset = mv88e6352_g1_reset,
3193 static const struct mv88e6xxx_ops mv88e6131_ops = {
3194 /* MV88E6XXX_FAMILY_6185 */
3195 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3196 .phy_read = mv88e6xxx_phy_ppu_read,
3197 .phy_write = mv88e6xxx_phy_ppu_write,
3198 .port_set_link = mv88e6xxx_port_set_link,
3199 .port_set_duplex = mv88e6xxx_port_set_duplex,
3200 .port_set_speed = mv88e6185_port_set_speed,
3201 .port_tag_remap = mv88e6095_port_tag_remap,
3202 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3203 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3204 .port_set_ether_type = mv88e6351_port_set_ether_type,
3205 .port_jumbo_config = mv88e6165_port_jumbo_config,
3206 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3207 .port_pause_config = mv88e6097_port_pause_config,
3208 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3209 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3210 .stats_get_strings = mv88e6095_stats_get_strings,
3211 .stats_get_stats = mv88e6095_stats_get_stats,
3212 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3213 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3214 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3215 .ppu_enable = mv88e6185_g1_ppu_enable,
3216 .ppu_disable = mv88e6185_g1_ppu_disable,
3217 .reset = mv88e6185_g1_reset,
3220 static const struct mv88e6xxx_ops mv88e6161_ops = {
3221 /* MV88E6XXX_FAMILY_6165 */
3222 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3223 .phy_read = mv88e6165_phy_read,
3224 .phy_write = mv88e6165_phy_write,
3225 .port_set_link = mv88e6xxx_port_set_link,
3226 .port_set_duplex = mv88e6xxx_port_set_duplex,
3227 .port_set_speed = mv88e6185_port_set_speed,
3228 .port_tag_remap = mv88e6095_port_tag_remap,
3229 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3230 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3231 .port_set_ether_type = mv88e6351_port_set_ether_type,
3232 .port_jumbo_config = mv88e6165_port_jumbo_config,
3233 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3234 .port_pause_config = mv88e6097_port_pause_config,
3235 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3236 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3237 .stats_get_strings = mv88e6095_stats_get_strings,
3238 .stats_get_stats = mv88e6095_stats_get_stats,
3239 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3240 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3241 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3242 .reset = mv88e6352_g1_reset,
3245 static const struct mv88e6xxx_ops mv88e6165_ops = {
3246 /* MV88E6XXX_FAMILY_6165 */
3247 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3248 .phy_read = mv88e6165_phy_read,
3249 .phy_write = mv88e6165_phy_write,
3250 .port_set_link = mv88e6xxx_port_set_link,
3251 .port_set_duplex = mv88e6xxx_port_set_duplex,
3252 .port_set_speed = mv88e6185_port_set_speed,
3253 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3254 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3255 .stats_get_strings = mv88e6095_stats_get_strings,
3256 .stats_get_stats = mv88e6095_stats_get_stats,
3257 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3258 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3259 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3260 .reset = mv88e6352_g1_reset,
3263 static const struct mv88e6xxx_ops mv88e6171_ops = {
3264 /* MV88E6XXX_FAMILY_6351 */
3265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3266 .phy_read = mv88e6xxx_g2_smi_phy_read,
3267 .phy_write = mv88e6xxx_g2_smi_phy_write,
3268 .port_set_link = mv88e6xxx_port_set_link,
3269 .port_set_duplex = mv88e6xxx_port_set_duplex,
3270 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3271 .port_set_speed = mv88e6185_port_set_speed,
3272 .port_tag_remap = mv88e6095_port_tag_remap,
3273 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3274 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3275 .port_set_ether_type = mv88e6351_port_set_ether_type,
3276 .port_jumbo_config = mv88e6165_port_jumbo_config,
3277 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3278 .port_pause_config = mv88e6097_port_pause_config,
3279 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3280 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3281 .stats_get_strings = mv88e6095_stats_get_strings,
3282 .stats_get_stats = mv88e6095_stats_get_stats,
3283 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3284 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3285 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3286 .reset = mv88e6352_g1_reset,
3289 static const struct mv88e6xxx_ops mv88e6172_ops = {
3290 /* MV88E6XXX_FAMILY_6352 */
3291 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3292 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3293 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3294 .phy_read = mv88e6xxx_g2_smi_phy_read,
3295 .phy_write = mv88e6xxx_g2_smi_phy_write,
3296 .port_set_link = mv88e6xxx_port_set_link,
3297 .port_set_duplex = mv88e6xxx_port_set_duplex,
3298 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3299 .port_set_speed = mv88e6352_port_set_speed,
3300 .port_tag_remap = mv88e6095_port_tag_remap,
3301 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3302 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3303 .port_set_ether_type = mv88e6351_port_set_ether_type,
3304 .port_jumbo_config = mv88e6165_port_jumbo_config,
3305 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3306 .port_pause_config = mv88e6097_port_pause_config,
3307 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3308 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3309 .stats_get_strings = mv88e6095_stats_get_strings,
3310 .stats_get_stats = mv88e6095_stats_get_stats,
3311 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3312 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3313 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3314 .reset = mv88e6352_g1_reset,
3317 static const struct mv88e6xxx_ops mv88e6175_ops = {
3318 /* MV88E6XXX_FAMILY_6351 */
3319 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3320 .phy_read = mv88e6xxx_g2_smi_phy_read,
3321 .phy_write = mv88e6xxx_g2_smi_phy_write,
3322 .port_set_link = mv88e6xxx_port_set_link,
3323 .port_set_duplex = mv88e6xxx_port_set_duplex,
3324 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3325 .port_set_speed = mv88e6185_port_set_speed,
3326 .port_tag_remap = mv88e6095_port_tag_remap,
3327 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3328 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3329 .port_set_ether_type = mv88e6351_port_set_ether_type,
3330 .port_jumbo_config = mv88e6165_port_jumbo_config,
3331 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3332 .port_pause_config = mv88e6097_port_pause_config,
3333 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3334 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3335 .stats_get_strings = mv88e6095_stats_get_strings,
3336 .stats_get_stats = mv88e6095_stats_get_stats,
3337 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3338 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3339 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3340 .reset = mv88e6352_g1_reset,
3343 static const struct mv88e6xxx_ops mv88e6176_ops = {
3344 /* MV88E6XXX_FAMILY_6352 */
3345 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3346 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3347 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3348 .phy_read = mv88e6xxx_g2_smi_phy_read,
3349 .phy_write = mv88e6xxx_g2_smi_phy_write,
3350 .port_set_link = mv88e6xxx_port_set_link,
3351 .port_set_duplex = mv88e6xxx_port_set_duplex,
3352 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3353 .port_set_speed = mv88e6352_port_set_speed,
3354 .port_tag_remap = mv88e6095_port_tag_remap,
3355 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3356 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3357 .port_set_ether_type = mv88e6351_port_set_ether_type,
3358 .port_jumbo_config = mv88e6165_port_jumbo_config,
3359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3360 .port_pause_config = mv88e6097_port_pause_config,
3361 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3362 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3363 .stats_get_strings = mv88e6095_stats_get_strings,
3364 .stats_get_stats = mv88e6095_stats_get_stats,
3365 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3366 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3367 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3368 .reset = mv88e6352_g1_reset,
3371 static const struct mv88e6xxx_ops mv88e6185_ops = {
3372 /* MV88E6XXX_FAMILY_6185 */
3373 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3374 .phy_read = mv88e6xxx_phy_ppu_read,
3375 .phy_write = mv88e6xxx_phy_ppu_write,
3376 .port_set_link = mv88e6xxx_port_set_link,
3377 .port_set_duplex = mv88e6xxx_port_set_duplex,
3378 .port_set_speed = mv88e6185_port_set_speed,
3379 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3380 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
3381 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3382 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3383 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3384 .stats_get_strings = mv88e6095_stats_get_strings,
3385 .stats_get_stats = mv88e6095_stats_get_stats,
3386 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3387 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3388 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3389 .ppu_enable = mv88e6185_g1_ppu_enable,
3390 .ppu_disable = mv88e6185_g1_ppu_disable,
3391 .reset = mv88e6185_g1_reset,
3394 static const struct mv88e6xxx_ops mv88e6190_ops = {
3395 /* MV88E6XXX_FAMILY_6390 */
3396 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3397 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3398 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3399 .phy_read = mv88e6xxx_g2_smi_phy_read,
3400 .phy_write = mv88e6xxx_g2_smi_phy_write,
3401 .port_set_link = mv88e6xxx_port_set_link,
3402 .port_set_duplex = mv88e6xxx_port_set_duplex,
3403 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3404 .port_set_speed = mv88e6390_port_set_speed,
3405 .port_tag_remap = mv88e6390_port_tag_remap,
3406 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3407 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3408 .port_set_ether_type = mv88e6351_port_set_ether_type,
3409 .port_pause_config = mv88e6390_port_pause_config,
3410 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3411 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3412 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3413 .stats_get_strings = mv88e6320_stats_get_strings,
3414 .stats_get_stats = mv88e6390_stats_get_stats,
3415 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3416 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3417 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3418 .reset = mv88e6352_g1_reset,
3421 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3422 /* MV88E6XXX_FAMILY_6390 */
3423 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3424 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3425 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3426 .phy_read = mv88e6xxx_g2_smi_phy_read,
3427 .phy_write = mv88e6xxx_g2_smi_phy_write,
3428 .port_set_link = mv88e6xxx_port_set_link,
3429 .port_set_duplex = mv88e6xxx_port_set_duplex,
3430 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3431 .port_set_speed = mv88e6390x_port_set_speed,
3432 .port_tag_remap = mv88e6390_port_tag_remap,
3433 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3434 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3435 .port_set_ether_type = mv88e6351_port_set_ether_type,
3436 .port_pause_config = mv88e6390_port_pause_config,
3437 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3438 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3439 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3440 .stats_get_strings = mv88e6320_stats_get_strings,
3441 .stats_get_stats = mv88e6390_stats_get_stats,
3442 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3443 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3444 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3445 .reset = mv88e6352_g1_reset,
3448 static const struct mv88e6xxx_ops mv88e6191_ops = {
3449 /* MV88E6XXX_FAMILY_6390 */
3450 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3451 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3452 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3453 .phy_read = mv88e6xxx_g2_smi_phy_read,
3454 .phy_write = mv88e6xxx_g2_smi_phy_write,
3455 .port_set_link = mv88e6xxx_port_set_link,
3456 .port_set_duplex = mv88e6xxx_port_set_duplex,
3457 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3458 .port_set_speed = mv88e6390_port_set_speed,
3459 .port_tag_remap = mv88e6390_port_tag_remap,
3460 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3461 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3462 .port_set_ether_type = mv88e6351_port_set_ether_type,
3463 .port_pause_config = mv88e6390_port_pause_config,
3464 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3465 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3466 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3467 .stats_get_strings = mv88e6320_stats_get_strings,
3468 .stats_get_stats = mv88e6390_stats_get_stats,
3469 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3470 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3471 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3472 .reset = mv88e6352_g1_reset,
3475 static const struct mv88e6xxx_ops mv88e6240_ops = {
3476 /* MV88E6XXX_FAMILY_6352 */
3477 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3478 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3479 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3480 .phy_read = mv88e6xxx_g2_smi_phy_read,
3481 .phy_write = mv88e6xxx_g2_smi_phy_write,
3482 .port_set_link = mv88e6xxx_port_set_link,
3483 .port_set_duplex = mv88e6xxx_port_set_duplex,
3484 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3485 .port_set_speed = mv88e6352_port_set_speed,
3486 .port_tag_remap = mv88e6095_port_tag_remap,
3487 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3488 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3489 .port_set_ether_type = mv88e6351_port_set_ether_type,
3490 .port_jumbo_config = mv88e6165_port_jumbo_config,
3491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3492 .port_pause_config = mv88e6097_port_pause_config,
3493 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3494 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3495 .stats_get_strings = mv88e6095_stats_get_strings,
3496 .stats_get_stats = mv88e6095_stats_get_stats,
3497 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3498 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3499 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3500 .reset = mv88e6352_g1_reset,
3503 static const struct mv88e6xxx_ops mv88e6290_ops = {
3504 /* MV88E6XXX_FAMILY_6390 */
3505 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3506 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3508 .phy_read = mv88e6xxx_g2_smi_phy_read,
3509 .phy_write = mv88e6xxx_g2_smi_phy_write,
3510 .port_set_link = mv88e6xxx_port_set_link,
3511 .port_set_duplex = mv88e6xxx_port_set_duplex,
3512 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3513 .port_set_speed = mv88e6390_port_set_speed,
3514 .port_tag_remap = mv88e6390_port_tag_remap,
3515 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3516 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3517 .port_set_ether_type = mv88e6351_port_set_ether_type,
3518 .port_pause_config = mv88e6390_port_pause_config,
3519 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3520 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3521 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3522 .stats_get_strings = mv88e6320_stats_get_strings,
3523 .stats_get_stats = mv88e6390_stats_get_stats,
3524 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3525 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3526 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3527 .reset = mv88e6352_g1_reset,
3530 static const struct mv88e6xxx_ops mv88e6320_ops = {
3531 /* MV88E6XXX_FAMILY_6320 */
3532 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3533 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3534 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3535 .phy_read = mv88e6xxx_g2_smi_phy_read,
3536 .phy_write = mv88e6xxx_g2_smi_phy_write,
3537 .port_set_link = mv88e6xxx_port_set_link,
3538 .port_set_duplex = mv88e6xxx_port_set_duplex,
3539 .port_set_speed = mv88e6185_port_set_speed,
3540 .port_tag_remap = mv88e6095_port_tag_remap,
3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3543 .port_set_ether_type = mv88e6351_port_set_ether_type,
3544 .port_jumbo_config = mv88e6165_port_jumbo_config,
3545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3546 .port_pause_config = mv88e6097_port_pause_config,
3547 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3548 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3549 .stats_get_strings = mv88e6320_stats_get_strings,
3550 .stats_get_stats = mv88e6320_stats_get_stats,
3551 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3552 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3553 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3554 .reset = mv88e6352_g1_reset,
3557 static const struct mv88e6xxx_ops mv88e6321_ops = {
3558 /* MV88E6XXX_FAMILY_6321 */
3559 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3560 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3561 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3562 .phy_read = mv88e6xxx_g2_smi_phy_read,
3563 .phy_write = mv88e6xxx_g2_smi_phy_write,
3564 .port_set_link = mv88e6xxx_port_set_link,
3565 .port_set_duplex = mv88e6xxx_port_set_duplex,
3566 .port_set_speed = mv88e6185_port_set_speed,
3567 .port_tag_remap = mv88e6095_port_tag_remap,
3568 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3569 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3570 .port_set_ether_type = mv88e6351_port_set_ether_type,
3571 .port_jumbo_config = mv88e6165_port_jumbo_config,
3572 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3573 .port_pause_config = mv88e6097_port_pause_config,
3574 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3575 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3576 .stats_get_strings = mv88e6320_stats_get_strings,
3577 .stats_get_stats = mv88e6320_stats_get_stats,
3578 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3579 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3580 .reset = mv88e6352_g1_reset,
3583 static const struct mv88e6xxx_ops mv88e6350_ops = {
3584 /* MV88E6XXX_FAMILY_6351 */
3585 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3586 .phy_read = mv88e6xxx_g2_smi_phy_read,
3587 .phy_write = mv88e6xxx_g2_smi_phy_write,
3588 .port_set_link = mv88e6xxx_port_set_link,
3589 .port_set_duplex = mv88e6xxx_port_set_duplex,
3590 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3591 .port_set_speed = mv88e6185_port_set_speed,
3592 .port_tag_remap = mv88e6095_port_tag_remap,
3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3594 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3595 .port_set_ether_type = mv88e6351_port_set_ether_type,
3596 .port_jumbo_config = mv88e6165_port_jumbo_config,
3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3598 .port_pause_config = mv88e6097_port_pause_config,
3599 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3600 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3601 .stats_get_strings = mv88e6095_stats_get_strings,
3602 .stats_get_stats = mv88e6095_stats_get_stats,
3603 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3604 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3605 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3606 .reset = mv88e6352_g1_reset,
3609 static const struct mv88e6xxx_ops mv88e6351_ops = {
3610 /* MV88E6XXX_FAMILY_6351 */
3611 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3612 .phy_read = mv88e6xxx_g2_smi_phy_read,
3613 .phy_write = mv88e6xxx_g2_smi_phy_write,
3614 .port_set_link = mv88e6xxx_port_set_link,
3615 .port_set_duplex = mv88e6xxx_port_set_duplex,
3616 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3617 .port_set_speed = mv88e6185_port_set_speed,
3618 .port_tag_remap = mv88e6095_port_tag_remap,
3619 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3620 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3621 .port_set_ether_type = mv88e6351_port_set_ether_type,
3622 .port_jumbo_config = mv88e6165_port_jumbo_config,
3623 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3624 .port_pause_config = mv88e6097_port_pause_config,
3625 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3626 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3627 .stats_get_strings = mv88e6095_stats_get_strings,
3628 .stats_get_stats = mv88e6095_stats_get_stats,
3629 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3630 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3631 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3632 .reset = mv88e6352_g1_reset,
3635 static const struct mv88e6xxx_ops mv88e6352_ops = {
3636 /* MV88E6XXX_FAMILY_6352 */
3637 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3638 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3639 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3640 .phy_read = mv88e6xxx_g2_smi_phy_read,
3641 .phy_write = mv88e6xxx_g2_smi_phy_write,
3642 .port_set_link = mv88e6xxx_port_set_link,
3643 .port_set_duplex = mv88e6xxx_port_set_duplex,
3644 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3645 .port_set_speed = mv88e6352_port_set_speed,
3646 .port_tag_remap = mv88e6095_port_tag_remap,
3647 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3648 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3649 .port_set_ether_type = mv88e6351_port_set_ether_type,
3650 .port_jumbo_config = mv88e6165_port_jumbo_config,
3651 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3652 .port_pause_config = mv88e6097_port_pause_config,
3653 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3654 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3655 .stats_get_strings = mv88e6095_stats_get_strings,
3656 .stats_get_stats = mv88e6095_stats_get_stats,
3657 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3658 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3659 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3660 .reset = mv88e6352_g1_reset,
3663 static const struct mv88e6xxx_ops mv88e6390_ops = {
3664 /* MV88E6XXX_FAMILY_6390 */
3665 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3666 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3667 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3668 .phy_read = mv88e6xxx_g2_smi_phy_read,
3669 .phy_write = mv88e6xxx_g2_smi_phy_write,
3670 .port_set_link = mv88e6xxx_port_set_link,
3671 .port_set_duplex = mv88e6xxx_port_set_duplex,
3672 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3673 .port_set_speed = mv88e6390_port_set_speed,
3674 .port_tag_remap = mv88e6390_port_tag_remap,
3675 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3676 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3677 .port_set_ether_type = mv88e6351_port_set_ether_type,
3678 .port_jumbo_config = mv88e6165_port_jumbo_config,
3679 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3680 .port_pause_config = mv88e6390_port_pause_config,
3681 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3682 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3683 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3684 .stats_get_strings = mv88e6320_stats_get_strings,
3685 .stats_get_stats = mv88e6390_stats_get_stats,
3686 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3687 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3688 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3689 .reset = mv88e6352_g1_reset,
3692 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3693 /* MV88E6XXX_FAMILY_6390 */
3694 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3695 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3696 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3697 .phy_read = mv88e6xxx_g2_smi_phy_read,
3698 .phy_write = mv88e6xxx_g2_smi_phy_write,
3699 .port_set_link = mv88e6xxx_port_set_link,
3700 .port_set_duplex = mv88e6xxx_port_set_duplex,
3701 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3702 .port_set_speed = mv88e6390x_port_set_speed,
3703 .port_tag_remap = mv88e6390_port_tag_remap,
3704 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3705 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3706 .port_set_ether_type = mv88e6351_port_set_ether_type,
3707 .port_jumbo_config = mv88e6165_port_jumbo_config,
3708 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3709 .port_pause_config = mv88e6390_port_pause_config,
3710 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3711 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3712 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3713 .stats_get_strings = mv88e6320_stats_get_strings,
3714 .stats_get_stats = mv88e6390_stats_get_stats,
3715 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3716 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3717 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3718 .reset = mv88e6352_g1_reset,
3721 static const struct mv88e6xxx_ops mv88e6391_ops = {
3722 /* MV88E6XXX_FAMILY_6390 */
3723 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3724 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3726 .phy_read = mv88e6xxx_g2_smi_phy_read,
3727 .phy_write = mv88e6xxx_g2_smi_phy_write,
3728 .port_set_link = mv88e6xxx_port_set_link,
3729 .port_set_duplex = mv88e6xxx_port_set_duplex,
3730 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3731 .port_set_speed = mv88e6390_port_set_speed,
3732 .port_tag_remap = mv88e6390_port_tag_remap,
3733 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3734 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3735 .port_set_ether_type = mv88e6351_port_set_ether_type,
3736 .port_pause_config = mv88e6390_port_pause_config,
3737 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3738 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3739 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3740 .stats_get_strings = mv88e6320_stats_get_strings,
3741 .stats_get_stats = mv88e6390_stats_get_stats,
3742 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3743 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3744 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3745 .reset = mv88e6352_g1_reset,
3748 static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3749 const struct mv88e6xxx_ops *ops)
3751 if (!ops->port_set_frame_mode) {
3752 dev_err(chip->dev, "Missing port_set_frame_mode");
3756 if (!ops->port_set_egress_unknowns) {
3757 dev_err(chip->dev, "Missing port_set_egress_mode");
3764 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3766 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3767 .family = MV88E6XXX_FAMILY_6097,
3768 .name = "Marvell 88E6085",
3769 .num_databases = 4096,
3771 .port_base_addr = 0x10,
3772 .global1_addr = 0x1b,
3773 .age_time_coeff = 15000,
3775 .tag_protocol = DSA_TAG_PROTO_DSA,
3776 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3777 .ops = &mv88e6085_ops,
3781 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3782 .family = MV88E6XXX_FAMILY_6095,
3783 .name = "Marvell 88E6095/88E6095F",
3784 .num_databases = 256,
3786 .port_base_addr = 0x10,
3787 .global1_addr = 0x1b,
3788 .age_time_coeff = 15000,
3790 .tag_protocol = DSA_TAG_PROTO_DSA,
3791 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3792 .ops = &mv88e6095_ops,
3796 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3797 .family = MV88E6XXX_FAMILY_6097,
3798 .name = "Marvell 88E6097/88E6097F",
3799 .num_databases = 4096,
3801 .port_base_addr = 0x10,
3802 .global1_addr = 0x1b,
3803 .age_time_coeff = 15000,
3805 .tag_protocol = DSA_TAG_PROTO_EDSA,
3806 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3807 .ops = &mv88e6097_ops,
3811 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3812 .family = MV88E6XXX_FAMILY_6165,
3813 .name = "Marvell 88E6123",
3814 .num_databases = 4096,
3816 .port_base_addr = 0x10,
3817 .global1_addr = 0x1b,
3818 .age_time_coeff = 15000,
3820 .tag_protocol = DSA_TAG_PROTO_DSA,
3821 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3822 .ops = &mv88e6123_ops,
3826 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3827 .family = MV88E6XXX_FAMILY_6185,
3828 .name = "Marvell 88E6131",
3829 .num_databases = 256,
3831 .port_base_addr = 0x10,
3832 .global1_addr = 0x1b,
3833 .age_time_coeff = 15000,
3835 .tag_protocol = DSA_TAG_PROTO_DSA,
3836 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3837 .ops = &mv88e6131_ops,
3841 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3842 .family = MV88E6XXX_FAMILY_6165,
3843 .name = "Marvell 88E6161",
3844 .num_databases = 4096,
3846 .port_base_addr = 0x10,
3847 .global1_addr = 0x1b,
3848 .age_time_coeff = 15000,
3850 .tag_protocol = DSA_TAG_PROTO_DSA,
3851 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3852 .ops = &mv88e6161_ops,
3856 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3857 .family = MV88E6XXX_FAMILY_6165,
3858 .name = "Marvell 88E6165",
3859 .num_databases = 4096,
3861 .port_base_addr = 0x10,
3862 .global1_addr = 0x1b,
3863 .age_time_coeff = 15000,
3865 .tag_protocol = DSA_TAG_PROTO_DSA,
3866 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3867 .ops = &mv88e6165_ops,
3871 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3872 .family = MV88E6XXX_FAMILY_6351,
3873 .name = "Marvell 88E6171",
3874 .num_databases = 4096,
3876 .port_base_addr = 0x10,
3877 .global1_addr = 0x1b,
3878 .age_time_coeff = 15000,
3880 .tag_protocol = DSA_TAG_PROTO_EDSA,
3881 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3882 .ops = &mv88e6171_ops,
3886 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3887 .family = MV88E6XXX_FAMILY_6352,
3888 .name = "Marvell 88E6172",
3889 .num_databases = 4096,
3891 .port_base_addr = 0x10,
3892 .global1_addr = 0x1b,
3893 .age_time_coeff = 15000,
3895 .tag_protocol = DSA_TAG_PROTO_EDSA,
3896 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3897 .ops = &mv88e6172_ops,
3901 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3902 .family = MV88E6XXX_FAMILY_6351,
3903 .name = "Marvell 88E6175",
3904 .num_databases = 4096,
3906 .port_base_addr = 0x10,
3907 .global1_addr = 0x1b,
3908 .age_time_coeff = 15000,
3910 .tag_protocol = DSA_TAG_PROTO_EDSA,
3911 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3912 .ops = &mv88e6175_ops,
3916 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3917 .family = MV88E6XXX_FAMILY_6352,
3918 .name = "Marvell 88E6176",
3919 .num_databases = 4096,
3921 .port_base_addr = 0x10,
3922 .global1_addr = 0x1b,
3923 .age_time_coeff = 15000,
3925 .tag_protocol = DSA_TAG_PROTO_EDSA,
3926 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3927 .ops = &mv88e6176_ops,
3931 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3932 .family = MV88E6XXX_FAMILY_6185,
3933 .name = "Marvell 88E6185",
3934 .num_databases = 256,
3936 .port_base_addr = 0x10,
3937 .global1_addr = 0x1b,
3938 .age_time_coeff = 15000,
3940 .tag_protocol = DSA_TAG_PROTO_EDSA,
3941 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3942 .ops = &mv88e6185_ops,
3946 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3947 .family = MV88E6XXX_FAMILY_6390,
3948 .name = "Marvell 88E6190",
3949 .num_databases = 4096,
3950 .num_ports = 11, /* 10 + Z80 */
3951 .port_base_addr = 0x0,
3952 .global1_addr = 0x1b,
3953 .tag_protocol = DSA_TAG_PROTO_DSA,
3954 .age_time_coeff = 15000,
3956 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3957 .ops = &mv88e6190_ops,
3961 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3962 .family = MV88E6XXX_FAMILY_6390,
3963 .name = "Marvell 88E6190X",
3964 .num_databases = 4096,
3965 .num_ports = 11, /* 10 + Z80 */
3966 .port_base_addr = 0x0,
3967 .global1_addr = 0x1b,
3968 .age_time_coeff = 15000,
3970 .tag_protocol = DSA_TAG_PROTO_DSA,
3971 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3972 .ops = &mv88e6190x_ops,
3976 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3977 .family = MV88E6XXX_FAMILY_6390,
3978 .name = "Marvell 88E6191",
3979 .num_databases = 4096,
3980 .num_ports = 11, /* 10 + Z80 */
3981 .port_base_addr = 0x0,
3982 .global1_addr = 0x1b,
3983 .age_time_coeff = 15000,
3985 .tag_protocol = DSA_TAG_PROTO_DSA,
3986 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3987 .ops = &mv88e6391_ops,
3991 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3992 .family = MV88E6XXX_FAMILY_6352,
3993 .name = "Marvell 88E6240",
3994 .num_databases = 4096,
3996 .port_base_addr = 0x10,
3997 .global1_addr = 0x1b,
3998 .age_time_coeff = 15000,
4000 .tag_protocol = DSA_TAG_PROTO_EDSA,
4001 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
4002 .ops = &mv88e6240_ops,
4006 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4007 .family = MV88E6XXX_FAMILY_6390,
4008 .name = "Marvell 88E6290",
4009 .num_databases = 4096,
4010 .num_ports = 11, /* 10 + Z80 */
4011 .port_base_addr = 0x0,
4012 .global1_addr = 0x1b,
4013 .age_time_coeff = 15000,
4015 .tag_protocol = DSA_TAG_PROTO_DSA,
4016 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4017 .ops = &mv88e6290_ops,
4021 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4022 .family = MV88E6XXX_FAMILY_6320,
4023 .name = "Marvell 88E6320",
4024 .num_databases = 4096,
4026 .port_base_addr = 0x10,
4027 .global1_addr = 0x1b,
4028 .age_time_coeff = 15000,
4030 .tag_protocol = DSA_TAG_PROTO_EDSA,
4031 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
4032 .ops = &mv88e6320_ops,
4036 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4037 .family = MV88E6XXX_FAMILY_6320,
4038 .name = "Marvell 88E6321",
4039 .num_databases = 4096,
4041 .port_base_addr = 0x10,
4042 .global1_addr = 0x1b,
4043 .age_time_coeff = 15000,
4045 .tag_protocol = DSA_TAG_PROTO_EDSA,
4046 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
4047 .ops = &mv88e6321_ops,
4051 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4052 .family = MV88E6XXX_FAMILY_6351,
4053 .name = "Marvell 88E6350",
4054 .num_databases = 4096,
4056 .port_base_addr = 0x10,
4057 .global1_addr = 0x1b,
4058 .age_time_coeff = 15000,
4060 .tag_protocol = DSA_TAG_PROTO_EDSA,
4061 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4062 .ops = &mv88e6350_ops,
4066 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4067 .family = MV88E6XXX_FAMILY_6351,
4068 .name = "Marvell 88E6351",
4069 .num_databases = 4096,
4071 .port_base_addr = 0x10,
4072 .global1_addr = 0x1b,
4073 .age_time_coeff = 15000,
4075 .tag_protocol = DSA_TAG_PROTO_EDSA,
4076 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4077 .ops = &mv88e6351_ops,
4081 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4082 .family = MV88E6XXX_FAMILY_6352,
4083 .name = "Marvell 88E6352",
4084 .num_databases = 4096,
4086 .port_base_addr = 0x10,
4087 .global1_addr = 0x1b,
4088 .age_time_coeff = 15000,
4090 .tag_protocol = DSA_TAG_PROTO_EDSA,
4091 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
4092 .ops = &mv88e6352_ops,
4095 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4096 .family = MV88E6XXX_FAMILY_6390,
4097 .name = "Marvell 88E6390",
4098 .num_databases = 4096,
4099 .num_ports = 11, /* 10 + Z80 */
4100 .port_base_addr = 0x0,
4101 .global1_addr = 0x1b,
4102 .age_time_coeff = 15000,
4104 .tag_protocol = DSA_TAG_PROTO_DSA,
4105 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4106 .ops = &mv88e6390_ops,
4109 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4110 .family = MV88E6XXX_FAMILY_6390,
4111 .name = "Marvell 88E6390X",
4112 .num_databases = 4096,
4113 .num_ports = 11, /* 10 + Z80 */
4114 .port_base_addr = 0x0,
4115 .global1_addr = 0x1b,
4116 .age_time_coeff = 15000,
4118 .tag_protocol = DSA_TAG_PROTO_DSA,
4119 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4120 .ops = &mv88e6390x_ops,
4124 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4128 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4129 if (mv88e6xxx_table[i].prod_num == prod_num)
4130 return &mv88e6xxx_table[i];
4135 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4137 const struct mv88e6xxx_info *info;
4138 unsigned int prod_num, rev;
4142 mutex_lock(&chip->reg_lock);
4143 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4144 mutex_unlock(&chip->reg_lock);
4148 prod_num = (id & 0xfff0) >> 4;
4151 info = mv88e6xxx_lookup_info(prod_num);
4155 /* Update the compatible info with the probed one */
4158 err = mv88e6xxx_g2_require(chip);
4162 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4163 chip->info->prod_num, chip->info->name, rev);
4168 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4170 struct mv88e6xxx_chip *chip;
4172 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4178 mutex_init(&chip->reg_lock);
4179 INIT_LIST_HEAD(&chip->mdios);
4184 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4186 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4187 mv88e6xxx_ppu_state_init(chip);
4190 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4192 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4193 mv88e6xxx_ppu_state_destroy(chip);
4196 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4197 struct mii_bus *bus, int sw_addr)
4200 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4201 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
4202 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4207 chip->sw_addr = sw_addr;
4212 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4214 struct mv88e6xxx_chip *chip = ds->priv;
4216 return chip->info->tag_protocol;
4219 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4220 struct device *host_dev, int sw_addr,
4223 struct mv88e6xxx_chip *chip;
4224 struct mii_bus *bus;
4227 bus = dsa_host_dev_to_mii_bus(host_dev);
4231 chip = mv88e6xxx_alloc_chip(dsa_dev);
4235 /* Legacy SMI probing will only support chips similar to 88E6085 */
4236 chip->info = &mv88e6xxx_table[MV88E6085];
4238 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4242 err = mv88e6xxx_detect(chip);
4246 mutex_lock(&chip->reg_lock);
4247 err = mv88e6xxx_switch_reset(chip);
4248 mutex_unlock(&chip->reg_lock);
4252 mv88e6xxx_phy_init(chip);
4254 err = mv88e6xxx_mdios_register(chip, NULL);
4260 return chip->info->name;
4262 devm_kfree(dsa_dev, chip);
4267 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4268 const struct switchdev_obj_port_mdb *mdb,
4269 struct switchdev_trans *trans)
4271 /* We don't need any dynamic resource from the kernel (yet),
4272 * so skip the prepare phase.
4278 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4279 const struct switchdev_obj_port_mdb *mdb,
4280 struct switchdev_trans *trans)
4282 struct mv88e6xxx_chip *chip = ds->priv;
4284 mutex_lock(&chip->reg_lock);
4285 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4286 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4287 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4288 mutex_unlock(&chip->reg_lock);
4291 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4292 const struct switchdev_obj_port_mdb *mdb)
4294 struct mv88e6xxx_chip *chip = ds->priv;
4297 mutex_lock(&chip->reg_lock);
4298 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4299 GLOBAL_ATU_DATA_STATE_UNUSED);
4300 mutex_unlock(&chip->reg_lock);
4305 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4306 struct switchdev_obj_port_mdb *mdb,
4307 int (*cb)(struct switchdev_obj *obj))
4309 struct mv88e6xxx_chip *chip = ds->priv;
4312 mutex_lock(&chip->reg_lock);
4313 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4314 mutex_unlock(&chip->reg_lock);
4319 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4320 .probe = mv88e6xxx_drv_probe,
4321 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4322 .setup = mv88e6xxx_setup,
4323 .set_addr = mv88e6xxx_set_addr,
4324 .adjust_link = mv88e6xxx_adjust_link,
4325 .get_strings = mv88e6xxx_get_strings,
4326 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4327 .get_sset_count = mv88e6xxx_get_sset_count,
4328 .set_eee = mv88e6xxx_set_eee,
4329 .get_eee = mv88e6xxx_get_eee,
4330 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4331 .get_eeprom = mv88e6xxx_get_eeprom,
4332 .set_eeprom = mv88e6xxx_set_eeprom,
4333 .get_regs_len = mv88e6xxx_get_regs_len,
4334 .get_regs = mv88e6xxx_get_regs,
4335 .set_ageing_time = mv88e6xxx_set_ageing_time,
4336 .port_bridge_join = mv88e6xxx_port_bridge_join,
4337 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4338 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4339 .port_fast_age = mv88e6xxx_port_fast_age,
4340 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4341 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4342 .port_vlan_add = mv88e6xxx_port_vlan_add,
4343 .port_vlan_del = mv88e6xxx_port_vlan_del,
4344 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4345 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4346 .port_fdb_add = mv88e6xxx_port_fdb_add,
4347 .port_fdb_del = mv88e6xxx_port_fdb_del,
4348 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4349 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4350 .port_mdb_add = mv88e6xxx_port_mdb_add,
4351 .port_mdb_del = mv88e6xxx_port_mdb_del,
4352 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4355 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4356 .ops = &mv88e6xxx_switch_ops,
4359 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4360 struct device_node *np)
4362 struct device *dev = chip->dev;
4363 struct dsa_switch *ds;
4365 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4371 ds->ops = &mv88e6xxx_switch_ops;
4373 dev_set_drvdata(dev, ds);
4375 return dsa_register_switch(ds, np);
4378 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4380 dsa_unregister_switch(chip->ds);
4383 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4385 struct device *dev = &mdiodev->dev;
4386 struct device_node *np = dev->of_node;
4387 const struct mv88e6xxx_info *compat_info;
4388 struct mv88e6xxx_chip *chip;
4392 compat_info = of_device_get_match_data(dev);
4396 chip = mv88e6xxx_alloc_chip(dev);
4400 chip->info = compat_info;
4402 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4406 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4410 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4411 if (IS_ERR(chip->reset))
4412 return PTR_ERR(chip->reset);
4414 err = mv88e6xxx_detect(chip);
4418 mv88e6xxx_phy_init(chip);
4420 if (chip->info->ops->get_eeprom &&
4421 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4422 chip->eeprom_len = eeprom_len;
4424 mutex_lock(&chip->reg_lock);
4425 err = mv88e6xxx_switch_reset(chip);
4426 mutex_unlock(&chip->reg_lock);
4430 chip->irq = of_irq_get(np, 0);
4431 if (chip->irq == -EPROBE_DEFER) {
4436 if (chip->irq > 0) {
4437 /* Has to be performed before the MDIO bus is created,
4438 * because the PHYs will link there interrupts to these
4439 * interrupt controllers
4441 mutex_lock(&chip->reg_lock);
4442 err = mv88e6xxx_g1_irq_setup(chip);
4443 mutex_unlock(&chip->reg_lock);
4448 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4449 err = mv88e6xxx_g2_irq_setup(chip);
4455 err = mv88e6xxx_mdios_register(chip, np);
4459 err = mv88e6xxx_register_switch(chip, np);
4466 mv88e6xxx_mdios_unregister(chip);
4468 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4469 mv88e6xxx_g2_irq_free(chip);
4471 if (chip->irq > 0) {
4472 mutex_lock(&chip->reg_lock);
4473 mv88e6xxx_g1_irq_free(chip);
4474 mutex_unlock(&chip->reg_lock);
4480 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4482 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4483 struct mv88e6xxx_chip *chip = ds->priv;
4485 mv88e6xxx_phy_destroy(chip);
4486 mv88e6xxx_unregister_switch(chip);
4487 mv88e6xxx_mdios_unregister(chip);
4489 if (chip->irq > 0) {
4490 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4491 mv88e6xxx_g2_irq_free(chip);
4492 mv88e6xxx_g1_irq_free(chip);
4496 static const struct of_device_id mv88e6xxx_of_match[] = {
4498 .compatible = "marvell,mv88e6085",
4499 .data = &mv88e6xxx_table[MV88E6085],
4502 .compatible = "marvell,mv88e6190",
4503 .data = &mv88e6xxx_table[MV88E6190],
4508 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4510 static struct mdio_driver mv88e6xxx_driver = {
4511 .probe = mv88e6xxx_probe,
4512 .remove = mv88e6xxx_remove,
4514 .name = "mv88e6085",
4515 .of_match_table = mv88e6xxx_of_match,
4519 static int __init mv88e6xxx_init(void)
4521 register_switch_driver(&mv88e6xxx_switch_drv);
4522 return mdio_driver_register(&mv88e6xxx_driver);
4524 module_init(mv88e6xxx_init);
4526 static void __exit mv88e6xxx_cleanup(void)
4528 mdio_driver_unregister(&mv88e6xxx_driver);
4529 unregister_switch_driver(&mv88e6xxx_switch_drv);
4531 module_exit(mv88e6xxx_cleanup);
4533 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4534 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4535 MODULE_LICENSE("GPL");