2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
35 #include <net/switchdev.h>
37 #include "mv88e6xxx.h"
42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
63 int addr, int reg, u16 *val)
68 return chip->smi_ops->read(chip, addr, reg, val);
71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
72 int addr, int reg, u16 val)
77 return chip->smi_ops->write(chip, addr, reg, val);
80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
81 int addr, int reg, u16 *val)
85 ret = mdiobus_read_nested(chip->bus, addr, reg);
94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
95 int addr, int reg, u16 val)
99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
116 for (i = 0; i < 16; i++) {
117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
121 if ((ret & SMI_CMD_BUSY) == 0)
128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
129 int addr, int reg, u16 *val)
133 /* Wait for the bus to become free. */
134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
138 /* Transmit the read command. */
139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
144 /* Wait for the read command to complete. */
145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
160 int addr, int reg, u16 val)
164 /* Wait for the bus to become free. */
165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
169 /* Transmit the data to write. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
174 /* Transmit the write command. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
180 /* Wait for the write command to complete. */
181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
197 assert_reg_lock(chip);
199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
213 assert_reg_lock(chip);
215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
228 int addr = phy; /* PHY devices addresses start at 0x0 */
230 if (!chip->info->ops->phy_read)
233 return chip->info->ops->phy_read(chip, addr, reg, val);
236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
239 int addr = phy; /* PHY devices addresses start at 0x0 */
241 if (!chip->info->ops->phy_write)
244 return chip->info->ops->phy_write(chip, addr, reg, val);
247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
272 /* There is no paging for registers 22 */
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
290 /* There is no paging for registers 22 */
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
320 chip->g1_irq.masked |= (1 << n);
323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
328 chip->g1_irq.masked &= ~(1 << n);
331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
342 mutex_unlock(&chip->reg_lock);
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
362 mutex_lock(&chip->reg_lock);
365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
377 reg |= (~chip->g1_irq.masked & mask);
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
384 mutex_unlock(&chip->reg_lock);
387 static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
397 irq_hw_number_t hwirq)
399 struct mv88e6xxx_chip *chip = d->host_data;
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
422 free_irq(chip->irq, chip);
424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
426 irq_dispose_mapping(virq);
429 irq_domain_remove(chip->g1_irq.domain);
432 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
484 irq_domain_remove(chip->g1_irq.domain);
489 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
493 for (i = 0; i < 16; i++) {
497 err = mv88e6xxx_read(chip, addr, reg, &val);
504 usleep_range(1000, 2000);
507 dev_err(chip->dev, "Timeout while waiting for switch\n");
511 /* Indirect write to single pointer-data register with an Update bit */
512 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
517 /* Wait until the previous operation is completed */
518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
525 return mv88e6xxx_write(chip, addr, reg, val);
528 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
533 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
537 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
538 val & ~GLOBAL_CONTROL_PPU_ENABLE);
542 for (i = 0; i < 16; i++) {
543 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
547 usleep_range(1000, 2000);
548 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
555 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
560 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
564 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
565 val | GLOBAL_CONTROL_PPU_ENABLE);
569 for (i = 0; i < 16; i++) {
570 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
574 usleep_range(1000, 2000);
575 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
582 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
584 struct mv88e6xxx_chip *chip;
586 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
588 mutex_lock(&chip->reg_lock);
590 if (mutex_trylock(&chip->ppu_mutex)) {
591 if (mv88e6xxx_ppu_enable(chip) == 0)
592 chip->ppu_disabled = 0;
593 mutex_unlock(&chip->ppu_mutex);
596 mutex_unlock(&chip->reg_lock);
599 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
601 struct mv88e6xxx_chip *chip = (void *)_ps;
603 schedule_work(&chip->ppu_work);
606 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
610 mutex_lock(&chip->ppu_mutex);
612 /* If the PHY polling unit is enabled, disable it so that
613 * we can access the PHY registers. If it was already
614 * disabled, cancel the timer that is going to re-enable
617 if (!chip->ppu_disabled) {
618 ret = mv88e6xxx_ppu_disable(chip);
620 mutex_unlock(&chip->ppu_mutex);
623 chip->ppu_disabled = 1;
625 del_timer(&chip->ppu_timer);
632 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
634 /* Schedule a timer to re-enable the PHY polling unit. */
635 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
636 mutex_unlock(&chip->ppu_mutex);
639 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
641 mutex_init(&chip->ppu_mutex);
642 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
643 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
644 (unsigned long)chip);
647 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
649 del_timer_sync(&chip->ppu_timer);
652 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
657 err = mv88e6xxx_ppu_access_get(chip);
659 err = mv88e6xxx_read(chip, addr, reg, val);
660 mv88e6xxx_ppu_access_put(chip);
666 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
671 err = mv88e6xxx_ppu_access_get(chip);
673 err = mv88e6xxx_write(chip, addr, reg, val);
674 mv88e6xxx_ppu_access_put(chip);
680 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
682 return chip->info->family == MV88E6XXX_FAMILY_6065;
685 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
687 return chip->info->family == MV88E6XXX_FAMILY_6095;
690 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
692 return chip->info->family == MV88E6XXX_FAMILY_6097;
695 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
697 return chip->info->family == MV88E6XXX_FAMILY_6165;
700 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
702 return chip->info->family == MV88E6XXX_FAMILY_6185;
705 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
707 return chip->info->family == MV88E6XXX_FAMILY_6320;
710 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
712 return chip->info->family == MV88E6XXX_FAMILY_6351;
715 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
717 return chip->info->family == MV88E6XXX_FAMILY_6352;
720 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
721 int link, int speed, int duplex,
722 phy_interface_t mode)
726 if (!chip->info->ops->port_set_link)
729 /* Port's MAC control must not be changed unless the link is down */
730 err = chip->info->ops->port_set_link(chip, port, 0);
734 if (chip->info->ops->port_set_speed) {
735 err = chip->info->ops->port_set_speed(chip, port, speed);
736 if (err && err != -EOPNOTSUPP)
740 if (chip->info->ops->port_set_duplex) {
741 err = chip->info->ops->port_set_duplex(chip, port, duplex);
742 if (err && err != -EOPNOTSUPP)
746 if (chip->info->ops->port_set_rgmii_delay) {
747 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
748 if (err && err != -EOPNOTSUPP)
754 if (chip->info->ops->port_set_link(chip, port, link))
755 netdev_err(chip->ds->ports[port].netdev,
756 "failed to restore MAC's link\n");
761 /* We expect the switch to perform auto negotiation if there is a real
762 * phy. However, in the case of a fixed link phy, we force the port
763 * settings from the fixed link settings.
765 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
766 struct phy_device *phydev)
768 struct mv88e6xxx_chip *chip = ds->priv;
771 if (!phy_is_pseudo_fixed_link(phydev))
774 mutex_lock(&chip->reg_lock);
775 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
776 phydev->duplex, phydev->interface);
777 mutex_unlock(&chip->reg_lock);
779 if (err && err != -EOPNOTSUPP)
780 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
783 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
785 if (!chip->info->ops->stats_snapshot)
788 return chip->info->ops->stats_snapshot(chip, port);
791 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
792 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
793 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
794 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
795 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
796 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
797 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
798 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
799 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
800 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
801 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
802 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
803 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
804 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
805 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
806 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
807 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
808 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
809 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
810 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
811 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
812 { "single", 4, 0x14, STATS_TYPE_BANK0, },
813 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
814 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
815 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
816 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
817 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
818 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
819 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
820 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
821 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
822 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
823 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
824 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
825 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
826 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
827 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
828 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
829 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
830 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
831 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
832 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
833 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
834 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
835 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
836 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
837 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
838 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
839 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
840 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
841 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
842 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
843 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
844 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
845 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
846 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
847 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
848 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
849 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
850 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
853 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
854 struct mv88e6xxx_hw_stat *s,
855 int port, u16 bank1_select,
865 case STATS_TYPE_PORT:
866 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
871 if (s->sizeof_stat == 4) {
872 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
878 case STATS_TYPE_BANK1:
881 case STATS_TYPE_BANK0:
882 reg |= s->reg | histogram;
883 mv88e6xxx_g1_stats_read(chip, reg, &low);
884 if (s->sizeof_stat == 8)
885 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
887 value = (((u64)high) << 16) | low;
891 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
892 uint8_t *data, int types)
894 struct mv88e6xxx_hw_stat *stat;
897 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
898 stat = &mv88e6xxx_hw_stats[i];
899 if (stat->type & types) {
900 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
907 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
910 mv88e6xxx_stats_get_strings(chip, data,
911 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
914 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
917 mv88e6xxx_stats_get_strings(chip, data,
918 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
921 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
924 struct mv88e6xxx_chip *chip = ds->priv;
926 if (chip->info->ops->stats_get_strings)
927 chip->info->ops->stats_get_strings(chip, data);
930 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
933 struct mv88e6xxx_hw_stat *stat;
936 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
937 stat = &mv88e6xxx_hw_stats[i];
938 if (stat->type & types)
944 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
946 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
950 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
952 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
956 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
958 struct mv88e6xxx_chip *chip = ds->priv;
960 if (chip->info->ops->stats_get_sset_count)
961 return chip->info->ops->stats_get_sset_count(chip);
966 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
967 uint64_t *data, int types,
968 u16 bank1_select, u16 histogram)
970 struct mv88e6xxx_hw_stat *stat;
973 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
974 stat = &mv88e6xxx_hw_stats[i];
975 if (stat->type & types) {
976 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
984 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
987 return mv88e6xxx_stats_get_stats(chip, port, data,
988 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
989 0, GLOBAL_STATS_OP_HIST_RX_TX);
992 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
995 return mv88e6xxx_stats_get_stats(chip, port, data,
996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
997 GLOBAL_STATS_OP_BANK_1_BIT_9,
998 GLOBAL_STATS_OP_HIST_RX_TX);
1001 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1004 return mv88e6xxx_stats_get_stats(chip, port, data,
1005 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1006 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
1009 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1012 if (chip->info->ops->stats_get_stats)
1013 chip->info->ops->stats_get_stats(chip, port, data);
1016 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1019 struct mv88e6xxx_chip *chip = ds->priv;
1022 mutex_lock(&chip->reg_lock);
1024 ret = mv88e6xxx_stats_snapshot(chip, port);
1026 mutex_unlock(&chip->reg_lock);
1030 mv88e6xxx_get_stats(chip, port, data);
1032 mutex_unlock(&chip->reg_lock);
1035 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1037 if (chip->info->ops->stats_set_histogram)
1038 return chip->info->ops->stats_set_histogram(chip);
1043 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1045 return 32 * sizeof(u16);
1048 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1049 struct ethtool_regs *regs, void *_p)
1051 struct mv88e6xxx_chip *chip = ds->priv;
1059 memset(p, 0xff, 32 * sizeof(u16));
1061 mutex_lock(&chip->reg_lock);
1063 for (i = 0; i < 32; i++) {
1065 err = mv88e6xxx_port_read(chip, port, i, ®);
1070 mutex_unlock(&chip->reg_lock);
1073 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1075 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
1078 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1079 struct ethtool_eee *e)
1081 struct mv88e6xxx_chip *chip = ds->priv;
1085 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1088 mutex_lock(&chip->reg_lock);
1090 err = mv88e6xxx_phy_read(chip, port, 16, ®);
1094 e->eee_enabled = !!(reg & 0x0200);
1095 e->tx_lpi_enabled = !!(reg & 0x0100);
1097 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
1101 e->eee_active = !!(reg & PORT_STATUS_EEE);
1103 mutex_unlock(&chip->reg_lock);
1108 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1109 struct phy_device *phydev, struct ethtool_eee *e)
1111 struct mv88e6xxx_chip *chip = ds->priv;
1115 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1118 mutex_lock(&chip->reg_lock);
1120 err = mv88e6xxx_phy_read(chip, port, 16, ®);
1127 if (e->tx_lpi_enabled)
1130 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1132 mutex_unlock(&chip->reg_lock);
1137 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1142 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
1143 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1146 } else if (mv88e6xxx_num_databases(chip) == 256) {
1147 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1148 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1152 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1153 (val & 0xfff) | ((fid << 8) & 0xf000));
1157 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1161 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1165 return _mv88e6xxx_atu_wait(chip);
1168 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1169 struct mv88e6xxx_atu_entry *entry)
1171 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1173 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1174 unsigned int mask, shift;
1177 data |= GLOBAL_ATU_DATA_TRUNK;
1178 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1179 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1181 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1182 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1185 data |= (entry->portv_trunkid << shift) & mask;
1188 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1191 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1192 struct mv88e6xxx_atu_entry *entry,
1198 err = _mv88e6xxx_atu_wait(chip);
1202 err = _mv88e6xxx_atu_data_write(chip, entry);
1207 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1208 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1210 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1211 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1214 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1217 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1218 u16 fid, bool static_too)
1220 struct mv88e6xxx_atu_entry entry = {
1222 .state = 0, /* EntryState bits must be 0 */
1225 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1228 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1229 int from_port, int to_port, bool static_too)
1231 struct mv88e6xxx_atu_entry entry = {
1236 /* EntryState bits must be 0xF */
1237 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1239 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1240 entry.portv_trunkid = (to_port & 0x0f) << 4;
1241 entry.portv_trunkid |= from_port & 0x0f;
1243 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1246 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1247 int port, bool static_too)
1249 /* Destination port 0xF means remove the entries */
1250 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1253 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1255 struct net_device *bridge = chip->ports[port].bridge_dev;
1256 struct dsa_switch *ds = chip->ds;
1257 u16 output_ports = 0;
1260 /* allow CPU port or DSA link(s) to send frames to every port */
1261 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1264 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1265 /* allow sending frames to every group member */
1266 if (bridge && chip->ports[i].bridge_dev == bridge)
1267 output_ports |= BIT(i);
1269 /* allow sending frames to CPU port and DSA link(s) */
1270 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1271 output_ports |= BIT(i);
1275 /* prevent frames from going back out of the port they came in on */
1276 output_ports &= ~BIT(port);
1278 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1281 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1284 struct mv88e6xxx_chip *chip = ds->priv;
1289 case BR_STATE_DISABLED:
1290 stp_state = PORT_CONTROL_STATE_DISABLED;
1292 case BR_STATE_BLOCKING:
1293 case BR_STATE_LISTENING:
1294 stp_state = PORT_CONTROL_STATE_BLOCKING;
1296 case BR_STATE_LEARNING:
1297 stp_state = PORT_CONTROL_STATE_LEARNING;
1299 case BR_STATE_FORWARDING:
1301 stp_state = PORT_CONTROL_STATE_FORWARDING;
1305 mutex_lock(&chip->reg_lock);
1306 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1307 mutex_unlock(&chip->reg_lock);
1310 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1313 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1315 struct mv88e6xxx_chip *chip = ds->priv;
1318 mutex_lock(&chip->reg_lock);
1319 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1320 mutex_unlock(&chip->reg_lock);
1323 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1326 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1328 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1331 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1335 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1339 return _mv88e6xxx_vtu_wait(chip);
1342 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1346 ret = _mv88e6xxx_vtu_wait(chip);
1350 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1353 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1354 struct mv88e6xxx_vtu_entry *entry,
1355 unsigned int nibble_offset)
1360 for (i = 0; i < 3; ++i) {
1361 u16 *reg = ®s[i];
1363 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1368 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1369 unsigned int shift = (i % 4) * 4 + nibble_offset;
1370 u16 reg = regs[i / 4];
1372 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1378 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1379 struct mv88e6xxx_vtu_entry *entry)
1381 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1384 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1385 struct mv88e6xxx_vtu_entry *entry)
1387 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1390 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1391 struct mv88e6xxx_vtu_entry *entry,
1392 unsigned int nibble_offset)
1394 u16 regs[3] = { 0 };
1397 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1398 unsigned int shift = (i % 4) * 4 + nibble_offset;
1399 u8 data = entry->data[i];
1401 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1404 for (i = 0; i < 3; ++i) {
1407 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1415 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1416 struct mv88e6xxx_vtu_entry *entry)
1418 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1421 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1422 struct mv88e6xxx_vtu_entry *entry)
1424 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1427 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1429 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1430 vid & GLOBAL_VTU_VID_MASK);
1433 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1434 struct mv88e6xxx_vtu_entry *entry)
1436 struct mv88e6xxx_vtu_entry next = { 0 };
1440 err = _mv88e6xxx_vtu_wait(chip);
1444 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1448 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1452 next.vid = val & GLOBAL_VTU_VID_MASK;
1453 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1456 err = mv88e6xxx_vtu_data_read(chip, &next);
1460 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1461 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1465 next.fid = val & GLOBAL_VTU_FID_MASK;
1466 } else if (mv88e6xxx_num_databases(chip) == 256) {
1467 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1468 * VTU DBNum[3:0] are located in VTU Operation 3:0
1470 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1474 next.fid = (val & 0xf00) >> 4;
1475 next.fid |= val & 0xf;
1478 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1479 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1483 next.sid = val & GLOBAL_VTU_SID_MASK;
1491 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1492 struct switchdev_obj_port_vlan *vlan,
1493 int (*cb)(struct switchdev_obj *obj))
1495 struct mv88e6xxx_chip *chip = ds->priv;
1496 struct mv88e6xxx_vtu_entry next;
1500 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1503 mutex_lock(&chip->reg_lock);
1505 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1509 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1514 err = _mv88e6xxx_vtu_getnext(chip, &next);
1521 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1524 /* reinit and dump this VLAN obj */
1525 vlan->vid_begin = next.vid;
1526 vlan->vid_end = next.vid;
1529 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1530 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1532 if (next.vid == pvid)
1533 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1535 err = cb(&vlan->obj);
1538 } while (next.vid < GLOBAL_VTU_VID_MASK);
1541 mutex_unlock(&chip->reg_lock);
1546 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1547 struct mv88e6xxx_vtu_entry *entry)
1549 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1553 err = _mv88e6xxx_vtu_wait(chip);
1560 /* Write port member tags */
1561 err = mv88e6xxx_vtu_data_write(chip, entry);
1565 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1566 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1567 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1572 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1573 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1574 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1577 } else if (mv88e6xxx_num_databases(chip) == 256) {
1578 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1579 * VTU DBNum[3:0] are located in VTU Operation 3:0
1581 op |= (entry->fid & 0xf0) << 8;
1582 op |= entry->fid & 0xf;
1585 reg = GLOBAL_VTU_VID_VALID;
1587 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1588 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1592 return _mv88e6xxx_vtu_cmd(chip, op);
1595 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1596 struct mv88e6xxx_vtu_entry *entry)
1598 struct mv88e6xxx_vtu_entry next = { 0 };
1602 err = _mv88e6xxx_vtu_wait(chip);
1606 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1607 sid & GLOBAL_VTU_SID_MASK);
1611 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1615 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1619 next.sid = val & GLOBAL_VTU_SID_MASK;
1621 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1625 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1628 err = mv88e6xxx_stu_data_read(chip, &next);
1637 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1638 struct mv88e6xxx_vtu_entry *entry)
1643 err = _mv88e6xxx_vtu_wait(chip);
1650 /* Write port states */
1651 err = mv88e6xxx_stu_data_write(chip, entry);
1655 reg = GLOBAL_VTU_VID_VALID;
1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1661 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1662 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1666 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1669 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1671 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1672 struct mv88e6xxx_vtu_entry vlan;
1675 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1677 /* Set every FID bit used by the (un)bridged ports */
1678 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1679 err = mv88e6xxx_port_get_fid(chip, i, fid);
1683 set_bit(*fid, fid_bitmap);
1686 /* Set every FID bit used by the VLAN entries */
1687 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1692 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1699 set_bit(vlan.fid, fid_bitmap);
1700 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1702 /* The reset value 0x000 is used to indicate that multiple address
1703 * databases are not needed. Return the next positive available.
1705 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1706 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1709 /* Clear the database */
1710 return _mv88e6xxx_atu_flush(chip, *fid, true);
1713 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1714 struct mv88e6xxx_vtu_entry *entry)
1716 struct dsa_switch *ds = chip->ds;
1717 struct mv88e6xxx_vtu_entry vlan = {
1723 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1727 /* exclude all ports except the CPU and DSA ports */
1728 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1729 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1730 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1731 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1733 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1734 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1735 struct mv88e6xxx_vtu_entry vstp;
1737 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1738 * implemented, only one STU entry is needed to cover all VTU
1739 * entries. Thus, validate the SID 0.
1742 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1746 if (vstp.sid != vlan.sid || !vstp.valid) {
1747 memset(&vstp, 0, sizeof(vstp));
1749 vstp.sid = vlan.sid;
1751 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1761 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1762 struct mv88e6xxx_vtu_entry *entry, bool creat)
1769 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1773 err = _mv88e6xxx_vtu_getnext(chip, entry);
1777 if (entry->vid != vid || !entry->valid) {
1780 /* -ENOENT would've been more appropriate, but switchdev expects
1781 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1784 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1790 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1791 u16 vid_begin, u16 vid_end)
1793 struct mv88e6xxx_chip *chip = ds->priv;
1794 struct mv88e6xxx_vtu_entry vlan;
1800 mutex_lock(&chip->reg_lock);
1802 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1807 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1814 if (vlan.vid > vid_end)
1817 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1818 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1822 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1825 if (chip->ports[i].bridge_dev ==
1826 chip->ports[port].bridge_dev)
1827 break; /* same bridge, check next VLAN */
1829 netdev_warn(ds->ports[port].netdev,
1830 "hardware VLAN %d already used by %s\n",
1832 netdev_name(chip->ports[i].bridge_dev));
1836 } while (vlan.vid < vid_end);
1839 mutex_unlock(&chip->reg_lock);
1844 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1845 bool vlan_filtering)
1847 struct mv88e6xxx_chip *chip = ds->priv;
1848 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1849 PORT_CONTROL_2_8021Q_DISABLED;
1852 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1855 mutex_lock(&chip->reg_lock);
1856 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1857 mutex_unlock(&chip->reg_lock);
1863 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1864 const struct switchdev_obj_port_vlan *vlan,
1865 struct switchdev_trans *trans)
1867 struct mv88e6xxx_chip *chip = ds->priv;
1870 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1873 /* If the requested port doesn't belong to the same bridge as the VLAN
1874 * members, do not support it (yet) and fallback to software VLAN.
1876 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1881 /* We don't need any dynamic resource from the kernel (yet),
1882 * so skip the prepare phase.
1887 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1888 u16 vid, bool untagged)
1890 struct mv88e6xxx_vtu_entry vlan;
1893 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1897 vlan.data[port] = untagged ?
1898 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1899 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1901 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1904 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1905 const struct switchdev_obj_port_vlan *vlan,
1906 struct switchdev_trans *trans)
1908 struct mv88e6xxx_chip *chip = ds->priv;
1909 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1910 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1913 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1916 mutex_lock(&chip->reg_lock);
1918 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1919 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1920 netdev_err(ds->ports[port].netdev,
1921 "failed to add VLAN %d%c\n",
1922 vid, untagged ? 'u' : 't');
1924 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1925 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1928 mutex_unlock(&chip->reg_lock);
1931 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1934 struct dsa_switch *ds = chip->ds;
1935 struct mv88e6xxx_vtu_entry vlan;
1938 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1942 /* Tell switchdev if this VLAN is handled in software */
1943 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1946 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1948 /* keep the VLAN unless all ports are excluded */
1950 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1951 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1954 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1960 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1964 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1967 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1968 const struct switchdev_obj_port_vlan *vlan)
1970 struct mv88e6xxx_chip *chip = ds->priv;
1974 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1977 mutex_lock(&chip->reg_lock);
1979 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1983 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1984 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1989 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1996 mutex_unlock(&chip->reg_lock);
2001 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2002 const unsigned char *addr)
2006 for (i = 0; i < 3; i++) {
2007 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2008 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2016 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2017 unsigned char *addr)
2022 for (i = 0; i < 3; i++) {
2023 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2027 addr[i * 2] = val >> 8;
2028 addr[i * 2 + 1] = val & 0xff;
2034 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2035 struct mv88e6xxx_atu_entry *entry)
2039 ret = _mv88e6xxx_atu_wait(chip);
2043 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2047 ret = _mv88e6xxx_atu_data_write(chip, entry);
2051 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2054 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2055 struct mv88e6xxx_atu_entry *entry);
2057 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2058 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2060 struct mv88e6xxx_atu_entry next;
2063 eth_broadcast_addr(next.mac);
2065 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2070 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2074 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2077 if (ether_addr_equal(next.mac, addr)) {
2081 } while (!is_broadcast_ether_addr(next.mac));
2083 memset(entry, 0, sizeof(*entry));
2085 ether_addr_copy(entry->mac, addr);
2090 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2091 const unsigned char *addr, u16 vid,
2094 struct mv88e6xxx_vtu_entry vlan;
2095 struct mv88e6xxx_atu_entry entry;
2098 /* Null VLAN ID corresponds to the port private database */
2100 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2102 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2106 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2110 /* Purge the ATU entry only if no port is using it anymore */
2111 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2112 entry.portv_trunkid &= ~BIT(port);
2113 if (!entry.portv_trunkid)
2114 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2116 entry.portv_trunkid |= BIT(port);
2117 entry.state = state;
2120 return _mv88e6xxx_atu_load(chip, &entry);
2123 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2124 const struct switchdev_obj_port_fdb *fdb,
2125 struct switchdev_trans *trans)
2127 /* We don't need any dynamic resource from the kernel (yet),
2128 * so skip the prepare phase.
2133 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2134 const struct switchdev_obj_port_fdb *fdb,
2135 struct switchdev_trans *trans)
2137 struct mv88e6xxx_chip *chip = ds->priv;
2139 mutex_lock(&chip->reg_lock);
2140 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2141 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2142 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2143 mutex_unlock(&chip->reg_lock);
2146 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2147 const struct switchdev_obj_port_fdb *fdb)
2149 struct mv88e6xxx_chip *chip = ds->priv;
2152 mutex_lock(&chip->reg_lock);
2153 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2154 GLOBAL_ATU_DATA_STATE_UNUSED);
2155 mutex_unlock(&chip->reg_lock);
2160 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2161 struct mv88e6xxx_atu_entry *entry)
2163 struct mv88e6xxx_atu_entry next = { 0 };
2169 err = _mv88e6xxx_atu_wait(chip);
2173 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2177 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2181 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2185 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2186 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2187 unsigned int mask, shift;
2189 if (val & GLOBAL_ATU_DATA_TRUNK) {
2191 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2192 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2195 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2196 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2199 next.portv_trunkid = (val & mask) >> shift;
2206 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2207 u16 fid, u16 vid, int port,
2208 struct switchdev_obj *obj,
2209 int (*cb)(struct switchdev_obj *obj))
2211 struct mv88e6xxx_atu_entry addr = {
2212 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2216 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2221 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2225 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2228 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2231 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2232 struct switchdev_obj_port_fdb *fdb;
2234 if (!is_unicast_ether_addr(addr.mac))
2237 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2239 ether_addr_copy(fdb->addr, addr.mac);
2240 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2241 fdb->ndm_state = NUD_NOARP;
2243 fdb->ndm_state = NUD_REACHABLE;
2244 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2245 struct switchdev_obj_port_mdb *mdb;
2247 if (!is_multicast_ether_addr(addr.mac))
2250 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2252 ether_addr_copy(mdb->addr, addr.mac);
2260 } while (!is_broadcast_ether_addr(addr.mac));
2265 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2266 struct switchdev_obj *obj,
2267 int (*cb)(struct switchdev_obj *obj))
2269 struct mv88e6xxx_vtu_entry vlan = {
2270 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2275 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2276 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2280 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2284 /* Dump VLANs' Filtering Information Databases */
2285 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2290 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2297 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2301 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2306 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2307 struct switchdev_obj_port_fdb *fdb,
2308 int (*cb)(struct switchdev_obj *obj))
2310 struct mv88e6xxx_chip *chip = ds->priv;
2313 mutex_lock(&chip->reg_lock);
2314 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2315 mutex_unlock(&chip->reg_lock);
2320 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2321 struct net_device *bridge)
2323 struct mv88e6xxx_chip *chip = ds->priv;
2326 mutex_lock(&chip->reg_lock);
2328 /* Assign the bridge and remap each port's VLANTable */
2329 chip->ports[port].bridge_dev = bridge;
2331 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2332 if (chip->ports[i].bridge_dev == bridge) {
2333 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2339 mutex_unlock(&chip->reg_lock);
2344 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2346 struct mv88e6xxx_chip *chip = ds->priv;
2347 struct net_device *bridge = chip->ports[port].bridge_dev;
2350 mutex_lock(&chip->reg_lock);
2352 /* Unassign the bridge and remap each port's VLANTable */
2353 chip->ports[port].bridge_dev = NULL;
2355 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2356 if (i == port || chip->ports[i].bridge_dev == bridge)
2357 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2358 netdev_warn(ds->ports[i].netdev,
2359 "failed to remap\n");
2361 mutex_unlock(&chip->reg_lock);
2364 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2366 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2367 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2368 struct gpio_desc *gpiod = chip->reset;
2369 unsigned long timeout;
2374 /* Set all ports to the disabled state. */
2375 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2376 err = mv88e6xxx_port_set_state(chip, i,
2377 PORT_CONTROL_STATE_DISABLED);
2382 /* Wait for transmit queues to drain. */
2383 usleep_range(2000, 4000);
2385 /* If there is a gpio connected to the reset pin, toggle it */
2387 gpiod_set_value_cansleep(gpiod, 1);
2388 usleep_range(10000, 20000);
2389 gpiod_set_value_cansleep(gpiod, 0);
2390 usleep_range(10000, 20000);
2393 /* Reset the switch. Keep the PPU active if requested. The PPU
2394 * needs to be active to support indirect phy register access
2395 * through global registers 0x18 and 0x19.
2398 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2400 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2404 /* Wait up to one second for reset to complete. */
2405 timeout = jiffies + 1 * HZ;
2406 while (time_before(jiffies, timeout)) {
2407 err = mv88e6xxx_g1_read(chip, 0x00, ®);
2411 if ((reg & is_reset) == is_reset)
2413 usleep_range(1000, 2000);
2415 if (time_after(jiffies, timeout))
2423 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2428 /* Clear Power Down bit */
2429 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2433 if (val & BMCR_PDOWN) {
2435 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2441 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2443 struct dsa_switch *ds = chip->ds;
2447 /* MAC Forcing register: don't force link, speed, duplex or flow control
2448 * state to any particular values on physical ports, but force the CPU
2449 * port and all DSA ports to their maximum bandwidth and full duplex.
2451 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2452 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2453 SPEED_MAX, DUPLEX_FULL,
2454 PHY_INTERFACE_MODE_NA);
2456 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2457 SPEED_UNFORCED, DUPLEX_UNFORCED,
2458 PHY_INTERFACE_MODE_NA);
2462 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2463 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2464 * tunneling, determine priority by looking at 802.1p and IP
2465 * priority fields (IP prio has precedence), and set STP state
2468 * If this is the CPU link, use DSA or EDSA tagging depending
2469 * on which tagging mode was configured.
2471 * If this is a link to another switch, use DSA tagging mode.
2473 * If this is the upstream port for this switch, enable
2474 * forwarding of unknown unicasts and multicasts.
2477 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2478 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2479 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2480 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2481 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2482 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2483 PORT_CONTROL_STATE_FORWARDING;
2484 if (dsa_is_cpu_port(ds, port)) {
2485 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2486 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2487 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2489 reg |= PORT_CONTROL_DSA_TAG;
2490 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2491 PORT_CONTROL_FORWARD_UNKNOWN;
2493 if (dsa_is_dsa_port(ds, port)) {
2494 if (mv88e6xxx_6095_family(chip) ||
2495 mv88e6xxx_6185_family(chip))
2496 reg |= PORT_CONTROL_DSA_TAG;
2497 if (mv88e6xxx_6352_family(chip) ||
2498 mv88e6xxx_6351_family(chip) ||
2499 mv88e6xxx_6165_family(chip) ||
2500 mv88e6xxx_6097_family(chip) ||
2501 mv88e6xxx_6320_family(chip)) {
2502 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2505 if (port == dsa_upstream_port(ds))
2506 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2507 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2510 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2515 /* If this port is connected to a SerDes, make sure the SerDes is not
2518 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2519 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
2522 reg &= PORT_STATUS_CMODE_MASK;
2523 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2524 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2525 (reg == PORT_STATUS_CMODE_SGMII)) {
2526 err = mv88e6xxx_serdes_power_on(chip);
2532 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2533 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2534 * untagged frames on this port, do a destination address lookup on all
2535 * received packets as usual, disable ARP mirroring and don't send a
2536 * copy of all transmitted/received frames on this port to the CPU.
2539 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2540 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2541 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2542 mv88e6xxx_6185_family(chip))
2543 reg = PORT_CONTROL_2_MAP_DA;
2545 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2546 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2547 reg |= PORT_CONTROL_2_JUMBO_10240;
2549 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2550 /* Set the upstream port this port should use */
2551 reg |= dsa_upstream_port(ds);
2552 /* enable forwarding of unknown multicast addresses to
2555 if (port == dsa_upstream_port(ds))
2556 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2559 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2562 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2567 /* Port Association Vector: when learning source addresses
2568 * of packets, add the address to the address database using
2569 * a port bitmap that has only the bit for this port set and
2570 * the other bits clear.
2573 /* Disable learning for CPU port */
2574 if (dsa_is_cpu_port(ds, port))
2577 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2581 /* Egress rate control 2: disable egress rate control. */
2582 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2586 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2587 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2588 mv88e6xxx_6320_family(chip)) {
2589 /* Do not limit the period of time that this port can
2590 * be paused for by the remote end or the period of
2591 * time that this port can pause the remote end.
2593 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2597 /* Port ATU control: disable limiting the number of
2598 * address database entries that this port is allowed
2601 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2603 /* Priority Override: disable DA, SA and VTU priority
2606 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2611 /* Port Ethertype: use the Ethertype DSA Ethertype
2614 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2615 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2622 if (chip->info->ops->port_tag_remap) {
2623 err = chip->info->ops->port_tag_remap(chip, port);
2628 /* Rate Control: disable ingress rate limiting. */
2629 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2630 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2631 mv88e6xxx_6320_family(chip)) {
2632 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2636 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2637 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2643 /* Port Control 1: disable trunking, disable sending
2644 * learning messages to this port.
2646 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2650 /* Port based VLAN map: give each port the same default address
2651 * database, and allow bidirectional communication between the
2652 * CPU and DSA port(s), and the other ports.
2654 err = mv88e6xxx_port_set_fid(chip, port, 0);
2658 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2662 /* Default VLAN ID and priority: don't set a default VLAN
2663 * ID, and set the default packet priority to zero.
2665 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2668 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2672 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2676 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2680 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2687 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2690 const unsigned int coeff = chip->info->age_time_coeff;
2691 const unsigned int min = 0x01 * coeff;
2692 const unsigned int max = 0xff * coeff;
2697 if (msecs < min || msecs > max)
2700 /* Round to nearest multiple of coeff */
2701 age_time = (msecs + coeff / 2) / coeff;
2703 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2707 /* AgeTime is 11:4 bits */
2709 val |= age_time << 4;
2711 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2714 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2715 unsigned int ageing_time)
2717 struct mv88e6xxx_chip *chip = ds->priv;
2720 mutex_lock(&chip->reg_lock);
2721 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2722 mutex_unlock(&chip->reg_lock);
2727 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2729 struct dsa_switch *ds = chip->ds;
2730 u32 upstream_port = dsa_upstream_port(ds);
2734 /* Enable the PHY Polling Unit if present, don't discard any packets,
2735 * and mask all interrupt sources.
2737 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
2741 reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
2742 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2743 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2744 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2746 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2750 if (chip->info->ops->g1_set_cpu_port) {
2751 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2756 if (chip->info->ops->g1_set_egress_port) {
2757 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2762 /* Disable remote management, and set the switch's DSA device number. */
2763 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2764 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2765 (ds->index & 0x1f));
2769 /* Clear all the VTU and STU entries */
2770 err = _mv88e6xxx_vtu_stu_flush(chip);
2774 /* Set the default address aging time to 5 minutes, and
2775 * enable address learn messages to be sent to all message
2778 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2779 GLOBAL_ATU_CONTROL_LEARN2ALL);
2783 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2787 /* Clear all ATU entries */
2788 err = _mv88e6xxx_atu_flush(chip, 0, true);
2792 /* Configure the IP ToS mapping registers. */
2793 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2796 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2799 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2802 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2805 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2808 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2811 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2814 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2818 /* Configure the IEEE 802.1p priority mapping register. */
2819 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2823 /* Initialize the statistics unit */
2824 err = mv88e6xxx_stats_set_histogram(chip);
2828 /* Clear the statistics counters for all ports */
2829 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2830 GLOBAL_STATS_OP_FLUSH_ALL);
2834 /* Wait for the flush to complete. */
2835 err = mv88e6xxx_g1_stats_wait(chip);
2842 static int mv88e6xxx_setup(struct dsa_switch *ds)
2844 struct mv88e6xxx_chip *chip = ds->priv;
2849 ds->slave_mii_bus = chip->mdio_bus;
2851 mutex_lock(&chip->reg_lock);
2853 /* Setup Switch Port Registers */
2854 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2855 err = mv88e6xxx_setup_port(chip, i);
2860 /* Setup Switch Global 1 Registers */
2861 err = mv88e6xxx_g1_setup(chip);
2865 /* Setup Switch Global 2 Registers */
2866 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2867 err = mv88e6xxx_g2_setup(chip);
2873 mutex_unlock(&chip->reg_lock);
2878 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2880 struct mv88e6xxx_chip *chip = ds->priv;
2883 if (!chip->info->ops->set_switch_mac)
2886 mutex_lock(&chip->reg_lock);
2887 err = chip->info->ops->set_switch_mac(chip, addr);
2888 mutex_unlock(&chip->reg_lock);
2893 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2895 struct mv88e6xxx_chip *chip = bus->priv;
2899 if (phy >= mv88e6xxx_num_ports(chip))
2902 mutex_lock(&chip->reg_lock);
2903 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2904 mutex_unlock(&chip->reg_lock);
2906 return err ? err : val;
2909 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2911 struct mv88e6xxx_chip *chip = bus->priv;
2914 if (phy >= mv88e6xxx_num_ports(chip))
2917 mutex_lock(&chip->reg_lock);
2918 err = mv88e6xxx_phy_write(chip, phy, reg, val);
2919 mutex_unlock(&chip->reg_lock);
2924 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2925 struct device_node *np)
2928 struct mii_bus *bus;
2932 chip->mdio_np = of_get_child_by_name(np, "mdio");
2934 bus = devm_mdiobus_alloc(chip->dev);
2938 bus->priv = (void *)chip;
2940 bus->name = np->full_name;
2941 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2943 bus->name = "mv88e6xxx SMI";
2944 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2947 bus->read = mv88e6xxx_mdio_read;
2948 bus->write = mv88e6xxx_mdio_write;
2949 bus->parent = chip->dev;
2952 err = of_mdiobus_register(bus, chip->mdio_np);
2954 err = mdiobus_register(bus);
2956 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2959 chip->mdio_bus = bus;
2965 of_node_put(chip->mdio_np);
2970 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
2973 struct mii_bus *bus = chip->mdio_bus;
2975 mdiobus_unregister(bus);
2978 of_node_put(chip->mdio_np);
2981 #ifdef CONFIG_NET_DSA_HWMON
2983 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2985 struct mv88e6xxx_chip *chip = ds->priv;
2991 mutex_lock(&chip->reg_lock);
2993 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
2997 /* Enable temperature sensor */
2998 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3002 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3006 /* Wait for temperature to stabilize */
3007 usleep_range(10000, 12000);
3009 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3013 /* Disable temperature sensor */
3014 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3018 *temp = ((val & 0x1f) - 5) * 5;
3021 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3022 mutex_unlock(&chip->reg_lock);
3026 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3028 struct mv88e6xxx_chip *chip = ds->priv;
3029 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3035 mutex_lock(&chip->reg_lock);
3036 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3037 mutex_unlock(&chip->reg_lock);
3041 *temp = (val & 0xff) - 25;
3046 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3048 struct mv88e6xxx_chip *chip = ds->priv;
3050 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3053 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3054 return mv88e63xx_get_temp(ds, temp);
3056 return mv88e61xx_get_temp(ds, temp);
3059 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3061 struct mv88e6xxx_chip *chip = ds->priv;
3062 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3066 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3071 mutex_lock(&chip->reg_lock);
3072 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3073 mutex_unlock(&chip->reg_lock);
3077 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3082 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3084 struct mv88e6xxx_chip *chip = ds->priv;
3085 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3089 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3092 mutex_lock(&chip->reg_lock);
3093 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3096 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3097 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3098 (val & 0xe0ff) | (temp << 8));
3100 mutex_unlock(&chip->reg_lock);
3105 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3107 struct mv88e6xxx_chip *chip = ds->priv;
3108 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3112 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3117 mutex_lock(&chip->reg_lock);
3118 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3119 mutex_unlock(&chip->reg_lock);
3123 *alarm = !!(val & 0x40);
3127 #endif /* CONFIG_NET_DSA_HWMON */
3129 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3131 struct mv88e6xxx_chip *chip = ds->priv;
3133 return chip->eeprom_len;
3136 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3137 struct ethtool_eeprom *eeprom, u8 *data)
3139 struct mv88e6xxx_chip *chip = ds->priv;
3142 if (!chip->info->ops->get_eeprom)
3145 mutex_lock(&chip->reg_lock);
3146 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3147 mutex_unlock(&chip->reg_lock);
3152 eeprom->magic = 0xc3ec4951;
3157 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3158 struct ethtool_eeprom *eeprom, u8 *data)
3160 struct mv88e6xxx_chip *chip = ds->priv;
3163 if (!chip->info->ops->set_eeprom)
3166 if (eeprom->magic != 0xc3ec4951)
3169 mutex_lock(&chip->reg_lock);
3170 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3171 mutex_unlock(&chip->reg_lock);
3176 static const struct mv88e6xxx_ops mv88e6085_ops = {
3177 /* MV88E6XXX_FAMILY_6097 */
3178 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3179 .phy_read = mv88e6xxx_phy_ppu_read,
3180 .phy_write = mv88e6xxx_phy_ppu_write,
3181 .port_set_link = mv88e6xxx_port_set_link,
3182 .port_set_duplex = mv88e6xxx_port_set_duplex,
3183 .port_set_speed = mv88e6185_port_set_speed,
3184 .port_tag_remap = mv88e6095_port_tag_remap,
3185 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3186 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3187 .stats_get_strings = mv88e6095_stats_get_strings,
3188 .stats_get_stats = mv88e6095_stats_get_stats,
3189 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3190 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3193 static const struct mv88e6xxx_ops mv88e6095_ops = {
3194 /* MV88E6XXX_FAMILY_6095 */
3195 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3196 .phy_read = mv88e6xxx_phy_ppu_read,
3197 .phy_write = mv88e6xxx_phy_ppu_write,
3198 .port_set_link = mv88e6xxx_port_set_link,
3199 .port_set_duplex = mv88e6xxx_port_set_duplex,
3200 .port_set_speed = mv88e6185_port_set_speed,
3201 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3202 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3203 .stats_get_strings = mv88e6095_stats_get_strings,
3204 .stats_get_stats = mv88e6095_stats_get_stats,
3207 static const struct mv88e6xxx_ops mv88e6097_ops = {
3208 /* MV88E6XXX_FAMILY_6097 */
3209 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3210 .phy_read = mv88e6xxx_g2_smi_phy_read,
3211 .phy_write = mv88e6xxx_g2_smi_phy_write,
3212 .port_set_link = mv88e6xxx_port_set_link,
3213 .port_set_duplex = mv88e6xxx_port_set_duplex,
3214 .port_set_speed = mv88e6185_port_set_speed,
3215 .port_tag_remap = mv88e6095_port_tag_remap,
3216 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3217 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3218 .stats_get_strings = mv88e6095_stats_get_strings,
3219 .stats_get_stats = mv88e6095_stats_get_stats,
3220 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3221 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3224 static const struct mv88e6xxx_ops mv88e6123_ops = {
3225 /* MV88E6XXX_FAMILY_6165 */
3226 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3227 .phy_read = mv88e6xxx_read,
3228 .phy_write = mv88e6xxx_write,
3229 .port_set_link = mv88e6xxx_port_set_link,
3230 .port_set_duplex = mv88e6xxx_port_set_duplex,
3231 .port_set_speed = mv88e6185_port_set_speed,
3232 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3233 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3234 .stats_get_strings = mv88e6095_stats_get_strings,
3235 .stats_get_stats = mv88e6095_stats_get_stats,
3236 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3237 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3240 static const struct mv88e6xxx_ops mv88e6131_ops = {
3241 /* MV88E6XXX_FAMILY_6185 */
3242 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3243 .phy_read = mv88e6xxx_phy_ppu_read,
3244 .phy_write = mv88e6xxx_phy_ppu_write,
3245 .port_set_link = mv88e6xxx_port_set_link,
3246 .port_set_duplex = mv88e6xxx_port_set_duplex,
3247 .port_set_speed = mv88e6185_port_set_speed,
3248 .port_tag_remap = mv88e6095_port_tag_remap,
3249 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3250 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3251 .stats_get_strings = mv88e6095_stats_get_strings,
3252 .stats_get_stats = mv88e6095_stats_get_stats,
3253 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3254 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3257 static const struct mv88e6xxx_ops mv88e6161_ops = {
3258 /* MV88E6XXX_FAMILY_6165 */
3259 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3260 .phy_read = mv88e6xxx_read,
3261 .phy_write = mv88e6xxx_write,
3262 .port_set_link = mv88e6xxx_port_set_link,
3263 .port_set_duplex = mv88e6xxx_port_set_duplex,
3264 .port_set_speed = mv88e6185_port_set_speed,
3265 .port_tag_remap = mv88e6095_port_tag_remap,
3266 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3267 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3268 .stats_get_strings = mv88e6095_stats_get_strings,
3269 .stats_get_stats = mv88e6095_stats_get_stats,
3270 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3271 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3274 static const struct mv88e6xxx_ops mv88e6165_ops = {
3275 /* MV88E6XXX_FAMILY_6165 */
3276 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3277 .phy_read = mv88e6xxx_read,
3278 .phy_write = mv88e6xxx_write,
3279 .port_set_link = mv88e6xxx_port_set_link,
3280 .port_set_duplex = mv88e6xxx_port_set_duplex,
3281 .port_set_speed = mv88e6185_port_set_speed,
3282 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3283 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3284 .stats_get_strings = mv88e6095_stats_get_strings,
3285 .stats_get_stats = mv88e6095_stats_get_stats,
3286 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3287 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3290 static const struct mv88e6xxx_ops mv88e6171_ops = {
3291 /* MV88E6XXX_FAMILY_6351 */
3292 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3293 .phy_read = mv88e6xxx_g2_smi_phy_read,
3294 .phy_write = mv88e6xxx_g2_smi_phy_write,
3295 .port_set_link = mv88e6xxx_port_set_link,
3296 .port_set_duplex = mv88e6xxx_port_set_duplex,
3297 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3298 .port_set_speed = mv88e6185_port_set_speed,
3299 .port_tag_remap = mv88e6095_port_tag_remap,
3300 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3301 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3302 .stats_get_strings = mv88e6095_stats_get_strings,
3303 .stats_get_stats = mv88e6095_stats_get_stats,
3304 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3305 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3308 static const struct mv88e6xxx_ops mv88e6172_ops = {
3309 /* MV88E6XXX_FAMILY_6352 */
3310 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3311 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3312 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3313 .phy_read = mv88e6xxx_g2_smi_phy_read,
3314 .phy_write = mv88e6xxx_g2_smi_phy_write,
3315 .port_set_link = mv88e6xxx_port_set_link,
3316 .port_set_duplex = mv88e6xxx_port_set_duplex,
3317 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3318 .port_set_speed = mv88e6352_port_set_speed,
3319 .port_tag_remap = mv88e6095_port_tag_remap,
3320 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3321 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3322 .stats_get_strings = mv88e6095_stats_get_strings,
3323 .stats_get_stats = mv88e6095_stats_get_stats,
3324 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3325 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3328 static const struct mv88e6xxx_ops mv88e6175_ops = {
3329 /* MV88E6XXX_FAMILY_6351 */
3330 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3331 .phy_read = mv88e6xxx_g2_smi_phy_read,
3332 .phy_write = mv88e6xxx_g2_smi_phy_write,
3333 .port_set_link = mv88e6xxx_port_set_link,
3334 .port_set_duplex = mv88e6xxx_port_set_duplex,
3335 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3336 .port_set_speed = mv88e6185_port_set_speed,
3337 .port_tag_remap = mv88e6095_port_tag_remap,
3338 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3339 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3340 .stats_get_strings = mv88e6095_stats_get_strings,
3341 .stats_get_stats = mv88e6095_stats_get_stats,
3342 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3343 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3346 static const struct mv88e6xxx_ops mv88e6176_ops = {
3347 /* MV88E6XXX_FAMILY_6352 */
3348 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3349 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3350 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3351 .phy_read = mv88e6xxx_g2_smi_phy_read,
3352 .phy_write = mv88e6xxx_g2_smi_phy_write,
3353 .port_set_link = mv88e6xxx_port_set_link,
3354 .port_set_duplex = mv88e6xxx_port_set_duplex,
3355 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3356 .port_set_speed = mv88e6352_port_set_speed,
3357 .port_tag_remap = mv88e6095_port_tag_remap,
3358 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3359 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3360 .stats_get_strings = mv88e6095_stats_get_strings,
3361 .stats_get_stats = mv88e6095_stats_get_stats,
3362 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3363 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3366 static const struct mv88e6xxx_ops mv88e6185_ops = {
3367 /* MV88E6XXX_FAMILY_6185 */
3368 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3369 .phy_read = mv88e6xxx_phy_ppu_read,
3370 .phy_write = mv88e6xxx_phy_ppu_write,
3371 .port_set_link = mv88e6xxx_port_set_link,
3372 .port_set_duplex = mv88e6xxx_port_set_duplex,
3373 .port_set_speed = mv88e6185_port_set_speed,
3374 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3375 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3376 .stats_get_strings = mv88e6095_stats_get_strings,
3377 .stats_get_stats = mv88e6095_stats_get_stats,
3378 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3379 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3382 static const struct mv88e6xxx_ops mv88e6190_ops = {
3383 /* MV88E6XXX_FAMILY_6390 */
3384 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3385 .phy_read = mv88e6xxx_g2_smi_phy_read,
3386 .phy_write = mv88e6xxx_g2_smi_phy_write,
3387 .port_set_link = mv88e6xxx_port_set_link,
3388 .port_set_duplex = mv88e6xxx_port_set_duplex,
3389 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3390 .port_set_speed = mv88e6390_port_set_speed,
3391 .port_tag_remap = mv88e6390_port_tag_remap,
3392 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3393 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3394 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3395 .stats_get_strings = mv88e6320_stats_get_strings,
3396 .stats_get_stats = mv88e6390_stats_get_stats,
3397 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3398 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3401 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3402 /* MV88E6XXX_FAMILY_6390 */
3403 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3404 .phy_read = mv88e6xxx_g2_smi_phy_read,
3405 .phy_write = mv88e6xxx_g2_smi_phy_write,
3406 .port_set_link = mv88e6xxx_port_set_link,
3407 .port_set_duplex = mv88e6xxx_port_set_duplex,
3408 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3409 .port_set_speed = mv88e6390x_port_set_speed,
3410 .port_tag_remap = mv88e6390_port_tag_remap,
3411 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3412 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3413 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3414 .stats_get_strings = mv88e6320_stats_get_strings,
3415 .stats_get_stats = mv88e6390_stats_get_stats,
3416 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3417 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3420 static const struct mv88e6xxx_ops mv88e6191_ops = {
3421 /* MV88E6XXX_FAMILY_6390 */
3422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3423 .phy_read = mv88e6xxx_g2_smi_phy_read,
3424 .phy_write = mv88e6xxx_g2_smi_phy_write,
3425 .port_set_link = mv88e6xxx_port_set_link,
3426 .port_set_duplex = mv88e6xxx_port_set_duplex,
3427 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3428 .port_set_speed = mv88e6390_port_set_speed,
3429 .port_tag_remap = mv88e6390_port_tag_remap,
3430 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3431 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3432 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3433 .stats_get_strings = mv88e6320_stats_get_strings,
3434 .stats_get_stats = mv88e6390_stats_get_stats,
3435 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3436 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3439 static const struct mv88e6xxx_ops mv88e6240_ops = {
3440 /* MV88E6XXX_FAMILY_6352 */
3441 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3442 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3443 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3444 .phy_read = mv88e6xxx_g2_smi_phy_read,
3445 .phy_write = mv88e6xxx_g2_smi_phy_write,
3446 .port_set_link = mv88e6xxx_port_set_link,
3447 .port_set_duplex = mv88e6xxx_port_set_duplex,
3448 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3449 .port_set_speed = mv88e6352_port_set_speed,
3450 .port_tag_remap = mv88e6095_port_tag_remap,
3451 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3452 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3453 .stats_get_strings = mv88e6095_stats_get_strings,
3454 .stats_get_stats = mv88e6095_stats_get_stats,
3455 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3456 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3459 static const struct mv88e6xxx_ops mv88e6290_ops = {
3460 /* MV88E6XXX_FAMILY_6390 */
3461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3462 .phy_read = mv88e6xxx_g2_smi_phy_read,
3463 .phy_write = mv88e6xxx_g2_smi_phy_write,
3464 .port_set_link = mv88e6xxx_port_set_link,
3465 .port_set_duplex = mv88e6xxx_port_set_duplex,
3466 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3467 .port_set_speed = mv88e6390_port_set_speed,
3468 .port_tag_remap = mv88e6390_port_tag_remap,
3469 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3470 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3471 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3472 .stats_get_strings = mv88e6320_stats_get_strings,
3473 .stats_get_stats = mv88e6390_stats_get_stats,
3474 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3475 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3478 static const struct mv88e6xxx_ops mv88e6320_ops = {
3479 /* MV88E6XXX_FAMILY_6320 */
3480 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3481 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3482 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3483 .phy_read = mv88e6xxx_g2_smi_phy_read,
3484 .phy_write = mv88e6xxx_g2_smi_phy_write,
3485 .port_set_link = mv88e6xxx_port_set_link,
3486 .port_set_duplex = mv88e6xxx_port_set_duplex,
3487 .port_set_speed = mv88e6185_port_set_speed,
3488 .port_tag_remap = mv88e6095_port_tag_remap,
3489 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3490 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3491 .stats_get_strings = mv88e6320_stats_get_strings,
3492 .stats_get_stats = mv88e6320_stats_get_stats,
3493 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3494 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3497 static const struct mv88e6xxx_ops mv88e6321_ops = {
3498 /* MV88E6XXX_FAMILY_6321 */
3499 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3500 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3501 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3502 .phy_read = mv88e6xxx_g2_smi_phy_read,
3503 .phy_write = mv88e6xxx_g2_smi_phy_write,
3504 .port_set_link = mv88e6xxx_port_set_link,
3505 .port_set_duplex = mv88e6xxx_port_set_duplex,
3506 .port_set_speed = mv88e6185_port_set_speed,
3507 .port_tag_remap = mv88e6095_port_tag_remap,
3508 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3509 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3510 .stats_get_strings = mv88e6320_stats_get_strings,
3511 .stats_get_stats = mv88e6320_stats_get_stats,
3512 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3513 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3516 static const struct mv88e6xxx_ops mv88e6350_ops = {
3517 /* MV88E6XXX_FAMILY_6351 */
3518 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3519 .phy_read = mv88e6xxx_g2_smi_phy_read,
3520 .phy_write = mv88e6xxx_g2_smi_phy_write,
3521 .port_set_link = mv88e6xxx_port_set_link,
3522 .port_set_duplex = mv88e6xxx_port_set_duplex,
3523 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3524 .port_set_speed = mv88e6185_port_set_speed,
3525 .port_tag_remap = mv88e6095_port_tag_remap,
3526 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3527 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3528 .stats_get_strings = mv88e6095_stats_get_strings,
3529 .stats_get_stats = mv88e6095_stats_get_stats,
3530 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3531 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3534 static const struct mv88e6xxx_ops mv88e6351_ops = {
3535 /* MV88E6XXX_FAMILY_6351 */
3536 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3537 .phy_read = mv88e6xxx_g2_smi_phy_read,
3538 .phy_write = mv88e6xxx_g2_smi_phy_write,
3539 .port_set_link = mv88e6xxx_port_set_link,
3540 .port_set_duplex = mv88e6xxx_port_set_duplex,
3541 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3542 .port_set_speed = mv88e6185_port_set_speed,
3543 .port_tag_remap = mv88e6095_port_tag_remap,
3544 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3545 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3546 .stats_get_strings = mv88e6095_stats_get_strings,
3547 .stats_get_stats = mv88e6095_stats_get_stats,
3548 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3549 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3552 static const struct mv88e6xxx_ops mv88e6352_ops = {
3553 /* MV88E6XXX_FAMILY_6352 */
3554 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3555 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3557 .phy_read = mv88e6xxx_g2_smi_phy_read,
3558 .phy_write = mv88e6xxx_g2_smi_phy_write,
3559 .port_set_link = mv88e6xxx_port_set_link,
3560 .port_set_duplex = mv88e6xxx_port_set_duplex,
3561 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3562 .port_set_speed = mv88e6352_port_set_speed,
3563 .port_tag_remap = mv88e6095_port_tag_remap,
3564 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3565 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3566 .stats_get_strings = mv88e6095_stats_get_strings,
3567 .stats_get_stats = mv88e6095_stats_get_stats,
3568 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3569 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3572 static const struct mv88e6xxx_ops mv88e6390_ops = {
3573 /* MV88E6XXX_FAMILY_6390 */
3574 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3575 .phy_read = mv88e6xxx_g2_smi_phy_read,
3576 .phy_write = mv88e6xxx_g2_smi_phy_write,
3577 .port_set_link = mv88e6xxx_port_set_link,
3578 .port_set_duplex = mv88e6xxx_port_set_duplex,
3579 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3580 .port_set_speed = mv88e6390_port_set_speed,
3581 .port_tag_remap = mv88e6390_port_tag_remap,
3582 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3583 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3584 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3585 .stats_get_strings = mv88e6320_stats_get_strings,
3586 .stats_get_stats = mv88e6390_stats_get_stats,
3587 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3588 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3591 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3592 /* MV88E6XXX_FAMILY_6390 */
3593 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3594 .phy_read = mv88e6xxx_g2_smi_phy_read,
3595 .phy_write = mv88e6xxx_g2_smi_phy_write,
3596 .port_set_link = mv88e6xxx_port_set_link,
3597 .port_set_duplex = mv88e6xxx_port_set_duplex,
3598 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3599 .port_set_speed = mv88e6390x_port_set_speed,
3600 .port_tag_remap = mv88e6390_port_tag_remap,
3601 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3602 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3603 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3604 .stats_get_strings = mv88e6320_stats_get_strings,
3605 .stats_get_stats = mv88e6390_stats_get_stats,
3606 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3607 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3610 static const struct mv88e6xxx_ops mv88e6391_ops = {
3611 /* MV88E6XXX_FAMILY_6390 */
3612 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3613 .phy_read = mv88e6xxx_g2_smi_phy_read,
3614 .phy_write = mv88e6xxx_g2_smi_phy_write,
3615 .port_set_link = mv88e6xxx_port_set_link,
3616 .port_set_duplex = mv88e6xxx_port_set_duplex,
3617 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3618 .port_set_speed = mv88e6390_port_set_speed,
3619 .port_tag_remap = mv88e6390_port_tag_remap,
3620 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3621 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3622 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3623 .stats_get_strings = mv88e6320_stats_get_strings,
3624 .stats_get_stats = mv88e6390_stats_get_stats,
3625 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3626 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3629 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3631 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3632 .family = MV88E6XXX_FAMILY_6097,
3633 .name = "Marvell 88E6085",
3634 .num_databases = 4096,
3636 .port_base_addr = 0x10,
3637 .global1_addr = 0x1b,
3638 .age_time_coeff = 15000,
3640 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3641 .ops = &mv88e6085_ops,
3645 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3646 .family = MV88E6XXX_FAMILY_6095,
3647 .name = "Marvell 88E6095/88E6095F",
3648 .num_databases = 256,
3650 .port_base_addr = 0x10,
3651 .global1_addr = 0x1b,
3652 .age_time_coeff = 15000,
3654 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3655 .ops = &mv88e6095_ops,
3659 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3660 .family = MV88E6XXX_FAMILY_6097,
3661 .name = "Marvell 88E6097/88E6097F",
3662 .num_databases = 4096,
3664 .port_base_addr = 0x10,
3665 .global1_addr = 0x1b,
3666 .age_time_coeff = 15000,
3668 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3669 .ops = &mv88e6097_ops,
3673 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3674 .family = MV88E6XXX_FAMILY_6165,
3675 .name = "Marvell 88E6123",
3676 .num_databases = 4096,
3678 .port_base_addr = 0x10,
3679 .global1_addr = 0x1b,
3680 .age_time_coeff = 15000,
3682 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3683 .ops = &mv88e6123_ops,
3687 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3688 .family = MV88E6XXX_FAMILY_6185,
3689 .name = "Marvell 88E6131",
3690 .num_databases = 256,
3692 .port_base_addr = 0x10,
3693 .global1_addr = 0x1b,
3694 .age_time_coeff = 15000,
3696 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3697 .ops = &mv88e6131_ops,
3701 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3702 .family = MV88E6XXX_FAMILY_6165,
3703 .name = "Marvell 88E6161",
3704 .num_databases = 4096,
3706 .port_base_addr = 0x10,
3707 .global1_addr = 0x1b,
3708 .age_time_coeff = 15000,
3710 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3711 .ops = &mv88e6161_ops,
3715 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3716 .family = MV88E6XXX_FAMILY_6165,
3717 .name = "Marvell 88E6165",
3718 .num_databases = 4096,
3720 .port_base_addr = 0x10,
3721 .global1_addr = 0x1b,
3722 .age_time_coeff = 15000,
3724 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3725 .ops = &mv88e6165_ops,
3729 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3730 .family = MV88E6XXX_FAMILY_6351,
3731 .name = "Marvell 88E6171",
3732 .num_databases = 4096,
3734 .port_base_addr = 0x10,
3735 .global1_addr = 0x1b,
3736 .age_time_coeff = 15000,
3738 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3739 .ops = &mv88e6171_ops,
3743 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3744 .family = MV88E6XXX_FAMILY_6352,
3745 .name = "Marvell 88E6172",
3746 .num_databases = 4096,
3748 .port_base_addr = 0x10,
3749 .global1_addr = 0x1b,
3750 .age_time_coeff = 15000,
3752 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3753 .ops = &mv88e6172_ops,
3757 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3758 .family = MV88E6XXX_FAMILY_6351,
3759 .name = "Marvell 88E6175",
3760 .num_databases = 4096,
3762 .port_base_addr = 0x10,
3763 .global1_addr = 0x1b,
3764 .age_time_coeff = 15000,
3766 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3767 .ops = &mv88e6175_ops,
3771 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3772 .family = MV88E6XXX_FAMILY_6352,
3773 .name = "Marvell 88E6176",
3774 .num_databases = 4096,
3776 .port_base_addr = 0x10,
3777 .global1_addr = 0x1b,
3778 .age_time_coeff = 15000,
3780 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3781 .ops = &mv88e6176_ops,
3785 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3786 .family = MV88E6XXX_FAMILY_6185,
3787 .name = "Marvell 88E6185",
3788 .num_databases = 256,
3790 .port_base_addr = 0x10,
3791 .global1_addr = 0x1b,
3792 .age_time_coeff = 15000,
3794 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3795 .ops = &mv88e6185_ops,
3799 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3800 .family = MV88E6XXX_FAMILY_6390,
3801 .name = "Marvell 88E6190",
3802 .num_databases = 4096,
3803 .num_ports = 11, /* 10 + Z80 */
3804 .port_base_addr = 0x0,
3805 .global1_addr = 0x1b,
3806 .age_time_coeff = 15000,
3808 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3809 .ops = &mv88e6190_ops,
3813 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3814 .family = MV88E6XXX_FAMILY_6390,
3815 .name = "Marvell 88E6190X",
3816 .num_databases = 4096,
3817 .num_ports = 11, /* 10 + Z80 */
3818 .port_base_addr = 0x0,
3819 .global1_addr = 0x1b,
3820 .age_time_coeff = 15000,
3822 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3823 .ops = &mv88e6190x_ops,
3827 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3828 .family = MV88E6XXX_FAMILY_6390,
3829 .name = "Marvell 88E6191",
3830 .num_databases = 4096,
3831 .num_ports = 11, /* 10 + Z80 */
3832 .port_base_addr = 0x0,
3833 .global1_addr = 0x1b,
3834 .age_time_coeff = 15000,
3835 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3836 .ops = &mv88e6391_ops,
3840 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3841 .family = MV88E6XXX_FAMILY_6352,
3842 .name = "Marvell 88E6240",
3843 .num_databases = 4096,
3845 .port_base_addr = 0x10,
3846 .global1_addr = 0x1b,
3847 .age_time_coeff = 15000,
3849 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3850 .ops = &mv88e6240_ops,
3854 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3855 .family = MV88E6XXX_FAMILY_6390,
3856 .name = "Marvell 88E6290",
3857 .num_databases = 4096,
3858 .num_ports = 11, /* 10 + Z80 */
3859 .port_base_addr = 0x0,
3860 .global1_addr = 0x1b,
3861 .age_time_coeff = 15000,
3863 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3864 .ops = &mv88e6290_ops,
3868 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3869 .family = MV88E6XXX_FAMILY_6320,
3870 .name = "Marvell 88E6320",
3871 .num_databases = 4096,
3873 .port_base_addr = 0x10,
3874 .global1_addr = 0x1b,
3875 .age_time_coeff = 15000,
3877 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3878 .ops = &mv88e6320_ops,
3882 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3883 .family = MV88E6XXX_FAMILY_6320,
3884 .name = "Marvell 88E6321",
3885 .num_databases = 4096,
3887 .port_base_addr = 0x10,
3888 .global1_addr = 0x1b,
3889 .age_time_coeff = 15000,
3891 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3892 .ops = &mv88e6321_ops,
3896 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3897 .family = MV88E6XXX_FAMILY_6351,
3898 .name = "Marvell 88E6350",
3899 .num_databases = 4096,
3901 .port_base_addr = 0x10,
3902 .global1_addr = 0x1b,
3903 .age_time_coeff = 15000,
3905 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3906 .ops = &mv88e6350_ops,
3910 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3911 .family = MV88E6XXX_FAMILY_6351,
3912 .name = "Marvell 88E6351",
3913 .num_databases = 4096,
3915 .port_base_addr = 0x10,
3916 .global1_addr = 0x1b,
3917 .age_time_coeff = 15000,
3919 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3920 .ops = &mv88e6351_ops,
3924 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3925 .family = MV88E6XXX_FAMILY_6352,
3926 .name = "Marvell 88E6352",
3927 .num_databases = 4096,
3929 .port_base_addr = 0x10,
3930 .global1_addr = 0x1b,
3931 .age_time_coeff = 15000,
3933 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3934 .ops = &mv88e6352_ops,
3937 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
3938 .family = MV88E6XXX_FAMILY_6390,
3939 .name = "Marvell 88E6390",
3940 .num_databases = 4096,
3941 .num_ports = 11, /* 10 + Z80 */
3942 .port_base_addr = 0x0,
3943 .global1_addr = 0x1b,
3944 .age_time_coeff = 15000,
3946 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3947 .ops = &mv88e6390_ops,
3950 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
3951 .family = MV88E6XXX_FAMILY_6390,
3952 .name = "Marvell 88E6390X",
3953 .num_databases = 4096,
3954 .num_ports = 11, /* 10 + Z80 */
3955 .port_base_addr = 0x0,
3956 .global1_addr = 0x1b,
3957 .age_time_coeff = 15000,
3959 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3960 .ops = &mv88e6390x_ops,
3964 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3968 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3969 if (mv88e6xxx_table[i].prod_num == prod_num)
3970 return &mv88e6xxx_table[i];
3975 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3977 const struct mv88e6xxx_info *info;
3978 unsigned int prod_num, rev;
3982 mutex_lock(&chip->reg_lock);
3983 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3984 mutex_unlock(&chip->reg_lock);
3988 prod_num = (id & 0xfff0) >> 4;
3991 info = mv88e6xxx_lookup_info(prod_num);
3995 /* Update the compatible info with the probed one */
3998 err = mv88e6xxx_g2_require(chip);
4002 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4003 chip->info->prod_num, chip->info->name, rev);
4008 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4010 struct mv88e6xxx_chip *chip;
4012 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4018 mutex_init(&chip->reg_lock);
4023 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4025 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
4026 mv88e6xxx_ppu_state_init(chip);
4029 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4031 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
4032 mv88e6xxx_ppu_state_destroy(chip);
4035 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4036 struct mii_bus *bus, int sw_addr)
4038 /* ADDR[0] pin is unavailable externally and considered zero */
4043 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4044 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
4045 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4050 chip->sw_addr = sw_addr;
4055 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4057 struct mv88e6xxx_chip *chip = ds->priv;
4059 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
4060 return DSA_TAG_PROTO_EDSA;
4062 return DSA_TAG_PROTO_DSA;
4065 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4066 struct device *host_dev, int sw_addr,
4069 struct mv88e6xxx_chip *chip;
4070 struct mii_bus *bus;
4073 bus = dsa_host_dev_to_mii_bus(host_dev);
4077 chip = mv88e6xxx_alloc_chip(dsa_dev);
4081 /* Legacy SMI probing will only support chips similar to 88E6085 */
4082 chip->info = &mv88e6xxx_table[MV88E6085];
4084 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4088 err = mv88e6xxx_detect(chip);
4092 mutex_lock(&chip->reg_lock);
4093 err = mv88e6xxx_switch_reset(chip);
4094 mutex_unlock(&chip->reg_lock);
4098 mv88e6xxx_phy_init(chip);
4100 err = mv88e6xxx_mdio_register(chip, NULL);
4106 return chip->info->name;
4108 devm_kfree(dsa_dev, chip);
4113 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4114 const struct switchdev_obj_port_mdb *mdb,
4115 struct switchdev_trans *trans)
4117 /* We don't need any dynamic resource from the kernel (yet),
4118 * so skip the prepare phase.
4124 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4125 const struct switchdev_obj_port_mdb *mdb,
4126 struct switchdev_trans *trans)
4128 struct mv88e6xxx_chip *chip = ds->priv;
4130 mutex_lock(&chip->reg_lock);
4131 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4132 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4133 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4134 mutex_unlock(&chip->reg_lock);
4137 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4138 const struct switchdev_obj_port_mdb *mdb)
4140 struct mv88e6xxx_chip *chip = ds->priv;
4143 mutex_lock(&chip->reg_lock);
4144 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4145 GLOBAL_ATU_DATA_STATE_UNUSED);
4146 mutex_unlock(&chip->reg_lock);
4151 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4152 struct switchdev_obj_port_mdb *mdb,
4153 int (*cb)(struct switchdev_obj *obj))
4155 struct mv88e6xxx_chip *chip = ds->priv;
4158 mutex_lock(&chip->reg_lock);
4159 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4160 mutex_unlock(&chip->reg_lock);
4165 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
4166 .probe = mv88e6xxx_drv_probe,
4167 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4168 .setup = mv88e6xxx_setup,
4169 .set_addr = mv88e6xxx_set_addr,
4170 .adjust_link = mv88e6xxx_adjust_link,
4171 .get_strings = mv88e6xxx_get_strings,
4172 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4173 .get_sset_count = mv88e6xxx_get_sset_count,
4174 .set_eee = mv88e6xxx_set_eee,
4175 .get_eee = mv88e6xxx_get_eee,
4176 #ifdef CONFIG_NET_DSA_HWMON
4177 .get_temp = mv88e6xxx_get_temp,
4178 .get_temp_limit = mv88e6xxx_get_temp_limit,
4179 .set_temp_limit = mv88e6xxx_set_temp_limit,
4180 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4182 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4183 .get_eeprom = mv88e6xxx_get_eeprom,
4184 .set_eeprom = mv88e6xxx_set_eeprom,
4185 .get_regs_len = mv88e6xxx_get_regs_len,
4186 .get_regs = mv88e6xxx_get_regs,
4187 .set_ageing_time = mv88e6xxx_set_ageing_time,
4188 .port_bridge_join = mv88e6xxx_port_bridge_join,
4189 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4190 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4191 .port_fast_age = mv88e6xxx_port_fast_age,
4192 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4193 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4194 .port_vlan_add = mv88e6xxx_port_vlan_add,
4195 .port_vlan_del = mv88e6xxx_port_vlan_del,
4196 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4197 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4198 .port_fdb_add = mv88e6xxx_port_fdb_add,
4199 .port_fdb_del = mv88e6xxx_port_fdb_del,
4200 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4201 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4202 .port_mdb_add = mv88e6xxx_port_mdb_add,
4203 .port_mdb_del = mv88e6xxx_port_mdb_del,
4204 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4207 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4208 struct device_node *np)
4210 struct device *dev = chip->dev;
4211 struct dsa_switch *ds;
4213 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4219 ds->ops = &mv88e6xxx_switch_ops;
4221 dev_set_drvdata(dev, ds);
4223 return dsa_register_switch(ds, np);
4226 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4228 dsa_unregister_switch(chip->ds);
4231 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4233 struct device *dev = &mdiodev->dev;
4234 struct device_node *np = dev->of_node;
4235 const struct mv88e6xxx_info *compat_info;
4236 struct mv88e6xxx_chip *chip;
4240 compat_info = of_device_get_match_data(dev);
4244 chip = mv88e6xxx_alloc_chip(dev);
4248 chip->info = compat_info;
4250 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4254 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4255 if (IS_ERR(chip->reset))
4256 return PTR_ERR(chip->reset);
4258 err = mv88e6xxx_detect(chip);
4262 mv88e6xxx_phy_init(chip);
4264 if (chip->info->ops->get_eeprom &&
4265 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4266 chip->eeprom_len = eeprom_len;
4268 mutex_lock(&chip->reg_lock);
4269 err = mv88e6xxx_switch_reset(chip);
4270 mutex_unlock(&chip->reg_lock);
4274 chip->irq = of_irq_get(np, 0);
4275 if (chip->irq == -EPROBE_DEFER) {
4280 if (chip->irq > 0) {
4281 /* Has to be performed before the MDIO bus is created,
4282 * because the PHYs will link there interrupts to these
4283 * interrupt controllers
4285 mutex_lock(&chip->reg_lock);
4286 err = mv88e6xxx_g1_irq_setup(chip);
4287 mutex_unlock(&chip->reg_lock);
4292 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4293 err = mv88e6xxx_g2_irq_setup(chip);
4299 err = mv88e6xxx_mdio_register(chip, np);
4303 err = mv88e6xxx_register_switch(chip, np);
4310 mv88e6xxx_mdio_unregister(chip);
4312 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4313 mv88e6xxx_g2_irq_free(chip);
4315 if (chip->irq > 0) {
4316 mutex_lock(&chip->reg_lock);
4317 mv88e6xxx_g1_irq_free(chip);
4318 mutex_unlock(&chip->reg_lock);
4324 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4326 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4327 struct mv88e6xxx_chip *chip = ds->priv;
4329 mv88e6xxx_phy_destroy(chip);
4330 mv88e6xxx_unregister_switch(chip);
4331 mv88e6xxx_mdio_unregister(chip);
4333 if (chip->irq > 0) {
4334 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4335 mv88e6xxx_g2_irq_free(chip);
4336 mv88e6xxx_g1_irq_free(chip);
4340 static const struct of_device_id mv88e6xxx_of_match[] = {
4342 .compatible = "marvell,mv88e6085",
4343 .data = &mv88e6xxx_table[MV88E6085],
4346 .compatible = "marvell,mv88e6190",
4347 .data = &mv88e6xxx_table[MV88E6190],
4352 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4354 static struct mdio_driver mv88e6xxx_driver = {
4355 .probe = mv88e6xxx_probe,
4356 .remove = mv88e6xxx_remove,
4358 .name = "mv88e6085",
4359 .of_match_table = mv88e6xxx_of_match,
4363 static int __init mv88e6xxx_init(void)
4365 register_switch_driver(&mv88e6xxx_switch_ops);
4366 return mdio_driver_register(&mv88e6xxx_driver);
4368 module_init(mv88e6xxx_init);
4370 static void __exit mv88e6xxx_cleanup(void)
4372 mdio_driver_unregister(&mv88e6xxx_driver);
4373 unregister_switch_driver(&mv88e6xxx_switch_ops);
4375 module_exit(mv88e6xxx_cleanup);
4377 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4378 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4379 MODULE_LICENSE("GPL");