drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
 220                               int reg, u16 *val)
 221 {
 222         int addr = phy; /* PHY devices addresses start at 0x0 */
 223
 224         if (!chip->phy_ops)
 225                 return -EOPNOTSUPP;
 226
 227         return chip->phy_ops->read(chip, addr, reg, val);
 228 }
 229
 230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
 231                                int reg, u16 val)
 232 {
 233         int addr = phy; /* PHY devices addresses start at 0x0 */
 234
 235         if (!chip->phy_ops)
 236                 return -EOPNOTSUPP;
 237
 238         return chip->phy_ops->write(chip, addr, reg, val);
 239 }
 240
 241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 242 {
 243         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
 244                 return -EOPNOTSUPP;
 245
 246         return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 247 }
 248
 249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
 250 {
 251         int err;
 252
 253         /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
 254         err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
 255         if (unlikely(err)) {
 256                 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
 257                         phy, err);
 258         }
 259 }
 260
 261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
 262                                    u8 page, int reg, u16 *val)
 263 {
 264         int err;
 265
 266         /* There is no paging for registers 22 */
 267         if (reg == PHY_PAGE)
 268                 return -EINVAL;
 269
 270         err = mv88e6xxx_phy_page_get(chip, phy, page);
 271         if (!err) {
 272                 err = mv88e6xxx_phy_read(chip, phy, reg, val);
 273                 mv88e6xxx_phy_page_put(chip, phy);
 274         }
 275
 276         return err;
 277 }
 278
 279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
 280                                     u8 page, int reg, u16 val)
 281 {
 282         int err;
 283
 284         /* There is no paging for registers 22 */
 285         if (reg == PHY_PAGE)
 286                 return -EINVAL;
 287
 288         err = mv88e6xxx_phy_page_get(chip, phy, page);
 289         if (!err) {
 290                 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 291                 mv88e6xxx_phy_page_put(chip, phy);
 292         }
 293
 294         return err;
 295 }
 296
 297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 298 {
 299         return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 300                                        reg, val);
 301 }
 302
 303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 304 {
 305         return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 306                                         reg, val);
 307 }
 308
 309 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
 310                           u16 mask)
 311 {
 312         int i;
 313
 314         for (i = 0; i < 16; i++) {
 315                 u16 val;
 316                 int err;
 317
 318                 err = mv88e6xxx_read(chip, addr, reg, &val);
 319                 if (err)
 320                         return err;
 321
 322                 if (!(val & mask))
 323                         return 0;
 324
 325                 usleep_range(1000, 2000);
 326         }
 327
 328         return -ETIMEDOUT;
 329 }
 330
 331 /* Indirect write to single pointer-data register with an Update bit */
 332 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 333                             u16 update)
 334 {
 335         u16 val;
 336         int i, err;
 337
 338         /* Wait until the previous operation is completed */
 339         for (i = 0; i < 16; ++i) {
 340                 err = mv88e6xxx_read(chip, addr, reg, &val);
 341                 if (err)
 342                         return err;
 343
 344                 if (!(val & BIT(15)))
 345                         break;
 346         }
 347
 348         if (i == 16)
 349                 return -ETIMEDOUT;
 350
 351         /* Set the Update bit to trigger a write operation */
 352         val = BIT(15) | update;
 353
 354         return mv88e6xxx_write(chip, addr, reg, val);
 355 }
 356
 357 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 358 {
 359         u16 val;
 360         int err;
 361
 362         err = mv88e6xxx_read(chip, addr, reg, &val);
 363         if (err)
 364                 return err;
 365
 366         return val;
 367 }
 368
 369 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 370                                 int reg, u16 val)
 371 {
 372         return mv88e6xxx_write(chip, addr, reg, val);
 373 }
 374
 375 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 376 {
 377         int ret;
 378         int i;
 379
 380         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 381         if (ret < 0)
 382                 return ret;
 383
 384         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 385                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 386         if (ret)
 387                 return ret;
 388
 389         for (i = 0; i < 16; i++) {
 390                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 391                 if (ret < 0)
 392                         return ret;
 393
 394                 usleep_range(1000, 2000);
 395                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 396                     GLOBAL_STATUS_PPU_POLLING)
 397                         return 0;
 398         }
 399
 400         return -ETIMEDOUT;
 401 }
 402
 403 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 404 {
 405         int ret, err, i;
 406
 407         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 408         if (ret < 0)
 409                 return ret;
 410
 411         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 412                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 413         if (err)
 414                 return err;
 415
 416         for (i = 0; i < 16; i++) {
 417                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 418                 if (ret < 0)
 419                         return ret;
 420
 421                 usleep_range(1000, 2000);
 422                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 423                     GLOBAL_STATUS_PPU_POLLING)
 424                         return 0;
 425         }
 426
 427         return -ETIMEDOUT;
 428 }
 429
 430 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 431 {
 432         struct mv88e6xxx_chip *chip;
 433
 434         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 435
 436         mutex_lock(&chip->reg_lock);
 437
 438         if (mutex_trylock(&chip->ppu_mutex)) {
 439                 if (mv88e6xxx_ppu_enable(chip) == 0)
 440                         chip->ppu_disabled = 0;
 441                 mutex_unlock(&chip->ppu_mutex);
 442         }
 443
 444         mutex_unlock(&chip->reg_lock);
 445 }
 446
 447 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 448 {
 449         struct mv88e6xxx_chip *chip = (void *)_ps;
 450
 451         schedule_work(&chip->ppu_work);
 452 }
 453
 454 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 455 {
 456         int ret;
 457
 458         mutex_lock(&chip->ppu_mutex);
 459
 460         /* If the PHY polling unit is enabled, disable it so that
 461          * we can access the PHY registers.  If it was already
 462          * disabled, cancel the timer that is going to re-enable
 463          * it.
 464          */
 465         if (!chip->ppu_disabled) {
 466                 ret = mv88e6xxx_ppu_disable(chip);
 467                 if (ret < 0) {
 468                         mutex_unlock(&chip->ppu_mutex);
 469                         return ret;
 470                 }
 471                 chip->ppu_disabled = 1;
 472         } else {
 473                 del_timer(&chip->ppu_timer);
 474                 ret = 0;
 475         }
 476
 477         return ret;
 478 }
 479
 480 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 481 {
 482         /* Schedule a timer to re-enable the PHY polling unit. */
 483         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 484         mutex_unlock(&chip->ppu_mutex);
 485 }
 486
 487 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 488 {
 489         mutex_init(&chip->ppu_mutex);
 490         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 491         init_timer(&chip->ppu_timer);
 492         chip->ppu_timer.data = (unsigned long)chip;
 493         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 494 }
 495
 496 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
 497                                   int reg, u16 *val)
 498 {
 499         int err;
 500
 501         err = mv88e6xxx_ppu_access_get(chip);
 502         if (!err) {
 503                 err = mv88e6xxx_read(chip, addr, reg, val);
 504                 mv88e6xxx_ppu_access_put(chip);
 505         }
 506
 507         return err;
 508 }
 509
 510 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
 511                                    int reg, u16 val)
 512 {
 513         int err;
 514
 515         err = mv88e6xxx_ppu_access_get(chip);
 516         if (!err) {
 517                 err = mv88e6xxx_write(chip, addr, reg, val);
 518                 mv88e6xxx_ppu_access_put(chip);
 519         }
 520
 521         return err;
 522 }
 523
 524 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
 525         .read = mv88e6xxx_phy_ppu_read,
 526         .write = mv88e6xxx_phy_ppu_write,
 527 };
 528
 529 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 530 {
 531         return chip->info->family == MV88E6XXX_FAMILY_6065;
 532 }
 533
 534 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 535 {
 536         return chip->info->family == MV88E6XXX_FAMILY_6095;
 537 }
 538
 539 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 540 {
 541         return chip->info->family == MV88E6XXX_FAMILY_6097;
 542 }
 543
 544 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 545 {
 546         return chip->info->family == MV88E6XXX_FAMILY_6165;
 547 }
 548
 549 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 550 {
 551         return chip->info->family == MV88E6XXX_FAMILY_6185;
 552 }
 553
 554 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 555 {
 556         return chip->info->family == MV88E6XXX_FAMILY_6320;
 557 }
 558
 559 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 560 {
 561         return chip->info->family == MV88E6XXX_FAMILY_6351;
 562 }
 563
 564 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 565 {
 566         return chip->info->family == MV88E6XXX_FAMILY_6352;
 567 }
 568
 569 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 570 {
 571         return chip->info->num_databases;
 572 }
 573
 574 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 575 {
 576         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 577         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 578             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 579                 return true;
 580
 581         return false;
 582 }
 583
 584 /* We expect the switch to perform auto negotiation if there is a real
 585  * phy. However, in the case of a fixed link phy, we force the port
 586  * settings from the fixed link settings.
 587  */
 588 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 589                                   struct phy_device *phydev)
 590 {
 591         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 592         u32 reg;
 593         int ret;
 594
 595         if (!phy_is_pseudo_fixed_link(phydev))
 596                 return;
 597
 598         mutex_lock(&chip->reg_lock);
 599
 600         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 601         if (ret < 0)
 602                 goto out;
 603
 604         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 605                       PORT_PCS_CTRL_FORCE_LINK |
 606                       PORT_PCS_CTRL_DUPLEX_FULL |
 607                       PORT_PCS_CTRL_FORCE_DUPLEX |
 608                       PORT_PCS_CTRL_UNFORCED);
 609
 610         reg |= PORT_PCS_CTRL_FORCE_LINK;
 611         if (phydev->link)
 612                 reg |= PORT_PCS_CTRL_LINK_UP;
 613
 614         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 615                 goto out;
 616
 617         switch (phydev->speed) {
 618         case SPEED_1000:
 619                 reg |= PORT_PCS_CTRL_1000;
 620                 break;
 621         case SPEED_100:
 622                 reg |= PORT_PCS_CTRL_100;
 623                 break;
 624         case SPEED_10:
 625                 reg |= PORT_PCS_CTRL_10;
 626                 break;
 627         default:
 628                 pr_info("Unknown speed");
 629                 goto out;
 630         }
 631
 632         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 633         if (phydev->duplex == DUPLEX_FULL)
 634                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 635
 636         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 637             (port >= chip->info->num_ports - 2)) {
 638                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 639                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 640                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 641                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 642                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 643                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 644                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 645         }
 646         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 647
 648 out:
 649         mutex_unlock(&chip->reg_lock);
 650 }
 651
 652 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 653 {
 654         int ret;
 655         int i;
 656
 657         for (i = 0; i < 10; i++) {
 658                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 659                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 660                         return 0;
 661         }
 662
 663         return -ETIMEDOUT;
 664 }
 665
 666 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 667 {
 668         int ret;
 669
 670         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 671                 port = (port + 1) << 5;
 672
 673         /* Snapshot the hardware statistics counters for this port. */
 674         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 675                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 676                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 677         if (ret < 0)
 678                 return ret;
 679
 680         /* Wait for the snapshotting to complete. */
 681         ret = _mv88e6xxx_stats_wait(chip);
 682         if (ret < 0)
 683                 return ret;
 684
 685         return 0;
 686 }
 687
 688 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 689                                   int stat, u32 *val)
 690 {
 691         u32 _val;
 692         int ret;
 693
 694         *val = 0;
 695
 696         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 697                                    GLOBAL_STATS_OP_READ_CAPTURED |
 698                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 699         if (ret < 0)
 700                 return;
 701
 702         ret = _mv88e6xxx_stats_wait(chip);
 703         if (ret < 0)
 704                 return;
 705
 706         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 707         if (ret < 0)
 708                 return;
 709
 710         _val = ret << 16;
 711
 712         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 713         if (ret < 0)
 714                 return;
 715
 716         *val = _val | ret;
 717 }
 718
 719 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 720         { "in_good_octets",     8, 0x00, BANK0, },
 721         { "in_bad_octets",      4, 0x02, BANK0, },
 722         { "in_unicast",         4, 0x04, BANK0, },
 723         { "in_broadcasts",      4, 0x06, BANK0, },
 724         { "in_multicasts",      4, 0x07, BANK0, },
 725         { "in_pause",           4, 0x16, BANK0, },
 726         { "in_undersize",       4, 0x18, BANK0, },
 727         { "in_fragments",       4, 0x19, BANK0, },
 728         { "in_oversize",        4, 0x1a, BANK0, },
 729         { "in_jabber",          4, 0x1b, BANK0, },
 730         { "in_rx_error",        4, 0x1c, BANK0, },
 731         { "in_fcs_error",       4, 0x1d, BANK0, },
 732         { "out_octets",         8, 0x0e, BANK0, },
 733         { "out_unicast",        4, 0x10, BANK0, },
 734         { "out_broadcasts",     4, 0x13, BANK0, },
 735         { "out_multicasts",     4, 0x12, BANK0, },
 736         { "out_pause",          4, 0x15, BANK0, },
 737         { "excessive",          4, 0x11, BANK0, },
 738         { "collisions",         4, 0x1e, BANK0, },
 739         { "deferred",           4, 0x05, BANK0, },
 740         { "single",             4, 0x14, BANK0, },
 741         { "multiple",           4, 0x17, BANK0, },
 742         { "out_fcs_error",      4, 0x03, BANK0, },
 743         { "late",               4, 0x1f, BANK0, },
 744         { "hist_64bytes",       4, 0x08, BANK0, },
 745         { "hist_65_127bytes",   4, 0x09, BANK0, },
 746         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 747         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 748         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 749         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 750         { "sw_in_discards",     4, 0x10, PORT, },
 751         { "sw_in_filtered",     2, 0x12, PORT, },
 752         { "sw_out_filtered",    2, 0x13, PORT, },
 753         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 754         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 755         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 756         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 757         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 758         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 759         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 760         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 761         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 762         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 763         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 764         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 765         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 766         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 767         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 768         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 769         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 770         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 771         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 772         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 773         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 774         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 775         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 776         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 777         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 778         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 779 };
 780
 781 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 782                                struct mv88e6xxx_hw_stat *stat)
 783 {
 784         switch (stat->type) {
 785         case BANK0:
 786                 return true;
 787         case BANK1:
 788                 return mv88e6xxx_6320_family(chip);
 789         case PORT:
 790                 return mv88e6xxx_6095_family(chip) ||
 791                         mv88e6xxx_6185_family(chip) ||
 792                         mv88e6xxx_6097_family(chip) ||
 793                         mv88e6xxx_6165_family(chip) ||
 794                         mv88e6xxx_6351_family(chip) ||
 795                         mv88e6xxx_6352_family(chip);
 796         }
 797         return false;
 798 }
 799
 800 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 801                                             struct mv88e6xxx_hw_stat *s,
 802                                             int port)
 803 {
 804         u32 low;
 805         u32 high = 0;
 806         int ret;
 807         u64 value;
 808
 809         switch (s->type) {
 810         case PORT:
 811                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 812                 if (ret < 0)
 813                         return UINT64_MAX;
 814
 815                 low = ret;
 816                 if (s->sizeof_stat == 4) {
 817                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 818                                                   s->reg + 1);
 819                         if (ret < 0)
 820                                 return UINT64_MAX;
 821                         high = ret;
 822                 }
 823                 break;
 824         case BANK0:
 825         case BANK1:
 826                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 827                 if (s->sizeof_stat == 8)
 828                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 829         }
 830         value = (((u64)high) << 16) | low;
 831         return value;
 832 }
 833
 834 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 835                                   uint8_t *data)
 836 {
 837         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 838         struct mv88e6xxx_hw_stat *stat;
 839         int i, j;
 840
 841         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 842                 stat = &mv88e6xxx_hw_stats[i];
 843                 if (mv88e6xxx_has_stat(chip, stat)) {
 844                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 845                                ETH_GSTRING_LEN);
 846                         j++;
 847                 }
 848         }
 849 }
 850
 851 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 852 {
 853         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 854         struct mv88e6xxx_hw_stat *stat;
 855         int i, j;
 856
 857         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 858                 stat = &mv88e6xxx_hw_stats[i];
 859                 if (mv88e6xxx_has_stat(chip, stat))
 860                         j++;
 861         }
 862         return j;
 863 }
 864
 865 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 866                                         uint64_t *data)
 867 {
 868         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 869         struct mv88e6xxx_hw_stat *stat;
 870         int ret;
 871         int i, j;
 872
 873         mutex_lock(&chip->reg_lock);
 874
 875         ret = _mv88e6xxx_stats_snapshot(chip, port);
 876         if (ret < 0) {
 877                 mutex_unlock(&chip->reg_lock);
 878                 return;
 879         }
 880         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 881                 stat = &mv88e6xxx_hw_stats[i];
 882                 if (mv88e6xxx_has_stat(chip, stat)) {
 883                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 884                         j++;
 885                 }
 886         }
 887
 888         mutex_unlock(&chip->reg_lock);
 889 }
 890
 891 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 892 {
 893         return 32 * sizeof(u16);
 894 }
 895
 896 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 897                                struct ethtool_regs *regs, void *_p)
 898 {
 899         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 900         u16 *p = _p;
 901         int i;
 902
 903         regs->version = 0;
 904
 905         memset(p, 0xff, 32 * sizeof(u16));
 906
 907         mutex_lock(&chip->reg_lock);
 908
 909         for (i = 0; i < 32; i++) {
 910                 int ret;
 911
 912                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 913                 if (ret >= 0)
 914                         p[i] = ret;
 915         }
 916
 917         mutex_unlock(&chip->reg_lock);
 918 }
 919
 920 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 921 {
 922         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 923                               GLOBAL_ATU_OP_BUSY);
 924 }
 925
 926 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 927                              struct ethtool_eee *e)
 928 {
 929         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 930         u16 reg;
 931         int err;
 932
 933         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 934                 return -EOPNOTSUPP;
 935
 936         mutex_lock(&chip->reg_lock);
 937
 938         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 939         if (err)
 940                 goto out;
 941
 942         e->eee_enabled = !!(reg & 0x0200);
 943         e->tx_lpi_enabled = !!(reg & 0x0100);
 944
 945         err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
 946         if (err)
 947                 goto out;
 948
 949         e->eee_active = !!(reg & PORT_STATUS_EEE);
 950 out:
 951         mutex_unlock(&chip->reg_lock);
 952
 953         return err;
 954 }
 955
 956 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 957                              struct phy_device *phydev, struct ethtool_eee *e)
 958 {
 959         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 960         u16 reg;
 961         int err;
 962
 963         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 964                 return -EOPNOTSUPP;
 965
 966         mutex_lock(&chip->reg_lock);
 967
 968         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 969         if (err)
 970                 goto out;
 971
 972         reg &= ~0x0300;
 973         if (e->eee_enabled)
 974                 reg |= 0x0200;
 975         if (e->tx_lpi_enabled)
 976                 reg |= 0x0100;
 977
 978         err = mv88e6xxx_phy_write(chip, port, 16, reg);
 979 out:
 980         mutex_unlock(&chip->reg_lock);
 981
 982         return err;
 983 }
 984
 985 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 986 {
 987         int ret;
 988
 989         if (mv88e6xxx_has_fid_reg(chip)) {
 990                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 991                                            fid);
 992                 if (ret < 0)
 993                         return ret;
 994         } else if (mv88e6xxx_num_databases(chip) == 256) {
 995                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 996                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
 997                 if (ret < 0)
 998                         return ret;
 999
1000                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1001                                            (ret & 0xfff) |
1002                                            ((fid << 8) & 0xf000));
1003                 if (ret < 0)
1004                         return ret;
1005
1006                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1007                 cmd |= fid & 0xf;
1008         }
1009
1010         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1011         if (ret < 0)
1012                 return ret;
1013
1014         return _mv88e6xxx_atu_wait(chip);
1015 }
1016
1017 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1018                                      struct mv88e6xxx_atu_entry *entry)
1019 {
1020         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1021
1022         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1023                 unsigned int mask, shift;
1024
1025                 if (entry->trunk) {
1026                         data |= GLOBAL_ATU_DATA_TRUNK;
1027                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1028                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1029                 } else {
1030                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1031                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1032                 }
1033
1034                 data |= (entry->portv_trunkid << shift) & mask;
1035         }
1036
1037         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1038 }
1039
1040 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1041                                      struct mv88e6xxx_atu_entry *entry,
1042                                      bool static_too)
1043 {
1044         int op;
1045         int err;
1046
1047         err = _mv88e6xxx_atu_wait(chip);
1048         if (err)
1049                 return err;
1050
1051         err = _mv88e6xxx_atu_data_write(chip, entry);
1052         if (err)
1053                 return err;
1054
1055         if (entry->fid) {
1056                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1057                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1058         } else {
1059                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1060                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1061         }
1062
1063         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1064 }
1065
1066 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1067                                 u16 fid, bool static_too)
1068 {
1069         struct mv88e6xxx_atu_entry entry = {
1070                 .fid = fid,
1071                 .state = 0, /* EntryState bits must be 0 */
1072         };
1073
1074         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1075 }
1076
1077 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1078                                int from_port, int to_port, bool static_too)
1079 {
1080         struct mv88e6xxx_atu_entry entry = {
1081                 .trunk = false,
1082                 .fid = fid,
1083         };
1084
1085         /* EntryState bits must be 0xF */
1086         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1087
1088         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1089         entry.portv_trunkid = (to_port & 0x0f) << 4;
1090         entry.portv_trunkid |= from_port & 0x0f;
1091
1092         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1093 }
1094
1095 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1096                                  int port, bool static_too)
1097 {
1098         /* Destination port 0xF means remove the entries */
1099         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1100 }
1101
1102 static const char * const mv88e6xxx_port_state_names[] = {
1103         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1104         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1105         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1106         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1107 };
1108
1109 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1110                                  u8 state)
1111 {
1112         struct dsa_switch *ds = chip->ds;
1113         int reg, ret = 0;
1114         u8 oldstate;
1115
1116         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1117         if (reg < 0)
1118                 return reg;
1119
1120         oldstate = reg & PORT_CONTROL_STATE_MASK;
1121
1122         if (oldstate != state) {
1123                 /* Flush forwarding database if we're moving a port
1124                  * from Learning or Forwarding state to Disabled or
1125                  * Blocking or Listening state.
1126                  */
1127                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1128                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1129                     (state == PORT_CONTROL_STATE_DISABLED ||
1130                      state == PORT_CONTROL_STATE_BLOCKING)) {
1131                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1132                         if (ret)
1133                                 return ret;
1134                 }
1135
1136                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1137                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1138                                            reg);
1139                 if (ret)
1140                         return ret;
1141
1142                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1143                            mv88e6xxx_port_state_names[state],
1144                            mv88e6xxx_port_state_names[oldstate]);
1145         }
1146
1147         return ret;
1148 }
1149
1150 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1151 {
1152         struct net_device *bridge = chip->ports[port].bridge_dev;
1153         const u16 mask = (1 << chip->info->num_ports) - 1;
1154         struct dsa_switch *ds = chip->ds;
1155         u16 output_ports = 0;
1156         int reg;
1157         int i;
1158
1159         /* allow CPU port or DSA link(s) to send frames to every port */
1160         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1161                 output_ports = mask;
1162         } else {
1163                 for (i = 0; i < chip->info->num_ports; ++i) {
1164                         /* allow sending frames to every group member */
1165                         if (bridge && chip->ports[i].bridge_dev == bridge)
1166                                 output_ports |= BIT(i);
1167
1168                         /* allow sending frames to CPU port and DSA link(s) */
1169                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1170                                 output_ports |= BIT(i);
1171                 }
1172         }
1173
1174         /* prevent frames from going back out of the port they came in on */
1175         output_ports &= ~BIT(port);
1176
1177         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1178         if (reg < 0)
1179                 return reg;
1180
1181         reg &= ~mask;
1182         reg |= output_ports & mask;
1183
1184         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1185 }
1186
1187 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1188                                          u8 state)
1189 {
1190         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1191         int stp_state;
1192         int err;
1193
1194         switch (state) {
1195         case BR_STATE_DISABLED:
1196                 stp_state = PORT_CONTROL_STATE_DISABLED;
1197                 break;
1198         case BR_STATE_BLOCKING:
1199         case BR_STATE_LISTENING:
1200                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1201                 break;
1202         case BR_STATE_LEARNING:
1203                 stp_state = PORT_CONTROL_STATE_LEARNING;
1204                 break;
1205         case BR_STATE_FORWARDING:
1206         default:
1207                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1208                 break;
1209         }
1210
1211         mutex_lock(&chip->reg_lock);
1212         err = _mv88e6xxx_port_state(chip, port, stp_state);
1213         mutex_unlock(&chip->reg_lock);
1214
1215         if (err)
1216                 netdev_err(ds->ports[port].netdev,
1217                            "failed to update state to %s\n",
1218                            mv88e6xxx_port_state_names[stp_state]);
1219 }
1220
1221 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1222                                 u16 *new, u16 *old)
1223 {
1224         struct dsa_switch *ds = chip->ds;
1225         u16 pvid;
1226         int ret;
1227
1228         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1229         if (ret < 0)
1230                 return ret;
1231
1232         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1233
1234         if (new) {
1235                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1236                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1237
1238                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1239                                            PORT_DEFAULT_VLAN, ret);
1240                 if (ret < 0)
1241                         return ret;
1242
1243                 netdev_dbg(ds->ports[port].netdev,
1244                            "DefaultVID %d (was %d)\n", *new, pvid);
1245         }
1246
1247         if (old)
1248                 *old = pvid;
1249
1250         return 0;
1251 }
1252
1253 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1254                                     int port, u16 *pvid)
1255 {
1256         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1257 }
1258
1259 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1260                                     int port, u16 pvid)
1261 {
1262         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1263 }
1264
1265 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1266 {
1267         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1268                               GLOBAL_VTU_OP_BUSY);
1269 }
1270
1271 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1272 {
1273         int ret;
1274
1275         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1276         if (ret < 0)
1277                 return ret;
1278
1279         return _mv88e6xxx_vtu_wait(chip);
1280 }
1281
1282 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1283 {
1284         int ret;
1285
1286         ret = _mv88e6xxx_vtu_wait(chip);
1287         if (ret < 0)
1288                 return ret;
1289
1290         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1291 }
1292
1293 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1294                                         struct mv88e6xxx_vtu_stu_entry *entry,
1295                                         unsigned int nibble_offset)
1296 {
1297         u16 regs[3];
1298         int i;
1299         int ret;
1300
1301         for (i = 0; i < 3; ++i) {
1302                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1303                                           GLOBAL_VTU_DATA_0_3 + i);
1304                 if (ret < 0)
1305                         return ret;
1306
1307                 regs[i] = ret;
1308         }
1309
1310         for (i = 0; i < chip->info->num_ports; ++i) {
1311                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1312                 u16 reg = regs[i / 4];
1313
1314                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1321                                    struct mv88e6xxx_vtu_stu_entry *entry)
1322 {
1323         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1324 }
1325
1326 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1327                                    struct mv88e6xxx_vtu_stu_entry *entry)
1328 {
1329         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1330 }
1331
1332 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1333                                          struct mv88e6xxx_vtu_stu_entry *entry,
1334                                          unsigned int nibble_offset)
1335 {
1336         u16 regs[3] = { 0 };
1337         int i;
1338         int ret;
1339
1340         for (i = 0; i < chip->info->num_ports; ++i) {
1341                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1342                 u8 data = entry->data[i];
1343
1344                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1345         }
1346
1347         for (i = 0; i < 3; ++i) {
1348                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1349                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1350                 if (ret < 0)
1351                         return ret;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1358                                     struct mv88e6xxx_vtu_stu_entry *entry)
1359 {
1360         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1361 }
1362
1363 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1364                                     struct mv88e6xxx_vtu_stu_entry *entry)
1365 {
1366         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1367 }
1368
1369 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1370 {
1371         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1372                                     vid & GLOBAL_VTU_VID_MASK);
1373 }
1374
1375 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1376                                   struct mv88e6xxx_vtu_stu_entry *entry)
1377 {
1378         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1379         int ret;
1380
1381         ret = _mv88e6xxx_vtu_wait(chip);
1382         if (ret < 0)
1383                 return ret;
1384
1385         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1386         if (ret < 0)
1387                 return ret;
1388
1389         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1390         if (ret < 0)
1391                 return ret;
1392
1393         next.vid = ret & GLOBAL_VTU_VID_MASK;
1394         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1395
1396         if (next.valid) {
1397                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1398                 if (ret < 0)
1399                         return ret;
1400
1401                 if (mv88e6xxx_has_fid_reg(chip)) {
1402                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1403                                                   GLOBAL_VTU_FID);
1404                         if (ret < 0)
1405                                 return ret;
1406
1407                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1408                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1409                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1410                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1411                          */
1412                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1413                                                   GLOBAL_VTU_OP);
1414                         if (ret < 0)
1415                                 return ret;
1416
1417                         next.fid = (ret & 0xf00) >> 4;
1418                         next.fid |= ret & 0xf;
1419                 }
1420
1421                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1422                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1423                                                   GLOBAL_VTU_SID);
1424                         if (ret < 0)
1425                                 return ret;
1426
1427                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1428                 }
1429         }
1430
1431         *entry = next;
1432         return 0;
1433 }
1434
1435 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1436                                     struct switchdev_obj_port_vlan *vlan,
1437                                     int (*cb)(struct switchdev_obj *obj))
1438 {
1439         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1440         struct mv88e6xxx_vtu_stu_entry next;
1441         u16 pvid;
1442         int err;
1443
1444         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1445                 return -EOPNOTSUPP;
1446
1447         mutex_lock(&chip->reg_lock);
1448
1449         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1450         if (err)
1451                 goto unlock;
1452
1453         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1454         if (err)
1455                 goto unlock;
1456
1457         do {
1458                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1459                 if (err)
1460                         break;
1461
1462                 if (!next.valid)
1463                         break;
1464
1465                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1466                         continue;
1467
1468                 /* reinit and dump this VLAN obj */
1469                 vlan->vid_begin = next.vid;
1470                 vlan->vid_end = next.vid;
1471                 vlan->flags = 0;
1472
1473                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1474                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1475
1476                 if (next.vid == pvid)
1477                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1478
1479                 err = cb(&vlan->obj);
1480                 if (err)
1481                         break;
1482         } while (next.vid < GLOBAL_VTU_VID_MASK);
1483
1484 unlock:
1485         mutex_unlock(&chip->reg_lock);
1486
1487         return err;
1488 }
1489
1490 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1491                                     struct mv88e6xxx_vtu_stu_entry *entry)
1492 {
1493         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1494         u16 reg = 0;
1495         int ret;
1496
1497         ret = _mv88e6xxx_vtu_wait(chip);
1498         if (ret < 0)
1499                 return ret;
1500
1501         if (!entry->valid)
1502                 goto loadpurge;
1503
1504         /* Write port member tags */
1505         ret = mv88e6xxx_vtu_data_write(chip, entry);
1506         if (ret < 0)
1507                 return ret;
1508
1509         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1510                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1511                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1512                                            reg);
1513                 if (ret < 0)
1514                         return ret;
1515         }
1516
1517         if (mv88e6xxx_has_fid_reg(chip)) {
1518                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1519                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1520                                            reg);
1521                 if (ret < 0)
1522                         return ret;
1523         } else if (mv88e6xxx_num_databases(chip) == 256) {
1524                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1525                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1526                  */
1527                 op |= (entry->fid & 0xf0) << 8;
1528                 op |= entry->fid & 0xf;
1529         }
1530
1531         reg = GLOBAL_VTU_VID_VALID;
1532 loadpurge:
1533         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1534         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1535         if (ret < 0)
1536                 return ret;
1537
1538         return _mv88e6xxx_vtu_cmd(chip, op);
1539 }
1540
1541 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1542                                   struct mv88e6xxx_vtu_stu_entry *entry)
1543 {
1544         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1545         int ret;
1546
1547         ret = _mv88e6xxx_vtu_wait(chip);
1548         if (ret < 0)
1549                 return ret;
1550
1551         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1552                                    sid & GLOBAL_VTU_SID_MASK);
1553         if (ret < 0)
1554                 return ret;
1555
1556         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1557         if (ret < 0)
1558                 return ret;
1559
1560         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1561         if (ret < 0)
1562                 return ret;
1563
1564         next.sid = ret & GLOBAL_VTU_SID_MASK;
1565
1566         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1567         if (ret < 0)
1568                 return ret;
1569
1570         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1571
1572         if (next.valid) {
1573                 ret = mv88e6xxx_stu_data_read(chip, &next);
1574                 if (ret < 0)
1575                         return ret;
1576         }
1577
1578         *entry = next;
1579         return 0;
1580 }
1581
1582 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1583                                     struct mv88e6xxx_vtu_stu_entry *entry)
1584 {
1585         u16 reg = 0;
1586         int ret;
1587
1588         ret = _mv88e6xxx_vtu_wait(chip);
1589         if (ret < 0)
1590                 return ret;
1591
1592         if (!entry->valid)
1593                 goto loadpurge;
1594
1595         /* Write port states */
1596         ret = mv88e6xxx_stu_data_write(chip, entry);
1597         if (ret < 0)
1598                 return ret;
1599
1600         reg = GLOBAL_VTU_VID_VALID;
1601 loadpurge:
1602         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1603         if (ret < 0)
1604                 return ret;
1605
1606         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1607         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1608         if (ret < 0)
1609                 return ret;
1610
1611         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1612 }
1613
1614 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1615                                u16 *new, u16 *old)
1616 {
1617         struct dsa_switch *ds = chip->ds;
1618         u16 upper_mask;
1619         u16 fid;
1620         int ret;
1621
1622         if (mv88e6xxx_num_databases(chip) == 4096)
1623                 upper_mask = 0xff;
1624         else if (mv88e6xxx_num_databases(chip) == 256)
1625                 upper_mask = 0xf;
1626         else
1627                 return -EOPNOTSUPP;
1628
1629         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1630         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1631         if (ret < 0)
1632                 return ret;
1633
1634         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1635
1636         if (new) {
1637                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1638                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1639
1640                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1641                                            ret);
1642                 if (ret < 0)
1643                         return ret;
1644         }
1645
1646         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1647         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1648         if (ret < 0)
1649                 return ret;
1650
1651         fid |= (ret & upper_mask) << 4;
1652
1653         if (new) {
1654                 ret &= ~upper_mask;
1655                 ret |= (*new >> 4) & upper_mask;
1656
1657                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1658                                            ret);
1659                 if (ret < 0)
1660                         return ret;
1661
1662                 netdev_dbg(ds->ports[port].netdev,
1663                            "FID %d (was %d)\n", *new, fid);
1664         }
1665
1666         if (old)
1667                 *old = fid;
1668
1669         return 0;
1670 }
1671
1672 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1673                                    int port, u16 *fid)
1674 {
1675         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1676 }
1677
1678 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1679                                    int port, u16 fid)
1680 {
1681         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1682 }
1683
1684 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1685 {
1686         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1687         struct mv88e6xxx_vtu_stu_entry vlan;
1688         int i, err;
1689
1690         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1691
1692         /* Set every FID bit used by the (un)bridged ports */
1693         for (i = 0; i < chip->info->num_ports; ++i) {
1694                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1695                 if (err)
1696                         return err;
1697
1698                 set_bit(*fid, fid_bitmap);
1699         }
1700
1701         /* Set every FID bit used by the VLAN entries */
1702         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1703         if (err)
1704                 return err;
1705
1706         do {
1707                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1708                 if (err)
1709                         return err;
1710
1711                 if (!vlan.valid)
1712                         break;
1713
1714                 set_bit(vlan.fid, fid_bitmap);
1715         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1716
1717         /* The reset value 0x000 is used to indicate that multiple address
1718          * databases are not needed. Return the next positive available.
1719          */
1720         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1721         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1722                 return -ENOSPC;
1723
1724         /* Clear the database */
1725         return _mv88e6xxx_atu_flush(chip, *fid, true);
1726 }
1727
1728 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1729                               struct mv88e6xxx_vtu_stu_entry *entry)
1730 {
1731         struct dsa_switch *ds = chip->ds;
1732         struct mv88e6xxx_vtu_stu_entry vlan = {
1733                 .valid = true,
1734                 .vid = vid,
1735         };
1736         int i, err;
1737
1738         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1739         if (err)
1740                 return err;
1741
1742         /* exclude all ports except the CPU and DSA ports */
1743         for (i = 0; i < chip->info->num_ports; ++i)
1744                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1745                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1746                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1747
1748         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1749             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1750                 struct mv88e6xxx_vtu_stu_entry vstp;
1751
1752                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1753                  * implemented, only one STU entry is needed to cover all VTU
1754                  * entries. Thus, validate the SID 0.
1755                  */
1756                 vlan.sid = 0;
1757                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1758                 if (err)
1759                         return err;
1760
1761                 if (vstp.sid != vlan.sid || !vstp.valid) {
1762                         memset(&vstp, 0, sizeof(vstp));
1763                         vstp.valid = true;
1764                         vstp.sid = vlan.sid;
1765
1766                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1767                         if (err)
1768                                 return err;
1769                 }
1770         }
1771
1772         *entry = vlan;
1773         return 0;
1774 }
1775
1776 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1777                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1778 {
1779         int err;
1780
1781         if (!vid)
1782                 return -EINVAL;
1783
1784         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1785         if (err)
1786                 return err;
1787
1788         err = _mv88e6xxx_vtu_getnext(chip, entry);
1789         if (err)
1790                 return err;
1791
1792         if (entry->vid != vid || !entry->valid) {
1793                 if (!creat)
1794                         return -EOPNOTSUPP;
1795                 /* -ENOENT would've been more appropriate, but switchdev expects
1796                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1797                  */
1798
1799                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1800         }
1801
1802         return err;
1803 }
1804
1805 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1806                                         u16 vid_begin, u16 vid_end)
1807 {
1808         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1809         struct mv88e6xxx_vtu_stu_entry vlan;
1810         int i, err;
1811
1812         if (!vid_begin)
1813                 return -EOPNOTSUPP;
1814
1815         mutex_lock(&chip->reg_lock);
1816
1817         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1818         if (err)
1819                 goto unlock;
1820
1821         do {
1822                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1823                 if (err)
1824                         goto unlock;
1825
1826                 if (!vlan.valid)
1827                         break;
1828
1829                 if (vlan.vid > vid_end)
1830                         break;
1831
1832                 for (i = 0; i < chip->info->num_ports; ++i) {
1833                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1834                                 continue;
1835
1836                         if (vlan.data[i] ==
1837                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1838                                 continue;
1839
1840                         if (chip->ports[i].bridge_dev ==
1841                             chip->ports[port].bridge_dev)
1842                                 break; /* same bridge, check next VLAN */
1843
1844                         netdev_warn(ds->ports[port].netdev,
1845                                     "hardware VLAN %d already used by %s\n",
1846                                     vlan.vid,
1847                                     netdev_name(chip->ports[i].bridge_dev));
1848                         err = -EOPNOTSUPP;
1849                         goto unlock;
1850                 }
1851         } while (vlan.vid < vid_end);
1852
1853 unlock:
1854         mutex_unlock(&chip->reg_lock);
1855
1856         return err;
1857 }
1858
1859 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1860         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1861         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1862         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1863         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1864 };
1865
1866 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1867                                          bool vlan_filtering)
1868 {
1869         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1870         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1871                 PORT_CONTROL_2_8021Q_DISABLED;
1872         int ret;
1873
1874         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1875                 return -EOPNOTSUPP;
1876
1877         mutex_lock(&chip->reg_lock);
1878
1879         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1880         if (ret < 0)
1881                 goto unlock;
1882
1883         old = ret & PORT_CONTROL_2_8021Q_MASK;
1884
1885         if (new != old) {
1886                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1887                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1888
1889                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1890                                            ret);
1891                 if (ret < 0)
1892                         goto unlock;
1893
1894                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1895                            mv88e6xxx_port_8021q_mode_names[new],
1896                            mv88e6xxx_port_8021q_mode_names[old]);
1897         }
1898
1899         ret = 0;
1900 unlock:
1901         mutex_unlock(&chip->reg_lock);
1902
1903         return ret;
1904 }
1905
1906 static int
1907 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1908                             const struct switchdev_obj_port_vlan *vlan,
1909                             struct switchdev_trans *trans)
1910 {
1911         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1912         int err;
1913
1914         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1915                 return -EOPNOTSUPP;
1916
1917         /* If the requested port doesn't belong to the same bridge as the VLAN
1918          * members, do not support it (yet) and fallback to software VLAN.
1919          */
1920         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1921                                            vlan->vid_end);
1922         if (err)
1923                 return err;
1924
1925         /* We don't need any dynamic resource from the kernel (yet),
1926          * so skip the prepare phase.
1927          */
1928         return 0;
1929 }
1930
1931 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1932                                     u16 vid, bool untagged)
1933 {
1934         struct mv88e6xxx_vtu_stu_entry vlan;
1935         int err;
1936
1937         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1938         if (err)
1939                 return err;
1940
1941         vlan.data[port] = untagged ?
1942                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1943                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1944
1945         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1946 }
1947
1948 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1949                                     const struct switchdev_obj_port_vlan *vlan,
1950                                     struct switchdev_trans *trans)
1951 {
1952         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1953         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1954         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1955         u16 vid;
1956
1957         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1958                 return;
1959
1960         mutex_lock(&chip->reg_lock);
1961
1962         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1963                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1964                         netdev_err(ds->ports[port].netdev,
1965                                    "failed to add VLAN %d%c\n",
1966                                    vid, untagged ? 'u' : 't');
1967
1968         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1969                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1970                            vlan->vid_end);
1971
1972         mutex_unlock(&chip->reg_lock);
1973 }
1974
1975 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1976                                     int port, u16 vid)
1977 {
1978         struct dsa_switch *ds = chip->ds;
1979         struct mv88e6xxx_vtu_stu_entry vlan;
1980         int i, err;
1981
1982         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1983         if (err)
1984                 return err;
1985
1986         /* Tell switchdev if this VLAN is handled in software */
1987         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1988                 return -EOPNOTSUPP;
1989
1990         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1991
1992         /* keep the VLAN unless all ports are excluded */
1993         vlan.valid = false;
1994         for (i = 0; i < chip->info->num_ports; ++i) {
1995                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1996                         continue;
1997
1998                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1999                         vlan.valid = true;
2000                         break;
2001                 }
2002         }
2003
2004         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2005         if (err)
2006                 return err;
2007
2008         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2009 }
2010
2011 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2012                                    const struct switchdev_obj_port_vlan *vlan)
2013 {
2014         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2015         u16 pvid, vid;
2016         int err = 0;
2017
2018         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2019                 return -EOPNOTSUPP;
2020
2021         mutex_lock(&chip->reg_lock);
2022
2023         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2024         if (err)
2025                 goto unlock;
2026
2027         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2028                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2029                 if (err)
2030                         goto unlock;
2031
2032                 if (vid == pvid) {
2033                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2034                         if (err)
2035                                 goto unlock;
2036                 }
2037         }
2038
2039 unlock:
2040         mutex_unlock(&chip->reg_lock);
2041
2042         return err;
2043 }
2044
2045 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2046                                     const unsigned char *addr)
2047 {
2048         int i, ret;
2049
2050         for (i = 0; i < 3; i++) {
2051                 ret = _mv88e6xxx_reg_write(
2052                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2053                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2054                 if (ret < 0)
2055                         return ret;
2056         }
2057
2058         return 0;
2059 }
2060
2061 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2062                                    unsigned char *addr)
2063 {
2064         int i, ret;
2065
2066         for (i = 0; i < 3; i++) {
2067                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2068                                           GLOBAL_ATU_MAC_01 + i);
2069                 if (ret < 0)
2070                         return ret;
2071                 addr[i * 2] = ret >> 8;
2072                 addr[i * 2 + 1] = ret & 0xff;
2073         }
2074
2075         return 0;
2076 }
2077
2078 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2079                                struct mv88e6xxx_atu_entry *entry)
2080 {
2081         int ret;
2082
2083         ret = _mv88e6xxx_atu_wait(chip);
2084         if (ret < 0)
2085                 return ret;
2086
2087         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2088         if (ret < 0)
2089                 return ret;
2090
2091         ret = _mv88e6xxx_atu_data_write(chip, entry);
2092         if (ret < 0)
2093                 return ret;
2094
2095         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2096 }
2097
2098 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2099                                     const unsigned char *addr, u16 vid,
2100                                     u8 state)
2101 {
2102         struct mv88e6xxx_atu_entry entry = { 0 };
2103         struct mv88e6xxx_vtu_stu_entry vlan;
2104         int err;
2105
2106         /* Null VLAN ID corresponds to the port private database */
2107         if (vid == 0)
2108                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2109         else
2110                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2111         if (err)
2112                 return err;
2113
2114         entry.fid = vlan.fid;
2115         entry.state = state;
2116         ether_addr_copy(entry.mac, addr);
2117         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2118                 entry.trunk = false;
2119                 entry.portv_trunkid = BIT(port);
2120         }
2121
2122         return _mv88e6xxx_atu_load(chip, &entry);
2123 }
2124
2125 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2126                                       const struct switchdev_obj_port_fdb *fdb,
2127                                       struct switchdev_trans *trans)
2128 {
2129         /* We don't need any dynamic resource from the kernel (yet),
2130          * so skip the prepare phase.
2131          */
2132         return 0;
2133 }
2134
2135 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2136                                    const struct switchdev_obj_port_fdb *fdb,
2137                                    struct switchdev_trans *trans)
2138 {
2139         int state = is_multicast_ether_addr(fdb->addr) ?
2140                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2141                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2142         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2143
2144         mutex_lock(&chip->reg_lock);
2145         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2146                 netdev_err(ds->ports[port].netdev,
2147                            "failed to load MAC address\n");
2148         mutex_unlock(&chip->reg_lock);
2149 }
2150
2151 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2152                                   const struct switchdev_obj_port_fdb *fdb)
2153 {
2154         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2155         int ret;
2156
2157         mutex_lock(&chip->reg_lock);
2158         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2159                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2160         mutex_unlock(&chip->reg_lock);
2161
2162         return ret;
2163 }
2164
2165 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2166                                   struct mv88e6xxx_atu_entry *entry)
2167 {
2168         struct mv88e6xxx_atu_entry next = { 0 };
2169         int ret;
2170
2171         next.fid = fid;
2172
2173         ret = _mv88e6xxx_atu_wait(chip);
2174         if (ret < 0)
2175                 return ret;
2176
2177         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2178         if (ret < 0)
2179                 return ret;
2180
2181         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2182         if (ret < 0)
2183                 return ret;
2184
2185         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2186         if (ret < 0)
2187                 return ret;
2188
2189         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2190         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2191                 unsigned int mask, shift;
2192
2193                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2194                         next.trunk = true;
2195                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2196                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2197                 } else {
2198                         next.trunk = false;
2199                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2200                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2201                 }
2202
2203                 next.portv_trunkid = (ret & mask) >> shift;
2204         }
2205
2206         *entry = next;
2207         return 0;
2208 }
2209
2210 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2211                                         u16 fid, u16 vid, int port,
2212                                         struct switchdev_obj_port_fdb *fdb,
2213                                         int (*cb)(struct switchdev_obj *obj))
2214 {
2215         struct mv88e6xxx_atu_entry addr = {
2216                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2217         };
2218         int err;
2219
2220         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2221         if (err)
2222                 return err;
2223
2224         do {
2225                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2226                 if (err)
2227                         break;
2228
2229                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2230                         break;
2231
2232                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2233                         bool is_static = addr.state ==
2234                                 (is_multicast_ether_addr(addr.mac) ?
2235                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2236                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2237
2238                         fdb->vid = vid;
2239                         ether_addr_copy(fdb->addr, addr.mac);
2240                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2241
2242                         err = cb(&fdb->obj);
2243                         if (err)
2244                                 break;
2245                 }
2246         } while (!is_broadcast_ether_addr(addr.mac));
2247
2248         return err;
2249 }
2250
2251 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2252                                    struct switchdev_obj_port_fdb *fdb,
2253                                    int (*cb)(struct switchdev_obj *obj))
2254 {
2255         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2256         struct mv88e6xxx_vtu_stu_entry vlan = {
2257                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2258         };
2259         u16 fid;
2260         int err;
2261
2262         mutex_lock(&chip->reg_lock);
2263
2264         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2265         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2266         if (err)
2267                 goto unlock;
2268
2269         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2270         if (err)
2271                 goto unlock;
2272
2273         /* Dump VLANs' Filtering Information Databases */
2274         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2275         if (err)
2276                 goto unlock;
2277
2278         do {
2279                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2280                 if (err)
2281                         break;
2282
2283                 if (!vlan.valid)
2284                         break;
2285
2286                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2287                                                    port, fdb, cb);
2288                 if (err)
2289                         break;
2290         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2291
2292 unlock:
2293         mutex_unlock(&chip->reg_lock);
2294
2295         return err;
2296 }
2297
2298 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2299                                       struct net_device *bridge)
2300 {
2301         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2302         int i, err = 0;
2303
2304         mutex_lock(&chip->reg_lock);
2305
2306         /* Assign the bridge and remap each port's VLANTable */
2307         chip->ports[port].bridge_dev = bridge;
2308
2309         for (i = 0; i < chip->info->num_ports; ++i) {
2310                 if (chip->ports[i].bridge_dev == bridge) {
2311                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2312                         if (err)
2313                                 break;
2314                 }
2315         }
2316
2317         mutex_unlock(&chip->reg_lock);
2318
2319         return err;
2320 }
2321
2322 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2323 {
2324         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2325         struct net_device *bridge = chip->ports[port].bridge_dev;
2326         int i;
2327
2328         mutex_lock(&chip->reg_lock);
2329
2330         /* Unassign the bridge and remap each port's VLANTable */
2331         chip->ports[port].bridge_dev = NULL;
2332
2333         for (i = 0; i < chip->info->num_ports; ++i)
2334                 if (i == port || chip->ports[i].bridge_dev == bridge)
2335                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2336                                 netdev_warn(ds->ports[i].netdev,
2337                                             "failed to remap\n");
2338
2339         mutex_unlock(&chip->reg_lock);
2340 }
2341
2342 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2343 {
2344         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2345         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2346         struct gpio_desc *gpiod = chip->reset;
2347         unsigned long timeout;
2348         int ret;
2349         int i;
2350
2351         /* Set all ports to the disabled state. */
2352         for (i = 0; i < chip->info->num_ports; i++) {
2353                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2354                 if (ret < 0)
2355                         return ret;
2356
2357                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2358                                            ret & 0xfffc);
2359                 if (ret)
2360                         return ret;
2361         }
2362
2363         /* Wait for transmit queues to drain. */
2364         usleep_range(2000, 4000);
2365
2366         /* If there is a gpio connected to the reset pin, toggle it */
2367         if (gpiod) {
2368                 gpiod_set_value_cansleep(gpiod, 1);
2369                 usleep_range(10000, 20000);
2370                 gpiod_set_value_cansleep(gpiod, 0);
2371                 usleep_range(10000, 20000);
2372         }
2373
2374         /* Reset the switch. Keep the PPU active if requested. The PPU
2375          * needs to be active to support indirect phy register access
2376          * through global registers 0x18 and 0x19.
2377          */
2378         if (ppu_active)
2379                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2380         else
2381                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2382         if (ret)
2383                 return ret;
2384
2385         /* Wait up to one second for reset to complete. */
2386         timeout = jiffies + 1 * HZ;
2387         while (time_before(jiffies, timeout)) {
2388                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2389                 if (ret < 0)
2390                         return ret;
2391
2392                 if ((ret & is_reset) == is_reset)
2393                         break;
2394                 usleep_range(1000, 2000);
2395         }
2396         if (time_after(jiffies, timeout))
2397                 ret = -ETIMEDOUT;
2398         else
2399                 ret = 0;
2400
2401         return ret;
2402 }
2403
2404 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2405 {
2406         u16 val;
2407         int err;
2408
2409         /* Clear Power Down bit */
2410         err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2411         if (err)
2412                 return err;
2413
2414         if (val & BMCR_PDOWN) {
2415                 val &= ~BMCR_PDOWN;
2416                 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2417         }
2418
2419         return err;
2420 }
2421
2422 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2423                                int reg, u16 *val)
2424 {
2425         int addr = chip->info->port_base_addr + port;
2426
2427         if (port >= chip->info->num_ports)
2428                 return -EINVAL;
2429
2430         return mv88e6xxx_read(chip, addr, reg, val);
2431 }
2432
2433 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2434 {
2435         struct dsa_switch *ds = chip->ds;
2436         int ret;
2437         u16 reg;
2438
2439         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2440             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2441             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2442             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2443                 /* MAC Forcing register: don't force link, speed,
2444                  * duplex or flow control state to any particular
2445                  * values on physical ports, but force the CPU port
2446                  * and all DSA ports to their maximum bandwidth and
2447                  * full duplex.
2448                  */
2449                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2450                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2451                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2452                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2453                                 PORT_PCS_CTRL_LINK_UP |
2454                                 PORT_PCS_CTRL_DUPLEX_FULL |
2455                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2456                         if (mv88e6xxx_6065_family(chip))
2457                                 reg |= PORT_PCS_CTRL_100;
2458                         else
2459                                 reg |= PORT_PCS_CTRL_1000;
2460                 } else {
2461                         reg |= PORT_PCS_CTRL_UNFORCED;
2462                 }
2463
2464                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2465                                            PORT_PCS_CTRL, reg);
2466                 if (ret)
2467                         return ret;
2468         }
2469
2470         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2471          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2472          * tunneling, determine priority by looking at 802.1p and IP
2473          * priority fields (IP prio has precedence), and set STP state
2474          * to Forwarding.
2475          *
2476          * If this is the CPU link, use DSA or EDSA tagging depending
2477          * on which tagging mode was configured.
2478          *
2479          * If this is a link to another switch, use DSA tagging mode.
2480          *
2481          * If this is the upstream port for this switch, enable
2482          * forwarding of unknown unicasts and multicasts.
2483          */
2484         reg = 0;
2485         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2486             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2487             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2488             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2489                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2490                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2491                 PORT_CONTROL_STATE_FORWARDING;
2492         if (dsa_is_cpu_port(ds, port)) {
2493                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2494                         reg |= PORT_CONTROL_DSA_TAG;
2495                 if (mv88e6xxx_6352_family(chip) ||
2496                     mv88e6xxx_6351_family(chip) ||
2497                     mv88e6xxx_6165_family(chip) ||
2498                     mv88e6xxx_6097_family(chip) ||
2499                     mv88e6xxx_6320_family(chip)) {
2500                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2501                                 PORT_CONTROL_FORWARD_UNKNOWN |
2502                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2503                 }
2504
2505                 if (mv88e6xxx_6352_family(chip) ||
2506                     mv88e6xxx_6351_family(chip) ||
2507                     mv88e6xxx_6165_family(chip) ||
2508                     mv88e6xxx_6097_family(chip) ||
2509                     mv88e6xxx_6095_family(chip) ||
2510                     mv88e6xxx_6065_family(chip) ||
2511                     mv88e6xxx_6185_family(chip) ||
2512                     mv88e6xxx_6320_family(chip)) {
2513                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2514                 }
2515         }
2516         if (dsa_is_dsa_port(ds, port)) {
2517                 if (mv88e6xxx_6095_family(chip) ||
2518                     mv88e6xxx_6185_family(chip))
2519                         reg |= PORT_CONTROL_DSA_TAG;
2520                 if (mv88e6xxx_6352_family(chip) ||
2521                     mv88e6xxx_6351_family(chip) ||
2522                     mv88e6xxx_6165_family(chip) ||
2523                     mv88e6xxx_6097_family(chip) ||
2524                     mv88e6xxx_6320_family(chip)) {
2525                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2526                 }
2527
2528                 if (port == dsa_upstream_port(ds))
2529                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2530                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2531         }
2532         if (reg) {
2533                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2534                                            PORT_CONTROL, reg);
2535                 if (ret)
2536                         return ret;
2537         }
2538
2539         /* If this port is connected to a SerDes, make sure the SerDes is not
2540          * powered down.
2541          */
2542         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2543                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2544                 if (ret < 0)
2545                         return ret;
2546                 ret &= PORT_STATUS_CMODE_MASK;
2547                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2548                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2549                     (ret == PORT_STATUS_CMODE_SGMII)) {
2550                         ret = mv88e6xxx_serdes_power_on(chip);
2551                         if (ret < 0)
2552                                 return ret;
2553                 }
2554         }
2555
2556         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2557          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2558          * untagged frames on this port, do a destination address lookup on all
2559          * received packets as usual, disable ARP mirroring and don't send a
2560          * copy of all transmitted/received frames on this port to the CPU.
2561          */
2562         reg = 0;
2563         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2564             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2565             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2566             mv88e6xxx_6185_family(chip))
2567                 reg = PORT_CONTROL_2_MAP_DA;
2568
2569         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2570             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2571                 reg |= PORT_CONTROL_2_JUMBO_10240;
2572
2573         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2574                 /* Set the upstream port this port should use */
2575                 reg |= dsa_upstream_port(ds);
2576                 /* enable forwarding of unknown multicast addresses to
2577                  * the upstream port
2578                  */
2579                 if (port == dsa_upstream_port(ds))
2580                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2581         }
2582
2583         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2584
2585         if (reg) {
2586                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2587                                            PORT_CONTROL_2, reg);
2588                 if (ret)
2589                         return ret;
2590         }
2591
2592         /* Port Association Vector: when learning source addresses
2593          * of packets, add the address to the address database using
2594          * a port bitmap that has only the bit for this port set and
2595          * the other bits clear.
2596          */
2597         reg = 1 << port;
2598         /* Disable learning for CPU port */
2599         if (dsa_is_cpu_port(ds, port))
2600                 reg = 0;
2601
2602         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2603                                    reg);
2604         if (ret)
2605                 return ret;
2606
2607         /* Egress rate control 2: disable egress rate control. */
2608         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2609                                    0x0000);
2610         if (ret)
2611                 return ret;
2612
2613         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2614             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2615             mv88e6xxx_6320_family(chip)) {
2616                 /* Do not limit the period of time that this port can
2617                  * be paused for by the remote end or the period of
2618                  * time that this port can pause the remote end.
2619                  */
2620                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2621                                            PORT_PAUSE_CTRL, 0x0000);
2622                 if (ret)
2623                         return ret;
2624
2625                 /* Port ATU control: disable limiting the number of
2626                  * address database entries that this port is allowed
2627                  * to use.
2628                  */
2629                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2630                                            PORT_ATU_CONTROL, 0x0000);
2631                 /* Priority Override: disable DA, SA and VTU priority
2632                  * override.
2633                  */
2634                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2635                                            PORT_PRI_OVERRIDE, 0x0000);
2636                 if (ret)
2637                         return ret;
2638
2639                 /* Port Ethertype: use the Ethertype DSA Ethertype
2640                  * value.
2641                  */
2642                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2643                                            PORT_ETH_TYPE, ETH_P_EDSA);
2644                 if (ret)
2645                         return ret;
2646                 /* Tag Remap: use an identity 802.1p prio -> switch
2647                  * prio mapping.
2648                  */
2649                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2650                                            PORT_TAG_REGMAP_0123, 0x3210);
2651                 if (ret)
2652                         return ret;
2653
2654                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2655                  * prio mapping.
2656                  */
2657                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2658                                            PORT_TAG_REGMAP_4567, 0x7654);
2659                 if (ret)
2660                         return ret;
2661         }
2662
2663         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2664             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2665             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2666             mv88e6xxx_6320_family(chip)) {
2667                 /* Rate Control: disable ingress rate limiting. */
2668                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2669                                            PORT_RATE_CONTROL, 0x0001);
2670                 if (ret)
2671                         return ret;
2672         }
2673
2674         /* Port Control 1: disable trunking, disable sending
2675          * learning messages to this port.
2676          */
2677         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2678                                    0x0000);
2679         if (ret)
2680                 return ret;
2681
2682         /* Port based VLAN map: give each port the same default address
2683          * database, and allow bidirectional communication between the
2684          * CPU and DSA port(s), and the other ports.
2685          */
2686         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2687         if (ret)
2688                 return ret;
2689
2690         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2691         if (ret)
2692                 return ret;
2693
2694         /* Default VLAN ID and priority: don't set a default VLAN
2695          * ID, and set the default packet priority to zero.
2696          */
2697         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2698                                    0x0000);
2699         if (ret)
2700                 return ret;
2701
2702         return 0;
2703 }
2704
2705 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2706 {
2707         int err;
2708
2709         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2710                               (addr[0] << 8) | addr[1]);
2711         if (err)
2712                 return err;
2713
2714         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2715                               (addr[2] << 8) | addr[3]);
2716         if (err)
2717                 return err;
2718
2719         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2720                                (addr[4] << 8) | addr[5]);
2721 }
2722
2723 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2724                                      unsigned int msecs)
2725 {
2726         const unsigned int coeff = chip->info->age_time_coeff;
2727         const unsigned int min = 0x01 * coeff;
2728         const unsigned int max = 0xff * coeff;
2729         u8 age_time;
2730         u16 val;
2731         int err;
2732
2733         if (msecs < min || msecs > max)
2734                 return -ERANGE;
2735
2736         /* Round to nearest multiple of coeff */
2737         age_time = (msecs + coeff / 2) / coeff;
2738
2739         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2740         if (err)
2741                 return err;
2742
2743         /* AgeTime is 11:4 bits */
2744         val &= ~0xff0;
2745         val |= age_time << 4;
2746
2747         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2748 }
2749
2750 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2751                                      unsigned int ageing_time)
2752 {
2753         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2754         int err;
2755
2756         mutex_lock(&chip->reg_lock);
2757         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2758         mutex_unlock(&chip->reg_lock);
2759
2760         return err;
2761 }
2762
2763 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2764 {
2765         struct dsa_switch *ds = chip->ds;
2766         u32 upstream_port = dsa_upstream_port(ds);
2767         u16 reg;
2768         int err;
2769
2770         /* Enable the PHY Polling Unit if present, don't discard any packets,
2771          * and mask all interrupt sources.
2772          */
2773         reg = 0;
2774         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2775             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2776                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2777
2778         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2779         if (err)
2780                 return err;
2781
2782         /* Configure the upstream port, and configure it as the port to which
2783          * ingress and egress and ARP monitor frames are to be sent.
2784          */
2785         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2786                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2787                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2788         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2789                                    reg);
2790         if (err)
2791                 return err;
2792
2793         /* Disable remote management, and set the switch's DSA device number. */
2794         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2795                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2796                                    (ds->index & 0x1f));
2797         if (err)
2798                 return err;
2799
2800         /* Clear all the VTU and STU entries */
2801         err = _mv88e6xxx_vtu_stu_flush(chip);
2802         if (err < 0)
2803                 return err;
2804
2805         /* Set the default address aging time to 5 minutes, and
2806          * enable address learn messages to be sent to all message
2807          * ports.
2808          */
2809         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2810                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2811         if (err)
2812                 return err;
2813
2814         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2815         if (err)
2816                 return err;
2817
2818         /* Clear all ATU entries */
2819         err = _mv88e6xxx_atu_flush(chip, 0, true);
2820         if (err)
2821                 return err;
2822
2823         /* Configure the IP ToS mapping registers. */
2824         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2825         if (err)
2826                 return err;
2827         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2828         if (err)
2829                 return err;
2830         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2831         if (err)
2832                 return err;
2833         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2834         if (err)
2835                 return err;
2836         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2837         if (err)
2838                 return err;
2839         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2840         if (err)
2841                 return err;
2842         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2843         if (err)
2844                 return err;
2845         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2846         if (err)
2847                 return err;
2848
2849         /* Configure the IEEE 802.1p priority mapping register. */
2850         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2851         if (err)
2852                 return err;
2853
2854         /* Clear the statistics counters for all ports */
2855         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2856                                    GLOBAL_STATS_OP_FLUSH_ALL);
2857         if (err)
2858                 return err;
2859
2860         /* Wait for the flush to complete. */
2861         err = _mv88e6xxx_stats_wait(chip);
2862         if (err)
2863                 return err;
2864
2865         return 0;
2866 }
2867
2868 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2869                                              int target, int port)
2870 {
2871         u16 val = (target << 8) | (port & 0xf);
2872
2873         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2874 }
2875
2876 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2877 {
2878         int target, port;
2879         int err;
2880
2881         /* Initialize the routing port to the 32 possible target devices */
2882         for (target = 0; target < 32; ++target) {
2883                 port = 0xf;
2884
2885                 if (target < DSA_MAX_SWITCHES) {
2886                         port = chip->ds->rtable[target];
2887                         if (port == DSA_RTABLE_NONE)
2888                                 port = 0xf;
2889                 }
2890
2891                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2892                 if (err)
2893                         break;
2894         }
2895
2896         return err;
2897 }
2898
2899 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2900                                          bool hask, u16 mask)
2901 {
2902         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2903         u16 val = (num << 12) | (mask & port_mask);
2904
2905         if (hask)
2906                 val |= GLOBAL2_TRUNK_MASK_HASK;
2907
2908         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2909 }
2910
2911 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2912                                             u16 map)
2913 {
2914         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2915         u16 val = (id << 11) | (map & port_mask);
2916
2917         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2918 }
2919
2920 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2921 {
2922         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2923         int i, err;
2924
2925         /* Clear all eight possible Trunk Mask vectors */
2926         for (i = 0; i < 8; ++i) {
2927                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2928                 if (err)
2929                         return err;
2930         }
2931
2932         /* Clear all sixteen possible Trunk ID routing vectors */
2933         for (i = 0; i < 16; ++i) {
2934                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2935                 if (err)
2936                         return err;
2937         }
2938
2939         return 0;
2940 }
2941
2942 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2943 {
2944         int port, err;
2945
2946         /* Init all Ingress Rate Limit resources of all ports */
2947         for (port = 0; port < chip->info->num_ports; ++port) {
2948                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2949                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2950                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2951                                       (port << 8));
2952                 if (err)
2953                         break;
2954
2955                 /* Wait for the operation to complete */
2956                 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2957                                      GLOBAL2_IRL_CMD_BUSY);
2958                 if (err)
2959                         break;
2960         }
2961
2962         return err;
2963 }
2964
2965 /* Indirect write to the Switch MAC/WoL/WoF register */
2966 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2967                                          unsigned int pointer, u8 data)
2968 {
2969         u16 val = (pointer << 8) | data;
2970
2971         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2972 }
2973
2974 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2975 {
2976         int i, err;
2977
2978         for (i = 0; i < 6; i++) {
2979                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2980                 if (err)
2981                         break;
2982         }
2983
2984         return err;
2985 }
2986
2987 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2988                                   u8 data)
2989 {
2990         u16 val = (pointer << 8) | (data & 0x7);
2991
2992         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2993 }
2994
2995 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2996 {
2997         int i, err;
2998
2999         /* Clear all sixteen possible Priority Override entries */
3000         for (i = 0; i < 16; i++) {
3001                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3002                 if (err)
3003                         break;
3004         }
3005
3006         return err;
3007 }
3008
3009 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3010 {
3011         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3012                               GLOBAL2_EEPROM_CMD_BUSY |
3013                               GLOBAL2_EEPROM_CMD_RUNNING);
3014 }
3015
3016 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3017 {
3018         int err;
3019
3020         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3021         if (err)
3022                 return err;
3023
3024         return mv88e6xxx_g2_eeprom_wait(chip);
3025 }
3026
3027 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3028                                       u8 addr, u16 *data)
3029 {
3030         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3031         int err;
3032
3033         err = mv88e6xxx_g2_eeprom_wait(chip);
3034         if (err)
3035                 return err;
3036
3037         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3038         if (err)
3039                 return err;
3040
3041         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3042 }
3043
3044 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3045                                        u8 addr, u16 data)
3046 {
3047         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3048         int err;
3049
3050         err = mv88e6xxx_g2_eeprom_wait(chip);
3051         if (err)
3052                 return err;
3053
3054         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3055         if (err)
3056                 return err;
3057
3058         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3059 }
3060
3061 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3062 {
3063         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3064                               GLOBAL2_SMI_PHY_CMD_BUSY);
3065 }
3066
3067 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3068 {
3069         int err;
3070
3071         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3072         if (err)
3073                 return err;
3074
3075         return mv88e6xxx_g2_smi_phy_wait(chip);
3076 }
3077
3078 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3079                                      int reg, u16 *val)
3080 {
3081         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3082         int err;
3083
3084         err = mv88e6xxx_g2_smi_phy_wait(chip);
3085         if (err)
3086                 return err;
3087
3088         err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3089         if (err)
3090                 return err;
3091
3092         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3093 }
3094
3095 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3096                                       int reg, u16 val)
3097 {
3098         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3099         int err;
3100
3101         err = mv88e6xxx_g2_smi_phy_wait(chip);
3102         if (err)
3103                 return err;
3104
3105         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3106         if (err)
3107                 return err;
3108
3109         return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3110 }
3111
3112 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3113         .read = mv88e6xxx_g2_smi_phy_read,
3114         .write = mv88e6xxx_g2_smi_phy_write,
3115 };
3116
3117 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3118 {
3119         u16 reg;
3120         int err;
3121
3122         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3123                 /* Consider the frames with reserved multicast destination
3124                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3125                  */
3126                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3127                                       0xffff);
3128                 if (err)
3129                         return err;
3130         }
3131
3132         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3133                 /* Consider the frames with reserved multicast destination
3134                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3135                  */
3136                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3137                                       0xffff);
3138                 if (err)
3139                         return err;
3140         }
3141
3142         /* Ignore removed tag data on doubly tagged packets, disable
3143          * flow control messages, force flow control priority to the
3144          * highest, and send all special multicast frames to the CPU
3145          * port at the highest priority.
3146          */
3147         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3148         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3149             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3150                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3151         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3152         if (err)
3153                 return err;
3154
3155         /* Program the DSA routing table. */
3156         err = mv88e6xxx_g2_set_device_mapping(chip);
3157         if (err)
3158                 return err;
3159
3160         /* Clear all trunk masks and mapping. */
3161         err = mv88e6xxx_g2_clear_trunk(chip);
3162         if (err)
3163                 return err;
3164
3165         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3166                 /* Disable ingress rate limiting by resetting all per port
3167                  * ingress rate limit resources to their initial state.
3168                  */
3169                 err = mv88e6xxx_g2_clear_irl(chip);
3170                         if (err)
3171                                 return err;
3172         }
3173
3174         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3175                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3176                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3177                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3178                 if (err)
3179                         return err;
3180         }
3181
3182         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3183                 /* Clear the priority override table. */
3184                 err = mv88e6xxx_g2_clear_pot(chip);
3185                 if (err)
3186                         return err;
3187         }
3188
3189         return 0;
3190 }
3191
3192 static int mv88e6xxx_setup(struct dsa_switch *ds)
3193 {
3194         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3195         int err;
3196         int i;
3197
3198         chip->ds = ds;
3199         ds->slave_mii_bus = chip->mdio_bus;
3200
3201         mutex_lock(&chip->reg_lock);
3202
3203         err = mv88e6xxx_switch_reset(chip);
3204         if (err)
3205                 goto unlock;
3206
3207         /* Setup Switch Port Registers */
3208         for (i = 0; i < chip->info->num_ports; i++) {
3209                 err = mv88e6xxx_setup_port(chip, i);
3210                 if (err)
3211                         goto unlock;
3212         }
3213
3214         /* Setup Switch Global 1 Registers */
3215         err = mv88e6xxx_g1_setup(chip);
3216         if (err)
3217                 goto unlock;
3218
3219         /* Setup Switch Global 2 Registers */
3220         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3221                 err = mv88e6xxx_g2_setup(chip);
3222                 if (err)
3223                         goto unlock;
3224         }
3225
3226 unlock:
3227         mutex_unlock(&chip->reg_lock);
3228
3229         return err;
3230 }
3231
3232 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3233 {
3234         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3235         int err;
3236
3237         mutex_lock(&chip->reg_lock);
3238
3239         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3240         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3241                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3242         else
3243                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3244
3245         mutex_unlock(&chip->reg_lock);
3246
3247         return err;
3248 }
3249
3250 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3251 {
3252         struct mv88e6xxx_chip *chip = bus->priv;
3253         u16 val;
3254         int err;
3255
3256         if (phy >= chip->info->num_ports)
3257                 return 0xffff;
3258
3259         mutex_lock(&chip->reg_lock);
3260         err = mv88e6xxx_phy_read(chip, phy, reg, &val);
3261         mutex_unlock(&chip->reg_lock);
3262
3263         return err ? err : val;
3264 }
3265
3266 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3267 {
3268         struct mv88e6xxx_chip *chip = bus->priv;
3269         int err;
3270
3271         if (phy >= chip->info->num_ports)
3272                 return 0xffff;
3273
3274         mutex_lock(&chip->reg_lock);
3275         err = mv88e6xxx_phy_write(chip, phy, reg, val);
3276         mutex_unlock(&chip->reg_lock);
3277
3278         return err;
3279 }
3280
3281 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3282                                    struct device_node *np)
3283 {
3284         static int index;
3285         struct mii_bus *bus;
3286         int err;
3287
3288         if (np)
3289                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3290
3291         bus = devm_mdiobus_alloc(chip->dev);
3292         if (!bus)
3293                 return -ENOMEM;
3294
3295         bus->priv = (void *)chip;
3296         if (np) {
3297                 bus->name = np->full_name;
3298                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3299         } else {
3300                 bus->name = "mv88e6xxx SMI";
3301                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3302         }
3303
3304         bus->read = mv88e6xxx_mdio_read;
3305         bus->write = mv88e6xxx_mdio_write;
3306         bus->parent = chip->dev;
3307
3308         if (chip->mdio_np)
3309                 err = of_mdiobus_register(bus, chip->mdio_np);
3310         else
3311                 err = mdiobus_register(bus);
3312         if (err) {
3313                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3314                 goto out;
3315         }
3316         chip->mdio_bus = bus;
3317
3318         return 0;
3319
3320 out:
3321         if (chip->mdio_np)
3322                 of_node_put(chip->mdio_np);
3323
3324         return err;
3325 }
3326
3327 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3328
3329 {
3330         struct mii_bus *bus = chip->mdio_bus;
3331
3332         mdiobus_unregister(bus);
3333
3334         if (chip->mdio_np)
3335                 of_node_put(chip->mdio_np);
3336 }
3337
3338 #ifdef CONFIG_NET_DSA_HWMON
3339
3340 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3341 {
3342         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3343         u16 val;
3344         int ret;
3345
3346         *temp = 0;
3347
3348         mutex_lock(&chip->reg_lock);
3349
3350         ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3351         if (ret < 0)
3352                 goto error;
3353
3354         /* Enable temperature sensor */
3355         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3356         if (ret < 0)
3357                 goto error;
3358
3359         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3360         if (ret < 0)
3361                 goto error;
3362
3363         /* Wait for temperature to stabilize */
3364         usleep_range(10000, 12000);
3365
3366         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3367         if (ret < 0)
3368                 goto error;
3369
3370         /* Disable temperature sensor */
3371         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3372         if (ret < 0)
3373                 goto error;
3374
3375         *temp = ((val & 0x1f) - 5) * 5;
3376
3377 error:
3378         mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3379         mutex_unlock(&chip->reg_lock);
3380         return ret;
3381 }
3382
3383 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3384 {
3385         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3386         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3387         u16 val;
3388         int ret;
3389
3390         *temp = 0;
3391
3392         mutex_lock(&chip->reg_lock);
3393         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3394         mutex_unlock(&chip->reg_lock);
3395         if (ret < 0)
3396                 return ret;
3397
3398         *temp = (val & 0xff) - 25;
3399
3400         return 0;
3401 }
3402
3403 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3404 {
3405         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3406
3407         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3408                 return -EOPNOTSUPP;
3409
3410         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3411                 return mv88e63xx_get_temp(ds, temp);
3412
3413         return mv88e61xx_get_temp(ds, temp);
3414 }
3415
3416 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3417 {
3418         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3419         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3420         u16 val;
3421         int ret;
3422
3423         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3424                 return -EOPNOTSUPP;
3425
3426         *temp = 0;
3427
3428         mutex_lock(&chip->reg_lock);
3429         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3430         mutex_unlock(&chip->reg_lock);
3431         if (ret < 0)
3432                 return ret;
3433
3434         *temp = (((val >> 8) & 0x1f) * 5) - 25;
3435
3436         return 0;
3437 }
3438
3439 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3440 {
3441         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3442         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3443         u16 val;
3444         int err;
3445
3446         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3447                 return -EOPNOTSUPP;
3448
3449         mutex_lock(&chip->reg_lock);
3450         err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3451         if (err)
3452                 goto unlock;
3453         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3454         err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3455                                        (val & 0xe0ff) | (temp << 8));
3456 unlock:
3457         mutex_unlock(&chip->reg_lock);
3458
3459         return err;
3460 }
3461
3462 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3463 {
3464         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3465         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3466         u16 val;
3467         int ret;
3468
3469         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3470                 return -EOPNOTSUPP;
3471
3472         *alarm = false;
3473
3474         mutex_lock(&chip->reg_lock);
3475         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3476         mutex_unlock(&chip->reg_lock);
3477         if (ret < 0)
3478                 return ret;
3479
3480         *alarm = !!(val & 0x40);
3481
3482         return 0;
3483 }
3484 #endif /* CONFIG_NET_DSA_HWMON */
3485
3486 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3487 {
3488         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3489
3490         return chip->eeprom_len;
3491 }
3492
3493 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3494                                   struct ethtool_eeprom *eeprom, u8 *data)
3495 {
3496         unsigned int offset = eeprom->offset;
3497         unsigned int len = eeprom->len;
3498         u16 val;
3499         int err;
3500
3501         eeprom->len = 0;
3502
3503         if (offset & 1) {
3504                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3505                 if (err)
3506                         return err;
3507
3508                 *data++ = (val >> 8) & 0xff;
3509
3510                 offset++;
3511                 len--;
3512                 eeprom->len++;
3513         }
3514
3515         while (len >= 2) {
3516                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3517                 if (err)
3518                         return err;
3519
3520                 *data++ = val & 0xff;
3521                 *data++ = (val >> 8) & 0xff;
3522
3523                 offset += 2;
3524                 len -= 2;
3525                 eeprom->len += 2;
3526         }
3527
3528         if (len) {
3529                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3530                 if (err)
3531                         return err;
3532
3533                 *data++ = val & 0xff;
3534
3535                 offset++;
3536                 len--;
3537                 eeprom->len++;
3538         }
3539
3540         return 0;
3541 }
3542
3543 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3544                                 struct ethtool_eeprom *eeprom, u8 *data)
3545 {
3546         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3547         int err;
3548
3549         mutex_lock(&chip->reg_lock);
3550
3551         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3552                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3553         else
3554                 err = -EOPNOTSUPP;
3555
3556         mutex_unlock(&chip->reg_lock);
3557
3558         if (err)
3559                 return err;
3560
3561         eeprom->magic = 0xc3ec4951;
3562
3563         return 0;
3564 }
3565
3566 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3567                                   struct ethtool_eeprom *eeprom, u8 *data)
3568 {
3569         unsigned int offset = eeprom->offset;
3570         unsigned int len = eeprom->len;
3571         u16 val;
3572         int err;
3573
3574         /* Ensure the RO WriteEn bit is set */
3575         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3576         if (err)
3577                 return err;
3578
3579         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3580                 return -EROFS;
3581
3582         eeprom->len = 0;
3583
3584         if (offset & 1) {
3585                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3586                 if (err)
3587                         return err;
3588
3589                 val = (*data++ << 8) | (val & 0xff);
3590
3591                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3592                 if (err)
3593                         return err;
3594
3595                 offset++;
3596                 len--;
3597                 eeprom->len++;
3598         }
3599
3600         while (len >= 2) {
3601                 val = *data++;
3602                 val |= *data++ << 8;
3603
3604                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3605                 if (err)
3606                         return err;
3607
3608                 offset += 2;
3609                 len -= 2;
3610                 eeprom->len += 2;
3611         }
3612
3613         if (len) {
3614                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3615                 if (err)
3616                         return err;
3617
3618                 val = (val & 0xff00) | *data++;
3619
3620                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3621                 if (err)
3622                         return err;
3623
3624                 offset++;
3625                 len--;
3626                 eeprom->len++;
3627         }
3628
3629         return 0;
3630 }
3631
3632 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3633                                 struct ethtool_eeprom *eeprom, u8 *data)
3634 {
3635         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3636         int err;
3637
3638         if (eeprom->magic != 0xc3ec4951)
3639                 return -EINVAL;
3640
3641         mutex_lock(&chip->reg_lock);
3642
3643         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3644                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3645         else
3646                 err = -EOPNOTSUPP;
3647
3648         mutex_unlock(&chip->reg_lock);
3649
3650         return err;
3651 }
3652
3653 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3654         [MV88E6085] = {
3655                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3656                 .family = MV88E6XXX_FAMILY_6097,
3657                 .name = "Marvell 88E6085",
3658                 .num_databases = 4096,
3659                 .num_ports = 10,
3660                 .port_base_addr = 0x10,
3661                 .age_time_coeff = 15000,
3662                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3663         },
3664
3665         [MV88E6095] = {
3666                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3667                 .family = MV88E6XXX_FAMILY_6095,
3668                 .name = "Marvell 88E6095/88E6095F",
3669                 .num_databases = 256,
3670                 .num_ports = 11,
3671                 .port_base_addr = 0x10,
3672                 .age_time_coeff = 15000,
3673                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3674         },
3675
3676         [MV88E6123] = {
3677                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3678                 .family = MV88E6XXX_FAMILY_6165,
3679                 .name = "Marvell 88E6123",
3680                 .num_databases = 4096,
3681                 .num_ports = 3,
3682                 .port_base_addr = 0x10,
3683                 .age_time_coeff = 15000,
3684                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3685         },
3686
3687         [MV88E6131] = {
3688                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3689                 .family = MV88E6XXX_FAMILY_6185,
3690                 .name = "Marvell 88E6131",
3691                 .num_databases = 256,
3692                 .num_ports = 8,
3693                 .port_base_addr = 0x10,
3694                 .age_time_coeff = 15000,
3695                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3696         },
3697
3698         [MV88E6161] = {
3699                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3700                 .family = MV88E6XXX_FAMILY_6165,
3701                 .name = "Marvell 88E6161",
3702                 .num_databases = 4096,
3703                 .num_ports = 6,
3704                 .port_base_addr = 0x10,
3705                 .age_time_coeff = 15000,
3706                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3707         },
3708
3709         [MV88E6165] = {
3710                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3711                 .family = MV88E6XXX_FAMILY_6165,
3712                 .name = "Marvell 88E6165",
3713                 .num_databases = 4096,
3714                 .num_ports = 6,
3715                 .port_base_addr = 0x10,
3716                 .age_time_coeff = 15000,
3717                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3718         },
3719
3720         [MV88E6171] = {
3721                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3722                 .family = MV88E6XXX_FAMILY_6351,
3723                 .name = "Marvell 88E6171",
3724                 .num_databases = 4096,
3725                 .num_ports = 7,
3726                 .port_base_addr = 0x10,
3727                 .age_time_coeff = 15000,
3728                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3729         },
3730
3731         [MV88E6172] = {
3732                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3733                 .family = MV88E6XXX_FAMILY_6352,
3734                 .name = "Marvell 88E6172",
3735                 .num_databases = 4096,
3736                 .num_ports = 7,
3737                 .port_base_addr = 0x10,
3738                 .age_time_coeff = 15000,
3739                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3740         },
3741
3742         [MV88E6175] = {
3743                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3744                 .family = MV88E6XXX_FAMILY_6351,
3745                 .name = "Marvell 88E6175",
3746                 .num_databases = 4096,
3747                 .num_ports = 7,
3748                 .port_base_addr = 0x10,
3749                 .age_time_coeff = 15000,
3750                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3751         },
3752
3753         [MV88E6176] = {
3754                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3755                 .family = MV88E6XXX_FAMILY_6352,
3756                 .name = "Marvell 88E6176",
3757                 .num_databases = 4096,
3758                 .num_ports = 7,
3759                 .port_base_addr = 0x10,
3760                 .age_time_coeff = 15000,
3761                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3762         },
3763
3764         [MV88E6185] = {
3765                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3766                 .family = MV88E6XXX_FAMILY_6185,
3767                 .name = "Marvell 88E6185",
3768                 .num_databases = 256,
3769                 .num_ports = 10,
3770                 .port_base_addr = 0x10,
3771                 .age_time_coeff = 15000,
3772                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3773         },
3774
3775         [MV88E6240] = {
3776                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3777                 .family = MV88E6XXX_FAMILY_6352,
3778                 .name = "Marvell 88E6240",
3779                 .num_databases = 4096,
3780                 .num_ports = 7,
3781                 .port_base_addr = 0x10,
3782                 .age_time_coeff = 15000,
3783                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3784         },
3785
3786         [MV88E6320] = {
3787                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3788                 .family = MV88E6XXX_FAMILY_6320,
3789                 .name = "Marvell 88E6320",
3790                 .num_databases = 4096,
3791                 .num_ports = 7,
3792                 .port_base_addr = 0x10,
3793                 .age_time_coeff = 15000,
3794                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3795         },
3796
3797         [MV88E6321] = {
3798                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3799                 .family = MV88E6XXX_FAMILY_6320,
3800                 .name = "Marvell 88E6321",
3801                 .num_databases = 4096,
3802                 .num_ports = 7,
3803                 .port_base_addr = 0x10,
3804                 .age_time_coeff = 15000,
3805                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3806         },
3807
3808         [MV88E6350] = {
3809                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3810                 .family = MV88E6XXX_FAMILY_6351,
3811                 .name = "Marvell 88E6350",
3812                 .num_databases = 4096,
3813                 .num_ports = 7,
3814                 .port_base_addr = 0x10,
3815                 .age_time_coeff = 15000,
3816                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3817         },
3818
3819         [MV88E6351] = {
3820                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3821                 .family = MV88E6XXX_FAMILY_6351,
3822                 .name = "Marvell 88E6351",
3823                 .num_databases = 4096,
3824                 .num_ports = 7,
3825                 .port_base_addr = 0x10,
3826                 .age_time_coeff = 15000,
3827                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3828         },
3829
3830         [MV88E6352] = {
3831                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3832                 .family = MV88E6XXX_FAMILY_6352,
3833                 .name = "Marvell 88E6352",
3834                 .num_databases = 4096,
3835                 .num_ports = 7,
3836                 .port_base_addr = 0x10,
3837                 .age_time_coeff = 15000,
3838                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3839         },
3840 };
3841
3842 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3843 {
3844         int i;
3845
3846         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3847                 if (mv88e6xxx_table[i].prod_num == prod_num)
3848                         return &mv88e6xxx_table[i];
3849
3850         return NULL;
3851 }
3852
3853 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3854 {
3855         const struct mv88e6xxx_info *info;
3856         unsigned int prod_num, rev;
3857         u16 id;
3858         int err;
3859
3860         mutex_lock(&chip->reg_lock);
3861         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3862         mutex_unlock(&chip->reg_lock);
3863         if (err)
3864                 return err;
3865
3866         prod_num = (id & 0xfff0) >> 4;
3867         rev = id & 0x000f;
3868
3869         info = mv88e6xxx_lookup_info(prod_num);
3870         if (!info)
3871                 return -ENODEV;
3872
3873         /* Update the compatible info with the probed one */
3874         chip->info = info;
3875
3876         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3877                  chip->info->prod_num, chip->info->name, rev);
3878
3879         return 0;
3880 }
3881
3882 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3883 {
3884         struct mv88e6xxx_chip *chip;
3885
3886         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3887         if (!chip)
3888                 return NULL;
3889
3890         chip->dev = dev;
3891
3892         mutex_init(&chip->reg_lock);
3893
3894         return chip;
3895 }
3896
3897 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3898         .read = mv88e6xxx_read,
3899         .write = mv88e6xxx_write,
3900 };
3901
3902 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3903 {
3904         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3905                 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3906         } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3907                 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3908                 mv88e6xxx_ppu_state_init(chip);
3909         } else {
3910                 chip->phy_ops = &mv88e6xxx_phy_ops;
3911         }
3912 }
3913
3914 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3915                               struct mii_bus *bus, int sw_addr)
3916 {
3917         /* ADDR[0] pin is unavailable externally and considered zero */
3918         if (sw_addr & 0x1)
3919                 return -EINVAL;
3920
3921         if (sw_addr == 0)
3922                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3923         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3924                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3925         else
3926                 return -EINVAL;
3927
3928         chip->bus = bus;
3929         chip->sw_addr = sw_addr;
3930
3931         return 0;
3932 }
3933
3934 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3935                                        struct device *host_dev, int sw_addr,
3936                                        void **priv)
3937 {
3938         struct mv88e6xxx_chip *chip;
3939         struct mii_bus *bus;
3940         int err;
3941
3942         bus = dsa_host_dev_to_mii_bus(host_dev);
3943         if (!bus)
3944                 return NULL;
3945
3946         chip = mv88e6xxx_alloc_chip(dsa_dev);
3947         if (!chip)
3948                 return NULL;
3949
3950         /* Legacy SMI probing will only support chips similar to 88E6085 */
3951         chip->info = &mv88e6xxx_table[MV88E6085];
3952
3953         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3954         if (err)
3955                 goto free;
3956
3957         err = mv88e6xxx_detect(chip);
3958         if (err)
3959                 goto free;
3960
3961         mv88e6xxx_phy_init(chip);
3962
3963         err = mv88e6xxx_mdio_register(chip, NULL);
3964         if (err)
3965                 goto free;
3966
3967         *priv = chip;
3968
3969         return chip->info->name;
3970 free:
3971         devm_kfree(dsa_dev, chip);
3972
3973         return NULL;
3974 }
3975
3976 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3977         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3978         .probe                  = mv88e6xxx_drv_probe,
3979         .setup                  = mv88e6xxx_setup,
3980         .set_addr               = mv88e6xxx_set_addr,
3981         .adjust_link            = mv88e6xxx_adjust_link,
3982         .get_strings            = mv88e6xxx_get_strings,
3983         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3984         .get_sset_count         = mv88e6xxx_get_sset_count,
3985         .set_eee                = mv88e6xxx_set_eee,
3986         .get_eee                = mv88e6xxx_get_eee,
3987 #ifdef CONFIG_NET_DSA_HWMON
3988         .get_temp               = mv88e6xxx_get_temp,
3989         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3990         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3991         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3992 #endif
3993         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3994         .get_eeprom             = mv88e6xxx_get_eeprom,
3995         .set_eeprom             = mv88e6xxx_set_eeprom,
3996         .get_regs_len           = mv88e6xxx_get_regs_len,
3997         .get_regs               = mv88e6xxx_get_regs,
3998         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3999         .port_bridge_join       = mv88e6xxx_port_bridge_join,
4000         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
4001         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
4002         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
4003         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
4004         .port_vlan_add          = mv88e6xxx_port_vlan_add,
4005         .port_vlan_del          = mv88e6xxx_port_vlan_del,
4006         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
4007         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
4008         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4009         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4010         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4011 };
4012
4013 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4014                                      struct device_node *np)
4015 {
4016         struct device *dev = chip->dev;
4017         struct dsa_switch *ds;
4018
4019         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4020         if (!ds)
4021                 return -ENOMEM;
4022
4023         ds->dev = dev;
4024         ds->priv = chip;
4025         ds->drv = &mv88e6xxx_switch_driver;
4026
4027         dev_set_drvdata(dev, ds);
4028
4029         return dsa_register_switch(ds, np);
4030 }
4031
4032 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4033 {
4034         dsa_unregister_switch(chip->ds);
4035 }
4036
4037 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4038 {
4039         struct device *dev = &mdiodev->dev;
4040         struct device_node *np = dev->of_node;
4041         const struct mv88e6xxx_info *compat_info;
4042         struct mv88e6xxx_chip *chip;
4043         u32 eeprom_len;
4044         int err;
4045
4046         compat_info = of_device_get_match_data(dev);
4047         if (!compat_info)
4048                 return -EINVAL;
4049
4050         chip = mv88e6xxx_alloc_chip(dev);
4051         if (!chip)
4052                 return -ENOMEM;
4053
4054         chip->info = compat_info;
4055
4056         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4057         if (err)
4058                 return err;
4059
4060         err = mv88e6xxx_detect(chip);
4061         if (err)
4062                 return err;
4063
4064         mv88e6xxx_phy_init(chip);
4065
4066         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4067         if (IS_ERR(chip->reset))
4068                 return PTR_ERR(chip->reset);
4069
4070         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4071             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4072                 chip->eeprom_len = eeprom_len;
4073
4074         err = mv88e6xxx_mdio_register(chip, np);
4075         if (err)
4076                 return err;
4077
4078         err = mv88e6xxx_register_switch(chip, np);
4079         if (err) {
4080                 mv88e6xxx_mdio_unregister(chip);
4081                 return err;
4082         }
4083
4084         return 0;
4085 }
4086
4087 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4088 {
4089         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4090         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4091
4092         mv88e6xxx_unregister_switch(chip);
4093         mv88e6xxx_mdio_unregister(chip);
4094 }
4095
4096 static const struct of_device_id mv88e6xxx_of_match[] = {
4097         {
4098                 .compatible = "marvell,mv88e6085",
4099                 .data = &mv88e6xxx_table[MV88E6085],
4100         },
4101         { /* sentinel */ },
4102 };
4103
4104 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4105
4106 static struct mdio_driver mv88e6xxx_driver = {
4107         .probe  = mv88e6xxx_probe,
4108         .remove = mv88e6xxx_remove,
4109         .mdiodrv.driver = {
4110                 .name = "mv88e6085",
4111                 .of_match_table = mv88e6xxx_of_match,
4112         },
4113 };
4114
4115 static int __init mv88e6xxx_init(void)
4116 {
4117         register_switch_driver(&mv88e6xxx_switch_driver);
4118         return mdio_driver_register(&mv88e6xxx_driver);
4119 }
4120 module_init(mv88e6xxx_init);
4121
4122 static void __exit mv88e6xxx_cleanup(void)
4123 {
4124         mdio_driver_unregister(&mv88e6xxx_driver);
4125         unregister_switch_driver(&mv88e6xxx_switch_driver);
4126 }
4127 module_exit(mv88e6xxx_cleanup);
4128
4129 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4130 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4131 MODULE_LICENSE("GPL");