drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/list.h>
  26 #include <linux/mdio.h>
  27 #include <linux/module.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/of_mdio.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/gpio/consumer.h>
  33 #include <linux/phy.h>
  34 #include <net/dsa.h>
  35 #include <net/switchdev.h>
  36
  37 #include "mv88e6xxx.h"
  38 #include "global1.h"
  39 #include "global2.h"
  40 #include "port.h"
  41
  42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  43 {
  44         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  45                 dev_err(chip->dev, "Switch registers lock not held!\n");
  46                 dump_stack();
  47         }
  48 }
  49
  50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  51  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  52  *
  53  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  54  * is the only device connected to the SMI master. In this mode it responds to
  55  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  56  *
  57  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  58  * multiple devices to share the SMI interface. In this mode it responds to only
  59  * 2 registers, used to indirectly access the internal SMI devices.
  60  */
  61
  62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  63                               int addr, int reg, u16 *val)
  64 {
  65         if (!chip->smi_ops)
  66                 return -EOPNOTSUPP;
  67
  68         return chip->smi_ops->read(chip, addr, reg, val);
  69 }
  70
  71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  72                                int addr, int reg, u16 val)
  73 {
  74         if (!chip->smi_ops)
  75                 return -EOPNOTSUPP;
  76
  77         return chip->smi_ops->write(chip, addr, reg, val);
  78 }
  79
  80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  81                                           int addr, int reg, u16 *val)
  82 {
  83         int ret;
  84
  85         ret = mdiobus_read_nested(chip->bus, addr, reg);
  86         if (ret < 0)
  87                 return ret;
  88
  89         *val = ret & 0xffff;
  90
  91         return 0;
  92 }
  93
  94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  95                                            int addr, int reg, u16 val)
  96 {
  97         int ret;
  98
  99         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
 100         if (ret < 0)
 101                 return ret;
 102
 103         return 0;
 104 }
 105
 106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
 107         .read = mv88e6xxx_smi_single_chip_read,
 108         .write = mv88e6xxx_smi_single_chip_write,
 109 };
 110
 111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 112 {
 113         int ret;
 114         int i;
 115
 116         for (i = 0; i < 16; i++) {
 117                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 118                 if (ret < 0)
 119                         return ret;
 120
 121                 if ((ret & SMI_CMD_BUSY) == 0)
 122                         return 0;
 123         }
 124
 125         return -ETIMEDOUT;
 126 }
 127
 128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 129                                          int addr, int reg, u16 *val)
 130 {
 131         int ret;
 132
 133         /* Wait for the bus to become free. */
 134         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 135         if (ret < 0)
 136                 return ret;
 137
 138         /* Transmit the read command. */
 139         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 140                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 141         if (ret < 0)
 142                 return ret;
 143
 144         /* Wait for the read command to complete. */
 145         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 146         if (ret < 0)
 147                 return ret;
 148
 149         /* Read the data. */
 150         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 151         if (ret < 0)
 152                 return ret;
 153
 154         *val = ret & 0xffff;
 155
 156         return 0;
 157 }
 158
 159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 160                                           int addr, int reg, u16 val)
 161 {
 162         int ret;
 163
 164         /* Wait for the bus to become free. */
 165         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 166         if (ret < 0)
 167                 return ret;
 168
 169         /* Transmit the data to write. */
 170         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 171         if (ret < 0)
 172                 return ret;
 173
 174         /* Transmit the write command. */
 175         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 176                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 177         if (ret < 0)
 178                 return ret;
 179
 180         /* Wait for the write command to complete. */
 181         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 182         if (ret < 0)
 183                 return ret;
 184
 185         return 0;
 186 }
 187
 188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
 189         .read = mv88e6xxx_smi_multi_chip_read,
 190         .write = mv88e6xxx_smi_multi_chip_write,
 191 };
 192
 193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
 194 {
 195         int err;
 196
 197         assert_reg_lock(chip);
 198
 199         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 200         if (err)
 201                 return err;
 202
 203         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 204                 addr, reg, *val);
 205
 206         return 0;
 207 }
 208
 209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
 210 {
 211         int err;
 212
 213         assert_reg_lock(chip);
 214
 215         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 216         if (err)
 217                 return err;
 218
 219         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 220                 addr, reg, val);
 221
 222         return 0;
 223 }
 224
 225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
 226                               int reg, u16 *val)
 227 {
 228         int addr = phy; /* PHY devices addresses start at 0x0 */
 229
 230         if (!chip->info->ops->phy_read)
 231                 return -EOPNOTSUPP;
 232
 233         return chip->info->ops->phy_read(chip, addr, reg, val);
 234 }
 235
 236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
 237                                int reg, u16 val)
 238 {
 239         int addr = phy; /* PHY devices addresses start at 0x0 */
 240
 241         if (!chip->info->ops->phy_write)
 242                 return -EOPNOTSUPP;
 243
 244         return chip->info->ops->phy_write(chip, addr, reg, val);
 245 }
 246
 247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 248 {
 249         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
 250                 return -EOPNOTSUPP;
 251
 252         return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 253 }
 254
 255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
 256 {
 257         int err;
 258
 259         /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
 260         err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
 261         if (unlikely(err)) {
 262                 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
 263                         phy, err);
 264         }
 265 }
 266
 267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
 268                                    u8 page, int reg, u16 *val)
 269 {
 270         int err;
 271
 272         /* There is no paging for registers 22 */
 273         if (reg == PHY_PAGE)
 274                 return -EINVAL;
 275
 276         err = mv88e6xxx_phy_page_get(chip, phy, page);
 277         if (!err) {
 278                 err = mv88e6xxx_phy_read(chip, phy, reg, val);
 279                 mv88e6xxx_phy_page_put(chip, phy);
 280         }
 281
 282         return err;
 283 }
 284
 285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
 286                                     u8 page, int reg, u16 val)
 287 {
 288         int err;
 289
 290         /* There is no paging for registers 22 */
 291         if (reg == PHY_PAGE)
 292                 return -EINVAL;
 293
 294         err = mv88e6xxx_phy_page_get(chip, phy, page);
 295         if (!err) {
 296                 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 297                 mv88e6xxx_phy_page_put(chip, phy);
 298         }
 299
 300         return err;
 301 }
 302
 303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 304 {
 305         return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 306                                        reg, val);
 307 }
 308
 309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 310 {
 311         return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 312                                         reg, val);
 313 }
 314
 315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 316 {
 317         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 318         unsigned int n = d->hwirq;
 319
 320         chip->g1_irq.masked |= (1 << n);
 321 }
 322
 323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 324 {
 325         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 326         unsigned int n = d->hwirq;
 327
 328         chip->g1_irq.masked &= ~(1 << n);
 329 }
 330
 331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 332 {
 333         struct mv88e6xxx_chip *chip = dev_id;
 334         unsigned int nhandled = 0;
 335         unsigned int sub_irq;
 336         unsigned int n;
 337         u16 reg;
 338         int err;
 339
 340         mutex_lock(&chip->reg_lock);
 341         err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
 342         mutex_unlock(&chip->reg_lock);
 343
 344         if (err)
 345                 goto out;
 346
 347         for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 348                 if (reg & (1 << n)) {
 349                         sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
 350                         handle_nested_irq(sub_irq);
 351                         ++nhandled;
 352                 }
 353         }
 354 out:
 355         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 356 }
 357
 358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 359 {
 360         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 361
 362         mutex_lock(&chip->reg_lock);
 363 }
 364
 365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 366 {
 367         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 368         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 369         u16 reg;
 370         int err;
 371
 372         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
 373         if (err)
 374                 goto out;
 375
 376         reg &= ~mask;
 377         reg |= (~chip->g1_irq.masked & mask);
 378
 379         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
 380         if (err)
 381                 goto out;
 382
 383 out:
 384         mutex_unlock(&chip->reg_lock);
 385 }
 386
 387 static struct irq_chip mv88e6xxx_g1_irq_chip = {
 388         .name                   = "mv88e6xxx-g1",
 389         .irq_mask               = mv88e6xxx_g1_irq_mask,
 390         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 391         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 392         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 393 };
 394
 395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 396                                        unsigned int irq,
 397                                        irq_hw_number_t hwirq)
 398 {
 399         struct mv88e6xxx_chip *chip = d->host_data;
 400
 401         irq_set_chip_data(irq, d->host_data);
 402         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 403         irq_set_noprobe(irq);
 404
 405         return 0;
 406 }
 407
 408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 409         .map    = mv88e6xxx_g1_irq_domain_map,
 410         .xlate  = irq_domain_xlate_twocell,
 411 };
 412
 413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 414 {
 415         int irq, virq;
 416
 417         for (irq = 0; irq < 16; irq++) {
 418                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 419                 irq_dispose_mapping(virq);
 420         }
 421
 422         irq_domain_remove(chip->g1_irq.domain);
 423 }
 424
 425 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 426 {
 427         int err, irq;
 428         u16 reg;
 429
 430         chip->g1_irq.nirqs = chip->info->g1_irqs;
 431         chip->g1_irq.domain = irq_domain_add_simple(
 432                 NULL, chip->g1_irq.nirqs, 0,
 433                 &mv88e6xxx_g1_irq_domain_ops, chip);
 434         if (!chip->g1_irq.domain)
 435                 return -ENOMEM;
 436
 437         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 438                 irq_create_mapping(chip->g1_irq.domain, irq);
 439
 440         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 441         chip->g1_irq.masked = ~0;
 442
 443         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
 444         if (err)
 445                 goto out;
 446
 447         reg &= ~GENMASK(chip->g1_irq.nirqs, 0);
 448
 449         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
 450         if (err)
 451                 goto out;
 452
 453         /* Reading the interrupt status clears (most of) them */
 454         err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
 455         if (err)
 456                 goto out;
 457
 458         err = request_threaded_irq(chip->irq, NULL,
 459                                    mv88e6xxx_g1_irq_thread_fn,
 460                                    IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
 461                                    dev_name(chip->dev), chip);
 462         if (err)
 463                 goto out;
 464
 465         return 0;
 466
 467 out:
 468         mv88e6xxx_g1_irq_free(chip);
 469
 470         return err;
 471 }
 472
 473 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
 474 {
 475         int i;
 476
 477         for (i = 0; i < 16; i++) {
 478                 u16 val;
 479                 int err;
 480
 481                 err = mv88e6xxx_read(chip, addr, reg, &val);
 482                 if (err)
 483                         return err;
 484
 485                 if (!(val & mask))
 486                         return 0;
 487
 488                 usleep_range(1000, 2000);
 489         }
 490
 491         dev_err(chip->dev, "Timeout while waiting for switch\n");
 492         return -ETIMEDOUT;
 493 }
 494
 495 /* Indirect write to single pointer-data register with an Update bit */
 496 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
 497 {
 498         u16 val;
 499         int err;
 500
 501         /* Wait until the previous operation is completed */
 502         err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
 503         if (err)
 504                 return err;
 505
 506         /* Set the Update bit to trigger a write operation */
 507         val = BIT(15) | update;
 508
 509         return mv88e6xxx_write(chip, addr, reg, val);
 510 }
 511
 512 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 513 {
 514         u16 val;
 515         int i, err;
 516
 517         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
 518         if (err)
 519                 return err;
 520
 521         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
 522                                  val & ~GLOBAL_CONTROL_PPU_ENABLE);
 523         if (err)
 524                 return err;
 525
 526         for (i = 0; i < 16; i++) {
 527                 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
 528                 if (err)
 529                         return err;
 530
 531                 usleep_range(1000, 2000);
 532                 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
 533                         return 0;
 534         }
 535
 536         return -ETIMEDOUT;
 537 }
 538
 539 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 540 {
 541         u16 val;
 542         int i, err;
 543
 544         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
 545         if (err)
 546                 return err;
 547
 548         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
 549                                  val | GLOBAL_CONTROL_PPU_ENABLE);
 550         if (err)
 551                 return err;
 552
 553         for (i = 0; i < 16; i++) {
 554                 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
 555                 if (err)
 556                         return err;
 557
 558                 usleep_range(1000, 2000);
 559                 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
 560                         return 0;
 561         }
 562
 563         return -ETIMEDOUT;
 564 }
 565
 566 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 567 {
 568         struct mv88e6xxx_chip *chip;
 569
 570         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 571
 572         mutex_lock(&chip->reg_lock);
 573
 574         if (mutex_trylock(&chip->ppu_mutex)) {
 575                 if (mv88e6xxx_ppu_enable(chip) == 0)
 576                         chip->ppu_disabled = 0;
 577                 mutex_unlock(&chip->ppu_mutex);
 578         }
 579
 580         mutex_unlock(&chip->reg_lock);
 581 }
 582
 583 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 584 {
 585         struct mv88e6xxx_chip *chip = (void *)_ps;
 586
 587         schedule_work(&chip->ppu_work);
 588 }
 589
 590 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 591 {
 592         int ret;
 593
 594         mutex_lock(&chip->ppu_mutex);
 595
 596         /* If the PHY polling unit is enabled, disable it so that
 597          * we can access the PHY registers.  If it was already
 598          * disabled, cancel the timer that is going to re-enable
 599          * it.
 600          */
 601         if (!chip->ppu_disabled) {
 602                 ret = mv88e6xxx_ppu_disable(chip);
 603                 if (ret < 0) {
 604                         mutex_unlock(&chip->ppu_mutex);
 605                         return ret;
 606                 }
 607                 chip->ppu_disabled = 1;
 608         } else {
 609                 del_timer(&chip->ppu_timer);
 610                 ret = 0;
 611         }
 612
 613         return ret;
 614 }
 615
 616 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 617 {
 618         /* Schedule a timer to re-enable the PHY polling unit. */
 619         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 620         mutex_unlock(&chip->ppu_mutex);
 621 }
 622
 623 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 624 {
 625         mutex_init(&chip->ppu_mutex);
 626         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 627         setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
 628                     (unsigned long)chip);
 629 }
 630
 631 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
 632 {
 633         del_timer_sync(&chip->ppu_timer);
 634 }
 635
 636 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
 637                                   int reg, u16 *val)
 638 {
 639         int err;
 640
 641         err = mv88e6xxx_ppu_access_get(chip);
 642         if (!err) {
 643                 err = mv88e6xxx_read(chip, addr, reg, val);
 644                 mv88e6xxx_ppu_access_put(chip);
 645         }
 646
 647         return err;
 648 }
 649
 650 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
 651                                    int reg, u16 val)
 652 {
 653         int err;
 654
 655         err = mv88e6xxx_ppu_access_get(chip);
 656         if (!err) {
 657                 err = mv88e6xxx_write(chip, addr, reg, val);
 658                 mv88e6xxx_ppu_access_put(chip);
 659         }
 660
 661         return err;
 662 }
 663
 664 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 665 {
 666         return chip->info->family == MV88E6XXX_FAMILY_6065;
 667 }
 668
 669 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 670 {
 671         return chip->info->family == MV88E6XXX_FAMILY_6095;
 672 }
 673
 674 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 675 {
 676         return chip->info->family == MV88E6XXX_FAMILY_6097;
 677 }
 678
 679 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 680 {
 681         return chip->info->family == MV88E6XXX_FAMILY_6165;
 682 }
 683
 684 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 685 {
 686         return chip->info->family == MV88E6XXX_FAMILY_6185;
 687 }
 688
 689 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 690 {
 691         return chip->info->family == MV88E6XXX_FAMILY_6320;
 692 }
 693
 694 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 695 {
 696         return chip->info->family == MV88E6XXX_FAMILY_6351;
 697 }
 698
 699 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 700 {
 701         return chip->info->family == MV88E6XXX_FAMILY_6352;
 702 }
 703
 704 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 705                                     int link, int speed, int duplex,
 706                                     phy_interface_t mode)
 707 {
 708         int err;
 709
 710         if (!chip->info->ops->port_set_link)
 711                 return 0;
 712
 713         /* Port's MAC control must not be changed unless the link is down */
 714         err = chip->info->ops->port_set_link(chip, port, 0);
 715         if (err)
 716                 return err;
 717
 718         if (chip->info->ops->port_set_speed) {
 719                 err = chip->info->ops->port_set_speed(chip, port, speed);
 720                 if (err && err != -EOPNOTSUPP)
 721                         goto restore_link;
 722         }
 723
 724         if (chip->info->ops->port_set_duplex) {
 725                 err = chip->info->ops->port_set_duplex(chip, port, duplex);
 726                 if (err && err != -EOPNOTSUPP)
 727                         goto restore_link;
 728         }
 729
 730         if (chip->info->ops->port_set_rgmii_delay) {
 731                 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
 732                 if (err && err != -EOPNOTSUPP)
 733                         goto restore_link;
 734         }
 735
 736         err = 0;
 737 restore_link:
 738         if (chip->info->ops->port_set_link(chip, port, link))
 739                 netdev_err(chip->ds->ports[port].netdev,
 740                            "failed to restore MAC's link\n");
 741
 742         return err;
 743 }
 744
 745 /* We expect the switch to perform auto negotiation if there is a real
 746  * phy. However, in the case of a fixed link phy, we force the port
 747  * settings from the fixed link settings.
 748  */
 749 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 750                                   struct phy_device *phydev)
 751 {
 752         struct mv88e6xxx_chip *chip = ds->priv;
 753         int err;
 754
 755         if (!phy_is_pseudo_fixed_link(phydev))
 756                 return;
 757
 758         mutex_lock(&chip->reg_lock);
 759         err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
 760                                        phydev->duplex, phydev->interface);
 761         mutex_unlock(&chip->reg_lock);
 762
 763         if (err && err != -EOPNOTSUPP)
 764                 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
 765 }
 766
 767 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 768 {
 769         u16 val;
 770         int i, err;
 771
 772         for (i = 0; i < 10; i++) {
 773                 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
 774                 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
 775                         return 0;
 776         }
 777
 778         return -ETIMEDOUT;
 779 }
 780
 781 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 782 {
 783         int err;
 784
 785         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 786                 port = (port + 1) << 5;
 787
 788         /* Snapshot the hardware statistics counters for this port. */
 789         err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
 790                                  GLOBAL_STATS_OP_CAPTURE_PORT |
 791                                  GLOBAL_STATS_OP_HIST_RX_TX | port);
 792         if (err)
 793                 return err;
 794
 795         /* Wait for the snapshotting to complete. */
 796         return _mv88e6xxx_stats_wait(chip);
 797 }
 798
 799 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 800                                   int stat, u32 *val)
 801 {
 802         u32 value;
 803         u16 reg;
 804         int err;
 805
 806         *val = 0;
 807
 808         err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
 809                                  GLOBAL_STATS_OP_READ_CAPTURED |
 810                                  GLOBAL_STATS_OP_HIST_RX_TX | stat);
 811         if (err)
 812                 return;
 813
 814         err = _mv88e6xxx_stats_wait(chip);
 815         if (err)
 816                 return;
 817
 818         err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
 819         if (err)
 820                 return;
 821
 822         value = reg << 16;
 823
 824         err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
 825         if (err)
 826                 return;
 827
 828         *val = value | reg;
 829 }
 830
 831 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 832         { "in_good_octets",     8, 0x00, BANK0, },
 833         { "in_bad_octets",      4, 0x02, BANK0, },
 834         { "in_unicast",         4, 0x04, BANK0, },
 835         { "in_broadcasts",      4, 0x06, BANK0, },
 836         { "in_multicasts",      4, 0x07, BANK0, },
 837         { "in_pause",           4, 0x16, BANK0, },
 838         { "in_undersize",       4, 0x18, BANK0, },
 839         { "in_fragments",       4, 0x19, BANK0, },
 840         { "in_oversize",        4, 0x1a, BANK0, },
 841         { "in_jabber",          4, 0x1b, BANK0, },
 842         { "in_rx_error",        4, 0x1c, BANK0, },
 843         { "in_fcs_error",       4, 0x1d, BANK0, },
 844         { "out_octets",         8, 0x0e, BANK0, },
 845         { "out_unicast",        4, 0x10, BANK0, },
 846         { "out_broadcasts",     4, 0x13, BANK0, },
 847         { "out_multicasts",     4, 0x12, BANK0, },
 848         { "out_pause",          4, 0x15, BANK0, },
 849         { "excessive",          4, 0x11, BANK0, },
 850         { "collisions",         4, 0x1e, BANK0, },
 851         { "deferred",           4, 0x05, BANK0, },
 852         { "single",             4, 0x14, BANK0, },
 853         { "multiple",           4, 0x17, BANK0, },
 854         { "out_fcs_error",      4, 0x03, BANK0, },
 855         { "late",               4, 0x1f, BANK0, },
 856         { "hist_64bytes",       4, 0x08, BANK0, },
 857         { "hist_65_127bytes",   4, 0x09, BANK0, },
 858         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 859         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 860         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 861         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 862         { "sw_in_discards",     4, 0x10, PORT, },
 863         { "sw_in_filtered",     2, 0x12, PORT, },
 864         { "sw_out_filtered",    2, 0x13, PORT, },
 865         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 866         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 867         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 868         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 869         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 870         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 871         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 872         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 873         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 874         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 875         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 876         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 877         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 878         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 879         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 880         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 881         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 882         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 883         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 884         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 885         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 886         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 887         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 888         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 889         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 890         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 891 };
 892
 893 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 894                                struct mv88e6xxx_hw_stat *stat)
 895 {
 896         switch (stat->type) {
 897         case BANK0:
 898                 return true;
 899         case BANK1:
 900                 return mv88e6xxx_6320_family(chip);
 901         case PORT:
 902                 return mv88e6xxx_6095_family(chip) ||
 903                         mv88e6xxx_6185_family(chip) ||
 904                         mv88e6xxx_6097_family(chip) ||
 905                         mv88e6xxx_6165_family(chip) ||
 906                         mv88e6xxx_6351_family(chip) ||
 907                         mv88e6xxx_6352_family(chip);
 908         }
 909         return false;
 910 }
 911
 912 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 913                                             struct mv88e6xxx_hw_stat *s,
 914                                             int port)
 915 {
 916         u32 low;
 917         u32 high = 0;
 918         int err;
 919         u16 reg;
 920         u64 value;
 921
 922         switch (s->type) {
 923         case PORT:
 924                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 925                 if (err)
 926                         return UINT64_MAX;
 927
 928                 low = reg;
 929                 if (s->sizeof_stat == 4) {
 930                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 931                         if (err)
 932                                 return UINT64_MAX;
 933                         high = reg;
 934                 }
 935                 break;
 936         case BANK0:
 937         case BANK1:
 938                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 939                 if (s->sizeof_stat == 8)
 940                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 941         }
 942         value = (((u64)high) << 16) | low;
 943         return value;
 944 }
 945
 946 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 947                                   uint8_t *data)
 948 {
 949         struct mv88e6xxx_chip *chip = ds->priv;
 950         struct mv88e6xxx_hw_stat *stat;
 951         int i, j;
 952
 953         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 954                 stat = &mv88e6xxx_hw_stats[i];
 955                 if (mv88e6xxx_has_stat(chip, stat)) {
 956                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 957                                ETH_GSTRING_LEN);
 958                         j++;
 959                 }
 960         }
 961 }
 962
 963 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 964 {
 965         struct mv88e6xxx_chip *chip = ds->priv;
 966         struct mv88e6xxx_hw_stat *stat;
 967         int i, j;
 968
 969         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 970                 stat = &mv88e6xxx_hw_stats[i];
 971                 if (mv88e6xxx_has_stat(chip, stat))
 972                         j++;
 973         }
 974         return j;
 975 }
 976
 977 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 978                                         uint64_t *data)
 979 {
 980         struct mv88e6xxx_chip *chip = ds->priv;
 981         struct mv88e6xxx_hw_stat *stat;
 982         int ret;
 983         int i, j;
 984
 985         mutex_lock(&chip->reg_lock);
 986
 987         ret = _mv88e6xxx_stats_snapshot(chip, port);
 988         if (ret < 0) {
 989                 mutex_unlock(&chip->reg_lock);
 990                 return;
 991         }
 992         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 993                 stat = &mv88e6xxx_hw_stats[i];
 994                 if (mv88e6xxx_has_stat(chip, stat)) {
 995                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 996                         j++;
 997                 }
 998         }
 999
1000         mutex_unlock(&chip->reg_lock);
1001 }
1002
1003 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1004 {
1005         return 32 * sizeof(u16);
1006 }
1007
1008 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1009                                struct ethtool_regs *regs, void *_p)
1010 {
1011         struct mv88e6xxx_chip *chip = ds->priv;
1012         int err;
1013         u16 reg;
1014         u16 *p = _p;
1015         int i;
1016
1017         regs->version = 0;
1018
1019         memset(p, 0xff, 32 * sizeof(u16));
1020
1021         mutex_lock(&chip->reg_lock);
1022
1023         for (i = 0; i < 32; i++) {
1024
1025                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1026                 if (!err)
1027                         p[i] = reg;
1028         }
1029
1030         mutex_unlock(&chip->reg_lock);
1031 }
1032
1033 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1034 {
1035         return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
1036 }
1037
1038 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1039                              struct ethtool_eee *e)
1040 {
1041         struct mv88e6xxx_chip *chip = ds->priv;
1042         u16 reg;
1043         int err;
1044
1045         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1046                 return -EOPNOTSUPP;
1047
1048         mutex_lock(&chip->reg_lock);
1049
1050         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1051         if (err)
1052                 goto out;
1053
1054         e->eee_enabled = !!(reg & 0x0200);
1055         e->tx_lpi_enabled = !!(reg & 0x0100);
1056
1057         err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
1058         if (err)
1059                 goto out;
1060
1061         e->eee_active = !!(reg & PORT_STATUS_EEE);
1062 out:
1063         mutex_unlock(&chip->reg_lock);
1064
1065         return err;
1066 }
1067
1068 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1069                              struct phy_device *phydev, struct ethtool_eee *e)
1070 {
1071         struct mv88e6xxx_chip *chip = ds->priv;
1072         u16 reg;
1073         int err;
1074
1075         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1076                 return -EOPNOTSUPP;
1077
1078         mutex_lock(&chip->reg_lock);
1079
1080         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1081         if (err)
1082                 goto out;
1083
1084         reg &= ~0x0300;
1085         if (e->eee_enabled)
1086                 reg |= 0x0200;
1087         if (e->tx_lpi_enabled)
1088                 reg |= 0x0100;
1089
1090         err = mv88e6xxx_phy_write(chip, port, 16, reg);
1091 out:
1092         mutex_unlock(&chip->reg_lock);
1093
1094         return err;
1095 }
1096
1097 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1098 {
1099         u16 val;
1100         int err;
1101
1102         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
1103                 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1104                 if (err)
1105                         return err;
1106         } else if (mv88e6xxx_num_databases(chip) == 256) {
1107                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1108                 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1109                 if (err)
1110                         return err;
1111
1112                 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1113                                          (val & 0xfff) | ((fid << 8) & 0xf000));
1114                 if (err)
1115                         return err;
1116
1117                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1118                 cmd |= fid & 0xf;
1119         }
1120
1121         err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1122         if (err)
1123                 return err;
1124
1125         return _mv88e6xxx_atu_wait(chip);
1126 }
1127
1128 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1129                                      struct mv88e6xxx_atu_entry *entry)
1130 {
1131         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1132
1133         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1134                 unsigned int mask, shift;
1135
1136                 if (entry->trunk) {
1137                         data |= GLOBAL_ATU_DATA_TRUNK;
1138                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1139                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1140                 } else {
1141                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1142                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1143                 }
1144
1145                 data |= (entry->portv_trunkid << shift) & mask;
1146         }
1147
1148         return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1149 }
1150
1151 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1152                                      struct mv88e6xxx_atu_entry *entry,
1153                                      bool static_too)
1154 {
1155         int op;
1156         int err;
1157
1158         err = _mv88e6xxx_atu_wait(chip);
1159         if (err)
1160                 return err;
1161
1162         err = _mv88e6xxx_atu_data_write(chip, entry);
1163         if (err)
1164                 return err;
1165
1166         if (entry->fid) {
1167                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1168                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1169         } else {
1170                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1171                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1172         }
1173
1174         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1175 }
1176
1177 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1178                                 u16 fid, bool static_too)
1179 {
1180         struct mv88e6xxx_atu_entry entry = {
1181                 .fid = fid,
1182                 .state = 0, /* EntryState bits must be 0 */
1183         };
1184
1185         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1186 }
1187
1188 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1189                                int from_port, int to_port, bool static_too)
1190 {
1191         struct mv88e6xxx_atu_entry entry = {
1192                 .trunk = false,
1193                 .fid = fid,
1194         };
1195
1196         /* EntryState bits must be 0xF */
1197         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1198
1199         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1200         entry.portv_trunkid = (to_port & 0x0f) << 4;
1201         entry.portv_trunkid |= from_port & 0x0f;
1202
1203         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1204 }
1205
1206 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1207                                  int port, bool static_too)
1208 {
1209         /* Destination port 0xF means remove the entries */
1210         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1211 }
1212
1213 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1214 {
1215         struct net_device *bridge = chip->ports[port].bridge_dev;
1216         struct dsa_switch *ds = chip->ds;
1217         u16 output_ports = 0;
1218         int i;
1219
1220         /* allow CPU port or DSA link(s) to send frames to every port */
1221         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1222                 output_ports = ~0;
1223         } else {
1224                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1225                         /* allow sending frames to every group member */
1226                         if (bridge && chip->ports[i].bridge_dev == bridge)
1227                                 output_ports |= BIT(i);
1228
1229                         /* allow sending frames to CPU port and DSA link(s) */
1230                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1231                                 output_ports |= BIT(i);
1232                 }
1233         }
1234
1235         /* prevent frames from going back out of the port they came in on */
1236         output_ports &= ~BIT(port);
1237
1238         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1239 }
1240
1241 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1242                                          u8 state)
1243 {
1244         struct mv88e6xxx_chip *chip = ds->priv;
1245         int stp_state;
1246         int err;
1247
1248         switch (state) {
1249         case BR_STATE_DISABLED:
1250                 stp_state = PORT_CONTROL_STATE_DISABLED;
1251                 break;
1252         case BR_STATE_BLOCKING:
1253         case BR_STATE_LISTENING:
1254                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1255                 break;
1256         case BR_STATE_LEARNING:
1257                 stp_state = PORT_CONTROL_STATE_LEARNING;
1258                 break;
1259         case BR_STATE_FORWARDING:
1260         default:
1261                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1262                 break;
1263         }
1264
1265         mutex_lock(&chip->reg_lock);
1266         err = mv88e6xxx_port_set_state(chip, port, stp_state);
1267         mutex_unlock(&chip->reg_lock);
1268
1269         if (err)
1270                 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1271 }
1272
1273 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1274 {
1275         struct mv88e6xxx_chip *chip = ds->priv;
1276         int err;
1277
1278         mutex_lock(&chip->reg_lock);
1279         err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1280         mutex_unlock(&chip->reg_lock);
1281
1282         if (err)
1283                 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1284 }
1285
1286 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1287 {
1288         return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1289 }
1290
1291 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1292 {
1293         int err;
1294
1295         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1296         if (err)
1297                 return err;
1298
1299         return _mv88e6xxx_vtu_wait(chip);
1300 }
1301
1302 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1303 {
1304         int ret;
1305
1306         ret = _mv88e6xxx_vtu_wait(chip);
1307         if (ret < 0)
1308                 return ret;
1309
1310         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1311 }
1312
1313 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1314                                         struct mv88e6xxx_vtu_entry *entry,
1315                                         unsigned int nibble_offset)
1316 {
1317         u16 regs[3];
1318         int i, err;
1319
1320         for (i = 0; i < 3; ++i) {
1321                 u16 *reg = &regs[i];
1322
1323                 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1324                 if (err)
1325                         return err;
1326         }
1327
1328         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1329                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1330                 u16 reg = regs[i / 4];
1331
1332                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1333         }
1334
1335         return 0;
1336 }
1337
1338 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1339                                    struct mv88e6xxx_vtu_entry *entry)
1340 {
1341         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1342 }
1343
1344 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1345                                    struct mv88e6xxx_vtu_entry *entry)
1346 {
1347         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1348 }
1349
1350 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1351                                          struct mv88e6xxx_vtu_entry *entry,
1352                                          unsigned int nibble_offset)
1353 {
1354         u16 regs[3] = { 0 };
1355         int i, err;
1356
1357         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1358                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1359                 u8 data = entry->data[i];
1360
1361                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1362         }
1363
1364         for (i = 0; i < 3; ++i) {
1365                 u16 reg = regs[i];
1366
1367                 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1368                 if (err)
1369                         return err;
1370         }
1371
1372         return 0;
1373 }
1374
1375 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1376                                     struct mv88e6xxx_vtu_entry *entry)
1377 {
1378         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1379 }
1380
1381 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1382                                     struct mv88e6xxx_vtu_entry *entry)
1383 {
1384         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1385 }
1386
1387 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1388 {
1389         return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1390                                   vid & GLOBAL_VTU_VID_MASK);
1391 }
1392
1393 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1394                                   struct mv88e6xxx_vtu_entry *entry)
1395 {
1396         struct mv88e6xxx_vtu_entry next = { 0 };
1397         u16 val;
1398         int err;
1399
1400         err = _mv88e6xxx_vtu_wait(chip);
1401         if (err)
1402                 return err;
1403
1404         err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1405         if (err)
1406                 return err;
1407
1408         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1409         if (err)
1410                 return err;
1411
1412         next.vid = val & GLOBAL_VTU_VID_MASK;
1413         next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1414
1415         if (next.valid) {
1416                 err = mv88e6xxx_vtu_data_read(chip, &next);
1417                 if (err)
1418                         return err;
1419
1420                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1421                         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1422                         if (err)
1423                                 return err;
1424
1425                         next.fid = val & GLOBAL_VTU_FID_MASK;
1426                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1427                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1428                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1429                          */
1430                         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1431                         if (err)
1432                                 return err;
1433
1434                         next.fid = (val & 0xf00) >> 4;
1435                         next.fid |= val & 0xf;
1436                 }
1437
1438                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1439                         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1440                         if (err)
1441                                 return err;
1442
1443                         next.sid = val & GLOBAL_VTU_SID_MASK;
1444                 }
1445         }
1446
1447         *entry = next;
1448         return 0;
1449 }
1450
1451 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1452                                     struct switchdev_obj_port_vlan *vlan,
1453                                     int (*cb)(struct switchdev_obj *obj))
1454 {
1455         struct mv88e6xxx_chip *chip = ds->priv;
1456         struct mv88e6xxx_vtu_entry next;
1457         u16 pvid;
1458         int err;
1459
1460         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1461                 return -EOPNOTSUPP;
1462
1463         mutex_lock(&chip->reg_lock);
1464
1465         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1466         if (err)
1467                 goto unlock;
1468
1469         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1470         if (err)
1471                 goto unlock;
1472
1473         do {
1474                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1475                 if (err)
1476                         break;
1477
1478                 if (!next.valid)
1479                         break;
1480
1481                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1482                         continue;
1483
1484                 /* reinit and dump this VLAN obj */
1485                 vlan->vid_begin = next.vid;
1486                 vlan->vid_end = next.vid;
1487                 vlan->flags = 0;
1488
1489                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1490                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1491
1492                 if (next.vid == pvid)
1493                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1494
1495                 err = cb(&vlan->obj);
1496                 if (err)
1497                         break;
1498         } while (next.vid < GLOBAL_VTU_VID_MASK);
1499
1500 unlock:
1501         mutex_unlock(&chip->reg_lock);
1502
1503         return err;
1504 }
1505
1506 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1507                                     struct mv88e6xxx_vtu_entry *entry)
1508 {
1509         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1510         u16 reg = 0;
1511         int err;
1512
1513         err = _mv88e6xxx_vtu_wait(chip);
1514         if (err)
1515                 return err;
1516
1517         if (!entry->valid)
1518                 goto loadpurge;
1519
1520         /* Write port member tags */
1521         err = mv88e6xxx_vtu_data_write(chip, entry);
1522         if (err)
1523                 return err;
1524
1525         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1526                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1527                 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1528                 if (err)
1529                         return err;
1530         }
1531
1532         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1533                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1534                 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1535                 if (err)
1536                         return err;
1537         } else if (mv88e6xxx_num_databases(chip) == 256) {
1538                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1539                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1540                  */
1541                 op |= (entry->fid & 0xf0) << 8;
1542                 op |= entry->fid & 0xf;
1543         }
1544
1545         reg = GLOBAL_VTU_VID_VALID;
1546 loadpurge:
1547         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1548         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1549         if (err)
1550                 return err;
1551
1552         return _mv88e6xxx_vtu_cmd(chip, op);
1553 }
1554
1555 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1556                                   struct mv88e6xxx_vtu_entry *entry)
1557 {
1558         struct mv88e6xxx_vtu_entry next = { 0 };
1559         u16 val;
1560         int err;
1561
1562         err = _mv88e6xxx_vtu_wait(chip);
1563         if (err)
1564                 return err;
1565
1566         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1567                                  sid & GLOBAL_VTU_SID_MASK);
1568         if (err)
1569                 return err;
1570
1571         err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1572         if (err)
1573                 return err;
1574
1575         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1576         if (err)
1577                 return err;
1578
1579         next.sid = val & GLOBAL_VTU_SID_MASK;
1580
1581         err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1582         if (err)
1583                 return err;
1584
1585         next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1586
1587         if (next.valid) {
1588                 err = mv88e6xxx_stu_data_read(chip, &next);
1589                 if (err)
1590                         return err;
1591         }
1592
1593         *entry = next;
1594         return 0;
1595 }
1596
1597 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1598                                     struct mv88e6xxx_vtu_entry *entry)
1599 {
1600         u16 reg = 0;
1601         int err;
1602
1603         err = _mv88e6xxx_vtu_wait(chip);
1604         if (err)
1605                 return err;
1606
1607         if (!entry->valid)
1608                 goto loadpurge;
1609
1610         /* Write port states */
1611         err = mv88e6xxx_stu_data_write(chip, entry);
1612         if (err)
1613                 return err;
1614
1615         reg = GLOBAL_VTU_VID_VALID;
1616 loadpurge:
1617         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1618         if (err)
1619                 return err;
1620
1621         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1622         err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1623         if (err)
1624                 return err;
1625
1626         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1627 }
1628
1629 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1630 {
1631         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1632         struct mv88e6xxx_vtu_entry vlan;
1633         int i, err;
1634
1635         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1636
1637         /* Set every FID bit used by the (un)bridged ports */
1638         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1639                 err = mv88e6xxx_port_get_fid(chip, i, fid);
1640                 if (err)
1641                         return err;
1642
1643                 set_bit(*fid, fid_bitmap);
1644         }
1645
1646         /* Set every FID bit used by the VLAN entries */
1647         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1648         if (err)
1649                 return err;
1650
1651         do {
1652                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1653                 if (err)
1654                         return err;
1655
1656                 if (!vlan.valid)
1657                         break;
1658
1659                 set_bit(vlan.fid, fid_bitmap);
1660         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1661
1662         /* The reset value 0x000 is used to indicate that multiple address
1663          * databases are not needed. Return the next positive available.
1664          */
1665         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1666         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1667                 return -ENOSPC;
1668
1669         /* Clear the database */
1670         return _mv88e6xxx_atu_flush(chip, *fid, true);
1671 }
1672
1673 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1674                               struct mv88e6xxx_vtu_entry *entry)
1675 {
1676         struct dsa_switch *ds = chip->ds;
1677         struct mv88e6xxx_vtu_entry vlan = {
1678                 .valid = true,
1679                 .vid = vid,
1680         };
1681         int i, err;
1682
1683         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1684         if (err)
1685                 return err;
1686
1687         /* exclude all ports except the CPU and DSA ports */
1688         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1689                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1690                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1691                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1692
1693         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1694             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1695                 struct mv88e6xxx_vtu_entry vstp;
1696
1697                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1698                  * implemented, only one STU entry is needed to cover all VTU
1699                  * entries. Thus, validate the SID 0.
1700                  */
1701                 vlan.sid = 0;
1702                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1703                 if (err)
1704                         return err;
1705
1706                 if (vstp.sid != vlan.sid || !vstp.valid) {
1707                         memset(&vstp, 0, sizeof(vstp));
1708                         vstp.valid = true;
1709                         vstp.sid = vlan.sid;
1710
1711                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1712                         if (err)
1713                                 return err;
1714                 }
1715         }
1716
1717         *entry = vlan;
1718         return 0;
1719 }
1720
1721 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1722                               struct mv88e6xxx_vtu_entry *entry, bool creat)
1723 {
1724         int err;
1725
1726         if (!vid)
1727                 return -EINVAL;
1728
1729         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1730         if (err)
1731                 return err;
1732
1733         err = _mv88e6xxx_vtu_getnext(chip, entry);
1734         if (err)
1735                 return err;
1736
1737         if (entry->vid != vid || !entry->valid) {
1738                 if (!creat)
1739                         return -EOPNOTSUPP;
1740                 /* -ENOENT would've been more appropriate, but switchdev expects
1741                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1742                  */
1743
1744                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1745         }
1746
1747         return err;
1748 }
1749
1750 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1751                                         u16 vid_begin, u16 vid_end)
1752 {
1753         struct mv88e6xxx_chip *chip = ds->priv;
1754         struct mv88e6xxx_vtu_entry vlan;
1755         int i, err;
1756
1757         if (!vid_begin)
1758                 return -EOPNOTSUPP;
1759
1760         mutex_lock(&chip->reg_lock);
1761
1762         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1763         if (err)
1764                 goto unlock;
1765
1766         do {
1767                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1768                 if (err)
1769                         goto unlock;
1770
1771                 if (!vlan.valid)
1772                         break;
1773
1774                 if (vlan.vid > vid_end)
1775                         break;
1776
1777                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1778                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1779                                 continue;
1780
1781                         if (vlan.data[i] ==
1782                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1783                                 continue;
1784
1785                         if (chip->ports[i].bridge_dev ==
1786                             chip->ports[port].bridge_dev)
1787                                 break; /* same bridge, check next VLAN */
1788
1789                         netdev_warn(ds->ports[port].netdev,
1790                                     "hardware VLAN %d already used by %s\n",
1791                                     vlan.vid,
1792                                     netdev_name(chip->ports[i].bridge_dev));
1793                         err = -EOPNOTSUPP;
1794                         goto unlock;
1795                 }
1796         } while (vlan.vid < vid_end);
1797
1798 unlock:
1799         mutex_unlock(&chip->reg_lock);
1800
1801         return err;
1802 }
1803
1804 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1805                                          bool vlan_filtering)
1806 {
1807         struct mv88e6xxx_chip *chip = ds->priv;
1808         u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1809                 PORT_CONTROL_2_8021Q_DISABLED;
1810         int err;
1811
1812         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1813                 return -EOPNOTSUPP;
1814
1815         mutex_lock(&chip->reg_lock);
1816         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1817         mutex_unlock(&chip->reg_lock);
1818
1819         return err;
1820 }
1821
1822 static int
1823 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1824                             const struct switchdev_obj_port_vlan *vlan,
1825                             struct switchdev_trans *trans)
1826 {
1827         struct mv88e6xxx_chip *chip = ds->priv;
1828         int err;
1829
1830         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1831                 return -EOPNOTSUPP;
1832
1833         /* If the requested port doesn't belong to the same bridge as the VLAN
1834          * members, do not support it (yet) and fallback to software VLAN.
1835          */
1836         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1837                                            vlan->vid_end);
1838         if (err)
1839                 return err;
1840
1841         /* We don't need any dynamic resource from the kernel (yet),
1842          * so skip the prepare phase.
1843          */
1844         return 0;
1845 }
1846
1847 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1848                                     u16 vid, bool untagged)
1849 {
1850         struct mv88e6xxx_vtu_entry vlan;
1851         int err;
1852
1853         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1854         if (err)
1855                 return err;
1856
1857         vlan.data[port] = untagged ?
1858                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1859                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1860
1861         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1862 }
1863
1864 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1865                                     const struct switchdev_obj_port_vlan *vlan,
1866                                     struct switchdev_trans *trans)
1867 {
1868         struct mv88e6xxx_chip *chip = ds->priv;
1869         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1870         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1871         u16 vid;
1872
1873         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1874                 return;
1875
1876         mutex_lock(&chip->reg_lock);
1877
1878         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1879                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1880                         netdev_err(ds->ports[port].netdev,
1881                                    "failed to add VLAN %d%c\n",
1882                                    vid, untagged ? 'u' : 't');
1883
1884         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1885                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1886                            vlan->vid_end);
1887
1888         mutex_unlock(&chip->reg_lock);
1889 }
1890
1891 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1892                                     int port, u16 vid)
1893 {
1894         struct dsa_switch *ds = chip->ds;
1895         struct mv88e6xxx_vtu_entry vlan;
1896         int i, err;
1897
1898         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1899         if (err)
1900                 return err;
1901
1902         /* Tell switchdev if this VLAN is handled in software */
1903         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1904                 return -EOPNOTSUPP;
1905
1906         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1907
1908         /* keep the VLAN unless all ports are excluded */
1909         vlan.valid = false;
1910         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1911                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1912                         continue;
1913
1914                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1915                         vlan.valid = true;
1916                         break;
1917                 }
1918         }
1919
1920         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1921         if (err)
1922                 return err;
1923
1924         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1925 }
1926
1927 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1928                                    const struct switchdev_obj_port_vlan *vlan)
1929 {
1930         struct mv88e6xxx_chip *chip = ds->priv;
1931         u16 pvid, vid;
1932         int err = 0;
1933
1934         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1935                 return -EOPNOTSUPP;
1936
1937         mutex_lock(&chip->reg_lock);
1938
1939         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1940         if (err)
1941                 goto unlock;
1942
1943         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1944                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1945                 if (err)
1946                         goto unlock;
1947
1948                 if (vid == pvid) {
1949                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
1950                         if (err)
1951                                 goto unlock;
1952                 }
1953         }
1954
1955 unlock:
1956         mutex_unlock(&chip->reg_lock);
1957
1958         return err;
1959 }
1960
1961 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
1962                                     const unsigned char *addr)
1963 {
1964         int i, err;
1965
1966         for (i = 0; i < 3; i++) {
1967                 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
1968                                          (addr[i * 2] << 8) | addr[i * 2 + 1]);
1969                 if (err)
1970                         return err;
1971         }
1972
1973         return 0;
1974 }
1975
1976 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
1977                                    unsigned char *addr)
1978 {
1979         u16 val;
1980         int i, err;
1981
1982         for (i = 0; i < 3; i++) {
1983                 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
1984                 if (err)
1985                         return err;
1986
1987                 addr[i * 2] = val >> 8;
1988                 addr[i * 2 + 1] = val & 0xff;
1989         }
1990
1991         return 0;
1992 }
1993
1994 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
1995                                struct mv88e6xxx_atu_entry *entry)
1996 {
1997         int ret;
1998
1999         ret = _mv88e6xxx_atu_wait(chip);
2000         if (ret < 0)
2001                 return ret;
2002
2003         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2004         if (ret < 0)
2005                 return ret;
2006
2007         ret = _mv88e6xxx_atu_data_write(chip, entry);
2008         if (ret < 0)
2009                 return ret;
2010
2011         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2012 }
2013
2014 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2015                                   struct mv88e6xxx_atu_entry *entry);
2016
2017 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2018                              const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2019 {
2020         struct mv88e6xxx_atu_entry next;
2021         int err;
2022
2023         eth_broadcast_addr(next.mac);
2024
2025         err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2026         if (err)
2027                 return err;
2028
2029         do {
2030                 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2031                 if (err)
2032                         return err;
2033
2034                 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2035                         break;
2036
2037                 if (ether_addr_equal(next.mac, addr)) {
2038                         *entry = next;
2039                         return 0;
2040                 }
2041         } while (!is_broadcast_ether_addr(next.mac));
2042
2043         memset(entry, 0, sizeof(*entry));
2044         entry->fid = fid;
2045         ether_addr_copy(entry->mac, addr);
2046
2047         return 0;
2048 }
2049
2050 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2051                                         const unsigned char *addr, u16 vid,
2052                                         u8 state)
2053 {
2054         struct mv88e6xxx_vtu_entry vlan;
2055         struct mv88e6xxx_atu_entry entry;
2056         int err;
2057
2058         /* Null VLAN ID corresponds to the port private database */
2059         if (vid == 0)
2060                 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2061         else
2062                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2063         if (err)
2064                 return err;
2065
2066         err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2067         if (err)
2068                 return err;
2069
2070         /* Purge the ATU entry only if no port is using it anymore */
2071         if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2072                 entry.portv_trunkid &= ~BIT(port);
2073                 if (!entry.portv_trunkid)
2074                         entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2075         } else {
2076                 entry.portv_trunkid |= BIT(port);
2077                 entry.state = state;
2078         }
2079
2080         return _mv88e6xxx_atu_load(chip, &entry);
2081 }
2082
2083 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2084                                       const struct switchdev_obj_port_fdb *fdb,
2085                                       struct switchdev_trans *trans)
2086 {
2087         /* We don't need any dynamic resource from the kernel (yet),
2088          * so skip the prepare phase.
2089          */
2090         return 0;
2091 }
2092
2093 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2094                                    const struct switchdev_obj_port_fdb *fdb,
2095                                    struct switchdev_trans *trans)
2096 {
2097         struct mv88e6xxx_chip *chip = ds->priv;
2098
2099         mutex_lock(&chip->reg_lock);
2100         if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2101                                          GLOBAL_ATU_DATA_STATE_UC_STATIC))
2102                 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2103         mutex_unlock(&chip->reg_lock);
2104 }
2105
2106 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2107                                   const struct switchdev_obj_port_fdb *fdb)
2108 {
2109         struct mv88e6xxx_chip *chip = ds->priv;
2110         int err;
2111
2112         mutex_lock(&chip->reg_lock);
2113         err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2114                                            GLOBAL_ATU_DATA_STATE_UNUSED);
2115         mutex_unlock(&chip->reg_lock);
2116
2117         return err;
2118 }
2119
2120 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2121                                   struct mv88e6xxx_atu_entry *entry)
2122 {
2123         struct mv88e6xxx_atu_entry next = { 0 };
2124         u16 val;
2125         int err;
2126
2127         next.fid = fid;
2128
2129         err = _mv88e6xxx_atu_wait(chip);
2130         if (err)
2131                 return err;
2132
2133         err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2134         if (err)
2135                 return err;
2136
2137         err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2138         if (err)
2139                 return err;
2140
2141         err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2142         if (err)
2143                 return err;
2144
2145         next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2146         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2147                 unsigned int mask, shift;
2148
2149                 if (val & GLOBAL_ATU_DATA_TRUNK) {
2150                         next.trunk = true;
2151                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2152                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2153                 } else {
2154                         next.trunk = false;
2155                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2156                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2157                 }
2158
2159                 next.portv_trunkid = (val & mask) >> shift;
2160         }
2161
2162         *entry = next;
2163         return 0;
2164 }
2165
2166 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2167                                       u16 fid, u16 vid, int port,
2168                                       struct switchdev_obj *obj,
2169                                       int (*cb)(struct switchdev_obj *obj))
2170 {
2171         struct mv88e6xxx_atu_entry addr = {
2172                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2173         };
2174         int err;
2175
2176         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2177         if (err)
2178                 return err;
2179
2180         do {
2181                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2182                 if (err)
2183                         return err;
2184
2185                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2186                         break;
2187
2188                 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2189                         continue;
2190
2191                 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2192                         struct switchdev_obj_port_fdb *fdb;
2193
2194                         if (!is_unicast_ether_addr(addr.mac))
2195                                 continue;
2196
2197                         fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2198                         fdb->vid = vid;
2199                         ether_addr_copy(fdb->addr, addr.mac);
2200                         if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2201                                 fdb->ndm_state = NUD_NOARP;
2202                         else
2203                                 fdb->ndm_state = NUD_REACHABLE;
2204                 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2205                         struct switchdev_obj_port_mdb *mdb;
2206
2207                         if (!is_multicast_ether_addr(addr.mac))
2208                                 continue;
2209
2210                         mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2211                         mdb->vid = vid;
2212                         ether_addr_copy(mdb->addr, addr.mac);
2213                 } else {
2214                         return -EOPNOTSUPP;
2215                 }
2216
2217                 err = cb(obj);
2218                 if (err)
2219                         return err;
2220         } while (!is_broadcast_ether_addr(addr.mac));
2221
2222         return err;
2223 }
2224
2225 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2226                                   struct switchdev_obj *obj,
2227                                   int (*cb)(struct switchdev_obj *obj))
2228 {
2229         struct mv88e6xxx_vtu_entry vlan = {
2230                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2231         };
2232         u16 fid;
2233         int err;
2234
2235         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2236         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2237         if (err)
2238                 return err;
2239
2240         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2241         if (err)
2242                 return err;
2243
2244         /* Dump VLANs' Filtering Information Databases */
2245         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2246         if (err)
2247                 return err;
2248
2249         do {
2250                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2251                 if (err)
2252                         return err;
2253
2254                 if (!vlan.valid)
2255                         break;
2256
2257                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2258                                                  obj, cb);
2259                 if (err)
2260                         return err;
2261         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2262
2263         return err;
2264 }
2265
2266 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2267                                    struct switchdev_obj_port_fdb *fdb,
2268                                    int (*cb)(struct switchdev_obj *obj))
2269 {
2270         struct mv88e6xxx_chip *chip = ds->priv;
2271         int err;
2272
2273         mutex_lock(&chip->reg_lock);
2274         err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2275         mutex_unlock(&chip->reg_lock);
2276
2277         return err;
2278 }
2279
2280 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2281                                       struct net_device *bridge)
2282 {
2283         struct mv88e6xxx_chip *chip = ds->priv;
2284         int i, err = 0;
2285
2286         mutex_lock(&chip->reg_lock);
2287
2288         /* Assign the bridge and remap each port's VLANTable */
2289         chip->ports[port].bridge_dev = bridge;
2290
2291         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2292                 if (chip->ports[i].bridge_dev == bridge) {
2293                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2294                         if (err)
2295                                 break;
2296                 }
2297         }
2298
2299         mutex_unlock(&chip->reg_lock);
2300
2301         return err;
2302 }
2303
2304 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2305 {
2306         struct mv88e6xxx_chip *chip = ds->priv;
2307         struct net_device *bridge = chip->ports[port].bridge_dev;
2308         int i;
2309
2310         mutex_lock(&chip->reg_lock);
2311
2312         /* Unassign the bridge and remap each port's VLANTable */
2313         chip->ports[port].bridge_dev = NULL;
2314
2315         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2316                 if (i == port || chip->ports[i].bridge_dev == bridge)
2317                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2318                                 netdev_warn(ds->ports[i].netdev,
2319                                             "failed to remap\n");
2320
2321         mutex_unlock(&chip->reg_lock);
2322 }
2323
2324 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2325 {
2326         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2327         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2328         struct gpio_desc *gpiod = chip->reset;
2329         unsigned long timeout;
2330         u16 reg;
2331         int err;
2332         int i;
2333
2334         /* Set all ports to the disabled state. */
2335         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2336                 err = mv88e6xxx_port_set_state(chip, i,
2337                                                PORT_CONTROL_STATE_DISABLED);
2338                 if (err)
2339                         return err;
2340         }
2341
2342         /* Wait for transmit queues to drain. */
2343         usleep_range(2000, 4000);
2344
2345         /* If there is a gpio connected to the reset pin, toggle it */
2346         if (gpiod) {
2347                 gpiod_set_value_cansleep(gpiod, 1);
2348                 usleep_range(10000, 20000);
2349                 gpiod_set_value_cansleep(gpiod, 0);
2350                 usleep_range(10000, 20000);
2351         }
2352
2353         /* Reset the switch. Keep the PPU active if requested. The PPU
2354          * needs to be active to support indirect phy register access
2355          * through global registers 0x18 and 0x19.
2356          */
2357         if (ppu_active)
2358                 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2359         else
2360                 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2361         if (err)
2362                 return err;
2363
2364         /* Wait up to one second for reset to complete. */
2365         timeout = jiffies + 1 * HZ;
2366         while (time_before(jiffies, timeout)) {
2367                 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2368                 if (err)
2369                         return err;
2370
2371                 if ((reg & is_reset) == is_reset)
2372                         break;
2373                 usleep_range(1000, 2000);
2374         }
2375         if (time_after(jiffies, timeout))
2376                 err = -ETIMEDOUT;
2377         else
2378                 err = 0;
2379
2380         return err;
2381 }
2382
2383 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2384 {
2385         u16 val;
2386         int err;
2387
2388         /* Clear Power Down bit */
2389         err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2390         if (err)
2391                 return err;
2392
2393         if (val & BMCR_PDOWN) {
2394                 val &= ~BMCR_PDOWN;
2395                 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2396         }
2397
2398         return err;
2399 }
2400
2401 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2402 {
2403         struct dsa_switch *ds = chip->ds;
2404         int err;
2405         u16 reg;
2406
2407         /* MAC Forcing register: don't force link, speed, duplex or flow control
2408          * state to any particular values on physical ports, but force the CPU
2409          * port and all DSA ports to their maximum bandwidth and full duplex.
2410          */
2411         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2412                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2413                                                SPEED_MAX, DUPLEX_FULL,
2414                                                PHY_INTERFACE_MODE_NA);
2415         else
2416                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2417                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2418                                                PHY_INTERFACE_MODE_NA);
2419         if (err)
2420                 return err;
2421
2422         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2423          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2424          * tunneling, determine priority by looking at 802.1p and IP
2425          * priority fields (IP prio has precedence), and set STP state
2426          * to Forwarding.
2427          *
2428          * If this is the CPU link, use DSA or EDSA tagging depending
2429          * on which tagging mode was configured.
2430          *
2431          * If this is a link to another switch, use DSA tagging mode.
2432          *
2433          * If this is the upstream port for this switch, enable
2434          * forwarding of unknown unicasts and multicasts.
2435          */
2436         reg = 0;
2437         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2438             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2439             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2440             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2441                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2442                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2443                 PORT_CONTROL_STATE_FORWARDING;
2444         if (dsa_is_cpu_port(ds, port)) {
2445                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2446                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2447                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2448                 else
2449                         reg |= PORT_CONTROL_DSA_TAG;
2450                 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2451                         PORT_CONTROL_FORWARD_UNKNOWN;
2452         }
2453         if (dsa_is_dsa_port(ds, port)) {
2454                 if (mv88e6xxx_6095_family(chip) ||
2455                     mv88e6xxx_6185_family(chip))
2456                         reg |= PORT_CONTROL_DSA_TAG;
2457                 if (mv88e6xxx_6352_family(chip) ||
2458                     mv88e6xxx_6351_family(chip) ||
2459                     mv88e6xxx_6165_family(chip) ||
2460                     mv88e6xxx_6097_family(chip) ||
2461                     mv88e6xxx_6320_family(chip)) {
2462                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2463                 }
2464
2465                 if (port == dsa_upstream_port(ds))
2466                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2467                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2468         }
2469         if (reg) {
2470                 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2471                 if (err)
2472                         return err;
2473         }
2474
2475         /* If this port is connected to a SerDes, make sure the SerDes is not
2476          * powered down.
2477          */
2478         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2479                 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2480                 if (err)
2481                         return err;
2482                 reg &= PORT_STATUS_CMODE_MASK;
2483                 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2484                     (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2485                     (reg == PORT_STATUS_CMODE_SGMII)) {
2486                         err = mv88e6xxx_serdes_power_on(chip);
2487                         if (err < 0)
2488                                 return err;
2489                 }
2490         }
2491
2492         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2493          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2494          * untagged frames on this port, do a destination address lookup on all
2495          * received packets as usual, disable ARP mirroring and don't send a
2496          * copy of all transmitted/received frames on this port to the CPU.
2497          */
2498         reg = 0;
2499         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2500             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2501             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2502             mv88e6xxx_6185_family(chip))
2503                 reg = PORT_CONTROL_2_MAP_DA;
2504
2505         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2506             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2507                 reg |= PORT_CONTROL_2_JUMBO_10240;
2508
2509         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2510                 /* Set the upstream port this port should use */
2511                 reg |= dsa_upstream_port(ds);
2512                 /* enable forwarding of unknown multicast addresses to
2513                  * the upstream port
2514                  */
2515                 if (port == dsa_upstream_port(ds))
2516                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2517         }
2518
2519         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2520
2521         if (reg) {
2522                 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2523                 if (err)
2524                         return err;
2525         }
2526
2527         /* Port Association Vector: when learning source addresses
2528          * of packets, add the address to the address database using
2529          * a port bitmap that has only the bit for this port set and
2530          * the other bits clear.
2531          */
2532         reg = 1 << port;
2533         /* Disable learning for CPU port */
2534         if (dsa_is_cpu_port(ds, port))
2535                 reg = 0;
2536
2537         err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2538         if (err)
2539                 return err;
2540
2541         /* Egress rate control 2: disable egress rate control. */
2542         err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2543         if (err)
2544                 return err;
2545
2546         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2547             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2548             mv88e6xxx_6320_family(chip)) {
2549                 /* Do not limit the period of time that this port can
2550                  * be paused for by the remote end or the period of
2551                  * time that this port can pause the remote end.
2552                  */
2553                 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2554                 if (err)
2555                         return err;
2556
2557                 /* Port ATU control: disable limiting the number of
2558                  * address database entries that this port is allowed
2559                  * to use.
2560                  */
2561                 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2562                                            0x0000);
2563                 /* Priority Override: disable DA, SA and VTU priority
2564                  * override.
2565                  */
2566                 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2567                                            0x0000);
2568                 if (err)
2569                         return err;
2570
2571                 /* Port Ethertype: use the Ethertype DSA Ethertype
2572                  * value.
2573                  */
2574                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2575                         err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2576                                                    ETH_P_EDSA);
2577                         if (err)
2578                                 return err;
2579                 }
2580
2581                 /* Tag Remap: use an identity 802.1p prio -> switch
2582                  * prio mapping.
2583                  */
2584                 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2585                                            0x3210);
2586                 if (err)
2587                         return err;
2588
2589                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2590                  * prio mapping.
2591                  */
2592                 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2593                                            0x7654);
2594                 if (err)
2595                         return err;
2596         }
2597
2598         /* Rate Control: disable ingress rate limiting. */
2599         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2600             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2601             mv88e6xxx_6320_family(chip)) {
2602                 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2603                                            0x0001);
2604                 if (err)
2605                         return err;
2606         } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2607                 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2608                                            0x0000);
2609                 if (err)
2610                         return err;
2611         }
2612
2613         /* Port Control 1: disable trunking, disable sending
2614          * learning messages to this port.
2615          */
2616         err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2617         if (err)
2618                 return err;
2619
2620         /* Port based VLAN map: give each port the same default address
2621          * database, and allow bidirectional communication between the
2622          * CPU and DSA port(s), and the other ports.
2623          */
2624         err = mv88e6xxx_port_set_fid(chip, port, 0);
2625         if (err)
2626                 return err;
2627
2628         err = _mv88e6xxx_port_based_vlan_map(chip, port);
2629         if (err)
2630                 return err;
2631
2632         /* Default VLAN ID and priority: don't set a default VLAN
2633          * ID, and set the default packet priority to zero.
2634          */
2635         return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2636 }
2637
2638 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2639 {
2640         int err;
2641
2642         err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2643         if (err)
2644                 return err;
2645
2646         err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2647         if (err)
2648                 return err;
2649
2650         err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2651         if (err)
2652                 return err;
2653
2654         return 0;
2655 }
2656
2657 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2658                                      unsigned int msecs)
2659 {
2660         const unsigned int coeff = chip->info->age_time_coeff;
2661         const unsigned int min = 0x01 * coeff;
2662         const unsigned int max = 0xff * coeff;
2663         u8 age_time;
2664         u16 val;
2665         int err;
2666
2667         if (msecs < min || msecs > max)
2668                 return -ERANGE;
2669
2670         /* Round to nearest multiple of coeff */
2671         age_time = (msecs + coeff / 2) / coeff;
2672
2673         err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2674         if (err)
2675                 return err;
2676
2677         /* AgeTime is 11:4 bits */
2678         val &= ~0xff0;
2679         val |= age_time << 4;
2680
2681         return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2682 }
2683
2684 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2685                                      unsigned int ageing_time)
2686 {
2687         struct mv88e6xxx_chip *chip = ds->priv;
2688         int err;
2689
2690         mutex_lock(&chip->reg_lock);
2691         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2692         mutex_unlock(&chip->reg_lock);
2693
2694         return err;
2695 }
2696
2697 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2698 {
2699         struct dsa_switch *ds = chip->ds;
2700         u32 upstream_port = dsa_upstream_port(ds);
2701         u16 reg;
2702         int err;
2703
2704         /* Enable the PHY Polling Unit if present, don't discard any packets,
2705          * and mask all interrupt sources.
2706          */
2707         err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
2708         if (err < 0)
2709                 return err;
2710
2711         reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
2712         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2713             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2714                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2715
2716         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2717         if (err)
2718                 return err;
2719
2720         /* Configure the upstream port, and configure it as the port to which
2721          * ingress and egress and ARP monitor frames are to be sent.
2722          */
2723         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2724                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2725                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2726         err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
2727         if (err)
2728                 return err;
2729
2730         /* Disable remote management, and set the switch's DSA device number. */
2731         err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2732                                  GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2733                                  (ds->index & 0x1f));
2734         if (err)
2735                 return err;
2736
2737         /* Clear all the VTU and STU entries */
2738         err = _mv88e6xxx_vtu_stu_flush(chip);
2739         if (err < 0)
2740                 return err;
2741
2742         /* Set the default address aging time to 5 minutes, and
2743          * enable address learn messages to be sent to all message
2744          * ports.
2745          */
2746         err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2747                                  GLOBAL_ATU_CONTROL_LEARN2ALL);
2748         if (err)
2749                 return err;
2750
2751         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2752         if (err)
2753                 return err;
2754
2755         /* Clear all ATU entries */
2756         err = _mv88e6xxx_atu_flush(chip, 0, true);
2757         if (err)
2758                 return err;
2759
2760         /* Configure the IP ToS mapping registers. */
2761         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2762         if (err)
2763                 return err;
2764         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2765         if (err)
2766                 return err;
2767         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2768         if (err)
2769                 return err;
2770         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2771         if (err)
2772                 return err;
2773         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2774         if (err)
2775                 return err;
2776         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2777         if (err)
2778                 return err;
2779         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2780         if (err)
2781                 return err;
2782         err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2783         if (err)
2784                 return err;
2785
2786         /* Configure the IEEE 802.1p priority mapping register. */
2787         err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2788         if (err)
2789                 return err;
2790
2791         /* Clear the statistics counters for all ports */
2792         err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2793                                  GLOBAL_STATS_OP_FLUSH_ALL);
2794         if (err)
2795                 return err;
2796
2797         /* Wait for the flush to complete. */
2798         err = _mv88e6xxx_stats_wait(chip);
2799         if (err)
2800                 return err;
2801
2802         return 0;
2803 }
2804
2805 static int mv88e6xxx_setup(struct dsa_switch *ds)
2806 {
2807         struct mv88e6xxx_chip *chip = ds->priv;
2808         int err;
2809         int i;
2810
2811         chip->ds = ds;
2812         ds->slave_mii_bus = chip->mdio_bus;
2813
2814         mutex_lock(&chip->reg_lock);
2815
2816         /* Setup Switch Port Registers */
2817         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2818                 err = mv88e6xxx_setup_port(chip, i);
2819                 if (err)
2820                         goto unlock;
2821         }
2822
2823         /* Setup Switch Global 1 Registers */
2824         err = mv88e6xxx_g1_setup(chip);
2825         if (err)
2826                 goto unlock;
2827
2828         /* Setup Switch Global 2 Registers */
2829         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2830                 err = mv88e6xxx_g2_setup(chip);
2831                 if (err)
2832                         goto unlock;
2833         }
2834
2835 unlock:
2836         mutex_unlock(&chip->reg_lock);
2837
2838         return err;
2839 }
2840
2841 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2842 {
2843         struct mv88e6xxx_chip *chip = ds->priv;
2844         int err;
2845
2846         if (!chip->info->ops->set_switch_mac)
2847                 return -EOPNOTSUPP;
2848
2849         mutex_lock(&chip->reg_lock);
2850         err = chip->info->ops->set_switch_mac(chip, addr);
2851         mutex_unlock(&chip->reg_lock);
2852
2853         return err;
2854 }
2855
2856 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2857 {
2858         struct mv88e6xxx_chip *chip = bus->priv;
2859         u16 val;
2860         int err;
2861
2862         if (phy >= mv88e6xxx_num_ports(chip))
2863                 return 0xffff;
2864
2865         mutex_lock(&chip->reg_lock);
2866         err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2867         mutex_unlock(&chip->reg_lock);
2868
2869         return err ? err : val;
2870 }
2871
2872 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2873 {
2874         struct mv88e6xxx_chip *chip = bus->priv;
2875         int err;
2876
2877         if (phy >= mv88e6xxx_num_ports(chip))
2878                 return 0xffff;
2879
2880         mutex_lock(&chip->reg_lock);
2881         err = mv88e6xxx_phy_write(chip, phy, reg, val);
2882         mutex_unlock(&chip->reg_lock);
2883
2884         return err;
2885 }
2886
2887 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2888                                    struct device_node *np)
2889 {
2890         static int index;
2891         struct mii_bus *bus;
2892         int err;
2893
2894         if (np)
2895                 chip->mdio_np = of_get_child_by_name(np, "mdio");
2896
2897         bus = devm_mdiobus_alloc(chip->dev);
2898         if (!bus)
2899                 return -ENOMEM;
2900
2901         bus->priv = (void *)chip;
2902         if (np) {
2903                 bus->name = np->full_name;
2904                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2905         } else {
2906                 bus->name = "mv88e6xxx SMI";
2907                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2908         }
2909
2910         bus->read = mv88e6xxx_mdio_read;
2911         bus->write = mv88e6xxx_mdio_write;
2912         bus->parent = chip->dev;
2913
2914         if (chip->mdio_np)
2915                 err = of_mdiobus_register(bus, chip->mdio_np);
2916         else
2917                 err = mdiobus_register(bus);
2918         if (err) {
2919                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2920                 goto out;
2921         }
2922         chip->mdio_bus = bus;
2923
2924         return 0;
2925
2926 out:
2927         if (chip->mdio_np)
2928                 of_node_put(chip->mdio_np);
2929
2930         return err;
2931 }
2932
2933 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
2934
2935 {
2936         struct mii_bus *bus = chip->mdio_bus;
2937
2938         mdiobus_unregister(bus);
2939
2940         if (chip->mdio_np)
2941                 of_node_put(chip->mdio_np);
2942 }
2943
2944 #ifdef CONFIG_NET_DSA_HWMON
2945
2946 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2947 {
2948         struct mv88e6xxx_chip *chip = ds->priv;
2949         u16 val;
2950         int ret;
2951
2952         *temp = 0;
2953
2954         mutex_lock(&chip->reg_lock);
2955
2956         ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
2957         if (ret < 0)
2958                 goto error;
2959
2960         /* Enable temperature sensor */
2961         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2962         if (ret < 0)
2963                 goto error;
2964
2965         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
2966         if (ret < 0)
2967                 goto error;
2968
2969         /* Wait for temperature to stabilize */
2970         usleep_range(10000, 12000);
2971
2972         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2973         if (ret < 0)
2974                 goto error;
2975
2976         /* Disable temperature sensor */
2977         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
2978         if (ret < 0)
2979                 goto error;
2980
2981         *temp = ((val & 0x1f) - 5) * 5;
2982
2983 error:
2984         mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
2985         mutex_unlock(&chip->reg_lock);
2986         return ret;
2987 }
2988
2989 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2990 {
2991         struct mv88e6xxx_chip *chip = ds->priv;
2992         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
2993         u16 val;
2994         int ret;
2995
2996         *temp = 0;
2997
2998         mutex_lock(&chip->reg_lock);
2999         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3000         mutex_unlock(&chip->reg_lock);
3001         if (ret < 0)
3002                 return ret;
3003
3004         *temp = (val & 0xff) - 25;
3005
3006         return 0;
3007 }
3008
3009 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3010 {
3011         struct mv88e6xxx_chip *chip = ds->priv;
3012
3013         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3014                 return -EOPNOTSUPP;
3015
3016         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3017                 return mv88e63xx_get_temp(ds, temp);
3018
3019         return mv88e61xx_get_temp(ds, temp);
3020 }
3021
3022 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3023 {
3024         struct mv88e6xxx_chip *chip = ds->priv;
3025         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3026         u16 val;
3027         int ret;
3028
3029         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3030                 return -EOPNOTSUPP;
3031
3032         *temp = 0;
3033
3034         mutex_lock(&chip->reg_lock);
3035         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3036         mutex_unlock(&chip->reg_lock);
3037         if (ret < 0)
3038                 return ret;
3039
3040         *temp = (((val >> 8) & 0x1f) * 5) - 25;
3041
3042         return 0;
3043 }
3044
3045 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3046 {
3047         struct mv88e6xxx_chip *chip = ds->priv;
3048         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3049         u16 val;
3050         int err;
3051
3052         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3053                 return -EOPNOTSUPP;
3054
3055         mutex_lock(&chip->reg_lock);
3056         err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3057         if (err)
3058                 goto unlock;
3059         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3060         err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3061                                        (val & 0xe0ff) | (temp << 8));
3062 unlock:
3063         mutex_unlock(&chip->reg_lock);
3064
3065         return err;
3066 }
3067
3068 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3069 {
3070         struct mv88e6xxx_chip *chip = ds->priv;
3071         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3072         u16 val;
3073         int ret;
3074
3075         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3076                 return -EOPNOTSUPP;
3077
3078         *alarm = false;
3079
3080         mutex_lock(&chip->reg_lock);
3081         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3082         mutex_unlock(&chip->reg_lock);
3083         if (ret < 0)
3084                 return ret;
3085
3086         *alarm = !!(val & 0x40);
3087
3088         return 0;
3089 }
3090 #endif /* CONFIG_NET_DSA_HWMON */
3091
3092 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3093 {
3094         struct mv88e6xxx_chip *chip = ds->priv;
3095
3096         return chip->eeprom_len;
3097 }
3098
3099 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3100                                 struct ethtool_eeprom *eeprom, u8 *data)
3101 {
3102         struct mv88e6xxx_chip *chip = ds->priv;
3103         int err;
3104
3105         if (!chip->info->ops->get_eeprom)
3106                 return -EOPNOTSUPP;
3107
3108         mutex_lock(&chip->reg_lock);
3109         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3110         mutex_unlock(&chip->reg_lock);
3111
3112         if (err)
3113                 return err;
3114
3115         eeprom->magic = 0xc3ec4951;
3116
3117         return 0;
3118 }
3119
3120 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3121                                 struct ethtool_eeprom *eeprom, u8 *data)
3122 {
3123         struct mv88e6xxx_chip *chip = ds->priv;
3124         int err;
3125
3126         if (!chip->info->ops->set_eeprom)
3127                 return -EOPNOTSUPP;
3128
3129         if (eeprom->magic != 0xc3ec4951)
3130                 return -EINVAL;
3131
3132         mutex_lock(&chip->reg_lock);
3133         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3134         mutex_unlock(&chip->reg_lock);
3135
3136         return err;
3137 }
3138
3139 static const struct mv88e6xxx_ops mv88e6085_ops = {
3140         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3141         .phy_read = mv88e6xxx_phy_ppu_read,
3142         .phy_write = mv88e6xxx_phy_ppu_write,
3143         .port_set_link = mv88e6xxx_port_set_link,
3144         .port_set_duplex = mv88e6xxx_port_set_duplex,
3145         .port_set_speed = mv88e6185_port_set_speed,
3146 };
3147
3148 static const struct mv88e6xxx_ops mv88e6095_ops = {
3149         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3150         .phy_read = mv88e6xxx_phy_ppu_read,
3151         .phy_write = mv88e6xxx_phy_ppu_write,
3152         .port_set_link = mv88e6xxx_port_set_link,
3153         .port_set_duplex = mv88e6xxx_port_set_duplex,
3154         .port_set_speed = mv88e6185_port_set_speed,
3155 };
3156
3157 static const struct mv88e6xxx_ops mv88e6123_ops = {
3158         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3159         .phy_read = mv88e6xxx_read,
3160         .phy_write = mv88e6xxx_write,
3161         .port_set_link = mv88e6xxx_port_set_link,
3162         .port_set_duplex = mv88e6xxx_port_set_duplex,
3163         .port_set_speed = mv88e6185_port_set_speed,
3164 };
3165
3166 static const struct mv88e6xxx_ops mv88e6131_ops = {
3167         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3168         .phy_read = mv88e6xxx_phy_ppu_read,
3169         .phy_write = mv88e6xxx_phy_ppu_write,
3170         .port_set_link = mv88e6xxx_port_set_link,
3171         .port_set_duplex = mv88e6xxx_port_set_duplex,
3172         .port_set_speed = mv88e6185_port_set_speed,
3173 };
3174
3175 static const struct mv88e6xxx_ops mv88e6161_ops = {
3176         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3177         .phy_read = mv88e6xxx_read,
3178         .phy_write = mv88e6xxx_write,
3179         .port_set_link = mv88e6xxx_port_set_link,
3180         .port_set_duplex = mv88e6xxx_port_set_duplex,
3181         .port_set_speed = mv88e6185_port_set_speed,
3182 };
3183
3184 static const struct mv88e6xxx_ops mv88e6165_ops = {
3185         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3186         .phy_read = mv88e6xxx_read,
3187         .phy_write = mv88e6xxx_write,
3188         .port_set_link = mv88e6xxx_port_set_link,
3189         .port_set_duplex = mv88e6xxx_port_set_duplex,
3190         .port_set_speed = mv88e6185_port_set_speed,
3191 };
3192
3193 static const struct mv88e6xxx_ops mv88e6171_ops = {
3194         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3195         .phy_read = mv88e6xxx_g2_smi_phy_read,
3196         .phy_write = mv88e6xxx_g2_smi_phy_write,
3197         .port_set_link = mv88e6xxx_port_set_link,
3198         .port_set_duplex = mv88e6xxx_port_set_duplex,
3199         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3200         .port_set_speed = mv88e6185_port_set_speed,
3201 };
3202
3203 static const struct mv88e6xxx_ops mv88e6172_ops = {
3204         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3205         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3206         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3207         .phy_read = mv88e6xxx_g2_smi_phy_read,
3208         .phy_write = mv88e6xxx_g2_smi_phy_write,
3209         .port_set_link = mv88e6xxx_port_set_link,
3210         .port_set_duplex = mv88e6xxx_port_set_duplex,
3211         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3212         .port_set_speed = mv88e6352_port_set_speed,
3213 };
3214
3215 static const struct mv88e6xxx_ops mv88e6175_ops = {
3216         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3217         .phy_read = mv88e6xxx_g2_smi_phy_read,
3218         .phy_write = mv88e6xxx_g2_smi_phy_write,
3219         .port_set_link = mv88e6xxx_port_set_link,
3220         .port_set_duplex = mv88e6xxx_port_set_duplex,
3221         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3222         .port_set_speed = mv88e6185_port_set_speed,
3223 };
3224
3225 static const struct mv88e6xxx_ops mv88e6176_ops = {
3226         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3227         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3228         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3229         .phy_read = mv88e6xxx_g2_smi_phy_read,
3230         .phy_write = mv88e6xxx_g2_smi_phy_write,
3231         .port_set_link = mv88e6xxx_port_set_link,
3232         .port_set_duplex = mv88e6xxx_port_set_duplex,
3233         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3234         .port_set_speed = mv88e6352_port_set_speed,
3235 };
3236
3237 static const struct mv88e6xxx_ops mv88e6185_ops = {
3238         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3239         .phy_read = mv88e6xxx_phy_ppu_read,
3240         .phy_write = mv88e6xxx_phy_ppu_write,
3241         .port_set_link = mv88e6xxx_port_set_link,
3242         .port_set_duplex = mv88e6xxx_port_set_duplex,
3243         .port_set_speed = mv88e6185_port_set_speed,
3244 };
3245
3246 static const struct mv88e6xxx_ops mv88e6240_ops = {
3247         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3248         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3249         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3250         .phy_read = mv88e6xxx_g2_smi_phy_read,
3251         .phy_write = mv88e6xxx_g2_smi_phy_write,
3252         .port_set_link = mv88e6xxx_port_set_link,
3253         .port_set_duplex = mv88e6xxx_port_set_duplex,
3254         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3255         .port_set_speed = mv88e6352_port_set_speed,
3256 };
3257
3258 static const struct mv88e6xxx_ops mv88e6320_ops = {
3259         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3260         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3261         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3262         .phy_read = mv88e6xxx_g2_smi_phy_read,
3263         .phy_write = mv88e6xxx_g2_smi_phy_write,
3264         .port_set_link = mv88e6xxx_port_set_link,
3265         .port_set_duplex = mv88e6xxx_port_set_duplex,
3266         .port_set_speed = mv88e6185_port_set_speed,
3267 };
3268
3269 static const struct mv88e6xxx_ops mv88e6321_ops = {
3270         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3271         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3272         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3273         .phy_read = mv88e6xxx_g2_smi_phy_read,
3274         .phy_write = mv88e6xxx_g2_smi_phy_write,
3275         .port_set_link = mv88e6xxx_port_set_link,
3276         .port_set_duplex = mv88e6xxx_port_set_duplex,
3277         .port_set_speed = mv88e6185_port_set_speed,
3278 };
3279
3280 static const struct mv88e6xxx_ops mv88e6350_ops = {
3281         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3282         .phy_read = mv88e6xxx_g2_smi_phy_read,
3283         .phy_write = mv88e6xxx_g2_smi_phy_write,
3284         .port_set_link = mv88e6xxx_port_set_link,
3285         .port_set_duplex = mv88e6xxx_port_set_duplex,
3286         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3287         .port_set_speed = mv88e6185_port_set_speed,
3288 };
3289
3290 static const struct mv88e6xxx_ops mv88e6351_ops = {
3291         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3292         .phy_read = mv88e6xxx_g2_smi_phy_read,
3293         .phy_write = mv88e6xxx_g2_smi_phy_write,
3294         .port_set_link = mv88e6xxx_port_set_link,
3295         .port_set_duplex = mv88e6xxx_port_set_duplex,
3296         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3297         .port_set_speed = mv88e6185_port_set_speed,
3298 };
3299
3300 static const struct mv88e6xxx_ops mv88e6352_ops = {
3301         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3302         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3303         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3304         .phy_read = mv88e6xxx_g2_smi_phy_read,
3305         .phy_write = mv88e6xxx_g2_smi_phy_write,
3306         .port_set_link = mv88e6xxx_port_set_link,
3307         .port_set_duplex = mv88e6xxx_port_set_duplex,
3308         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3309         .port_set_speed = mv88e6352_port_set_speed,
3310 };
3311
3312 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3313         [MV88E6085] = {
3314                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3315                 .family = MV88E6XXX_FAMILY_6097,
3316                 .name = "Marvell 88E6085",
3317                 .num_databases = 4096,
3318                 .num_ports = 10,
3319                 .port_base_addr = 0x10,
3320                 .global1_addr = 0x1b,
3321                 .age_time_coeff = 15000,
3322                 .g1_irqs = 8,
3323                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3324                 .ops = &mv88e6085_ops,
3325         },
3326
3327         [MV88E6095] = {
3328                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3329                 .family = MV88E6XXX_FAMILY_6095,
3330                 .name = "Marvell 88E6095/88E6095F",
3331                 .num_databases = 256,
3332                 .num_ports = 11,
3333                 .port_base_addr = 0x10,
3334                 .global1_addr = 0x1b,
3335                 .age_time_coeff = 15000,
3336                 .g1_irqs = 8,
3337                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3338                 .ops = &mv88e6095_ops,
3339         },
3340
3341         [MV88E6123] = {
3342                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3343                 .family = MV88E6XXX_FAMILY_6165,
3344                 .name = "Marvell 88E6123",
3345                 .num_databases = 4096,
3346                 .num_ports = 3,
3347                 .port_base_addr = 0x10,
3348                 .global1_addr = 0x1b,
3349                 .age_time_coeff = 15000,
3350                 .g1_irqs = 9,
3351                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3352                 .ops = &mv88e6123_ops,
3353         },
3354
3355         [MV88E6131] = {
3356                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3357                 .family = MV88E6XXX_FAMILY_6185,
3358                 .name = "Marvell 88E6131",
3359                 .num_databases = 256,
3360                 .num_ports = 8,
3361                 .port_base_addr = 0x10,
3362                 .global1_addr = 0x1b,
3363                 .age_time_coeff = 15000,
3364                 .g1_irqs = 9,
3365                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3366                 .ops = &mv88e6131_ops,
3367         },
3368
3369         [MV88E6161] = {
3370                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3371                 .family = MV88E6XXX_FAMILY_6165,
3372                 .name = "Marvell 88E6161",
3373                 .num_databases = 4096,
3374                 .num_ports = 6,
3375                 .port_base_addr = 0x10,
3376                 .global1_addr = 0x1b,
3377                 .age_time_coeff = 15000,
3378                 .g1_irqs = 9,
3379                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3380                 .ops = &mv88e6161_ops,
3381         },
3382
3383         [MV88E6165] = {
3384                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3385                 .family = MV88E6XXX_FAMILY_6165,
3386                 .name = "Marvell 88E6165",
3387                 .num_databases = 4096,
3388                 .num_ports = 6,
3389                 .port_base_addr = 0x10,
3390                 .global1_addr = 0x1b,
3391                 .age_time_coeff = 15000,
3392                 .g1_irqs = 9,
3393                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3394                 .ops = &mv88e6165_ops,
3395         },
3396
3397         [MV88E6171] = {
3398                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3399                 .family = MV88E6XXX_FAMILY_6351,
3400                 .name = "Marvell 88E6171",
3401                 .num_databases = 4096,
3402                 .num_ports = 7,
3403                 .port_base_addr = 0x10,
3404                 .global1_addr = 0x1b,
3405                 .age_time_coeff = 15000,
3406                 .g1_irqs = 9,
3407                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3408                 .ops = &mv88e6171_ops,
3409         },
3410
3411         [MV88E6172] = {
3412                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3413                 .family = MV88E6XXX_FAMILY_6352,
3414                 .name = "Marvell 88E6172",
3415                 .num_databases = 4096,
3416                 .num_ports = 7,
3417                 .port_base_addr = 0x10,
3418                 .global1_addr = 0x1b,
3419                 .age_time_coeff = 15000,
3420                 .g1_irqs = 9,
3421                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3422                 .ops = &mv88e6172_ops,
3423         },
3424
3425         [MV88E6175] = {
3426                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3427                 .family = MV88E6XXX_FAMILY_6351,
3428                 .name = "Marvell 88E6175",
3429                 .num_databases = 4096,
3430                 .num_ports = 7,
3431                 .port_base_addr = 0x10,
3432                 .global1_addr = 0x1b,
3433                 .age_time_coeff = 15000,
3434                 .g1_irqs = 9,
3435                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3436                 .ops = &mv88e6175_ops,
3437         },
3438
3439         [MV88E6176] = {
3440                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3441                 .family = MV88E6XXX_FAMILY_6352,
3442                 .name = "Marvell 88E6176",
3443                 .num_databases = 4096,
3444                 .num_ports = 7,
3445                 .port_base_addr = 0x10,
3446                 .global1_addr = 0x1b,
3447                 .age_time_coeff = 15000,
3448                 .g1_irqs = 9,
3449                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3450                 .ops = &mv88e6176_ops,
3451         },
3452
3453         [MV88E6185] = {
3454                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3455                 .family = MV88E6XXX_FAMILY_6185,
3456                 .name = "Marvell 88E6185",
3457                 .num_databases = 256,
3458                 .num_ports = 10,
3459                 .port_base_addr = 0x10,
3460                 .global1_addr = 0x1b,
3461                 .age_time_coeff = 15000,
3462                 .g1_irqs = 8,
3463                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3464                 .ops = &mv88e6185_ops,
3465         },
3466
3467         [MV88E6240] = {
3468                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3469                 .family = MV88E6XXX_FAMILY_6352,
3470                 .name = "Marvell 88E6240",
3471                 .num_databases = 4096,
3472                 .num_ports = 7,
3473                 .port_base_addr = 0x10,
3474                 .global1_addr = 0x1b,
3475                 .age_time_coeff = 15000,
3476                 .g1_irqs = 9,
3477                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3478                 .ops = &mv88e6240_ops,
3479         },
3480
3481         [MV88E6320] = {
3482                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3483                 .family = MV88E6XXX_FAMILY_6320,
3484                 .name = "Marvell 88E6320",
3485                 .num_databases = 4096,
3486                 .num_ports = 7,
3487                 .port_base_addr = 0x10,
3488                 .global1_addr = 0x1b,
3489                 .age_time_coeff = 15000,
3490                 .g1_irqs = 8,
3491                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3492                 .ops = &mv88e6320_ops,
3493         },
3494
3495         [MV88E6321] = {
3496                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3497                 .family = MV88E6XXX_FAMILY_6320,
3498                 .name = "Marvell 88E6321",
3499                 .num_databases = 4096,
3500                 .num_ports = 7,
3501                 .port_base_addr = 0x10,
3502                 .global1_addr = 0x1b,
3503                 .age_time_coeff = 15000,
3504                 .g1_irqs = 8,
3505                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3506                 .ops = &mv88e6321_ops,
3507         },
3508
3509         [MV88E6350] = {
3510                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3511                 .family = MV88E6XXX_FAMILY_6351,
3512                 .name = "Marvell 88E6350",
3513                 .num_databases = 4096,
3514                 .num_ports = 7,
3515                 .port_base_addr = 0x10,
3516                 .global1_addr = 0x1b,
3517                 .age_time_coeff = 15000,
3518                 .g1_irqs = 9,
3519                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3520                 .ops = &mv88e6350_ops,
3521         },
3522
3523         [MV88E6351] = {
3524                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3525                 .family = MV88E6XXX_FAMILY_6351,
3526                 .name = "Marvell 88E6351",
3527                 .num_databases = 4096,
3528                 .num_ports = 7,
3529                 .port_base_addr = 0x10,
3530                 .global1_addr = 0x1b,
3531                 .age_time_coeff = 15000,
3532                 .g1_irqs = 9,
3533                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3534                 .ops = &mv88e6351_ops,
3535         },
3536
3537         [MV88E6352] = {
3538                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3539                 .family = MV88E6XXX_FAMILY_6352,
3540                 .name = "Marvell 88E6352",
3541                 .num_databases = 4096,
3542                 .num_ports = 7,
3543                 .port_base_addr = 0x10,
3544                 .global1_addr = 0x1b,
3545                 .age_time_coeff = 15000,
3546                 .g1_irqs = 9,
3547                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3548                 .ops = &mv88e6352_ops,
3549         },
3550 };
3551
3552 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3553 {
3554         int i;
3555
3556         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3557                 if (mv88e6xxx_table[i].prod_num == prod_num)
3558                         return &mv88e6xxx_table[i];
3559
3560         return NULL;
3561 }
3562
3563 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3564 {
3565         const struct mv88e6xxx_info *info;
3566         unsigned int prod_num, rev;
3567         u16 id;
3568         int err;
3569
3570         mutex_lock(&chip->reg_lock);
3571         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3572         mutex_unlock(&chip->reg_lock);
3573         if (err)
3574                 return err;
3575
3576         prod_num = (id & 0xfff0) >> 4;
3577         rev = id & 0x000f;
3578
3579         info = mv88e6xxx_lookup_info(prod_num);
3580         if (!info)
3581                 return -ENODEV;
3582
3583         /* Update the compatible info with the probed one */
3584         chip->info = info;
3585
3586         err = mv88e6xxx_g2_require(chip);
3587         if (err)
3588                 return err;
3589
3590         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3591                  chip->info->prod_num, chip->info->name, rev);
3592
3593         return 0;
3594 }
3595
3596 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3597 {
3598         struct mv88e6xxx_chip *chip;
3599
3600         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3601         if (!chip)
3602                 return NULL;
3603
3604         chip->dev = dev;
3605
3606         mutex_init(&chip->reg_lock);
3607
3608         return chip;
3609 }
3610
3611 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3612 {
3613         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3614                 mv88e6xxx_ppu_state_init(chip);
3615 }
3616
3617 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3618 {
3619         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3620                 mv88e6xxx_ppu_state_destroy(chip);
3621 }
3622
3623 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3624                               struct mii_bus *bus, int sw_addr)
3625 {
3626         /* ADDR[0] pin is unavailable externally and considered zero */
3627         if (sw_addr & 0x1)
3628                 return -EINVAL;
3629
3630         if (sw_addr == 0)
3631                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3632         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3633                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3634         else
3635                 return -EINVAL;
3636
3637         chip->bus = bus;
3638         chip->sw_addr = sw_addr;
3639
3640         return 0;
3641 }
3642
3643 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3644 {
3645         struct mv88e6xxx_chip *chip = ds->priv;
3646
3647         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3648                 return DSA_TAG_PROTO_EDSA;
3649
3650         return DSA_TAG_PROTO_DSA;
3651 }
3652
3653 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3654                                        struct device *host_dev, int sw_addr,
3655                                        void **priv)
3656 {
3657         struct mv88e6xxx_chip *chip;
3658         struct mii_bus *bus;
3659         int err;
3660
3661         bus = dsa_host_dev_to_mii_bus(host_dev);
3662         if (!bus)
3663                 return NULL;
3664
3665         chip = mv88e6xxx_alloc_chip(dsa_dev);
3666         if (!chip)
3667                 return NULL;
3668
3669         /* Legacy SMI probing will only support chips similar to 88E6085 */
3670         chip->info = &mv88e6xxx_table[MV88E6085];
3671
3672         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3673         if (err)
3674                 goto free;
3675
3676         err = mv88e6xxx_detect(chip);
3677         if (err)
3678                 goto free;
3679
3680         mutex_lock(&chip->reg_lock);
3681         err = mv88e6xxx_switch_reset(chip);
3682         mutex_unlock(&chip->reg_lock);
3683         if (err)
3684                 goto free;
3685
3686         mv88e6xxx_phy_init(chip);
3687
3688         err = mv88e6xxx_mdio_register(chip, NULL);
3689         if (err)
3690                 goto free;
3691
3692         *priv = chip;
3693
3694         return chip->info->name;
3695 free:
3696         devm_kfree(dsa_dev, chip);
3697
3698         return NULL;
3699 }
3700
3701 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3702                                       const struct switchdev_obj_port_mdb *mdb,
3703                                       struct switchdev_trans *trans)
3704 {
3705         /* We don't need any dynamic resource from the kernel (yet),
3706          * so skip the prepare phase.
3707          */
3708
3709         return 0;
3710 }
3711
3712 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3713                                    const struct switchdev_obj_port_mdb *mdb,
3714                                    struct switchdev_trans *trans)
3715 {
3716         struct mv88e6xxx_chip *chip = ds->priv;
3717
3718         mutex_lock(&chip->reg_lock);
3719         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3720                                          GLOBAL_ATU_DATA_STATE_MC_STATIC))
3721                 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3722         mutex_unlock(&chip->reg_lock);
3723 }
3724
3725 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3726                                   const struct switchdev_obj_port_mdb *mdb)
3727 {
3728         struct mv88e6xxx_chip *chip = ds->priv;
3729         int err;
3730
3731         mutex_lock(&chip->reg_lock);
3732         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3733                                            GLOBAL_ATU_DATA_STATE_UNUSED);
3734         mutex_unlock(&chip->reg_lock);
3735
3736         return err;
3737 }
3738
3739 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3740                                    struct switchdev_obj_port_mdb *mdb,
3741                                    int (*cb)(struct switchdev_obj *obj))
3742 {
3743         struct mv88e6xxx_chip *chip = ds->priv;
3744         int err;
3745
3746         mutex_lock(&chip->reg_lock);
3747         err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3748         mutex_unlock(&chip->reg_lock);
3749
3750         return err;
3751 }
3752
3753 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3754         .probe                  = mv88e6xxx_drv_probe,
3755         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
3756         .setup                  = mv88e6xxx_setup,
3757         .set_addr               = mv88e6xxx_set_addr,
3758         .adjust_link            = mv88e6xxx_adjust_link,
3759         .get_strings            = mv88e6xxx_get_strings,
3760         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3761         .get_sset_count         = mv88e6xxx_get_sset_count,
3762         .set_eee                = mv88e6xxx_set_eee,
3763         .get_eee                = mv88e6xxx_get_eee,
3764 #ifdef CONFIG_NET_DSA_HWMON
3765         .get_temp               = mv88e6xxx_get_temp,
3766         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3767         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3768         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3769 #endif
3770         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3771         .get_eeprom             = mv88e6xxx_get_eeprom,
3772         .set_eeprom             = mv88e6xxx_set_eeprom,
3773         .get_regs_len           = mv88e6xxx_get_regs_len,
3774         .get_regs               = mv88e6xxx_get_regs,
3775         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3776         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3777         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3778         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3779         .port_fast_age          = mv88e6xxx_port_fast_age,
3780         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3781         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3782         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3783         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3784         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3785         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
3786         .port_fdb_add           = mv88e6xxx_port_fdb_add,
3787         .port_fdb_del           = mv88e6xxx_port_fdb_del,
3788         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3789         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
3790         .port_mdb_add           = mv88e6xxx_port_mdb_add,
3791         .port_mdb_del           = mv88e6xxx_port_mdb_del,
3792         .port_mdb_dump          = mv88e6xxx_port_mdb_dump,
3793 };
3794
3795 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3796                                      struct device_node *np)
3797 {
3798         struct device *dev = chip->dev;
3799         struct dsa_switch *ds;
3800
3801         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3802         if (!ds)
3803                 return -ENOMEM;
3804
3805         ds->dev = dev;
3806         ds->priv = chip;
3807         ds->ops = &mv88e6xxx_switch_ops;
3808
3809         dev_set_drvdata(dev, ds);
3810
3811         return dsa_register_switch(ds, np);
3812 }
3813
3814 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3815 {
3816         dsa_unregister_switch(chip->ds);
3817 }
3818
3819 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3820 {
3821         struct device *dev = &mdiodev->dev;
3822         struct device_node *np = dev->of_node;
3823         const struct mv88e6xxx_info *compat_info;
3824         struct mv88e6xxx_chip *chip;
3825         u32 eeprom_len;
3826         int err;
3827
3828         compat_info = of_device_get_match_data(dev);
3829         if (!compat_info)
3830                 return -EINVAL;
3831
3832         chip = mv88e6xxx_alloc_chip(dev);
3833         if (!chip)
3834                 return -ENOMEM;
3835
3836         chip->info = compat_info;
3837
3838         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3839         if (err)
3840                 return err;
3841
3842         err = mv88e6xxx_detect(chip);
3843         if (err)
3844                 return err;
3845
3846         mv88e6xxx_phy_init(chip);
3847
3848         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3849         if (IS_ERR(chip->reset))
3850                 return PTR_ERR(chip->reset);
3851
3852         if (chip->info->ops->get_eeprom &&
3853             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3854                 chip->eeprom_len = eeprom_len;
3855
3856         mutex_lock(&chip->reg_lock);
3857         err = mv88e6xxx_switch_reset(chip);
3858         mutex_unlock(&chip->reg_lock);
3859         if (err)
3860                 goto out;
3861
3862         chip->irq = of_irq_get(np, 0);
3863         if (chip->irq == -EPROBE_DEFER) {
3864                 err = chip->irq;
3865                 goto out;
3866         }
3867
3868         if (chip->irq > 0) {
3869                 /* Has to be performed before the MDIO bus is created,
3870                  * because the PHYs will link there interrupts to these
3871                  * interrupt controllers
3872                  */
3873                 mutex_lock(&chip->reg_lock);
3874                 err = mv88e6xxx_g1_irq_setup(chip);
3875                 mutex_unlock(&chip->reg_lock);
3876
3877                 if (err)
3878                         goto out;
3879
3880                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
3881                         err = mv88e6xxx_g2_irq_setup(chip);
3882                         if (err)
3883                                 goto out_g1_irq;
3884                 }
3885         }
3886
3887         err = mv88e6xxx_mdio_register(chip, np);
3888         if (err)
3889                 goto out_g2_irq;
3890
3891         err = mv88e6xxx_register_switch(chip, np);
3892         if (err)
3893                 goto out_mdio;
3894
3895         return 0;
3896
3897 out_mdio:
3898         mv88e6xxx_mdio_unregister(chip);
3899 out_g2_irq:
3900         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
3901                 mv88e6xxx_g2_irq_free(chip);
3902 out_g1_irq:
3903         if (chip->irq > 0)
3904                 mv88e6xxx_g1_irq_free(chip);
3905 out:
3906         return err;
3907 }
3908
3909 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3910 {
3911         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3912         struct mv88e6xxx_chip *chip = ds->priv;
3913
3914         mv88e6xxx_phy_destroy(chip);
3915         mv88e6xxx_unregister_switch(chip);
3916         mv88e6xxx_mdio_unregister(chip);
3917
3918         if (chip->irq > 0) {
3919                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
3920                         mv88e6xxx_g2_irq_free(chip);
3921                 mv88e6xxx_g1_irq_free(chip);
3922         }
3923 }
3924
3925 static const struct of_device_id mv88e6xxx_of_match[] = {
3926         {
3927                 .compatible = "marvell,mv88e6085",
3928                 .data = &mv88e6xxx_table[MV88E6085],
3929         },
3930         { /* sentinel */ },
3931 };
3932
3933 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3934
3935 static struct mdio_driver mv88e6xxx_driver = {
3936         .probe  = mv88e6xxx_probe,
3937         .remove = mv88e6xxx_remove,
3938         .mdiodrv.driver = {
3939                 .name = "mv88e6085",
3940                 .of_match_table = mv88e6xxx_of_match,
3941         },
3942 };
3943
3944 static int __init mv88e6xxx_init(void)
3945 {
3946         register_switch_driver(&mv88e6xxx_switch_ops);
3947         return mdio_driver_register(&mv88e6xxx_driver);
3948 }
3949 module_init(mv88e6xxx_init);
3950
3951 static void __exit mv88e6xxx_cleanup(void)
3952 {
3953         mdio_driver_unregister(&mv88e6xxx_driver);
3954         unregister_switch_driver(&mv88e6xxx_switch_ops);
3955 }
3956 module_exit(mv88e6xxx_cleanup);
3957
3958 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3959 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3960 MODULE_LICENSE("GPL");