2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/debugfs.h>
15 #include <linux/delay.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/jiffies.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
23 #include <linux/phy.h>
24 #include <linux/seq_file.h>
26 #include "mv88e6xxx.h"
28 /* MDIO bus access can be nested in the case of PHYs connected to the
29 * internal MDIO bus of the switch, which is accessed via MDIO bus of
30 * the Ethernet interface. Avoid lockdep false positives by using
31 * mutex_lock_nested().
33 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
37 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
38 ret = bus->read(bus, addr, regnum);
39 mutex_unlock(&bus->mdio_lock);
44 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
49 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
50 ret = bus->write(bus, addr, regnum, val);
51 mutex_unlock(&bus->mdio_lock);
56 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
57 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
58 * will be directly accessible on some {device address,register address}
59 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
60 * will only respond to SMI transactions to that specific address, and
61 * an indirect addressing mechanism needs to be used to access its
64 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
69 for (i = 0; i < 16; i++) {
70 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
74 if ((ret & SMI_CMD_BUSY) == 0)
81 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
86 return mv88e6xxx_mdiobus_read(bus, addr, reg);
88 /* Wait for the bus to become free. */
89 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
93 /* Transmit the read command. */
94 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
95 SMI_CMD_OP_22_READ | (addr << 5) | reg);
99 /* Wait for the read command to complete. */
100 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
105 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
112 /* Must be called with SMI mutex held */
113 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
115 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
121 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
125 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
131 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
133 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
136 mutex_lock(&ps->smi_mutex);
137 ret = _mv88e6xxx_reg_read(ds, addr, reg);
138 mutex_unlock(&ps->smi_mutex);
143 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
149 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
151 /* Wait for the bus to become free. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
156 /* Transmit the data to write. */
157 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
161 /* Transmit the write command. */
162 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
163 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
167 /* Wait for the write command to complete. */
168 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
175 /* Must be called with SMI mutex held */
176 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
179 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
184 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
187 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
190 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
192 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
195 mutex_lock(&ps->smi_mutex);
196 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
197 mutex_unlock(&ps->smi_mutex);
202 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
206 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
211 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
216 for (i = 0; i < 6; i++) {
219 /* Write the MAC address byte. */
220 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
221 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
223 /* Wait for the write to complete. */
224 for (j = 0; j < 16; j++) {
225 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
226 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
236 /* Must be called with SMI mutex held */
237 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
240 return _mv88e6xxx_reg_read(ds, addr, regnum);
244 /* Must be called with SMI mutex held */
245 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
249 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
253 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
254 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
257 unsigned long timeout;
259 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
260 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
261 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
263 timeout = jiffies + 1 * HZ;
264 while (time_before(jiffies, timeout)) {
265 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
266 usleep_range(1000, 2000);
267 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
268 GLOBAL_STATUS_PPU_POLLING)
275 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
278 unsigned long timeout;
280 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
281 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
283 timeout = jiffies + 1 * HZ;
284 while (time_before(jiffies, timeout)) {
285 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
286 usleep_range(1000, 2000);
287 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
288 GLOBAL_STATUS_PPU_POLLING)
295 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
297 struct mv88e6xxx_priv_state *ps;
299 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
300 if (mutex_trylock(&ps->ppu_mutex)) {
301 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
303 if (mv88e6xxx_ppu_enable(ds) == 0)
304 ps->ppu_disabled = 0;
305 mutex_unlock(&ps->ppu_mutex);
309 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
311 struct mv88e6xxx_priv_state *ps = (void *)_ps;
313 schedule_work(&ps->ppu_work);
316 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
318 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
321 mutex_lock(&ps->ppu_mutex);
323 /* If the PHY polling unit is enabled, disable it so that
324 * we can access the PHY registers. If it was already
325 * disabled, cancel the timer that is going to re-enable
328 if (!ps->ppu_disabled) {
329 ret = mv88e6xxx_ppu_disable(ds);
331 mutex_unlock(&ps->ppu_mutex);
334 ps->ppu_disabled = 1;
336 del_timer(&ps->ppu_timer);
343 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
345 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
347 /* Schedule a timer to re-enable the PHY polling unit. */
348 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
349 mutex_unlock(&ps->ppu_mutex);
352 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
354 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
356 mutex_init(&ps->ppu_mutex);
357 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
358 init_timer(&ps->ppu_timer);
359 ps->ppu_timer.data = (unsigned long)ps;
360 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
363 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
367 ret = mv88e6xxx_ppu_access_get(ds);
369 ret = mv88e6xxx_reg_read(ds, addr, regnum);
370 mv88e6xxx_ppu_access_put(ds);
376 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
381 ret = mv88e6xxx_ppu_access_get(ds);
383 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
384 mv88e6xxx_ppu_access_put(ds);
391 void mv88e6xxx_poll_link(struct dsa_switch *ds)
395 for (i = 0; i < DSA_MAX_PORTS; i++) {
396 struct net_device *dev;
397 int uninitialized_var(port_status);
408 pcs_ctrl = mv88e6xxx_reg_read(ds, REG_PORT(i), PORT_PCS_CTRL);
409 if (pcs_ctrl < 0 || pcs_ctrl & PORT_PCS_CTRL_FORCE_LINK)
413 if (dev->flags & IFF_UP) {
414 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
419 link = !!(port_status & PORT_STATUS_LINK);
423 if (netif_carrier_ok(dev)) {
424 netdev_info(dev, "link down\n");
425 netif_carrier_off(dev);
430 switch (port_status & PORT_STATUS_SPEED_MASK) {
431 case PORT_STATUS_SPEED_10:
434 case PORT_STATUS_SPEED_100:
437 case PORT_STATUS_SPEED_1000:
444 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
445 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
447 if (!netif_carrier_ok(dev)) {
449 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
451 duplex ? "full" : "half",
453 netif_carrier_on(dev);
458 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
460 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
463 case PORT_SWITCH_ID_6031:
464 case PORT_SWITCH_ID_6061:
465 case PORT_SWITCH_ID_6035:
466 case PORT_SWITCH_ID_6065:
472 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
474 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
477 case PORT_SWITCH_ID_6092:
478 case PORT_SWITCH_ID_6095:
484 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
486 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
489 case PORT_SWITCH_ID_6046:
490 case PORT_SWITCH_ID_6085:
491 case PORT_SWITCH_ID_6096:
492 case PORT_SWITCH_ID_6097:
498 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
500 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
503 case PORT_SWITCH_ID_6123:
504 case PORT_SWITCH_ID_6161:
505 case PORT_SWITCH_ID_6165:
511 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
513 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
516 case PORT_SWITCH_ID_6121:
517 case PORT_SWITCH_ID_6122:
518 case PORT_SWITCH_ID_6152:
519 case PORT_SWITCH_ID_6155:
520 case PORT_SWITCH_ID_6182:
521 case PORT_SWITCH_ID_6185:
522 case PORT_SWITCH_ID_6108:
523 case PORT_SWITCH_ID_6131:
529 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
531 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
534 case PORT_SWITCH_ID_6320:
535 case PORT_SWITCH_ID_6321:
541 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
543 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
546 case PORT_SWITCH_ID_6171:
547 case PORT_SWITCH_ID_6175:
548 case PORT_SWITCH_ID_6350:
549 case PORT_SWITCH_ID_6351:
555 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
557 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
560 case PORT_SWITCH_ID_6172:
561 case PORT_SWITCH_ID_6176:
562 case PORT_SWITCH_ID_6240:
563 case PORT_SWITCH_ID_6352:
569 /* We expect the switch to perform auto negotiation if there is a real
570 * phy. However, in the case of a fixed link phy, we force the port
571 * settings from the fixed link settings.
573 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
574 struct phy_device *phydev)
576 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
579 if (!phy_is_pseudo_fixed_link(phydev))
582 mutex_lock(&ps->smi_mutex);
584 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
588 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
589 PORT_PCS_CTRL_FORCE_LINK |
590 PORT_PCS_CTRL_DUPLEX_FULL |
591 PORT_PCS_CTRL_FORCE_DUPLEX |
592 PORT_PCS_CTRL_UNFORCED);
594 reg |= PORT_PCS_CTRL_FORCE_LINK;
596 reg |= PORT_PCS_CTRL_LINK_UP;
598 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
601 switch (phydev->speed) {
603 reg |= PORT_PCS_CTRL_1000;
606 reg |= PORT_PCS_CTRL_100;
609 reg |= PORT_PCS_CTRL_10;
612 pr_info("Unknown speed");
616 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
617 if (phydev->duplex == DUPLEX_FULL)
618 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
620 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
621 (port >= ps->num_ports - 2)) {
622 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
623 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
624 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
625 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
626 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
627 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
628 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
630 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
633 mutex_unlock(&ps->smi_mutex);
636 /* Must be called with SMI mutex held */
637 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
642 for (i = 0; i < 10; i++) {
643 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
644 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
651 /* Must be called with SMI mutex held */
652 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
656 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
657 port = (port + 1) << 5;
659 /* Snapshot the hardware statistics counters for this port. */
660 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
661 GLOBAL_STATS_OP_CAPTURE_PORT |
662 GLOBAL_STATS_OP_HIST_RX_TX | port);
666 /* Wait for the snapshotting to complete. */
667 ret = _mv88e6xxx_stats_wait(ds);
674 /* Must be called with SMI mutex held */
675 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
682 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
683 GLOBAL_STATS_OP_READ_CAPTURED |
684 GLOBAL_STATS_OP_HIST_RX_TX | stat);
688 ret = _mv88e6xxx_stats_wait(ds);
692 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
698 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
705 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
706 { "in_good_octets", 8, 0x00, },
707 { "in_bad_octets", 4, 0x02, },
708 { "in_unicast", 4, 0x04, },
709 { "in_broadcasts", 4, 0x06, },
710 { "in_multicasts", 4, 0x07, },
711 { "in_pause", 4, 0x16, },
712 { "in_undersize", 4, 0x18, },
713 { "in_fragments", 4, 0x19, },
714 { "in_oversize", 4, 0x1a, },
715 { "in_jabber", 4, 0x1b, },
716 { "in_rx_error", 4, 0x1c, },
717 { "in_fcs_error", 4, 0x1d, },
718 { "out_octets", 8, 0x0e, },
719 { "out_unicast", 4, 0x10, },
720 { "out_broadcasts", 4, 0x13, },
721 { "out_multicasts", 4, 0x12, },
722 { "out_pause", 4, 0x15, },
723 { "excessive", 4, 0x11, },
724 { "collisions", 4, 0x1e, },
725 { "deferred", 4, 0x05, },
726 { "single", 4, 0x14, },
727 { "multiple", 4, 0x17, },
728 { "out_fcs_error", 4, 0x03, },
729 { "late", 4, 0x1f, },
730 { "hist_64bytes", 4, 0x08, },
731 { "hist_65_127bytes", 4, 0x09, },
732 { "hist_128_255bytes", 4, 0x0a, },
733 { "hist_256_511bytes", 4, 0x0b, },
734 { "hist_512_1023bytes", 4, 0x0c, },
735 { "hist_1024_max_bytes", 4, 0x0d, },
736 /* Not all devices have the following counters */
737 { "sw_in_discards", 4, 0x110, },
738 { "sw_in_filtered", 2, 0x112, },
739 { "sw_out_filtered", 2, 0x113, },
743 static bool have_sw_in_discards(struct dsa_switch *ds)
745 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
748 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
749 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
750 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
751 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
752 case PORT_SWITCH_ID_6352:
759 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
761 struct mv88e6xxx_hw_stat *stats,
762 int port, uint8_t *data)
766 for (i = 0; i < nr_stats; i++) {
767 memcpy(data + i * ETH_GSTRING_LEN,
768 stats[i].string, ETH_GSTRING_LEN);
772 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
774 struct mv88e6xxx_hw_stat *stats,
777 struct mv88e6xxx_hw_stat *s = stats + stat;
783 if (s->reg >= 0x100) {
784 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
790 if (s->sizeof_stat == 4) {
791 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
798 _mv88e6xxx_stats_read(ds, s->reg, &low);
799 if (s->sizeof_stat == 8)
800 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
802 value = (((u64)high) << 16) | low;
806 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
808 struct mv88e6xxx_hw_stat *stats,
809 int port, uint64_t *data)
811 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
815 mutex_lock(&ps->smi_mutex);
817 ret = _mv88e6xxx_stats_snapshot(ds, port);
819 mutex_unlock(&ps->smi_mutex);
823 /* Read each of the counters. */
824 for (i = 0; i < nr_stats; i++)
825 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
827 mutex_unlock(&ps->smi_mutex);
830 /* All the statistics in the table */
832 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
834 if (have_sw_in_discards(ds))
835 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
836 mv88e6xxx_hw_stats, port, data);
838 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
839 mv88e6xxx_hw_stats, port, data);
842 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
844 if (have_sw_in_discards(ds))
845 return ARRAY_SIZE(mv88e6xxx_hw_stats);
846 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
850 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
851 int port, uint64_t *data)
853 if (have_sw_in_discards(ds))
854 _mv88e6xxx_get_ethtool_stats(
855 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
856 mv88e6xxx_hw_stats, port, data);
858 _mv88e6xxx_get_ethtool_stats(
859 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
860 mv88e6xxx_hw_stats, port, data);
863 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
865 return 32 * sizeof(u16);
868 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
869 struct ethtool_regs *regs, void *_p)
876 memset(p, 0xff, 32 * sizeof(u16));
878 for (i = 0; i < 32; i++) {
881 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
887 /* Must be called with SMI lock held */
888 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
891 unsigned long timeout = jiffies + HZ / 10;
893 while (time_before(jiffies, timeout)) {
896 ret = _mv88e6xxx_reg_read(ds, reg, offset);
902 usleep_range(1000, 2000);
907 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
909 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
912 mutex_lock(&ps->smi_mutex);
913 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
914 mutex_unlock(&ps->smi_mutex);
919 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
921 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
922 GLOBAL2_SMI_OP_BUSY);
925 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
927 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
928 GLOBAL2_EEPROM_OP_LOAD);
931 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
933 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
934 GLOBAL2_EEPROM_OP_BUSY);
937 /* Must be called with SMI lock held */
938 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
940 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
944 /* Must be called with SMI lock held */
945 static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
947 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
948 GLOBAL2_SCRATCH_BUSY);
951 /* Must be called with SMI mutex held */
952 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
957 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
958 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
963 ret = _mv88e6xxx_phy_wait(ds);
967 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
970 /* Must be called with SMI mutex held */
971 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
976 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
980 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
981 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
984 return _mv88e6xxx_phy_wait(ds);
987 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
989 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
992 mutex_lock(&ps->smi_mutex);
994 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
998 e->eee_enabled = !!(reg & 0x0200);
999 e->tx_lpi_enabled = !!(reg & 0x0100);
1001 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
1005 e->eee_active = !!(reg & PORT_STATUS_EEE);
1009 mutex_unlock(&ps->smi_mutex);
1013 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1014 struct phy_device *phydev, struct ethtool_eee *e)
1016 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1020 mutex_lock(&ps->smi_mutex);
1022 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
1026 reg = ret & ~0x0300;
1029 if (e->tx_lpi_enabled)
1032 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
1034 mutex_unlock(&ps->smi_mutex);
1039 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
1043 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1047 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1051 return _mv88e6xxx_atu_wait(ds);
1054 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
1058 ret = _mv88e6xxx_atu_wait(ds);
1062 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
1065 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1067 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1071 mutex_lock(&ps->smi_mutex);
1073 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1079 oldstate = reg & PORT_CONTROL_STATE_MASK;
1080 if (oldstate != state) {
1081 /* Flush forwarding database if we're moving a port
1082 * from Learning or Forwarding state to Disabled or
1083 * Blocking or Listening state.
1085 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1086 state <= PORT_CONTROL_STATE_BLOCKING) {
1087 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1091 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1092 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1097 mutex_unlock(&ps->smi_mutex);
1101 /* Must be called with smi lock held */
1102 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1104 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1105 u8 fid = ps->fid[port];
1106 u16 reg = fid << 12;
1108 if (dsa_is_cpu_port(ds, port))
1109 reg |= ds->phys_port_mask;
1111 reg |= (ps->bridge_mask[fid] |
1112 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1114 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1117 /* Must be called with smi lock held */
1118 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1120 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1125 mask = ds->phys_port_mask;
1128 mask &= ~(1 << port);
1129 if (ps->fid[port] != fid)
1132 ret = _mv88e6xxx_update_port_config(ds, port);
1137 return _mv88e6xxx_flush_fid(ds, fid);
1140 /* Bridge handling functions */
1142 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1144 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1149 /* If the bridge group is not empty, join that group.
1150 * Otherwise create a new group.
1152 fid = ps->fid[port];
1153 nmask = br_port_mask & ~(1 << port);
1155 fid = ps->fid[__ffs(nmask)];
1157 nmask = ps->bridge_mask[fid] | (1 << port);
1158 if (nmask != br_port_mask) {
1159 netdev_err(ds->ports[port],
1160 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1161 fid, br_port_mask, nmask);
1165 mutex_lock(&ps->smi_mutex);
1167 ps->bridge_mask[fid] = br_port_mask;
1169 if (fid != ps->fid[port]) {
1170 clear_bit(ps->fid[port], ps->fid_bitmap);
1171 ps->fid[port] = fid;
1172 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1175 mutex_unlock(&ps->smi_mutex);
1180 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1182 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1186 fid = ps->fid[port];
1188 if (ps->bridge_mask[fid] != br_port_mask) {
1189 netdev_err(ds->ports[port],
1190 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1191 fid, br_port_mask, ps->bridge_mask[fid]);
1195 /* If the port was the last port of a bridge, we are done.
1196 * Otherwise assign a new fid to the port, and fix up
1197 * the bridge configuration.
1199 if (br_port_mask == (1 << port))
1202 mutex_lock(&ps->smi_mutex);
1204 newfid = find_next_zero_bit(ps->fid_bitmap, VLAN_N_VID, 1);
1205 if (unlikely(newfid > ps->num_ports)) {
1206 netdev_err(ds->ports[port], "all first %d FIDs are used\n",
1212 ps->fid[port] = newfid;
1213 set_bit(newfid, ps->fid_bitmap);
1214 ps->bridge_mask[fid] &= ~(1 << port);
1215 ps->bridge_mask[newfid] = 1 << port;
1217 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1219 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1222 mutex_unlock(&ps->smi_mutex);
1227 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1229 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1233 case BR_STATE_DISABLED:
1234 stp_state = PORT_CONTROL_STATE_DISABLED;
1236 case BR_STATE_BLOCKING:
1237 case BR_STATE_LISTENING:
1238 stp_state = PORT_CONTROL_STATE_BLOCKING;
1240 case BR_STATE_LEARNING:
1241 stp_state = PORT_CONTROL_STATE_LEARNING;
1243 case BR_STATE_FORWARDING:
1245 stp_state = PORT_CONTROL_STATE_FORWARDING;
1249 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1251 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1252 * so we can not update the port state directly but need to schedule it.
1254 ps->port_state[port] = stp_state;
1255 set_bit(port, &ps->port_state_update_mask);
1256 schedule_work(&ps->bridge_work);
1261 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1265 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1269 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1274 int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1276 return mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1277 pvid & PORT_DEFAULT_VLAN_MASK);
1280 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1282 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1283 GLOBAL_VTU_OP_BUSY);
1286 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1290 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1294 return _mv88e6xxx_vtu_wait(ds);
1297 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1301 ret = _mv88e6xxx_vtu_wait(ds);
1305 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1308 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1309 struct mv88e6xxx_vtu_stu_entry *entry,
1310 unsigned int nibble_offset)
1312 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1317 for (i = 0; i < 3; ++i) {
1318 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1319 GLOBAL_VTU_DATA_0_3 + i);
1326 for (i = 0; i < ps->num_ports; ++i) {
1327 unsigned int shift = (i % 4) * 4 + nibble_offset;
1328 u16 reg = regs[i / 4];
1330 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1336 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1337 struct mv88e6xxx_vtu_stu_entry *entry,
1338 unsigned int nibble_offset)
1340 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1341 u16 regs[3] = { 0 };
1345 for (i = 0; i < ps->num_ports; ++i) {
1346 unsigned int shift = (i % 4) * 4 + nibble_offset;
1347 u8 data = entry->data[i];
1349 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1352 for (i = 0; i < 3; ++i) {
1353 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1354 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1362 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, u16 vid,
1363 struct mv88e6xxx_vtu_stu_entry *entry)
1365 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1368 ret = _mv88e6xxx_vtu_wait(ds);
1372 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1373 vid & GLOBAL_VTU_VID_MASK);
1377 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1381 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1385 next.vid = ret & GLOBAL_VTU_VID_MASK;
1386 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1389 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1393 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1394 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1395 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1400 next.fid = ret & GLOBAL_VTU_FID_MASK;
1402 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1407 next.sid = ret & GLOBAL_VTU_SID_MASK;
1415 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1416 struct mv88e6xxx_vtu_stu_entry *entry)
1421 ret = _mv88e6xxx_vtu_wait(ds);
1428 /* Write port member tags */
1429 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1433 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1434 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1435 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1436 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1440 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1441 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1446 reg = GLOBAL_VTU_VID_VALID;
1448 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1449 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1453 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1456 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1457 struct mv88e6xxx_vtu_stu_entry *entry)
1459 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1462 ret = _mv88e6xxx_vtu_wait(ds);
1466 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1467 sid & GLOBAL_VTU_SID_MASK);
1471 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1475 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1479 next.sid = ret & GLOBAL_VTU_SID_MASK;
1481 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1485 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1488 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1497 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1498 struct mv88e6xxx_vtu_stu_entry *entry)
1503 ret = _mv88e6xxx_vtu_wait(ds);
1510 /* Write port states */
1511 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1515 reg = GLOBAL_VTU_VID_VALID;
1517 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1521 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1522 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1526 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1529 static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1530 struct mv88e6xxx_vtu_stu_entry *entry)
1532 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1533 struct mv88e6xxx_vtu_stu_entry vlan = {
1539 /* exclude all ports except the CPU */
1540 for (i = 0; i < ps->num_ports; ++i)
1541 vlan.data[i] = dsa_is_cpu_port(ds, i) ?
1542 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED :
1543 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1545 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1546 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1547 struct mv88e6xxx_vtu_stu_entry vstp;
1550 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1551 * implemented, only one STU entry is needed to cover all VTU
1552 * entries. Thus, validate the SID 0.
1555 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1559 if (vstp.sid != vlan.sid || !vstp.valid) {
1560 memset(&vstp, 0, sizeof(vstp));
1562 vstp.sid = vlan.sid;
1564 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1569 /* Non-bridged ports and bridge groups use FIDs from 1 to
1570 * num_ports; VLANs use FIDs from num_ports+1 to 4095.
1572 vlan.fid = find_next_zero_bit(ps->fid_bitmap, VLAN_N_VID,
1574 if (unlikely(vlan.fid == VLAN_N_VID)) {
1575 pr_err("no more FID available for VLAN %d\n", vid);
1579 err = _mv88e6xxx_flush_fid(ds, vlan.fid);
1583 set_bit(vlan.fid, ps->fid_bitmap);
1590 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1593 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1594 struct mv88e6xxx_vtu_stu_entry vlan;
1597 mutex_lock(&ps->smi_mutex);
1598 err = _mv88e6xxx_vtu_getnext(ds, vid - 1, &vlan);
1602 if (vlan.vid != vid || !vlan.valid) {
1603 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1608 vlan.data[port] = untagged ?
1609 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1610 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1612 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1614 mutex_unlock(&ps->smi_mutex);
1619 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1621 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1622 struct mv88e6xxx_vtu_stu_entry vlan;
1626 mutex_lock(&ps->smi_mutex);
1628 err = _mv88e6xxx_vtu_getnext(ds, vid - 1, &vlan);
1632 if (vlan.vid != vid || !vlan.valid ||
1633 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1638 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1640 /* keep the VLAN unless all ports are excluded */
1641 for (i = 0; i < ps->num_ports; ++i) {
1642 if (dsa_is_cpu_port(ds, i))
1645 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1652 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1657 clear_bit(vlan.fid, ps->fid_bitmap);
1660 mutex_unlock(&ps->smi_mutex);
1665 static int _mv88e6xxx_port_vtu_getnext(struct dsa_switch *ds, int port, u16 vid,
1666 struct mv88e6xxx_vtu_stu_entry *entry)
1674 err = _mv88e6xxx_vtu_getnext(ds, vid, entry);
1682 } while (entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED &&
1683 entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED);
1688 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1689 unsigned long *ports, unsigned long *untagged)
1691 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1692 struct mv88e6xxx_vtu_stu_entry next;
1699 mutex_lock(&ps->smi_mutex);
1700 err = _mv88e6xxx_vtu_getnext(ds, *vid, &next);
1701 mutex_unlock(&ps->smi_mutex);
1711 for (port = 0; port < ps->num_ports; ++port) {
1712 clear_bit(port, ports);
1713 clear_bit(port, untagged);
1715 if (dsa_is_cpu_port(ds, port))
1718 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1719 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1720 set_bit(port, ports);
1722 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1723 set_bit(port, untagged);
1729 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1730 const unsigned char *addr)
1734 for (i = 0; i < 3; i++) {
1735 ret = _mv88e6xxx_reg_write(
1736 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1737 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1745 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1749 for (i = 0; i < 3; i++) {
1750 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1751 GLOBAL_ATU_MAC_01 + i);
1754 addr[i * 2] = ret >> 8;
1755 addr[i * 2 + 1] = ret & 0xff;
1761 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1762 struct mv88e6xxx_atu_entry *entry)
1767 ret = _mv88e6xxx_atu_wait(ds);
1771 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1775 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1776 unsigned int mask, shift;
1779 reg |= GLOBAL_ATU_DATA_TRUNK;
1780 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1781 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1783 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1784 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1787 reg |= (entry->portv_trunkid << shift) & mask;
1790 reg |= entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1792 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, reg);
1796 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
1799 static int _mv88e6xxx_port_vid_to_fid(struct dsa_switch *ds, int port, u16 vid)
1801 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1802 struct mv88e6xxx_vtu_stu_entry vlan;
1806 return ps->fid[port];
1808 err = _mv88e6xxx_port_vtu_getnext(ds, port, vid - 1, &vlan);
1812 if (vlan.vid == vid)
1818 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1819 const unsigned char *addr, u16 vid,
1822 struct mv88e6xxx_atu_entry entry = { 0 };
1825 ret = _mv88e6xxx_port_vid_to_fid(ds, port, vid);
1830 entry.state = state;
1831 ether_addr_copy(entry.mac, addr);
1832 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1833 entry.trunk = false;
1834 entry.portv_trunkid = BIT(port);
1837 return _mv88e6xxx_atu_load(ds, &entry);
1840 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1841 const unsigned char *addr, u16 vid)
1843 int state = is_multicast_ether_addr(addr) ?
1844 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1845 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1846 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1849 mutex_lock(&ps->smi_mutex);
1850 ret = _mv88e6xxx_port_fdb_load(ds, port, addr, vid, state);
1851 mutex_unlock(&ps->smi_mutex);
1856 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1857 const unsigned char *addr, u16 vid)
1859 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1862 mutex_lock(&ps->smi_mutex);
1863 ret = _mv88e6xxx_port_fdb_load(ds, port, addr, vid,
1864 GLOBAL_ATU_DATA_STATE_UNUSED);
1865 mutex_unlock(&ps->smi_mutex);
1870 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1871 const unsigned char *addr,
1872 struct mv88e6xxx_atu_entry *entry)
1874 struct mv88e6xxx_atu_entry next = { 0 };
1879 ret = _mv88e6xxx_atu_wait(ds);
1883 ret = _mv88e6xxx_atu_mac_write(ds, addr);
1887 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1891 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1895 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1899 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1900 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1901 unsigned int mask, shift;
1903 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1905 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1906 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1909 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1910 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1913 next.portv_trunkid = (ret & mask) >> shift;
1920 /* get next entry for port */
1921 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1922 unsigned char *addr, u16 *vid, bool *is_static)
1924 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1925 struct mv88e6xxx_atu_entry next;
1929 mutex_lock(&ps->smi_mutex);
1931 ret = _mv88e6xxx_port_vid_to_fid(ds, port, *vid);
1937 if (is_broadcast_ether_addr(addr)) {
1938 struct mv88e6xxx_vtu_stu_entry vtu;
1940 ret = _mv88e6xxx_port_vtu_getnext(ds, port, *vid, &vtu);
1948 ret = _mv88e6xxx_atu_getnext(ds, fid, addr, &next);
1952 ether_addr_copy(addr, next.mac);
1954 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1956 } while (next.trunk || (next.portv_trunkid & BIT(port)) == 0);
1958 *is_static = next.state == (is_multicast_ether_addr(addr) ?
1959 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1960 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1962 mutex_unlock(&ps->smi_mutex);
1967 static void mv88e6xxx_bridge_work(struct work_struct *work)
1969 struct mv88e6xxx_priv_state *ps;
1970 struct dsa_switch *ds;
1973 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1974 ds = ((struct dsa_switch *)ps) - 1;
1976 while (ps->port_state_update_mask) {
1977 port = __ffs(ps->port_state_update_mask);
1978 clear_bit(port, &ps->port_state_update_mask);
1979 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1983 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1985 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1989 mutex_lock(&ps->smi_mutex);
1991 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1992 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1993 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1994 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1995 /* MAC Forcing register: don't force link, speed,
1996 * duplex or flow control state to any particular
1997 * values on physical ports, but force the CPU port
1998 * and all DSA ports to their maximum bandwidth and
2001 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2002 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2003 reg &= ~PORT_PCS_CTRL_UNFORCED;
2004 reg |= PORT_PCS_CTRL_FORCE_LINK |
2005 PORT_PCS_CTRL_LINK_UP |
2006 PORT_PCS_CTRL_DUPLEX_FULL |
2007 PORT_PCS_CTRL_FORCE_DUPLEX;
2008 if (mv88e6xxx_6065_family(ds))
2009 reg |= PORT_PCS_CTRL_100;
2011 reg |= PORT_PCS_CTRL_1000;
2013 reg |= PORT_PCS_CTRL_UNFORCED;
2016 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2017 PORT_PCS_CTRL, reg);
2022 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2023 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2024 * tunneling, determine priority by looking at 802.1p and IP
2025 * priority fields (IP prio has precedence), and set STP state
2028 * If this is the CPU link, use DSA or EDSA tagging depending
2029 * on which tagging mode was configured.
2031 * If this is a link to another switch, use DSA tagging mode.
2033 * If this is the upstream port for this switch, enable
2034 * forwarding of unknown unicasts and multicasts.
2037 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2038 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2039 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2040 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2041 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2042 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2043 PORT_CONTROL_STATE_FORWARDING;
2044 if (dsa_is_cpu_port(ds, port)) {
2045 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2046 reg |= PORT_CONTROL_DSA_TAG;
2047 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2048 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2049 mv88e6xxx_6320_family(ds)) {
2050 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2051 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2053 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2054 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2055 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2058 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2059 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2060 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2061 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2062 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2063 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2066 if (dsa_is_dsa_port(ds, port)) {
2067 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2068 reg |= PORT_CONTROL_DSA_TAG;
2069 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2070 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2071 mv88e6xxx_6320_family(ds)) {
2072 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2075 if (port == dsa_upstream_port(ds))
2076 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2077 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2080 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2086 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2087 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2088 * untagged frames on this port, do a destination address lookup on all
2089 * received packets as usual, disable ARP mirroring and don't send a
2090 * copy of all transmitted/received frames on this port to the CPU.
2093 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2094 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2095 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2096 reg = PORT_CONTROL_2_MAP_DA;
2098 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2099 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2100 reg |= PORT_CONTROL_2_JUMBO_10240;
2102 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2103 /* Set the upstream port this port should use */
2104 reg |= dsa_upstream_port(ds);
2105 /* enable forwarding of unknown multicast addresses to
2108 if (port == dsa_upstream_port(ds))
2109 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2112 reg |= PORT_CONTROL_2_8021Q_FALLBACK;
2115 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2116 PORT_CONTROL_2, reg);
2121 /* Port Association Vector: when learning source addresses
2122 * of packets, add the address to the address database using
2123 * a port bitmap that has only the bit for this port set and
2124 * the other bits clear.
2126 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
2131 /* Egress rate control 2: disable egress rate control. */
2132 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2137 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2138 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2139 mv88e6xxx_6320_family(ds)) {
2140 /* Do not limit the period of time that this port can
2141 * be paused for by the remote end or the period of
2142 * time that this port can pause the remote end.
2144 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2145 PORT_PAUSE_CTRL, 0x0000);
2149 /* Port ATU control: disable limiting the number of
2150 * address database entries that this port is allowed
2153 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2154 PORT_ATU_CONTROL, 0x0000);
2155 /* Priority Override: disable DA, SA and VTU priority
2158 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2159 PORT_PRI_OVERRIDE, 0x0000);
2163 /* Port Ethertype: use the Ethertype DSA Ethertype
2166 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2167 PORT_ETH_TYPE, ETH_P_EDSA);
2170 /* Tag Remap: use an identity 802.1p prio -> switch
2173 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2174 PORT_TAG_REGMAP_0123, 0x3210);
2178 /* Tag Remap 2: use an identity 802.1p prio -> switch
2181 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2182 PORT_TAG_REGMAP_4567, 0x7654);
2187 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2188 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2189 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2190 mv88e6xxx_6320_family(ds)) {
2191 /* Rate Control: disable ingress rate limiting. */
2192 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2193 PORT_RATE_CONTROL, 0x0001);
2198 /* Port Control 1: disable trunking, disable sending
2199 * learning messages to this port.
2201 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2205 /* Port based VLAN map: give each port its own address
2206 * database, allow the CPU port to talk to each of the 'real'
2207 * ports, and allow each of the 'real' ports to only talk to
2208 * the upstream port.
2211 ps->fid[port] = fid;
2212 set_bit(fid, ps->fid_bitmap);
2214 if (!dsa_is_cpu_port(ds, port))
2215 ps->bridge_mask[fid] = 1 << port;
2217 ret = _mv88e6xxx_update_port_config(ds, port);
2221 /* Default VLAN ID and priority: don't set a default VLAN
2222 * ID, and set the default packet priority to zero.
2224 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2227 mutex_unlock(&ps->smi_mutex);
2231 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2233 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2237 for (i = 0; i < ps->num_ports; i++) {
2238 ret = mv88e6xxx_setup_port(ds, i);
2245 static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
2247 struct dsa_switch *ds = s->private;
2249 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2252 seq_puts(s, " GLOBAL GLOBAL2 ");
2253 for (port = 0 ; port < ps->num_ports; port++)
2254 seq_printf(s, " %2d ", port);
2257 for (reg = 0; reg < 32; reg++) {
2258 seq_printf(s, "%2x: ", reg);
2259 seq_printf(s, " %4x %4x ",
2260 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
2261 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
2263 for (port = 0 ; port < ps->num_ports; port++)
2264 seq_printf(s, "%4x ",
2265 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
2272 static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
2274 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
2277 static const struct file_operations mv88e6xxx_regs_fops = {
2278 .open = mv88e6xxx_regs_open,
2280 .llseek = no_llseek,
2281 .release = single_release,
2282 .owner = THIS_MODULE,
2285 static void mv88e6xxx_atu_show_header(struct seq_file *s)
2287 seq_puts(s, "DB T/P Vec State Addr\n");
2290 static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
2291 unsigned char *addr, int data)
2293 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
2294 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
2295 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
2296 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
2298 seq_printf(s, "%03x %5s %10pb %x %pM\n",
2299 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
2302 static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
2305 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2306 unsigned char addr[6];
2307 int ret, data, state;
2309 ret = _mv88e6xxx_atu_mac_write(ds, bcast);
2314 ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB);
2317 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2321 state = data & GLOBAL_ATU_DATA_STATE_MASK;
2322 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
2324 ret = _mv88e6xxx_atu_mac_read(ds, addr);
2327 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
2328 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
2333 static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
2335 struct dsa_switch *ds = s->private;
2336 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2339 mv88e6xxx_atu_show_header(s);
2341 for (dbnum = 0; dbnum < 255; dbnum++) {
2342 mutex_lock(&ps->smi_mutex);
2343 mv88e6xxx_atu_show_db(s, ds, dbnum);
2344 mutex_unlock(&ps->smi_mutex);
2350 static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
2352 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
2355 static const struct file_operations mv88e6xxx_atu_fops = {
2356 .open = mv88e6xxx_atu_open,
2358 .llseek = no_llseek,
2359 .release = single_release,
2360 .owner = THIS_MODULE,
2363 static void mv88e6xxx_stats_show_header(struct seq_file *s,
2364 struct mv88e6xxx_priv_state *ps)
2368 seq_puts(s, " Statistic ");
2369 for (port = 0 ; port < ps->num_ports; port++)
2370 seq_printf(s, "Port %2d ", port);
2374 static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
2376 struct dsa_switch *ds = s->private;
2377 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2378 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
2379 int port, stat, max_stats;
2382 if (have_sw_in_discards(ds))
2383 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
2385 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
2387 mv88e6xxx_stats_show_header(s, ps);
2389 mutex_lock(&ps->smi_mutex);
2391 for (stat = 0; stat < max_stats; stat++) {
2392 seq_printf(s, "%19s: ", stats[stat].string);
2393 for (port = 0 ; port < ps->num_ports; port++) {
2394 _mv88e6xxx_stats_snapshot(ds, port);
2395 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
2397 seq_printf(s, "%8llu ", value);
2401 mutex_unlock(&ps->smi_mutex);
2406 static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
2408 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
2411 static const struct file_operations mv88e6xxx_stats_fops = {
2412 .open = mv88e6xxx_stats_open,
2414 .llseek = no_llseek,
2415 .release = single_release,
2416 .owner = THIS_MODULE,
2419 static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
2421 struct dsa_switch *ds = s->private;
2422 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2425 seq_puts(s, "Target Port\n");
2427 mutex_lock(&ps->smi_mutex);
2428 for (target = 0; target < 32; target++) {
2429 ret = _mv88e6xxx_reg_write(
2430 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2431 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
2434 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2435 GLOBAL2_DEVICE_MAPPING);
2436 seq_printf(s, " %2d %2d\n", target,
2437 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
2440 mutex_unlock(&ps->smi_mutex);
2445 static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
2447 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
2450 static const struct file_operations mv88e6xxx_device_map_fops = {
2451 .open = mv88e6xxx_device_map_open,
2453 .llseek = no_llseek,
2454 .release = single_release,
2455 .owner = THIS_MODULE,
2458 static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
2460 struct dsa_switch *ds = s->private;
2461 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2464 seq_puts(s, "Register Value\n");
2466 mutex_lock(&ps->smi_mutex);
2467 for (reg = 0; reg < 0x80; reg++) {
2468 ret = _mv88e6xxx_reg_write(
2469 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
2470 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
2474 ret = _mv88e6xxx_scratch_wait(ds);
2478 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2479 GLOBAL2_SCRATCH_MISC);
2480 seq_printf(s, " %2x %2x\n", reg,
2481 ret & GLOBAL2_SCRATCH_VALUE_MASK);
2484 mutex_unlock(&ps->smi_mutex);
2489 static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
2491 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
2494 static const struct file_operations mv88e6xxx_scratch_fops = {
2495 .open = mv88e6xxx_scratch_open,
2497 .llseek = no_llseek,
2498 .release = single_release,
2499 .owner = THIS_MODULE,
2502 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2504 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2507 mutex_init(&ps->smi_mutex);
2509 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2511 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2513 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
2514 ps->dbgfs = debugfs_create_dir(name, NULL);
2517 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
2518 &mv88e6xxx_regs_fops);
2520 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
2521 &mv88e6xxx_atu_fops);
2523 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
2524 &mv88e6xxx_stats_fops);
2526 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
2527 &mv88e6xxx_device_map_fops);
2529 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
2530 &mv88e6xxx_scratch_fops);
2534 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2536 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2540 /* Set the default address aging time to 5 minutes, and
2541 * enable address learn messages to be sent to all message
2544 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2545 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2547 /* Configure the IP ToS mapping registers. */
2548 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2549 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2550 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2551 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2552 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2553 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2554 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2555 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2557 /* Configure the IEEE 802.1p priority mapping register. */
2558 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2560 /* Send all frames with destination addresses matching
2561 * 01:80:c2:00:00:0x to the CPU port.
2563 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2565 /* Ignore removed tag data on doubly tagged packets, disable
2566 * flow control messages, force flow control priority to the
2567 * highest, and send all special multicast frames to the CPU
2568 * port at the highest priority.
2570 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2571 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2572 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2574 /* Program the DSA routing table. */
2575 for (i = 0; i < 32; i++) {
2578 if (ds->pd->rtable &&
2579 i != ds->index && i < ds->dst->pd->nr_chips)
2580 nexthop = ds->pd->rtable[i] & 0x1f;
2582 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2583 GLOBAL2_DEVICE_MAPPING_UPDATE |
2584 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2588 /* Clear all trunk masks. */
2589 for (i = 0; i < 8; i++)
2590 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2591 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2592 ((1 << ps->num_ports) - 1));
2594 /* Clear all trunk mappings. */
2595 for (i = 0; i < 16; i++)
2596 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2597 GLOBAL2_TRUNK_MAPPING_UPDATE |
2598 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2600 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2601 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2602 mv88e6xxx_6320_family(ds)) {
2603 /* Send all frames with destination addresses matching
2604 * 01:80:c2:00:00:2x to the CPU port.
2606 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2608 /* Initialise cross-chip port VLAN table to reset
2611 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2613 /* Clear the priority override table. */
2614 for (i = 0; i < 16; i++)
2615 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2619 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2620 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2621 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2622 mv88e6xxx_6320_family(ds)) {
2623 /* Disable ingress rate limiting by resetting all
2624 * ingress rate limit registers to their initial
2627 for (i = 0; i < ps->num_ports; i++)
2628 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2632 /* Clear the statistics counters for all ports */
2633 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2635 /* Wait for the flush to complete. */
2636 mutex_lock(&ps->smi_mutex);
2637 ret = _mv88e6xxx_stats_wait(ds);
2641 /* Clear all the VTU and STU entries */
2642 ret = _mv88e6xxx_vtu_stu_flush(ds);
2644 mutex_unlock(&ps->smi_mutex);
2649 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2651 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2652 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2653 unsigned long timeout;
2657 /* Set all ports to the disabled state. */
2658 for (i = 0; i < ps->num_ports; i++) {
2659 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2660 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2663 /* Wait for transmit queues to drain. */
2664 usleep_range(2000, 4000);
2666 /* Reset the switch. Keep the PPU active if requested. The PPU
2667 * needs to be active to support indirect phy register access
2668 * through global registers 0x18 and 0x19.
2671 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2673 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2675 /* Wait up to one second for reset to complete. */
2676 timeout = jiffies + 1 * HZ;
2677 while (time_before(jiffies, timeout)) {
2678 ret = REG_READ(REG_GLOBAL, 0x00);
2679 if ((ret & is_reset) == is_reset)
2681 usleep_range(1000, 2000);
2683 if (time_after(jiffies, timeout))
2689 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2691 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2694 mutex_lock(&ps->smi_mutex);
2695 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2698 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2700 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2701 mutex_unlock(&ps->smi_mutex);
2705 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2708 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2711 mutex_lock(&ps->smi_mutex);
2712 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2716 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2718 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2719 mutex_unlock(&ps->smi_mutex);
2723 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2725 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2727 if (port >= 0 && port < ps->num_ports)
2733 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2736 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2742 mutex_lock(&ps->smi_mutex);
2743 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2744 mutex_unlock(&ps->smi_mutex);
2749 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2751 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2752 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2758 mutex_lock(&ps->smi_mutex);
2759 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2760 mutex_unlock(&ps->smi_mutex);
2765 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2767 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2768 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2774 mutex_lock(&ps->smi_mutex);
2775 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2776 mutex_unlock(&ps->smi_mutex);
2781 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2784 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2785 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2791 mutex_lock(&ps->smi_mutex);
2792 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2793 mutex_unlock(&ps->smi_mutex);
2797 #ifdef CONFIG_NET_DSA_HWMON
2799 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2801 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2807 mutex_lock(&ps->smi_mutex);
2809 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2813 /* Enable temperature sensor */
2814 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2818 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2822 /* Wait for temperature to stabilize */
2823 usleep_range(10000, 12000);
2825 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2831 /* Disable temperature sensor */
2832 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2836 *temp = ((val & 0x1f) - 5) * 5;
2839 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2840 mutex_unlock(&ps->smi_mutex);
2844 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2846 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2851 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2855 *temp = (ret & 0xff) - 25;
2860 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2862 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2863 return mv88e63xx_get_temp(ds, temp);
2865 return mv88e61xx_get_temp(ds, temp);
2868 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2870 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2873 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2878 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2882 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2887 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2889 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2892 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2895 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2898 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2899 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2900 (ret & 0xe0ff) | (temp << 8));
2903 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2905 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2908 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2913 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2917 *alarm = !!(ret & 0x40);
2921 #endif /* CONFIG_NET_DSA_HWMON */
2923 static int __init mv88e6xxx_init(void)
2925 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2926 register_switch_driver(&mv88e6131_switch_driver);
2928 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2929 register_switch_driver(&mv88e6123_61_65_switch_driver);
2931 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2932 register_switch_driver(&mv88e6352_switch_driver);
2934 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2935 register_switch_driver(&mv88e6171_switch_driver);
2939 module_init(mv88e6xxx_init);
2941 static void __exit mv88e6xxx_cleanup(void)
2943 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2944 unregister_switch_driver(&mv88e6171_switch_driver);
2946 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2947 unregister_switch_driver(&mv88e6352_switch_driver);
2949 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2950 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2952 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2953 unregister_switch_driver(&mv88e6131_switch_driver);
2956 module_exit(mv88e6xxx_cleanup);
2958 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2959 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2960 MODULE_LICENSE("GPL");