2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/delay.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_bridge.h>
20 #include <linux/jiffies.h>
21 #include <linux/list.h>
22 #include <linux/mdio.h>
23 #include <linux/module.h>
24 #include <linux/of_mdio.h>
25 #include <linux/netdevice.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/phy.h>
29 #include <net/switchdev.h>
30 #include "mv88e6xxx.h"
32 static void assert_smi_lock(struct mv88e6xxx_priv_state *ps)
34 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
35 dev_err(ps->dev, "SMI lock not held!\n");
40 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
41 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
42 * will be directly accessible on some {device address,register address}
43 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
44 * will only respond to SMI transactions to that specific address, and
45 * an indirect addressing mechanism needs to be used to access its
48 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
53 for (i = 0; i < 16; i++) {
54 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
58 if ((ret & SMI_CMD_BUSY) == 0)
65 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
71 return mdiobus_read_nested(bus, addr, reg);
73 /* Wait for the bus to become free. */
74 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
78 /* Transmit the read command. */
79 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
80 SMI_CMD_OP_22_READ | (addr << 5) | reg);
84 /* Wait for the read command to complete. */
85 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
90 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
97 static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
104 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
108 dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
114 static int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr,
119 mutex_lock(&ps->smi_mutex);
120 ret = _mv88e6xxx_reg_read(ps, addr, reg);
121 mutex_unlock(&ps->smi_mutex);
126 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
132 return mdiobus_write_nested(bus, addr, reg, val);
134 /* Wait for the bus to become free. */
135 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
139 /* Transmit the data to write. */
140 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
144 /* Transmit the write command. */
145 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
146 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
150 /* Wait for the write command to complete. */
151 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
158 static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
163 dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
166 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
169 static int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
174 mutex_lock(&ps->smi_mutex);
175 ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
176 mutex_unlock(&ps->smi_mutex);
181 static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
183 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
186 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
187 (addr[0] << 8) | addr[1]);
191 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
192 (addr[2] << 8) | addr[3]);
196 return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
197 (addr[4] << 8) | addr[5]);
200 static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
202 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
206 for (i = 0; i < 6; i++) {
209 /* Write the MAC address byte. */
210 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
211 GLOBAL2_SWITCH_MAC_BUSY |
216 /* Wait for the write to complete. */
217 for (j = 0; j < 16; j++) {
218 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
223 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
233 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
235 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
237 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
238 return mv88e6xxx_set_addr_indirect(ds, addr);
240 return mv88e6xxx_set_addr_direct(ds, addr);
243 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_priv_state *ps,
244 int addr, int regnum)
247 return _mv88e6xxx_reg_read(ps, addr, regnum);
251 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_priv_state *ps,
252 int addr, int regnum, u16 val)
255 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
259 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
262 unsigned long timeout;
264 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
268 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
269 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
273 timeout = jiffies + 1 * HZ;
274 while (time_before(jiffies, timeout)) {
275 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
279 usleep_range(1000, 2000);
280 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
281 GLOBAL_STATUS_PPU_POLLING)
288 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
291 unsigned long timeout;
293 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
297 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
298 ret | GLOBAL_CONTROL_PPU_ENABLE);
302 timeout = jiffies + 1 * HZ;
303 while (time_before(jiffies, timeout)) {
304 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
308 usleep_range(1000, 2000);
309 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
310 GLOBAL_STATUS_PPU_POLLING)
317 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
319 struct mv88e6xxx_priv_state *ps;
321 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
323 mutex_lock(&ps->smi_mutex);
325 if (mutex_trylock(&ps->ppu_mutex)) {
326 if (mv88e6xxx_ppu_enable(ps) == 0)
327 ps->ppu_disabled = 0;
328 mutex_unlock(&ps->ppu_mutex);
331 mutex_unlock(&ps->smi_mutex);
334 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
336 struct mv88e6xxx_priv_state *ps = (void *)_ps;
338 schedule_work(&ps->ppu_work);
341 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
345 mutex_lock(&ps->ppu_mutex);
347 /* If the PHY polling unit is enabled, disable it so that
348 * we can access the PHY registers. If it was already
349 * disabled, cancel the timer that is going to re-enable
352 if (!ps->ppu_disabled) {
353 ret = mv88e6xxx_ppu_disable(ps);
355 mutex_unlock(&ps->ppu_mutex);
358 ps->ppu_disabled = 1;
360 del_timer(&ps->ppu_timer);
367 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
369 /* Schedule a timer to re-enable the PHY polling unit. */
370 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
371 mutex_unlock(&ps->ppu_mutex);
374 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
376 mutex_init(&ps->ppu_mutex);
377 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
378 init_timer(&ps->ppu_timer);
379 ps->ppu_timer.data = (unsigned long)ps;
380 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
383 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
388 ret = mv88e6xxx_ppu_access_get(ps);
390 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
391 mv88e6xxx_ppu_access_put(ps);
397 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
402 ret = mv88e6xxx_ppu_access_get(ps);
404 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
405 mv88e6xxx_ppu_access_put(ps);
411 static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
413 return ps->info->family == MV88E6XXX_FAMILY_6065;
416 static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
418 return ps->info->family == MV88E6XXX_FAMILY_6095;
421 static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
423 return ps->info->family == MV88E6XXX_FAMILY_6097;
426 static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
428 return ps->info->family == MV88E6XXX_FAMILY_6165;
431 static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
433 return ps->info->family == MV88E6XXX_FAMILY_6185;
436 static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
438 return ps->info->family == MV88E6XXX_FAMILY_6320;
441 static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
443 return ps->info->family == MV88E6XXX_FAMILY_6351;
446 static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
448 return ps->info->family == MV88E6XXX_FAMILY_6352;
451 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
453 return ps->info->num_databases;
456 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
458 /* Does the device have dedicated FID registers for ATU and VTU ops? */
459 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
460 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
466 /* We expect the switch to perform auto negotiation if there is a real
467 * phy. However, in the case of a fixed link phy, we force the port
468 * settings from the fixed link settings.
470 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
471 struct phy_device *phydev)
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
477 if (!phy_is_pseudo_fixed_link(phydev))
480 mutex_lock(&ps->smi_mutex);
482 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
486 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
487 PORT_PCS_CTRL_FORCE_LINK |
488 PORT_PCS_CTRL_DUPLEX_FULL |
489 PORT_PCS_CTRL_FORCE_DUPLEX |
490 PORT_PCS_CTRL_UNFORCED);
492 reg |= PORT_PCS_CTRL_FORCE_LINK;
494 reg |= PORT_PCS_CTRL_LINK_UP;
496 if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
499 switch (phydev->speed) {
501 reg |= PORT_PCS_CTRL_1000;
504 reg |= PORT_PCS_CTRL_100;
507 reg |= PORT_PCS_CTRL_10;
510 pr_info("Unknown speed");
514 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
515 if (phydev->duplex == DUPLEX_FULL)
516 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
518 if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
519 (port >= ps->info->num_ports - 2)) {
520 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
521 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
522 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
523 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
524 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
525 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
526 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
528 _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
531 mutex_unlock(&ps->smi_mutex);
534 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
539 for (i = 0; i < 10; i++) {
540 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
541 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
548 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
553 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
554 port = (port + 1) << 5;
556 /* Snapshot the hardware statistics counters for this port. */
557 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
558 GLOBAL_STATS_OP_CAPTURE_PORT |
559 GLOBAL_STATS_OP_HIST_RX_TX | port);
563 /* Wait for the snapshotting to complete. */
564 ret = _mv88e6xxx_stats_wait(ps);
571 static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
579 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
580 GLOBAL_STATS_OP_READ_CAPTURED |
581 GLOBAL_STATS_OP_HIST_RX_TX | stat);
585 ret = _mv88e6xxx_stats_wait(ps);
589 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
595 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
602 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
603 { "in_good_octets", 8, 0x00, BANK0, },
604 { "in_bad_octets", 4, 0x02, BANK0, },
605 { "in_unicast", 4, 0x04, BANK0, },
606 { "in_broadcasts", 4, 0x06, BANK0, },
607 { "in_multicasts", 4, 0x07, BANK0, },
608 { "in_pause", 4, 0x16, BANK0, },
609 { "in_undersize", 4, 0x18, BANK0, },
610 { "in_fragments", 4, 0x19, BANK0, },
611 { "in_oversize", 4, 0x1a, BANK0, },
612 { "in_jabber", 4, 0x1b, BANK0, },
613 { "in_rx_error", 4, 0x1c, BANK0, },
614 { "in_fcs_error", 4, 0x1d, BANK0, },
615 { "out_octets", 8, 0x0e, BANK0, },
616 { "out_unicast", 4, 0x10, BANK0, },
617 { "out_broadcasts", 4, 0x13, BANK0, },
618 { "out_multicasts", 4, 0x12, BANK0, },
619 { "out_pause", 4, 0x15, BANK0, },
620 { "excessive", 4, 0x11, BANK0, },
621 { "collisions", 4, 0x1e, BANK0, },
622 { "deferred", 4, 0x05, BANK0, },
623 { "single", 4, 0x14, BANK0, },
624 { "multiple", 4, 0x17, BANK0, },
625 { "out_fcs_error", 4, 0x03, BANK0, },
626 { "late", 4, 0x1f, BANK0, },
627 { "hist_64bytes", 4, 0x08, BANK0, },
628 { "hist_65_127bytes", 4, 0x09, BANK0, },
629 { "hist_128_255bytes", 4, 0x0a, BANK0, },
630 { "hist_256_511bytes", 4, 0x0b, BANK0, },
631 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
632 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
633 { "sw_in_discards", 4, 0x10, PORT, },
634 { "sw_in_filtered", 2, 0x12, PORT, },
635 { "sw_out_filtered", 2, 0x13, PORT, },
636 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
637 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
638 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
639 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
640 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
641 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
642 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
643 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
644 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
645 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
646 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
647 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
648 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
649 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
650 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
651 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
652 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
653 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
665 struct mv88e6xxx_hw_stat *stat)
667 switch (stat->type) {
671 return mv88e6xxx_6320_family(ps);
673 return mv88e6xxx_6095_family(ps) ||
674 mv88e6xxx_6185_family(ps) ||
675 mv88e6xxx_6097_family(ps) ||
676 mv88e6xxx_6165_family(ps) ||
677 mv88e6xxx_6351_family(ps) ||
678 mv88e6xxx_6352_family(ps);
683 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
684 struct mv88e6xxx_hw_stat *s,
694 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
699 if (s->sizeof_stat == 4) {
700 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
709 _mv88e6xxx_stats_read(ps, s->reg, &low);
710 if (s->sizeof_stat == 8)
711 _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
713 value = (((u64)high) << 16) | low;
717 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
720 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
721 struct mv88e6xxx_hw_stat *stat;
724 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
725 stat = &mv88e6xxx_hw_stats[i];
726 if (mv88e6xxx_has_stat(ps, stat)) {
727 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
734 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
736 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
737 struct mv88e6xxx_hw_stat *stat;
740 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
741 stat = &mv88e6xxx_hw_stats[i];
742 if (mv88e6xxx_has_stat(ps, stat))
748 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
751 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
752 struct mv88e6xxx_hw_stat *stat;
756 mutex_lock(&ps->smi_mutex);
758 ret = _mv88e6xxx_stats_snapshot(ps, port);
760 mutex_unlock(&ps->smi_mutex);
763 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
764 stat = &mv88e6xxx_hw_stats[i];
765 if (mv88e6xxx_has_stat(ps, stat)) {
766 data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
771 mutex_unlock(&ps->smi_mutex);
774 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
776 return 32 * sizeof(u16);
779 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
780 struct ethtool_regs *regs, void *_p)
782 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
788 memset(p, 0xff, 32 * sizeof(u16));
790 mutex_lock(&ps->smi_mutex);
792 for (i = 0; i < 32; i++) {
795 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
800 mutex_unlock(&ps->smi_mutex);
803 static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
806 unsigned long timeout = jiffies + HZ / 10;
808 while (time_before(jiffies, timeout)) {
811 ret = _mv88e6xxx_reg_read(ps, reg, offset);
817 usleep_range(1000, 2000);
822 static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
823 int offset, u16 mask)
827 mutex_lock(&ps->smi_mutex);
828 ret = _mv88e6xxx_wait(ps, reg, offset, mask);
829 mutex_unlock(&ps->smi_mutex);
834 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_priv_state *ps)
836 return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
837 GLOBAL2_SMI_OP_BUSY);
840 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
842 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
844 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
845 GLOBAL2_EEPROM_OP_LOAD);
848 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
850 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
852 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_BUSY);
856 static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
858 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
861 mutex_lock(&ps->eeprom_mutex);
863 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
864 GLOBAL2_EEPROM_OP_READ |
865 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
869 ret = mv88e6xxx_eeprom_busy_wait(ds);
873 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
875 mutex_unlock(&ps->eeprom_mutex);
879 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
881 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
883 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
884 return ps->eeprom_len;
889 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
890 struct ethtool_eeprom *eeprom, u8 *data)
892 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
897 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
900 offset = eeprom->offset;
904 eeprom->magic = 0xc3ec4951;
906 ret = mv88e6xxx_eeprom_load_wait(ds);
913 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
917 *data++ = (word >> 8) & 0xff;
927 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
931 *data++ = word & 0xff;
932 *data++ = (word >> 8) & 0xff;
942 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
946 *data++ = word & 0xff;
956 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
958 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
961 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
965 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
971 static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
974 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
977 mutex_lock(&ps->eeprom_mutex);
979 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
983 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
984 GLOBAL2_EEPROM_OP_WRITE |
985 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
989 ret = mv88e6xxx_eeprom_busy_wait(ds);
991 mutex_unlock(&ps->eeprom_mutex);
995 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
996 struct ethtool_eeprom *eeprom, u8 *data)
998 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1003 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
1006 if (eeprom->magic != 0xc3ec4951)
1009 ret = mv88e6xxx_eeprom_is_readonly(ds);
1013 offset = eeprom->offset;
1017 ret = mv88e6xxx_eeprom_load_wait(ds);
1024 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1028 word = (*data++ << 8) | (word & 0xff);
1030 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1043 word |= *data++ << 8;
1045 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1057 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1061 word = (word & 0xff00) | *data++;
1063 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1075 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
1077 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
1078 GLOBAL_ATU_OP_BUSY);
1081 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_priv_state *ps,
1082 int addr, int regnum)
1086 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
1087 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1092 ret = mv88e6xxx_mdio_wait(ps);
1096 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1101 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_priv_state *ps,
1102 int addr, int regnum, u16 val)
1106 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
1110 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
1111 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1114 return mv88e6xxx_mdio_wait(ps);
1117 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1118 struct ethtool_eee *e)
1120 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1123 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1126 mutex_lock(&ps->smi_mutex);
1128 reg = mv88e6xxx_mdio_read_indirect(ps, port, 16);
1132 e->eee_enabled = !!(reg & 0x0200);
1133 e->tx_lpi_enabled = !!(reg & 0x0100);
1135 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
1139 e->eee_active = !!(reg & PORT_STATUS_EEE);
1143 mutex_unlock(&ps->smi_mutex);
1147 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1148 struct phy_device *phydev, struct ethtool_eee *e)
1150 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1154 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1157 mutex_lock(&ps->smi_mutex);
1159 ret = mv88e6xxx_mdio_read_indirect(ps, port, 16);
1163 reg = ret & ~0x0300;
1166 if (e->tx_lpi_enabled)
1169 ret = mv88e6xxx_mdio_write_indirect(ps, port, 16, reg);
1171 mutex_unlock(&ps->smi_mutex);
1176 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
1180 if (mv88e6xxx_has_fid_reg(ps)) {
1181 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1184 } else if (mv88e6xxx_num_databases(ps) == 256) {
1185 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1186 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1190 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1192 ((fid << 8) & 0xf000));
1196 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1200 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1204 return _mv88e6xxx_atu_wait(ps);
1207 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
1208 struct mv88e6xxx_atu_entry *entry)
1210 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1212 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1213 unsigned int mask, shift;
1216 data |= GLOBAL_ATU_DATA_TRUNK;
1217 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1218 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1220 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1221 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1224 data |= (entry->portv_trunkid << shift) & mask;
1227 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1230 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
1231 struct mv88e6xxx_atu_entry *entry,
1237 err = _mv88e6xxx_atu_wait(ps);
1241 err = _mv88e6xxx_atu_data_write(ps, entry);
1246 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1247 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1249 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1250 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1253 return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
1256 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1257 u16 fid, bool static_too)
1259 struct mv88e6xxx_atu_entry entry = {
1261 .state = 0, /* EntryState bits must be 0 */
1264 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
1267 static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1268 int from_port, int to_port, bool static_too)
1270 struct mv88e6xxx_atu_entry entry = {
1275 /* EntryState bits must be 0xF */
1276 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1278 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1279 entry.portv_trunkid = (to_port & 0x0f) << 4;
1280 entry.portv_trunkid |= from_port & 0x0f;
1282 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
1285 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1286 int port, bool static_too)
1288 /* Destination port 0xF means remove the entries */
1289 return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
1292 static const char * const mv88e6xxx_port_state_names[] = {
1293 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1294 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1295 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1296 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1299 static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1302 struct dsa_switch *ds = ps->ds;
1306 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
1310 oldstate = reg & PORT_CONTROL_STATE_MASK;
1312 if (oldstate != state) {
1313 /* Flush forwarding database if we're moving a port
1314 * from Learning or Forwarding state to Disabled or
1315 * Blocking or Listening state.
1317 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1318 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1319 (state == PORT_CONTROL_STATE_DISABLED ||
1320 state == PORT_CONTROL_STATE_BLOCKING)) {
1321 ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
1326 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1327 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
1332 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1333 mv88e6xxx_port_state_names[state],
1334 mv88e6xxx_port_state_names[oldstate]);
1340 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1343 struct net_device *bridge = ps->ports[port].bridge_dev;
1344 const u16 mask = (1 << ps->info->num_ports) - 1;
1345 struct dsa_switch *ds = ps->ds;
1346 u16 output_ports = 0;
1350 /* allow CPU port or DSA link(s) to send frames to every port */
1351 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1352 output_ports = mask;
1354 for (i = 0; i < ps->info->num_ports; ++i) {
1355 /* allow sending frames to every group member */
1356 if (bridge && ps->ports[i].bridge_dev == bridge)
1357 output_ports |= BIT(i);
1359 /* allow sending frames to CPU port and DSA link(s) */
1360 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1361 output_ports |= BIT(i);
1365 /* prevent frames from going back out of the port they came in on */
1366 output_ports &= ~BIT(port);
1368 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
1373 reg |= output_ports & mask;
1375 return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
1378 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1381 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1385 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE))
1389 case BR_STATE_DISABLED:
1390 stp_state = PORT_CONTROL_STATE_DISABLED;
1392 case BR_STATE_BLOCKING:
1393 case BR_STATE_LISTENING:
1394 stp_state = PORT_CONTROL_STATE_BLOCKING;
1396 case BR_STATE_LEARNING:
1397 stp_state = PORT_CONTROL_STATE_LEARNING;
1399 case BR_STATE_FORWARDING:
1401 stp_state = PORT_CONTROL_STATE_FORWARDING;
1405 mutex_lock(&ps->smi_mutex);
1406 err = _mv88e6xxx_port_state(ps, port, stp_state);
1407 mutex_unlock(&ps->smi_mutex);
1410 netdev_err(ds->ports[port].netdev,
1411 "failed to update state to %s\n",
1412 mv88e6xxx_port_state_names[stp_state]);
1415 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1418 struct dsa_switch *ds = ps->ds;
1422 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
1426 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1429 ret &= ~PORT_DEFAULT_VLAN_MASK;
1430 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1432 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
1433 PORT_DEFAULT_VLAN, ret);
1437 netdev_dbg(ds->ports[port].netdev,
1438 "DefaultVID %d (was %d)\n", *new, pvid);
1447 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1448 int port, u16 *pvid)
1450 return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
1453 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1456 return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
1459 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
1461 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
1462 GLOBAL_VTU_OP_BUSY);
1465 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
1469 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
1473 return _mv88e6xxx_vtu_wait(ps);
1476 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
1480 ret = _mv88e6xxx_vtu_wait(ps);
1484 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
1487 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
1488 struct mv88e6xxx_vtu_stu_entry *entry,
1489 unsigned int nibble_offset)
1495 for (i = 0; i < 3; ++i) {
1496 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1497 GLOBAL_VTU_DATA_0_3 + i);
1504 for (i = 0; i < ps->info->num_ports; ++i) {
1505 unsigned int shift = (i % 4) * 4 + nibble_offset;
1506 u16 reg = regs[i / 4];
1508 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1514 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state *ps,
1515 struct mv88e6xxx_vtu_stu_entry *entry)
1517 return _mv88e6xxx_vtu_stu_data_read(ps, entry, 0);
1520 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state *ps,
1521 struct mv88e6xxx_vtu_stu_entry *entry)
1523 return _mv88e6xxx_vtu_stu_data_read(ps, entry, 2);
1526 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
1527 struct mv88e6xxx_vtu_stu_entry *entry,
1528 unsigned int nibble_offset)
1530 u16 regs[3] = { 0 };
1534 for (i = 0; i < ps->info->num_ports; ++i) {
1535 unsigned int shift = (i % 4) * 4 + nibble_offset;
1536 u8 data = entry->data[i];
1538 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1541 for (i = 0; i < 3; ++i) {
1542 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
1543 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1551 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state *ps,
1552 struct mv88e6xxx_vtu_stu_entry *entry)
1554 return _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
1557 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state *ps,
1558 struct mv88e6xxx_vtu_stu_entry *entry)
1560 return _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
1563 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
1565 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
1566 vid & GLOBAL_VTU_VID_MASK);
1569 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
1570 struct mv88e6xxx_vtu_stu_entry *entry)
1572 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1575 ret = _mv88e6xxx_vtu_wait(ps);
1579 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
1583 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
1587 next.vid = ret & GLOBAL_VTU_VID_MASK;
1588 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1591 ret = mv88e6xxx_vtu_data_read(ps, &next);
1595 if (mv88e6xxx_has_fid_reg(ps)) {
1596 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1601 next.fid = ret & GLOBAL_VTU_FID_MASK;
1602 } else if (mv88e6xxx_num_databases(ps) == 256) {
1603 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1604 * VTU DBNum[3:0] are located in VTU Operation 3:0
1606 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1611 next.fid = (ret & 0xf00) >> 4;
1612 next.fid |= ret & 0xf;
1615 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) {
1616 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1621 next.sid = ret & GLOBAL_VTU_SID_MASK;
1629 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1630 struct switchdev_obj_port_vlan *vlan,
1631 int (*cb)(struct switchdev_obj *obj))
1633 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1634 struct mv88e6xxx_vtu_stu_entry next;
1638 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
1641 mutex_lock(&ps->smi_mutex);
1643 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
1647 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
1652 err = _mv88e6xxx_vtu_getnext(ps, &next);
1659 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1662 /* reinit and dump this VLAN obj */
1663 vlan->vid_begin = next.vid;
1664 vlan->vid_end = next.vid;
1667 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1668 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1670 if (next.vid == pvid)
1671 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1673 err = cb(&vlan->obj);
1676 } while (next.vid < GLOBAL_VTU_VID_MASK);
1679 mutex_unlock(&ps->smi_mutex);
1684 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
1685 struct mv88e6xxx_vtu_stu_entry *entry)
1687 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1691 ret = _mv88e6xxx_vtu_wait(ps);
1698 /* Write port member tags */
1699 ret = mv88e6xxx_vtu_data_write(ps, entry);
1703 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) {
1704 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1705 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1710 if (mv88e6xxx_has_fid_reg(ps)) {
1711 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1712 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1715 } else if (mv88e6xxx_num_databases(ps) == 256) {
1716 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1717 * VTU DBNum[3:0] are located in VTU Operation 3:0
1719 op |= (entry->fid & 0xf0) << 8;
1720 op |= entry->fid & 0xf;
1723 reg = GLOBAL_VTU_VID_VALID;
1725 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1726 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1730 return _mv88e6xxx_vtu_cmd(ps, op);
1733 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
1734 struct mv88e6xxx_vtu_stu_entry *entry)
1736 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1739 ret = _mv88e6xxx_vtu_wait(ps);
1743 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
1744 sid & GLOBAL_VTU_SID_MASK);
1748 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
1752 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
1756 next.sid = ret & GLOBAL_VTU_SID_MASK;
1758 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
1762 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1765 ret = mv88e6xxx_stu_data_read(ps, &next);
1774 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
1775 struct mv88e6xxx_vtu_stu_entry *entry)
1780 ret = _mv88e6xxx_vtu_wait(ps);
1787 /* Write port states */
1788 ret = mv88e6xxx_stu_data_write(ps, entry);
1792 reg = GLOBAL_VTU_VID_VALID;
1794 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1798 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1799 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1803 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1806 static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1809 struct dsa_switch *ds = ps->ds;
1814 if (mv88e6xxx_num_databases(ps) == 4096)
1816 else if (mv88e6xxx_num_databases(ps) == 256)
1821 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1822 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
1826 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1829 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1830 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1832 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
1838 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1839 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
1843 fid |= (ret & upper_mask) << 4;
1847 ret |= (*new >> 4) & upper_mask;
1849 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
1854 netdev_dbg(ds->ports[port].netdev,
1855 "FID %d (was %d)\n", *new, fid);
1864 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1867 return _mv88e6xxx_port_fid(ps, port, NULL, fid);
1870 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1873 return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
1876 static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
1878 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1879 struct mv88e6xxx_vtu_stu_entry vlan;
1882 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1884 /* Set every FID bit used by the (un)bridged ports */
1885 for (i = 0; i < ps->info->num_ports; ++i) {
1886 err = _mv88e6xxx_port_fid_get(ps, i, fid);
1890 set_bit(*fid, fid_bitmap);
1893 /* Set every FID bit used by the VLAN entries */
1894 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
1899 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
1906 set_bit(vlan.fid, fid_bitmap);
1907 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1909 /* The reset value 0x000 is used to indicate that multiple address
1910 * databases are not needed. Return the next positive available.
1912 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1913 if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
1916 /* Clear the database */
1917 return _mv88e6xxx_atu_flush(ps, *fid, true);
1920 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
1921 struct mv88e6xxx_vtu_stu_entry *entry)
1923 struct dsa_switch *ds = ps->ds;
1924 struct mv88e6xxx_vtu_stu_entry vlan = {
1930 err = _mv88e6xxx_fid_new(ps, &vlan.fid);
1934 /* exclude all ports except the CPU and DSA ports */
1935 for (i = 0; i < ps->info->num_ports; ++i)
1936 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1937 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1938 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1940 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1941 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
1942 struct mv88e6xxx_vtu_stu_entry vstp;
1944 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1945 * implemented, only one STU entry is needed to cover all VTU
1946 * entries. Thus, validate the SID 0.
1949 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
1953 if (vstp.sid != vlan.sid || !vstp.valid) {
1954 memset(&vstp, 0, sizeof(vstp));
1956 vstp.sid = vlan.sid;
1958 err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
1968 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
1969 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1976 err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
1980 err = _mv88e6xxx_vtu_getnext(ps, entry);
1984 if (entry->vid != vid || !entry->valid) {
1987 /* -ENOENT would've been more appropriate, but switchdev expects
1988 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1991 err = _mv88e6xxx_vtu_new(ps, vid, entry);
1997 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1998 u16 vid_begin, u16 vid_end)
2000 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2001 struct mv88e6xxx_vtu_stu_entry vlan;
2007 mutex_lock(&ps->smi_mutex);
2009 err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
2014 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
2021 if (vlan.vid > vid_end)
2024 for (i = 0; i < ps->info->num_ports; ++i) {
2025 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2029 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2032 if (ps->ports[i].bridge_dev ==
2033 ps->ports[port].bridge_dev)
2034 break; /* same bridge, check next VLAN */
2036 netdev_warn(ds->ports[port].netdev,
2037 "hardware VLAN %d already used by %s\n",
2039 netdev_name(ps->ports[i].bridge_dev));
2043 } while (vlan.vid < vid_end);
2046 mutex_unlock(&ps->smi_mutex);
2051 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2052 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2053 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2054 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2055 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2058 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2059 bool vlan_filtering)
2061 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2062 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2063 PORT_CONTROL_2_8021Q_DISABLED;
2066 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2069 mutex_lock(&ps->smi_mutex);
2071 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
2075 old = ret & PORT_CONTROL_2_8021Q_MASK;
2078 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2079 ret |= new & PORT_CONTROL_2_8021Q_MASK;
2081 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
2086 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
2087 mv88e6xxx_port_8021q_mode_names[new],
2088 mv88e6xxx_port_8021q_mode_names[old]);
2093 mutex_unlock(&ps->smi_mutex);
2099 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2100 const struct switchdev_obj_port_vlan *vlan,
2101 struct switchdev_trans *trans)
2103 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2106 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2109 /* If the requested port doesn't belong to the same bridge as the VLAN
2110 * members, do not support it (yet) and fallback to software VLAN.
2112 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2117 /* We don't need any dynamic resource from the kernel (yet),
2118 * so skip the prepare phase.
2123 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2124 u16 vid, bool untagged)
2126 struct mv88e6xxx_vtu_stu_entry vlan;
2129 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
2133 vlan.data[port] = untagged ?
2134 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2135 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2137 return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
2140 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2141 const struct switchdev_obj_port_vlan *vlan,
2142 struct switchdev_trans *trans)
2144 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2145 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2146 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2149 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2152 mutex_lock(&ps->smi_mutex);
2154 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2155 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
2156 netdev_err(ds->ports[port].netdev,
2157 "failed to add VLAN %d%c\n",
2158 vid, untagged ? 'u' : 't');
2160 if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
2161 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
2164 mutex_unlock(&ps->smi_mutex);
2167 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2170 struct dsa_switch *ds = ps->ds;
2171 struct mv88e6xxx_vtu_stu_entry vlan;
2174 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
2178 /* Tell switchdev if this VLAN is handled in software */
2179 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2182 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2184 /* keep the VLAN unless all ports are excluded */
2186 for (i = 0; i < ps->info->num_ports; ++i) {
2187 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2190 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2196 err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
2200 return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
2203 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2204 const struct switchdev_obj_port_vlan *vlan)
2206 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2210 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2213 mutex_lock(&ps->smi_mutex);
2215 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
2219 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2220 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
2225 err = _mv88e6xxx_port_pvid_set(ps, port, 0);
2232 mutex_unlock(&ps->smi_mutex);
2237 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
2238 const unsigned char *addr)
2242 for (i = 0; i < 3; i++) {
2243 ret = _mv88e6xxx_reg_write(
2244 ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2245 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2253 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2254 unsigned char *addr)
2258 for (i = 0; i < 3; i++) {
2259 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
2260 GLOBAL_ATU_MAC_01 + i);
2263 addr[i * 2] = ret >> 8;
2264 addr[i * 2 + 1] = ret & 0xff;
2270 static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
2271 struct mv88e6xxx_atu_entry *entry)
2275 ret = _mv88e6xxx_atu_wait(ps);
2279 ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
2283 ret = _mv88e6xxx_atu_data_write(ps, entry);
2287 return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2290 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
2291 const unsigned char *addr, u16 vid,
2294 struct mv88e6xxx_atu_entry entry = { 0 };
2295 struct mv88e6xxx_vtu_stu_entry vlan;
2298 /* Null VLAN ID corresponds to the port private database */
2300 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2302 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
2306 entry.fid = vlan.fid;
2307 entry.state = state;
2308 ether_addr_copy(entry.mac, addr);
2309 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2310 entry.trunk = false;
2311 entry.portv_trunkid = BIT(port);
2314 return _mv88e6xxx_atu_load(ps, &entry);
2317 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2318 const struct switchdev_obj_port_fdb *fdb,
2319 struct switchdev_trans *trans)
2321 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2323 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2326 /* We don't need any dynamic resource from the kernel (yet),
2327 * so skip the prepare phase.
2332 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2333 const struct switchdev_obj_port_fdb *fdb,
2334 struct switchdev_trans *trans)
2336 int state = is_multicast_ether_addr(fdb->addr) ?
2337 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2338 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2339 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2341 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2344 mutex_lock(&ps->smi_mutex);
2345 if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
2346 netdev_err(ds->ports[port].netdev,
2347 "failed to load MAC address\n");
2348 mutex_unlock(&ps->smi_mutex);
2351 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2352 const struct switchdev_obj_port_fdb *fdb)
2354 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2357 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2360 mutex_lock(&ps->smi_mutex);
2361 ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
2362 GLOBAL_ATU_DATA_STATE_UNUSED);
2363 mutex_unlock(&ps->smi_mutex);
2368 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
2369 struct mv88e6xxx_atu_entry *entry)
2371 struct mv88e6xxx_atu_entry next = { 0 };
2376 ret = _mv88e6xxx_atu_wait(ps);
2380 ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2384 ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
2388 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
2392 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2393 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2394 unsigned int mask, shift;
2396 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2398 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2399 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2402 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2403 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2406 next.portv_trunkid = (ret & mask) >> shift;
2413 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2414 u16 fid, u16 vid, int port,
2415 struct switchdev_obj_port_fdb *fdb,
2416 int (*cb)(struct switchdev_obj *obj))
2418 struct mv88e6xxx_atu_entry addr = {
2419 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2423 err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
2428 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
2432 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2435 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2436 bool is_static = addr.state ==
2437 (is_multicast_ether_addr(addr.mac) ?
2438 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2439 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2442 ether_addr_copy(fdb->addr, addr.mac);
2443 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2445 err = cb(&fdb->obj);
2449 } while (!is_broadcast_ether_addr(addr.mac));
2454 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2455 struct switchdev_obj_port_fdb *fdb,
2456 int (*cb)(struct switchdev_obj *obj))
2458 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2459 struct mv88e6xxx_vtu_stu_entry vlan = {
2460 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2465 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2468 mutex_lock(&ps->smi_mutex);
2470 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2471 err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2475 err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2479 /* Dump VLANs' Filtering Information Databases */
2480 err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
2485 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
2492 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
2496 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2499 mutex_unlock(&ps->smi_mutex);
2504 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2505 struct net_device *bridge)
2507 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2510 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2513 mutex_lock(&ps->smi_mutex);
2515 /* Assign the bridge and remap each port's VLANTable */
2516 ps->ports[port].bridge_dev = bridge;
2518 for (i = 0; i < ps->info->num_ports; ++i) {
2519 if (ps->ports[i].bridge_dev == bridge) {
2520 err = _mv88e6xxx_port_based_vlan_map(ps, i);
2526 mutex_unlock(&ps->smi_mutex);
2531 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2533 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2534 struct net_device *bridge = ps->ports[port].bridge_dev;
2537 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2540 mutex_lock(&ps->smi_mutex);
2542 /* Unassign the bridge and remap each port's VLANTable */
2543 ps->ports[port].bridge_dev = NULL;
2545 for (i = 0; i < ps->info->num_ports; ++i)
2546 if (i == port || ps->ports[i].bridge_dev == bridge)
2547 if (_mv88e6xxx_port_based_vlan_map(ps, i))
2548 netdev_warn(ds->ports[i].netdev,
2549 "failed to remap\n");
2551 mutex_unlock(&ps->smi_mutex);
2554 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_priv_state *ps,
2555 int port, int page, int reg, int val)
2559 ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page);
2561 goto restore_page_0;
2563 ret = mv88e6xxx_mdio_write_indirect(ps, port, reg, val);
2565 mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0);
2570 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_priv_state *ps,
2571 int port, int page, int reg)
2575 ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page);
2577 goto restore_page_0;
2579 ret = mv88e6xxx_mdio_read_indirect(ps, port, reg);
2581 mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0);
2586 static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2588 bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE);
2589 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2590 struct gpio_desc *gpiod = ps->reset;
2591 unsigned long timeout;
2595 /* Set all ports to the disabled state. */
2596 for (i = 0; i < ps->info->num_ports; i++) {
2597 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
2601 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
2607 /* Wait for transmit queues to drain. */
2608 usleep_range(2000, 4000);
2610 /* If there is a gpio connected to the reset pin, toggle it */
2612 gpiod_set_value_cansleep(gpiod, 1);
2613 usleep_range(10000, 20000);
2614 gpiod_set_value_cansleep(gpiod, 0);
2615 usleep_range(10000, 20000);
2618 /* Reset the switch. Keep the PPU active if requested. The PPU
2619 * needs to be active to support indirect phy register access
2620 * through global registers 0x18 and 0x19.
2623 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
2625 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
2629 /* Wait up to one second for reset to complete. */
2630 timeout = jiffies + 1 * HZ;
2631 while (time_before(jiffies, timeout)) {
2632 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
2636 if ((ret & is_reset) == is_reset)
2638 usleep_range(1000, 2000);
2640 if (time_after(jiffies, timeout))
2648 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
2652 ret = _mv88e6xxx_mdio_page_read(ps, REG_FIBER_SERDES,
2653 PAGE_FIBER_SERDES, MII_BMCR);
2657 if (ret & BMCR_PDOWN) {
2659 ret = _mv88e6xxx_mdio_page_write(ps, REG_FIBER_SERDES,
2660 PAGE_FIBER_SERDES, MII_BMCR,
2667 static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2669 struct dsa_switch *ds = ps->ds;
2673 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2674 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2675 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2676 mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
2677 /* MAC Forcing register: don't force link, speed,
2678 * duplex or flow control state to any particular
2679 * values on physical ports, but force the CPU port
2680 * and all DSA ports to their maximum bandwidth and
2683 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
2684 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2685 reg &= ~PORT_PCS_CTRL_UNFORCED;
2686 reg |= PORT_PCS_CTRL_FORCE_LINK |
2687 PORT_PCS_CTRL_LINK_UP |
2688 PORT_PCS_CTRL_DUPLEX_FULL |
2689 PORT_PCS_CTRL_FORCE_DUPLEX;
2690 if (mv88e6xxx_6065_family(ps))
2691 reg |= PORT_PCS_CTRL_100;
2693 reg |= PORT_PCS_CTRL_1000;
2695 reg |= PORT_PCS_CTRL_UNFORCED;
2698 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2699 PORT_PCS_CTRL, reg);
2704 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2705 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2706 * tunneling, determine priority by looking at 802.1p and IP
2707 * priority fields (IP prio has precedence), and set STP state
2710 * If this is the CPU link, use DSA or EDSA tagging depending
2711 * on which tagging mode was configured.
2713 * If this is a link to another switch, use DSA tagging mode.
2715 * If this is the upstream port for this switch, enable
2716 * forwarding of unknown unicasts and multicasts.
2719 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2720 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2721 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2722 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
2723 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2724 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2725 PORT_CONTROL_STATE_FORWARDING;
2726 if (dsa_is_cpu_port(ds, port)) {
2727 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
2728 reg |= PORT_CONTROL_DSA_TAG;
2729 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2730 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2731 mv88e6xxx_6320_family(ps)) {
2732 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2733 PORT_CONTROL_FORWARD_UNKNOWN |
2734 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2737 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2738 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2739 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2740 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
2741 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2744 if (dsa_is_dsa_port(ds, port)) {
2745 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
2746 reg |= PORT_CONTROL_DSA_TAG;
2747 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2748 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2749 mv88e6xxx_6320_family(ps)) {
2750 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2753 if (port == dsa_upstream_port(ds))
2754 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2755 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2758 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2764 /* If this port is connected to a SerDes, make sure the SerDes is not
2767 if (mv88e6xxx_6352_family(ps)) {
2768 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
2771 ret &= PORT_STATUS_CMODE_MASK;
2772 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2773 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2774 (ret == PORT_STATUS_CMODE_SGMII)) {
2775 ret = mv88e6xxx_power_on_serdes(ps);
2781 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2782 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2783 * untagged frames on this port, do a destination address lookup on all
2784 * received packets as usual, disable ARP mirroring and don't send a
2785 * copy of all transmitted/received frames on this port to the CPU.
2788 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2789 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2790 mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2791 mv88e6xxx_6185_family(ps))
2792 reg = PORT_CONTROL_2_MAP_DA;
2794 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2795 mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
2796 reg |= PORT_CONTROL_2_JUMBO_10240;
2798 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
2799 /* Set the upstream port this port should use */
2800 reg |= dsa_upstream_port(ds);
2801 /* enable forwarding of unknown multicast addresses to
2804 if (port == dsa_upstream_port(ds))
2805 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2808 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2811 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2812 PORT_CONTROL_2, reg);
2817 /* Port Association Vector: when learning source addresses
2818 * of packets, add the address to the address database using
2819 * a port bitmap that has only the bit for this port set and
2820 * the other bits clear.
2823 /* Disable learning for CPU port */
2824 if (dsa_is_cpu_port(ds, port))
2827 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2831 /* Egress rate control 2: disable egress rate control. */
2832 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
2837 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2838 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2839 mv88e6xxx_6320_family(ps)) {
2840 /* Do not limit the period of time that this port can
2841 * be paused for by the remote end or the period of
2842 * time that this port can pause the remote end.
2844 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2845 PORT_PAUSE_CTRL, 0x0000);
2849 /* Port ATU control: disable limiting the number of
2850 * address database entries that this port is allowed
2853 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2854 PORT_ATU_CONTROL, 0x0000);
2855 /* Priority Override: disable DA, SA and VTU priority
2858 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2859 PORT_PRI_OVERRIDE, 0x0000);
2863 /* Port Ethertype: use the Ethertype DSA Ethertype
2866 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2867 PORT_ETH_TYPE, ETH_P_EDSA);
2870 /* Tag Remap: use an identity 802.1p prio -> switch
2873 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2874 PORT_TAG_REGMAP_0123, 0x3210);
2878 /* Tag Remap 2: use an identity 802.1p prio -> switch
2881 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2882 PORT_TAG_REGMAP_4567, 0x7654);
2887 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2888 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2889 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2890 mv88e6xxx_6320_family(ps)) {
2891 /* Rate Control: disable ingress rate limiting. */
2892 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2893 PORT_RATE_CONTROL, 0x0001);
2898 /* Port Control 1: disable trunking, disable sending
2899 * learning messages to this port.
2901 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2905 /* Port based VLAN map: give each port the same default address
2906 * database, and allow bidirectional communication between the
2907 * CPU and DSA port(s), and the other ports.
2909 ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2913 ret = _mv88e6xxx_port_based_vlan_map(ps, port);
2917 /* Default VLAN ID and priority: don't set a default VLAN
2918 * ID, and set the default packet priority to zero.
2920 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
2928 static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
2930 struct dsa_switch *ds = ps->ds;
2931 u32 upstream_port = dsa_upstream_port(ds);
2936 /* Enable the PHY Polling Unit if present, don't discard any packets,
2937 * and mask all interrupt sources.
2940 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) ||
2941 mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE))
2942 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2944 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg);
2948 /* Configure the upstream port, and configure it as the port to which
2949 * ingress and egress and ARP monitor frames are to be sent.
2951 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2952 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2953 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2954 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
2958 /* Disable remote management, and set the switch's DSA device number. */
2959 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
2960 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2961 (ds->index & 0x1f));
2965 /* Set the default address aging time to 5 minutes, and
2966 * enable address learn messages to be sent to all message
2969 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2970 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2974 /* Configure the IP ToS mapping registers. */
2975 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2978 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2981 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2984 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2987 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2990 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2993 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2996 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
3000 /* Configure the IEEE 802.1p priority mapping register. */
3001 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
3005 /* Send all frames with destination addresses matching
3006 * 01:80:c2:00:00:0x to the CPU port.
3008 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
3012 /* Ignore removed tag data on doubly tagged packets, disable
3013 * flow control messages, force flow control priority to the
3014 * highest, and send all special multicast frames to the CPU
3015 * port at the highest priority.
3017 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
3018 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
3019 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
3023 /* Program the DSA routing table. */
3024 for (i = 0; i < 32; i++) {
3027 if (i != ds->index && i < DSA_MAX_SWITCHES)
3028 nexthop = ds->rtable[i] & 0x1f;
3030 err = _mv88e6xxx_reg_write(
3032 GLOBAL2_DEVICE_MAPPING,
3033 GLOBAL2_DEVICE_MAPPING_UPDATE |
3034 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
3039 /* Clear all trunk masks. */
3040 for (i = 0; i < 8; i++) {
3041 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
3043 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
3044 ((1 << ps->info->num_ports) - 1));
3049 /* Clear all trunk mappings. */
3050 for (i = 0; i < 16; i++) {
3051 err = _mv88e6xxx_reg_write(
3053 GLOBAL2_TRUNK_MAPPING,
3054 GLOBAL2_TRUNK_MAPPING_UPDATE |
3055 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
3060 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3061 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3062 mv88e6xxx_6320_family(ps)) {
3063 /* Send all frames with destination addresses matching
3064 * 01:80:c2:00:00:2x to the CPU port.
3066 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3067 GLOBAL2_MGMT_EN_2X, 0xffff);
3071 /* Initialise cross-chip port VLAN table to reset
3074 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3075 GLOBAL2_PVT_ADDR, 0x9000);
3079 /* Clear the priority override table. */
3080 for (i = 0; i < 16; i++) {
3081 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3082 GLOBAL2_PRIO_OVERRIDE,
3089 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3090 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3091 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
3092 mv88e6xxx_6320_family(ps)) {
3093 /* Disable ingress rate limiting by resetting all
3094 * ingress rate limit registers to their initial
3097 for (i = 0; i < ps->info->num_ports; i++) {
3098 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3106 /* Clear the statistics counters for all ports */
3107 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
3108 GLOBAL_STATS_OP_FLUSH_ALL);
3112 /* Wait for the flush to complete. */
3113 err = _mv88e6xxx_stats_wait(ps);
3117 /* Clear all ATU entries */
3118 err = _mv88e6xxx_atu_flush(ps, 0, true);
3122 /* Clear all the VTU and STU entries */
3123 err = _mv88e6xxx_vtu_stu_flush(ps);
3130 static int mv88e6xxx_setup(struct dsa_switch *ds)
3132 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3137 ds->slave_mii_bus = ps->mdio_bus;
3139 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
3140 mutex_init(&ps->eeprom_mutex);
3142 mutex_lock(&ps->smi_mutex);
3144 err = mv88e6xxx_switch_reset(ps);
3148 err = mv88e6xxx_setup_global(ps);
3152 for (i = 0; i < ps->info->num_ports; i++) {
3153 err = mv88e6xxx_setup_port(ps, i);
3159 mutex_unlock(&ps->smi_mutex);
3164 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3167 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3170 mutex_lock(&ps->smi_mutex);
3171 ret = _mv88e6xxx_mdio_page_read(ps, port, page, reg);
3172 mutex_unlock(&ps->smi_mutex);
3177 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3180 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3183 mutex_lock(&ps->smi_mutex);
3184 ret = _mv88e6xxx_mdio_page_write(ps, port, page, reg, val);
3185 mutex_unlock(&ps->smi_mutex);
3190 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_priv_state *ps,
3193 if (port >= 0 && port < ps->info->num_ports)
3198 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3200 struct mv88e6xxx_priv_state *ps = bus->priv;
3201 int addr = mv88e6xxx_port_to_mdio_addr(ps, port);
3207 mutex_lock(&ps->smi_mutex);
3209 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3210 ret = mv88e6xxx_mdio_read_ppu(ps, addr, regnum);
3211 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3212 ret = mv88e6xxx_mdio_read_indirect(ps, addr, regnum);
3214 ret = mv88e6xxx_mdio_read_direct(ps, addr, regnum);
3216 mutex_unlock(&ps->smi_mutex);
3220 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3223 struct mv88e6xxx_priv_state *ps = bus->priv;
3224 int addr = mv88e6xxx_port_to_mdio_addr(ps, port);
3230 mutex_lock(&ps->smi_mutex);
3232 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3233 ret = mv88e6xxx_mdio_write_ppu(ps, addr, regnum, val);
3234 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3235 ret = mv88e6xxx_mdio_write_indirect(ps, addr, regnum, val);
3237 ret = mv88e6xxx_mdio_write_direct(ps, addr, regnum, val);
3239 mutex_unlock(&ps->smi_mutex);
3243 static int mv88e6xxx_mdio_register(struct mv88e6xxx_priv_state *ps,
3244 struct device_node *np)
3247 struct mii_bus *bus;
3250 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3251 mv88e6xxx_ppu_state_init(ps);
3254 ps->mdio_np = of_get_child_by_name(np, "mdio");
3256 bus = devm_mdiobus_alloc(ps->dev);
3260 bus->priv = (void *)ps;
3262 bus->name = np->full_name;
3263 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3265 bus->name = "mv88e6xxx SMI";
3266 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3269 bus->read = mv88e6xxx_mdio_read;
3270 bus->write = mv88e6xxx_mdio_write;
3271 bus->parent = ps->dev;
3274 err = of_mdiobus_register(bus, ps->mdio_np);
3276 err = mdiobus_register(bus);
3278 dev_err(ps->dev, "Cannot register MDIO bus (%d)\n", err);
3287 of_node_put(ps->mdio_np);
3292 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_priv_state *ps)
3295 struct mii_bus *bus = ps->mdio_bus;
3297 mdiobus_unregister(bus);
3300 of_node_put(ps->mdio_np);
3303 #ifdef CONFIG_NET_DSA_HWMON
3305 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3307 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3313 mutex_lock(&ps->smi_mutex);
3315 ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x6);
3319 /* Enable temperature sensor */
3320 ret = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a);
3324 ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret | (1 << 5));
3328 /* Wait for temperature to stabilize */
3329 usleep_range(10000, 12000);
3331 val = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a);
3337 /* Disable temperature sensor */
3338 ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret & ~(1 << 5));
3342 *temp = ((val & 0x1f) - 5) * 5;
3345 mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x0);
3346 mutex_unlock(&ps->smi_mutex);
3350 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3352 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3353 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3358 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3362 *temp = (ret & 0xff) - 25;
3367 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3369 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3371 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3374 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
3375 return mv88e63xx_get_temp(ds, temp);
3377 return mv88e61xx_get_temp(ds, temp);
3380 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3382 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3383 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3386 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3391 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3395 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3400 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3403 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3406 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3409 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3412 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3413 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3414 (ret & 0xe0ff) | (temp << 8));
3417 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3419 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3420 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3423 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3428 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3432 *alarm = !!(ret & 0x40);
3436 #endif /* CONFIG_NET_DSA_HWMON */
3438 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3440 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3441 .family = MV88E6XXX_FAMILY_6097,
3442 .name = "Marvell 88E6085",
3443 .num_databases = 4096,
3445 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3449 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3450 .family = MV88E6XXX_FAMILY_6095,
3451 .name = "Marvell 88E6095/88E6095F",
3452 .num_databases = 256,
3454 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3458 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3459 .family = MV88E6XXX_FAMILY_6165,
3460 .name = "Marvell 88E6123",
3461 .num_databases = 4096,
3463 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3467 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3468 .family = MV88E6XXX_FAMILY_6185,
3469 .name = "Marvell 88E6131",
3470 .num_databases = 256,
3472 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3476 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3477 .family = MV88E6XXX_FAMILY_6165,
3478 .name = "Marvell 88E6161",
3479 .num_databases = 4096,
3481 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3485 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3486 .family = MV88E6XXX_FAMILY_6165,
3487 .name = "Marvell 88E6165",
3488 .num_databases = 4096,
3490 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3494 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3495 .family = MV88E6XXX_FAMILY_6351,
3496 .name = "Marvell 88E6171",
3497 .num_databases = 4096,
3499 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3503 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3504 .family = MV88E6XXX_FAMILY_6352,
3505 .name = "Marvell 88E6172",
3506 .num_databases = 4096,
3508 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3512 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3513 .family = MV88E6XXX_FAMILY_6351,
3514 .name = "Marvell 88E6175",
3515 .num_databases = 4096,
3517 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3521 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3522 .family = MV88E6XXX_FAMILY_6352,
3523 .name = "Marvell 88E6176",
3524 .num_databases = 4096,
3526 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3530 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3531 .family = MV88E6XXX_FAMILY_6185,
3532 .name = "Marvell 88E6185",
3533 .num_databases = 256,
3535 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3539 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3540 .family = MV88E6XXX_FAMILY_6352,
3541 .name = "Marvell 88E6240",
3542 .num_databases = 4096,
3544 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3548 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3549 .family = MV88E6XXX_FAMILY_6320,
3550 .name = "Marvell 88E6320",
3551 .num_databases = 4096,
3553 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3557 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3558 .family = MV88E6XXX_FAMILY_6320,
3559 .name = "Marvell 88E6321",
3560 .num_databases = 4096,
3562 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3566 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3567 .family = MV88E6XXX_FAMILY_6351,
3568 .name = "Marvell 88E6350",
3569 .num_databases = 4096,
3571 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3575 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3576 .family = MV88E6XXX_FAMILY_6351,
3577 .name = "Marvell 88E6351",
3578 .num_databases = 4096,
3580 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3584 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3585 .family = MV88E6XXX_FAMILY_6352,
3586 .name = "Marvell 88E6352",
3587 .num_databases = 4096,
3589 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3593 static const struct mv88e6xxx_info *
3594 mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
3599 for (i = 0; i < num; ++i)
3600 if (table[i].prod_num == prod_num)
3606 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3607 struct device *host_dev, int sw_addr,
3610 const struct mv88e6xxx_info *info;
3611 struct mv88e6xxx_priv_state *ps;
3612 struct mii_bus *bus;
3614 int id, prod_num, rev;
3617 bus = dsa_host_dev_to_mii_bus(host_dev);
3621 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3625 prod_num = (id & 0xfff0) >> 4;
3628 info = mv88e6xxx_lookup_info(prod_num, mv88e6xxx_table,
3629 ARRAY_SIZE(mv88e6xxx_table));
3635 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3640 ps->sw_addr = sw_addr;
3643 mutex_init(&ps->smi_mutex);
3645 err = mv88e6xxx_mdio_register(ps, NULL);
3651 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3652 prod_num, name, rev);
3657 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3658 .tag_protocol = DSA_TAG_PROTO_EDSA,
3659 .probe = mv88e6xxx_drv_probe,
3660 .setup = mv88e6xxx_setup,
3661 .set_addr = mv88e6xxx_set_addr,
3662 .adjust_link = mv88e6xxx_adjust_link,
3663 .get_strings = mv88e6xxx_get_strings,
3664 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3665 .get_sset_count = mv88e6xxx_get_sset_count,
3666 .set_eee = mv88e6xxx_set_eee,
3667 .get_eee = mv88e6xxx_get_eee,
3668 #ifdef CONFIG_NET_DSA_HWMON
3669 .get_temp = mv88e6xxx_get_temp,
3670 .get_temp_limit = mv88e6xxx_get_temp_limit,
3671 .set_temp_limit = mv88e6xxx_set_temp_limit,
3672 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3674 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3675 .get_eeprom = mv88e6xxx_get_eeprom,
3676 .set_eeprom = mv88e6xxx_set_eeprom,
3677 .get_regs_len = mv88e6xxx_get_regs_len,
3678 .get_regs = mv88e6xxx_get_regs,
3679 .port_bridge_join = mv88e6xxx_port_bridge_join,
3680 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3681 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3682 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3683 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3684 .port_vlan_add = mv88e6xxx_port_vlan_add,
3685 .port_vlan_del = mv88e6xxx_port_vlan_del,
3686 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3687 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3688 .port_fdb_add = mv88e6xxx_port_fdb_add,
3689 .port_fdb_del = mv88e6xxx_port_fdb_del,
3690 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3693 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3695 struct device *dev = &mdiodev->dev;
3696 struct device_node *np = dev->of_node;
3697 struct mv88e6xxx_priv_state *ps;
3698 int id, prod_num, rev;
3699 struct dsa_switch *ds;
3703 ds = devm_kzalloc(dev, sizeof(*ds) + sizeof(*ps), GFP_KERNEL);
3707 ps = (struct mv88e6xxx_priv_state *)(ds + 1);
3711 ps->bus = mdiodev->bus;
3712 ps->sw_addr = mdiodev->addr;
3713 mutex_init(&ps->smi_mutex);
3715 ds->drv = &mv88e6xxx_switch_driver;
3717 id = mv88e6xxx_reg_read(ps, REG_PORT(0), PORT_SWITCH_ID);
3721 prod_num = (id & 0xfff0) >> 4;
3724 ps->info = mv88e6xxx_lookup_info(prod_num, mv88e6xxx_table,
3725 ARRAY_SIZE(mv88e6xxx_table));
3729 ps->reset = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
3730 if (IS_ERR(ps->reset)) {
3731 err = PTR_ERR(ps->reset);
3732 if (err == -ENOENT) {
3733 /* Optional, so not an error */
3740 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM) &&
3741 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3742 ps->eeprom_len = eeprom_len;
3744 err = mv88e6xxx_mdio_register(ps, np);
3748 dev_set_drvdata(dev, ds);
3750 err = dsa_register_switch(ds, np);
3752 mv88e6xxx_mdio_unregister(ps);
3756 dev_info(dev, "switch 0x%x probed: %s, revision %u\n",
3757 prod_num, ps->info->name, rev);
3762 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3764 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3765 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3767 dsa_unregister_switch(ds);
3769 mv88e6xxx_mdio_unregister(ps);
3772 static const struct of_device_id mv88e6xxx_of_match[] = {
3773 { .compatible = "marvell,mv88e6085" },
3777 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3779 static struct mdio_driver mv88e6xxx_driver = {
3780 .probe = mv88e6xxx_probe,
3781 .remove = mv88e6xxx_remove,
3783 .name = "mv88e6085",
3784 .of_match_table = mv88e6xxx_of_match,
3788 static int __init mv88e6xxx_init(void)
3790 register_switch_driver(&mv88e6xxx_switch_driver);
3791 return mdio_driver_register(&mv88e6xxx_driver);
3793 module_init(mv88e6xxx_init);
3795 static void __exit mv88e6xxx_cleanup(void)
3797 mdio_driver_unregister(&mv88e6xxx_driver);
3798 unregister_switch_driver(&mv88e6xxx_switch_driver);
3800 module_exit(mv88e6xxx_cleanup);
3802 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3803 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3804 MODULE_LICENSE("GPL");