drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Copper)
  32  * 82571EB Gigabit Ethernet Controller (Fiber)
  33  * 82571EB Dual Port Gigabit Mezzanine Adapter
  34  * 82571EB Quad Port Gigabit Mezzanine Adapter
  35  * 82571PT Gigabit PT Quad Port Server ExpressModule
  36  * 82572EI Gigabit Ethernet Controller (Copper)
  37  * 82572EI Gigabit Ethernet Controller (Fiber)
  38  * 82572EI Gigabit Ethernet Controller
  39  * 82573V Gigabit Ethernet Controller (Copper)
  40  * 82573E Gigabit Ethernet Controller (Copper)
  41  * 82573L Gigabit Ethernet Controller
  42  * 82574L Gigabit Network Connection
  43  * 82583V Gigabit Network Connection
  44  */
  45
  46 #include "e1000.h"
  47
  48 #define ID_LED_RESERVED_F746 0xF746
  49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  50                               (ID_LED_OFF1_ON2  <<  8) | \
  51                               (ID_LED_DEF1_DEF2 <<  4) | \
  52                               (ID_LED_DEF1_DEF2))
  53
  54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  55 #define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */
  56 #define E1000_BASE1000T_STATUS          10
  57 #define E1000_IDLE_ERROR_COUNT_MASK     0xFF
  58 #define E1000_RECEIVE_ERROR_COUNTER     21
  59 #define E1000_RECEIVE_ERROR_MAX         0xFFFF
  60
  61 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  62
  63 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  64 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  65 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  66 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  67 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  68                                       u16 words, u16 *data);
  69 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  70 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  71 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  73 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  74 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  75 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  77 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  78 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  79 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  81 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
  82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
  83
  84 /**
  85  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  86  *  @hw: pointer to the HW structure
  87  **/
  88 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  89 {
  90         struct e1000_phy_info *phy = &hw->phy;
  91         s32 ret_val;
  92
  93         if (hw->phy.media_type != e1000_media_type_copper) {
  94                 phy->type = e1000_phy_none;
  95                 return 0;
  96         }
  97
  98         phy->addr                        = 1;
  99         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 100         phy->reset_delay_us              = 100;
 101
 102         phy->ops.power_up                = e1000_power_up_phy_copper;
 103         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 104
 105         switch (hw->mac.type) {
 106         case e1000_82571:
 107         case e1000_82572:
 108                 phy->type                = e1000_phy_igp_2;
 109                 break;
 110         case e1000_82573:
 111                 phy->type                = e1000_phy_m88;
 112                 break;
 113         case e1000_82574:
 114         case e1000_82583:
 115                 phy->type                = e1000_phy_bm;
 116                 phy->ops.acquire = e1000_get_hw_semaphore_82574;
 117                 phy->ops.release = e1000_put_hw_semaphore_82574;
 118                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 119                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 120                 break;
 121         default:
 122                 return -E1000_ERR_PHY;
 123                 break;
 124         }
 125
 126         /* This can only be done after all function pointers are setup. */
 127         ret_val = e1000_get_phy_id_82571(hw);
 128         if (ret_val) {
 129                 e_dbg("Error getting PHY ID\n");
 130                 return ret_val;
 131         }
 132
 133         /* Verify phy id */
 134         switch (hw->mac.type) {
 135         case e1000_82571:
 136         case e1000_82572:
 137                 if (phy->id != IGP01E1000_I_PHY_ID)
 138                         ret_val = -E1000_ERR_PHY;
 139                 break;
 140         case e1000_82573:
 141                 if (phy->id != M88E1111_I_PHY_ID)
 142                         ret_val = -E1000_ERR_PHY;
 143                 break;
 144         case e1000_82574:
 145         case e1000_82583:
 146                 if (phy->id != BME1000_E_PHY_ID_R2)
 147                         ret_val = -E1000_ERR_PHY;
 148                 break;
 149         default:
 150                 ret_val = -E1000_ERR_PHY;
 151                 break;
 152         }
 153
 154         if (ret_val)
 155                 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
 156
 157         return ret_val;
 158 }
 159
 160 /**
 161  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 162  *  @hw: pointer to the HW structure
 163  **/
 164 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 165 {
 166         struct e1000_nvm_info *nvm = &hw->nvm;
 167         u32 eecd = er32(EECD);
 168         u16 size;
 169
 170         nvm->opcode_bits = 8;
 171         nvm->delay_usec = 1;
 172         switch (nvm->override) {
 173         case e1000_nvm_override_spi_large:
 174                 nvm->page_size = 32;
 175                 nvm->address_bits = 16;
 176                 break;
 177         case e1000_nvm_override_spi_small:
 178                 nvm->page_size = 8;
 179                 nvm->address_bits = 8;
 180                 break;
 181         default:
 182                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 183                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 184                 break;
 185         }
 186
 187         switch (hw->mac.type) {
 188         case e1000_82573:
 189         case e1000_82574:
 190         case e1000_82583:
 191                 if (((eecd >> 15) & 0x3) == 0x3) {
 192                         nvm->type = e1000_nvm_flash_hw;
 193                         nvm->word_size = 2048;
 194                         /*
 195                          * Autonomous Flash update bit must be cleared due
 196                          * to Flash update issue.
 197                          */
 198                         eecd &= ~E1000_EECD_AUPDEN;
 199                         ew32(EECD, eecd);
 200                         break;
 201                 }
 202                 /* Fall Through */
 203         default:
 204                 nvm->type = e1000_nvm_eeprom_spi;
 205                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 206                                   E1000_EECD_SIZE_EX_SHIFT);
 207                 /*
 208                  * Added to a constant, "size" becomes the left-shift value
 209                  * for setting word_size.
 210                  */
 211                 size += NVM_WORD_SIZE_BASE_SHIFT;
 212
 213                 /* EEPROM access above 16k is unsupported */
 214                 if (size > 14)
 215                         size = 14;
 216                 nvm->word_size  = 1 << size;
 217                 break;
 218         }
 219
 220         /* Function Pointers */
 221         switch (hw->mac.type) {
 222         case e1000_82574:
 223         case e1000_82583:
 224                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 225                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 226                 break;
 227         default:
 228                 break;
 229         }
 230
 231         return 0;
 232 }
 233
 234 /**
 235  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 236  *  @hw: pointer to the HW structure
 237  **/
 238 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 239 {
 240         struct e1000_hw *hw = &adapter->hw;
 241         struct e1000_mac_info *mac = &hw->mac;
 242         struct e1000_mac_operations *func = &mac->ops;
 243         u32 swsm = 0;
 244         u32 swsm2 = 0;
 245         bool force_clear_smbi = false;
 246
 247         /* Set media type */
 248         switch (adapter->pdev->device) {
 249         case E1000_DEV_ID_82571EB_FIBER:
 250         case E1000_DEV_ID_82572EI_FIBER:
 251         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 252                 hw->phy.media_type = e1000_media_type_fiber;
 253                 break;
 254         case E1000_DEV_ID_82571EB_SERDES:
 255         case E1000_DEV_ID_82572EI_SERDES:
 256         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 257         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 258                 hw->phy.media_type = e1000_media_type_internal_serdes;
 259                 break;
 260         default:
 261                 hw->phy.media_type = e1000_media_type_copper;
 262                 break;
 263         }
 264
 265         /* Set mta register count */
 266         mac->mta_reg_count = 128;
 267         /* Set rar entry count */
 268         mac->rar_entry_count = E1000_RAR_ENTRIES;
 269         /* Adaptive IFS supported */
 270         mac->adaptive_ifs = true;
 271
 272         /* check for link */
 273         switch (hw->phy.media_type) {
 274         case e1000_media_type_copper:
 275                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 276                 func->check_for_link = e1000e_check_for_copper_link;
 277                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 278                 break;
 279         case e1000_media_type_fiber:
 280                 func->setup_physical_interface =
 281                         e1000_setup_fiber_serdes_link_82571;
 282                 func->check_for_link = e1000e_check_for_fiber_link;
 283                 func->get_link_up_info =
 284                         e1000e_get_speed_and_duplex_fiber_serdes;
 285                 break;
 286         case e1000_media_type_internal_serdes:
 287                 func->setup_physical_interface =
 288                         e1000_setup_fiber_serdes_link_82571;
 289                 func->check_for_link = e1000_check_for_serdes_link_82571;
 290                 func->get_link_up_info =
 291                         e1000e_get_speed_and_duplex_fiber_serdes;
 292                 break;
 293         default:
 294                 return -E1000_ERR_CONFIG;
 295                 break;
 296         }
 297
 298         switch (hw->mac.type) {
 299         case e1000_82573:
 300                 func->set_lan_id = e1000_set_lan_id_single_port;
 301                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 302                 func->led_on = e1000e_led_on_generic;
 303                 func->blink_led = e1000e_blink_led_generic;
 304
 305                 /* FWSM register */
 306                 mac->has_fwsm = true;
 307                 /*
 308                  * ARC supported; valid only if manageability features are
 309                  * enabled.
 310                  */
 311                 mac->arc_subsystem_valid =
 312                         (er32(FWSM) & E1000_FWSM_MODE_MASK)
 313                         ? true : false;
 314                 break;
 315         case e1000_82574:
 316         case e1000_82583:
 317                 func->set_lan_id = e1000_set_lan_id_single_port;
 318                 func->check_mng_mode = e1000_check_mng_mode_82574;
 319                 func->led_on = e1000_led_on_82574;
 320                 break;
 321         default:
 322                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 323                 func->led_on = e1000e_led_on_generic;
 324                 func->blink_led = e1000e_blink_led_generic;
 325
 326                 /* FWSM register */
 327                 mac->has_fwsm = true;
 328                 break;
 329         }
 330
 331         /*
 332          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 333          * first NVM or PHY access. This should be done for single-port
 334          * devices, and for one port only on dual-port devices so that
 335          * for those devices we can still use the SMBI lock to synchronize
 336          * inter-port accesses to the PHY & NVM.
 337          */
 338         switch (hw->mac.type) {
 339         case e1000_82571:
 340         case e1000_82572:
 341                 swsm2 = er32(SWSM2);
 342
 343                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 344                         /* Only do this for the first interface on this card */
 345                         ew32(SWSM2,
 346                             swsm2 | E1000_SWSM2_LOCK);
 347                         force_clear_smbi = true;
 348                 } else
 349                         force_clear_smbi = false;
 350                 break;
 351         default:
 352                 force_clear_smbi = true;
 353                 break;
 354         }
 355
 356         if (force_clear_smbi) {
 357                 /* Make sure SWSM.SMBI is clear */
 358                 swsm = er32(SWSM);
 359                 if (swsm & E1000_SWSM_SMBI) {
 360                         /* This bit should not be set on a first interface, and
 361                          * indicates that the bootagent or EFI code has
 362                          * improperly left this bit enabled
 363                          */
 364                         e_dbg("Please update your 82571 Bootagent\n");
 365                 }
 366                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 367         }
 368
 369         /*
 370          * Initialize device specific counter of SMBI acquisition
 371          * timeouts.
 372          */
 373          hw->dev_spec.e82571.smb_counter = 0;
 374
 375         return 0;
 376 }
 377
 378 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 379 {
 380         struct e1000_hw *hw = &adapter->hw;
 381         static int global_quad_port_a; /* global port a indication */
 382         struct pci_dev *pdev = adapter->pdev;
 383         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 384         s32 rc;
 385
 386         rc = e1000_init_mac_params_82571(adapter);
 387         if (rc)
 388                 return rc;
 389
 390         rc = e1000_init_nvm_params_82571(hw);
 391         if (rc)
 392                 return rc;
 393
 394         rc = e1000_init_phy_params_82571(hw);
 395         if (rc)
 396                 return rc;
 397
 398         /* tag quad port adapters first, it's used below */
 399         switch (pdev->device) {
 400         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 401         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 402         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 403         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 404                 adapter->flags |= FLAG_IS_QUAD_PORT;
 405                 /* mark the first port */
 406                 if (global_quad_port_a == 0)
 407                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 408                 /* Reset for multiple quad port adapters */
 409                 global_quad_port_a++;
 410                 if (global_quad_port_a == 4)
 411                         global_quad_port_a = 0;
 412                 break;
 413         default:
 414                 break;
 415         }
 416
 417         switch (adapter->hw.mac.type) {
 418         case e1000_82571:
 419                 /* these dual ports don't have WoL on port B at all */
 420                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 421                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 422                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 423                     (is_port_b))
 424                         adapter->flags &= ~FLAG_HAS_WOL;
 425                 /* quad ports only support WoL on port A */
 426                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 427                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 428                         adapter->flags &= ~FLAG_HAS_WOL;
 429                 /* Does not support WoL on any port */
 430                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 431                         adapter->flags &= ~FLAG_HAS_WOL;
 432                 break;
 433         case e1000_82573:
 434         case e1000_82574:
 435         case e1000_82583:
 436                 if (pdev->device == E1000_DEV_ID_82573L) {
 437                         adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 438                         adapter->max_hw_frame_size = DEFAULT_JUMBO;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return 0;
 446 }
 447
 448 /**
 449  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 450  *  @hw: pointer to the HW structure
 451  *
 452  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 453  *  revision in the hardware structure.
 454  **/
 455 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 456 {
 457         struct e1000_phy_info *phy = &hw->phy;
 458         s32 ret_val;
 459         u16 phy_id = 0;
 460
 461         switch (hw->mac.type) {
 462         case e1000_82571:
 463         case e1000_82572:
 464                 /*
 465                  * The 82571 firmware may still be configuring the PHY.
 466                  * In this case, we cannot access the PHY until the
 467                  * configuration is done.  So we explicitly set the
 468                  * PHY ID.
 469                  */
 470                 phy->id = IGP01E1000_I_PHY_ID;
 471                 break;
 472         case e1000_82573:
 473                 return e1000e_get_phy_id(hw);
 474                 break;
 475         case e1000_82574:
 476         case e1000_82583:
 477                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 478                 if (ret_val)
 479                         return ret_val;
 480
 481                 phy->id = (u32)(phy_id << 16);
 482                 udelay(20);
 483                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 484                 if (ret_val)
 485                         return ret_val;
 486
 487                 phy->id |= (u32)(phy_id);
 488                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 489                 break;
 490         default:
 491                 return -E1000_ERR_PHY;
 492                 break;
 493         }
 494
 495         return 0;
 496 }
 497
 498 /**
 499  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 500  *  @hw: pointer to the HW structure
 501  *
 502  *  Acquire the HW semaphore to access the PHY or NVM
 503  **/
 504 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 505 {
 506         u32 swsm;
 507         s32 sw_timeout = hw->nvm.word_size + 1;
 508         s32 fw_timeout = hw->nvm.word_size + 1;
 509         s32 i = 0;
 510
 511         /*
 512          * If we have timedout 3 times on trying to acquire
 513          * the inter-port SMBI semaphore, there is old code
 514          * operating on the other port, and it is not
 515          * releasing SMBI. Modify the number of times that
 516          * we try for the semaphore to interwork with this
 517          * older code.
 518          */
 519         if (hw->dev_spec.e82571.smb_counter > 2)
 520                 sw_timeout = 1;
 521
 522         /* Get the SW semaphore */
 523         while (i < sw_timeout) {
 524                 swsm = er32(SWSM);
 525                 if (!(swsm & E1000_SWSM_SMBI))
 526                         break;
 527
 528                 udelay(50);
 529                 i++;
 530         }
 531
 532         if (i == sw_timeout) {
 533                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 534                 hw->dev_spec.e82571.smb_counter++;
 535         }
 536         /* Get the FW semaphore. */
 537         for (i = 0; i < fw_timeout; i++) {
 538                 swsm = er32(SWSM);
 539                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 540
 541                 /* Semaphore acquired if bit latched */
 542                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 543                         break;
 544
 545                 udelay(50);
 546         }
 547
 548         if (i == fw_timeout) {
 549                 /* Release semaphores */
 550                 e1000_put_hw_semaphore_82571(hw);
 551                 e_dbg("Driver can't access the NVM\n");
 552                 return -E1000_ERR_NVM;
 553         }
 554
 555         return 0;
 556 }
 557
 558 /**
 559  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 560  *  @hw: pointer to the HW structure
 561  *
 562  *  Release hardware semaphore used to access the PHY or NVM
 563  **/
 564 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 565 {
 566         u32 swsm;
 567
 568         swsm = er32(SWSM);
 569         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 570         ew32(SWSM, swsm);
 571 }
 572 /**
 573  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 574  *  @hw: pointer to the HW structure
 575  *
 576  *  Acquire the HW semaphore during reset.
 577  *
 578  **/
 579 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 580 {
 581         u32 extcnf_ctrl;
 582         s32 ret_val = 0;
 583         s32 i = 0;
 584
 585         extcnf_ctrl = er32(EXTCNF_CTRL);
 586         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 587         do {
 588                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 589                 extcnf_ctrl = er32(EXTCNF_CTRL);
 590
 591                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 592                         break;
 593
 594                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 595
 596                 usleep_range(2000, 4000);
 597                 i++;
 598         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 599
 600         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 601                 /* Release semaphores */
 602                 e1000_put_hw_semaphore_82573(hw);
 603                 e_dbg("Driver can't access the PHY\n");
 604                 ret_val = -E1000_ERR_PHY;
 605                 goto out;
 606         }
 607
 608 out:
 609         return ret_val;
 610 }
 611
 612 /**
 613  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 614  *  @hw: pointer to the HW structure
 615  *
 616  *  Release hardware semaphore used during reset.
 617  *
 618  **/
 619 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 620 {
 621         u32 extcnf_ctrl;
 622
 623         extcnf_ctrl = er32(EXTCNF_CTRL);
 624         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 625         ew32(EXTCNF_CTRL, extcnf_ctrl);
 626 }
 627
 628 static DEFINE_MUTEX(swflag_mutex);
 629
 630 /**
 631  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 632  *  @hw: pointer to the HW structure
 633  *
 634  *  Acquire the HW semaphore to access the PHY or NVM.
 635  *
 636  **/
 637 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 638 {
 639         s32 ret_val;
 640
 641         mutex_lock(&swflag_mutex);
 642         ret_val = e1000_get_hw_semaphore_82573(hw);
 643         if (ret_val)
 644                 mutex_unlock(&swflag_mutex);
 645         return ret_val;
 646 }
 647
 648 /**
 649  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Release hardware semaphore used to access the PHY or NVM
 653  *
 654  **/
 655 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 656 {
 657         e1000_put_hw_semaphore_82573(hw);
 658         mutex_unlock(&swflag_mutex);
 659 }
 660
 661 /**
 662  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 663  *  @hw: pointer to the HW structure
 664  *  @active: true to enable LPLU, false to disable
 665  *
 666  *  Sets the LPLU D0 state according to the active flag.
 667  *  LPLU will not be activated unless the
 668  *  device autonegotiation advertisement meets standards of
 669  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 670  *  This is a function pointer entry point only called by
 671  *  PHY setup routines.
 672  **/
 673 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 674 {
 675         u16 data = er32(POEMB);
 676
 677         if (active)
 678                 data |= E1000_PHY_CTRL_D0A_LPLU;
 679         else
 680                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 681
 682         ew32(POEMB, data);
 683         return 0;
 684 }
 685
 686 /**
 687  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 688  *  @hw: pointer to the HW structure
 689  *  @active: boolean used to enable/disable lplu
 690  *
 691  *  The low power link up (lplu) state is set to the power management level D3
 692  *  when active is true, else clear lplu for D3. LPLU
 693  *  is used during Dx states where the power conservation is most important.
 694  *  During driver activity, SmartSpeed should be enabled so performance is
 695  *  maintained.
 696  **/
 697 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 698 {
 699         u16 data = er32(POEMB);
 700
 701         if (!active) {
 702                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 703         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 704                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 705                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 706                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 707         }
 708
 709         ew32(POEMB, data);
 710         return 0;
 711 }
 712
 713 /**
 714  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 715  *  @hw: pointer to the HW structure
 716  *
 717  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 718  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 719  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 720  *  hardware semaphore.
 721  **/
 722 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 723 {
 724         s32 ret_val;
 725
 726         ret_val = e1000_get_hw_semaphore_82571(hw);
 727         if (ret_val)
 728                 return ret_val;
 729
 730         switch (hw->mac.type) {
 731         case e1000_82573:
 732                 break;
 733         default:
 734                 ret_val = e1000e_acquire_nvm(hw);
 735                 break;
 736         }
 737
 738         if (ret_val)
 739                 e1000_put_hw_semaphore_82571(hw);
 740
 741         return ret_val;
 742 }
 743
 744 /**
 745  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 746  *  @hw: pointer to the HW structure
 747  *
 748  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 749  **/
 750 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 751 {
 752         e1000e_release_nvm(hw);
 753         e1000_put_hw_semaphore_82571(hw);
 754 }
 755
 756 /**
 757  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 758  *  @hw: pointer to the HW structure
 759  *  @offset: offset within the EEPROM to be written to
 760  *  @words: number of words to write
 761  *  @data: 16 bit word(s) to be written to the EEPROM
 762  *
 763  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 764  *
 765  *  If e1000e_update_nvm_checksum is not called after this function, the
 766  *  EEPROM will most likely contain an invalid checksum.
 767  **/
 768 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 769                                  u16 *data)
 770 {
 771         s32 ret_val;
 772
 773         switch (hw->mac.type) {
 774         case e1000_82573:
 775         case e1000_82574:
 776         case e1000_82583:
 777                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 778                 break;
 779         case e1000_82571:
 780         case e1000_82572:
 781                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 782                 break;
 783         default:
 784                 ret_val = -E1000_ERR_NVM;
 785                 break;
 786         }
 787
 788         return ret_val;
 789 }
 790
 791 /**
 792  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 793  *  @hw: pointer to the HW structure
 794  *
 795  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 796  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 797  *  value to the EEPROM.
 798  **/
 799 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 800 {
 801         u32 eecd;
 802         s32 ret_val;
 803         u16 i;
 804
 805         ret_val = e1000e_update_nvm_checksum_generic(hw);
 806         if (ret_val)
 807                 return ret_val;
 808
 809         /*
 810          * If our nvm is an EEPROM, then we're done
 811          * otherwise, commit the checksum to the flash NVM.
 812          */
 813         if (hw->nvm.type != e1000_nvm_flash_hw)
 814                 return ret_val;
 815
 816         /* Check for pending operations. */
 817         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 818                 usleep_range(1000, 2000);
 819                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 820                         break;
 821         }
 822
 823         if (i == E1000_FLASH_UPDATES)
 824                 return -E1000_ERR_NVM;
 825
 826         /* Reset the firmware if using STM opcode. */
 827         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 828                 /*
 829                  * The enabling of and the actual reset must be done
 830                  * in two write cycles.
 831                  */
 832                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 833                 e1e_flush();
 834                 ew32(HICR, E1000_HICR_FW_RESET);
 835         }
 836
 837         /* Commit the write to flash */
 838         eecd = er32(EECD) | E1000_EECD_FLUPD;
 839         ew32(EECD, eecd);
 840
 841         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 842                 usleep_range(1000, 2000);
 843                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 844                         break;
 845         }
 846
 847         if (i == E1000_FLASH_UPDATES)
 848                 return -E1000_ERR_NVM;
 849
 850         return 0;
 851 }
 852
 853 /**
 854  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 855  *  @hw: pointer to the HW structure
 856  *
 857  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 858  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 859  **/
 860 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 861 {
 862         if (hw->nvm.type == e1000_nvm_flash_hw)
 863                 e1000_fix_nvm_checksum_82571(hw);
 864
 865         return e1000e_validate_nvm_checksum_generic(hw);
 866 }
 867
 868 /**
 869  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 870  *  @hw: pointer to the HW structure
 871  *  @offset: offset within the EEPROM to be written to
 872  *  @words: number of words to write
 873  *  @data: 16 bit word(s) to be written to the EEPROM
 874  *
 875  *  After checking for invalid values, poll the EEPROM to ensure the previous
 876  *  command has completed before trying to write the next word.  After write
 877  *  poll for completion.
 878  *
 879  *  If e1000e_update_nvm_checksum is not called after this function, the
 880  *  EEPROM will most likely contain an invalid checksum.
 881  **/
 882 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 883                                       u16 words, u16 *data)
 884 {
 885         struct e1000_nvm_info *nvm = &hw->nvm;
 886         u32 i, eewr = 0;
 887         s32 ret_val = 0;
 888
 889         /*
 890          * A check for invalid values:  offset too large, too many words,
 891          * and not enough words.
 892          */
 893         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 894             (words == 0)) {
 895                 e_dbg("nvm parameter(s) out of bounds\n");
 896                 return -E1000_ERR_NVM;
 897         }
 898
 899         for (i = 0; i < words; i++) {
 900                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 901                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 902                        E1000_NVM_RW_REG_START;
 903
 904                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 905                 if (ret_val)
 906                         break;
 907
 908                 ew32(EEWR, eewr);
 909
 910                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 911                 if (ret_val)
 912                         break;
 913         }
 914
 915         return ret_val;
 916 }
 917
 918 /**
 919  *  e1000_get_cfg_done_82571 - Poll for configuration done
 920  *  @hw: pointer to the HW structure
 921  *
 922  *  Reads the management control register for the config done bit to be set.
 923  **/
 924 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 925 {
 926         s32 timeout = PHY_CFG_TIMEOUT;
 927
 928         while (timeout) {
 929                 if (er32(EEMNGCTL) &
 930                     E1000_NVM_CFG_DONE_PORT_0)
 931                         break;
 932                 usleep_range(1000, 2000);
 933                 timeout--;
 934         }
 935         if (!timeout) {
 936                 e_dbg("MNG configuration cycle has not completed.\n");
 937                 return -E1000_ERR_RESET;
 938         }
 939
 940         return 0;
 941 }
 942
 943 /**
 944  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 945  *  @hw: pointer to the HW structure
 946  *  @active: true to enable LPLU, false to disable
 947  *
 948  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 949  *  this function also disables smart speed and vice versa.  LPLU will not be
 950  *  activated unless the device autonegotiation advertisement meets standards
 951  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 952  *  pointer entry point only called by PHY setup routines.
 953  **/
 954 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 955 {
 956         struct e1000_phy_info *phy = &hw->phy;
 957         s32 ret_val;
 958         u16 data;
 959
 960         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 961         if (ret_val)
 962                 return ret_val;
 963
 964         if (active) {
 965                 data |= IGP02E1000_PM_D0_LPLU;
 966                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 967                 if (ret_val)
 968                         return ret_val;
 969
 970                 /* When LPLU is enabled, we should disable SmartSpeed */
 971                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 972                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 973                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 974                 if (ret_val)
 975                         return ret_val;
 976         } else {
 977                 data &= ~IGP02E1000_PM_D0_LPLU;
 978                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 979                 /*
 980                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 981                  * during Dx states where the power conservation is most
 982                  * important.  During driver activity we should enable
 983                  * SmartSpeed, so performance is maintained.
 984                  */
 985                 if (phy->smart_speed == e1000_smart_speed_on) {
 986                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 987                                            &data);
 988                         if (ret_val)
 989                                 return ret_val;
 990
 991                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 992                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 993                                            data);
 994                         if (ret_val)
 995                                 return ret_val;
 996                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 997                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 998                                            &data);
 999                         if (ret_val)
1000                                 return ret_val;
1001
1002                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1003                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1004                                            data);
1005                         if (ret_val)
1006                                 return ret_val;
1007                 }
1008         }
1009
1010         return 0;
1011 }
1012
1013 /**
1014  *  e1000_reset_hw_82571 - Reset hardware
1015  *  @hw: pointer to the HW structure
1016  *
1017  *  This resets the hardware into a known state.
1018  **/
1019 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1020 {
1021         u32 ctrl, ctrl_ext;
1022         s32 ret_val;
1023
1024         /*
1025          * Prevent the PCI-E bus from sticking if there is no TLP connection
1026          * on the last TLP read/write transaction when MAC is reset.
1027          */
1028         ret_val = e1000e_disable_pcie_master(hw);
1029         if (ret_val)
1030                 e_dbg("PCI-E Master disable polling has failed.\n");
1031
1032         e_dbg("Masking off all interrupts\n");
1033         ew32(IMC, 0xffffffff);
1034
1035         ew32(RCTL, 0);
1036         ew32(TCTL, E1000_TCTL_PSP);
1037         e1e_flush();
1038
1039         usleep_range(10000, 20000);
1040
1041         /*
1042          * Must acquire the MDIO ownership before MAC reset.
1043          * Ownership defaults to firmware after a reset.
1044          */
1045         switch (hw->mac.type) {
1046         case e1000_82573:
1047                 ret_val = e1000_get_hw_semaphore_82573(hw);
1048                 break;
1049         case e1000_82574:
1050         case e1000_82583:
1051                 ret_val = e1000_get_hw_semaphore_82574(hw);
1052                 break;
1053         default:
1054                 break;
1055         }
1056         if (ret_val)
1057                 e_dbg("Cannot acquire MDIO ownership\n");
1058
1059         ctrl = er32(CTRL);
1060
1061         e_dbg("Issuing a global reset to MAC\n");
1062         ew32(CTRL, ctrl | E1000_CTRL_RST);
1063
1064         /* Must release MDIO ownership and mutex after MAC reset. */
1065         switch (hw->mac.type) {
1066         case e1000_82574:
1067         case e1000_82583:
1068                 e1000_put_hw_semaphore_82574(hw);
1069                 break;
1070         default:
1071                 break;
1072         }
1073
1074         if (hw->nvm.type == e1000_nvm_flash_hw) {
1075                 udelay(10);
1076                 ctrl_ext = er32(CTRL_EXT);
1077                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1078                 ew32(CTRL_EXT, ctrl_ext);
1079                 e1e_flush();
1080         }
1081
1082         ret_val = e1000e_get_auto_rd_done(hw);
1083         if (ret_val)
1084                 /* We don't want to continue accessing MAC registers. */
1085                 return ret_val;
1086
1087         /*
1088          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1089          * Need to wait for Phy configuration completion before accessing
1090          * NVM and Phy.
1091          */
1092
1093         switch (hw->mac.type) {
1094         case e1000_82573:
1095         case e1000_82574:
1096         case e1000_82583:
1097                 msleep(25);
1098                 break;
1099         default:
1100                 break;
1101         }
1102
1103         /* Clear any pending interrupt events. */
1104         ew32(IMC, 0xffffffff);
1105         er32(ICR);
1106
1107         if (hw->mac.type == e1000_82571) {
1108                 /* Install any alternate MAC address into RAR0 */
1109                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1110                 if (ret_val)
1111                         return ret_val;
1112
1113                 e1000e_set_laa_state_82571(hw, true);
1114         }
1115
1116         /* Reinitialize the 82571 serdes link state machine */
1117         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1118                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1119
1120         return 0;
1121 }
1122
1123 /**
1124  *  e1000_init_hw_82571 - Initialize hardware
1125  *  @hw: pointer to the HW structure
1126  *
1127  *  This inits the hardware readying it for operation.
1128  **/
1129 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1130 {
1131         struct e1000_mac_info *mac = &hw->mac;
1132         u32 reg_data;
1133         s32 ret_val;
1134         u16 i, rar_count = mac->rar_entry_count;
1135
1136         e1000_initialize_hw_bits_82571(hw);
1137
1138         /* Initialize identification LED */
1139         ret_val = e1000e_id_led_init(hw);
1140         if (ret_val)
1141                 e_dbg("Error initializing identification LED\n");
1142                 /* This is not fatal and we should not stop init due to this */
1143
1144         /* Disabling VLAN filtering */
1145         e_dbg("Initializing the IEEE VLAN\n");
1146         mac->ops.clear_vfta(hw);
1147
1148         /* Setup the receive address. */
1149         /*
1150          * If, however, a locally administered address was assigned to the
1151          * 82571, we must reserve a RAR for it to work around an issue where
1152          * resetting one port will reload the MAC on the other port.
1153          */
1154         if (e1000e_get_laa_state_82571(hw))
1155                 rar_count--;
1156         e1000e_init_rx_addrs(hw, rar_count);
1157
1158         /* Zero out the Multicast HASH table */
1159         e_dbg("Zeroing the MTA\n");
1160         for (i = 0; i < mac->mta_reg_count; i++)
1161                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1162
1163         /* Setup link and flow control */
1164         ret_val = e1000_setup_link_82571(hw);
1165
1166         /* Set the transmit descriptor write-back policy */
1167         reg_data = er32(TXDCTL(0));
1168         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1169                    E1000_TXDCTL_FULL_TX_DESC_WB |
1170                    E1000_TXDCTL_COUNT_DESC;
1171         ew32(TXDCTL(0), reg_data);
1172
1173         /* ...for both queues. */
1174         switch (mac->type) {
1175         case e1000_82573:
1176                 e1000e_enable_tx_pkt_filtering(hw);
1177                 /* fall through */
1178         case e1000_82574:
1179         case e1000_82583:
1180                 reg_data = er32(GCR);
1181                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1182                 ew32(GCR, reg_data);
1183                 break;
1184         default:
1185                 reg_data = er32(TXDCTL(1));
1186                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1187                            E1000_TXDCTL_FULL_TX_DESC_WB |
1188                            E1000_TXDCTL_COUNT_DESC;
1189                 ew32(TXDCTL(1), reg_data);
1190                 break;
1191         }
1192
1193         /*
1194          * Clear all of the statistics registers (clear on read).  It is
1195          * important that we do this after we have tried to establish link
1196          * because the symbol error count will increment wildly if there
1197          * is no link.
1198          */
1199         e1000_clear_hw_cntrs_82571(hw);
1200
1201         return ret_val;
1202 }
1203
1204 /**
1205  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1206  *  @hw: pointer to the HW structure
1207  *
1208  *  Initializes required hardware-dependent bits needed for normal operation.
1209  **/
1210 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1211 {
1212         u32 reg;
1213
1214         /* Transmit Descriptor Control 0 */
1215         reg = er32(TXDCTL(0));
1216         reg |= (1 << 22);
1217         ew32(TXDCTL(0), reg);
1218
1219         /* Transmit Descriptor Control 1 */
1220         reg = er32(TXDCTL(1));
1221         reg |= (1 << 22);
1222         ew32(TXDCTL(1), reg);
1223
1224         /* Transmit Arbitration Control 0 */
1225         reg = er32(TARC(0));
1226         reg &= ~(0xF << 27); /* 30:27 */
1227         switch (hw->mac.type) {
1228         case e1000_82571:
1229         case e1000_82572:
1230                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1231                 break;
1232         default:
1233                 break;
1234         }
1235         ew32(TARC(0), reg);
1236
1237         /* Transmit Arbitration Control 1 */
1238         reg = er32(TARC(1));
1239         switch (hw->mac.type) {
1240         case e1000_82571:
1241         case e1000_82572:
1242                 reg &= ~((1 << 29) | (1 << 30));
1243                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1244                 if (er32(TCTL) & E1000_TCTL_MULR)
1245                         reg &= ~(1 << 28);
1246                 else
1247                         reg |= (1 << 28);
1248                 ew32(TARC(1), reg);
1249                 break;
1250         default:
1251                 break;
1252         }
1253
1254         /* Device Control */
1255         switch (hw->mac.type) {
1256         case e1000_82573:
1257         case e1000_82574:
1258         case e1000_82583:
1259                 reg = er32(CTRL);
1260                 reg &= ~(1 << 29);
1261                 ew32(CTRL, reg);
1262                 break;
1263         default:
1264                 break;
1265         }
1266
1267         /* Extended Device Control */
1268         switch (hw->mac.type) {
1269         case e1000_82573:
1270         case e1000_82574:
1271         case e1000_82583:
1272                 reg = er32(CTRL_EXT);
1273                 reg &= ~(1 << 23);
1274                 reg |= (1 << 22);
1275                 ew32(CTRL_EXT, reg);
1276                 break;
1277         default:
1278                 break;
1279         }
1280
1281         if (hw->mac.type == e1000_82571) {
1282                 reg = er32(PBA_ECC);
1283                 reg |= E1000_PBA_ECC_CORR_EN;
1284                 ew32(PBA_ECC, reg);
1285         }
1286         /*
1287          * Workaround for hardware errata.
1288          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1289          */
1290
1291         if ((hw->mac.type == e1000_82571) ||
1292            (hw->mac.type == e1000_82572)) {
1293                 reg = er32(CTRL_EXT);
1294                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1295                 ew32(CTRL_EXT, reg);
1296         }
1297
1298
1299         /* PCI-Ex Control Registers */
1300         switch (hw->mac.type) {
1301         case e1000_82574:
1302         case e1000_82583:
1303                 reg = er32(GCR);
1304                 reg |= (1 << 22);
1305                 ew32(GCR, reg);
1306
1307                 /*
1308                  * Workaround for hardware errata.
1309                  * apply workaround for hardware errata documented in errata
1310                  * docs Fixes issue where some error prone or unreliable PCIe
1311                  * completions are occurring, particularly with ASPM enabled.
1312                  * Without fix, issue can cause Tx timeouts.
1313                  */
1314                 reg = er32(GCR2);
1315                 reg |= 1;
1316                 ew32(GCR2, reg);
1317                 break;
1318         default:
1319                 break;
1320         }
1321 }
1322
1323 /**
1324  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1325  *  @hw: pointer to the HW structure
1326  *
1327  *  Clears the register array which contains the VLAN filter table by
1328  *  setting all the values to 0.
1329  **/
1330 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1331 {
1332         u32 offset;
1333         u32 vfta_value = 0;
1334         u32 vfta_offset = 0;
1335         u32 vfta_bit_in_reg = 0;
1336
1337         switch (hw->mac.type) {
1338         case e1000_82573:
1339         case e1000_82574:
1340         case e1000_82583:
1341                 if (hw->mng_cookie.vlan_id != 0) {
1342                         /*
1343                          * The VFTA is a 4096b bit-field, each identifying
1344                          * a single VLAN ID.  The following operations
1345                          * determine which 32b entry (i.e. offset) into the
1346                          * array we want to set the VLAN ID (i.e. bit) of
1347                          * the manageability unit.
1348                          */
1349                         vfta_offset = (hw->mng_cookie.vlan_id >>
1350                                        E1000_VFTA_ENTRY_SHIFT) &
1351                                       E1000_VFTA_ENTRY_MASK;
1352                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1353                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1354                 }
1355                 break;
1356         default:
1357                 break;
1358         }
1359         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1360                 /*
1361                  * If the offset we want to clear is the same offset of the
1362                  * manageability VLAN ID, then clear all bits except that of
1363                  * the manageability unit.
1364                  */
1365                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1366                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1367                 e1e_flush();
1368         }
1369 }
1370
1371 /**
1372  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1373  *  @hw: pointer to the HW structure
1374  *
1375  *  Reads the NVM Initialization Control Word 2 and returns true
1376  *  (>0) if any manageability is enabled, else false (0).
1377  **/
1378 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1379 {
1380         u16 data;
1381
1382         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1383         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1384 }
1385
1386 /**
1387  *  e1000_led_on_82574 - Turn LED on
1388  *  @hw: pointer to the HW structure
1389  *
1390  *  Turn LED on.
1391  **/
1392 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1393 {
1394         u32 ctrl;
1395         u32 i;
1396
1397         ctrl = hw->mac.ledctl_mode2;
1398         if (!(E1000_STATUS_LU & er32(STATUS))) {
1399                 /*
1400                  * If no link, then turn LED on by setting the invert bit
1401                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1402                  */
1403                 for (i = 0; i < 4; i++)
1404                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1405                             E1000_LEDCTL_MODE_LED_ON)
1406                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1407         }
1408         ew32(LEDCTL, ctrl);
1409
1410         return 0;
1411 }
1412
1413 /**
1414  *  e1000_check_phy_82574 - check 82574 phy hung state
1415  *  @hw: pointer to the HW structure
1416  *
1417  *  Returns whether phy is hung or not
1418  **/
1419 bool e1000_check_phy_82574(struct e1000_hw *hw)
1420 {
1421         u16 status_1kbt = 0;
1422         u16 receive_errors = 0;
1423         bool phy_hung = false;
1424         s32 ret_val = 0;
1425
1426         /*
1427          * Read PHY Receive Error counter first, if its is max - all F's then
1428          * read the Base1000T status register If both are max then PHY is hung.
1429          */
1430         ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1431
1432         if (ret_val)
1433                 goto out;
1434         if (receive_errors == E1000_RECEIVE_ERROR_MAX)  {
1435                 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1436                 if (ret_val)
1437                         goto out;
1438                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1439                     E1000_IDLE_ERROR_COUNT_MASK)
1440                         phy_hung = true;
1441         }
1442 out:
1443         return phy_hung;
1444 }
1445
1446 /**
1447  *  e1000_setup_link_82571 - Setup flow control and link settings
1448  *  @hw: pointer to the HW structure
1449  *
1450  *  Determines which flow control settings to use, then configures flow
1451  *  control.  Calls the appropriate media-specific link configuration
1452  *  function.  Assuming the adapter has a valid link partner, a valid link
1453  *  should be established.  Assumes the hardware has previously been reset
1454  *  and the transmitter and receiver are not enabled.
1455  **/
1456 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1457 {
1458         /*
1459          * 82573 does not have a word in the NVM to determine
1460          * the default flow control setting, so we explicitly
1461          * set it to full.
1462          */
1463         switch (hw->mac.type) {
1464         case e1000_82573:
1465         case e1000_82574:
1466         case e1000_82583:
1467                 if (hw->fc.requested_mode == e1000_fc_default)
1468                         hw->fc.requested_mode = e1000_fc_full;
1469                 break;
1470         default:
1471                 break;
1472         }
1473
1474         return e1000e_setup_link(hw);
1475 }
1476
1477 /**
1478  *  e1000_setup_copper_link_82571 - Configure copper link settings
1479  *  @hw: pointer to the HW structure
1480  *
1481  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1482  *  for link, once link is established calls to configure collision distance
1483  *  and flow control are called.
1484  **/
1485 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1486 {
1487         u32 ctrl;
1488         s32 ret_val;
1489
1490         ctrl = er32(CTRL);
1491         ctrl |= E1000_CTRL_SLU;
1492         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1493         ew32(CTRL, ctrl);
1494
1495         switch (hw->phy.type) {
1496         case e1000_phy_m88:
1497         case e1000_phy_bm:
1498                 ret_val = e1000e_copper_link_setup_m88(hw);
1499                 break;
1500         case e1000_phy_igp_2:
1501                 ret_val = e1000e_copper_link_setup_igp(hw);
1502                 break;
1503         default:
1504                 return -E1000_ERR_PHY;
1505                 break;
1506         }
1507
1508         if (ret_val)
1509                 return ret_val;
1510
1511         ret_val = e1000e_setup_copper_link(hw);
1512
1513         return ret_val;
1514 }
1515
1516 /**
1517  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1518  *  @hw: pointer to the HW structure
1519  *
1520  *  Configures collision distance and flow control for fiber and serdes links.
1521  *  Upon successful setup, poll for link.
1522  **/
1523 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1524 {
1525         switch (hw->mac.type) {
1526         case e1000_82571:
1527         case e1000_82572:
1528                 /*
1529                  * If SerDes loopback mode is entered, there is no form
1530                  * of reset to take the adapter out of that mode.  So we
1531                  * have to explicitly take the adapter out of loopback
1532                  * mode.  This prevents drivers from twiddling their thumbs
1533                  * if another tool failed to take it out of loopback mode.
1534                  */
1535                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1536                 break;
1537         default:
1538                 break;
1539         }
1540
1541         return e1000e_setup_fiber_serdes_link(hw);
1542 }
1543
1544 /**
1545  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1546  *  @hw: pointer to the HW structure
1547  *
1548  *  Reports the link state as up or down.
1549  *
1550  *  If autonegotiation is supported by the link partner, the link state is
1551  *  determined by the result of autonegotiation. This is the most likely case.
1552  *  If autonegotiation is not supported by the link partner, and the link
1553  *  has a valid signal, force the link up.
1554  *
1555  *  The link state is represented internally here by 4 states:
1556  *
1557  *  1) down
1558  *  2) autoneg_progress
1559  *  3) autoneg_complete (the link successfully autonegotiated)
1560  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1561  *
1562  **/
1563 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1564 {
1565         struct e1000_mac_info *mac = &hw->mac;
1566         u32 rxcw;
1567         u32 ctrl;
1568         u32 status;
1569         u32 txcw;
1570         u32 i;
1571         s32 ret_val = 0;
1572
1573         ctrl = er32(CTRL);
1574         status = er32(STATUS);
1575         rxcw = er32(RXCW);
1576
1577         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1578
1579                 /* Receiver is synchronized with no invalid bits.  */
1580                 switch (mac->serdes_link_state) {
1581                 case e1000_serdes_link_autoneg_complete:
1582                         if (!(status & E1000_STATUS_LU)) {
1583                                 /*
1584                                  * We have lost link, retry autoneg before
1585                                  * reporting link failure
1586                                  */
1587                                 mac->serdes_link_state =
1588                                     e1000_serdes_link_autoneg_progress;
1589                                 mac->serdes_has_link = false;
1590                                 e_dbg("AN_UP     -> AN_PROG\n");
1591                         } else {
1592                                 mac->serdes_has_link = true;
1593                         }
1594                         break;
1595
1596                 case e1000_serdes_link_forced_up:
1597                         /*
1598                          * If we are receiving /C/ ordered sets, re-enable
1599                          * auto-negotiation in the TXCW register and disable
1600                          * forced link in the Device Control register in an
1601                          * attempt to auto-negotiate with our link partner.
1602                          * If the partner code word is null, stop forcing
1603                          * and restart auto negotiation.
1604                          */
1605                         if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
1606                                 /* Enable autoneg, and unforce link up */
1607                                 ew32(TXCW, mac->txcw);
1608                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1609                                 mac->serdes_link_state =
1610                                     e1000_serdes_link_autoneg_progress;
1611                                 mac->serdes_has_link = false;
1612                                 e_dbg("FORCED_UP -> AN_PROG\n");
1613                         } else {
1614                                 mac->serdes_has_link = true;
1615                         }
1616                         break;
1617
1618                 case e1000_serdes_link_autoneg_progress:
1619                         if (rxcw & E1000_RXCW_C) {
1620                                 /*
1621                                  * We received /C/ ordered sets, meaning the
1622                                  * link partner has autonegotiated, and we can
1623                                  * trust the Link Up (LU) status bit.
1624                                  */
1625                                 if (status & E1000_STATUS_LU) {
1626                                         mac->serdes_link_state =
1627                                             e1000_serdes_link_autoneg_complete;
1628                                         e_dbg("AN_PROG   -> AN_UP\n");
1629                                         mac->serdes_has_link = true;
1630                                 } else {
1631                                         /* Autoneg completed, but failed. */
1632                                         mac->serdes_link_state =
1633                                             e1000_serdes_link_down;
1634                                         e_dbg("AN_PROG   -> DOWN\n");
1635                                 }
1636                         } else {
1637                                 /*
1638                                  * The link partner did not autoneg.
1639                                  * Force link up and full duplex, and change
1640                                  * state to forced.
1641                                  */
1642                                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1643                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1644                                 ew32(CTRL, ctrl);
1645
1646                                 /* Configure Flow Control after link up. */
1647                                 ret_val = e1000e_config_fc_after_link_up(hw);
1648                                 if (ret_val) {
1649                                         e_dbg("Error config flow control\n");
1650                                         break;
1651                                 }
1652                                 mac->serdes_link_state =
1653                                     e1000_serdes_link_forced_up;
1654                                 mac->serdes_has_link = true;
1655                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1656                         }
1657                         break;
1658
1659                 case e1000_serdes_link_down:
1660                 default:
1661                         /*
1662                          * The link was down but the receiver has now gained
1663                          * valid sync, so lets see if we can bring the link
1664                          * up.
1665                          */
1666                         ew32(TXCW, mac->txcw);
1667                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1668                         mac->serdes_link_state =
1669                             e1000_serdes_link_autoneg_progress;
1670                         mac->serdes_has_link = false;
1671                         e_dbg("DOWN      -> AN_PROG\n");
1672                         break;
1673                 }
1674         } else {
1675                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1676                         mac->serdes_has_link = false;
1677                         mac->serdes_link_state = e1000_serdes_link_down;
1678                         e_dbg("ANYSTATE  -> DOWN\n");
1679                 } else {
1680                         /*
1681                          * Check several times, if Sync and Config
1682                          * both are consistently 1 then simply ignore
1683                          * the Invalid bit and restart Autoneg
1684                          */
1685                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1686                                 udelay(10);
1687                                 rxcw = er32(RXCW);
1688                                 if ((rxcw & E1000_RXCW_IV) &&
1689                                     !((rxcw & E1000_RXCW_SYNCH) &&
1690                                       (rxcw & E1000_RXCW_C))) {
1691                                         mac->serdes_has_link = false;
1692                                         mac->serdes_link_state =
1693                                             e1000_serdes_link_down;
1694                                         e_dbg("ANYSTATE  -> DOWN\n");
1695                                         break;
1696                                 }
1697                         }
1698
1699                         if (i == AN_RETRY_COUNT) {
1700                                 txcw = er32(TXCW);
1701                                 txcw |= E1000_TXCW_ANE;
1702                                 ew32(TXCW, txcw);
1703                                 mac->serdes_link_state =
1704                                     e1000_serdes_link_autoneg_progress;
1705                                 mac->serdes_has_link = false;
1706                                 e_dbg("ANYSTATE  -> AN_PROG\n");
1707                         }
1708                 }
1709         }
1710
1711         return ret_val;
1712 }
1713
1714 /**
1715  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1716  *  @hw: pointer to the HW structure
1717  *  @data: pointer to the NVM (EEPROM)
1718  *
1719  *  Read the EEPROM for the current default LED configuration.  If the
1720  *  LED configuration is not valid, set to a valid LED configuration.
1721  **/
1722 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1723 {
1724         s32 ret_val;
1725
1726         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1727         if (ret_val) {
1728                 e_dbg("NVM Read Error\n");
1729                 return ret_val;
1730         }
1731
1732         switch (hw->mac.type) {
1733         case e1000_82573:
1734         case e1000_82574:
1735         case e1000_82583:
1736                 if (*data == ID_LED_RESERVED_F746)
1737                         *data = ID_LED_DEFAULT_82573;
1738                 break;
1739         default:
1740                 if (*data == ID_LED_RESERVED_0000 ||
1741                     *data == ID_LED_RESERVED_FFFF)
1742                         *data = ID_LED_DEFAULT;
1743                 break;
1744         }
1745
1746         return 0;
1747 }
1748
1749 /**
1750  *  e1000e_get_laa_state_82571 - Get locally administered address state
1751  *  @hw: pointer to the HW structure
1752  *
1753  *  Retrieve and return the current locally administered address state.
1754  **/
1755 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1756 {
1757         if (hw->mac.type != e1000_82571)
1758                 return false;
1759
1760         return hw->dev_spec.e82571.laa_is_present;
1761 }
1762
1763 /**
1764  *  e1000e_set_laa_state_82571 - Set locally administered address state
1765  *  @hw: pointer to the HW structure
1766  *  @state: enable/disable locally administered address
1767  *
1768  *  Enable/Disable the current locally administered address state.
1769  **/
1770 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1771 {
1772         if (hw->mac.type != e1000_82571)
1773                 return;
1774
1775         hw->dev_spec.e82571.laa_is_present = state;
1776
1777         /* If workaround is activated... */
1778         if (state)
1779                 /*
1780                  * Hold a copy of the LAA in RAR[14] This is done so that
1781                  * between the time RAR[0] gets clobbered and the time it
1782                  * gets fixed, the actual LAA is in one of the RARs and no
1783                  * incoming packets directed to this port are dropped.
1784                  * Eventually the LAA will be in RAR[0] and RAR[14].
1785                  */
1786                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1787 }
1788
1789 /**
1790  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1791  *  @hw: pointer to the HW structure
1792  *
1793  *  Verifies that the EEPROM has completed the update.  After updating the
1794  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1795  *  the checksum fix is not implemented, we need to set the bit and update
1796  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1797  *  we need to return bad checksum.
1798  **/
1799 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1800 {
1801         struct e1000_nvm_info *nvm = &hw->nvm;
1802         s32 ret_val;
1803         u16 data;
1804
1805         if (nvm->type != e1000_nvm_flash_hw)
1806                 return 0;
1807
1808         /*
1809          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1810          * 10h-12h.  Checksum may need to be fixed.
1811          */
1812         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1813         if (ret_val)
1814                 return ret_val;
1815
1816         if (!(data & 0x10)) {
1817                 /*
1818                  * Read 0x23 and check bit 15.  This bit is a 1
1819                  * when the checksum has already been fixed.  If
1820                  * the checksum is still wrong and this bit is a
1821                  * 1, we need to return bad checksum.  Otherwise,
1822                  * we need to set this bit to a 1 and update the
1823                  * checksum.
1824                  */
1825                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1826                 if (ret_val)
1827                         return ret_val;
1828
1829                 if (!(data & 0x8000)) {
1830                         data |= 0x8000;
1831                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1832                         if (ret_val)
1833                                 return ret_val;
1834                         ret_val = e1000e_update_nvm_checksum(hw);
1835                 }
1836         }
1837
1838         return 0;
1839 }
1840
1841 /**
1842  *  e1000_read_mac_addr_82571 - Read device MAC address
1843  *  @hw: pointer to the HW structure
1844  **/
1845 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1846 {
1847         s32 ret_val = 0;
1848
1849         if (hw->mac.type == e1000_82571) {
1850                 /*
1851                  * If there's an alternate MAC address place it in RAR0
1852                  * so that it will override the Si installed default perm
1853                  * address.
1854                  */
1855                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1856                 if (ret_val)
1857                         goto out;
1858         }
1859
1860         ret_val = e1000_read_mac_addr_generic(hw);
1861
1862 out:
1863         return ret_val;
1864 }
1865
1866 /**
1867  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1868  * @hw: pointer to the HW structure
1869  *
1870  * In the case of a PHY power down to save power, or to turn off link during a
1871  * driver unload, or wake on lan is not enabled, remove the link.
1872  **/
1873 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1874 {
1875         struct e1000_phy_info *phy = &hw->phy;
1876         struct e1000_mac_info *mac = &hw->mac;
1877
1878         if (!(phy->ops.check_reset_block))
1879                 return;
1880
1881         /* If the management interface is not enabled, then power down */
1882         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1883                 e1000_power_down_phy_copper(hw);
1884 }
1885
1886 /**
1887  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1888  *  @hw: pointer to the HW structure
1889  *
1890  *  Clears the hardware counters by reading the counter registers.
1891  **/
1892 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1893 {
1894         e1000e_clear_hw_cntrs_base(hw);
1895
1896         er32(PRC64);
1897         er32(PRC127);
1898         er32(PRC255);
1899         er32(PRC511);
1900         er32(PRC1023);
1901         er32(PRC1522);
1902         er32(PTC64);
1903         er32(PTC127);
1904         er32(PTC255);
1905         er32(PTC511);
1906         er32(PTC1023);
1907         er32(PTC1522);
1908
1909         er32(ALGNERRC);
1910         er32(RXERRC);
1911         er32(TNCRS);
1912         er32(CEXTERR);
1913         er32(TSCTC);
1914         er32(TSCTFC);
1915
1916         er32(MGTPRC);
1917         er32(MGTPDC);
1918         er32(MGTPTC);
1919
1920         er32(IAC);
1921         er32(ICRXOC);
1922
1923         er32(ICRXPTC);
1924         er32(ICRXATC);
1925         er32(ICTXPTC);
1926         er32(ICTXATC);
1927         er32(ICTXQEC);
1928         er32(ICTXQMTC);
1929         er32(ICRXDMTC);
1930 }
1931
1932 static struct e1000_mac_operations e82571_mac_ops = {
1933         /* .check_mng_mode: mac type dependent */
1934         /* .check_for_link: media type dependent */
1935         .id_led_init            = e1000e_id_led_init,
1936         .cleanup_led            = e1000e_cleanup_led_generic,
1937         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1938         .get_bus_info           = e1000e_get_bus_info_pcie,
1939         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1940         /* .get_link_up_info: media type dependent */
1941         /* .led_on: mac type dependent */
1942         .led_off                = e1000e_led_off_generic,
1943         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1944         .write_vfta             = e1000_write_vfta_generic,
1945         .clear_vfta             = e1000_clear_vfta_82571,
1946         .reset_hw               = e1000_reset_hw_82571,
1947         .init_hw                = e1000_init_hw_82571,
1948         .setup_link             = e1000_setup_link_82571,
1949         /* .setup_physical_interface: media type dependent */
1950         .setup_led              = e1000e_setup_led_generic,
1951         .read_mac_addr          = e1000_read_mac_addr_82571,
1952 };
1953
1954 static struct e1000_phy_operations e82_phy_ops_igp = {
1955         .acquire                = e1000_get_hw_semaphore_82571,
1956         .check_polarity         = e1000_check_polarity_igp,
1957         .check_reset_block      = e1000e_check_reset_block_generic,
1958         .commit                 = NULL,
1959         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1960         .get_cfg_done           = e1000_get_cfg_done_82571,
1961         .get_cable_length       = e1000e_get_cable_length_igp_2,
1962         .get_info               = e1000e_get_phy_info_igp,
1963         .read_reg               = e1000e_read_phy_reg_igp,
1964         .release                = e1000_put_hw_semaphore_82571,
1965         .reset                  = e1000e_phy_hw_reset_generic,
1966         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1967         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1968         .write_reg              = e1000e_write_phy_reg_igp,
1969         .cfg_on_link_up         = NULL,
1970 };
1971
1972 static struct e1000_phy_operations e82_phy_ops_m88 = {
1973         .acquire                = e1000_get_hw_semaphore_82571,
1974         .check_polarity         = e1000_check_polarity_m88,
1975         .check_reset_block      = e1000e_check_reset_block_generic,
1976         .commit                 = e1000e_phy_sw_reset,
1977         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1978         .get_cfg_done           = e1000e_get_cfg_done,
1979         .get_cable_length       = e1000e_get_cable_length_m88,
1980         .get_info               = e1000e_get_phy_info_m88,
1981         .read_reg               = e1000e_read_phy_reg_m88,
1982         .release                = e1000_put_hw_semaphore_82571,
1983         .reset                  = e1000e_phy_hw_reset_generic,
1984         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1985         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1986         .write_reg              = e1000e_write_phy_reg_m88,
1987         .cfg_on_link_up         = NULL,
1988 };
1989
1990 static struct e1000_phy_operations e82_phy_ops_bm = {
1991         .acquire                = e1000_get_hw_semaphore_82571,
1992         .check_polarity         = e1000_check_polarity_m88,
1993         .check_reset_block      = e1000e_check_reset_block_generic,
1994         .commit                 = e1000e_phy_sw_reset,
1995         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1996         .get_cfg_done           = e1000e_get_cfg_done,
1997         .get_cable_length       = e1000e_get_cable_length_m88,
1998         .get_info               = e1000e_get_phy_info_m88,
1999         .read_reg               = e1000e_read_phy_reg_bm2,
2000         .release                = e1000_put_hw_semaphore_82571,
2001         .reset                  = e1000e_phy_hw_reset_generic,
2002         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
2003         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
2004         .write_reg              = e1000e_write_phy_reg_bm2,
2005         .cfg_on_link_up         = NULL,
2006 };
2007
2008 static struct e1000_nvm_operations e82571_nvm_ops = {
2009         .acquire                = e1000_acquire_nvm_82571,
2010         .read                   = e1000e_read_nvm_eerd,
2011         .release                = e1000_release_nvm_82571,
2012         .update                 = e1000_update_nvm_checksum_82571,
2013         .valid_led_default      = e1000_valid_led_default_82571,
2014         .validate               = e1000_validate_nvm_checksum_82571,
2015         .write                  = e1000_write_nvm_82571,
2016 };
2017
2018 struct e1000_info e1000_82571_info = {
2019         .mac                    = e1000_82571,
2020         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2021                                   | FLAG_HAS_JUMBO_FRAMES
2022                                   | FLAG_HAS_WOL
2023                                   | FLAG_APME_IN_CTRL3
2024                                   | FLAG_RX_CSUM_ENABLED
2025                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2026                                   | FLAG_HAS_SMART_POWER_DOWN
2027                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
2028                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
2029                                   | FLAG_APME_CHECK_PORT_B,
2030         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2031                                   | FLAG2_DMA_BURST,
2032         .pba                    = 38,
2033         .max_hw_frame_size      = DEFAULT_JUMBO,
2034         .get_variants           = e1000_get_variants_82571,
2035         .mac_ops                = &e82571_mac_ops,
2036         .phy_ops                = &e82_phy_ops_igp,
2037         .nvm_ops                = &e82571_nvm_ops,
2038 };
2039
2040 struct e1000_info e1000_82572_info = {
2041         .mac                    = e1000_82572,
2042         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2043                                   | FLAG_HAS_JUMBO_FRAMES
2044                                   | FLAG_HAS_WOL
2045                                   | FLAG_APME_IN_CTRL3
2046                                   | FLAG_RX_CSUM_ENABLED
2047                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2048                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
2049         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2050                                   | FLAG2_DMA_BURST,
2051         .pba                    = 38,
2052         .max_hw_frame_size      = DEFAULT_JUMBO,
2053         .get_variants           = e1000_get_variants_82571,
2054         .mac_ops                = &e82571_mac_ops,
2055         .phy_ops                = &e82_phy_ops_igp,
2056         .nvm_ops                = &e82571_nvm_ops,
2057 };
2058
2059 struct e1000_info e1000_82573_info = {
2060         .mac                    = e1000_82573,
2061         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2062                                   | FLAG_HAS_WOL
2063                                   | FLAG_APME_IN_CTRL3
2064                                   | FLAG_RX_CSUM_ENABLED
2065                                   | FLAG_HAS_SMART_POWER_DOWN
2066                                   | FLAG_HAS_AMT
2067                                   | FLAG_HAS_SWSM_ON_LOAD,
2068         .flags2                 = FLAG2_DISABLE_ASPM_L1
2069                                   | FLAG2_DISABLE_ASPM_L0S,
2070         .pba                    = 20,
2071         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
2072         .get_variants           = e1000_get_variants_82571,
2073         .mac_ops                = &e82571_mac_ops,
2074         .phy_ops                = &e82_phy_ops_m88,
2075         .nvm_ops                = &e82571_nvm_ops,
2076 };
2077
2078 struct e1000_info e1000_82574_info = {
2079         .mac                    = e1000_82574,
2080         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2081                                   | FLAG_HAS_MSIX
2082                                   | FLAG_HAS_JUMBO_FRAMES
2083                                   | FLAG_HAS_WOL
2084                                   | FLAG_APME_IN_CTRL3
2085                                   | FLAG_RX_CSUM_ENABLED
2086                                   | FLAG_HAS_SMART_POWER_DOWN
2087                                   | FLAG_HAS_AMT
2088                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2089         .flags2                   = FLAG2_CHECK_PHY_HANG
2090                                   | FLAG2_DISABLE_ASPM_L0S,
2091         .pba                    = 32,
2092         .max_hw_frame_size      = DEFAULT_JUMBO,
2093         .get_variants           = e1000_get_variants_82571,
2094         .mac_ops                = &e82571_mac_ops,
2095         .phy_ops                = &e82_phy_ops_bm,
2096         .nvm_ops                = &e82571_nvm_ops,
2097 };
2098
2099 struct e1000_info e1000_82583_info = {
2100         .mac                    = e1000_82583,
2101         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2102                                   | FLAG_HAS_WOL
2103                                   | FLAG_APME_IN_CTRL3
2104                                   | FLAG_RX_CSUM_ENABLED
2105                                   | FLAG_HAS_SMART_POWER_DOWN
2106                                   | FLAG_HAS_AMT
2107                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2108         .flags2                 = FLAG2_DISABLE_ASPM_L0S,
2109         .pba                    = 32,
2110         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
2111         .get_variants           = e1000_get_variants_82571,
2112         .mac_ops                = &e82571_mac_ops,
2113         .phy_ops                = &e82_phy_ops_bm,
2114         .nvm_ops                = &e82571_nvm_ops,
2115 };
2116