1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
63 u16 words, u16 *data);
64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
75 * e1000_init_phy_params_82571 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
80 struct e1000_phy_info *phy = &hw->phy;
83 if (hw->phy.media_type != e1000_media_type_copper) {
84 phy->type = e1000_phy_none;
89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
90 phy->reset_delay_us = 100;
92 phy->ops.power_up = e1000_power_up_phy_copper;
93 phy->ops.power_down = e1000_power_down_phy_copper_82571;
95 switch (hw->mac.type) {
98 phy->type = e1000_phy_igp_2;
101 phy->type = e1000_phy_m88;
105 phy->type = e1000_phy_bm;
108 return -E1000_ERR_PHY;
112 /* This can only be done after all function pointers are setup. */
113 ret_val = e1000_get_phy_id_82571(hw);
116 switch (hw->mac.type) {
119 if (phy->id != IGP01E1000_I_PHY_ID)
120 return -E1000_ERR_PHY;
123 if (phy->id != M88E1111_I_PHY_ID)
124 return -E1000_ERR_PHY;
128 if (phy->id != BME1000_E_PHY_ID_R2)
129 return -E1000_ERR_PHY;
132 return -E1000_ERR_PHY;
140 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
141 * @hw: pointer to the HW structure
143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
145 struct e1000_nvm_info *nvm = &hw->nvm;
146 u32 eecd = er32(EECD);
149 nvm->opcode_bits = 8;
151 switch (nvm->override) {
152 case e1000_nvm_override_spi_large:
154 nvm->address_bits = 16;
156 case e1000_nvm_override_spi_small:
158 nvm->address_bits = 8;
161 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
162 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
166 switch (hw->mac.type) {
170 if (((eecd >> 15) & 0x3) == 0x3) {
171 nvm->type = e1000_nvm_flash_hw;
172 nvm->word_size = 2048;
174 * Autonomous Flash update bit must be cleared due
175 * to Flash update issue.
177 eecd &= ~E1000_EECD_AUPDEN;
183 nvm->type = e1000_nvm_eeprom_spi;
184 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
185 E1000_EECD_SIZE_EX_SHIFT);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size += NVM_WORD_SIZE_BASE_SHIFT;
192 /* EEPROM access above 16k is unsupported */
195 nvm->word_size = 1 << size;
203 * e1000_init_mac_params_82571 - Init MAC func ptrs.
204 * @hw: pointer to the HW structure
206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_mac_info *mac = &hw->mac;
210 struct e1000_mac_operations *func = &mac->ops;
213 bool force_clear_smbi = false;
216 switch (adapter->pdev->device) {
217 case E1000_DEV_ID_82571EB_FIBER:
218 case E1000_DEV_ID_82572EI_FIBER:
219 case E1000_DEV_ID_82571EB_QUAD_FIBER:
220 hw->phy.media_type = e1000_media_type_fiber;
222 case E1000_DEV_ID_82571EB_SERDES:
223 case E1000_DEV_ID_82572EI_SERDES:
224 case E1000_DEV_ID_82571EB_SERDES_DUAL:
225 case E1000_DEV_ID_82571EB_SERDES_QUAD:
226 hw->phy.media_type = e1000_media_type_internal_serdes;
229 hw->phy.media_type = e1000_media_type_copper;
233 /* Set mta register count */
234 mac->mta_reg_count = 128;
235 /* Set rar entry count */
236 mac->rar_entry_count = E1000_RAR_ENTRIES;
237 /* Set if manageability features are enabled. */
238 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
240 /* Adaptive IFS supported */
241 mac->adaptive_ifs = true;
244 switch (hw->phy.media_type) {
245 case e1000_media_type_copper:
246 func->setup_physical_interface = e1000_setup_copper_link_82571;
247 func->check_for_link = e1000e_check_for_copper_link;
248 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
250 case e1000_media_type_fiber:
251 func->setup_physical_interface =
252 e1000_setup_fiber_serdes_link_82571;
253 func->check_for_link = e1000e_check_for_fiber_link;
254 func->get_link_up_info =
255 e1000e_get_speed_and_duplex_fiber_serdes;
257 case e1000_media_type_internal_serdes:
258 func->setup_physical_interface =
259 e1000_setup_fiber_serdes_link_82571;
260 func->check_for_link = e1000_check_for_serdes_link_82571;
261 func->get_link_up_info =
262 e1000e_get_speed_and_duplex_fiber_serdes;
265 return -E1000_ERR_CONFIG;
269 switch (hw->mac.type) {
272 func->check_mng_mode = e1000_check_mng_mode_82574;
273 func->led_on = e1000_led_on_82574;
276 func->check_mng_mode = e1000e_check_mng_mode_generic;
277 func->led_on = e1000e_led_on_generic;
282 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
283 * first NVM or PHY acess. This should be done for single-port
284 * devices, and for one port only on dual-port devices so that
285 * for those devices we can still use the SMBI lock to synchronize
286 * inter-port accesses to the PHY & NVM.
288 switch (hw->mac.type) {
293 if (!(swsm2 & E1000_SWSM2_LOCK)) {
294 /* Only do this for the first interface on this card */
296 swsm2 | E1000_SWSM2_LOCK);
297 force_clear_smbi = true;
299 force_clear_smbi = false;
302 force_clear_smbi = true;
306 if (force_clear_smbi) {
307 /* Make sure SWSM.SMBI is clear */
309 if (swsm & E1000_SWSM_SMBI) {
310 /* This bit should not be set on a first interface, and
311 * indicates that the bootagent or EFI code has
312 * improperly left this bit enabled
314 e_dbg("Please update your 82571 Bootagent\n");
316 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
320 * Initialze device specific counter of SMBI acquisition
323 hw->dev_spec.e82571.smb_counter = 0;
328 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
330 struct e1000_hw *hw = &adapter->hw;
331 static int global_quad_port_a; /* global port a indication */
332 struct pci_dev *pdev = adapter->pdev;
334 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
337 rc = e1000_init_mac_params_82571(adapter);
341 rc = e1000_init_nvm_params_82571(hw);
345 rc = e1000_init_phy_params_82571(hw);
349 /* tag quad port adapters first, it's used below */
350 switch (pdev->device) {
351 case E1000_DEV_ID_82571EB_QUAD_COPPER:
352 case E1000_DEV_ID_82571EB_QUAD_FIBER:
353 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
354 case E1000_DEV_ID_82571PT_QUAD_COPPER:
355 adapter->flags |= FLAG_IS_QUAD_PORT;
356 /* mark the first port */
357 if (global_quad_port_a == 0)
358 adapter->flags |= FLAG_IS_QUAD_PORT_A;
359 /* Reset for multiple quad port adapters */
360 global_quad_port_a++;
361 if (global_quad_port_a == 4)
362 global_quad_port_a = 0;
368 switch (adapter->hw.mac.type) {
370 /* these dual ports don't have WoL on port B at all */
371 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
372 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
373 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
375 adapter->flags &= ~FLAG_HAS_WOL;
376 /* quad ports only support WoL on port A */
377 if (adapter->flags & FLAG_IS_QUAD_PORT &&
378 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
379 adapter->flags &= ~FLAG_HAS_WOL;
380 /* Does not support WoL on any port */
381 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
382 adapter->flags &= ~FLAG_HAS_WOL;
386 if (pdev->device == E1000_DEV_ID_82573L) {
387 if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
390 if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
391 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
392 adapter->max_hw_frame_size = DEFAULT_JUMBO;
404 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
405 * @hw: pointer to the HW structure
407 * Reads the PHY registers and stores the PHY ID and possibly the PHY
408 * revision in the hardware structure.
410 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
412 struct e1000_phy_info *phy = &hw->phy;
416 switch (hw->mac.type) {
420 * The 82571 firmware may still be configuring the PHY.
421 * In this case, we cannot access the PHY until the
422 * configuration is done. So we explicitly set the
425 phy->id = IGP01E1000_I_PHY_ID;
428 return e1000e_get_phy_id(hw);
432 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
436 phy->id = (u32)(phy_id << 16);
438 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
442 phy->id |= (u32)(phy_id);
443 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
446 return -E1000_ERR_PHY;
454 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
455 * @hw: pointer to the HW structure
457 * Acquire the HW semaphore to access the PHY or NVM
459 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
462 s32 sw_timeout = hw->nvm.word_size + 1;
463 s32 fw_timeout = hw->nvm.word_size + 1;
467 * If we have timedout 3 times on trying to acquire
468 * the inter-port SMBI semaphore, there is old code
469 * operating on the other port, and it is not
470 * releasing SMBI. Modify the number of times that
471 * we try for the semaphore to interwork with this
474 if (hw->dev_spec.e82571.smb_counter > 2)
477 /* Get the SW semaphore */
478 while (i < sw_timeout) {
480 if (!(swsm & E1000_SWSM_SMBI))
487 if (i == sw_timeout) {
488 e_dbg("Driver can't access device - SMBI bit is set.\n");
489 hw->dev_spec.e82571.smb_counter++;
491 /* Get the FW semaphore. */
492 for (i = 0; i < fw_timeout; i++) {
494 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
496 /* Semaphore acquired if bit latched */
497 if (er32(SWSM) & E1000_SWSM_SWESMBI)
503 if (i == fw_timeout) {
504 /* Release semaphores */
505 e1000_put_hw_semaphore_82571(hw);
506 e_dbg("Driver can't access the NVM\n");
507 return -E1000_ERR_NVM;
514 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
515 * @hw: pointer to the HW structure
517 * Release hardware semaphore used to access the PHY or NVM
519 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
524 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
529 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
530 * @hw: pointer to the HW structure
532 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
533 * Then for non-82573 hardware, set the EEPROM access request bit and wait
534 * for EEPROM access grant bit. If the access grant bit is not set, release
535 * hardware semaphore.
537 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
541 ret_val = e1000_get_hw_semaphore_82571(hw);
545 switch (hw->mac.type) {
551 ret_val = e1000e_acquire_nvm(hw);
556 e1000_put_hw_semaphore_82571(hw);
562 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
563 * @hw: pointer to the HW structure
565 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
567 static void e1000_release_nvm_82571(struct e1000_hw *hw)
569 e1000e_release_nvm(hw);
570 e1000_put_hw_semaphore_82571(hw);
574 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
575 * @hw: pointer to the HW structure
576 * @offset: offset within the EEPROM to be written to
577 * @words: number of words to write
578 * @data: 16 bit word(s) to be written to the EEPROM
580 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
582 * If e1000e_update_nvm_checksum is not called after this function, the
583 * EEPROM will most likely contain an invalid checksum.
585 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
590 switch (hw->mac.type) {
594 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
598 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
601 ret_val = -E1000_ERR_NVM;
609 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
610 * @hw: pointer to the HW structure
612 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
613 * up to the checksum. Then calculates the EEPROM checksum and writes the
614 * value to the EEPROM.
616 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
622 ret_val = e1000e_update_nvm_checksum_generic(hw);
627 * If our nvm is an EEPROM, then we're done
628 * otherwise, commit the checksum to the flash NVM.
630 if (hw->nvm.type != e1000_nvm_flash_hw)
633 /* Check for pending operations. */
634 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
636 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
640 if (i == E1000_FLASH_UPDATES)
641 return -E1000_ERR_NVM;
643 /* Reset the firmware if using STM opcode. */
644 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
646 * The enabling of and the actual reset must be done
647 * in two write cycles.
649 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
651 ew32(HICR, E1000_HICR_FW_RESET);
654 /* Commit the write to flash */
655 eecd = er32(EECD) | E1000_EECD_FLUPD;
658 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
660 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
664 if (i == E1000_FLASH_UPDATES)
665 return -E1000_ERR_NVM;
671 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
672 * @hw: pointer to the HW structure
674 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
675 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
677 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
679 if (hw->nvm.type == e1000_nvm_flash_hw)
680 e1000_fix_nvm_checksum_82571(hw);
682 return e1000e_validate_nvm_checksum_generic(hw);
686 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
687 * @hw: pointer to the HW structure
688 * @offset: offset within the EEPROM to be written to
689 * @words: number of words to write
690 * @data: 16 bit word(s) to be written to the EEPROM
692 * After checking for invalid values, poll the EEPROM to ensure the previous
693 * command has completed before trying to write the next word. After write
694 * poll for completion.
696 * If e1000e_update_nvm_checksum is not called after this function, the
697 * EEPROM will most likely contain an invalid checksum.
699 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
700 u16 words, u16 *data)
702 struct e1000_nvm_info *nvm = &hw->nvm;
707 * A check for invalid values: offset too large, too many words,
708 * and not enough words.
710 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
712 e_dbg("nvm parameter(s) out of bounds\n");
713 return -E1000_ERR_NVM;
716 for (i = 0; i < words; i++) {
717 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
718 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
719 E1000_NVM_RW_REG_START;
721 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
727 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
736 * e1000_get_cfg_done_82571 - Poll for configuration done
737 * @hw: pointer to the HW structure
739 * Reads the management control register for the config done bit to be set.
741 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
743 s32 timeout = PHY_CFG_TIMEOUT;
747 E1000_NVM_CFG_DONE_PORT_0)
753 e_dbg("MNG configuration cycle has not completed.\n");
754 return -E1000_ERR_RESET;
761 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
762 * @hw: pointer to the HW structure
763 * @active: true to enable LPLU, false to disable
765 * Sets the LPLU D0 state according to the active flag. When activating LPLU
766 * this function also disables smart speed and vice versa. LPLU will not be
767 * activated unless the device autonegotiation advertisement meets standards
768 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
769 * pointer entry point only called by PHY setup routines.
771 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
773 struct e1000_phy_info *phy = &hw->phy;
777 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
782 data |= IGP02E1000_PM_D0_LPLU;
783 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
787 /* When LPLU is enabled, we should disable SmartSpeed */
788 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
789 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
790 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
794 data &= ~IGP02E1000_PM_D0_LPLU;
795 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
797 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
798 * during Dx states where the power conservation is most
799 * important. During driver activity we should enable
800 * SmartSpeed, so performance is maintained.
802 if (phy->smart_speed == e1000_smart_speed_on) {
803 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
808 data |= IGP01E1000_PSCFR_SMART_SPEED;
809 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
813 } else if (phy->smart_speed == e1000_smart_speed_off) {
814 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
819 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
820 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
831 * e1000_reset_hw_82571 - Reset hardware
832 * @hw: pointer to the HW structure
834 * This resets the hardware into a known state.
836 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
838 u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
843 * Prevent the PCI-E bus from sticking if there is no TLP connection
844 * on the last TLP read/write transaction when MAC is reset.
846 ret_val = e1000e_disable_pcie_master(hw);
848 e_dbg("PCI-E Master disable polling has failed.\n");
850 e_dbg("Masking off all interrupts\n");
851 ew32(IMC, 0xffffffff);
854 ew32(TCTL, E1000_TCTL_PSP);
860 * Must acquire the MDIO ownership before MAC reset.
861 * Ownership defaults to firmware after a reset.
863 switch (hw->mac.type) {
867 extcnf_ctrl = er32(EXTCNF_CTRL);
868 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
871 ew32(EXTCNF_CTRL, extcnf_ctrl);
872 extcnf_ctrl = er32(EXTCNF_CTRL);
874 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
877 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
881 } while (i < MDIO_OWNERSHIP_TIMEOUT);
889 e_dbg("Issuing a global reset to MAC\n");
890 ew32(CTRL, ctrl | E1000_CTRL_RST);
892 if (hw->nvm.type == e1000_nvm_flash_hw) {
894 ctrl_ext = er32(CTRL_EXT);
895 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
896 ew32(CTRL_EXT, ctrl_ext);
900 ret_val = e1000e_get_auto_rd_done(hw);
902 /* We don't want to continue accessing MAC registers. */
906 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
907 * Need to wait for Phy configuration completion before accessing
911 switch (hw->mac.type) {
921 /* Clear any pending interrupt events. */
922 ew32(IMC, 0xffffffff);
925 /* Install any alternate MAC address into RAR0 */
926 ret_val = e1000_check_alt_mac_addr_generic(hw);
930 e1000e_set_laa_state_82571(hw, true);
932 /* Reinitialize the 82571 serdes link state machine */
933 if (hw->phy.media_type == e1000_media_type_internal_serdes)
934 hw->mac.serdes_link_state = e1000_serdes_link_down;
940 * e1000_init_hw_82571 - Initialize hardware
941 * @hw: pointer to the HW structure
943 * This inits the hardware readying it for operation.
945 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
947 struct e1000_mac_info *mac = &hw->mac;
950 u16 i, rar_count = mac->rar_entry_count;
952 e1000_initialize_hw_bits_82571(hw);
954 /* Initialize identification LED */
955 ret_val = e1000e_id_led_init(hw);
957 e_dbg("Error initializing identification LED\n");
958 /* This is not fatal and we should not stop init due to this */
960 /* Disabling VLAN filtering */
961 e_dbg("Initializing the IEEE VLAN\n");
962 mac->ops.clear_vfta(hw);
964 /* Setup the receive address. */
966 * If, however, a locally administered address was assigned to the
967 * 82571, we must reserve a RAR for it to work around an issue where
968 * resetting one port will reload the MAC on the other port.
970 if (e1000e_get_laa_state_82571(hw))
972 e1000e_init_rx_addrs(hw, rar_count);
974 /* Zero out the Multicast HASH table */
975 e_dbg("Zeroing the MTA\n");
976 for (i = 0; i < mac->mta_reg_count; i++)
977 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
979 /* Setup link and flow control */
980 ret_val = e1000_setup_link_82571(hw);
982 /* Set the transmit descriptor write-back policy */
983 reg_data = er32(TXDCTL(0));
984 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
985 E1000_TXDCTL_FULL_TX_DESC_WB |
986 E1000_TXDCTL_COUNT_DESC;
987 ew32(TXDCTL(0), reg_data);
989 /* ...for both queues. */
994 e1000e_enable_tx_pkt_filtering(hw);
995 reg_data = er32(GCR);
996 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1000 reg_data = er32(TXDCTL(1));
1001 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1002 E1000_TXDCTL_FULL_TX_DESC_WB |
1003 E1000_TXDCTL_COUNT_DESC;
1004 ew32(TXDCTL(1), reg_data);
1009 * Clear all of the statistics registers (clear on read). It is
1010 * important that we do this after we have tried to establish link
1011 * because the symbol error count will increment wildly if there
1014 e1000_clear_hw_cntrs_82571(hw);
1020 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1021 * @hw: pointer to the HW structure
1023 * Initializes required hardware-dependent bits needed for normal operation.
1025 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1029 /* Transmit Descriptor Control 0 */
1030 reg = er32(TXDCTL(0));
1032 ew32(TXDCTL(0), reg);
1034 /* Transmit Descriptor Control 1 */
1035 reg = er32(TXDCTL(1));
1037 ew32(TXDCTL(1), reg);
1039 /* Transmit Arbitration Control 0 */
1040 reg = er32(TARC(0));
1041 reg &= ~(0xF << 27); /* 30:27 */
1042 switch (hw->mac.type) {
1045 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1052 /* Transmit Arbitration Control 1 */
1053 reg = er32(TARC(1));
1054 switch (hw->mac.type) {
1057 reg &= ~((1 << 29) | (1 << 30));
1058 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1059 if (er32(TCTL) & E1000_TCTL_MULR)
1069 /* Device Control */
1070 switch (hw->mac.type) {
1082 /* Extended Device Control */
1083 switch (hw->mac.type) {
1087 reg = er32(CTRL_EXT);
1090 ew32(CTRL_EXT, reg);
1096 if (hw->mac.type == e1000_82571) {
1097 reg = er32(PBA_ECC);
1098 reg |= E1000_PBA_ECC_CORR_EN;
1102 * Workaround for hardware errata.
1103 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1106 if ((hw->mac.type == e1000_82571) ||
1107 (hw->mac.type == e1000_82572)) {
1108 reg = er32(CTRL_EXT);
1109 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1110 ew32(CTRL_EXT, reg);
1114 /* PCI-Ex Control Registers */
1115 switch (hw->mac.type) {
1123 * Workaround for hardware errata.
1124 * apply workaround for hardware errata documented in errata
1125 * docs Fixes issue where some error prone or unreliable PCIe
1126 * completions are occurring, particularly with ASPM enabled.
1127 * Without fix, issue can cause tx timeouts.
1141 * e1000_clear_vfta_82571 - Clear VLAN filter table
1142 * @hw: pointer to the HW structure
1144 * Clears the register array which contains the VLAN filter table by
1145 * setting all the values to 0.
1147 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1151 u32 vfta_offset = 0;
1152 u32 vfta_bit_in_reg = 0;
1154 switch (hw->mac.type) {
1158 if (hw->mng_cookie.vlan_id != 0) {
1160 * The VFTA is a 4096b bit-field, each identifying
1161 * a single VLAN ID. The following operations
1162 * determine which 32b entry (i.e. offset) into the
1163 * array we want to set the VLAN ID (i.e. bit) of
1164 * the manageability unit.
1166 vfta_offset = (hw->mng_cookie.vlan_id >>
1167 E1000_VFTA_ENTRY_SHIFT) &
1168 E1000_VFTA_ENTRY_MASK;
1169 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1170 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1176 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1178 * If the offset we want to clear is the same offset of the
1179 * manageability VLAN ID, then clear all bits except that of
1180 * the manageability unit.
1182 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1183 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1189 * e1000_check_mng_mode_82574 - Check manageability is enabled
1190 * @hw: pointer to the HW structure
1192 * Reads the NVM Initialization Control Word 2 and returns true
1193 * (>0) if any manageability is enabled, else false (0).
1195 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1199 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1200 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1204 * e1000_led_on_82574 - Turn LED on
1205 * @hw: pointer to the HW structure
1209 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1214 ctrl = hw->mac.ledctl_mode2;
1215 if (!(E1000_STATUS_LU & er32(STATUS))) {
1217 * If no link, then turn LED on by setting the invert bit
1218 * for each LED that's "on" (0x0E) in ledctl_mode2.
1220 for (i = 0; i < 4; i++)
1221 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1222 E1000_LEDCTL_MODE_LED_ON)
1223 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1231 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1232 * @hw: pointer to the HW structure
1233 * @mc_addr_list: array of multicast addresses to program
1234 * @mc_addr_count: number of multicast addresses to program
1235 * @rar_used_count: the first RAR register free to program
1236 * @rar_count: total number of supported Receive Address Registers
1238 * Updates the Receive Address Registers and Multicast Table Array.
1239 * The caller must have a packed mc_addr_list of multicast addresses.
1240 * The parameter rar_count will usually be hw->mac.rar_entry_count
1241 * unless there are workarounds that change this.
1243 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1249 if (e1000e_get_laa_state_82571(hw))
1252 e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1253 rar_used_count, rar_count);
1257 * e1000_setup_link_82571 - Setup flow control and link settings
1258 * @hw: pointer to the HW structure
1260 * Determines which flow control settings to use, then configures flow
1261 * control. Calls the appropriate media-specific link configuration
1262 * function. Assuming the adapter has a valid link partner, a valid link
1263 * should be established. Assumes the hardware has previously been reset
1264 * and the transmitter and receiver are not enabled.
1266 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1269 * 82573 does not have a word in the NVM to determine
1270 * the default flow control setting, so we explicitly
1273 switch (hw->mac.type) {
1277 if (hw->fc.requested_mode == e1000_fc_default)
1278 hw->fc.requested_mode = e1000_fc_full;
1284 return e1000e_setup_link(hw);
1288 * e1000_setup_copper_link_82571 - Configure copper link settings
1289 * @hw: pointer to the HW structure
1291 * Configures the link for auto-neg or forced speed and duplex. Then we check
1292 * for link, once link is established calls to configure collision distance
1293 * and flow control are called.
1295 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1301 ctrl |= E1000_CTRL_SLU;
1302 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1305 switch (hw->phy.type) {
1308 ret_val = e1000e_copper_link_setup_m88(hw);
1310 case e1000_phy_igp_2:
1311 ret_val = e1000e_copper_link_setup_igp(hw);
1314 return -E1000_ERR_PHY;
1321 ret_val = e1000e_setup_copper_link(hw);
1327 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1328 * @hw: pointer to the HW structure
1330 * Configures collision distance and flow control for fiber and serdes links.
1331 * Upon successful setup, poll for link.
1333 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1335 switch (hw->mac.type) {
1339 * If SerDes loopback mode is entered, there is no form
1340 * of reset to take the adapter out of that mode. So we
1341 * have to explicitly take the adapter out of loopback
1342 * mode. This prevents drivers from twiddling their thumbs
1343 * if another tool failed to take it out of loopback mode.
1345 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1351 return e1000e_setup_fiber_serdes_link(hw);
1355 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1356 * @hw: pointer to the HW structure
1358 * Reports the link state as up or down.
1360 * If autonegotiation is supported by the link partner, the link state is
1361 * determined by the result of autonegotiation. This is the most likely case.
1362 * If autonegotiation is not supported by the link partner, and the link
1363 * has a valid signal, force the link up.
1365 * The link state is represented internally here by 4 states:
1368 * 2) autoneg_progress
1369 * 3) autoneg_complete (the link sucessfully autonegotiated)
1370 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1373 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1375 struct e1000_mac_info *mac = &hw->mac;
1382 status = er32(STATUS);
1385 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1387 /* Receiver is synchronized with no invalid bits. */
1388 switch (mac->serdes_link_state) {
1389 case e1000_serdes_link_autoneg_complete:
1390 if (!(status & E1000_STATUS_LU)) {
1392 * We have lost link, retry autoneg before
1393 * reporting link failure
1395 mac->serdes_link_state =
1396 e1000_serdes_link_autoneg_progress;
1397 mac->serdes_has_link = false;
1398 e_dbg("AN_UP -> AN_PROG\n");
1402 case e1000_serdes_link_forced_up:
1404 * If we are receiving /C/ ordered sets, re-enable
1405 * auto-negotiation in the TXCW register and disable
1406 * forced link in the Device Control register in an
1407 * attempt to auto-negotiate with our link partner.
1409 if (rxcw & E1000_RXCW_C) {
1410 /* Enable autoneg, and unforce link up */
1411 ew32(TXCW, mac->txcw);
1412 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1413 mac->serdes_link_state =
1414 e1000_serdes_link_autoneg_progress;
1415 mac->serdes_has_link = false;
1416 e_dbg("FORCED_UP -> AN_PROG\n");
1420 case e1000_serdes_link_autoneg_progress:
1421 if (rxcw & E1000_RXCW_C) {
1423 * We received /C/ ordered sets, meaning the
1424 * link partner has autonegotiated, and we can
1425 * trust the Link Up (LU) status bit.
1427 if (status & E1000_STATUS_LU) {
1428 mac->serdes_link_state =
1429 e1000_serdes_link_autoneg_complete;
1430 e_dbg("AN_PROG -> AN_UP\n");
1431 mac->serdes_has_link = true;
1433 /* Autoneg completed, but failed. */
1434 mac->serdes_link_state =
1435 e1000_serdes_link_down;
1436 e_dbg("AN_PROG -> DOWN\n");
1440 * The link partner did not autoneg.
1441 * Force link up and full duplex, and change
1444 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1445 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1448 /* Configure Flow Control after link up. */
1449 ret_val = e1000e_config_fc_after_link_up(hw);
1451 e_dbg("Error config flow control\n");
1454 mac->serdes_link_state =
1455 e1000_serdes_link_forced_up;
1456 mac->serdes_has_link = true;
1457 e_dbg("AN_PROG -> FORCED_UP\n");
1461 case e1000_serdes_link_down:
1464 * The link was down but the receiver has now gained
1465 * valid sync, so lets see if we can bring the link
1468 ew32(TXCW, mac->txcw);
1469 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1470 mac->serdes_link_state =
1471 e1000_serdes_link_autoneg_progress;
1472 e_dbg("DOWN -> AN_PROG\n");
1476 if (!(rxcw & E1000_RXCW_SYNCH)) {
1477 mac->serdes_has_link = false;
1478 mac->serdes_link_state = e1000_serdes_link_down;
1479 e_dbg("ANYSTATE -> DOWN\n");
1482 * We have sync, and can tolerate one invalid (IV)
1483 * codeword before declaring link down, so reread
1488 if (rxcw & E1000_RXCW_IV) {
1489 mac->serdes_link_state = e1000_serdes_link_down;
1490 mac->serdes_has_link = false;
1491 e_dbg("ANYSTATE -> DOWN\n");
1500 * e1000_valid_led_default_82571 - Verify a valid default LED config
1501 * @hw: pointer to the HW structure
1502 * @data: pointer to the NVM (EEPROM)
1504 * Read the EEPROM for the current default LED configuration. If the
1505 * LED configuration is not valid, set to a valid LED configuration.
1507 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1511 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1513 e_dbg("NVM Read Error\n");
1517 switch (hw->mac.type) {
1521 if (*data == ID_LED_RESERVED_F746)
1522 *data = ID_LED_DEFAULT_82573;
1525 if (*data == ID_LED_RESERVED_0000 ||
1526 *data == ID_LED_RESERVED_FFFF)
1527 *data = ID_LED_DEFAULT;
1535 * e1000e_get_laa_state_82571 - Get locally administered address state
1536 * @hw: pointer to the HW structure
1538 * Retrieve and return the current locally administered address state.
1540 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1542 if (hw->mac.type != e1000_82571)
1545 return hw->dev_spec.e82571.laa_is_present;
1549 * e1000e_set_laa_state_82571 - Set locally administered address state
1550 * @hw: pointer to the HW structure
1551 * @state: enable/disable locally administered address
1553 * Enable/Disable the current locally administered address state.
1555 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1557 if (hw->mac.type != e1000_82571)
1560 hw->dev_spec.e82571.laa_is_present = state;
1562 /* If workaround is activated... */
1565 * Hold a copy of the LAA in RAR[14] This is done so that
1566 * between the time RAR[0] gets clobbered and the time it
1567 * gets fixed, the actual LAA is in one of the RARs and no
1568 * incoming packets directed to this port are dropped.
1569 * Eventually the LAA will be in RAR[0] and RAR[14].
1571 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1575 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1576 * @hw: pointer to the HW structure
1578 * Verifies that the EEPROM has completed the update. After updating the
1579 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1580 * the checksum fix is not implemented, we need to set the bit and update
1581 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1582 * we need to return bad checksum.
1584 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1586 struct e1000_nvm_info *nvm = &hw->nvm;
1590 if (nvm->type != e1000_nvm_flash_hw)
1594 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1595 * 10h-12h. Checksum may need to be fixed.
1597 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1601 if (!(data & 0x10)) {
1603 * Read 0x23 and check bit 15. This bit is a 1
1604 * when the checksum has already been fixed. If
1605 * the checksum is still wrong and this bit is a
1606 * 1, we need to return bad checksum. Otherwise,
1607 * we need to set this bit to a 1 and update the
1610 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1614 if (!(data & 0x8000)) {
1616 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1619 ret_val = e1000e_update_nvm_checksum(hw);
1627 * e1000_read_mac_addr_82571 - Read device MAC address
1628 * @hw: pointer to the HW structure
1630 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1635 * If there's an alternate MAC address place it in RAR0
1636 * so that it will override the Si installed default perm
1639 ret_val = e1000_check_alt_mac_addr_generic(hw);
1643 ret_val = e1000_read_mac_addr_generic(hw);
1650 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1651 * @hw: pointer to the HW structure
1653 * In the case of a PHY power down to save power, or to turn off link during a
1654 * driver unload, or wake on lan is not enabled, remove the link.
1656 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1658 struct e1000_phy_info *phy = &hw->phy;
1659 struct e1000_mac_info *mac = &hw->mac;
1661 if (!(phy->ops.check_reset_block))
1664 /* If the management interface is not enabled, then power down */
1665 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1666 e1000_power_down_phy_copper(hw);
1672 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1673 * @hw: pointer to the HW structure
1675 * Clears the hardware counters by reading the counter registers.
1677 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1679 e1000e_clear_hw_cntrs_base(hw);
1717 static struct e1000_mac_operations e82571_mac_ops = {
1718 /* .check_mng_mode: mac type dependent */
1719 /* .check_for_link: media type dependent */
1720 .id_led_init = e1000e_id_led_init,
1721 .cleanup_led = e1000e_cleanup_led_generic,
1722 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1723 .get_bus_info = e1000e_get_bus_info_pcie,
1724 /* .get_link_up_info: media type dependent */
1725 /* .led_on: mac type dependent */
1726 .led_off = e1000e_led_off_generic,
1727 .update_mc_addr_list = e1000_update_mc_addr_list_82571,
1728 .write_vfta = e1000_write_vfta_generic,
1729 .clear_vfta = e1000_clear_vfta_82571,
1730 .reset_hw = e1000_reset_hw_82571,
1731 .init_hw = e1000_init_hw_82571,
1732 .setup_link = e1000_setup_link_82571,
1733 /* .setup_physical_interface: media type dependent */
1734 .setup_led = e1000e_setup_led_generic,
1735 .read_mac_addr = e1000_read_mac_addr_82571,
1738 static struct e1000_phy_operations e82_phy_ops_igp = {
1739 .acquire = e1000_get_hw_semaphore_82571,
1740 .check_polarity = e1000_check_polarity_igp,
1741 .check_reset_block = e1000e_check_reset_block_generic,
1743 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1744 .get_cfg_done = e1000_get_cfg_done_82571,
1745 .get_cable_length = e1000e_get_cable_length_igp_2,
1746 .get_info = e1000e_get_phy_info_igp,
1747 .read_reg = e1000e_read_phy_reg_igp,
1748 .release = e1000_put_hw_semaphore_82571,
1749 .reset = e1000e_phy_hw_reset_generic,
1750 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1751 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1752 .write_reg = e1000e_write_phy_reg_igp,
1753 .cfg_on_link_up = NULL,
1756 static struct e1000_phy_operations e82_phy_ops_m88 = {
1757 .acquire = e1000_get_hw_semaphore_82571,
1758 .check_polarity = e1000_check_polarity_m88,
1759 .check_reset_block = e1000e_check_reset_block_generic,
1760 .commit = e1000e_phy_sw_reset,
1761 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1762 .get_cfg_done = e1000e_get_cfg_done,
1763 .get_cable_length = e1000e_get_cable_length_m88,
1764 .get_info = e1000e_get_phy_info_m88,
1765 .read_reg = e1000e_read_phy_reg_m88,
1766 .release = e1000_put_hw_semaphore_82571,
1767 .reset = e1000e_phy_hw_reset_generic,
1768 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1769 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1770 .write_reg = e1000e_write_phy_reg_m88,
1771 .cfg_on_link_up = NULL,
1774 static struct e1000_phy_operations e82_phy_ops_bm = {
1775 .acquire = e1000_get_hw_semaphore_82571,
1776 .check_polarity = e1000_check_polarity_m88,
1777 .check_reset_block = e1000e_check_reset_block_generic,
1778 .commit = e1000e_phy_sw_reset,
1779 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1780 .get_cfg_done = e1000e_get_cfg_done,
1781 .get_cable_length = e1000e_get_cable_length_m88,
1782 .get_info = e1000e_get_phy_info_m88,
1783 .read_reg = e1000e_read_phy_reg_bm2,
1784 .release = e1000_put_hw_semaphore_82571,
1785 .reset = e1000e_phy_hw_reset_generic,
1786 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1787 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1788 .write_reg = e1000e_write_phy_reg_bm2,
1789 .cfg_on_link_up = NULL,
1792 static struct e1000_nvm_operations e82571_nvm_ops = {
1793 .acquire = e1000_acquire_nvm_82571,
1794 .read = e1000e_read_nvm_eerd,
1795 .release = e1000_release_nvm_82571,
1796 .update = e1000_update_nvm_checksum_82571,
1797 .valid_led_default = e1000_valid_led_default_82571,
1798 .validate = e1000_validate_nvm_checksum_82571,
1799 .write = e1000_write_nvm_82571,
1802 struct e1000_info e1000_82571_info = {
1804 .flags = FLAG_HAS_HW_VLAN_FILTER
1805 | FLAG_HAS_JUMBO_FRAMES
1807 | FLAG_APME_IN_CTRL3
1808 | FLAG_RX_CSUM_ENABLED
1809 | FLAG_HAS_CTRLEXT_ON_LOAD
1810 | FLAG_HAS_SMART_POWER_DOWN
1811 | FLAG_RESET_OVERWRITES_LAA /* errata */
1812 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1813 | FLAG_APME_CHECK_PORT_B,
1815 .max_hw_frame_size = DEFAULT_JUMBO,
1816 .get_variants = e1000_get_variants_82571,
1817 .mac_ops = &e82571_mac_ops,
1818 .phy_ops = &e82_phy_ops_igp,
1819 .nvm_ops = &e82571_nvm_ops,
1822 struct e1000_info e1000_82572_info = {
1824 .flags = FLAG_HAS_HW_VLAN_FILTER
1825 | FLAG_HAS_JUMBO_FRAMES
1827 | FLAG_APME_IN_CTRL3
1828 | FLAG_RX_CSUM_ENABLED
1829 | FLAG_HAS_CTRLEXT_ON_LOAD
1830 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1832 .max_hw_frame_size = DEFAULT_JUMBO,
1833 .get_variants = e1000_get_variants_82571,
1834 .mac_ops = &e82571_mac_ops,
1835 .phy_ops = &e82_phy_ops_igp,
1836 .nvm_ops = &e82571_nvm_ops,
1839 struct e1000_info e1000_82573_info = {
1841 .flags = FLAG_HAS_HW_VLAN_FILTER
1842 | FLAG_HAS_JUMBO_FRAMES
1844 | FLAG_APME_IN_CTRL3
1845 | FLAG_RX_CSUM_ENABLED
1846 | FLAG_HAS_SMART_POWER_DOWN
1849 | FLAG_HAS_SWSM_ON_LOAD,
1851 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1852 .get_variants = e1000_get_variants_82571,
1853 .mac_ops = &e82571_mac_ops,
1854 .phy_ops = &e82_phy_ops_m88,
1855 .nvm_ops = &e82571_nvm_ops,
1858 struct e1000_info e1000_82574_info = {
1860 .flags = FLAG_HAS_HW_VLAN_FILTER
1862 | FLAG_HAS_JUMBO_FRAMES
1864 | FLAG_APME_IN_CTRL3
1865 | FLAG_RX_CSUM_ENABLED
1866 | FLAG_HAS_SMART_POWER_DOWN
1868 | FLAG_HAS_CTRLEXT_ON_LOAD,
1870 .max_hw_frame_size = DEFAULT_JUMBO,
1871 .get_variants = e1000_get_variants_82571,
1872 .mac_ops = &e82571_mac_ops,
1873 .phy_ops = &e82_phy_ops_bm,
1874 .nvm_ops = &e82571_nvm_ops,
1877 struct e1000_info e1000_82583_info = {
1879 .flags = FLAG_HAS_HW_VLAN_FILTER
1881 | FLAG_APME_IN_CTRL3
1882 | FLAG_RX_CSUM_ENABLED
1883 | FLAG_HAS_SMART_POWER_DOWN
1885 | FLAG_HAS_CTRLEXT_ON_LOAD,
1887 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1888 .get_variants = e1000_get_variants_82571,
1889 .mac_ops = &e82571_mac_ops,
1890 .phy_ops = &e82_phy_ops_bm,
1891 .nvm_ops = &e82571_nvm_ops,