1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
49 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
99 * A table for the GG82563 cable length where the range is defined
100 * with a lower bound at "index" and the upper bound at
103 static const u16 e1000_gg82563_cable_length_table[] =
104 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
106 ARRAY_SIZE(e1000_gg82563_cable_length_table)
108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
116 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
118 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
123 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
124 * @hw: pointer to the HW structure
126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
128 struct e1000_phy_info *phy = &hw->phy;
131 if (hw->phy.media_type != e1000_media_type_copper) {
132 phy->type = e1000_phy_none;
135 phy->ops.power_up = e1000_power_up_phy_copper;
136 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
140 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
141 phy->reset_delay_us = 100;
142 phy->type = e1000_phy_gg82563;
144 /* This can only be done after all function pointers are setup. */
145 ret_val = e1000e_get_phy_id(hw);
148 if (phy->id != GG82563_E_PHY_ID)
149 return -E1000_ERR_PHY;
155 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
156 * @hw: pointer to the HW structure
158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
160 struct e1000_nvm_info *nvm = &hw->nvm;
161 u32 eecd = er32(EECD);
164 nvm->opcode_bits = 8;
166 switch (nvm->override) {
167 case e1000_nvm_override_spi_large:
169 nvm->address_bits = 16;
171 case e1000_nvm_override_spi_small:
173 nvm->address_bits = 8;
176 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
177 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
181 nvm->type = e1000_nvm_eeprom_spi;
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size += NVM_WORD_SIZE_BASE_SHIFT;
192 /* EEPROM access above 16k is unsupported */
195 nvm->word_size = 1 << size;
201 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
202 * @hw: pointer to the HW structure
204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
206 struct e1000_hw *hw = &adapter->hw;
207 struct e1000_mac_info *mac = &hw->mac;
208 struct e1000_mac_operations *func = &mac->ops;
211 switch (adapter->pdev->device) {
212 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
213 hw->phy.media_type = e1000_media_type_internal_serdes;
216 hw->phy.media_type = e1000_media_type_copper;
220 /* Set mta register count */
221 mac->mta_reg_count = 128;
222 /* Set rar entry count */
223 mac->rar_entry_count = E1000_RAR_ENTRIES;
224 /* Set if manageability features are enabled. */
225 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
227 /* Adaptive IFS not supported */
228 mac->adaptive_ifs = false;
231 switch (hw->phy.media_type) {
232 case e1000_media_type_copper:
233 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
234 func->check_for_link = e1000e_check_for_copper_link;
236 case e1000_media_type_fiber:
237 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
238 func->check_for_link = e1000e_check_for_fiber_link;
240 case e1000_media_type_internal_serdes:
241 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
242 func->check_for_link = e1000e_check_for_serdes_link;
245 return -E1000_ERR_CONFIG;
252 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
254 struct e1000_hw *hw = &adapter->hw;
257 rc = e1000_init_mac_params_80003es2lan(adapter);
261 rc = e1000_init_nvm_params_80003es2lan(hw);
265 rc = e1000_init_phy_params_80003es2lan(hw);
273 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
274 * @hw: pointer to the HW structure
276 * A wrapper to acquire access rights to the correct PHY.
278 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
282 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
283 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
287 * e1000_release_phy_80003es2lan - Release rights to access PHY
288 * @hw: pointer to the HW structure
290 * A wrapper to release access rights to the correct PHY.
292 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
296 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
297 e1000_release_swfw_sync_80003es2lan(hw, mask);
301 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
302 * @hw: pointer to the HW structure
304 * Acquire the semaphore to access the Kumeran interface.
307 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
311 mask = E1000_SWFW_CSR_SM;
313 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
317 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
318 * @hw: pointer to the HW structure
320 * Release the semaphore used to access the Kumeran interface
322 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
326 mask = E1000_SWFW_CSR_SM;
328 e1000_release_swfw_sync_80003es2lan(hw, mask);
332 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
333 * @hw: pointer to the HW structure
335 * Acquire the semaphore to access the EEPROM.
337 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
341 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
345 ret_val = e1000e_acquire_nvm(hw);
348 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
354 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
355 * @hw: pointer to the HW structure
357 * Release the semaphore used to access the EEPROM.
359 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
361 e1000e_release_nvm(hw);
362 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
366 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
367 * @hw: pointer to the HW structure
368 * @mask: specifies which semaphore to acquire
370 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
371 * will also specify which port we're acquiring the lock for.
373 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
377 u32 fwmask = mask << 16;
381 while (i < timeout) {
382 if (e1000e_get_hw_semaphore(hw))
383 return -E1000_ERR_SWFW_SYNC;
385 swfw_sync = er32(SW_FW_SYNC);
386 if (!(swfw_sync & (fwmask | swmask)))
390 * Firmware currently using resource (fwmask)
391 * or other software thread using resource (swmask)
393 e1000e_put_hw_semaphore(hw);
399 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
400 return -E1000_ERR_SWFW_SYNC;
404 ew32(SW_FW_SYNC, swfw_sync);
406 e1000e_put_hw_semaphore(hw);
412 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
413 * @hw: pointer to the HW structure
414 * @mask: specifies which semaphore to acquire
416 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
417 * will also specify which port we're releasing the lock for.
419 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
423 while (e1000e_get_hw_semaphore(hw) != 0);
426 swfw_sync = er32(SW_FW_SYNC);
428 ew32(SW_FW_SYNC, swfw_sync);
430 e1000e_put_hw_semaphore(hw);
434 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
435 * @hw: pointer to the HW structure
436 * @offset: offset of the register to read
437 * @data: pointer to the data returned from the operation
439 * Read the GG82563 PHY register.
441 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
442 u32 offset, u16 *data)
448 ret_val = e1000_acquire_phy_80003es2lan(hw);
452 /* Select Configuration Page */
453 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
454 page_select = GG82563_PHY_PAGE_SELECT;
457 * Use Alternative Page Select register to access
458 * registers 30 and 31
460 page_select = GG82563_PHY_PAGE_SELECT_ALT;
463 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
464 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
466 e1000_release_phy_80003es2lan(hw);
470 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
472 * The "ready" bit in the MDIC register may be incorrectly set
473 * before the device has completed the "Page Select" MDI
474 * transaction. So we wait 200us after each MDI command...
478 /* ...and verify the command was successful. */
479 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
481 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
482 ret_val = -E1000_ERR_PHY;
483 e1000_release_phy_80003es2lan(hw);
489 ret_val = e1000e_read_phy_reg_mdic(hw,
490 MAX_PHY_REG_ADDRESS & offset,
495 ret_val = e1000e_read_phy_reg_mdic(hw,
496 MAX_PHY_REG_ADDRESS & offset,
500 e1000_release_phy_80003es2lan(hw);
506 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
507 * @hw: pointer to the HW structure
508 * @offset: offset of the register to read
509 * @data: value to write to the register
511 * Write to the GG82563 PHY register.
513 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
514 u32 offset, u16 data)
520 ret_val = e1000_acquire_phy_80003es2lan(hw);
524 /* Select Configuration Page */
525 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
526 page_select = GG82563_PHY_PAGE_SELECT;
529 * Use Alternative Page Select register to access
530 * registers 30 and 31
532 page_select = GG82563_PHY_PAGE_SELECT_ALT;
535 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
536 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
538 e1000_release_phy_80003es2lan(hw);
542 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
544 * The "ready" bit in the MDIC register may be incorrectly set
545 * before the device has completed the "Page Select" MDI
546 * transaction. So we wait 200us after each MDI command...
550 /* ...and verify the command was successful. */
551 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
553 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
554 e1000_release_phy_80003es2lan(hw);
555 return -E1000_ERR_PHY;
560 ret_val = e1000e_write_phy_reg_mdic(hw,
561 MAX_PHY_REG_ADDRESS & offset,
566 ret_val = e1000e_write_phy_reg_mdic(hw,
567 MAX_PHY_REG_ADDRESS & offset,
571 e1000_release_phy_80003es2lan(hw);
577 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
578 * @hw: pointer to the HW structure
579 * @offset: offset of the register to read
580 * @words: number of words to write
581 * @data: buffer of data to write to the NVM
583 * Write "words" of data to the ESB2 NVM.
585 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
586 u16 words, u16 *data)
588 return e1000e_write_nvm_spi(hw, offset, words, data);
592 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
593 * @hw: pointer to the HW structure
595 * Wait a specific amount of time for manageability processes to complete.
596 * This is a function pointer entry point called by the phy module.
598 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
600 s32 timeout = PHY_CFG_TIMEOUT;
601 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
603 if (hw->bus.func == 1)
604 mask = E1000_NVM_CFG_DONE_PORT_1;
607 if (er32(EEMNGCTL) & mask)
613 e_dbg("MNG configuration cycle has not completed.\n");
614 return -E1000_ERR_RESET;
621 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
622 * @hw: pointer to the HW structure
624 * Force the speed and duplex settings onto the PHY. This is a
625 * function pointer entry point called by the phy module.
627 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
634 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
635 * forced whenever speed and duplex are forced.
637 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
641 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
642 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
646 e_dbg("GG82563 PSCR: %X\n", phy_data);
648 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
652 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
654 /* Reset the phy to commit changes. */
655 phy_data |= MII_CR_RESET;
657 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
663 if (hw->phy.autoneg_wait_to_complete) {
664 e_dbg("Waiting for forced speed/duplex link "
665 "on GG82563 phy.\n");
667 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
674 * We didn't get link.
675 * Reset the DSP and cross our fingers.
677 ret_val = e1000e_phy_reset_dsp(hw);
683 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
689 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
694 * Resetting the phy means we need to verify the TX_CLK corresponds
695 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
697 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
698 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
699 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
701 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
704 * In addition, we must re-enable CRS on Tx for both half and full
707 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
708 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
714 * e1000_get_cable_length_80003es2lan - Set approximate cable length
715 * @hw: pointer to the HW structure
717 * Find the approximate cable length as measured by the GG82563 PHY.
718 * This is a function pointer entry point called by the phy module.
720 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
722 struct e1000_phy_info *phy = &hw->phy;
726 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
730 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
732 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
733 ret_val = -E1000_ERR_PHY;
737 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
738 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
740 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
747 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
748 * @hw: pointer to the HW structure
749 * @speed: pointer to speed buffer
750 * @duplex: pointer to duplex buffer
752 * Retrieve the current speed and duplex configuration.
754 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
759 if (hw->phy.media_type == e1000_media_type_copper) {
760 ret_val = e1000e_get_speed_and_duplex_copper(hw,
763 hw->phy.ops.cfg_on_link_up(hw);
765 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
774 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
775 * @hw: pointer to the HW structure
777 * Perform a global reset to the ESB2 controller.
779 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
785 * Prevent the PCI-E bus from sticking if there is no TLP connection
786 * on the last TLP read/write transaction when MAC is reset.
788 ret_val = e1000e_disable_pcie_master(hw);
790 e_dbg("PCI-E Master disable polling has failed.\n");
792 e_dbg("Masking off all interrupts\n");
793 ew32(IMC, 0xffffffff);
796 ew32(TCTL, E1000_TCTL_PSP);
803 ret_val = e1000_acquire_phy_80003es2lan(hw);
804 e_dbg("Issuing a global reset to MAC\n");
805 ew32(CTRL, ctrl | E1000_CTRL_RST);
806 e1000_release_phy_80003es2lan(hw);
808 ret_val = e1000e_get_auto_rd_done(hw);
810 /* We don't want to continue accessing MAC registers. */
813 /* Clear any pending interrupt events. */
814 ew32(IMC, 0xffffffff);
821 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
822 * @hw: pointer to the HW structure
824 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
826 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
828 struct e1000_mac_info *mac = &hw->mac;
833 e1000_initialize_hw_bits_80003es2lan(hw);
835 /* Initialize identification LED */
836 ret_val = e1000e_id_led_init(hw);
838 e_dbg("Error initializing identification LED\n");
839 /* This is not fatal and we should not stop init due to this */
841 /* Disabling VLAN filtering */
842 e_dbg("Initializing the IEEE VLAN\n");
843 mac->ops.clear_vfta(hw);
845 /* Setup the receive address. */
846 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
848 /* Zero out the Multicast HASH table */
849 e_dbg("Zeroing the MTA\n");
850 for (i = 0; i < mac->mta_reg_count; i++)
851 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
853 /* Setup link and flow control */
854 ret_val = e1000e_setup_link(hw);
856 /* Set the transmit descriptor write-back policy */
857 reg_data = er32(TXDCTL(0));
858 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
859 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
860 ew32(TXDCTL(0), reg_data);
862 /* ...for both queues. */
863 reg_data = er32(TXDCTL(1));
864 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
865 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
866 ew32(TXDCTL(1), reg_data);
868 /* Enable retransmit on late collisions */
869 reg_data = er32(TCTL);
870 reg_data |= E1000_TCTL_RTLC;
871 ew32(TCTL, reg_data);
873 /* Configure Gigabit Carry Extend Padding */
874 reg_data = er32(TCTL_EXT);
875 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
876 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
877 ew32(TCTL_EXT, reg_data);
879 /* Configure Transmit Inter-Packet Gap */
880 reg_data = er32(TIPG);
881 reg_data &= ~E1000_TIPG_IPGT_MASK;
882 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
883 ew32(TIPG, reg_data);
885 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
886 reg_data &= ~0x00100000;
887 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
889 /* default to true to enable the MDIC W/A */
890 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
892 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
893 E1000_KMRNCTRLSTA_OFFSET >>
894 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
897 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
898 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
899 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
903 * Clear all of the statistics registers (clear on read). It is
904 * important that we do this after we have tried to establish link
905 * because the symbol error count will increment wildly if there
908 e1000_clear_hw_cntrs_80003es2lan(hw);
914 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
915 * @hw: pointer to the HW structure
917 * Initializes required hardware-dependent bits needed for normal operation.
919 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
923 /* Transmit Descriptor Control 0 */
924 reg = er32(TXDCTL(0));
926 ew32(TXDCTL(0), reg);
928 /* Transmit Descriptor Control 1 */
929 reg = er32(TXDCTL(1));
931 ew32(TXDCTL(1), reg);
933 /* Transmit Arbitration Control 0 */
935 reg &= ~(0xF << 27); /* 30:27 */
936 if (hw->phy.media_type != e1000_media_type_copper)
940 /* Transmit Arbitration Control 1 */
942 if (er32(TCTL) & E1000_TCTL_MULR)
950 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
951 * @hw: pointer to the HW structure
953 * Setup some GG82563 PHY registers for obtaining link
955 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
957 struct e1000_phy_info *phy = &hw->phy;
962 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
966 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
967 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
968 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
970 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
976 * MDI/MDI-X = 0 (default)
977 * 0 - Auto for all speeds
980 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
982 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
986 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
990 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
993 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
997 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1003 * disable_polarity_correction = 0 (default)
1004 * Automatic Correction for Reversed Cable Polarity
1008 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1009 if (phy->disable_polarity_correction)
1010 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1012 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1016 /* SW Reset the PHY so all changes take effect */
1017 ret_val = e1000e_commit_phy(hw);
1019 e_dbg("Error Resetting the PHY\n");
1023 /* Bypass Rx and Tx FIFO's */
1024 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1025 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1026 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1027 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1031 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1032 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1036 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1037 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1038 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1043 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1047 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1048 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1052 ctrl_ext = er32(CTRL_EXT);
1053 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1054 ew32(CTRL_EXT, ctrl_ext);
1056 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1061 * Do not init these registers when the HW is in IAMT mode, since the
1062 * firmware will have already initialized them. We only initialize
1063 * them if the HW is not in IAMT mode.
1065 if (!e1000e_check_mng_mode(hw)) {
1066 /* Enable Electrical Idle on the PHY */
1067 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1068 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1072 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1076 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1077 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1083 * Workaround: Disable padding in Kumeran interface in the MAC
1084 * and in the PHY to avoid CRC errors.
1086 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1090 data |= GG82563_ICR_DIS_PADDING;
1091 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1099 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1100 * @hw: pointer to the HW structure
1102 * Essentially a wrapper for setting up all things "copper" related.
1103 * This is a function pointer entry point called by the mac module.
1105 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1112 ctrl |= E1000_CTRL_SLU;
1113 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1117 * Set the mac to wait the maximum time between each
1118 * iteration and increase the max iterations when
1119 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1121 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1125 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1130 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1134 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1135 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1139 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1140 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1141 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1146 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1150 ret_val = e1000e_setup_copper_link(hw);
1156 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1157 * @hw: pointer to the HW structure
1158 * @duplex: current duplex setting
1160 * Configure the KMRN interface by applying last minute quirks for
1163 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1169 if (hw->phy.media_type == e1000_media_type_copper) {
1170 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1175 if (speed == SPEED_1000)
1176 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1178 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1185 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1186 * @hw: pointer to the HW structure
1187 * @duplex: current duplex setting
1189 * Configure the KMRN interface by applying last minute quirks for
1192 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1197 u16 reg_data, reg_data2;
1199 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1200 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1201 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1206 /* Configure Transmit Inter-Packet Gap */
1208 tipg &= ~E1000_TIPG_IPGT_MASK;
1209 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1213 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1217 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1221 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1223 if (duplex == HALF_DUPLEX)
1224 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1226 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1228 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1234 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1235 * @hw: pointer to the HW structure
1237 * Configure the KMRN interface by applying last minute quirks for
1238 * gigabit operation.
1240 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1243 u16 reg_data, reg_data2;
1247 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1248 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1249 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1254 /* Configure Transmit Inter-Packet Gap */
1256 tipg &= ~E1000_TIPG_IPGT_MASK;
1257 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1261 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1265 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1269 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1271 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1272 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1278 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1279 * @hw: pointer to the HW structure
1280 * @offset: register offset to be read
1281 * @data: pointer to the read data
1283 * Acquire semaphore, then read the PHY register at offset
1284 * using the kumeran interface. The information retrieved is stored in data.
1285 * Release the semaphore before exiting.
1287 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1293 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1297 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1298 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1299 ew32(KMRNCTRLSTA, kmrnctrlsta);
1303 kmrnctrlsta = er32(KMRNCTRLSTA);
1304 *data = (u16)kmrnctrlsta;
1306 e1000_release_mac_csr_80003es2lan(hw);
1312 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1313 * @hw: pointer to the HW structure
1314 * @offset: register offset to write to
1315 * @data: data to write at register offset
1317 * Acquire semaphore, then write the data to PHY register
1318 * at the offset using the kumeran interface. Release semaphore
1321 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1327 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1331 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1332 E1000_KMRNCTRLSTA_OFFSET) | data;
1333 ew32(KMRNCTRLSTA, kmrnctrlsta);
1337 e1000_release_mac_csr_80003es2lan(hw);
1343 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1344 * @hw: pointer to the HW structure
1346 * In the case of a PHY power down to save power, or to turn off link during a
1347 * driver unload, or wake on lan is not enabled, remove the link.
1349 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1351 /* If the management interface is not enabled, then power down */
1352 if (!(hw->mac.ops.check_mng_mode(hw) ||
1353 hw->phy.ops.check_reset_block(hw)))
1354 e1000_power_down_phy_copper(hw);
1360 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1361 * @hw: pointer to the HW structure
1363 * Clears the hardware counters by reading the counter registers.
1365 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1367 e1000e_clear_hw_cntrs_base(hw);
1405 static struct e1000_mac_operations es2_mac_ops = {
1406 .id_led_init = e1000e_id_led_init,
1407 .check_mng_mode = e1000e_check_mng_mode_generic,
1408 /* check_for_link dependent on media type */
1409 .cleanup_led = e1000e_cleanup_led_generic,
1410 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1411 .get_bus_info = e1000e_get_bus_info_pcie,
1412 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1413 .led_on = e1000e_led_on_generic,
1414 .led_off = e1000e_led_off_generic,
1415 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1416 .write_vfta = e1000_write_vfta_generic,
1417 .clear_vfta = e1000_clear_vfta_generic,
1418 .reset_hw = e1000_reset_hw_80003es2lan,
1419 .init_hw = e1000_init_hw_80003es2lan,
1420 .setup_link = e1000e_setup_link,
1421 /* setup_physical_interface dependent on media type */
1422 .setup_led = e1000e_setup_led_generic,
1425 static struct e1000_phy_operations es2_phy_ops = {
1426 .acquire = e1000_acquire_phy_80003es2lan,
1427 .check_polarity = e1000_check_polarity_m88,
1428 .check_reset_block = e1000e_check_reset_block_generic,
1429 .commit = e1000e_phy_sw_reset,
1430 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1431 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1432 .get_cable_length = e1000_get_cable_length_80003es2lan,
1433 .get_info = e1000e_get_phy_info_m88,
1434 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1435 .release = e1000_release_phy_80003es2lan,
1436 .reset = e1000e_phy_hw_reset_generic,
1437 .set_d0_lplu_state = NULL,
1438 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1439 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1440 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1443 static struct e1000_nvm_operations es2_nvm_ops = {
1444 .acquire = e1000_acquire_nvm_80003es2lan,
1445 .read = e1000e_read_nvm_eerd,
1446 .release = e1000_release_nvm_80003es2lan,
1447 .update = e1000e_update_nvm_checksum_generic,
1448 .valid_led_default = e1000e_valid_led_default,
1449 .validate = e1000e_validate_nvm_checksum_generic,
1450 .write = e1000_write_nvm_80003es2lan,
1453 struct e1000_info e1000_es2_info = {
1454 .mac = e1000_80003es2lan,
1455 .flags = FLAG_HAS_HW_VLAN_FILTER
1456 | FLAG_HAS_JUMBO_FRAMES
1458 | FLAG_APME_IN_CTRL3
1459 | FLAG_RX_CSUM_ENABLED
1460 | FLAG_HAS_CTRLEXT_ON_LOAD
1461 | FLAG_RX_NEEDS_RESTART /* errata */
1462 | FLAG_TARC_SET_BIT_ZERO /* errata */
1463 | FLAG_APME_CHECK_PORT_B
1464 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1465 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1467 .max_hw_frame_size = DEFAULT_JUMBO,
1468 .get_variants = e1000_get_variants_80003es2lan,
1469 .mac_ops = &es2_mac_ops,
1470 .phy_ops = &es2_phy_ops,
1471 .nvm_ops = &es2_nvm_ops,