drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* EMI Registers */
 144 #define I82579_EMI_ADDR         0x10
 145 #define I82579_EMI_DATA         0x11
 146 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 147
 148 /* Strapping Option Register - RO */
 149 #define E1000_STRAP                     0x0000C
 150 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 152
 153 /* OEM Bits Phy Register */
 154 #define HV_OEM_BITS            PHY_REG(768, 25)
 155 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 156 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 158
 159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 160 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 161
 162 /* KMRN Mode Control */
 163 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 164 #define HV_KMRN_MDIO_SLOW      0x0400
 165
 166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 167 /* Offset 04h HSFSTS */
 168 union ich8_hws_flash_status {
 169         struct ich8_hsfsts {
 170                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 171                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 172                 u16 dael       :1; /* bit 2 Direct Access error Log */
 173                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 174                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 175                 u16 reserved1  :2; /* bit 13:6 Reserved */
 176                 u16 reserved2  :6; /* bit 13:6 Reserved */
 177                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 178                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 179         } hsf_status;
 180         u16 regval;
 181 };
 182
 183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 184 /* Offset 06h FLCTL */
 185 union ich8_hws_flash_ctrl {
 186         struct ich8_hsflctl {
 187                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 188                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 189                 u16 reserved   :5;   /* 7:3 Reserved  */
 190                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 191                 u16 flockdn    :6;   /* 15:10 Reserved */
 192         } hsf_ctrl;
 193         u16 regval;
 194 };
 195
 196 /* ICH Flash Region Access Permissions */
 197 union ich8_hws_flash_regacc {
 198         struct ich8_flracc {
 199                 u32 grra      :8; /* 0:7 GbE region Read Access */
 200                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 201                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 202                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 203         } hsf_flregacc;
 204         u16 regval;
 205 };
 206
 207 /* ICH Flash Protected Region */
 208 union ich8_flash_protected_range {
 209         struct ich8_pr {
 210                 u32 base:13;     /* 0:12 Protected Range Base */
 211                 u32 reserved1:2; /* 13:14 Reserved */
 212                 u32 rpe:1;       /* 15 Read Protection Enable */
 213                 u32 limit:13;    /* 16:28 Protected Range Limit */
 214                 u32 reserved2:2; /* 29:30 Reserved */
 215                 u32 wpe:1;       /* 31 Write Protection Enable */
 216         } range;
 217         u32 regval;
 218 };
 219
 220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 225                                                 u32 offset, u8 byte);
 226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 227                                          u8 *data);
 228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 229                                          u16 *data);
 230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 231                                          u8 size, u16 *data);
 232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 246 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 252
 253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 254 {
 255         return readw(hw->flash_address + reg);
 256 }
 257
 258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 259 {
 260         return readl(hw->flash_address + reg);
 261 }
 262
 263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 264 {
 265         writew(val, hw->flash_address + reg);
 266 }
 267
 268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 269 {
 270         writel(val, hw->flash_address + reg);
 271 }
 272
 273 #define er16flash(reg)          __er16flash(hw, (reg))
 274 #define er32flash(reg)          __er32flash(hw, (reg))
 275 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 276 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 277
 278 /**
 279  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 280  *  @hw: pointer to the HW structure
 281  *
 282  *  Initialize family-specific PHY parameters and function pointers.
 283  **/
 284 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 285 {
 286         struct e1000_phy_info *phy = &hw->phy;
 287         u32 ctrl, fwsm;
 288         s32 ret_val = 0;
 289
 290         phy->addr                     = 1;
 291         phy->reset_delay_us           = 100;
 292
 293         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 294         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 295         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 296         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 297         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 298         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 299         phy->ops.power_up             = e1000_power_up_phy_copper;
 300         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 301         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 302
 303         /*
 304          * The MAC-PHY interconnect may still be in SMBus mode
 305          * after Sx->S0.  If the manageability engine (ME) is
 306          * disabled, then toggle the LANPHYPC Value bit to force
 307          * the interconnect to PCIe mode.
 308          */
 309         fwsm = er32(FWSM);
 310         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 311                 ctrl = er32(CTRL);
 312                 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 313                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 314                 ew32(CTRL, ctrl);
 315                 udelay(10);
 316                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 317                 ew32(CTRL, ctrl);
 318                 msleep(50);
 319
 320                 /*
 321                  * Gate automatic PHY configuration by hardware on
 322                  * non-managed 82579
 323                  */
 324                 if (hw->mac.type == e1000_pch2lan)
 325                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 326         }
 327
 328         /*
 329          * Reset the PHY before any access to it.  Doing so, ensures that
 330          * the PHY is in a known good state before we read/write PHY registers.
 331          * The generic reset is sufficient here, because we haven't determined
 332          * the PHY type yet.
 333          */
 334         ret_val = e1000e_phy_hw_reset_generic(hw);
 335         if (ret_val)
 336                 goto out;
 337
 338         /* Ungate automatic PHY configuration on non-managed 82579 */
 339         if ((hw->mac.type == e1000_pch2lan) &&
 340             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 341                 usleep_range(10000, 20000);
 342                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 343         }
 344
 345         phy->id = e1000_phy_unknown;
 346         switch (hw->mac.type) {
 347         default:
 348                 ret_val = e1000e_get_phy_id(hw);
 349                 if (ret_val)
 350                         goto out;
 351                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 352                         break;
 353                 /* fall-through */
 354         case e1000_pch2lan:
 355                 /*
 356                  * In case the PHY needs to be in mdio slow mode,
 357                  * set slow mode and try to get the PHY id again.
 358                  */
 359                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 360                 if (ret_val)
 361                         goto out;
 362                 ret_val = e1000e_get_phy_id(hw);
 363                 if (ret_val)
 364                         goto out;
 365                 break;
 366         }
 367         phy->type = e1000e_get_phy_type_from_id(phy->id);
 368
 369         switch (phy->type) {
 370         case e1000_phy_82577:
 371         case e1000_phy_82579:
 372                 phy->ops.check_polarity = e1000_check_polarity_82577;
 373                 phy->ops.force_speed_duplex =
 374                     e1000_phy_force_speed_duplex_82577;
 375                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 376                 phy->ops.get_info = e1000_get_phy_info_82577;
 377                 phy->ops.commit = e1000e_phy_sw_reset;
 378                 break;
 379         case e1000_phy_82578:
 380                 phy->ops.check_polarity = e1000_check_polarity_m88;
 381                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 382                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 383                 phy->ops.get_info = e1000e_get_phy_info_m88;
 384                 break;
 385         default:
 386                 ret_val = -E1000_ERR_PHY;
 387                 break;
 388         }
 389
 390 out:
 391         return ret_val;
 392 }
 393
 394 /**
 395  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 396  *  @hw: pointer to the HW structure
 397  *
 398  *  Initialize family-specific PHY parameters and function pointers.
 399  **/
 400 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 401 {
 402         struct e1000_phy_info *phy = &hw->phy;
 403         s32 ret_val;
 404         u16 i = 0;
 405
 406         phy->addr                       = 1;
 407         phy->reset_delay_us             = 100;
 408
 409         phy->ops.power_up               = e1000_power_up_phy_copper;
 410         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 411
 412         /*
 413          * We may need to do this twice - once for IGP and if that fails,
 414          * we'll set BM func pointers and try again
 415          */
 416         ret_val = e1000e_determine_phy_address(hw);
 417         if (ret_val) {
 418                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 419                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 420                 ret_val = e1000e_determine_phy_address(hw);
 421                 if (ret_val) {
 422                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 423                         return ret_val;
 424                 }
 425         }
 426
 427         phy->id = 0;
 428         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 429                (i++ < 100)) {
 430                 usleep_range(1000, 2000);
 431                 ret_val = e1000e_get_phy_id(hw);
 432                 if (ret_val)
 433                         return ret_val;
 434         }
 435
 436         /* Verify phy id */
 437         switch (phy->id) {
 438         case IGP03E1000_E_PHY_ID:
 439                 phy->type = e1000_phy_igp_3;
 440                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 441                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 442                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 443                 phy->ops.get_info = e1000e_get_phy_info_igp;
 444                 phy->ops.check_polarity = e1000_check_polarity_igp;
 445                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 446                 break;
 447         case IFE_E_PHY_ID:
 448         case IFE_PLUS_E_PHY_ID:
 449         case IFE_C_E_PHY_ID:
 450                 phy->type = e1000_phy_ife;
 451                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 452                 phy->ops.get_info = e1000_get_phy_info_ife;
 453                 phy->ops.check_polarity = e1000_check_polarity_ife;
 454                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 455                 break;
 456         case BME1000_E_PHY_ID:
 457                 phy->type = e1000_phy_bm;
 458                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 459                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 460                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 461                 phy->ops.commit = e1000e_phy_sw_reset;
 462                 phy->ops.get_info = e1000e_get_phy_info_m88;
 463                 phy->ops.check_polarity = e1000_check_polarity_m88;
 464                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 465                 break;
 466         default:
 467                 return -E1000_ERR_PHY;
 468                 break;
 469         }
 470
 471         return 0;
 472 }
 473
 474 /**
 475  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 476  *  @hw: pointer to the HW structure
 477  *
 478  *  Initialize family-specific NVM parameters and function
 479  *  pointers.
 480  **/
 481 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 482 {
 483         struct e1000_nvm_info *nvm = &hw->nvm;
 484         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 485         u32 gfpreg, sector_base_addr, sector_end_addr;
 486         u16 i;
 487
 488         /* Can't read flash registers if the register set isn't mapped. */
 489         if (!hw->flash_address) {
 490                 e_dbg("ERROR: Flash registers not mapped\n");
 491                 return -E1000_ERR_CONFIG;
 492         }
 493
 494         nvm->type = e1000_nvm_flash_sw;
 495
 496         gfpreg = er32flash(ICH_FLASH_GFPREG);
 497
 498         /*
 499          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 500          * Add 1 to sector_end_addr since this sector is included in
 501          * the overall size.
 502          */
 503         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 504         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 505
 506         /* flash_base_addr is byte-aligned */
 507         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 508
 509         /*
 510          * find total size of the NVM, then cut in half since the total
 511          * size represents two separate NVM banks.
 512          */
 513         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 514                                 << FLASH_SECTOR_ADDR_SHIFT;
 515         nvm->flash_bank_size /= 2;
 516         /* Adjust to word count */
 517         nvm->flash_bank_size /= sizeof(u16);
 518
 519         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 520
 521         /* Clear shadow ram */
 522         for (i = 0; i < nvm->word_size; i++) {
 523                 dev_spec->shadow_ram[i].modified = false;
 524                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 525         }
 526
 527         return 0;
 528 }
 529
 530 /**
 531  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 532  *  @hw: pointer to the HW structure
 533  *
 534  *  Initialize family-specific MAC parameters and function
 535  *  pointers.
 536  **/
 537 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 538 {
 539         struct e1000_hw *hw = &adapter->hw;
 540         struct e1000_mac_info *mac = &hw->mac;
 541
 542         /* Set media type function pointer */
 543         hw->phy.media_type = e1000_media_type_copper;
 544
 545         /* Set mta register count */
 546         mac->mta_reg_count = 32;
 547         /* Set rar entry count */
 548         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 549         if (mac->type == e1000_ich8lan)
 550                 mac->rar_entry_count--;
 551         /* FWSM register */
 552         mac->has_fwsm = true;
 553         /* ARC subsystem not supported */
 554         mac->arc_subsystem_valid = false;
 555         /* Adaptive IFS supported */
 556         mac->adaptive_ifs = true;
 557
 558         /* LED operations */
 559         switch (mac->type) {
 560         case e1000_ich8lan:
 561         case e1000_ich9lan:
 562         case e1000_ich10lan:
 563                 /* check management mode */
 564                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 565                 /* ID LED init */
 566                 mac->ops.id_led_init = e1000e_id_led_init;
 567                 /* blink LED */
 568                 mac->ops.blink_led = e1000e_blink_led_generic;
 569                 /* setup LED */
 570                 mac->ops.setup_led = e1000e_setup_led_generic;
 571                 /* cleanup LED */
 572                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 573                 /* turn on/off LED */
 574                 mac->ops.led_on = e1000_led_on_ich8lan;
 575                 mac->ops.led_off = e1000_led_off_ich8lan;
 576                 break;
 577         case e1000_pchlan:
 578         case e1000_pch2lan:
 579                 /* check management mode */
 580                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 581                 /* ID LED init */
 582                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 583                 /* setup LED */
 584                 mac->ops.setup_led = e1000_setup_led_pchlan;
 585                 /* cleanup LED */
 586                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 587                 /* turn on/off LED */
 588                 mac->ops.led_on = e1000_led_on_pchlan;
 589                 mac->ops.led_off = e1000_led_off_pchlan;
 590                 break;
 591         default:
 592                 break;
 593         }
 594
 595         /* Enable PCS Lock-loss workaround for ICH8 */
 596         if (mac->type == e1000_ich8lan)
 597                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 598
 599         /* Gate automatic PHY configuration by hardware on managed 82579 */
 600         if ((mac->type == e1000_pch2lan) &&
 601             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 602                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 603
 604         return 0;
 605 }
 606
 607 /**
 608  *  e1000_set_eee_pchlan - Enable/disable EEE support
 609  *  @hw: pointer to the HW structure
 610  *
 611  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 612  *  the LPI Control register will remain set only if/when link is up.
 613  **/
 614 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 615 {
 616         s32 ret_val = 0;
 617         u16 phy_reg;
 618
 619         if (hw->phy.type != e1000_phy_82579)
 620                 goto out;
 621
 622         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 623         if (ret_val)
 624                 goto out;
 625
 626         if (hw->dev_spec.ich8lan.eee_disable)
 627                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 628         else
 629                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 630
 631         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 632 out:
 633         return ret_val;
 634 }
 635
 636 /**
 637  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 638  *  @hw: pointer to the HW structure
 639  *
 640  *  Checks to see of the link status of the hardware has changed.  If a
 641  *  change in link status has been detected, then we read the PHY registers
 642  *  to get the current speed/duplex if link exists.
 643  **/
 644 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 645 {
 646         struct e1000_mac_info *mac = &hw->mac;
 647         s32 ret_val;
 648         bool link;
 649
 650         /*
 651          * We only want to go out to the PHY registers to see if Auto-Neg
 652          * has completed and/or if our link status has changed.  The
 653          * get_link_status flag is set upon receiving a Link Status
 654          * Change or Rx Sequence Error interrupt.
 655          */
 656         if (!mac->get_link_status) {
 657                 ret_val = 0;
 658                 goto out;
 659         }
 660
 661         /*
 662          * First we want to see if the MII Status Register reports
 663          * link.  If so, then we want to get the current speed/duplex
 664          * of the PHY.
 665          */
 666         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 667         if (ret_val)
 668                 goto out;
 669
 670         if (hw->mac.type == e1000_pchlan) {
 671                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 672                 if (ret_val)
 673                         goto out;
 674         }
 675
 676         if (!link)
 677                 goto out; /* No link detected */
 678
 679         mac->get_link_status = false;
 680
 681         if (hw->phy.type == e1000_phy_82578) {
 682                 ret_val = e1000_link_stall_workaround_hv(hw);
 683                 if (ret_val)
 684                         goto out;
 685         }
 686
 687         if (hw->mac.type == e1000_pch2lan) {
 688                 ret_val = e1000_k1_workaround_lv(hw);
 689                 if (ret_val)
 690                         goto out;
 691         }
 692
 693         /*
 694          * Check if there was DownShift, must be checked
 695          * immediately after link-up
 696          */
 697         e1000e_check_downshift(hw);
 698
 699         /* Enable/Disable EEE after link up */
 700         ret_val = e1000_set_eee_pchlan(hw);
 701         if (ret_val)
 702                 goto out;
 703
 704         /*
 705          * If we are forcing speed/duplex, then we simply return since
 706          * we have already determined whether we have link or not.
 707          */
 708         if (!mac->autoneg) {
 709                 ret_val = -E1000_ERR_CONFIG;
 710                 goto out;
 711         }
 712
 713         /*
 714          * Auto-Neg is enabled.  Auto Speed Detection takes care
 715          * of MAC speed/duplex configuration.  So we only need to
 716          * configure Collision Distance in the MAC.
 717          */
 718         e1000e_config_collision_dist(hw);
 719
 720         /*
 721          * Configure Flow Control now that Auto-Neg has completed.
 722          * First, we need to restore the desired flow control
 723          * settings because we may have had to re-autoneg with a
 724          * different link partner.
 725          */
 726         ret_val = e1000e_config_fc_after_link_up(hw);
 727         if (ret_val)
 728                 e_dbg("Error configuring flow control\n");
 729
 730 out:
 731         return ret_val;
 732 }
 733
 734 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 735 {
 736         struct e1000_hw *hw = &adapter->hw;
 737         s32 rc;
 738
 739         rc = e1000_init_mac_params_ich8lan(adapter);
 740         if (rc)
 741                 return rc;
 742
 743         rc = e1000_init_nvm_params_ich8lan(hw);
 744         if (rc)
 745                 return rc;
 746
 747         switch (hw->mac.type) {
 748         case e1000_ich8lan:
 749         case e1000_ich9lan:
 750         case e1000_ich10lan:
 751                 rc = e1000_init_phy_params_ich8lan(hw);
 752                 break;
 753         case e1000_pchlan:
 754         case e1000_pch2lan:
 755                 rc = e1000_init_phy_params_pchlan(hw);
 756                 break;
 757         default:
 758                 break;
 759         }
 760         if (rc)
 761                 return rc;
 762
 763         /*
 764          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 765          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 766          */
 767         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 768             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 769              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 770                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 771                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 772
 773                 hw->mac.ops.blink_led = NULL;
 774         }
 775
 776         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 777             (adapter->hw.phy.type == e1000_phy_igp_3))
 778                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 779
 780         /* Disable EEE by default until IEEE802.3az spec is finalized */
 781         if (adapter->flags2 & FLAG2_HAS_EEE)
 782                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 783
 784         return 0;
 785 }
 786
 787 static DEFINE_MUTEX(nvm_mutex);
 788
 789 /**
 790  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 791  *  @hw: pointer to the HW structure
 792  *
 793  *  Acquires the mutex for performing NVM operations.
 794  **/
 795 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 796 {
 797         mutex_lock(&nvm_mutex);
 798
 799         return 0;
 800 }
 801
 802 /**
 803  *  e1000_release_nvm_ich8lan - Release NVM mutex
 804  *  @hw: pointer to the HW structure
 805  *
 806  *  Releases the mutex used while performing NVM operations.
 807  **/
 808 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 809 {
 810         mutex_unlock(&nvm_mutex);
 811 }
 812
 813 static DEFINE_MUTEX(swflag_mutex);
 814
 815 /**
 816  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 817  *  @hw: pointer to the HW structure
 818  *
 819  *  Acquires the software control flag for performing PHY and select
 820  *  MAC CSR accesses.
 821  **/
 822 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 823 {
 824         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 825         s32 ret_val = 0;
 826
 827         mutex_lock(&swflag_mutex);
 828
 829         while (timeout) {
 830                 extcnf_ctrl = er32(EXTCNF_CTRL);
 831                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 832                         break;
 833
 834                 mdelay(1);
 835                 timeout--;
 836         }
 837
 838         if (!timeout) {
 839                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 840                 ret_val = -E1000_ERR_CONFIG;
 841                 goto out;
 842         }
 843
 844         timeout = SW_FLAG_TIMEOUT;
 845
 846         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 847         ew32(EXTCNF_CTRL, extcnf_ctrl);
 848
 849         while (timeout) {
 850                 extcnf_ctrl = er32(EXTCNF_CTRL);
 851                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 852                         break;
 853
 854                 mdelay(1);
 855                 timeout--;
 856         }
 857
 858         if (!timeout) {
 859                 e_dbg("Failed to acquire the semaphore.\n");
 860                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 861                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 862                 ret_val = -E1000_ERR_CONFIG;
 863                 goto out;
 864         }
 865
 866 out:
 867         if (ret_val)
 868                 mutex_unlock(&swflag_mutex);
 869
 870         return ret_val;
 871 }
 872
 873 /**
 874  *  e1000_release_swflag_ich8lan - Release software control flag
 875  *  @hw: pointer to the HW structure
 876  *
 877  *  Releases the software control flag for performing PHY and select
 878  *  MAC CSR accesses.
 879  **/
 880 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 881 {
 882         u32 extcnf_ctrl;
 883
 884         extcnf_ctrl = er32(EXTCNF_CTRL);
 885         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 886         ew32(EXTCNF_CTRL, extcnf_ctrl);
 887
 888         mutex_unlock(&swflag_mutex);
 889 }
 890
 891 /**
 892  *  e1000_check_mng_mode_ich8lan - Checks management mode
 893  *  @hw: pointer to the HW structure
 894  *
 895  *  This checks if the adapter has any manageability enabled.
 896  *  This is a function pointer entry point only called by read/write
 897  *  routines for the PHY and NVM parts.
 898  **/
 899 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 900 {
 901         u32 fwsm;
 902
 903         fwsm = er32(FWSM);
 904         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 905                ((fwsm & E1000_FWSM_MODE_MASK) ==
 906                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 907 }
 908
 909 /**
 910  *  e1000_check_mng_mode_pchlan - Checks management mode
 911  *  @hw: pointer to the HW structure
 912  *
 913  *  This checks if the adapter has iAMT enabled.
 914  *  This is a function pointer entry point only called by read/write
 915  *  routines for the PHY and NVM parts.
 916  **/
 917 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 918 {
 919         u32 fwsm;
 920
 921         fwsm = er32(FWSM);
 922         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 923                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 924 }
 925
 926 /**
 927  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 928  *  @hw: pointer to the HW structure
 929  *
 930  *  Checks if firmware is blocking the reset of the PHY.
 931  *  This is a function pointer entry point only called by
 932  *  reset routines.
 933  **/
 934 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 935 {
 936         u32 fwsm;
 937
 938         fwsm = er32(FWSM);
 939
 940         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 941 }
 942
 943 /**
 944  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 945  *  @hw: pointer to the HW structure
 946  *
 947  *  Assumes semaphore already acquired.
 948  *
 949  **/
 950 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 951 {
 952         u16 phy_data;
 953         u32 strap = er32(STRAP);
 954         s32 ret_val = 0;
 955
 956         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 957
 958         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 959         if (ret_val)
 960                 goto out;
 961
 962         phy_data &= ~HV_SMB_ADDR_MASK;
 963         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 964         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 965         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 966
 967 out:
 968         return ret_val;
 969 }
 970
 971 /**
 972  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 973  *  @hw:   pointer to the HW structure
 974  *
 975  *  SW should configure the LCD from the NVM extended configuration region
 976  *  as a workaround for certain parts.
 977  **/
 978 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 979 {
 980         struct e1000_phy_info *phy = &hw->phy;
 981         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 982         s32 ret_val = 0;
 983         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 984
 985         /*
 986          * Initialize the PHY from the NVM on ICH platforms.  This
 987          * is needed due to an issue where the NVM configuration is
 988          * not properly autoloaded after power transitions.
 989          * Therefore, after each PHY reset, we will load the
 990          * configuration data out of the NVM manually.
 991          */
 992         switch (hw->mac.type) {
 993         case e1000_ich8lan:
 994                 if (phy->type != e1000_phy_igp_3)
 995                         return ret_val;
 996
 997                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
 998                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
 999                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1000                         break;
1001                 }
1002                 /* Fall-thru */
1003         case e1000_pchlan:
1004         case e1000_pch2lan:
1005                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1006                 break;
1007         default:
1008                 return ret_val;
1009         }
1010
1011         ret_val = hw->phy.ops.acquire(hw);
1012         if (ret_val)
1013                 return ret_val;
1014
1015         data = er32(FEXTNVM);
1016         if (!(data & sw_cfg_mask))
1017                 goto out;
1018
1019         /*
1020          * Make sure HW does not configure LCD from PHY
1021          * extended configuration before SW configuration
1022          */
1023         data = er32(EXTCNF_CTRL);
1024         if (!(hw->mac.type == e1000_pch2lan)) {
1025                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1026                         goto out;
1027         }
1028
1029         cnf_size = er32(EXTCNF_SIZE);
1030         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1031         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1032         if (!cnf_size)
1033                 goto out;
1034
1035         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1036         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1037
1038         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1039             (hw->mac.type == e1000_pchlan)) ||
1040              (hw->mac.type == e1000_pch2lan)) {
1041                 /*
1042                  * HW configures the SMBus address and LEDs when the
1043                  * OEM and LCD Write Enable bits are set in the NVM.
1044                  * When both NVM bits are cleared, SW will configure
1045                  * them instead.
1046                  */
1047                 ret_val = e1000_write_smbus_addr(hw);
1048                 if (ret_val)
1049                         goto out;
1050
1051                 data = er32(LEDCTL);
1052                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1053                                                         (u16)data);
1054                 if (ret_val)
1055                         goto out;
1056         }
1057
1058         /* Configure LCD from extended configuration region. */
1059
1060         /* cnf_base_addr is in DWORD */
1061         word_addr = (u16)(cnf_base_addr << 1);
1062
1063         for (i = 0; i < cnf_size; i++) {
1064                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1065                                          &reg_data);
1066                 if (ret_val)
1067                         goto out;
1068
1069                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1070                                          1, &reg_addr);
1071                 if (ret_val)
1072                         goto out;
1073
1074                 /* Save off the PHY page for future writes. */
1075                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1076                         phy_page = reg_data;
1077                         continue;
1078                 }
1079
1080                 reg_addr &= PHY_REG_MASK;
1081                 reg_addr |= phy_page;
1082
1083                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1084                                                     reg_data);
1085                 if (ret_val)
1086                         goto out;
1087         }
1088
1089 out:
1090         hw->phy.ops.release(hw);
1091         return ret_val;
1092 }
1093
1094 /**
1095  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1096  *  @hw:   pointer to the HW structure
1097  *  @link: link up bool flag
1098  *
1099  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1100  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1101  *  If link is down, the function will restore the default K1 setting located
1102  *  in the NVM.
1103  **/
1104 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1105 {
1106         s32 ret_val = 0;
1107         u16 status_reg = 0;
1108         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1109
1110         if (hw->mac.type != e1000_pchlan)
1111                 goto out;
1112
1113         /* Wrap the whole flow with the sw flag */
1114         ret_val = hw->phy.ops.acquire(hw);
1115         if (ret_val)
1116                 goto out;
1117
1118         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1119         if (link) {
1120                 if (hw->phy.type == e1000_phy_82578) {
1121                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1122                                                                   &status_reg);
1123                         if (ret_val)
1124                                 goto release;
1125
1126                         status_reg &= BM_CS_STATUS_LINK_UP |
1127                                       BM_CS_STATUS_RESOLVED |
1128                                       BM_CS_STATUS_SPEED_MASK;
1129
1130                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1131                                            BM_CS_STATUS_RESOLVED |
1132                                            BM_CS_STATUS_SPEED_1000))
1133                                 k1_enable = false;
1134                 }
1135
1136                 if (hw->phy.type == e1000_phy_82577) {
1137                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1138                                                                   &status_reg);
1139                         if (ret_val)
1140                                 goto release;
1141
1142                         status_reg &= HV_M_STATUS_LINK_UP |
1143                                       HV_M_STATUS_AUTONEG_COMPLETE |
1144                                       HV_M_STATUS_SPEED_MASK;
1145
1146                         if (status_reg == (HV_M_STATUS_LINK_UP |
1147                                            HV_M_STATUS_AUTONEG_COMPLETE |
1148                                            HV_M_STATUS_SPEED_1000))
1149                                 k1_enable = false;
1150                 }
1151
1152                 /* Link stall fix for link up */
1153                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1154                                                            0x0100);
1155                 if (ret_val)
1156                         goto release;
1157
1158         } else {
1159                 /* Link stall fix for link down */
1160                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1161                                                            0x4100);
1162                 if (ret_val)
1163                         goto release;
1164         }
1165
1166         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1167
1168 release:
1169         hw->phy.ops.release(hw);
1170 out:
1171         return ret_val;
1172 }
1173
1174 /**
1175  *  e1000_configure_k1_ich8lan - Configure K1 power state
1176  *  @hw: pointer to the HW structure
1177  *  @enable: K1 state to configure
1178  *
1179  *  Configure the K1 power state based on the provided parameter.
1180  *  Assumes semaphore already acquired.
1181  *
1182  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1183  **/
1184 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1185 {
1186         s32 ret_val = 0;
1187         u32 ctrl_reg = 0;
1188         u32 ctrl_ext = 0;
1189         u32 reg = 0;
1190         u16 kmrn_reg = 0;
1191
1192         ret_val = e1000e_read_kmrn_reg_locked(hw,
1193                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1194                                              &kmrn_reg);
1195         if (ret_val)
1196                 goto out;
1197
1198         if (k1_enable)
1199                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1200         else
1201                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1202
1203         ret_val = e1000e_write_kmrn_reg_locked(hw,
1204                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1205                                               kmrn_reg);
1206         if (ret_val)
1207                 goto out;
1208
1209         udelay(20);
1210         ctrl_ext = er32(CTRL_EXT);
1211         ctrl_reg = er32(CTRL);
1212
1213         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1214         reg |= E1000_CTRL_FRCSPD;
1215         ew32(CTRL, reg);
1216
1217         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1218         udelay(20);
1219         ew32(CTRL, ctrl_reg);
1220         ew32(CTRL_EXT, ctrl_ext);
1221         udelay(20);
1222
1223 out:
1224         return ret_val;
1225 }
1226
1227 /**
1228  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1229  *  @hw:       pointer to the HW structure
1230  *  @d0_state: boolean if entering d0 or d3 device state
1231  *
1232  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1233  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1234  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1235  **/
1236 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1237 {
1238         s32 ret_val = 0;
1239         u32 mac_reg;
1240         u16 oem_reg;
1241
1242         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1243                 return ret_val;
1244
1245         ret_val = hw->phy.ops.acquire(hw);
1246         if (ret_val)
1247                 return ret_val;
1248
1249         if (!(hw->mac.type == e1000_pch2lan)) {
1250                 mac_reg = er32(EXTCNF_CTRL);
1251                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1252                         goto out;
1253         }
1254
1255         mac_reg = er32(FEXTNVM);
1256         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1257                 goto out;
1258
1259         mac_reg = er32(PHY_CTRL);
1260
1261         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1262         if (ret_val)
1263                 goto out;
1264
1265         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1266
1267         if (d0_state) {
1268                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1269                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1270
1271                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1272                         oem_reg |= HV_OEM_BITS_LPLU;
1273         } else {
1274                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1275                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1276
1277                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1278                         oem_reg |= HV_OEM_BITS_LPLU;
1279         }
1280         /* Restart auto-neg to activate the bits */
1281         if (!e1000_check_reset_block(hw))
1282                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1283         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1284
1285 out:
1286         hw->phy.ops.release(hw);
1287
1288         return ret_val;
1289 }
1290
1291
1292 /**
1293  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1294  *  @hw:   pointer to the HW structure
1295  **/
1296 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1297 {
1298         s32 ret_val;
1299         u16 data;
1300
1301         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1302         if (ret_val)
1303                 return ret_val;
1304
1305         data |= HV_KMRN_MDIO_SLOW;
1306
1307         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1308
1309         return ret_val;
1310 }
1311
1312 /**
1313  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1314  *  done after every PHY reset.
1315  **/
1316 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1317 {
1318         s32 ret_val = 0;
1319         u16 phy_data;
1320
1321         if (hw->mac.type != e1000_pchlan)
1322                 return ret_val;
1323
1324         /* Set MDIO slow mode before any other MDIO access */
1325         if (hw->phy.type == e1000_phy_82577) {
1326                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1327                 if (ret_val)
1328                         goto out;
1329         }
1330
1331         if (((hw->phy.type == e1000_phy_82577) &&
1332              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1333             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1334                 /* Disable generation of early preamble */
1335                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1336                 if (ret_val)
1337                         return ret_val;
1338
1339                 /* Preamble tuning for SSC */
1340                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1341                 if (ret_val)
1342                         return ret_val;
1343         }
1344
1345         if (hw->phy.type == e1000_phy_82578) {
1346                 /*
1347                  * Return registers to default by doing a soft reset then
1348                  * writing 0x3140 to the control register.
1349                  */
1350                 if (hw->phy.revision < 2) {
1351                         e1000e_phy_sw_reset(hw);
1352                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1353                 }
1354         }
1355
1356         /* Select page 0 */
1357         ret_val = hw->phy.ops.acquire(hw);
1358         if (ret_val)
1359                 return ret_val;
1360
1361         hw->phy.addr = 1;
1362         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1363         hw->phy.ops.release(hw);
1364         if (ret_val)
1365                 goto out;
1366
1367         /*
1368          * Configure the K1 Si workaround during phy reset assuming there is
1369          * link so that it disables K1 if link is in 1Gbps.
1370          */
1371         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1372         if (ret_val)
1373                 goto out;
1374
1375         /* Workaround for link disconnects on a busy hub in half duplex */
1376         ret_val = hw->phy.ops.acquire(hw);
1377         if (ret_val)
1378                 goto out;
1379         ret_val = hw->phy.ops.read_reg_locked(hw,
1380                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1381                                               &phy_data);
1382         if (ret_val)
1383                 goto release;
1384         ret_val = hw->phy.ops.write_reg_locked(hw,
1385                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1386                                                phy_data & 0x00FF);
1387 release:
1388         hw->phy.ops.release(hw);
1389 out:
1390         return ret_val;
1391 }
1392
1393 /**
1394  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1395  *  @hw:   pointer to the HW structure
1396  **/
1397 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1398 {
1399         u32 mac_reg;
1400         u16 i;
1401
1402         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1403         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1404                 mac_reg = er32(RAL(i));
1405                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1406                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1407                 mac_reg = er32(RAH(i));
1408                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1409                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1410         }
1411 }
1412
1413 /**
1414  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1415  *  with 82579 PHY
1416  *  @hw: pointer to the HW structure
1417  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1418  **/
1419 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1420 {
1421         s32 ret_val = 0;
1422         u16 phy_reg, data;
1423         u32 mac_reg;
1424         u16 i;
1425
1426         if (hw->mac.type != e1000_pch2lan)
1427                 goto out;
1428
1429         /* disable Rx path while enabling/disabling workaround */
1430         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1431         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1432         if (ret_val)
1433                 goto out;
1434
1435         if (enable) {
1436                 /*
1437                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1438                  * SHRAL/H) and initial CRC values to the MAC
1439                  */
1440                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1441                         u8 mac_addr[ETH_ALEN] = {0};
1442                         u32 addr_high, addr_low;
1443
1444                         addr_high = er32(RAH(i));
1445                         if (!(addr_high & E1000_RAH_AV))
1446                                 continue;
1447                         addr_low = er32(RAL(i));
1448                         mac_addr[0] = (addr_low & 0xFF);
1449                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1450                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1451                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1452                         mac_addr[4] = (addr_high & 0xFF);
1453                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1454
1455                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1456                 }
1457
1458                 /* Write Rx addresses to the PHY */
1459                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1460
1461                 /* Enable jumbo frame workaround in the MAC */
1462                 mac_reg = er32(FFLT_DBG);
1463                 mac_reg &= ~(1 << 14);
1464                 mac_reg |= (7 << 15);
1465                 ew32(FFLT_DBG, mac_reg);
1466
1467                 mac_reg = er32(RCTL);
1468                 mac_reg |= E1000_RCTL_SECRC;
1469                 ew32(RCTL, mac_reg);
1470
1471                 ret_val = e1000e_read_kmrn_reg(hw,
1472                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1473                                                 &data);
1474                 if (ret_val)
1475                         goto out;
1476                 ret_val = e1000e_write_kmrn_reg(hw,
1477                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1478                                                 data | (1 << 0));
1479                 if (ret_val)
1480                         goto out;
1481                 ret_val = e1000e_read_kmrn_reg(hw,
1482                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1483                                                 &data);
1484                 if (ret_val)
1485                         goto out;
1486                 data &= ~(0xF << 8);
1487                 data |= (0xB << 8);
1488                 ret_val = e1000e_write_kmrn_reg(hw,
1489                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1490                                                 data);
1491                 if (ret_val)
1492                         goto out;
1493
1494                 /* Enable jumbo frame workaround in the PHY */
1495                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1496                 data &= ~(0x7F << 5);
1497                 data |= (0x37 << 5);
1498                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1499                 if (ret_val)
1500                         goto out;
1501                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1502                 data &= ~(1 << 13);
1503                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1504                 if (ret_val)
1505                         goto out;
1506                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1507                 data &= ~(0x3FF << 2);
1508                 data |= (0x1A << 2);
1509                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1510                 if (ret_val)
1511                         goto out;
1512                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1513                 if (ret_val)
1514                         goto out;
1515                 e1e_rphy(hw, HV_PM_CTRL, &data);
1516                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1517                 if (ret_val)
1518                         goto out;
1519         } else {
1520                 /* Write MAC register values back to h/w defaults */
1521                 mac_reg = er32(FFLT_DBG);
1522                 mac_reg &= ~(0xF << 14);
1523                 ew32(FFLT_DBG, mac_reg);
1524
1525                 mac_reg = er32(RCTL);
1526                 mac_reg &= ~E1000_RCTL_SECRC;
1527                 ew32(RCTL, mac_reg);
1528
1529                 ret_val = e1000e_read_kmrn_reg(hw,
1530                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1531                                                 &data);
1532                 if (ret_val)
1533                         goto out;
1534                 ret_val = e1000e_write_kmrn_reg(hw,
1535                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1536                                                 data & ~(1 << 0));
1537                 if (ret_val)
1538                         goto out;
1539                 ret_val = e1000e_read_kmrn_reg(hw,
1540                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1541                                                 &data);
1542                 if (ret_val)
1543                         goto out;
1544                 data &= ~(0xF << 8);
1545                 data |= (0xB << 8);
1546                 ret_val = e1000e_write_kmrn_reg(hw,
1547                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1548                                                 data);
1549                 if (ret_val)
1550                         goto out;
1551
1552                 /* Write PHY register values back to h/w defaults */
1553                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1554                 data &= ~(0x7F << 5);
1555                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1556                 if (ret_val)
1557                         goto out;
1558                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1559                 data |= (1 << 13);
1560                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1561                 if (ret_val)
1562                         goto out;
1563                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1564                 data &= ~(0x3FF << 2);
1565                 data |= (0x8 << 2);
1566                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1567                 if (ret_val)
1568                         goto out;
1569                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1570                 if (ret_val)
1571                         goto out;
1572                 e1e_rphy(hw, HV_PM_CTRL, &data);
1573                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1574                 if (ret_val)
1575                         goto out;
1576         }
1577
1578         /* re-enable Rx path after enabling/disabling workaround */
1579         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1580
1581 out:
1582         return ret_val;
1583 }
1584
1585 /**
1586  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1587  *  done after every PHY reset.
1588  **/
1589 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1590 {
1591         s32 ret_val = 0;
1592
1593         if (hw->mac.type != e1000_pch2lan)
1594                 goto out;
1595
1596         /* Set MDIO slow mode before any other MDIO access */
1597         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1598
1599 out:
1600         return ret_val;
1601 }
1602
1603 /**
1604  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1605  *  @hw:   pointer to the HW structure
1606  *
1607  *  Workaround to set the K1 beacon duration for 82579 parts
1608  **/
1609 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1610 {
1611         s32 ret_val = 0;
1612         u16 status_reg = 0;
1613         u32 mac_reg;
1614
1615         if (hw->mac.type != e1000_pch2lan)
1616                 goto out;
1617
1618         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1619         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1620         if (ret_val)
1621                 goto out;
1622
1623         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1624             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1625                 mac_reg = er32(FEXTNVM4);
1626                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1627
1628                 if (status_reg & HV_M_STATUS_SPEED_1000)
1629                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1630                 else
1631                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1632
1633                 ew32(FEXTNVM4, mac_reg);
1634         }
1635
1636 out:
1637         return ret_val;
1638 }
1639
1640 /**
1641  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1642  *  @hw:   pointer to the HW structure
1643  *  @gate: boolean set to true to gate, false to ungate
1644  *
1645  *  Gate/ungate the automatic PHY configuration via hardware; perform
1646  *  the configuration via software instead.
1647  **/
1648 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1649 {
1650         u32 extcnf_ctrl;
1651
1652         if (hw->mac.type != e1000_pch2lan)
1653                 return;
1654
1655         extcnf_ctrl = er32(EXTCNF_CTRL);
1656
1657         if (gate)
1658                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1659         else
1660                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1661
1662         ew32(EXTCNF_CTRL, extcnf_ctrl);
1663         return;
1664 }
1665
1666 /**
1667  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1668  *  @hw: pointer to the HW structure
1669  *
1670  *  Check the appropriate indication the MAC has finished configuring the
1671  *  PHY after a software reset.
1672  **/
1673 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1674 {
1675         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1676
1677         /* Wait for basic configuration completes before proceeding */
1678         do {
1679                 data = er32(STATUS);
1680                 data &= E1000_STATUS_LAN_INIT_DONE;
1681                 udelay(100);
1682         } while ((!data) && --loop);
1683
1684         /*
1685          * If basic configuration is incomplete before the above loop
1686          * count reaches 0, loading the configuration from NVM will
1687          * leave the PHY in a bad state possibly resulting in no link.
1688          */
1689         if (loop == 0)
1690                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1691
1692         /* Clear the Init Done bit for the next init event */
1693         data = er32(STATUS);
1694         data &= ~E1000_STATUS_LAN_INIT_DONE;
1695         ew32(STATUS, data);
1696 }
1697
1698 /**
1699  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1700  *  @hw: pointer to the HW structure
1701  **/
1702 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1703 {
1704         s32 ret_val = 0;
1705         u16 reg;
1706
1707         if (e1000_check_reset_block(hw))
1708                 goto out;
1709
1710         /* Allow time for h/w to get to quiescent state after reset */
1711         usleep_range(10000, 20000);
1712
1713         /* Perform any necessary post-reset workarounds */
1714         switch (hw->mac.type) {
1715         case e1000_pchlan:
1716                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1717                 if (ret_val)
1718                         goto out;
1719                 break;
1720         case e1000_pch2lan:
1721                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1722                 if (ret_val)
1723                         goto out;
1724                 break;
1725         default:
1726                 break;
1727         }
1728
1729         /* Dummy read to clear the phy wakeup bit after lcd reset */
1730         if (hw->mac.type >= e1000_pchlan)
1731                 e1e_rphy(hw, BM_WUC, &reg);
1732
1733         /* Configure the LCD with the extended configuration region in NVM */
1734         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1735         if (ret_val)
1736                 goto out;
1737
1738         /* Configure the LCD with the OEM bits in NVM */
1739         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1740
1741         if (hw->mac.type == e1000_pch2lan) {
1742                 /* Ungate automatic PHY configuration on non-managed 82579 */
1743                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1744                         usleep_range(10000, 20000);
1745                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1746                 }
1747
1748                 /* Set EEE LPI Update Timer to 200usec */
1749                 ret_val = hw->phy.ops.acquire(hw);
1750                 if (ret_val)
1751                         goto out;
1752                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1753                                                        I82579_LPI_UPDATE_TIMER);
1754                 if (ret_val)
1755                         goto release;
1756                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1757                                                        0x1387);
1758 release:
1759                 hw->phy.ops.release(hw);
1760         }
1761
1762 out:
1763         return ret_val;
1764 }
1765
1766 /**
1767  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1768  *  @hw: pointer to the HW structure
1769  *
1770  *  Resets the PHY
1771  *  This is a function pointer entry point called by drivers
1772  *  or other shared routines.
1773  **/
1774 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1775 {
1776         s32 ret_val = 0;
1777
1778         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1779         if ((hw->mac.type == e1000_pch2lan) &&
1780             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1781                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1782
1783         ret_val = e1000e_phy_hw_reset_generic(hw);
1784         if (ret_val)
1785                 goto out;
1786
1787         ret_val = e1000_post_phy_reset_ich8lan(hw);
1788
1789 out:
1790         return ret_val;
1791 }
1792
1793 /**
1794  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1795  *  @hw: pointer to the HW structure
1796  *  @active: true to enable LPLU, false to disable
1797  *
1798  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1799  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1800  *  the phy speed. This function will manually set the LPLU bit and restart
1801  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1802  *  since it configures the same bit.
1803  **/
1804 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1805 {
1806         s32 ret_val = 0;
1807         u16 oem_reg;
1808
1809         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1810         if (ret_val)
1811                 goto out;
1812
1813         if (active)
1814                 oem_reg |= HV_OEM_BITS_LPLU;
1815         else
1816                 oem_reg &= ~HV_OEM_BITS_LPLU;
1817
1818         oem_reg |= HV_OEM_BITS_RESTART_AN;
1819         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1820
1821 out:
1822         return ret_val;
1823 }
1824
1825 /**
1826  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1827  *  @hw: pointer to the HW structure
1828  *  @active: true to enable LPLU, false to disable
1829  *
1830  *  Sets the LPLU D0 state according to the active flag.  When
1831  *  activating LPLU this function also disables smart speed
1832  *  and vice versa.  LPLU will not be activated unless the
1833  *  device autonegotiation advertisement meets standards of
1834  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1835  *  This is a function pointer entry point only called by
1836  *  PHY setup routines.
1837  **/
1838 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1839 {
1840         struct e1000_phy_info *phy = &hw->phy;
1841         u32 phy_ctrl;
1842         s32 ret_val = 0;
1843         u16 data;
1844
1845         if (phy->type == e1000_phy_ife)
1846                 return ret_val;
1847
1848         phy_ctrl = er32(PHY_CTRL);
1849
1850         if (active) {
1851                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1852                 ew32(PHY_CTRL, phy_ctrl);
1853
1854                 if (phy->type != e1000_phy_igp_3)
1855                         return 0;
1856
1857                 /*
1858                  * Call gig speed drop workaround on LPLU before accessing
1859                  * any PHY registers
1860                  */
1861                 if (hw->mac.type == e1000_ich8lan)
1862                         e1000e_gig_downshift_workaround_ich8lan(hw);
1863
1864                 /* When LPLU is enabled, we should disable SmartSpeed */
1865                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1866                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1867                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1868                 if (ret_val)
1869                         return ret_val;
1870         } else {
1871                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1872                 ew32(PHY_CTRL, phy_ctrl);
1873
1874                 if (phy->type != e1000_phy_igp_3)
1875                         return 0;
1876
1877                 /*
1878                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1879                  * during Dx states where the power conservation is most
1880                  * important.  During driver activity we should enable
1881                  * SmartSpeed, so performance is maintained.
1882                  */
1883                 if (phy->smart_speed == e1000_smart_speed_on) {
1884                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1885                                            &data);
1886                         if (ret_val)
1887                                 return ret_val;
1888
1889                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1890                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1891                                            data);
1892                         if (ret_val)
1893                                 return ret_val;
1894                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1895                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1896                                            &data);
1897                         if (ret_val)
1898                                 return ret_val;
1899
1900                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1901                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1902                                            data);
1903                         if (ret_val)
1904                                 return ret_val;
1905                 }
1906         }
1907
1908         return 0;
1909 }
1910
1911 /**
1912  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1913  *  @hw: pointer to the HW structure
1914  *  @active: true to enable LPLU, false to disable
1915  *
1916  *  Sets the LPLU D3 state according to the active flag.  When
1917  *  activating LPLU this function also disables smart speed
1918  *  and vice versa.  LPLU will not be activated unless the
1919  *  device autonegotiation advertisement meets standards of
1920  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1921  *  This is a function pointer entry point only called by
1922  *  PHY setup routines.
1923  **/
1924 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1925 {
1926         struct e1000_phy_info *phy = &hw->phy;
1927         u32 phy_ctrl;
1928         s32 ret_val;
1929         u16 data;
1930
1931         phy_ctrl = er32(PHY_CTRL);
1932
1933         if (!active) {
1934                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1935                 ew32(PHY_CTRL, phy_ctrl);
1936
1937                 if (phy->type != e1000_phy_igp_3)
1938                         return 0;
1939
1940                 /*
1941                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1942                  * during Dx states where the power conservation is most
1943                  * important.  During driver activity we should enable
1944                  * SmartSpeed, so performance is maintained.
1945                  */
1946                 if (phy->smart_speed == e1000_smart_speed_on) {
1947                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1948                                            &data);
1949                         if (ret_val)
1950                                 return ret_val;
1951
1952                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1953                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1954                                            data);
1955                         if (ret_val)
1956                                 return ret_val;
1957                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1958                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1959                                            &data);
1960                         if (ret_val)
1961                                 return ret_val;
1962
1963                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1964                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1965                                            data);
1966                         if (ret_val)
1967                                 return ret_val;
1968                 }
1969         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1970                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1971                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1972                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1973                 ew32(PHY_CTRL, phy_ctrl);
1974
1975                 if (phy->type != e1000_phy_igp_3)
1976                         return 0;
1977
1978                 /*
1979                  * Call gig speed drop workaround on LPLU before accessing
1980                  * any PHY registers
1981                  */
1982                 if (hw->mac.type == e1000_ich8lan)
1983                         e1000e_gig_downshift_workaround_ich8lan(hw);
1984
1985                 /* When LPLU is enabled, we should disable SmartSpeed */
1986                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1987                 if (ret_val)
1988                         return ret_val;
1989
1990                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1991                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1992         }
1993
1994         return 0;
1995 }
1996
1997 /**
1998  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1999  *  @hw: pointer to the HW structure
2000  *  @bank:  pointer to the variable that returns the active bank
2001  *
2002  *  Reads signature byte from the NVM using the flash access registers.
2003  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2004  **/
2005 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2006 {
2007         u32 eecd;
2008         struct e1000_nvm_info *nvm = &hw->nvm;
2009         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2010         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2011         u8 sig_byte = 0;
2012         s32 ret_val = 0;
2013
2014         switch (hw->mac.type) {
2015         case e1000_ich8lan:
2016         case e1000_ich9lan:
2017                 eecd = er32(EECD);
2018                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2019                     E1000_EECD_SEC1VAL_VALID_MASK) {
2020                         if (eecd & E1000_EECD_SEC1VAL)
2021                                 *bank = 1;
2022                         else
2023                                 *bank = 0;
2024
2025                         return 0;
2026                 }
2027                 e_dbg("Unable to determine valid NVM bank via EEC - "
2028                        "reading flash signature\n");
2029                 /* fall-thru */
2030         default:
2031                 /* set bank to 0 in case flash read fails */
2032                 *bank = 0;
2033
2034                 /* Check bank 0 */
2035                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2036                                                         &sig_byte);
2037                 if (ret_val)
2038                         return ret_val;
2039                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2040                     E1000_ICH_NVM_SIG_VALUE) {
2041                         *bank = 0;
2042                         return 0;
2043                 }
2044
2045                 /* Check bank 1 */
2046                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2047                                                         bank1_offset,
2048                                                         &sig_byte);
2049                 if (ret_val)
2050                         return ret_val;
2051                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2052                     E1000_ICH_NVM_SIG_VALUE) {
2053                         *bank = 1;
2054                         return 0;
2055                 }
2056
2057                 e_dbg("ERROR: No valid NVM bank present\n");
2058                 return -E1000_ERR_NVM;
2059         }
2060
2061         return 0;
2062 }
2063
2064 /**
2065  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2066  *  @hw: pointer to the HW structure
2067  *  @offset: The offset (in bytes) of the word(s) to read.
2068  *  @words: Size of data to read in words
2069  *  @data: Pointer to the word(s) to read at offset.
2070  *
2071  *  Reads a word(s) from the NVM using the flash access registers.
2072  **/
2073 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2074                                   u16 *data)
2075 {
2076         struct e1000_nvm_info *nvm = &hw->nvm;
2077         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2078         u32 act_offset;
2079         s32 ret_val = 0;
2080         u32 bank = 0;
2081         u16 i, word;
2082
2083         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2084             (words == 0)) {
2085                 e_dbg("nvm parameter(s) out of bounds\n");
2086                 ret_val = -E1000_ERR_NVM;
2087                 goto out;
2088         }
2089
2090         nvm->ops.acquire(hw);
2091
2092         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2093         if (ret_val) {
2094                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2095                 bank = 0;
2096         }
2097
2098         act_offset = (bank) ? nvm->flash_bank_size : 0;
2099         act_offset += offset;
2100
2101         ret_val = 0;
2102         for (i = 0; i < words; i++) {
2103                 if ((dev_spec->shadow_ram) &&
2104                     (dev_spec->shadow_ram[offset+i].modified)) {
2105                         data[i] = dev_spec->shadow_ram[offset+i].value;
2106                 } else {
2107                         ret_val = e1000_read_flash_word_ich8lan(hw,
2108                                                                 act_offset + i,
2109                                                                 &word);
2110                         if (ret_val)
2111                                 break;
2112                         data[i] = word;
2113                 }
2114         }
2115
2116         nvm->ops.release(hw);
2117
2118 out:
2119         if (ret_val)
2120                 e_dbg("NVM read error: %d\n", ret_val);
2121
2122         return ret_val;
2123 }
2124
2125 /**
2126  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2127  *  @hw: pointer to the HW structure
2128  *
2129  *  This function does initial flash setup so that a new read/write/erase cycle
2130  *  can be started.
2131  **/
2132 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2133 {
2134         union ich8_hws_flash_status hsfsts;
2135         s32 ret_val = -E1000_ERR_NVM;
2136
2137         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2138
2139         /* Check if the flash descriptor is valid */
2140         if (hsfsts.hsf_status.fldesvalid == 0) {
2141                 e_dbg("Flash descriptor invalid.  "
2142                          "SW Sequencing must be used.\n");
2143                 return -E1000_ERR_NVM;
2144         }
2145
2146         /* Clear FCERR and DAEL in hw status by writing 1 */
2147         hsfsts.hsf_status.flcerr = 1;
2148         hsfsts.hsf_status.dael = 1;
2149
2150         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2151
2152         /*
2153          * Either we should have a hardware SPI cycle in progress
2154          * bit to check against, in order to start a new cycle or
2155          * FDONE bit should be changed in the hardware so that it
2156          * is 1 after hardware reset, which can then be used as an
2157          * indication whether a cycle is in progress or has been
2158          * completed.
2159          */
2160
2161         if (hsfsts.hsf_status.flcinprog == 0) {
2162                 /*
2163                  * There is no cycle running at present,
2164                  * so we can start a cycle.
2165                  * Begin by setting Flash Cycle Done.
2166                  */
2167                 hsfsts.hsf_status.flcdone = 1;
2168                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2169                 ret_val = 0;
2170         } else {
2171                 s32 i = 0;
2172
2173                 /*
2174                  * Otherwise poll for sometime so the current
2175                  * cycle has a chance to end before giving up.
2176                  */
2177                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2178                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2179                         if (hsfsts.hsf_status.flcinprog == 0) {
2180                                 ret_val = 0;
2181                                 break;
2182                         }
2183                         udelay(1);
2184                 }
2185                 if (ret_val == 0) {
2186                         /*
2187                          * Successful in waiting for previous cycle to timeout,
2188                          * now set the Flash Cycle Done.
2189                          */
2190                         hsfsts.hsf_status.flcdone = 1;
2191                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2192                 } else {
2193                         e_dbg("Flash controller busy, cannot get access\n");
2194                 }
2195         }
2196
2197         return ret_val;
2198 }
2199
2200 /**
2201  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2202  *  @hw: pointer to the HW structure
2203  *  @timeout: maximum time to wait for completion
2204  *
2205  *  This function starts a flash cycle and waits for its completion.
2206  **/
2207 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2208 {
2209         union ich8_hws_flash_ctrl hsflctl;
2210         union ich8_hws_flash_status hsfsts;
2211         s32 ret_val = -E1000_ERR_NVM;
2212         u32 i = 0;
2213
2214         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2215         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2216         hsflctl.hsf_ctrl.flcgo = 1;
2217         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2218
2219         /* wait till FDONE bit is set to 1 */
2220         do {
2221                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2222                 if (hsfsts.hsf_status.flcdone == 1)
2223                         break;
2224                 udelay(1);
2225         } while (i++ < timeout);
2226
2227         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2228                 return 0;
2229
2230         return ret_val;
2231 }
2232
2233 /**
2234  *  e1000_read_flash_word_ich8lan - Read word from flash
2235  *  @hw: pointer to the HW structure
2236  *  @offset: offset to data location
2237  *  @data: pointer to the location for storing the data
2238  *
2239  *  Reads the flash word at offset into data.  Offset is converted
2240  *  to bytes before read.
2241  **/
2242 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2243                                          u16 *data)
2244 {
2245         /* Must convert offset into bytes. */
2246         offset <<= 1;
2247
2248         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2249 }
2250
2251 /**
2252  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2253  *  @hw: pointer to the HW structure
2254  *  @offset: The offset of the byte to read.
2255  *  @data: Pointer to a byte to store the value read.
2256  *
2257  *  Reads a single byte from the NVM using the flash access registers.
2258  **/
2259 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2260                                          u8 *data)
2261 {
2262         s32 ret_val;
2263         u16 word = 0;
2264
2265         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2266         if (ret_val)
2267                 return ret_val;
2268
2269         *data = (u8)word;
2270
2271         return 0;
2272 }
2273
2274 /**
2275  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2276  *  @hw: pointer to the HW structure
2277  *  @offset: The offset (in bytes) of the byte or word to read.
2278  *  @size: Size of data to read, 1=byte 2=word
2279  *  @data: Pointer to the word to store the value read.
2280  *
2281  *  Reads a byte or word from the NVM using the flash access registers.
2282  **/
2283 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2284                                          u8 size, u16 *data)
2285 {
2286         union ich8_hws_flash_status hsfsts;
2287         union ich8_hws_flash_ctrl hsflctl;
2288         u32 flash_linear_addr;
2289         u32 flash_data = 0;
2290         s32 ret_val = -E1000_ERR_NVM;
2291         u8 count = 0;
2292
2293         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2294                 return -E1000_ERR_NVM;
2295
2296         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2297                             hw->nvm.flash_base_addr;
2298
2299         do {
2300                 udelay(1);
2301                 /* Steps */
2302                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2303                 if (ret_val != 0)
2304                         break;
2305
2306                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2307                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2308                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2309                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2310                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2311
2312                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2313
2314                 ret_val = e1000_flash_cycle_ich8lan(hw,
2315                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2316
2317                 /*
2318                  * Check if FCERR is set to 1, if set to 1, clear it
2319                  * and try the whole sequence a few more times, else
2320                  * read in (shift in) the Flash Data0, the order is
2321                  * least significant byte first msb to lsb
2322                  */
2323                 if (ret_val == 0) {
2324                         flash_data = er32flash(ICH_FLASH_FDATA0);
2325                         if (size == 1)
2326                                 *data = (u8)(flash_data & 0x000000FF);
2327                         else if (size == 2)
2328                                 *data = (u16)(flash_data & 0x0000FFFF);
2329                         break;
2330                 } else {
2331                         /*
2332                          * If we've gotten here, then things are probably
2333                          * completely hosed, but if the error condition is
2334                          * detected, it won't hurt to give it another try...
2335                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2336                          */
2337                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2338                         if (hsfsts.hsf_status.flcerr == 1) {
2339                                 /* Repeat for some time before giving up. */
2340                                 continue;
2341                         } else if (hsfsts.hsf_status.flcdone == 0) {
2342                                 e_dbg("Timeout error - flash cycle "
2343                                          "did not complete.\n");
2344                                 break;
2345                         }
2346                 }
2347         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2348
2349         return ret_val;
2350 }
2351
2352 /**
2353  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2354  *  @hw: pointer to the HW structure
2355  *  @offset: The offset (in bytes) of the word(s) to write.
2356  *  @words: Size of data to write in words
2357  *  @data: Pointer to the word(s) to write at offset.
2358  *
2359  *  Writes a byte or word to the NVM using the flash access registers.
2360  **/
2361 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2362                                    u16 *data)
2363 {
2364         struct e1000_nvm_info *nvm = &hw->nvm;
2365         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2366         u16 i;
2367
2368         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2369             (words == 0)) {
2370                 e_dbg("nvm parameter(s) out of bounds\n");
2371                 return -E1000_ERR_NVM;
2372         }
2373
2374         nvm->ops.acquire(hw);
2375
2376         for (i = 0; i < words; i++) {
2377                 dev_spec->shadow_ram[offset+i].modified = true;
2378                 dev_spec->shadow_ram[offset+i].value = data[i];
2379         }
2380
2381         nvm->ops.release(hw);
2382
2383         return 0;
2384 }
2385
2386 /**
2387  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2388  *  @hw: pointer to the HW structure
2389  *
2390  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2391  *  which writes the checksum to the shadow ram.  The changes in the shadow
2392  *  ram are then committed to the EEPROM by processing each bank at a time
2393  *  checking for the modified bit and writing only the pending changes.
2394  *  After a successful commit, the shadow ram is cleared and is ready for
2395  *  future writes.
2396  **/
2397 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2398 {
2399         struct e1000_nvm_info *nvm = &hw->nvm;
2400         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2401         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2402         s32 ret_val;
2403         u16 data;
2404
2405         ret_val = e1000e_update_nvm_checksum_generic(hw);
2406         if (ret_val)
2407                 goto out;
2408
2409         if (nvm->type != e1000_nvm_flash_sw)
2410                 goto out;
2411
2412         nvm->ops.acquire(hw);
2413
2414         /*
2415          * We're writing to the opposite bank so if we're on bank 1,
2416          * write to bank 0 etc.  We also need to erase the segment that
2417          * is going to be written
2418          */
2419         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2420         if (ret_val) {
2421                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2422                 bank = 0;
2423         }
2424
2425         if (bank == 0) {
2426                 new_bank_offset = nvm->flash_bank_size;
2427                 old_bank_offset = 0;
2428                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2429                 if (ret_val)
2430                         goto release;
2431         } else {
2432                 old_bank_offset = nvm->flash_bank_size;
2433                 new_bank_offset = 0;
2434                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2435                 if (ret_val)
2436                         goto release;
2437         }
2438
2439         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2440                 /*
2441                  * Determine whether to write the value stored
2442                  * in the other NVM bank or a modified value stored
2443                  * in the shadow RAM
2444                  */
2445                 if (dev_spec->shadow_ram[i].modified) {
2446                         data = dev_spec->shadow_ram[i].value;
2447                 } else {
2448                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2449                                                                 old_bank_offset,
2450                                                                 &data);
2451                         if (ret_val)
2452                                 break;
2453                 }
2454
2455                 /*
2456                  * If the word is 0x13, then make sure the signature bits
2457                  * (15:14) are 11b until the commit has completed.
2458                  * This will allow us to write 10b which indicates the
2459                  * signature is valid.  We want to do this after the write
2460                  * has completed so that we don't mark the segment valid
2461                  * while the write is still in progress
2462                  */
2463                 if (i == E1000_ICH_NVM_SIG_WORD)
2464                         data |= E1000_ICH_NVM_SIG_MASK;
2465
2466                 /* Convert offset to bytes. */
2467                 act_offset = (i + new_bank_offset) << 1;
2468
2469                 udelay(100);
2470                 /* Write the bytes to the new bank. */
2471                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2472                                                                act_offset,
2473                                                                (u8)data);
2474                 if (ret_val)
2475                         break;
2476
2477                 udelay(100);
2478                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2479                                                           act_offset + 1,
2480                                                           (u8)(data >> 8));
2481                 if (ret_val)
2482                         break;
2483         }
2484
2485         /*
2486          * Don't bother writing the segment valid bits if sector
2487          * programming failed.
2488          */
2489         if (ret_val) {
2490                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2491                 e_dbg("Flash commit failed.\n");
2492                 goto release;
2493         }
2494
2495         /*
2496          * Finally validate the new segment by setting bit 15:14
2497          * to 10b in word 0x13 , this can be done without an
2498          * erase as well since these bits are 11 to start with
2499          * and we need to change bit 14 to 0b
2500          */
2501         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2502         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2503         if (ret_val)
2504                 goto release;
2505
2506         data &= 0xBFFF;
2507         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2508                                                        act_offset * 2 + 1,
2509                                                        (u8)(data >> 8));
2510         if (ret_val)
2511                 goto release;
2512
2513         /*
2514          * And invalidate the previously valid segment by setting
2515          * its signature word (0x13) high_byte to 0b. This can be
2516          * done without an erase because flash erase sets all bits
2517          * to 1's. We can write 1's to 0's without an erase
2518          */
2519         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2520         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2521         if (ret_val)
2522                 goto release;
2523
2524         /* Great!  Everything worked, we can now clear the cached entries. */
2525         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2526                 dev_spec->shadow_ram[i].modified = false;
2527                 dev_spec->shadow_ram[i].value = 0xFFFF;
2528         }
2529
2530 release:
2531         nvm->ops.release(hw);
2532
2533         /*
2534          * Reload the EEPROM, or else modifications will not appear
2535          * until after the next adapter reset.
2536          */
2537         if (!ret_val) {
2538                 e1000e_reload_nvm(hw);
2539                 usleep_range(10000, 20000);
2540         }
2541
2542 out:
2543         if (ret_val)
2544                 e_dbg("NVM update error: %d\n", ret_val);
2545
2546         return ret_val;
2547 }
2548
2549 /**
2550  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2551  *  @hw: pointer to the HW structure
2552  *
2553  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2554  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2555  *  calculated, in which case we need to calculate the checksum and set bit 6.
2556  **/
2557 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2558 {
2559         s32 ret_val;
2560         u16 data;
2561
2562         /*
2563          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2564          * needs to be fixed.  This bit is an indication that the NVM
2565          * was prepared by OEM software and did not calculate the
2566          * checksum...a likely scenario.
2567          */
2568         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2569         if (ret_val)
2570                 return ret_val;
2571
2572         if ((data & 0x40) == 0) {
2573                 data |= 0x40;
2574                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2575                 if (ret_val)
2576                         return ret_val;
2577                 ret_val = e1000e_update_nvm_checksum(hw);
2578                 if (ret_val)
2579                         return ret_val;
2580         }
2581
2582         return e1000e_validate_nvm_checksum_generic(hw);
2583 }
2584
2585 /**
2586  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2587  *  @hw: pointer to the HW structure
2588  *
2589  *  To prevent malicious write/erase of the NVM, set it to be read-only
2590  *  so that the hardware ignores all write/erase cycles of the NVM via
2591  *  the flash control registers.  The shadow-ram copy of the NVM will
2592  *  still be updated, however any updates to this copy will not stick
2593  *  across driver reloads.
2594  **/
2595 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2596 {
2597         struct e1000_nvm_info *nvm = &hw->nvm;
2598         union ich8_flash_protected_range pr0;
2599         union ich8_hws_flash_status hsfsts;
2600         u32 gfpreg;
2601
2602         nvm->ops.acquire(hw);
2603
2604         gfpreg = er32flash(ICH_FLASH_GFPREG);
2605
2606         /* Write-protect GbE Sector of NVM */
2607         pr0.regval = er32flash(ICH_FLASH_PR0);
2608         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2609         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2610         pr0.range.wpe = true;
2611         ew32flash(ICH_FLASH_PR0, pr0.regval);
2612
2613         /*
2614          * Lock down a subset of GbE Flash Control Registers, e.g.
2615          * PR0 to prevent the write-protection from being lifted.
2616          * Once FLOCKDN is set, the registers protected by it cannot
2617          * be written until FLOCKDN is cleared by a hardware reset.
2618          */
2619         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2620         hsfsts.hsf_status.flockdn = true;
2621         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2622
2623         nvm->ops.release(hw);
2624 }
2625
2626 /**
2627  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2628  *  @hw: pointer to the HW structure
2629  *  @offset: The offset (in bytes) of the byte/word to read.
2630  *  @size: Size of data to read, 1=byte 2=word
2631  *  @data: The byte(s) to write to the NVM.
2632  *
2633  *  Writes one/two bytes to the NVM using the flash access registers.
2634  **/
2635 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2636                                           u8 size, u16 data)
2637 {
2638         union ich8_hws_flash_status hsfsts;
2639         union ich8_hws_flash_ctrl hsflctl;
2640         u32 flash_linear_addr;
2641         u32 flash_data = 0;
2642         s32 ret_val;
2643         u8 count = 0;
2644
2645         if (size < 1 || size > 2 || data > size * 0xff ||
2646             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2647                 return -E1000_ERR_NVM;
2648
2649         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2650                             hw->nvm.flash_base_addr;
2651
2652         do {
2653                 udelay(1);
2654                 /* Steps */
2655                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2656                 if (ret_val)
2657                         break;
2658
2659                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2660                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2661                 hsflctl.hsf_ctrl.fldbcount = size -1;
2662                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2663                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2664
2665                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2666
2667                 if (size == 1)
2668                         flash_data = (u32)data & 0x00FF;
2669                 else
2670                         flash_data = (u32)data;
2671
2672                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2673
2674                 /*
2675                  * check if FCERR is set to 1 , if set to 1, clear it
2676                  * and try the whole sequence a few more times else done
2677                  */
2678                 ret_val = e1000_flash_cycle_ich8lan(hw,
2679                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2680                 if (!ret_val)
2681                         break;
2682
2683                 /*
2684                  * If we're here, then things are most likely
2685                  * completely hosed, but if the error condition
2686                  * is detected, it won't hurt to give it another
2687                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2688                  */
2689                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2690                 if (hsfsts.hsf_status.flcerr == 1)
2691                         /* Repeat for some time before giving up. */
2692                         continue;
2693                 if (hsfsts.hsf_status.flcdone == 0) {
2694                         e_dbg("Timeout error - flash cycle "
2695                                  "did not complete.");
2696                         break;
2697                 }
2698         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2699
2700         return ret_val;
2701 }
2702
2703 /**
2704  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2705  *  @hw: pointer to the HW structure
2706  *  @offset: The index of the byte to read.
2707  *  @data: The byte to write to the NVM.
2708  *
2709  *  Writes a single byte to the NVM using the flash access registers.
2710  **/
2711 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2712                                           u8 data)
2713 {
2714         u16 word = (u16)data;
2715
2716         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2717 }
2718
2719 /**
2720  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2721  *  @hw: pointer to the HW structure
2722  *  @offset: The offset of the byte to write.
2723  *  @byte: The byte to write to the NVM.
2724  *
2725  *  Writes a single byte to the NVM using the flash access registers.
2726  *  Goes through a retry algorithm before giving up.
2727  **/
2728 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2729                                                 u32 offset, u8 byte)
2730 {
2731         s32 ret_val;
2732         u16 program_retries;
2733
2734         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2735         if (!ret_val)
2736                 return ret_val;
2737
2738         for (program_retries = 0; program_retries < 100; program_retries++) {
2739                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2740                 udelay(100);
2741                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2742                 if (!ret_val)
2743                         break;
2744         }
2745         if (program_retries == 100)
2746                 return -E1000_ERR_NVM;
2747
2748         return 0;
2749 }
2750
2751 /**
2752  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2753  *  @hw: pointer to the HW structure
2754  *  @bank: 0 for first bank, 1 for second bank, etc.
2755  *
2756  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2757  *  bank N is 4096 * N + flash_reg_addr.
2758  **/
2759 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2760 {
2761         struct e1000_nvm_info *nvm = &hw->nvm;
2762         union ich8_hws_flash_status hsfsts;
2763         union ich8_hws_flash_ctrl hsflctl;
2764         u32 flash_linear_addr;
2765         /* bank size is in 16bit words - adjust to bytes */
2766         u32 flash_bank_size = nvm->flash_bank_size * 2;
2767         s32 ret_val;
2768         s32 count = 0;
2769         s32 j, iteration, sector_size;
2770
2771         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2772
2773         /*
2774          * Determine HW Sector size: Read BERASE bits of hw flash status
2775          * register
2776          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2777          *     consecutive sectors.  The start index for the nth Hw sector
2778          *     can be calculated as = bank * 4096 + n * 256
2779          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2780          *     The start index for the nth Hw sector can be calculated
2781          *     as = bank * 4096
2782          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2783          *     (ich9 only, otherwise error condition)
2784          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2785          */
2786         switch (hsfsts.hsf_status.berasesz) {
2787         case 0:
2788                 /* Hw sector size 256 */
2789                 sector_size = ICH_FLASH_SEG_SIZE_256;
2790                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2791                 break;
2792         case 1:
2793                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2794                 iteration = 1;
2795                 break;
2796         case 2:
2797                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2798                 iteration = 1;
2799                 break;
2800         case 3:
2801                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2802                 iteration = 1;
2803                 break;
2804         default:
2805                 return -E1000_ERR_NVM;
2806         }
2807
2808         /* Start with the base address, then add the sector offset. */
2809         flash_linear_addr = hw->nvm.flash_base_addr;
2810         flash_linear_addr += (bank) ? flash_bank_size : 0;
2811
2812         for (j = 0; j < iteration ; j++) {
2813                 do {
2814                         /* Steps */
2815                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2816                         if (ret_val)
2817                                 return ret_val;
2818
2819                         /*
2820                          * Write a value 11 (block Erase) in Flash
2821                          * Cycle field in hw flash control
2822                          */
2823                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2824                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2825                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2826
2827                         /*
2828                          * Write the last 24 bits of an index within the
2829                          * block into Flash Linear address field in Flash
2830                          * Address.
2831                          */
2832                         flash_linear_addr += (j * sector_size);
2833                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2834
2835                         ret_val = e1000_flash_cycle_ich8lan(hw,
2836                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2837                         if (ret_val == 0)
2838                                 break;
2839
2840                         /*
2841                          * Check if FCERR is set to 1.  If 1,
2842                          * clear it and try the whole sequence
2843                          * a few more times else Done
2844                          */
2845                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2846                         if (hsfsts.hsf_status.flcerr == 1)
2847                                 /* repeat for some time before giving up */
2848                                 continue;
2849                         else if (hsfsts.hsf_status.flcdone == 0)
2850                                 return ret_val;
2851                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2852         }
2853
2854         return 0;
2855 }
2856
2857 /**
2858  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2859  *  @hw: pointer to the HW structure
2860  *  @data: Pointer to the LED settings
2861  *
2862  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2863  *  settings is all 0's or F's, set the LED default to a valid LED default
2864  *  setting.
2865  **/
2866 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2867 {
2868         s32 ret_val;
2869
2870         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2871         if (ret_val) {
2872                 e_dbg("NVM Read Error\n");
2873                 return ret_val;
2874         }
2875
2876         if (*data == ID_LED_RESERVED_0000 ||
2877             *data == ID_LED_RESERVED_FFFF)
2878                 *data = ID_LED_DEFAULT_ICH8LAN;
2879
2880         return 0;
2881 }
2882
2883 /**
2884  *  e1000_id_led_init_pchlan - store LED configurations
2885  *  @hw: pointer to the HW structure
2886  *
2887  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2888  *  the PHY LED configuration register.
2889  *
2890  *  PCH also does not have an "always on" or "always off" mode which
2891  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2892  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2893  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2894  *  link based on logic in e1000_led_[on|off]_pchlan().
2895  **/
2896 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2897 {
2898         struct e1000_mac_info *mac = &hw->mac;
2899         s32 ret_val;
2900         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2901         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2902         u16 data, i, temp, shift;
2903
2904         /* Get default ID LED modes */
2905         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2906         if (ret_val)
2907                 goto out;
2908
2909         mac->ledctl_default = er32(LEDCTL);
2910         mac->ledctl_mode1 = mac->ledctl_default;
2911         mac->ledctl_mode2 = mac->ledctl_default;
2912
2913         for (i = 0; i < 4; i++) {
2914                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2915                 shift = (i * 5);
2916                 switch (temp) {
2917                 case ID_LED_ON1_DEF2:
2918                 case ID_LED_ON1_ON2:
2919                 case ID_LED_ON1_OFF2:
2920                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2921                         mac->ledctl_mode1 |= (ledctl_on << shift);
2922                         break;
2923                 case ID_LED_OFF1_DEF2:
2924                 case ID_LED_OFF1_ON2:
2925                 case ID_LED_OFF1_OFF2:
2926                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2927                         mac->ledctl_mode1 |= (ledctl_off << shift);
2928                         break;
2929                 default:
2930                         /* Do nothing */
2931                         break;
2932                 }
2933                 switch (temp) {
2934                 case ID_LED_DEF1_ON2:
2935                 case ID_LED_ON1_ON2:
2936                 case ID_LED_OFF1_ON2:
2937                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2938                         mac->ledctl_mode2 |= (ledctl_on << shift);
2939                         break;
2940                 case ID_LED_DEF1_OFF2:
2941                 case ID_LED_ON1_OFF2:
2942                 case ID_LED_OFF1_OFF2:
2943                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2944                         mac->ledctl_mode2 |= (ledctl_off << shift);
2945                         break;
2946                 default:
2947                         /* Do nothing */
2948                         break;
2949                 }
2950         }
2951
2952 out:
2953         return ret_val;
2954 }
2955
2956 /**
2957  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2958  *  @hw: pointer to the HW structure
2959  *
2960  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2961  *  register, so the the bus width is hard coded.
2962  **/
2963 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2964 {
2965         struct e1000_bus_info *bus = &hw->bus;
2966         s32 ret_val;
2967
2968         ret_val = e1000e_get_bus_info_pcie(hw);
2969
2970         /*
2971          * ICH devices are "PCI Express"-ish.  They have
2972          * a configuration space, but do not contain
2973          * PCI Express Capability registers, so bus width
2974          * must be hardcoded.
2975          */
2976         if (bus->width == e1000_bus_width_unknown)
2977                 bus->width = e1000_bus_width_pcie_x1;
2978
2979         return ret_val;
2980 }
2981
2982 /**
2983  *  e1000_reset_hw_ich8lan - Reset the hardware
2984  *  @hw: pointer to the HW structure
2985  *
2986  *  Does a full reset of the hardware which includes a reset of the PHY and
2987  *  MAC.
2988  **/
2989 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2990 {
2991         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2992         u16 reg;
2993         u32 ctrl, kab;
2994         s32 ret_val;
2995
2996         /*
2997          * Prevent the PCI-E bus from sticking if there is no TLP connection
2998          * on the last TLP read/write transaction when MAC is reset.
2999          */
3000         ret_val = e1000e_disable_pcie_master(hw);
3001         if (ret_val)
3002                 e_dbg("PCI-E Master disable polling has failed.\n");
3003
3004         e_dbg("Masking off all interrupts\n");
3005         ew32(IMC, 0xffffffff);
3006
3007         /*
3008          * Disable the Transmit and Receive units.  Then delay to allow
3009          * any pending transactions to complete before we hit the MAC
3010          * with the global reset.
3011          */
3012         ew32(RCTL, 0);
3013         ew32(TCTL, E1000_TCTL_PSP);
3014         e1e_flush();
3015
3016         usleep_range(10000, 20000);
3017
3018         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3019         if (hw->mac.type == e1000_ich8lan) {
3020                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3021                 ew32(PBA, E1000_PBA_8K);
3022                 /* Set Packet Buffer Size to 16k. */
3023                 ew32(PBS, E1000_PBS_16K);
3024         }
3025
3026         if (hw->mac.type == e1000_pchlan) {
3027                 /* Save the NVM K1 bit setting*/
3028                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3029                 if (ret_val)
3030                         return ret_val;
3031
3032                 if (reg & E1000_NVM_K1_ENABLE)
3033                         dev_spec->nvm_k1_enabled = true;
3034                 else
3035                         dev_spec->nvm_k1_enabled = false;
3036         }
3037
3038         ctrl = er32(CTRL);
3039
3040         if (!e1000_check_reset_block(hw)) {
3041                 /*
3042                  * Full-chip reset requires MAC and PHY reset at the same
3043                  * time to make sure the interface between MAC and the
3044                  * external PHY is reset.
3045                  */
3046                 ctrl |= E1000_CTRL_PHY_RST;
3047
3048                 /*
3049                  * Gate automatic PHY configuration by hardware on
3050                  * non-managed 82579
3051                  */
3052                 if ((hw->mac.type == e1000_pch2lan) &&
3053                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3054                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3055         }
3056         ret_val = e1000_acquire_swflag_ich8lan(hw);
3057         e_dbg("Issuing a global reset to ich8lan\n");
3058         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3059         msleep(20);
3060
3061         if (!ret_val)
3062                 e1000_release_swflag_ich8lan(hw);
3063
3064         if (ctrl & E1000_CTRL_PHY_RST) {
3065                 ret_val = hw->phy.ops.get_cfg_done(hw);
3066                 if (ret_val)
3067                         goto out;
3068
3069                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3070                 if (ret_val)
3071                         goto out;
3072         }
3073
3074         /*
3075          * For PCH, this write will make sure that any noise
3076          * will be detected as a CRC error and be dropped rather than show up
3077          * as a bad packet to the DMA engine.
3078          */
3079         if (hw->mac.type == e1000_pchlan)
3080                 ew32(CRC_OFFSET, 0x65656565);
3081
3082         ew32(IMC, 0xffffffff);
3083         er32(ICR);
3084
3085         kab = er32(KABGTXD);
3086         kab |= E1000_KABGTXD_BGSQLBIAS;
3087         ew32(KABGTXD, kab);
3088
3089 out:
3090         return ret_val;
3091 }
3092
3093 /**
3094  *  e1000_init_hw_ich8lan - Initialize the hardware
3095  *  @hw: pointer to the HW structure
3096  *
3097  *  Prepares the hardware for transmit and receive by doing the following:
3098  *   - initialize hardware bits
3099  *   - initialize LED identification
3100  *   - setup receive address registers
3101  *   - setup flow control
3102  *   - setup transmit descriptors
3103  *   - clear statistics
3104  **/
3105 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3106 {
3107         struct e1000_mac_info *mac = &hw->mac;
3108         u32 ctrl_ext, txdctl, snoop;
3109         s32 ret_val;
3110         u16 i;
3111
3112         e1000_initialize_hw_bits_ich8lan(hw);
3113
3114         /* Initialize identification LED */
3115         ret_val = mac->ops.id_led_init(hw);
3116         if (ret_val)
3117                 e_dbg("Error initializing identification LED\n");
3118                 /* This is not fatal and we should not stop init due to this */
3119
3120         /* Setup the receive address. */
3121         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3122
3123         /* Zero out the Multicast HASH table */
3124         e_dbg("Zeroing the MTA\n");
3125         for (i = 0; i < mac->mta_reg_count; i++)
3126                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3127
3128         /*
3129          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3130          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
3131          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3132          */
3133         if (hw->phy.type == e1000_phy_82578) {
3134                 e1e_rphy(hw, BM_WUC, &i);
3135                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3136                 if (ret_val)
3137                         return ret_val;
3138         }
3139
3140         /* Setup link and flow control */
3141         ret_val = e1000_setup_link_ich8lan(hw);
3142
3143         /* Set the transmit descriptor write-back policy for both queues */
3144         txdctl = er32(TXDCTL(0));
3145         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3146                  E1000_TXDCTL_FULL_TX_DESC_WB;
3147         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3148                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3149         ew32(TXDCTL(0), txdctl);
3150         txdctl = er32(TXDCTL(1));
3151         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3152                  E1000_TXDCTL_FULL_TX_DESC_WB;
3153         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3154                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3155         ew32(TXDCTL(1), txdctl);
3156
3157         /*
3158          * ICH8 has opposite polarity of no_snoop bits.
3159          * By default, we should use snoop behavior.
3160          */
3161         if (mac->type == e1000_ich8lan)
3162                 snoop = PCIE_ICH8_SNOOP_ALL;
3163         else
3164                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3165         e1000e_set_pcie_no_snoop(hw, snoop);
3166
3167         ctrl_ext = er32(CTRL_EXT);
3168         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3169         ew32(CTRL_EXT, ctrl_ext);
3170
3171         /*
3172          * Clear all of the statistics registers (clear on read).  It is
3173          * important that we do this after we have tried to establish link
3174          * because the symbol error count will increment wildly if there
3175          * is no link.
3176          */
3177         e1000_clear_hw_cntrs_ich8lan(hw);
3178
3179         return 0;
3180 }
3181 /**
3182  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3183  *  @hw: pointer to the HW structure
3184  *
3185  *  Sets/Clears required hardware bits necessary for correctly setting up the
3186  *  hardware for transmit and receive.
3187  **/
3188 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3189 {
3190         u32 reg;
3191
3192         /* Extended Device Control */
3193         reg = er32(CTRL_EXT);
3194         reg |= (1 << 22);
3195         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3196         if (hw->mac.type >= e1000_pchlan)
3197                 reg |= E1000_CTRL_EXT_PHYPDEN;
3198         ew32(CTRL_EXT, reg);
3199
3200         /* Transmit Descriptor Control 0 */
3201         reg = er32(TXDCTL(0));
3202         reg |= (1 << 22);
3203         ew32(TXDCTL(0), reg);
3204
3205         /* Transmit Descriptor Control 1 */
3206         reg = er32(TXDCTL(1));
3207         reg |= (1 << 22);
3208         ew32(TXDCTL(1), reg);
3209
3210         /* Transmit Arbitration Control 0 */
3211         reg = er32(TARC(0));
3212         if (hw->mac.type == e1000_ich8lan)
3213                 reg |= (1 << 28) | (1 << 29);
3214         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3215         ew32(TARC(0), reg);
3216
3217         /* Transmit Arbitration Control 1 */
3218         reg = er32(TARC(1));
3219         if (er32(TCTL) & E1000_TCTL_MULR)
3220                 reg &= ~(1 << 28);
3221         else
3222                 reg |= (1 << 28);
3223         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3224         ew32(TARC(1), reg);
3225
3226         /* Device Status */
3227         if (hw->mac.type == e1000_ich8lan) {
3228                 reg = er32(STATUS);
3229                 reg &= ~(1 << 31);
3230                 ew32(STATUS, reg);
3231         }
3232
3233         /*
3234          * work-around descriptor data corruption issue during nfs v2 udp
3235          * traffic, just disable the nfs filtering capability
3236          */
3237         reg = er32(RFCTL);
3238         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3239         ew32(RFCTL, reg);
3240 }
3241
3242 /**
3243  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3244  *  @hw: pointer to the HW structure
3245  *
3246  *  Determines which flow control settings to use, then configures flow
3247  *  control.  Calls the appropriate media-specific link configuration
3248  *  function.  Assuming the adapter has a valid link partner, a valid link
3249  *  should be established.  Assumes the hardware has previously been reset
3250  *  and the transmitter and receiver are not enabled.
3251  **/
3252 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3253 {
3254         s32 ret_val;
3255
3256         if (e1000_check_reset_block(hw))
3257                 return 0;
3258
3259         /*
3260          * ICH parts do not have a word in the NVM to determine
3261          * the default flow control setting, so we explicitly
3262          * set it to full.
3263          */
3264         if (hw->fc.requested_mode == e1000_fc_default) {
3265                 /* Workaround h/w hang when Tx flow control enabled */
3266                 if (hw->mac.type == e1000_pchlan)
3267                         hw->fc.requested_mode = e1000_fc_rx_pause;
3268                 else
3269                         hw->fc.requested_mode = e1000_fc_full;
3270         }
3271
3272         /*
3273          * Save off the requested flow control mode for use later.  Depending
3274          * on the link partner's capabilities, we may or may not use this mode.
3275          */
3276         hw->fc.current_mode = hw->fc.requested_mode;
3277
3278         e_dbg("After fix-ups FlowControl is now = %x\n",
3279                 hw->fc.current_mode);
3280
3281         /* Continue to configure the copper link. */
3282         ret_val = e1000_setup_copper_link_ich8lan(hw);
3283         if (ret_val)
3284                 return ret_val;
3285
3286         ew32(FCTTV, hw->fc.pause_time);
3287         if ((hw->phy.type == e1000_phy_82578) ||
3288             (hw->phy.type == e1000_phy_82579) ||
3289             (hw->phy.type == e1000_phy_82577)) {
3290                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3291
3292                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3293                                    hw->fc.pause_time);
3294                 if (ret_val)
3295                         return ret_val;
3296         }
3297
3298         return e1000e_set_fc_watermarks(hw);
3299 }
3300
3301 /**
3302  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3303  *  @hw: pointer to the HW structure
3304  *
3305  *  Configures the kumeran interface to the PHY to wait the appropriate time
3306  *  when polling the PHY, then call the generic setup_copper_link to finish
3307  *  configuring the copper link.
3308  **/
3309 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3310 {
3311         u32 ctrl;
3312         s32 ret_val;
3313         u16 reg_data;
3314
3315         ctrl = er32(CTRL);
3316         ctrl |= E1000_CTRL_SLU;
3317         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3318         ew32(CTRL, ctrl);
3319
3320         /*
3321          * Set the mac to wait the maximum time between each iteration
3322          * and increase the max iterations when polling the phy;
3323          * this fixes erroneous timeouts at 10Mbps.
3324          */
3325         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3326         if (ret_val)
3327                 return ret_val;
3328         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3329                                        &reg_data);
3330         if (ret_val)
3331                 return ret_val;
3332         reg_data |= 0x3F;
3333         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3334                                         reg_data);
3335         if (ret_val)
3336                 return ret_val;
3337
3338         switch (hw->phy.type) {
3339         case e1000_phy_igp_3:
3340                 ret_val = e1000e_copper_link_setup_igp(hw);
3341                 if (ret_val)
3342                         return ret_val;
3343                 break;
3344         case e1000_phy_bm:
3345         case e1000_phy_82578:
3346                 ret_val = e1000e_copper_link_setup_m88(hw);
3347                 if (ret_val)
3348                         return ret_val;
3349                 break;
3350         case e1000_phy_82577:
3351         case e1000_phy_82579:
3352                 ret_val = e1000_copper_link_setup_82577(hw);
3353                 if (ret_val)
3354                         return ret_val;
3355                 break;
3356         case e1000_phy_ife:
3357                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3358                 if (ret_val)
3359                         return ret_val;
3360
3361                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3362
3363                 switch (hw->phy.mdix) {
3364                 case 1:
3365                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3366                         break;
3367                 case 2:
3368                         reg_data |= IFE_PMC_FORCE_MDIX;
3369                         break;
3370                 case 0:
3371                 default:
3372                         reg_data |= IFE_PMC_AUTO_MDIX;
3373                         break;
3374                 }
3375                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3376                 if (ret_val)
3377                         return ret_val;
3378                 break;
3379         default:
3380                 break;
3381         }
3382         return e1000e_setup_copper_link(hw);
3383 }
3384
3385 /**
3386  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3387  *  @hw: pointer to the HW structure
3388  *  @speed: pointer to store current link speed
3389  *  @duplex: pointer to store the current link duplex
3390  *
3391  *  Calls the generic get_speed_and_duplex to retrieve the current link
3392  *  information and then calls the Kumeran lock loss workaround for links at
3393  *  gigabit speeds.
3394  **/
3395 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3396                                           u16 *duplex)
3397 {
3398         s32 ret_val;
3399
3400         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3401         if (ret_val)
3402                 return ret_val;
3403
3404         if ((hw->mac.type == e1000_ich8lan) &&
3405             (hw->phy.type == e1000_phy_igp_3) &&
3406             (*speed == SPEED_1000)) {
3407                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3408         }
3409
3410         return ret_val;
3411 }
3412
3413 /**
3414  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3415  *  @hw: pointer to the HW structure
3416  *
3417  *  Work-around for 82566 Kumeran PCS lock loss:
3418  *  On link status change (i.e. PCI reset, speed change) and link is up and
3419  *  speed is gigabit-
3420  *    0) if workaround is optionally disabled do nothing
3421  *    1) wait 1ms for Kumeran link to come up
3422  *    2) check Kumeran Diagnostic register PCS lock loss bit
3423  *    3) if not set the link is locked (all is good), otherwise...
3424  *    4) reset the PHY
3425  *    5) repeat up to 10 times
3426  *  Note: this is only called for IGP3 copper when speed is 1gb.
3427  **/
3428 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3429 {
3430         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3431         u32 phy_ctrl;
3432         s32 ret_val;
3433         u16 i, data;
3434         bool link;
3435
3436         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3437                 return 0;
3438
3439         /*
3440          * Make sure link is up before proceeding.  If not just return.
3441          * Attempting this while link is negotiating fouled up link
3442          * stability
3443          */
3444         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3445         if (!link)
3446                 return 0;
3447
3448         for (i = 0; i < 10; i++) {
3449                 /* read once to clear */
3450                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3451                 if (ret_val)
3452                         return ret_val;
3453                 /* and again to get new status */
3454                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3455                 if (ret_val)
3456                         return ret_val;
3457
3458                 /* check for PCS lock */
3459                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3460                         return 0;
3461
3462                 /* Issue PHY reset */
3463                 e1000_phy_hw_reset(hw);
3464                 mdelay(5);
3465         }
3466         /* Disable GigE link negotiation */
3467         phy_ctrl = er32(PHY_CTRL);
3468         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3469                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3470         ew32(PHY_CTRL, phy_ctrl);
3471
3472         /*
3473          * Call gig speed drop workaround on Gig disable before accessing
3474          * any PHY registers
3475          */
3476         e1000e_gig_downshift_workaround_ich8lan(hw);
3477
3478         /* unable to acquire PCS lock */
3479         return -E1000_ERR_PHY;
3480 }
3481
3482 /**
3483  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3484  *  @hw: pointer to the HW structure
3485  *  @state: boolean value used to set the current Kumeran workaround state
3486  *
3487  *  If ICH8, set the current Kumeran workaround state (enabled - true
3488  *  /disabled - false).
3489  **/
3490 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3491                                                  bool state)
3492 {
3493         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3494
3495         if (hw->mac.type != e1000_ich8lan) {
3496                 e_dbg("Workaround applies to ICH8 only.\n");
3497                 return;
3498         }
3499
3500         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3501 }
3502
3503 /**
3504  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3505  *  @hw: pointer to the HW structure
3506  *
3507  *  Workaround for 82566 power-down on D3 entry:
3508  *    1) disable gigabit link
3509  *    2) write VR power-down enable
3510  *    3) read it back
3511  *  Continue if successful, else issue LCD reset and repeat
3512  **/
3513 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3514 {
3515         u32 reg;
3516         u16 data;
3517         u8  retry = 0;
3518
3519         if (hw->phy.type != e1000_phy_igp_3)
3520                 return;
3521
3522         /* Try the workaround twice (if needed) */
3523         do {
3524                 /* Disable link */
3525                 reg = er32(PHY_CTRL);
3526                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3527                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3528                 ew32(PHY_CTRL, reg);
3529
3530                 /*
3531                  * Call gig speed drop workaround on Gig disable before
3532                  * accessing any PHY registers
3533                  */
3534                 if (hw->mac.type == e1000_ich8lan)
3535                         e1000e_gig_downshift_workaround_ich8lan(hw);
3536
3537                 /* Write VR power-down enable */
3538                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3539                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3540                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3541
3542                 /* Read it back and test */
3543                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3544                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3545                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3546                         break;
3547
3548                 /* Issue PHY reset and repeat at most one more time */
3549                 reg = er32(CTRL);
3550                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3551                 retry++;
3552         } while (retry);
3553 }
3554
3555 /**
3556  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3557  *  @hw: pointer to the HW structure
3558  *
3559  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3560  *  LPLU, Gig disable, MDIC PHY reset):
3561  *    1) Set Kumeran Near-end loopback
3562  *    2) Clear Kumeran Near-end loopback
3563  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3564  **/
3565 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3566 {
3567         s32 ret_val;
3568         u16 reg_data;
3569
3570         if ((hw->mac.type != e1000_ich8lan) ||
3571             (hw->phy.type != e1000_phy_igp_3))
3572                 return;
3573
3574         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3575                                       &reg_data);
3576         if (ret_val)
3577                 return;
3578         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3579         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3580                                        reg_data);
3581         if (ret_val)
3582                 return;
3583         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3584         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3585                                        reg_data);
3586 }
3587
3588 /**
3589  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3590  *  @hw: pointer to the HW structure
3591  *
3592  *  During S0 to Sx transition, it is possible the link remains at gig
3593  *  instead of negotiating to a lower speed.  Before going to Sx, set
3594  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3595  *  to a lower speed.
3596  *
3597  *  Should only be called for applicable parts.
3598  **/
3599 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3600 {
3601         u32 phy_ctrl;
3602         s32 ret_val;
3603
3604         phy_ctrl = er32(PHY_CTRL);
3605         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3606         ew32(PHY_CTRL, phy_ctrl);
3607
3608         if (hw->mac.type >= e1000_pchlan) {
3609                 e1000_oem_bits_config_ich8lan(hw, false);
3610                 ret_val = hw->phy.ops.acquire(hw);
3611                 if (ret_val)
3612                         return;
3613                 e1000_write_smbus_addr(hw);
3614                 hw->phy.ops.release(hw);
3615         }
3616 }
3617
3618 /**
3619  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3620  *  @hw: pointer to the HW structure
3621  *
3622  *  Return the LED back to the default configuration.
3623  **/
3624 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3625 {
3626         if (hw->phy.type == e1000_phy_ife)
3627                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3628
3629         ew32(LEDCTL, hw->mac.ledctl_default);
3630         return 0;
3631 }
3632
3633 /**
3634  *  e1000_led_on_ich8lan - Turn LEDs on
3635  *  @hw: pointer to the HW structure
3636  *
3637  *  Turn on the LEDs.
3638  **/
3639 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3640 {
3641         if (hw->phy.type == e1000_phy_ife)
3642                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3643                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3644
3645         ew32(LEDCTL, hw->mac.ledctl_mode2);
3646         return 0;
3647 }
3648
3649 /**
3650  *  e1000_led_off_ich8lan - Turn LEDs off
3651  *  @hw: pointer to the HW structure
3652  *
3653  *  Turn off the LEDs.
3654  **/
3655 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3656 {
3657         if (hw->phy.type == e1000_phy_ife)
3658                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3659                                 (IFE_PSCL_PROBE_MODE |
3660                                  IFE_PSCL_PROBE_LEDS_OFF));
3661
3662         ew32(LEDCTL, hw->mac.ledctl_mode1);
3663         return 0;
3664 }
3665
3666 /**
3667  *  e1000_setup_led_pchlan - Configures SW controllable LED
3668  *  @hw: pointer to the HW structure
3669  *
3670  *  This prepares the SW controllable LED for use.
3671  **/
3672 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3673 {
3674         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3675 }
3676
3677 /**
3678  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3679  *  @hw: pointer to the HW structure
3680  *
3681  *  Return the LED back to the default configuration.
3682  **/
3683 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3684 {
3685         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3686 }
3687
3688 /**
3689  *  e1000_led_on_pchlan - Turn LEDs on
3690  *  @hw: pointer to the HW structure
3691  *
3692  *  Turn on the LEDs.
3693  **/
3694 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3695 {
3696         u16 data = (u16)hw->mac.ledctl_mode2;
3697         u32 i, led;
3698
3699         /*
3700          * If no link, then turn LED on by setting the invert bit
3701          * for each LED that's mode is "link_up" in ledctl_mode2.
3702          */
3703         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3704                 for (i = 0; i < 3; i++) {
3705                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3706                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3707                             E1000_LEDCTL_MODE_LINK_UP)
3708                                 continue;
3709                         if (led & E1000_PHY_LED0_IVRT)
3710                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3711                         else
3712                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3713                 }
3714         }
3715
3716         return e1e_wphy(hw, HV_LED_CONFIG, data);
3717 }
3718
3719 /**
3720  *  e1000_led_off_pchlan - Turn LEDs off
3721  *  @hw: pointer to the HW structure
3722  *
3723  *  Turn off the LEDs.
3724  **/
3725 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3726 {
3727         u16 data = (u16)hw->mac.ledctl_mode1;
3728         u32 i, led;
3729
3730         /*
3731          * If no link, then turn LED off by clearing the invert bit
3732          * for each LED that's mode is "link_up" in ledctl_mode1.
3733          */
3734         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3735                 for (i = 0; i < 3; i++) {
3736                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3737                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3738                             E1000_LEDCTL_MODE_LINK_UP)
3739                                 continue;
3740                         if (led & E1000_PHY_LED0_IVRT)
3741                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3742                         else
3743                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3744                 }
3745         }
3746
3747         return e1e_wphy(hw, HV_LED_CONFIG, data);
3748 }
3749
3750 /**
3751  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3752  *  @hw: pointer to the HW structure
3753  *
3754  *  Read appropriate register for the config done bit for completion status
3755  *  and configure the PHY through s/w for EEPROM-less parts.
3756  *
3757  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3758  *  config done bit, so only an error is logged and continues.  If we were
3759  *  to return with error, EEPROM-less silicon would not be able to be reset
3760  *  or change link.
3761  **/
3762 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3763 {
3764         s32 ret_val = 0;
3765         u32 bank = 0;
3766         u32 status;
3767
3768         e1000e_get_cfg_done(hw);
3769
3770         /* Wait for indication from h/w that it has completed basic config */
3771         if (hw->mac.type >= e1000_ich10lan) {
3772                 e1000_lan_init_done_ich8lan(hw);
3773         } else {
3774                 ret_val = e1000e_get_auto_rd_done(hw);
3775                 if (ret_val) {
3776                         /*
3777                          * When auto config read does not complete, do not
3778                          * return with an error. This can happen in situations
3779                          * where there is no eeprom and prevents getting link.
3780                          */
3781                         e_dbg("Auto Read Done did not complete\n");
3782                         ret_val = 0;
3783                 }
3784         }
3785
3786         /* Clear PHY Reset Asserted bit */
3787         status = er32(STATUS);
3788         if (status & E1000_STATUS_PHYRA)
3789                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3790         else
3791                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3792
3793         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3794         if (hw->mac.type <= e1000_ich9lan) {
3795                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3796                     (hw->phy.type == e1000_phy_igp_3)) {
3797                         e1000e_phy_init_script_igp3(hw);
3798                 }
3799         } else {
3800                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3801                         /* Maybe we should do a basic PHY config */
3802                         e_dbg("EEPROM not present\n");
3803                         ret_val = -E1000_ERR_CONFIG;
3804                 }
3805         }
3806
3807         return ret_val;
3808 }
3809
3810 /**
3811  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3812  * @hw: pointer to the HW structure
3813  *
3814  * In the case of a PHY power down to save power, or to turn off link during a
3815  * driver unload, or wake on lan is not enabled, remove the link.
3816  **/
3817 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3818 {
3819         /* If the management interface is not enabled, then power down */
3820         if (!(hw->mac.ops.check_mng_mode(hw) ||
3821               hw->phy.ops.check_reset_block(hw)))
3822                 e1000_power_down_phy_copper(hw);
3823 }
3824
3825 /**
3826  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3827  *  @hw: pointer to the HW structure
3828  *
3829  *  Clears hardware counters specific to the silicon family and calls
3830  *  clear_hw_cntrs_generic to clear all general purpose counters.
3831  **/
3832 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3833 {
3834         u16 phy_data;
3835
3836         e1000e_clear_hw_cntrs_base(hw);
3837
3838         er32(ALGNERRC);
3839         er32(RXERRC);
3840         er32(TNCRS);
3841         er32(CEXTERR);
3842         er32(TSCTC);
3843         er32(TSCTFC);
3844
3845         er32(MGTPRC);
3846         er32(MGTPDC);
3847         er32(MGTPTC);
3848
3849         er32(IAC);
3850         er32(ICRXOC);
3851
3852         /* Clear PHY statistics registers */
3853         if ((hw->phy.type == e1000_phy_82578) ||
3854             (hw->phy.type == e1000_phy_82579) ||
3855             (hw->phy.type == e1000_phy_82577)) {
3856                 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3857                 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3858                 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3859                 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3860                 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3861                 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3862                 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3863                 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3864                 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3865                 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3866                 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3867                 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3868                 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3869                 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3870         }
3871 }
3872
3873 static struct e1000_mac_operations ich8_mac_ops = {
3874         .id_led_init            = e1000e_id_led_init,
3875         /* check_mng_mode dependent on mac type */
3876         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3877         /* cleanup_led dependent on mac type */
3878         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3879         .get_bus_info           = e1000_get_bus_info_ich8lan,
3880         .set_lan_id             = e1000_set_lan_id_single_port,
3881         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3882         /* led_on dependent on mac type */
3883         /* led_off dependent on mac type */
3884         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3885         .reset_hw               = e1000_reset_hw_ich8lan,
3886         .init_hw                = e1000_init_hw_ich8lan,
3887         .setup_link             = e1000_setup_link_ich8lan,
3888         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3889         /* id_led_init dependent on mac type */
3890 };
3891
3892 static struct e1000_phy_operations ich8_phy_ops = {
3893         .acquire                = e1000_acquire_swflag_ich8lan,
3894         .check_reset_block      = e1000_check_reset_block_ich8lan,
3895         .commit                 = NULL,
3896         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3897         .get_cable_length       = e1000e_get_cable_length_igp_2,
3898         .read_reg               = e1000e_read_phy_reg_igp,
3899         .release                = e1000_release_swflag_ich8lan,
3900         .reset                  = e1000_phy_hw_reset_ich8lan,
3901         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3902         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3903         .write_reg              = e1000e_write_phy_reg_igp,
3904 };
3905
3906 static struct e1000_nvm_operations ich8_nvm_ops = {
3907         .acquire                = e1000_acquire_nvm_ich8lan,
3908         .read                   = e1000_read_nvm_ich8lan,
3909         .release                = e1000_release_nvm_ich8lan,
3910         .update                 = e1000_update_nvm_checksum_ich8lan,
3911         .valid_led_default      = e1000_valid_led_default_ich8lan,
3912         .validate               = e1000_validate_nvm_checksum_ich8lan,
3913         .write                  = e1000_write_nvm_ich8lan,
3914 };
3915
3916 struct e1000_info e1000_ich8_info = {
3917         .mac                    = e1000_ich8lan,
3918         .flags                  = FLAG_HAS_WOL
3919                                   | FLAG_IS_ICH
3920                                   | FLAG_RX_CSUM_ENABLED
3921                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3922                                   | FLAG_HAS_AMT
3923                                   | FLAG_HAS_FLASH
3924                                   | FLAG_APME_IN_WUC,
3925         .pba                    = 8,
3926         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3927         .get_variants           = e1000_get_variants_ich8lan,
3928         .mac_ops                = &ich8_mac_ops,
3929         .phy_ops                = &ich8_phy_ops,
3930         .nvm_ops                = &ich8_nvm_ops,
3931 };
3932
3933 struct e1000_info e1000_ich9_info = {
3934         .mac                    = e1000_ich9lan,
3935         .flags                  = FLAG_HAS_JUMBO_FRAMES
3936                                   | FLAG_IS_ICH
3937                                   | FLAG_HAS_WOL
3938                                   | FLAG_RX_CSUM_ENABLED
3939                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3940                                   | FLAG_HAS_AMT
3941                                   | FLAG_HAS_ERT
3942                                   | FLAG_HAS_FLASH
3943                                   | FLAG_APME_IN_WUC,
3944         .pba                    = 10,
3945         .max_hw_frame_size      = DEFAULT_JUMBO,
3946         .get_variants           = e1000_get_variants_ich8lan,
3947         .mac_ops                = &ich8_mac_ops,
3948         .phy_ops                = &ich8_phy_ops,
3949         .nvm_ops                = &ich8_nvm_ops,
3950 };
3951
3952 struct e1000_info e1000_ich10_info = {
3953         .mac                    = e1000_ich10lan,
3954         .flags                  = FLAG_HAS_JUMBO_FRAMES
3955                                   | FLAG_IS_ICH
3956                                   | FLAG_HAS_WOL
3957                                   | FLAG_RX_CSUM_ENABLED
3958                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3959                                   | FLAG_HAS_AMT
3960                                   | FLAG_HAS_ERT
3961                                   | FLAG_HAS_FLASH
3962                                   | FLAG_APME_IN_WUC,
3963         .pba                    = 10,
3964         .max_hw_frame_size      = DEFAULT_JUMBO,
3965         .get_variants           = e1000_get_variants_ich8lan,
3966         .mac_ops                = &ich8_mac_ops,
3967         .phy_ops                = &ich8_phy_ops,
3968         .nvm_ops                = &ich8_nvm_ops,
3969 };
3970
3971 struct e1000_info e1000_pch_info = {
3972         .mac                    = e1000_pchlan,
3973         .flags                  = FLAG_IS_ICH
3974                                   | FLAG_HAS_WOL
3975                                   | FLAG_RX_CSUM_ENABLED
3976                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3977                                   | FLAG_HAS_AMT
3978                                   | FLAG_HAS_FLASH
3979                                   | FLAG_HAS_JUMBO_FRAMES
3980                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3981                                   | FLAG_APME_IN_WUC,
3982         .flags2                 = FLAG2_HAS_PHY_STATS,
3983         .pba                    = 26,
3984         .max_hw_frame_size      = 4096,
3985         .get_variants           = e1000_get_variants_ich8lan,
3986         .mac_ops                = &ich8_mac_ops,
3987         .phy_ops                = &ich8_phy_ops,
3988         .nvm_ops                = &ich8_nvm_ops,
3989 };
3990
3991 struct e1000_info e1000_pch2_info = {
3992         .mac                    = e1000_pch2lan,
3993         .flags                  = FLAG_IS_ICH
3994                                   | FLAG_HAS_WOL
3995                                   | FLAG_RX_CSUM_ENABLED
3996                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3997                                   | FLAG_HAS_AMT
3998                                   | FLAG_HAS_FLASH
3999                                   | FLAG_HAS_JUMBO_FRAMES
4000                                   | FLAG_APME_IN_WUC,
4001         .flags2                 = FLAG2_HAS_PHY_STATS
4002                                   | FLAG2_HAS_EEE,
4003         .pba                    = 26,
4004         .max_hw_frame_size      = DEFAULT_JUMBO,
4005         .get_variants           = e1000_get_variants_ich8lan,
4006         .mac_ops                = &ich8_mac_ops,
4007         .phy_ops                = &ich8_phy_ops,
4008         .nvm_ops                = &ich8_nvm_ops,
4009 };