drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* EMI Registers */
 144 #define I82579_EMI_ADDR         0x10
 145 #define I82579_EMI_DATA         0x11
 146 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 147
 148 /* Strapping Option Register - RO */
 149 #define E1000_STRAP                     0x0000C
 150 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 152
 153 /* OEM Bits Phy Register */
 154 #define HV_OEM_BITS            PHY_REG(768, 25)
 155 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 156 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 158
 159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 160 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 161
 162 /* KMRN Mode Control */
 163 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 164 #define HV_KMRN_MDIO_SLOW      0x0400
 165
 166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 167 /* Offset 04h HSFSTS */
 168 union ich8_hws_flash_status {
 169         struct ich8_hsfsts {
 170                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 171                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 172                 u16 dael       :1; /* bit 2 Direct Access error Log */
 173                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 174                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 175                 u16 reserved1  :2; /* bit 13:6 Reserved */
 176                 u16 reserved2  :6; /* bit 13:6 Reserved */
 177                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 178                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 179         } hsf_status;
 180         u16 regval;
 181 };
 182
 183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 184 /* Offset 06h FLCTL */
 185 union ich8_hws_flash_ctrl {
 186         struct ich8_hsflctl {
 187                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 188                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 189                 u16 reserved   :5;   /* 7:3 Reserved  */
 190                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 191                 u16 flockdn    :6;   /* 15:10 Reserved */
 192         } hsf_ctrl;
 193         u16 regval;
 194 };
 195
 196 /* ICH Flash Region Access Permissions */
 197 union ich8_hws_flash_regacc {
 198         struct ich8_flracc {
 199                 u32 grra      :8; /* 0:7 GbE region Read Access */
 200                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 201                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 202                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 203         } hsf_flregacc;
 204         u16 regval;
 205 };
 206
 207 /* ICH Flash Protected Region */
 208 union ich8_flash_protected_range {
 209         struct ich8_pr {
 210                 u32 base:13;     /* 0:12 Protected Range Base */
 211                 u32 reserved1:2; /* 13:14 Reserved */
 212                 u32 rpe:1;       /* 15 Read Protection Enable */
 213                 u32 limit:13;    /* 16:28 Protected Range Limit */
 214                 u32 reserved2:2; /* 29:30 Reserved */
 215                 u32 wpe:1;       /* 31 Write Protection Enable */
 216         } range;
 217         u32 regval;
 218 };
 219
 220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 225                                                 u32 offset, u8 byte);
 226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 227                                          u8 *data);
 228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 229                                          u16 *data);
 230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 231                                          u8 size, u16 *data);
 232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 246 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 252
 253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 254 {
 255         return readw(hw->flash_address + reg);
 256 }
 257
 258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 259 {
 260         return readl(hw->flash_address + reg);
 261 }
 262
 263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 264 {
 265         writew(val, hw->flash_address + reg);
 266 }
 267
 268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 269 {
 270         writel(val, hw->flash_address + reg);
 271 }
 272
 273 #define er16flash(reg)          __er16flash(hw, (reg))
 274 #define er32flash(reg)          __er32flash(hw, (reg))
 275 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 276 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 277
 278 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 279 {
 280         u32 ctrl;
 281
 282         ctrl = er32(CTRL);
 283         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 284         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 285         ew32(CTRL, ctrl);
 286         udelay(10);
 287         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 288         ew32(CTRL, ctrl);
 289 }
 290
 291 /**
 292  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 293  *  @hw: pointer to the HW structure
 294  *
 295  *  Initialize family-specific PHY parameters and function pointers.
 296  **/
 297 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 298 {
 299         struct e1000_phy_info *phy = &hw->phy;
 300         u32 fwsm;
 301         s32 ret_val = 0;
 302
 303         phy->addr                     = 1;
 304         phy->reset_delay_us           = 100;
 305
 306         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 307         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 308         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 309         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 310         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 311         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 312         phy->ops.power_up             = e1000_power_up_phy_copper;
 313         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 314         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 315
 316         /*
 317          * The MAC-PHY interconnect may still be in SMBus mode
 318          * after Sx->S0.  If the manageability engine (ME) is
 319          * disabled, then toggle the LANPHYPC Value bit to force
 320          * the interconnect to PCIe mode.
 321          */
 322         fwsm = er32(FWSM);
 323         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 324                 e1000_toggle_lanphypc_value_ich8lan(hw);
 325                 msleep(50);
 326
 327                 /*
 328                  * Gate automatic PHY configuration by hardware on
 329                  * non-managed 82579
 330                  */
 331                 if (hw->mac.type == e1000_pch2lan)
 332                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 333         }
 334
 335         /*
 336          * Reset the PHY before any access to it.  Doing so, ensures that
 337          * the PHY is in a known good state before we read/write PHY registers.
 338          * The generic reset is sufficient here, because we haven't determined
 339          * the PHY type yet.
 340          */
 341         ret_val = e1000e_phy_hw_reset_generic(hw);
 342         if (ret_val)
 343                 goto out;
 344
 345         /* Ungate automatic PHY configuration on non-managed 82579 */
 346         if ((hw->mac.type == e1000_pch2lan) &&
 347             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 348                 usleep_range(10000, 20000);
 349                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 350         }
 351
 352         phy->id = e1000_phy_unknown;
 353         switch (hw->mac.type) {
 354         default:
 355                 ret_val = e1000e_get_phy_id(hw);
 356                 if (ret_val)
 357                         goto out;
 358                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 359                         break;
 360                 /* fall-through */
 361         case e1000_pch2lan:
 362                 /*
 363                  * In case the PHY needs to be in mdio slow mode,
 364                  * set slow mode and try to get the PHY id again.
 365                  */
 366                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 367                 if (ret_val)
 368                         goto out;
 369                 ret_val = e1000e_get_phy_id(hw);
 370                 if (ret_val)
 371                         goto out;
 372                 break;
 373         }
 374         phy->type = e1000e_get_phy_type_from_id(phy->id);
 375
 376         switch (phy->type) {
 377         case e1000_phy_82577:
 378         case e1000_phy_82579:
 379                 phy->ops.check_polarity = e1000_check_polarity_82577;
 380                 phy->ops.force_speed_duplex =
 381                     e1000_phy_force_speed_duplex_82577;
 382                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 383                 phy->ops.get_info = e1000_get_phy_info_82577;
 384                 phy->ops.commit = e1000e_phy_sw_reset;
 385                 break;
 386         case e1000_phy_82578:
 387                 phy->ops.check_polarity = e1000_check_polarity_m88;
 388                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 389                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 390                 phy->ops.get_info = e1000e_get_phy_info_m88;
 391                 break;
 392         default:
 393                 ret_val = -E1000_ERR_PHY;
 394                 break;
 395         }
 396
 397 out:
 398         return ret_val;
 399 }
 400
 401 /**
 402  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 403  *  @hw: pointer to the HW structure
 404  *
 405  *  Initialize family-specific PHY parameters and function pointers.
 406  **/
 407 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 408 {
 409         struct e1000_phy_info *phy = &hw->phy;
 410         s32 ret_val;
 411         u16 i = 0;
 412
 413         phy->addr                       = 1;
 414         phy->reset_delay_us             = 100;
 415
 416         phy->ops.power_up               = e1000_power_up_phy_copper;
 417         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 418
 419         /*
 420          * We may need to do this twice - once for IGP and if that fails,
 421          * we'll set BM func pointers and try again
 422          */
 423         ret_val = e1000e_determine_phy_address(hw);
 424         if (ret_val) {
 425                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 426                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 427                 ret_val = e1000e_determine_phy_address(hw);
 428                 if (ret_val) {
 429                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 430                         return ret_val;
 431                 }
 432         }
 433
 434         phy->id = 0;
 435         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 436                (i++ < 100)) {
 437                 usleep_range(1000, 2000);
 438                 ret_val = e1000e_get_phy_id(hw);
 439                 if (ret_val)
 440                         return ret_val;
 441         }
 442
 443         /* Verify phy id */
 444         switch (phy->id) {
 445         case IGP03E1000_E_PHY_ID:
 446                 phy->type = e1000_phy_igp_3;
 447                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 448                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 449                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 450                 phy->ops.get_info = e1000e_get_phy_info_igp;
 451                 phy->ops.check_polarity = e1000_check_polarity_igp;
 452                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 453                 break;
 454         case IFE_E_PHY_ID:
 455         case IFE_PLUS_E_PHY_ID:
 456         case IFE_C_E_PHY_ID:
 457                 phy->type = e1000_phy_ife;
 458                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 459                 phy->ops.get_info = e1000_get_phy_info_ife;
 460                 phy->ops.check_polarity = e1000_check_polarity_ife;
 461                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 462                 break;
 463         case BME1000_E_PHY_ID:
 464                 phy->type = e1000_phy_bm;
 465                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 466                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 467                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 468                 phy->ops.commit = e1000e_phy_sw_reset;
 469                 phy->ops.get_info = e1000e_get_phy_info_m88;
 470                 phy->ops.check_polarity = e1000_check_polarity_m88;
 471                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 472                 break;
 473         default:
 474                 return -E1000_ERR_PHY;
 475                 break;
 476         }
 477
 478         return 0;
 479 }
 480
 481 /**
 482  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 483  *  @hw: pointer to the HW structure
 484  *
 485  *  Initialize family-specific NVM parameters and function
 486  *  pointers.
 487  **/
 488 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 489 {
 490         struct e1000_nvm_info *nvm = &hw->nvm;
 491         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 492         u32 gfpreg, sector_base_addr, sector_end_addr;
 493         u16 i;
 494
 495         /* Can't read flash registers if the register set isn't mapped. */
 496         if (!hw->flash_address) {
 497                 e_dbg("ERROR: Flash registers not mapped\n");
 498                 return -E1000_ERR_CONFIG;
 499         }
 500
 501         nvm->type = e1000_nvm_flash_sw;
 502
 503         gfpreg = er32flash(ICH_FLASH_GFPREG);
 504
 505         /*
 506          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 507          * Add 1 to sector_end_addr since this sector is included in
 508          * the overall size.
 509          */
 510         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 511         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 512
 513         /* flash_base_addr is byte-aligned */
 514         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 515
 516         /*
 517          * find total size of the NVM, then cut in half since the total
 518          * size represents two separate NVM banks.
 519          */
 520         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 521                                 << FLASH_SECTOR_ADDR_SHIFT;
 522         nvm->flash_bank_size /= 2;
 523         /* Adjust to word count */
 524         nvm->flash_bank_size /= sizeof(u16);
 525
 526         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 527
 528         /* Clear shadow ram */
 529         for (i = 0; i < nvm->word_size; i++) {
 530                 dev_spec->shadow_ram[i].modified = false;
 531                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 532         }
 533
 534         return 0;
 535 }
 536
 537 /**
 538  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 539  *  @hw: pointer to the HW structure
 540  *
 541  *  Initialize family-specific MAC parameters and function
 542  *  pointers.
 543  **/
 544 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 545 {
 546         struct e1000_hw *hw = &adapter->hw;
 547         struct e1000_mac_info *mac = &hw->mac;
 548
 549         /* Set media type function pointer */
 550         hw->phy.media_type = e1000_media_type_copper;
 551
 552         /* Set mta register count */
 553         mac->mta_reg_count = 32;
 554         /* Set rar entry count */
 555         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 556         if (mac->type == e1000_ich8lan)
 557                 mac->rar_entry_count--;
 558         /* FWSM register */
 559         mac->has_fwsm = true;
 560         /* ARC subsystem not supported */
 561         mac->arc_subsystem_valid = false;
 562         /* Adaptive IFS supported */
 563         mac->adaptive_ifs = true;
 564
 565         /* LED operations */
 566         switch (mac->type) {
 567         case e1000_ich8lan:
 568         case e1000_ich9lan:
 569         case e1000_ich10lan:
 570                 /* check management mode */
 571                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 572                 /* ID LED init */
 573                 mac->ops.id_led_init = e1000e_id_led_init;
 574                 /* blink LED */
 575                 mac->ops.blink_led = e1000e_blink_led_generic;
 576                 /* setup LED */
 577                 mac->ops.setup_led = e1000e_setup_led_generic;
 578                 /* cleanup LED */
 579                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 580                 /* turn on/off LED */
 581                 mac->ops.led_on = e1000_led_on_ich8lan;
 582                 mac->ops.led_off = e1000_led_off_ich8lan;
 583                 break;
 584         case e1000_pchlan:
 585         case e1000_pch2lan:
 586                 /* check management mode */
 587                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 588                 /* ID LED init */
 589                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 590                 /* setup LED */
 591                 mac->ops.setup_led = e1000_setup_led_pchlan;
 592                 /* cleanup LED */
 593                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 594                 /* turn on/off LED */
 595                 mac->ops.led_on = e1000_led_on_pchlan;
 596                 mac->ops.led_off = e1000_led_off_pchlan;
 597                 break;
 598         default:
 599                 break;
 600         }
 601
 602         /* Enable PCS Lock-loss workaround for ICH8 */
 603         if (mac->type == e1000_ich8lan)
 604                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 605
 606         /* Gate automatic PHY configuration by hardware on managed 82579 */
 607         if ((mac->type == e1000_pch2lan) &&
 608             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 609                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 610
 611         return 0;
 612 }
 613
 614 /**
 615  *  e1000_set_eee_pchlan - Enable/disable EEE support
 616  *  @hw: pointer to the HW structure
 617  *
 618  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 619  *  the LPI Control register will remain set only if/when link is up.
 620  **/
 621 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 622 {
 623         s32 ret_val = 0;
 624         u16 phy_reg;
 625
 626         if (hw->phy.type != e1000_phy_82579)
 627                 goto out;
 628
 629         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 630         if (ret_val)
 631                 goto out;
 632
 633         if (hw->dev_spec.ich8lan.eee_disable)
 634                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 635         else
 636                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 637
 638         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 639 out:
 640         return ret_val;
 641 }
 642
 643 /**
 644  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 645  *  @hw: pointer to the HW structure
 646  *
 647  *  Checks to see of the link status of the hardware has changed.  If a
 648  *  change in link status has been detected, then we read the PHY registers
 649  *  to get the current speed/duplex if link exists.
 650  **/
 651 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 652 {
 653         struct e1000_mac_info *mac = &hw->mac;
 654         s32 ret_val;
 655         bool link;
 656
 657         /*
 658          * We only want to go out to the PHY registers to see if Auto-Neg
 659          * has completed and/or if our link status has changed.  The
 660          * get_link_status flag is set upon receiving a Link Status
 661          * Change or Rx Sequence Error interrupt.
 662          */
 663         if (!mac->get_link_status) {
 664                 ret_val = 0;
 665                 goto out;
 666         }
 667
 668         /*
 669          * First we want to see if the MII Status Register reports
 670          * link.  If so, then we want to get the current speed/duplex
 671          * of the PHY.
 672          */
 673         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 674         if (ret_val)
 675                 goto out;
 676
 677         if (hw->mac.type == e1000_pchlan) {
 678                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 679                 if (ret_val)
 680                         goto out;
 681         }
 682
 683         if (!link)
 684                 goto out; /* No link detected */
 685
 686         mac->get_link_status = false;
 687
 688         if (hw->phy.type == e1000_phy_82578) {
 689                 ret_val = e1000_link_stall_workaround_hv(hw);
 690                 if (ret_val)
 691                         goto out;
 692         }
 693
 694         if (hw->mac.type == e1000_pch2lan) {
 695                 ret_val = e1000_k1_workaround_lv(hw);
 696                 if (ret_val)
 697                         goto out;
 698         }
 699
 700         /*
 701          * Check if there was DownShift, must be checked
 702          * immediately after link-up
 703          */
 704         e1000e_check_downshift(hw);
 705
 706         /* Enable/Disable EEE after link up */
 707         ret_val = e1000_set_eee_pchlan(hw);
 708         if (ret_val)
 709                 goto out;
 710
 711         /*
 712          * If we are forcing speed/duplex, then we simply return since
 713          * we have already determined whether we have link or not.
 714          */
 715         if (!mac->autoneg) {
 716                 ret_val = -E1000_ERR_CONFIG;
 717                 goto out;
 718         }
 719
 720         /*
 721          * Auto-Neg is enabled.  Auto Speed Detection takes care
 722          * of MAC speed/duplex configuration.  So we only need to
 723          * configure Collision Distance in the MAC.
 724          */
 725         e1000e_config_collision_dist(hw);
 726
 727         /*
 728          * Configure Flow Control now that Auto-Neg has completed.
 729          * First, we need to restore the desired flow control
 730          * settings because we may have had to re-autoneg with a
 731          * different link partner.
 732          */
 733         ret_val = e1000e_config_fc_after_link_up(hw);
 734         if (ret_val)
 735                 e_dbg("Error configuring flow control\n");
 736
 737 out:
 738         return ret_val;
 739 }
 740
 741 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 742 {
 743         struct e1000_hw *hw = &adapter->hw;
 744         s32 rc;
 745
 746         rc = e1000_init_mac_params_ich8lan(adapter);
 747         if (rc)
 748                 return rc;
 749
 750         rc = e1000_init_nvm_params_ich8lan(hw);
 751         if (rc)
 752                 return rc;
 753
 754         switch (hw->mac.type) {
 755         case e1000_ich8lan:
 756         case e1000_ich9lan:
 757         case e1000_ich10lan:
 758                 rc = e1000_init_phy_params_ich8lan(hw);
 759                 break;
 760         case e1000_pchlan:
 761         case e1000_pch2lan:
 762                 rc = e1000_init_phy_params_pchlan(hw);
 763                 break;
 764         default:
 765                 break;
 766         }
 767         if (rc)
 768                 return rc;
 769
 770         /*
 771          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 772          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 773          */
 774         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 775             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 776              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 777                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 778                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 779
 780                 hw->mac.ops.blink_led = NULL;
 781         }
 782
 783         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 784             (adapter->hw.phy.type == e1000_phy_igp_3))
 785                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 786
 787         /* Disable EEE by default until IEEE802.3az spec is finalized */
 788         if (adapter->flags2 & FLAG2_HAS_EEE)
 789                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 790
 791         return 0;
 792 }
 793
 794 static DEFINE_MUTEX(nvm_mutex);
 795
 796 /**
 797  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 798  *  @hw: pointer to the HW structure
 799  *
 800  *  Acquires the mutex for performing NVM operations.
 801  **/
 802 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 803 {
 804         mutex_lock(&nvm_mutex);
 805
 806         return 0;
 807 }
 808
 809 /**
 810  *  e1000_release_nvm_ich8lan - Release NVM mutex
 811  *  @hw: pointer to the HW structure
 812  *
 813  *  Releases the mutex used while performing NVM operations.
 814  **/
 815 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 816 {
 817         mutex_unlock(&nvm_mutex);
 818 }
 819
 820 static DEFINE_MUTEX(swflag_mutex);
 821
 822 /**
 823  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 824  *  @hw: pointer to the HW structure
 825  *
 826  *  Acquires the software control flag for performing PHY and select
 827  *  MAC CSR accesses.
 828  **/
 829 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 830 {
 831         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 832         s32 ret_val = 0;
 833
 834         mutex_lock(&swflag_mutex);
 835
 836         while (timeout) {
 837                 extcnf_ctrl = er32(EXTCNF_CTRL);
 838                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 839                         break;
 840
 841                 mdelay(1);
 842                 timeout--;
 843         }
 844
 845         if (!timeout) {
 846                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 847                 ret_val = -E1000_ERR_CONFIG;
 848                 goto out;
 849         }
 850
 851         timeout = SW_FLAG_TIMEOUT;
 852
 853         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 854         ew32(EXTCNF_CTRL, extcnf_ctrl);
 855
 856         while (timeout) {
 857                 extcnf_ctrl = er32(EXTCNF_CTRL);
 858                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 859                         break;
 860
 861                 mdelay(1);
 862                 timeout--;
 863         }
 864
 865         if (!timeout) {
 866                 e_dbg("Failed to acquire the semaphore.\n");
 867                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 868                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 869                 ret_val = -E1000_ERR_CONFIG;
 870                 goto out;
 871         }
 872
 873 out:
 874         if (ret_val)
 875                 mutex_unlock(&swflag_mutex);
 876
 877         return ret_val;
 878 }
 879
 880 /**
 881  *  e1000_release_swflag_ich8lan - Release software control flag
 882  *  @hw: pointer to the HW structure
 883  *
 884  *  Releases the software control flag for performing PHY and select
 885  *  MAC CSR accesses.
 886  **/
 887 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 888 {
 889         u32 extcnf_ctrl;
 890
 891         extcnf_ctrl = er32(EXTCNF_CTRL);
 892
 893         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 894                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 895                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 896         } else {
 897                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 898         }
 899
 900         mutex_unlock(&swflag_mutex);
 901 }
 902
 903 /**
 904  *  e1000_check_mng_mode_ich8lan - Checks management mode
 905  *  @hw: pointer to the HW structure
 906  *
 907  *  This checks if the adapter has any manageability enabled.
 908  *  This is a function pointer entry point only called by read/write
 909  *  routines for the PHY and NVM parts.
 910  **/
 911 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 912 {
 913         u32 fwsm;
 914
 915         fwsm = er32(FWSM);
 916         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 917                ((fwsm & E1000_FWSM_MODE_MASK) ==
 918                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 919 }
 920
 921 /**
 922  *  e1000_check_mng_mode_pchlan - Checks management mode
 923  *  @hw: pointer to the HW structure
 924  *
 925  *  This checks if the adapter has iAMT enabled.
 926  *  This is a function pointer entry point only called by read/write
 927  *  routines for the PHY and NVM parts.
 928  **/
 929 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 930 {
 931         u32 fwsm;
 932
 933         fwsm = er32(FWSM);
 934         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 935                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 936 }
 937
 938 /**
 939  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 940  *  @hw: pointer to the HW structure
 941  *
 942  *  Checks if firmware is blocking the reset of the PHY.
 943  *  This is a function pointer entry point only called by
 944  *  reset routines.
 945  **/
 946 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 947 {
 948         u32 fwsm;
 949
 950         fwsm = er32(FWSM);
 951
 952         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 953 }
 954
 955 /**
 956  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 957  *  @hw: pointer to the HW structure
 958  *
 959  *  Assumes semaphore already acquired.
 960  *
 961  **/
 962 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 963 {
 964         u16 phy_data;
 965         u32 strap = er32(STRAP);
 966         s32 ret_val = 0;
 967
 968         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 969
 970         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 971         if (ret_val)
 972                 goto out;
 973
 974         phy_data &= ~HV_SMB_ADDR_MASK;
 975         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 976         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 977         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 978
 979 out:
 980         return ret_val;
 981 }
 982
 983 /**
 984  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 985  *  @hw:   pointer to the HW structure
 986  *
 987  *  SW should configure the LCD from the NVM extended configuration region
 988  *  as a workaround for certain parts.
 989  **/
 990 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 991 {
 992         struct e1000_phy_info *phy = &hw->phy;
 993         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 994         s32 ret_val = 0;
 995         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 996
 997         /*
 998          * Initialize the PHY from the NVM on ICH platforms.  This
 999          * is needed due to an issue where the NVM configuration is
1000          * not properly autoloaded after power transitions.
1001          * Therefore, after each PHY reset, we will load the
1002          * configuration data out of the NVM manually.
1003          */
1004         switch (hw->mac.type) {
1005         case e1000_ich8lan:
1006                 if (phy->type != e1000_phy_igp_3)
1007                         return ret_val;
1008
1009                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1010                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1011                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1012                         break;
1013                 }
1014                 /* Fall-thru */
1015         case e1000_pchlan:
1016         case e1000_pch2lan:
1017                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1018                 break;
1019         default:
1020                 return ret_val;
1021         }
1022
1023         ret_val = hw->phy.ops.acquire(hw);
1024         if (ret_val)
1025                 return ret_val;
1026
1027         data = er32(FEXTNVM);
1028         if (!(data & sw_cfg_mask))
1029                 goto out;
1030
1031         /*
1032          * Make sure HW does not configure LCD from PHY
1033          * extended configuration before SW configuration
1034          */
1035         data = er32(EXTCNF_CTRL);
1036         if (!(hw->mac.type == e1000_pch2lan)) {
1037                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1038                         goto out;
1039         }
1040
1041         cnf_size = er32(EXTCNF_SIZE);
1042         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1043         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1044         if (!cnf_size)
1045                 goto out;
1046
1047         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1048         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1049
1050         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1051             (hw->mac.type == e1000_pchlan)) ||
1052              (hw->mac.type == e1000_pch2lan)) {
1053                 /*
1054                  * HW configures the SMBus address and LEDs when the
1055                  * OEM and LCD Write Enable bits are set in the NVM.
1056                  * When both NVM bits are cleared, SW will configure
1057                  * them instead.
1058                  */
1059                 ret_val = e1000_write_smbus_addr(hw);
1060                 if (ret_val)
1061                         goto out;
1062
1063                 data = er32(LEDCTL);
1064                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1065                                                         (u16)data);
1066                 if (ret_val)
1067                         goto out;
1068         }
1069
1070         /* Configure LCD from extended configuration region. */
1071
1072         /* cnf_base_addr is in DWORD */
1073         word_addr = (u16)(cnf_base_addr << 1);
1074
1075         for (i = 0; i < cnf_size; i++) {
1076                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1077                                          &reg_data);
1078                 if (ret_val)
1079                         goto out;
1080
1081                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1082                                          1, &reg_addr);
1083                 if (ret_val)
1084                         goto out;
1085
1086                 /* Save off the PHY page for future writes. */
1087                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1088                         phy_page = reg_data;
1089                         continue;
1090                 }
1091
1092                 reg_addr &= PHY_REG_MASK;
1093                 reg_addr |= phy_page;
1094
1095                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1096                                                     reg_data);
1097                 if (ret_val)
1098                         goto out;
1099         }
1100
1101 out:
1102         hw->phy.ops.release(hw);
1103         return ret_val;
1104 }
1105
1106 /**
1107  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1108  *  @hw:   pointer to the HW structure
1109  *  @link: link up bool flag
1110  *
1111  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1112  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1113  *  If link is down, the function will restore the default K1 setting located
1114  *  in the NVM.
1115  **/
1116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1117 {
1118         s32 ret_val = 0;
1119         u16 status_reg = 0;
1120         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1121
1122         if (hw->mac.type != e1000_pchlan)
1123                 goto out;
1124
1125         /* Wrap the whole flow with the sw flag */
1126         ret_val = hw->phy.ops.acquire(hw);
1127         if (ret_val)
1128                 goto out;
1129
1130         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1131         if (link) {
1132                 if (hw->phy.type == e1000_phy_82578) {
1133                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1134                                                                   &status_reg);
1135                         if (ret_val)
1136                                 goto release;
1137
1138                         status_reg &= BM_CS_STATUS_LINK_UP |
1139                                       BM_CS_STATUS_RESOLVED |
1140                                       BM_CS_STATUS_SPEED_MASK;
1141
1142                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1143                                            BM_CS_STATUS_RESOLVED |
1144                                            BM_CS_STATUS_SPEED_1000))
1145                                 k1_enable = false;
1146                 }
1147
1148                 if (hw->phy.type == e1000_phy_82577) {
1149                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1150                                                                   &status_reg);
1151                         if (ret_val)
1152                                 goto release;
1153
1154                         status_reg &= HV_M_STATUS_LINK_UP |
1155                                       HV_M_STATUS_AUTONEG_COMPLETE |
1156                                       HV_M_STATUS_SPEED_MASK;
1157
1158                         if (status_reg == (HV_M_STATUS_LINK_UP |
1159                                            HV_M_STATUS_AUTONEG_COMPLETE |
1160                                            HV_M_STATUS_SPEED_1000))
1161                                 k1_enable = false;
1162                 }
1163
1164                 /* Link stall fix for link up */
1165                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1166                                                            0x0100);
1167                 if (ret_val)
1168                         goto release;
1169
1170         } else {
1171                 /* Link stall fix for link down */
1172                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1173                                                            0x4100);
1174                 if (ret_val)
1175                         goto release;
1176         }
1177
1178         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1179
1180 release:
1181         hw->phy.ops.release(hw);
1182 out:
1183         return ret_val;
1184 }
1185
1186 /**
1187  *  e1000_configure_k1_ich8lan - Configure K1 power state
1188  *  @hw: pointer to the HW structure
1189  *  @enable: K1 state to configure
1190  *
1191  *  Configure the K1 power state based on the provided parameter.
1192  *  Assumes semaphore already acquired.
1193  *
1194  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1195  **/
1196 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1197 {
1198         s32 ret_val = 0;
1199         u32 ctrl_reg = 0;
1200         u32 ctrl_ext = 0;
1201         u32 reg = 0;
1202         u16 kmrn_reg = 0;
1203
1204         ret_val = e1000e_read_kmrn_reg_locked(hw,
1205                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1206                                              &kmrn_reg);
1207         if (ret_val)
1208                 goto out;
1209
1210         if (k1_enable)
1211                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1212         else
1213                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1214
1215         ret_val = e1000e_write_kmrn_reg_locked(hw,
1216                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1217                                               kmrn_reg);
1218         if (ret_val)
1219                 goto out;
1220
1221         udelay(20);
1222         ctrl_ext = er32(CTRL_EXT);
1223         ctrl_reg = er32(CTRL);
1224
1225         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1226         reg |= E1000_CTRL_FRCSPD;
1227         ew32(CTRL, reg);
1228
1229         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1230         udelay(20);
1231         ew32(CTRL, ctrl_reg);
1232         ew32(CTRL_EXT, ctrl_ext);
1233         udelay(20);
1234
1235 out:
1236         return ret_val;
1237 }
1238
1239 /**
1240  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1241  *  @hw:       pointer to the HW structure
1242  *  @d0_state: boolean if entering d0 or d3 device state
1243  *
1244  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1245  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1246  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1247  **/
1248 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1249 {
1250         s32 ret_val = 0;
1251         u32 mac_reg;
1252         u16 oem_reg;
1253
1254         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1255                 return ret_val;
1256
1257         ret_val = hw->phy.ops.acquire(hw);
1258         if (ret_val)
1259                 return ret_val;
1260
1261         if (!(hw->mac.type == e1000_pch2lan)) {
1262                 mac_reg = er32(EXTCNF_CTRL);
1263                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1264                         goto out;
1265         }
1266
1267         mac_reg = er32(FEXTNVM);
1268         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1269                 goto out;
1270
1271         mac_reg = er32(PHY_CTRL);
1272
1273         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1274         if (ret_val)
1275                 goto out;
1276
1277         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1278
1279         if (d0_state) {
1280                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1281                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1282
1283                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1284                         oem_reg |= HV_OEM_BITS_LPLU;
1285         } else {
1286                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1287                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1288
1289                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1290                         oem_reg |= HV_OEM_BITS_LPLU;
1291         }
1292         /* Restart auto-neg to activate the bits */
1293         if (!e1000_check_reset_block(hw))
1294                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1295         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1296
1297 out:
1298         hw->phy.ops.release(hw);
1299
1300         return ret_val;
1301 }
1302
1303
1304 /**
1305  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1306  *  @hw:   pointer to the HW structure
1307  **/
1308 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1309 {
1310         s32 ret_val;
1311         u16 data;
1312
1313         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1314         if (ret_val)
1315                 return ret_val;
1316
1317         data |= HV_KMRN_MDIO_SLOW;
1318
1319         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1320
1321         return ret_val;
1322 }
1323
1324 /**
1325  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1326  *  done after every PHY reset.
1327  **/
1328 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1329 {
1330         s32 ret_val = 0;
1331         u16 phy_data;
1332
1333         if (hw->mac.type != e1000_pchlan)
1334                 return ret_val;
1335
1336         /* Set MDIO slow mode before any other MDIO access */
1337         if (hw->phy.type == e1000_phy_82577) {
1338                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1339                 if (ret_val)
1340                         goto out;
1341         }
1342
1343         if (((hw->phy.type == e1000_phy_82577) &&
1344              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1345             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1346                 /* Disable generation of early preamble */
1347                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1348                 if (ret_val)
1349                         return ret_val;
1350
1351                 /* Preamble tuning for SSC */
1352                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1353                 if (ret_val)
1354                         return ret_val;
1355         }
1356
1357         if (hw->phy.type == e1000_phy_82578) {
1358                 /*
1359                  * Return registers to default by doing a soft reset then
1360                  * writing 0x3140 to the control register.
1361                  */
1362                 if (hw->phy.revision < 2) {
1363                         e1000e_phy_sw_reset(hw);
1364                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1365                 }
1366         }
1367
1368         /* Select page 0 */
1369         ret_val = hw->phy.ops.acquire(hw);
1370         if (ret_val)
1371                 return ret_val;
1372
1373         hw->phy.addr = 1;
1374         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1375         hw->phy.ops.release(hw);
1376         if (ret_val)
1377                 goto out;
1378
1379         /*
1380          * Configure the K1 Si workaround during phy reset assuming there is
1381          * link so that it disables K1 if link is in 1Gbps.
1382          */
1383         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1384         if (ret_val)
1385                 goto out;
1386
1387         /* Workaround for link disconnects on a busy hub in half duplex */
1388         ret_val = hw->phy.ops.acquire(hw);
1389         if (ret_val)
1390                 goto out;
1391         ret_val = hw->phy.ops.read_reg_locked(hw,
1392                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1393                                               &phy_data);
1394         if (ret_val)
1395                 goto release;
1396         ret_val = hw->phy.ops.write_reg_locked(hw,
1397                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1398                                                phy_data & 0x00FF);
1399 release:
1400         hw->phy.ops.release(hw);
1401 out:
1402         return ret_val;
1403 }
1404
1405 /**
1406  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1407  *  @hw:   pointer to the HW structure
1408  **/
1409 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1410 {
1411         u32 mac_reg;
1412         u16 i;
1413
1414         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1415         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1416                 mac_reg = er32(RAL(i));
1417                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1418                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1419                 mac_reg = er32(RAH(i));
1420                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1421                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1422         }
1423 }
1424
1425 /**
1426  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1427  *  with 82579 PHY
1428  *  @hw: pointer to the HW structure
1429  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1430  **/
1431 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1432 {
1433         s32 ret_val = 0;
1434         u16 phy_reg, data;
1435         u32 mac_reg;
1436         u16 i;
1437
1438         if (hw->mac.type != e1000_pch2lan)
1439                 goto out;
1440
1441         /* disable Rx path while enabling/disabling workaround */
1442         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1443         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1444         if (ret_val)
1445                 goto out;
1446
1447         if (enable) {
1448                 /*
1449                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1450                  * SHRAL/H) and initial CRC values to the MAC
1451                  */
1452                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1453                         u8 mac_addr[ETH_ALEN] = {0};
1454                         u32 addr_high, addr_low;
1455
1456                         addr_high = er32(RAH(i));
1457                         if (!(addr_high & E1000_RAH_AV))
1458                                 continue;
1459                         addr_low = er32(RAL(i));
1460                         mac_addr[0] = (addr_low & 0xFF);
1461                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1462                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1463                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1464                         mac_addr[4] = (addr_high & 0xFF);
1465                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1466
1467                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1468                 }
1469
1470                 /* Write Rx addresses to the PHY */
1471                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1472
1473                 /* Enable jumbo frame workaround in the MAC */
1474                 mac_reg = er32(FFLT_DBG);
1475                 mac_reg &= ~(1 << 14);
1476                 mac_reg |= (7 << 15);
1477                 ew32(FFLT_DBG, mac_reg);
1478
1479                 mac_reg = er32(RCTL);
1480                 mac_reg |= E1000_RCTL_SECRC;
1481                 ew32(RCTL, mac_reg);
1482
1483                 ret_val = e1000e_read_kmrn_reg(hw,
1484                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1485                                                 &data);
1486                 if (ret_val)
1487                         goto out;
1488                 ret_val = e1000e_write_kmrn_reg(hw,
1489                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1490                                                 data | (1 << 0));
1491                 if (ret_val)
1492                         goto out;
1493                 ret_val = e1000e_read_kmrn_reg(hw,
1494                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1495                                                 &data);
1496                 if (ret_val)
1497                         goto out;
1498                 data &= ~(0xF << 8);
1499                 data |= (0xB << 8);
1500                 ret_val = e1000e_write_kmrn_reg(hw,
1501                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1502                                                 data);
1503                 if (ret_val)
1504                         goto out;
1505
1506                 /* Enable jumbo frame workaround in the PHY */
1507                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1508                 data &= ~(0x7F << 5);
1509                 data |= (0x37 << 5);
1510                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1511                 if (ret_val)
1512                         goto out;
1513                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1514                 data &= ~(1 << 13);
1515                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1516                 if (ret_val)
1517                         goto out;
1518                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1519                 data &= ~(0x3FF << 2);
1520                 data |= (0x1A << 2);
1521                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1522                 if (ret_val)
1523                         goto out;
1524                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1525                 if (ret_val)
1526                         goto out;
1527                 e1e_rphy(hw, HV_PM_CTRL, &data);
1528                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1529                 if (ret_val)
1530                         goto out;
1531         } else {
1532                 /* Write MAC register values back to h/w defaults */
1533                 mac_reg = er32(FFLT_DBG);
1534                 mac_reg &= ~(0xF << 14);
1535                 ew32(FFLT_DBG, mac_reg);
1536
1537                 mac_reg = er32(RCTL);
1538                 mac_reg &= ~E1000_RCTL_SECRC;
1539                 ew32(RCTL, mac_reg);
1540
1541                 ret_val = e1000e_read_kmrn_reg(hw,
1542                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1543                                                 &data);
1544                 if (ret_val)
1545                         goto out;
1546                 ret_val = e1000e_write_kmrn_reg(hw,
1547                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1548                                                 data & ~(1 << 0));
1549                 if (ret_val)
1550                         goto out;
1551                 ret_val = e1000e_read_kmrn_reg(hw,
1552                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1553                                                 &data);
1554                 if (ret_val)
1555                         goto out;
1556                 data &= ~(0xF << 8);
1557                 data |= (0xB << 8);
1558                 ret_val = e1000e_write_kmrn_reg(hw,
1559                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1560                                                 data);
1561                 if (ret_val)
1562                         goto out;
1563
1564                 /* Write PHY register values back to h/w defaults */
1565                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1566                 data &= ~(0x7F << 5);
1567                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1568                 if (ret_val)
1569                         goto out;
1570                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1571                 data |= (1 << 13);
1572                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1573                 if (ret_val)
1574                         goto out;
1575                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1576                 data &= ~(0x3FF << 2);
1577                 data |= (0x8 << 2);
1578                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1579                 if (ret_val)
1580                         goto out;
1581                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1582                 if (ret_val)
1583                         goto out;
1584                 e1e_rphy(hw, HV_PM_CTRL, &data);
1585                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1586                 if (ret_val)
1587                         goto out;
1588         }
1589
1590         /* re-enable Rx path after enabling/disabling workaround */
1591         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1592
1593 out:
1594         return ret_val;
1595 }
1596
1597 /**
1598  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1599  *  done after every PHY reset.
1600  **/
1601 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1602 {
1603         s32 ret_val = 0;
1604
1605         if (hw->mac.type != e1000_pch2lan)
1606                 goto out;
1607
1608         /* Set MDIO slow mode before any other MDIO access */
1609         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1610
1611 out:
1612         return ret_val;
1613 }
1614
1615 /**
1616  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1617  *  @hw:   pointer to the HW structure
1618  *
1619  *  Workaround to set the K1 beacon duration for 82579 parts
1620  **/
1621 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1622 {
1623         s32 ret_val = 0;
1624         u16 status_reg = 0;
1625         u32 mac_reg;
1626
1627         if (hw->mac.type != e1000_pch2lan)
1628                 goto out;
1629
1630         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1631         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1632         if (ret_val)
1633                 goto out;
1634
1635         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1636             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1637                 mac_reg = er32(FEXTNVM4);
1638                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1639
1640                 if (status_reg & HV_M_STATUS_SPEED_1000)
1641                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1642                 else
1643                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1644
1645                 ew32(FEXTNVM4, mac_reg);
1646         }
1647
1648 out:
1649         return ret_val;
1650 }
1651
1652 /**
1653  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1654  *  @hw:   pointer to the HW structure
1655  *  @gate: boolean set to true to gate, false to ungate
1656  *
1657  *  Gate/ungate the automatic PHY configuration via hardware; perform
1658  *  the configuration via software instead.
1659  **/
1660 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1661 {
1662         u32 extcnf_ctrl;
1663
1664         if (hw->mac.type != e1000_pch2lan)
1665                 return;
1666
1667         extcnf_ctrl = er32(EXTCNF_CTRL);
1668
1669         if (gate)
1670                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1671         else
1672                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1673
1674         ew32(EXTCNF_CTRL, extcnf_ctrl);
1675         return;
1676 }
1677
1678 /**
1679  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1680  *  @hw: pointer to the HW structure
1681  *
1682  *  Check the appropriate indication the MAC has finished configuring the
1683  *  PHY after a software reset.
1684  **/
1685 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1686 {
1687         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1688
1689         /* Wait for basic configuration completes before proceeding */
1690         do {
1691                 data = er32(STATUS);
1692                 data &= E1000_STATUS_LAN_INIT_DONE;
1693                 udelay(100);
1694         } while ((!data) && --loop);
1695
1696         /*
1697          * If basic configuration is incomplete before the above loop
1698          * count reaches 0, loading the configuration from NVM will
1699          * leave the PHY in a bad state possibly resulting in no link.
1700          */
1701         if (loop == 0)
1702                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1703
1704         /* Clear the Init Done bit for the next init event */
1705         data = er32(STATUS);
1706         data &= ~E1000_STATUS_LAN_INIT_DONE;
1707         ew32(STATUS, data);
1708 }
1709
1710 /**
1711  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1712  *  @hw: pointer to the HW structure
1713  **/
1714 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1715 {
1716         s32 ret_val = 0;
1717         u16 reg;
1718
1719         if (e1000_check_reset_block(hw))
1720                 goto out;
1721
1722         /* Allow time for h/w to get to quiescent state after reset */
1723         usleep_range(10000, 20000);
1724
1725         /* Perform any necessary post-reset workarounds */
1726         switch (hw->mac.type) {
1727         case e1000_pchlan:
1728                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1729                 if (ret_val)
1730                         goto out;
1731                 break;
1732         case e1000_pch2lan:
1733                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1734                 if (ret_val)
1735                         goto out;
1736                 break;
1737         default:
1738                 break;
1739         }
1740
1741         /* Dummy read to clear the phy wakeup bit after lcd reset */
1742         if (hw->mac.type >= e1000_pchlan)
1743                 e1e_rphy(hw, BM_WUC, &reg);
1744
1745         /* Configure the LCD with the extended configuration region in NVM */
1746         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1747         if (ret_val)
1748                 goto out;
1749
1750         /* Configure the LCD with the OEM bits in NVM */
1751         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1752
1753         if (hw->mac.type == e1000_pch2lan) {
1754                 /* Ungate automatic PHY configuration on non-managed 82579 */
1755                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1756                         usleep_range(10000, 20000);
1757                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1758                 }
1759
1760                 /* Set EEE LPI Update Timer to 200usec */
1761                 ret_val = hw->phy.ops.acquire(hw);
1762                 if (ret_val)
1763                         goto out;
1764                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1765                                                        I82579_LPI_UPDATE_TIMER);
1766                 if (ret_val)
1767                         goto release;
1768                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1769                                                        0x1387);
1770 release:
1771                 hw->phy.ops.release(hw);
1772         }
1773
1774 out:
1775         return ret_val;
1776 }
1777
1778 /**
1779  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1780  *  @hw: pointer to the HW structure
1781  *
1782  *  Resets the PHY
1783  *  This is a function pointer entry point called by drivers
1784  *  or other shared routines.
1785  **/
1786 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1787 {
1788         s32 ret_val = 0;
1789
1790         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1791         if ((hw->mac.type == e1000_pch2lan) &&
1792             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1793                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1794
1795         ret_val = e1000e_phy_hw_reset_generic(hw);
1796         if (ret_val)
1797                 goto out;
1798
1799         ret_val = e1000_post_phy_reset_ich8lan(hw);
1800
1801 out:
1802         return ret_val;
1803 }
1804
1805 /**
1806  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1807  *  @hw: pointer to the HW structure
1808  *  @active: true to enable LPLU, false to disable
1809  *
1810  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1811  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1812  *  the phy speed. This function will manually set the LPLU bit and restart
1813  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1814  *  since it configures the same bit.
1815  **/
1816 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1817 {
1818         s32 ret_val = 0;
1819         u16 oem_reg;
1820
1821         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1822         if (ret_val)
1823                 goto out;
1824
1825         if (active)
1826                 oem_reg |= HV_OEM_BITS_LPLU;
1827         else
1828                 oem_reg &= ~HV_OEM_BITS_LPLU;
1829
1830         oem_reg |= HV_OEM_BITS_RESTART_AN;
1831         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1832
1833 out:
1834         return ret_val;
1835 }
1836
1837 /**
1838  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1839  *  @hw: pointer to the HW structure
1840  *  @active: true to enable LPLU, false to disable
1841  *
1842  *  Sets the LPLU D0 state according to the active flag.  When
1843  *  activating LPLU this function also disables smart speed
1844  *  and vice versa.  LPLU will not be activated unless the
1845  *  device autonegotiation advertisement meets standards of
1846  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1847  *  This is a function pointer entry point only called by
1848  *  PHY setup routines.
1849  **/
1850 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1851 {
1852         struct e1000_phy_info *phy = &hw->phy;
1853         u32 phy_ctrl;
1854         s32 ret_val = 0;
1855         u16 data;
1856
1857         if (phy->type == e1000_phy_ife)
1858                 return ret_val;
1859
1860         phy_ctrl = er32(PHY_CTRL);
1861
1862         if (active) {
1863                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1864                 ew32(PHY_CTRL, phy_ctrl);
1865
1866                 if (phy->type != e1000_phy_igp_3)
1867                         return 0;
1868
1869                 /*
1870                  * Call gig speed drop workaround on LPLU before accessing
1871                  * any PHY registers
1872                  */
1873                 if (hw->mac.type == e1000_ich8lan)
1874                         e1000e_gig_downshift_workaround_ich8lan(hw);
1875
1876                 /* When LPLU is enabled, we should disable SmartSpeed */
1877                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1878                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1879                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1880                 if (ret_val)
1881                         return ret_val;
1882         } else {
1883                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1884                 ew32(PHY_CTRL, phy_ctrl);
1885
1886                 if (phy->type != e1000_phy_igp_3)
1887                         return 0;
1888
1889                 /*
1890                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1891                  * during Dx states where the power conservation is most
1892                  * important.  During driver activity we should enable
1893                  * SmartSpeed, so performance is maintained.
1894                  */
1895                 if (phy->smart_speed == e1000_smart_speed_on) {
1896                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1897                                            &data);
1898                         if (ret_val)
1899                                 return ret_val;
1900
1901                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1902                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1903                                            data);
1904                         if (ret_val)
1905                                 return ret_val;
1906                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1907                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1908                                            &data);
1909                         if (ret_val)
1910                                 return ret_val;
1911
1912                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1913                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1914                                            data);
1915                         if (ret_val)
1916                                 return ret_val;
1917                 }
1918         }
1919
1920         return 0;
1921 }
1922
1923 /**
1924  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1925  *  @hw: pointer to the HW structure
1926  *  @active: true to enable LPLU, false to disable
1927  *
1928  *  Sets the LPLU D3 state according to the active flag.  When
1929  *  activating LPLU this function also disables smart speed
1930  *  and vice versa.  LPLU will not be activated unless the
1931  *  device autonegotiation advertisement meets standards of
1932  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1933  *  This is a function pointer entry point only called by
1934  *  PHY setup routines.
1935  **/
1936 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1937 {
1938         struct e1000_phy_info *phy = &hw->phy;
1939         u32 phy_ctrl;
1940         s32 ret_val;
1941         u16 data;
1942
1943         phy_ctrl = er32(PHY_CTRL);
1944
1945         if (!active) {
1946                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1947                 ew32(PHY_CTRL, phy_ctrl);
1948
1949                 if (phy->type != e1000_phy_igp_3)
1950                         return 0;
1951
1952                 /*
1953                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1954                  * during Dx states where the power conservation is most
1955                  * important.  During driver activity we should enable
1956                  * SmartSpeed, so performance is maintained.
1957                  */
1958                 if (phy->smart_speed == e1000_smart_speed_on) {
1959                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1960                                            &data);
1961                         if (ret_val)
1962                                 return ret_val;
1963
1964                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1965                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1966                                            data);
1967                         if (ret_val)
1968                                 return ret_val;
1969                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1970                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1971                                            &data);
1972                         if (ret_val)
1973                                 return ret_val;
1974
1975                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1976                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1977                                            data);
1978                         if (ret_val)
1979                                 return ret_val;
1980                 }
1981         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1982                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1983                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1984                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1985                 ew32(PHY_CTRL, phy_ctrl);
1986
1987                 if (phy->type != e1000_phy_igp_3)
1988                         return 0;
1989
1990                 /*
1991                  * Call gig speed drop workaround on LPLU before accessing
1992                  * any PHY registers
1993                  */
1994                 if (hw->mac.type == e1000_ich8lan)
1995                         e1000e_gig_downshift_workaround_ich8lan(hw);
1996
1997                 /* When LPLU is enabled, we should disable SmartSpeed */
1998                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1999                 if (ret_val)
2000                         return ret_val;
2001
2002                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2003                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2004         }
2005
2006         return 0;
2007 }
2008
2009 /**
2010  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2011  *  @hw: pointer to the HW structure
2012  *  @bank:  pointer to the variable that returns the active bank
2013  *
2014  *  Reads signature byte from the NVM using the flash access registers.
2015  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2016  **/
2017 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2018 {
2019         u32 eecd;
2020         struct e1000_nvm_info *nvm = &hw->nvm;
2021         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2022         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2023         u8 sig_byte = 0;
2024         s32 ret_val = 0;
2025
2026         switch (hw->mac.type) {
2027         case e1000_ich8lan:
2028         case e1000_ich9lan:
2029                 eecd = er32(EECD);
2030                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2031                     E1000_EECD_SEC1VAL_VALID_MASK) {
2032                         if (eecd & E1000_EECD_SEC1VAL)
2033                                 *bank = 1;
2034                         else
2035                                 *bank = 0;
2036
2037                         return 0;
2038                 }
2039                 e_dbg("Unable to determine valid NVM bank via EEC - "
2040                        "reading flash signature\n");
2041                 /* fall-thru */
2042         default:
2043                 /* set bank to 0 in case flash read fails */
2044                 *bank = 0;
2045
2046                 /* Check bank 0 */
2047                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2048                                                         &sig_byte);
2049                 if (ret_val)
2050                         return ret_val;
2051                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2052                     E1000_ICH_NVM_SIG_VALUE) {
2053                         *bank = 0;
2054                         return 0;
2055                 }
2056
2057                 /* Check bank 1 */
2058                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2059                                                         bank1_offset,
2060                                                         &sig_byte);
2061                 if (ret_val)
2062                         return ret_val;
2063                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2064                     E1000_ICH_NVM_SIG_VALUE) {
2065                         *bank = 1;
2066                         return 0;
2067                 }
2068
2069                 e_dbg("ERROR: No valid NVM bank present\n");
2070                 return -E1000_ERR_NVM;
2071         }
2072
2073         return 0;
2074 }
2075
2076 /**
2077  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2078  *  @hw: pointer to the HW structure
2079  *  @offset: The offset (in bytes) of the word(s) to read.
2080  *  @words: Size of data to read in words
2081  *  @data: Pointer to the word(s) to read at offset.
2082  *
2083  *  Reads a word(s) from the NVM using the flash access registers.
2084  **/
2085 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2086                                   u16 *data)
2087 {
2088         struct e1000_nvm_info *nvm = &hw->nvm;
2089         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2090         u32 act_offset;
2091         s32 ret_val = 0;
2092         u32 bank = 0;
2093         u16 i, word;
2094
2095         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2096             (words == 0)) {
2097                 e_dbg("nvm parameter(s) out of bounds\n");
2098                 ret_val = -E1000_ERR_NVM;
2099                 goto out;
2100         }
2101
2102         nvm->ops.acquire(hw);
2103
2104         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2105         if (ret_val) {
2106                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2107                 bank = 0;
2108         }
2109
2110         act_offset = (bank) ? nvm->flash_bank_size : 0;
2111         act_offset += offset;
2112
2113         ret_val = 0;
2114         for (i = 0; i < words; i++) {
2115                 if ((dev_spec->shadow_ram) &&
2116                     (dev_spec->shadow_ram[offset+i].modified)) {
2117                         data[i] = dev_spec->shadow_ram[offset+i].value;
2118                 } else {
2119                         ret_val = e1000_read_flash_word_ich8lan(hw,
2120                                                                 act_offset + i,
2121                                                                 &word);
2122                         if (ret_val)
2123                                 break;
2124                         data[i] = word;
2125                 }
2126         }
2127
2128         nvm->ops.release(hw);
2129
2130 out:
2131         if (ret_val)
2132                 e_dbg("NVM read error: %d\n", ret_val);
2133
2134         return ret_val;
2135 }
2136
2137 /**
2138  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2139  *  @hw: pointer to the HW structure
2140  *
2141  *  This function does initial flash setup so that a new read/write/erase cycle
2142  *  can be started.
2143  **/
2144 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2145 {
2146         union ich8_hws_flash_status hsfsts;
2147         s32 ret_val = -E1000_ERR_NVM;
2148
2149         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2150
2151         /* Check if the flash descriptor is valid */
2152         if (hsfsts.hsf_status.fldesvalid == 0) {
2153                 e_dbg("Flash descriptor invalid.  "
2154                          "SW Sequencing must be used.\n");
2155                 return -E1000_ERR_NVM;
2156         }
2157
2158         /* Clear FCERR and DAEL in hw status by writing 1 */
2159         hsfsts.hsf_status.flcerr = 1;
2160         hsfsts.hsf_status.dael = 1;
2161
2162         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2163
2164         /*
2165          * Either we should have a hardware SPI cycle in progress
2166          * bit to check against, in order to start a new cycle or
2167          * FDONE bit should be changed in the hardware so that it
2168          * is 1 after hardware reset, which can then be used as an
2169          * indication whether a cycle is in progress or has been
2170          * completed.
2171          */
2172
2173         if (hsfsts.hsf_status.flcinprog == 0) {
2174                 /*
2175                  * There is no cycle running at present,
2176                  * so we can start a cycle.
2177                  * Begin by setting Flash Cycle Done.
2178                  */
2179                 hsfsts.hsf_status.flcdone = 1;
2180                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2181                 ret_val = 0;
2182         } else {
2183                 s32 i = 0;
2184
2185                 /*
2186                  * Otherwise poll for sometime so the current
2187                  * cycle has a chance to end before giving up.
2188                  */
2189                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2190                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2191                         if (hsfsts.hsf_status.flcinprog == 0) {
2192                                 ret_val = 0;
2193                                 break;
2194                         }
2195                         udelay(1);
2196                 }
2197                 if (ret_val == 0) {
2198                         /*
2199                          * Successful in waiting for previous cycle to timeout,
2200                          * now set the Flash Cycle Done.
2201                          */
2202                         hsfsts.hsf_status.flcdone = 1;
2203                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2204                 } else {
2205                         e_dbg("Flash controller busy, cannot get access\n");
2206                 }
2207         }
2208
2209         return ret_val;
2210 }
2211
2212 /**
2213  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2214  *  @hw: pointer to the HW structure
2215  *  @timeout: maximum time to wait for completion
2216  *
2217  *  This function starts a flash cycle and waits for its completion.
2218  **/
2219 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2220 {
2221         union ich8_hws_flash_ctrl hsflctl;
2222         union ich8_hws_flash_status hsfsts;
2223         s32 ret_val = -E1000_ERR_NVM;
2224         u32 i = 0;
2225
2226         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2227         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2228         hsflctl.hsf_ctrl.flcgo = 1;
2229         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2230
2231         /* wait till FDONE bit is set to 1 */
2232         do {
2233                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2234                 if (hsfsts.hsf_status.flcdone == 1)
2235                         break;
2236                 udelay(1);
2237         } while (i++ < timeout);
2238
2239         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2240                 return 0;
2241
2242         return ret_val;
2243 }
2244
2245 /**
2246  *  e1000_read_flash_word_ich8lan - Read word from flash
2247  *  @hw: pointer to the HW structure
2248  *  @offset: offset to data location
2249  *  @data: pointer to the location for storing the data
2250  *
2251  *  Reads the flash word at offset into data.  Offset is converted
2252  *  to bytes before read.
2253  **/
2254 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2255                                          u16 *data)
2256 {
2257         /* Must convert offset into bytes. */
2258         offset <<= 1;
2259
2260         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2261 }
2262
2263 /**
2264  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2265  *  @hw: pointer to the HW structure
2266  *  @offset: The offset of the byte to read.
2267  *  @data: Pointer to a byte to store the value read.
2268  *
2269  *  Reads a single byte from the NVM using the flash access registers.
2270  **/
2271 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2272                                          u8 *data)
2273 {
2274         s32 ret_val;
2275         u16 word = 0;
2276
2277         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2278         if (ret_val)
2279                 return ret_val;
2280
2281         *data = (u8)word;
2282
2283         return 0;
2284 }
2285
2286 /**
2287  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2288  *  @hw: pointer to the HW structure
2289  *  @offset: The offset (in bytes) of the byte or word to read.
2290  *  @size: Size of data to read, 1=byte 2=word
2291  *  @data: Pointer to the word to store the value read.
2292  *
2293  *  Reads a byte or word from the NVM using the flash access registers.
2294  **/
2295 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2296                                          u8 size, u16 *data)
2297 {
2298         union ich8_hws_flash_status hsfsts;
2299         union ich8_hws_flash_ctrl hsflctl;
2300         u32 flash_linear_addr;
2301         u32 flash_data = 0;
2302         s32 ret_val = -E1000_ERR_NVM;
2303         u8 count = 0;
2304
2305         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2306                 return -E1000_ERR_NVM;
2307
2308         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2309                             hw->nvm.flash_base_addr;
2310
2311         do {
2312                 udelay(1);
2313                 /* Steps */
2314                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2315                 if (ret_val != 0)
2316                         break;
2317
2318                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2319                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2320                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2321                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2322                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2323
2324                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2325
2326                 ret_val = e1000_flash_cycle_ich8lan(hw,
2327                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2328
2329                 /*
2330                  * Check if FCERR is set to 1, if set to 1, clear it
2331                  * and try the whole sequence a few more times, else
2332                  * read in (shift in) the Flash Data0, the order is
2333                  * least significant byte first msb to lsb
2334                  */
2335                 if (ret_val == 0) {
2336                         flash_data = er32flash(ICH_FLASH_FDATA0);
2337                         if (size == 1)
2338                                 *data = (u8)(flash_data & 0x000000FF);
2339                         else if (size == 2)
2340                                 *data = (u16)(flash_data & 0x0000FFFF);
2341                         break;
2342                 } else {
2343                         /*
2344                          * If we've gotten here, then things are probably
2345                          * completely hosed, but if the error condition is
2346                          * detected, it won't hurt to give it another try...
2347                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2348                          */
2349                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2350                         if (hsfsts.hsf_status.flcerr == 1) {
2351                                 /* Repeat for some time before giving up. */
2352                                 continue;
2353                         } else if (hsfsts.hsf_status.flcdone == 0) {
2354                                 e_dbg("Timeout error - flash cycle "
2355                                          "did not complete.\n");
2356                                 break;
2357                         }
2358                 }
2359         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2360
2361         return ret_val;
2362 }
2363
2364 /**
2365  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2366  *  @hw: pointer to the HW structure
2367  *  @offset: The offset (in bytes) of the word(s) to write.
2368  *  @words: Size of data to write in words
2369  *  @data: Pointer to the word(s) to write at offset.
2370  *
2371  *  Writes a byte or word to the NVM using the flash access registers.
2372  **/
2373 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2374                                    u16 *data)
2375 {
2376         struct e1000_nvm_info *nvm = &hw->nvm;
2377         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2378         u16 i;
2379
2380         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2381             (words == 0)) {
2382                 e_dbg("nvm parameter(s) out of bounds\n");
2383                 return -E1000_ERR_NVM;
2384         }
2385
2386         nvm->ops.acquire(hw);
2387
2388         for (i = 0; i < words; i++) {
2389                 dev_spec->shadow_ram[offset+i].modified = true;
2390                 dev_spec->shadow_ram[offset+i].value = data[i];
2391         }
2392
2393         nvm->ops.release(hw);
2394
2395         return 0;
2396 }
2397
2398 /**
2399  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2400  *  @hw: pointer to the HW structure
2401  *
2402  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2403  *  which writes the checksum to the shadow ram.  The changes in the shadow
2404  *  ram are then committed to the EEPROM by processing each bank at a time
2405  *  checking for the modified bit and writing only the pending changes.
2406  *  After a successful commit, the shadow ram is cleared and is ready for
2407  *  future writes.
2408  **/
2409 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2410 {
2411         struct e1000_nvm_info *nvm = &hw->nvm;
2412         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2413         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2414         s32 ret_val;
2415         u16 data;
2416
2417         ret_val = e1000e_update_nvm_checksum_generic(hw);
2418         if (ret_val)
2419                 goto out;
2420
2421         if (nvm->type != e1000_nvm_flash_sw)
2422                 goto out;
2423
2424         nvm->ops.acquire(hw);
2425
2426         /*
2427          * We're writing to the opposite bank so if we're on bank 1,
2428          * write to bank 0 etc.  We also need to erase the segment that
2429          * is going to be written
2430          */
2431         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2432         if (ret_val) {
2433                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2434                 bank = 0;
2435         }
2436
2437         if (bank == 0) {
2438                 new_bank_offset = nvm->flash_bank_size;
2439                 old_bank_offset = 0;
2440                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2441                 if (ret_val)
2442                         goto release;
2443         } else {
2444                 old_bank_offset = nvm->flash_bank_size;
2445                 new_bank_offset = 0;
2446                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2447                 if (ret_val)
2448                         goto release;
2449         }
2450
2451         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2452                 /*
2453                  * Determine whether to write the value stored
2454                  * in the other NVM bank or a modified value stored
2455                  * in the shadow RAM
2456                  */
2457                 if (dev_spec->shadow_ram[i].modified) {
2458                         data = dev_spec->shadow_ram[i].value;
2459                 } else {
2460                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2461                                                                 old_bank_offset,
2462                                                                 &data);
2463                         if (ret_val)
2464                                 break;
2465                 }
2466
2467                 /*
2468                  * If the word is 0x13, then make sure the signature bits
2469                  * (15:14) are 11b until the commit has completed.
2470                  * This will allow us to write 10b which indicates the
2471                  * signature is valid.  We want to do this after the write
2472                  * has completed so that we don't mark the segment valid
2473                  * while the write is still in progress
2474                  */
2475                 if (i == E1000_ICH_NVM_SIG_WORD)
2476                         data |= E1000_ICH_NVM_SIG_MASK;
2477
2478                 /* Convert offset to bytes. */
2479                 act_offset = (i + new_bank_offset) << 1;
2480
2481                 udelay(100);
2482                 /* Write the bytes to the new bank. */
2483                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2484                                                                act_offset,
2485                                                                (u8)data);
2486                 if (ret_val)
2487                         break;
2488
2489                 udelay(100);
2490                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2491                                                           act_offset + 1,
2492                                                           (u8)(data >> 8));
2493                 if (ret_val)
2494                         break;
2495         }
2496
2497         /*
2498          * Don't bother writing the segment valid bits if sector
2499          * programming failed.
2500          */
2501         if (ret_val) {
2502                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2503                 e_dbg("Flash commit failed.\n");
2504                 goto release;
2505         }
2506
2507         /*
2508          * Finally validate the new segment by setting bit 15:14
2509          * to 10b in word 0x13 , this can be done without an
2510          * erase as well since these bits are 11 to start with
2511          * and we need to change bit 14 to 0b
2512          */
2513         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2514         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2515         if (ret_val)
2516                 goto release;
2517
2518         data &= 0xBFFF;
2519         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2520                                                        act_offset * 2 + 1,
2521                                                        (u8)(data >> 8));
2522         if (ret_val)
2523                 goto release;
2524
2525         /*
2526          * And invalidate the previously valid segment by setting
2527          * its signature word (0x13) high_byte to 0b. This can be
2528          * done without an erase because flash erase sets all bits
2529          * to 1's. We can write 1's to 0's without an erase
2530          */
2531         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2532         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2533         if (ret_val)
2534                 goto release;
2535
2536         /* Great!  Everything worked, we can now clear the cached entries. */
2537         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2538                 dev_spec->shadow_ram[i].modified = false;
2539                 dev_spec->shadow_ram[i].value = 0xFFFF;
2540         }
2541
2542 release:
2543         nvm->ops.release(hw);
2544
2545         /*
2546          * Reload the EEPROM, or else modifications will not appear
2547          * until after the next adapter reset.
2548          */
2549         if (!ret_val) {
2550                 e1000e_reload_nvm(hw);
2551                 usleep_range(10000, 20000);
2552         }
2553
2554 out:
2555         if (ret_val)
2556                 e_dbg("NVM update error: %d\n", ret_val);
2557
2558         return ret_val;
2559 }
2560
2561 /**
2562  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2563  *  @hw: pointer to the HW structure
2564  *
2565  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2566  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2567  *  calculated, in which case we need to calculate the checksum and set bit 6.
2568  **/
2569 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2570 {
2571         s32 ret_val;
2572         u16 data;
2573
2574         /*
2575          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2576          * needs to be fixed.  This bit is an indication that the NVM
2577          * was prepared by OEM software and did not calculate the
2578          * checksum...a likely scenario.
2579          */
2580         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2581         if (ret_val)
2582                 return ret_val;
2583
2584         if ((data & 0x40) == 0) {
2585                 data |= 0x40;
2586                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2587                 if (ret_val)
2588                         return ret_val;
2589                 ret_val = e1000e_update_nvm_checksum(hw);
2590                 if (ret_val)
2591                         return ret_val;
2592         }
2593
2594         return e1000e_validate_nvm_checksum_generic(hw);
2595 }
2596
2597 /**
2598  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2599  *  @hw: pointer to the HW structure
2600  *
2601  *  To prevent malicious write/erase of the NVM, set it to be read-only
2602  *  so that the hardware ignores all write/erase cycles of the NVM via
2603  *  the flash control registers.  The shadow-ram copy of the NVM will
2604  *  still be updated, however any updates to this copy will not stick
2605  *  across driver reloads.
2606  **/
2607 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2608 {
2609         struct e1000_nvm_info *nvm = &hw->nvm;
2610         union ich8_flash_protected_range pr0;
2611         union ich8_hws_flash_status hsfsts;
2612         u32 gfpreg;
2613
2614         nvm->ops.acquire(hw);
2615
2616         gfpreg = er32flash(ICH_FLASH_GFPREG);
2617
2618         /* Write-protect GbE Sector of NVM */
2619         pr0.regval = er32flash(ICH_FLASH_PR0);
2620         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2621         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2622         pr0.range.wpe = true;
2623         ew32flash(ICH_FLASH_PR0, pr0.regval);
2624
2625         /*
2626          * Lock down a subset of GbE Flash Control Registers, e.g.
2627          * PR0 to prevent the write-protection from being lifted.
2628          * Once FLOCKDN is set, the registers protected by it cannot
2629          * be written until FLOCKDN is cleared by a hardware reset.
2630          */
2631         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2632         hsfsts.hsf_status.flockdn = true;
2633         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2634
2635         nvm->ops.release(hw);
2636 }
2637
2638 /**
2639  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2640  *  @hw: pointer to the HW structure
2641  *  @offset: The offset (in bytes) of the byte/word to read.
2642  *  @size: Size of data to read, 1=byte 2=word
2643  *  @data: The byte(s) to write to the NVM.
2644  *
2645  *  Writes one/two bytes to the NVM using the flash access registers.
2646  **/
2647 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2648                                           u8 size, u16 data)
2649 {
2650         union ich8_hws_flash_status hsfsts;
2651         union ich8_hws_flash_ctrl hsflctl;
2652         u32 flash_linear_addr;
2653         u32 flash_data = 0;
2654         s32 ret_val;
2655         u8 count = 0;
2656
2657         if (size < 1 || size > 2 || data > size * 0xff ||
2658             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2659                 return -E1000_ERR_NVM;
2660
2661         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2662                             hw->nvm.flash_base_addr;
2663
2664         do {
2665                 udelay(1);
2666                 /* Steps */
2667                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2668                 if (ret_val)
2669                         break;
2670
2671                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2672                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2673                 hsflctl.hsf_ctrl.fldbcount = size -1;
2674                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2675                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2676
2677                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2678
2679                 if (size == 1)
2680                         flash_data = (u32)data & 0x00FF;
2681                 else
2682                         flash_data = (u32)data;
2683
2684                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2685
2686                 /*
2687                  * check if FCERR is set to 1 , if set to 1, clear it
2688                  * and try the whole sequence a few more times else done
2689                  */
2690                 ret_val = e1000_flash_cycle_ich8lan(hw,
2691                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2692                 if (!ret_val)
2693                         break;
2694
2695                 /*
2696                  * If we're here, then things are most likely
2697                  * completely hosed, but if the error condition
2698                  * is detected, it won't hurt to give it another
2699                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2700                  */
2701                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2702                 if (hsfsts.hsf_status.flcerr == 1)
2703                         /* Repeat for some time before giving up. */
2704                         continue;
2705                 if (hsfsts.hsf_status.flcdone == 0) {
2706                         e_dbg("Timeout error - flash cycle "
2707                                  "did not complete.");
2708                         break;
2709                 }
2710         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2711
2712         return ret_val;
2713 }
2714
2715 /**
2716  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2717  *  @hw: pointer to the HW structure
2718  *  @offset: The index of the byte to read.
2719  *  @data: The byte to write to the NVM.
2720  *
2721  *  Writes a single byte to the NVM using the flash access registers.
2722  **/
2723 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2724                                           u8 data)
2725 {
2726         u16 word = (u16)data;
2727
2728         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2729 }
2730
2731 /**
2732  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2733  *  @hw: pointer to the HW structure
2734  *  @offset: The offset of the byte to write.
2735  *  @byte: The byte to write to the NVM.
2736  *
2737  *  Writes a single byte to the NVM using the flash access registers.
2738  *  Goes through a retry algorithm before giving up.
2739  **/
2740 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2741                                                 u32 offset, u8 byte)
2742 {
2743         s32 ret_val;
2744         u16 program_retries;
2745
2746         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2747         if (!ret_val)
2748                 return ret_val;
2749
2750         for (program_retries = 0; program_retries < 100; program_retries++) {
2751                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2752                 udelay(100);
2753                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2754                 if (!ret_val)
2755                         break;
2756         }
2757         if (program_retries == 100)
2758                 return -E1000_ERR_NVM;
2759
2760         return 0;
2761 }
2762
2763 /**
2764  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2765  *  @hw: pointer to the HW structure
2766  *  @bank: 0 for first bank, 1 for second bank, etc.
2767  *
2768  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2769  *  bank N is 4096 * N + flash_reg_addr.
2770  **/
2771 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2772 {
2773         struct e1000_nvm_info *nvm = &hw->nvm;
2774         union ich8_hws_flash_status hsfsts;
2775         union ich8_hws_flash_ctrl hsflctl;
2776         u32 flash_linear_addr;
2777         /* bank size is in 16bit words - adjust to bytes */
2778         u32 flash_bank_size = nvm->flash_bank_size * 2;
2779         s32 ret_val;
2780         s32 count = 0;
2781         s32 j, iteration, sector_size;
2782
2783         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2784
2785         /*
2786          * Determine HW Sector size: Read BERASE bits of hw flash status
2787          * register
2788          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2789          *     consecutive sectors.  The start index for the nth Hw sector
2790          *     can be calculated as = bank * 4096 + n * 256
2791          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2792          *     The start index for the nth Hw sector can be calculated
2793          *     as = bank * 4096
2794          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2795          *     (ich9 only, otherwise error condition)
2796          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2797          */
2798         switch (hsfsts.hsf_status.berasesz) {
2799         case 0:
2800                 /* Hw sector size 256 */
2801                 sector_size = ICH_FLASH_SEG_SIZE_256;
2802                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2803                 break;
2804         case 1:
2805                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2806                 iteration = 1;
2807                 break;
2808         case 2:
2809                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2810                 iteration = 1;
2811                 break;
2812         case 3:
2813                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2814                 iteration = 1;
2815                 break;
2816         default:
2817                 return -E1000_ERR_NVM;
2818         }
2819
2820         /* Start with the base address, then add the sector offset. */
2821         flash_linear_addr = hw->nvm.flash_base_addr;
2822         flash_linear_addr += (bank) ? flash_bank_size : 0;
2823
2824         for (j = 0; j < iteration ; j++) {
2825                 do {
2826                         /* Steps */
2827                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2828                         if (ret_val)
2829                                 return ret_val;
2830
2831                         /*
2832                          * Write a value 11 (block Erase) in Flash
2833                          * Cycle field in hw flash control
2834                          */
2835                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2836                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2837                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2838
2839                         /*
2840                          * Write the last 24 bits of an index within the
2841                          * block into Flash Linear address field in Flash
2842                          * Address.
2843                          */
2844                         flash_linear_addr += (j * sector_size);
2845                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2846
2847                         ret_val = e1000_flash_cycle_ich8lan(hw,
2848                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2849                         if (ret_val == 0)
2850                                 break;
2851
2852                         /*
2853                          * Check if FCERR is set to 1.  If 1,
2854                          * clear it and try the whole sequence
2855                          * a few more times else Done
2856                          */
2857                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2858                         if (hsfsts.hsf_status.flcerr == 1)
2859                                 /* repeat for some time before giving up */
2860                                 continue;
2861                         else if (hsfsts.hsf_status.flcdone == 0)
2862                                 return ret_val;
2863                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2864         }
2865
2866         return 0;
2867 }
2868
2869 /**
2870  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2871  *  @hw: pointer to the HW structure
2872  *  @data: Pointer to the LED settings
2873  *
2874  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2875  *  settings is all 0's or F's, set the LED default to a valid LED default
2876  *  setting.
2877  **/
2878 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2879 {
2880         s32 ret_val;
2881
2882         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2883         if (ret_val) {
2884                 e_dbg("NVM Read Error\n");
2885                 return ret_val;
2886         }
2887
2888         if (*data == ID_LED_RESERVED_0000 ||
2889             *data == ID_LED_RESERVED_FFFF)
2890                 *data = ID_LED_DEFAULT_ICH8LAN;
2891
2892         return 0;
2893 }
2894
2895 /**
2896  *  e1000_id_led_init_pchlan - store LED configurations
2897  *  @hw: pointer to the HW structure
2898  *
2899  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2900  *  the PHY LED configuration register.
2901  *
2902  *  PCH also does not have an "always on" or "always off" mode which
2903  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2904  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2905  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2906  *  link based on logic in e1000_led_[on|off]_pchlan().
2907  **/
2908 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2909 {
2910         struct e1000_mac_info *mac = &hw->mac;
2911         s32 ret_val;
2912         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2913         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2914         u16 data, i, temp, shift;
2915
2916         /* Get default ID LED modes */
2917         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2918         if (ret_val)
2919                 goto out;
2920
2921         mac->ledctl_default = er32(LEDCTL);
2922         mac->ledctl_mode1 = mac->ledctl_default;
2923         mac->ledctl_mode2 = mac->ledctl_default;
2924
2925         for (i = 0; i < 4; i++) {
2926                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2927                 shift = (i * 5);
2928                 switch (temp) {
2929                 case ID_LED_ON1_DEF2:
2930                 case ID_LED_ON1_ON2:
2931                 case ID_LED_ON1_OFF2:
2932                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2933                         mac->ledctl_mode1 |= (ledctl_on << shift);
2934                         break;
2935                 case ID_LED_OFF1_DEF2:
2936                 case ID_LED_OFF1_ON2:
2937                 case ID_LED_OFF1_OFF2:
2938                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2939                         mac->ledctl_mode1 |= (ledctl_off << shift);
2940                         break;
2941                 default:
2942                         /* Do nothing */
2943                         break;
2944                 }
2945                 switch (temp) {
2946                 case ID_LED_DEF1_ON2:
2947                 case ID_LED_ON1_ON2:
2948                 case ID_LED_OFF1_ON2:
2949                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2950                         mac->ledctl_mode2 |= (ledctl_on << shift);
2951                         break;
2952                 case ID_LED_DEF1_OFF2:
2953                 case ID_LED_ON1_OFF2:
2954                 case ID_LED_OFF1_OFF2:
2955                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2956                         mac->ledctl_mode2 |= (ledctl_off << shift);
2957                         break;
2958                 default:
2959                         /* Do nothing */
2960                         break;
2961                 }
2962         }
2963
2964 out:
2965         return ret_val;
2966 }
2967
2968 /**
2969  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2970  *  @hw: pointer to the HW structure
2971  *
2972  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2973  *  register, so the the bus width is hard coded.
2974  **/
2975 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2976 {
2977         struct e1000_bus_info *bus = &hw->bus;
2978         s32 ret_val;
2979
2980         ret_val = e1000e_get_bus_info_pcie(hw);
2981
2982         /*
2983          * ICH devices are "PCI Express"-ish.  They have
2984          * a configuration space, but do not contain
2985          * PCI Express Capability registers, so bus width
2986          * must be hardcoded.
2987          */
2988         if (bus->width == e1000_bus_width_unknown)
2989                 bus->width = e1000_bus_width_pcie_x1;
2990
2991         return ret_val;
2992 }
2993
2994 /**
2995  *  e1000_reset_hw_ich8lan - Reset the hardware
2996  *  @hw: pointer to the HW structure
2997  *
2998  *  Does a full reset of the hardware which includes a reset of the PHY and
2999  *  MAC.
3000  **/
3001 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3002 {
3003         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3004         u16 reg;
3005         u32 ctrl, kab;
3006         s32 ret_val;
3007
3008         /*
3009          * Prevent the PCI-E bus from sticking if there is no TLP connection
3010          * on the last TLP read/write transaction when MAC is reset.
3011          */
3012         ret_val = e1000e_disable_pcie_master(hw);
3013         if (ret_val)
3014                 e_dbg("PCI-E Master disable polling has failed.\n");
3015
3016         e_dbg("Masking off all interrupts\n");
3017         ew32(IMC, 0xffffffff);
3018
3019         /*
3020          * Disable the Transmit and Receive units.  Then delay to allow
3021          * any pending transactions to complete before we hit the MAC
3022          * with the global reset.
3023          */
3024         ew32(RCTL, 0);
3025         ew32(TCTL, E1000_TCTL_PSP);
3026         e1e_flush();
3027
3028         usleep_range(10000, 20000);
3029
3030         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3031         if (hw->mac.type == e1000_ich8lan) {
3032                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3033                 ew32(PBA, E1000_PBA_8K);
3034                 /* Set Packet Buffer Size to 16k. */
3035                 ew32(PBS, E1000_PBS_16K);
3036         }
3037
3038         if (hw->mac.type == e1000_pchlan) {
3039                 /* Save the NVM K1 bit setting*/
3040                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3041                 if (ret_val)
3042                         return ret_val;
3043
3044                 if (reg & E1000_NVM_K1_ENABLE)
3045                         dev_spec->nvm_k1_enabled = true;
3046                 else
3047                         dev_spec->nvm_k1_enabled = false;
3048         }
3049
3050         ctrl = er32(CTRL);
3051
3052         if (!e1000_check_reset_block(hw)) {
3053                 /*
3054                  * Full-chip reset requires MAC and PHY reset at the same
3055                  * time to make sure the interface between MAC and the
3056                  * external PHY is reset.
3057                  */
3058                 ctrl |= E1000_CTRL_PHY_RST;
3059
3060                 /*
3061                  * Gate automatic PHY configuration by hardware on
3062                  * non-managed 82579
3063                  */
3064                 if ((hw->mac.type == e1000_pch2lan) &&
3065                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3066                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3067         }
3068         ret_val = e1000_acquire_swflag_ich8lan(hw);
3069         e_dbg("Issuing a global reset to ich8lan\n");
3070         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3071         msleep(20);
3072
3073         if (!ret_val)
3074                 mutex_unlock(&swflag_mutex);
3075
3076         if (ctrl & E1000_CTRL_PHY_RST) {
3077                 ret_val = hw->phy.ops.get_cfg_done(hw);
3078                 if (ret_val)
3079                         goto out;
3080
3081                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3082                 if (ret_val)
3083                         goto out;
3084         }
3085
3086         /*
3087          * For PCH, this write will make sure that any noise
3088          * will be detected as a CRC error and be dropped rather than show up
3089          * as a bad packet to the DMA engine.
3090          */
3091         if (hw->mac.type == e1000_pchlan)
3092                 ew32(CRC_OFFSET, 0x65656565);
3093
3094         ew32(IMC, 0xffffffff);
3095         er32(ICR);
3096
3097         kab = er32(KABGTXD);
3098         kab |= E1000_KABGTXD_BGSQLBIAS;
3099         ew32(KABGTXD, kab);
3100
3101 out:
3102         return ret_val;
3103 }
3104
3105 /**
3106  *  e1000_init_hw_ich8lan - Initialize the hardware
3107  *  @hw: pointer to the HW structure
3108  *
3109  *  Prepares the hardware for transmit and receive by doing the following:
3110  *   - initialize hardware bits
3111  *   - initialize LED identification
3112  *   - setup receive address registers
3113  *   - setup flow control
3114  *   - setup transmit descriptors
3115  *   - clear statistics
3116  **/
3117 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3118 {
3119         struct e1000_mac_info *mac = &hw->mac;
3120         u32 ctrl_ext, txdctl, snoop;
3121         s32 ret_val;
3122         u16 i;
3123
3124         e1000_initialize_hw_bits_ich8lan(hw);
3125
3126         /* Initialize identification LED */
3127         ret_val = mac->ops.id_led_init(hw);
3128         if (ret_val)
3129                 e_dbg("Error initializing identification LED\n");
3130                 /* This is not fatal and we should not stop init due to this */
3131
3132         /* Setup the receive address. */
3133         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3134
3135         /* Zero out the Multicast HASH table */
3136         e_dbg("Zeroing the MTA\n");
3137         for (i = 0; i < mac->mta_reg_count; i++)
3138                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3139
3140         /*
3141          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3142          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
3143          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3144          */
3145         if (hw->phy.type == e1000_phy_82578) {
3146                 e1e_rphy(hw, BM_WUC, &i);
3147                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3148                 if (ret_val)
3149                         return ret_val;
3150         }
3151
3152         /* Setup link and flow control */
3153         ret_val = e1000_setup_link_ich8lan(hw);
3154
3155         /* Set the transmit descriptor write-back policy for both queues */
3156         txdctl = er32(TXDCTL(0));
3157         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3158                  E1000_TXDCTL_FULL_TX_DESC_WB;
3159         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3160                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3161         ew32(TXDCTL(0), txdctl);
3162         txdctl = er32(TXDCTL(1));
3163         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3164                  E1000_TXDCTL_FULL_TX_DESC_WB;
3165         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3166                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3167         ew32(TXDCTL(1), txdctl);
3168
3169         /*
3170          * ICH8 has opposite polarity of no_snoop bits.
3171          * By default, we should use snoop behavior.
3172          */
3173         if (mac->type == e1000_ich8lan)
3174                 snoop = PCIE_ICH8_SNOOP_ALL;
3175         else
3176                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3177         e1000e_set_pcie_no_snoop(hw, snoop);
3178
3179         ctrl_ext = er32(CTRL_EXT);
3180         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3181         ew32(CTRL_EXT, ctrl_ext);
3182
3183         /*
3184          * Clear all of the statistics registers (clear on read).  It is
3185          * important that we do this after we have tried to establish link
3186          * because the symbol error count will increment wildly if there
3187          * is no link.
3188          */
3189         e1000_clear_hw_cntrs_ich8lan(hw);
3190
3191         return 0;
3192 }
3193 /**
3194  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3195  *  @hw: pointer to the HW structure
3196  *
3197  *  Sets/Clears required hardware bits necessary for correctly setting up the
3198  *  hardware for transmit and receive.
3199  **/
3200 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3201 {
3202         u32 reg;
3203
3204         /* Extended Device Control */
3205         reg = er32(CTRL_EXT);
3206         reg |= (1 << 22);
3207         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3208         if (hw->mac.type >= e1000_pchlan)
3209                 reg |= E1000_CTRL_EXT_PHYPDEN;
3210         ew32(CTRL_EXT, reg);
3211
3212         /* Transmit Descriptor Control 0 */
3213         reg = er32(TXDCTL(0));
3214         reg |= (1 << 22);
3215         ew32(TXDCTL(0), reg);
3216
3217         /* Transmit Descriptor Control 1 */
3218         reg = er32(TXDCTL(1));
3219         reg |= (1 << 22);
3220         ew32(TXDCTL(1), reg);
3221
3222         /* Transmit Arbitration Control 0 */
3223         reg = er32(TARC(0));
3224         if (hw->mac.type == e1000_ich8lan)
3225                 reg |= (1 << 28) | (1 << 29);
3226         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3227         ew32(TARC(0), reg);
3228
3229         /* Transmit Arbitration Control 1 */
3230         reg = er32(TARC(1));
3231         if (er32(TCTL) & E1000_TCTL_MULR)
3232                 reg &= ~(1 << 28);
3233         else
3234                 reg |= (1 << 28);
3235         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3236         ew32(TARC(1), reg);
3237
3238         /* Device Status */
3239         if (hw->mac.type == e1000_ich8lan) {
3240                 reg = er32(STATUS);
3241                 reg &= ~(1 << 31);
3242                 ew32(STATUS, reg);
3243         }
3244
3245         /*
3246          * work-around descriptor data corruption issue during nfs v2 udp
3247          * traffic, just disable the nfs filtering capability
3248          */
3249         reg = er32(RFCTL);
3250         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3251         ew32(RFCTL, reg);
3252 }
3253
3254 /**
3255  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3256  *  @hw: pointer to the HW structure
3257  *
3258  *  Determines which flow control settings to use, then configures flow
3259  *  control.  Calls the appropriate media-specific link configuration
3260  *  function.  Assuming the adapter has a valid link partner, a valid link
3261  *  should be established.  Assumes the hardware has previously been reset
3262  *  and the transmitter and receiver are not enabled.
3263  **/
3264 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3265 {
3266         s32 ret_val;
3267
3268         if (e1000_check_reset_block(hw))
3269                 return 0;
3270
3271         /*
3272          * ICH parts do not have a word in the NVM to determine
3273          * the default flow control setting, so we explicitly
3274          * set it to full.
3275          */
3276         if (hw->fc.requested_mode == e1000_fc_default) {
3277                 /* Workaround h/w hang when Tx flow control enabled */
3278                 if (hw->mac.type == e1000_pchlan)
3279                         hw->fc.requested_mode = e1000_fc_rx_pause;
3280                 else
3281                         hw->fc.requested_mode = e1000_fc_full;
3282         }
3283
3284         /*
3285          * Save off the requested flow control mode for use later.  Depending
3286          * on the link partner's capabilities, we may or may not use this mode.
3287          */
3288         hw->fc.current_mode = hw->fc.requested_mode;
3289
3290         e_dbg("After fix-ups FlowControl is now = %x\n",
3291                 hw->fc.current_mode);
3292
3293         /* Continue to configure the copper link. */
3294         ret_val = e1000_setup_copper_link_ich8lan(hw);
3295         if (ret_val)
3296                 return ret_val;
3297
3298         ew32(FCTTV, hw->fc.pause_time);
3299         if ((hw->phy.type == e1000_phy_82578) ||
3300             (hw->phy.type == e1000_phy_82579) ||
3301             (hw->phy.type == e1000_phy_82577)) {
3302                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3303
3304                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3305                                    hw->fc.pause_time);
3306                 if (ret_val)
3307                         return ret_val;
3308         }
3309
3310         return e1000e_set_fc_watermarks(hw);
3311 }
3312
3313 /**
3314  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3315  *  @hw: pointer to the HW structure
3316  *
3317  *  Configures the kumeran interface to the PHY to wait the appropriate time
3318  *  when polling the PHY, then call the generic setup_copper_link to finish
3319  *  configuring the copper link.
3320  **/
3321 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3322 {
3323         u32 ctrl;
3324         s32 ret_val;
3325         u16 reg_data;
3326
3327         ctrl = er32(CTRL);
3328         ctrl |= E1000_CTRL_SLU;
3329         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3330         ew32(CTRL, ctrl);
3331
3332         /*
3333          * Set the mac to wait the maximum time between each iteration
3334          * and increase the max iterations when polling the phy;
3335          * this fixes erroneous timeouts at 10Mbps.
3336          */
3337         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3338         if (ret_val)
3339                 return ret_val;
3340         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3341                                        &reg_data);
3342         if (ret_val)
3343                 return ret_val;
3344         reg_data |= 0x3F;
3345         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3346                                         reg_data);
3347         if (ret_val)
3348                 return ret_val;
3349
3350         switch (hw->phy.type) {
3351         case e1000_phy_igp_3:
3352                 ret_val = e1000e_copper_link_setup_igp(hw);
3353                 if (ret_val)
3354                         return ret_val;
3355                 break;
3356         case e1000_phy_bm:
3357         case e1000_phy_82578:
3358                 ret_val = e1000e_copper_link_setup_m88(hw);
3359                 if (ret_val)
3360                         return ret_val;
3361                 break;
3362         case e1000_phy_82577:
3363         case e1000_phy_82579:
3364                 ret_val = e1000_copper_link_setup_82577(hw);
3365                 if (ret_val)
3366                         return ret_val;
3367                 break;
3368         case e1000_phy_ife:
3369                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3370                 if (ret_val)
3371                         return ret_val;
3372
3373                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3374
3375                 switch (hw->phy.mdix) {
3376                 case 1:
3377                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3378                         break;
3379                 case 2:
3380                         reg_data |= IFE_PMC_FORCE_MDIX;
3381                         break;
3382                 case 0:
3383                 default:
3384                         reg_data |= IFE_PMC_AUTO_MDIX;
3385                         break;
3386                 }
3387                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3388                 if (ret_val)
3389                         return ret_val;
3390                 break;
3391         default:
3392                 break;
3393         }
3394         return e1000e_setup_copper_link(hw);
3395 }
3396
3397 /**
3398  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3399  *  @hw: pointer to the HW structure
3400  *  @speed: pointer to store current link speed
3401  *  @duplex: pointer to store the current link duplex
3402  *
3403  *  Calls the generic get_speed_and_duplex to retrieve the current link
3404  *  information and then calls the Kumeran lock loss workaround for links at
3405  *  gigabit speeds.
3406  **/
3407 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3408                                           u16 *duplex)
3409 {
3410         s32 ret_val;
3411
3412         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3413         if (ret_val)
3414                 return ret_val;
3415
3416         if ((hw->mac.type == e1000_ich8lan) &&
3417             (hw->phy.type == e1000_phy_igp_3) &&
3418             (*speed == SPEED_1000)) {
3419                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3420         }
3421
3422         return ret_val;
3423 }
3424
3425 /**
3426  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3427  *  @hw: pointer to the HW structure
3428  *
3429  *  Work-around for 82566 Kumeran PCS lock loss:
3430  *  On link status change (i.e. PCI reset, speed change) and link is up and
3431  *  speed is gigabit-
3432  *    0) if workaround is optionally disabled do nothing
3433  *    1) wait 1ms for Kumeran link to come up
3434  *    2) check Kumeran Diagnostic register PCS lock loss bit
3435  *    3) if not set the link is locked (all is good), otherwise...
3436  *    4) reset the PHY
3437  *    5) repeat up to 10 times
3438  *  Note: this is only called for IGP3 copper when speed is 1gb.
3439  **/
3440 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3441 {
3442         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3443         u32 phy_ctrl;
3444         s32 ret_val;
3445         u16 i, data;
3446         bool link;
3447
3448         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3449                 return 0;
3450
3451         /*
3452          * Make sure link is up before proceeding.  If not just return.
3453          * Attempting this while link is negotiating fouled up link
3454          * stability
3455          */
3456         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3457         if (!link)
3458                 return 0;
3459
3460         for (i = 0; i < 10; i++) {
3461                 /* read once to clear */
3462                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3463                 if (ret_val)
3464                         return ret_val;
3465                 /* and again to get new status */
3466                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3467                 if (ret_val)
3468                         return ret_val;
3469
3470                 /* check for PCS lock */
3471                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3472                         return 0;
3473
3474                 /* Issue PHY reset */
3475                 e1000_phy_hw_reset(hw);
3476                 mdelay(5);
3477         }
3478         /* Disable GigE link negotiation */
3479         phy_ctrl = er32(PHY_CTRL);
3480         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3481                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3482         ew32(PHY_CTRL, phy_ctrl);
3483
3484         /*
3485          * Call gig speed drop workaround on Gig disable before accessing
3486          * any PHY registers
3487          */
3488         e1000e_gig_downshift_workaround_ich8lan(hw);
3489
3490         /* unable to acquire PCS lock */
3491         return -E1000_ERR_PHY;
3492 }
3493
3494 /**
3495  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3496  *  @hw: pointer to the HW structure
3497  *  @state: boolean value used to set the current Kumeran workaround state
3498  *
3499  *  If ICH8, set the current Kumeran workaround state (enabled - true
3500  *  /disabled - false).
3501  **/
3502 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3503                                                  bool state)
3504 {
3505         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3506
3507         if (hw->mac.type != e1000_ich8lan) {
3508                 e_dbg("Workaround applies to ICH8 only.\n");
3509                 return;
3510         }
3511
3512         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3513 }
3514
3515 /**
3516  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3517  *  @hw: pointer to the HW structure
3518  *
3519  *  Workaround for 82566 power-down on D3 entry:
3520  *    1) disable gigabit link
3521  *    2) write VR power-down enable
3522  *    3) read it back
3523  *  Continue if successful, else issue LCD reset and repeat
3524  **/
3525 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3526 {
3527         u32 reg;
3528         u16 data;
3529         u8  retry = 0;
3530
3531         if (hw->phy.type != e1000_phy_igp_3)
3532                 return;
3533
3534         /* Try the workaround twice (if needed) */
3535         do {
3536                 /* Disable link */
3537                 reg = er32(PHY_CTRL);
3538                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3539                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3540                 ew32(PHY_CTRL, reg);
3541
3542                 /*
3543                  * Call gig speed drop workaround on Gig disable before
3544                  * accessing any PHY registers
3545                  */
3546                 if (hw->mac.type == e1000_ich8lan)
3547                         e1000e_gig_downshift_workaround_ich8lan(hw);
3548
3549                 /* Write VR power-down enable */
3550                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3551                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3552                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3553
3554                 /* Read it back and test */
3555                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3556                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3557                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3558                         break;
3559
3560                 /* Issue PHY reset and repeat at most one more time */
3561                 reg = er32(CTRL);
3562                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3563                 retry++;
3564         } while (retry);
3565 }
3566
3567 /**
3568  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3569  *  @hw: pointer to the HW structure
3570  *
3571  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3572  *  LPLU, Gig disable, MDIC PHY reset):
3573  *    1) Set Kumeran Near-end loopback
3574  *    2) Clear Kumeran Near-end loopback
3575  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3576  **/
3577 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3578 {
3579         s32 ret_val;
3580         u16 reg_data;
3581
3582         if ((hw->mac.type != e1000_ich8lan) ||
3583             (hw->phy.type != e1000_phy_igp_3))
3584                 return;
3585
3586         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3587                                       &reg_data);
3588         if (ret_val)
3589                 return;
3590         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3591         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3592                                        reg_data);
3593         if (ret_val)
3594                 return;
3595         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3596         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3597                                        reg_data);
3598 }
3599
3600 /**
3601  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3602  *  @hw: pointer to the HW structure
3603  *
3604  *  During S0 to Sx transition, it is possible the link remains at gig
3605  *  instead of negotiating to a lower speed.  Before going to Sx, set
3606  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3607  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3608  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3609  **/
3610 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3611 {
3612         u32 phy_ctrl;
3613         s32 ret_val;
3614
3615         phy_ctrl = er32(PHY_CTRL);
3616         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3617         ew32(PHY_CTRL, phy_ctrl);
3618
3619         if (hw->mac.type >= e1000_pchlan) {
3620                 e1000_oem_bits_config_ich8lan(hw, false);
3621                 ret_val = hw->phy.ops.acquire(hw);
3622                 if (ret_val)
3623                         return;
3624                 e1000_write_smbus_addr(hw);
3625                 hw->phy.ops.release(hw);
3626         }
3627 }
3628
3629 /**
3630  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3631  *  @hw: pointer to the HW structure
3632  *
3633  *  During Sx to S0 transitions on non-managed devices or managed devices
3634  *  on which PHY resets are not blocked, if the PHY registers cannot be
3635  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3636  *  the PHY.
3637  **/
3638 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3639 {
3640         u32 fwsm;
3641
3642         if (hw->mac.type != e1000_pch2lan)
3643                 return;
3644
3645         fwsm = er32(FWSM);
3646         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3647                 u16 phy_id1, phy_id2;
3648                 s32 ret_val;
3649
3650                 ret_val = hw->phy.ops.acquire(hw);
3651                 if (ret_val) {
3652                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3653                         return;
3654                 }
3655
3656                 /* Test access to the PHY registers by reading the ID regs */
3657                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3658                 if (ret_val)
3659                         goto release;
3660                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3661                 if (ret_val)
3662                         goto release;
3663
3664                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3665                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3666                         goto release;
3667
3668                 e1000_toggle_lanphypc_value_ich8lan(hw);
3669
3670                 hw->phy.ops.release(hw);
3671                 msleep(50);
3672                 e1000_phy_hw_reset(hw);
3673                 msleep(50);
3674                 return;
3675         }
3676
3677 release:
3678         hw->phy.ops.release(hw);
3679
3680         return;
3681 }
3682
3683 /**
3684  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3685  *  @hw: pointer to the HW structure
3686  *
3687  *  Return the LED back to the default configuration.
3688  **/
3689 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3690 {
3691         if (hw->phy.type == e1000_phy_ife)
3692                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3693
3694         ew32(LEDCTL, hw->mac.ledctl_default);
3695         return 0;
3696 }
3697
3698 /**
3699  *  e1000_led_on_ich8lan - Turn LEDs on
3700  *  @hw: pointer to the HW structure
3701  *
3702  *  Turn on the LEDs.
3703  **/
3704 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3705 {
3706         if (hw->phy.type == e1000_phy_ife)
3707                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3708                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3709
3710         ew32(LEDCTL, hw->mac.ledctl_mode2);
3711         return 0;
3712 }
3713
3714 /**
3715  *  e1000_led_off_ich8lan - Turn LEDs off
3716  *  @hw: pointer to the HW structure
3717  *
3718  *  Turn off the LEDs.
3719  **/
3720 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3721 {
3722         if (hw->phy.type == e1000_phy_ife)
3723                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3724                                 (IFE_PSCL_PROBE_MODE |
3725                                  IFE_PSCL_PROBE_LEDS_OFF));
3726
3727         ew32(LEDCTL, hw->mac.ledctl_mode1);
3728         return 0;
3729 }
3730
3731 /**
3732  *  e1000_setup_led_pchlan - Configures SW controllable LED
3733  *  @hw: pointer to the HW structure
3734  *
3735  *  This prepares the SW controllable LED for use.
3736  **/
3737 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3738 {
3739         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3740 }
3741
3742 /**
3743  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3744  *  @hw: pointer to the HW structure
3745  *
3746  *  Return the LED back to the default configuration.
3747  **/
3748 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3749 {
3750         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3751 }
3752
3753 /**
3754  *  e1000_led_on_pchlan - Turn LEDs on
3755  *  @hw: pointer to the HW structure
3756  *
3757  *  Turn on the LEDs.
3758  **/
3759 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3760 {
3761         u16 data = (u16)hw->mac.ledctl_mode2;
3762         u32 i, led;
3763
3764         /*
3765          * If no link, then turn LED on by setting the invert bit
3766          * for each LED that's mode is "link_up" in ledctl_mode2.
3767          */
3768         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3769                 for (i = 0; i < 3; i++) {
3770                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3771                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3772                             E1000_LEDCTL_MODE_LINK_UP)
3773                                 continue;
3774                         if (led & E1000_PHY_LED0_IVRT)
3775                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3776                         else
3777                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3778                 }
3779         }
3780
3781         return e1e_wphy(hw, HV_LED_CONFIG, data);
3782 }
3783
3784 /**
3785  *  e1000_led_off_pchlan - Turn LEDs off
3786  *  @hw: pointer to the HW structure
3787  *
3788  *  Turn off the LEDs.
3789  **/
3790 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3791 {
3792         u16 data = (u16)hw->mac.ledctl_mode1;
3793         u32 i, led;
3794
3795         /*
3796          * If no link, then turn LED off by clearing the invert bit
3797          * for each LED that's mode is "link_up" in ledctl_mode1.
3798          */
3799         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3800                 for (i = 0; i < 3; i++) {
3801                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3802                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3803                             E1000_LEDCTL_MODE_LINK_UP)
3804                                 continue;
3805                         if (led & E1000_PHY_LED0_IVRT)
3806                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3807                         else
3808                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3809                 }
3810         }
3811
3812         return e1e_wphy(hw, HV_LED_CONFIG, data);
3813 }
3814
3815 /**
3816  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3817  *  @hw: pointer to the HW structure
3818  *
3819  *  Read appropriate register for the config done bit for completion status
3820  *  and configure the PHY through s/w for EEPROM-less parts.
3821  *
3822  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3823  *  config done bit, so only an error is logged and continues.  If we were
3824  *  to return with error, EEPROM-less silicon would not be able to be reset
3825  *  or change link.
3826  **/
3827 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3828 {
3829         s32 ret_val = 0;
3830         u32 bank = 0;
3831         u32 status;
3832
3833         e1000e_get_cfg_done(hw);
3834
3835         /* Wait for indication from h/w that it has completed basic config */
3836         if (hw->mac.type >= e1000_ich10lan) {
3837                 e1000_lan_init_done_ich8lan(hw);
3838         } else {
3839                 ret_val = e1000e_get_auto_rd_done(hw);
3840                 if (ret_val) {
3841                         /*
3842                          * When auto config read does not complete, do not
3843                          * return with an error. This can happen in situations
3844                          * where there is no eeprom and prevents getting link.
3845                          */
3846                         e_dbg("Auto Read Done did not complete\n");
3847                         ret_val = 0;
3848                 }
3849         }
3850
3851         /* Clear PHY Reset Asserted bit */
3852         status = er32(STATUS);
3853         if (status & E1000_STATUS_PHYRA)
3854                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3855         else
3856                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3857
3858         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3859         if (hw->mac.type <= e1000_ich9lan) {
3860                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3861                     (hw->phy.type == e1000_phy_igp_3)) {
3862                         e1000e_phy_init_script_igp3(hw);
3863                 }
3864         } else {
3865                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3866                         /* Maybe we should do a basic PHY config */
3867                         e_dbg("EEPROM not present\n");
3868                         ret_val = -E1000_ERR_CONFIG;
3869                 }
3870         }
3871
3872         return ret_val;
3873 }
3874
3875 /**
3876  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3877  * @hw: pointer to the HW structure
3878  *
3879  * In the case of a PHY power down to save power, or to turn off link during a
3880  * driver unload, or wake on lan is not enabled, remove the link.
3881  **/
3882 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3883 {
3884         /* If the management interface is not enabled, then power down */
3885         if (!(hw->mac.ops.check_mng_mode(hw) ||
3886               hw->phy.ops.check_reset_block(hw)))
3887                 e1000_power_down_phy_copper(hw);
3888 }
3889
3890 /**
3891  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3892  *  @hw: pointer to the HW structure
3893  *
3894  *  Clears hardware counters specific to the silicon family and calls
3895  *  clear_hw_cntrs_generic to clear all general purpose counters.
3896  **/
3897 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3898 {
3899         u16 phy_data;
3900
3901         e1000e_clear_hw_cntrs_base(hw);
3902
3903         er32(ALGNERRC);
3904         er32(RXERRC);
3905         er32(TNCRS);
3906         er32(CEXTERR);
3907         er32(TSCTC);
3908         er32(TSCTFC);
3909
3910         er32(MGTPRC);
3911         er32(MGTPDC);
3912         er32(MGTPTC);
3913
3914         er32(IAC);
3915         er32(ICRXOC);
3916
3917         /* Clear PHY statistics registers */
3918         if ((hw->phy.type == e1000_phy_82578) ||
3919             (hw->phy.type == e1000_phy_82579) ||
3920             (hw->phy.type == e1000_phy_82577)) {
3921                 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3922                 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3923                 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3924                 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3925                 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3926                 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3927                 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3928                 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3929                 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3930                 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3931                 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3932                 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3933                 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3934                 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3935         }
3936 }
3937
3938 static struct e1000_mac_operations ich8_mac_ops = {
3939         .id_led_init            = e1000e_id_led_init,
3940         /* check_mng_mode dependent on mac type */
3941         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3942         /* cleanup_led dependent on mac type */
3943         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3944         .get_bus_info           = e1000_get_bus_info_ich8lan,
3945         .set_lan_id             = e1000_set_lan_id_single_port,
3946         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3947         /* led_on dependent on mac type */
3948         /* led_off dependent on mac type */
3949         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3950         .reset_hw               = e1000_reset_hw_ich8lan,
3951         .init_hw                = e1000_init_hw_ich8lan,
3952         .setup_link             = e1000_setup_link_ich8lan,
3953         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3954         /* id_led_init dependent on mac type */
3955 };
3956
3957 static struct e1000_phy_operations ich8_phy_ops = {
3958         .acquire                = e1000_acquire_swflag_ich8lan,
3959         .check_reset_block      = e1000_check_reset_block_ich8lan,
3960         .commit                 = NULL,
3961         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3962         .get_cable_length       = e1000e_get_cable_length_igp_2,
3963         .read_reg               = e1000e_read_phy_reg_igp,
3964         .release                = e1000_release_swflag_ich8lan,
3965         .reset                  = e1000_phy_hw_reset_ich8lan,
3966         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3967         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3968         .write_reg              = e1000e_write_phy_reg_igp,
3969 };
3970
3971 static struct e1000_nvm_operations ich8_nvm_ops = {
3972         .acquire                = e1000_acquire_nvm_ich8lan,
3973         .read                   = e1000_read_nvm_ich8lan,
3974         .release                = e1000_release_nvm_ich8lan,
3975         .update                 = e1000_update_nvm_checksum_ich8lan,
3976         .valid_led_default      = e1000_valid_led_default_ich8lan,
3977         .validate               = e1000_validate_nvm_checksum_ich8lan,
3978         .write                  = e1000_write_nvm_ich8lan,
3979 };
3980
3981 struct e1000_info e1000_ich8_info = {
3982         .mac                    = e1000_ich8lan,
3983         .flags                  = FLAG_HAS_WOL
3984                                   | FLAG_IS_ICH
3985                                   | FLAG_RX_CSUM_ENABLED
3986                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3987                                   | FLAG_HAS_AMT
3988                                   | FLAG_HAS_FLASH
3989                                   | FLAG_APME_IN_WUC,
3990         .pba                    = 8,
3991         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3992         .get_variants           = e1000_get_variants_ich8lan,
3993         .mac_ops                = &ich8_mac_ops,
3994         .phy_ops                = &ich8_phy_ops,
3995         .nvm_ops                = &ich8_nvm_ops,
3996 };
3997
3998 struct e1000_info e1000_ich9_info = {
3999         .mac                    = e1000_ich9lan,
4000         .flags                  = FLAG_HAS_JUMBO_FRAMES
4001                                   | FLAG_IS_ICH
4002                                   | FLAG_HAS_WOL
4003                                   | FLAG_RX_CSUM_ENABLED
4004                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4005                                   | FLAG_HAS_AMT
4006                                   | FLAG_HAS_ERT
4007                                   | FLAG_HAS_FLASH
4008                                   | FLAG_APME_IN_WUC,
4009         .pba                    = 10,
4010         .max_hw_frame_size      = DEFAULT_JUMBO,
4011         .get_variants           = e1000_get_variants_ich8lan,
4012         .mac_ops                = &ich8_mac_ops,
4013         .phy_ops                = &ich8_phy_ops,
4014         .nvm_ops                = &ich8_nvm_ops,
4015 };
4016
4017 struct e1000_info e1000_ich10_info = {
4018         .mac                    = e1000_ich10lan,
4019         .flags                  = FLAG_HAS_JUMBO_FRAMES
4020                                   | FLAG_IS_ICH
4021                                   | FLAG_HAS_WOL
4022                                   | FLAG_RX_CSUM_ENABLED
4023                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4024                                   | FLAG_HAS_AMT
4025                                   | FLAG_HAS_ERT
4026                                   | FLAG_HAS_FLASH
4027                                   | FLAG_APME_IN_WUC,
4028         .pba                    = 10,
4029         .max_hw_frame_size      = DEFAULT_JUMBO,
4030         .get_variants           = e1000_get_variants_ich8lan,
4031         .mac_ops                = &ich8_mac_ops,
4032         .phy_ops                = &ich8_phy_ops,
4033         .nvm_ops                = &ich8_nvm_ops,
4034 };
4035
4036 struct e1000_info e1000_pch_info = {
4037         .mac                    = e1000_pchlan,
4038         .flags                  = FLAG_IS_ICH
4039                                   | FLAG_HAS_WOL
4040                                   | FLAG_RX_CSUM_ENABLED
4041                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4042                                   | FLAG_HAS_AMT
4043                                   | FLAG_HAS_FLASH
4044                                   | FLAG_HAS_JUMBO_FRAMES
4045                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4046                                   | FLAG_APME_IN_WUC,
4047         .flags2                 = FLAG2_HAS_PHY_STATS,
4048         .pba                    = 26,
4049         .max_hw_frame_size      = 4096,
4050         .get_variants           = e1000_get_variants_ich8lan,
4051         .mac_ops                = &ich8_mac_ops,
4052         .phy_ops                = &ich8_phy_ops,
4053         .nvm_ops                = &ich8_nvm_ops,
4054 };
4055
4056 struct e1000_info e1000_pch2_info = {
4057         .mac                    = e1000_pch2lan,
4058         .flags                  = FLAG_IS_ICH
4059                                   | FLAG_HAS_WOL
4060                                   | FLAG_RX_CSUM_ENABLED
4061                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4062                                   | FLAG_HAS_AMT
4063                                   | FLAG_HAS_FLASH
4064                                   | FLAG_HAS_JUMBO_FRAMES
4065                                   | FLAG_APME_IN_WUC,
4066         .flags2                 = FLAG2_HAS_PHY_STATS
4067                                   | FLAG2_HAS_EEE,
4068         .pba                    = 26,
4069         .max_hw_frame_size      = DEFAULT_JUMBO,
4070         .get_variants           = e1000_get_variants_ich8lan,
4071         .mac_ops                = &ich8_mac_ops,
4072         .phy_ops                = &ich8_phy_ops,
4073         .nvm_ops                = &ich8_nvm_ops,
4074 };