2 * Blackfin On-Chip MAC Driver
4 * Copyright 2004-2010 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #define DRV_VERSION "1.1"
12 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
26 #include <linux/ioport.h>
27 #include <linux/crc32.h>
28 #include <linux/device.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
40 #include <asm/div64.h>
42 #include <asm/blackfin.h>
43 #include <asm/cacheflush.h>
44 #include <asm/portmux.h>
49 MODULE_AUTHOR("Bryan Wu, Luke Yang");
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56 # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
58 # define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
64 #define PKT_BUF_SZ 1580
66 #define MAX_TIMEOUT_CNT 500
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
78 static void desc_list_free(void)
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
83 #if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
92 dev_kfree_skb(t->skb);
98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
106 dev_kfree_skb(r->skb);
112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
116 static int desc_list_init(struct net_device *dev)
119 struct sk_buff *new_skb;
120 #if !defined(CONFIG_BFIN_MAC_USE_L1)
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
125 dma_addr_t dma_handle;
128 tx_desc = bfin_mac_alloc(&dma_handle,
129 sizeof(struct net_dma_desc_tx),
130 CONFIG_BFIN_TX_DESC_NUM);
134 rx_desc = bfin_mac_alloc(&dma_handle,
135 sizeof(struct net_dma_desc_rx),
136 CONFIG_BFIN_RX_DESC_NUM);
141 tx_list_head = tx_list_tail = tx_desc;
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
158 a->next_dma_desc = b;
162 * write to memory WNR = 1
163 * wordsize is 32 bits
165 * 6 half words is desc size
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
182 rx_list_head = rx_list_tail = rx_desc;
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
189 /* allocate a new skb for next time receive */
190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
194 skb_reserve(new_skb, NET_IP_ALIGN);
195 /* Invidate the data cache of skb->data range when it is write back
196 * cache. It will prevent overwritting the new data from DMA
198 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199 (unsigned long)new_skb->end);
204 * write to memory WNR = 1
205 * wordsize is 32 bits
207 * 6 half words is desc size
210 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211 /* since RXDWA is enabled */
212 a->start_addr = (unsigned long)new_skb->data - 2;
214 a->next_dma_desc = b;
218 * write to memory WNR = 1
219 * wordsize is 32 bits
221 * 6 half words is desc size
224 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225 NDSIZE_6 | DMAFLOW_LARGE;
226 b->start_addr = (unsigned long)(&(r->status));
229 rx_list_tail->desc_b.next_dma_desc = a;
230 rx_list_tail->next = r;
233 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
234 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235 current_rx_ptr = rx_list_head;
241 pr_err("kmalloc failed\n");
246 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
251 /* Wait until the previous MDC/MDIO transaction has completed */
252 static int bfin_mdio_poll(void)
254 int timeout_cnt = MAX_TIMEOUT_CNT;
256 /* poll the STABUSY bit */
257 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
259 if (timeout_cnt-- < 0) {
260 pr_err("wait MDC/MDIO transaction to complete timeout\n");
268 /* Read an off-chip register in a PHY through the MDC/MDIO port */
269 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
273 ret = bfin_mdio_poll();
278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
282 ret = bfin_mdio_poll();
286 return (int) bfin_read_EMAC_STADAT();
289 /* Write an off-chip register in a PHY through the MDC/MDIO port */
290 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
295 ret = bfin_mdio_poll();
299 bfin_write_EMAC_STADAT((u32) value);
302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
307 return bfin_mdio_poll();
310 static void bfin_mac_adjust_link(struct net_device *dev)
312 struct bfin_mac_local *lp = netdev_priv(dev);
313 struct phy_device *phydev = lp->phydev;
317 spin_lock_irqsave(&lp->lock, flags);
319 /* Now we make sure that we can be in full duplex mode.
320 * If not, we operate in half-duplex mode. */
321 if (phydev->duplex != lp->old_duplex) {
322 u32 opmode = bfin_read_EMAC_OPMODE();
330 bfin_write_EMAC_OPMODE(opmode);
331 lp->old_duplex = phydev->duplex;
334 if (phydev->speed != lp->old_speed) {
335 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
336 u32 opmode = bfin_read_EMAC_OPMODE();
337 switch (phydev->speed) {
346 "Ack! Speed (%d) is not 10/100!\n",
350 bfin_write_EMAC_OPMODE(opmode);
354 lp->old_speed = phydev->speed;
361 } else if (lp->old_link) {
369 u32 opmode = bfin_read_EMAC_OPMODE();
370 phy_print_status(phydev);
371 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
374 spin_unlock_irqrestore(&lp->lock, flags);
378 #define MDC_CLK 2500000
380 static int mii_probe(struct net_device *dev, int phy_mode)
382 struct bfin_mac_local *lp = netdev_priv(dev);
383 struct phy_device *phydev = NULL;
384 unsigned short sysctl;
388 /* Enable PHY output early */
389 if (!(bfin_read_VR_CTL() & CLKBUFOE))
390 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
393 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
395 sysctl = bfin_read_EMAC_SYSCTL();
396 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
397 bfin_write_EMAC_SYSCTL(sysctl);
399 /* search for connected PHY device */
400 for (i = 0; i < PHY_MAX_ADDR; ++i) {
401 struct phy_device *const tmp_phydev =
402 mdiobus_get_phy(lp->mii_bus, i);
405 continue; /* no PHY here... */
408 break; /* found it */
411 /* now we are supposed to have a proper phydev, to attach to... */
413 netdev_err(dev, "no phy device found\n");
417 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
418 phy_mode != PHY_INTERFACE_MODE_MII) {
419 netdev_err(dev, "invalid phy interface mode\n");
423 phydev = phy_connect(dev, phydev_name(phydev),
424 &bfin_mac_adjust_link, phy_mode);
426 if (IS_ERR(phydev)) {
427 netdev_err(dev, "could not attach PHY\n");
428 return PTR_ERR(phydev);
431 /* mask with MAC supported features */
432 phydev->supported &= (SUPPORTED_10baseT_Half
433 | SUPPORTED_10baseT_Full
434 | SUPPORTED_100baseT_Half
435 | SUPPORTED_100baseT_Full
437 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
441 phydev->advertising = phydev->supported;
448 phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
449 MDC_CLK, mdc_div, sclk / 1000000);
459 * interrupt routine for magic packet wakeup
461 static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
467 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
469 struct bfin_mac_local *lp = netdev_priv(dev);
472 return phy_ethtool_gset(lp->phydev, cmd);
478 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
480 struct bfin_mac_local *lp = netdev_priv(dev);
482 if (!capable(CAP_NET_ADMIN))
486 return phy_ethtool_sset(lp->phydev, cmd);
491 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
492 struct ethtool_drvinfo *info)
494 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
495 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
496 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
497 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
500 static void bfin_mac_ethtool_getwol(struct net_device *dev,
501 struct ethtool_wolinfo *wolinfo)
503 struct bfin_mac_local *lp = netdev_priv(dev);
505 wolinfo->supported = WAKE_MAGIC;
506 wolinfo->wolopts = lp->wol;
509 static int bfin_mac_ethtool_setwol(struct net_device *dev,
510 struct ethtool_wolinfo *wolinfo)
512 struct bfin_mac_local *lp = netdev_priv(dev);
515 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
522 lp->wol = wolinfo->wolopts;
524 if (lp->wol && !lp->irq_wake_requested) {
525 /* register wake irq handler */
526 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
527 0, "EMAC_WAKE", dev);
530 lp->irq_wake_requested = true;
533 if (!lp->wol && lp->irq_wake_requested) {
534 free_irq(IRQ_MAC_WAKEDET, dev);
535 lp->irq_wake_requested = false;
538 /* Make sure the PHY driver doesn't suspend */
539 device_init_wakeup(&dev->dev, lp->wol);
544 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
545 static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
546 struct ethtool_ts_info *info)
548 struct bfin_mac_local *lp = netdev_priv(dev);
550 info->so_timestamping =
551 SOF_TIMESTAMPING_TX_HARDWARE |
552 SOF_TIMESTAMPING_RX_HARDWARE |
553 SOF_TIMESTAMPING_RAW_HARDWARE;
554 info->phc_index = lp->phc_index;
556 (1 << HWTSTAMP_TX_OFF) |
557 (1 << HWTSTAMP_TX_ON);
559 (1 << HWTSTAMP_FILTER_NONE) |
560 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
561 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
562 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
567 static const struct ethtool_ops bfin_mac_ethtool_ops = {
568 .get_settings = bfin_mac_ethtool_getsettings,
569 .set_settings = bfin_mac_ethtool_setsettings,
570 .get_link = ethtool_op_get_link,
571 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
572 .get_wol = bfin_mac_ethtool_getwol,
573 .set_wol = bfin_mac_ethtool_setwol,
574 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
575 .get_ts_info = bfin_mac_ethtool_get_ts_info,
579 /**************************************************************************/
580 static void setup_system_regs(struct net_device *dev)
582 struct bfin_mac_local *lp = netdev_priv(dev);
584 unsigned short sysctl;
587 * Odd word alignment for Receive Frame DMA word
588 * Configure checksum support and rcve frame word alignment
590 sysctl = bfin_read_EMAC_SYSCTL();
592 * check if interrupt is requested for any PHY,
593 * enable PHY interrupt only if needed
595 for (i = 0; i < PHY_MAX_ADDR; ++i)
596 if (lp->mii_bus->irq[i] != PHY_POLL)
598 if (i < PHY_MAX_ADDR)
601 #if defined(BFIN_MAC_CSUM_OFFLOAD)
606 bfin_write_EMAC_SYSCTL(sysctl);
608 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
610 /* Set vlan regs to let 1522 bytes long packets pass through */
611 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
612 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
614 /* Initialize the TX DMA channel registers */
615 bfin_write_DMA2_X_COUNT(0);
616 bfin_write_DMA2_X_MODIFY(4);
617 bfin_write_DMA2_Y_COUNT(0);
618 bfin_write_DMA2_Y_MODIFY(0);
620 /* Initialize the RX DMA channel registers */
621 bfin_write_DMA1_X_COUNT(0);
622 bfin_write_DMA1_X_MODIFY(4);
623 bfin_write_DMA1_Y_COUNT(0);
624 bfin_write_DMA1_Y_MODIFY(0);
627 static void setup_mac_addr(u8 *mac_addr)
629 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
630 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
632 /* this depends on a little-endian machine */
633 bfin_write_EMAC_ADDRLO(addr_low);
634 bfin_write_EMAC_ADDRHI(addr_hi);
637 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
639 struct sockaddr *addr = p;
640 if (netif_running(dev))
642 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
643 setup_mac_addr(dev->dev_addr);
647 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
648 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
650 static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
652 u32 ipn = 1000000000UL / input_clk;
654 unsigned int shift = 0;
660 *shift_result = shift;
661 return 1000000000UL / ppn;
664 static int bfin_mac_hwtstamp_set(struct net_device *netdev,
667 struct hwtstamp_config config;
668 struct bfin_mac_local *lp = netdev_priv(netdev);
670 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
672 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
675 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
676 __func__, config.flags, config.tx_type, config.rx_filter);
678 /* reserved for future extensions */
682 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
683 (config.tx_type != HWTSTAMP_TX_ON))
686 ptpctl = bfin_read_EMAC_PTP_CTL();
688 switch (config.rx_filter) {
689 case HWTSTAMP_FILTER_NONE:
691 * Dont allow any timestamping
694 bfin_write_EMAC_PTP_FV3(ptpfv3);
696 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
697 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
698 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
700 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
701 * to enable all the field matches.
704 bfin_write_EMAC_PTP_CTL(ptpctl);
706 * Keep the default values of the EMAC_PTP_FOFF register.
708 ptpfoff = 0x4A24170C;
709 bfin_write_EMAC_PTP_FOFF(ptpfoff);
711 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
715 bfin_write_EMAC_PTP_FV1(ptpfv1);
717 bfin_write_EMAC_PTP_FV2(ptpfv2);
719 * The default value (0xFFFC) allows the timestamping of both
720 * received Sync messages and Delay_Req messages.
723 bfin_write_EMAC_PTP_FV3(ptpfv3);
725 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
727 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
728 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
729 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
730 /* Clear all five comparison mask bits (bits[12:8]) in the
731 * EMAC_PTP_CTL register to enable all the field matches.
734 bfin_write_EMAC_PTP_CTL(ptpctl);
736 * Keep the default values of the EMAC_PTP_FOFF register, except set
737 * the PTPCOF field to 0x2A.
739 ptpfoff = 0x2A24170C;
740 bfin_write_EMAC_PTP_FOFF(ptpfoff);
742 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
746 bfin_write_EMAC_PTP_FV1(ptpfv1);
748 bfin_write_EMAC_PTP_FV2(ptpfv2);
750 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
751 * the value to 0xFFF0.
754 bfin_write_EMAC_PTP_FV3(ptpfv3);
756 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
758 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
759 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
760 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
762 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
763 * EFTM and PTPCM field comparison.
766 bfin_write_EMAC_PTP_CTL(ptpctl);
768 * Keep the default values of all the fields of the EMAC_PTP_FOFF
769 * register, except set the PTPCOF field to 0x0E.
771 ptpfoff = 0x0E24170C;
772 bfin_write_EMAC_PTP_FOFF(ptpfoff);
774 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
775 * corresponds to PTP messages on the MAC layer.
778 bfin_write_EMAC_PTP_FV1(ptpfv1);
780 bfin_write_EMAC_PTP_FV2(ptpfv2);
782 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
783 * messages, set the value to 0xFFF0.
786 bfin_write_EMAC_PTP_FV3(ptpfv3);
788 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
794 if (config.tx_type == HWTSTAMP_TX_OFF &&
795 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
797 bfin_write_EMAC_PTP_CTL(ptpctl);
802 bfin_write_EMAC_PTP_CTL(ptpctl);
805 * clear any existing timestamp
807 bfin_read_EMAC_PTP_RXSNAPLO();
808 bfin_read_EMAC_PTP_RXSNAPHI();
810 bfin_read_EMAC_PTP_TXSNAPLO();
811 bfin_read_EMAC_PTP_TXSNAPHI();
816 lp->stamp_cfg = config;
817 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
821 static int bfin_mac_hwtstamp_get(struct net_device *netdev,
824 struct bfin_mac_local *lp = netdev_priv(netdev);
826 return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
827 sizeof(lp->stamp_cfg)) ?
831 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
833 struct bfin_mac_local *lp = netdev_priv(netdev);
835 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
836 int timeout_cnt = MAX_TIMEOUT_CNT;
838 /* When doing time stamping, keep the connection to the socket
841 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
844 * The timestamping is done at the EMAC module's MII/RMII interface
845 * when the module sees the Start of Frame of an event message packet. This
846 * interface is the closest possible place to the physical Ethernet transmission
847 * medium, providing the best timing accuracy.
849 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
851 if (timeout_cnt == 0)
852 netdev_err(netdev, "timestamp the TX packet failed\n");
854 struct skb_shared_hwtstamps shhwtstamps;
858 regval = bfin_read_EMAC_PTP_TXSNAPLO();
859 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
860 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
861 ns = regval << lp->shift;
862 shhwtstamps.hwtstamp = ns_to_ktime(ns);
863 skb_tstamp_tx(skb, &shhwtstamps);
868 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
870 struct bfin_mac_local *lp = netdev_priv(netdev);
873 struct skb_shared_hwtstamps *shhwtstamps;
875 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
878 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
882 shhwtstamps = skb_hwtstamps(skb);
884 regval = bfin_read_EMAC_PTP_RXSNAPLO();
885 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
886 ns = regval << lp->shift;
887 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
888 shhwtstamps->hwtstamp = ns_to_ktime(ns);
891 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
893 struct bfin_mac_local *lp = netdev_priv(netdev);
895 u32 input_clk, phc_clk;
897 /* Initialize hardware timer */
898 input_clk = get_sclk();
899 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
900 addend = phc_clk * (1ULL << 32);
901 do_div(addend, input_clk);
902 bfin_write_EMAC_PTP_ADDEND((u32)addend);
905 ppb = 1000000000ULL * input_clk;
906 do_div(ppb, phc_clk);
907 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
909 /* Initialize hwstamp config */
910 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
911 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
914 static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
919 lo = bfin_read_EMAC_PTP_TIMELO();
920 hi = bfin_read_EMAC_PTP_TIMEHI();
922 ns = ((u64) hi) << 32;
929 static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
935 lo = ns & 0xffffffff;
937 bfin_write_EMAC_PTP_TIMELO(lo);
938 bfin_write_EMAC_PTP_TIMEHI(hi);
941 /* PTP Hardware Clock operations */
943 static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
948 struct bfin_mac_local *lp =
949 container_of(ptp, struct bfin_mac_local, caps);
958 diff = div_u64(adj, 1000000000ULL);
960 addend = neg_adj ? addend - diff : addend + diff;
962 bfin_write_EMAC_PTP_ADDEND(addend);
967 static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
971 struct bfin_mac_local *lp =
972 container_of(ptp, struct bfin_mac_local, caps);
974 spin_lock_irqsave(&lp->phc_lock, flags);
976 now = bfin_ptp_time_read(lp);
978 bfin_ptp_time_write(lp, now);
980 spin_unlock_irqrestore(&lp->phc_lock, flags);
985 static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
989 struct bfin_mac_local *lp =
990 container_of(ptp, struct bfin_mac_local, caps);
992 spin_lock_irqsave(&lp->phc_lock, flags);
994 ns = bfin_ptp_time_read(lp);
996 spin_unlock_irqrestore(&lp->phc_lock, flags);
998 *ts = ns_to_timespec64(ns);
1003 static int bfin_ptp_settime(struct ptp_clock_info *ptp,
1004 const struct timespec64 *ts)
1007 unsigned long flags;
1008 struct bfin_mac_local *lp =
1009 container_of(ptp, struct bfin_mac_local, caps);
1011 ns = timespec64_to_ns(ts);
1013 spin_lock_irqsave(&lp->phc_lock, flags);
1015 bfin_ptp_time_write(lp, ns);
1017 spin_unlock_irqrestore(&lp->phc_lock, flags);
1022 static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1023 struct ptp_clock_request *rq, int on)
1028 static struct ptp_clock_info bfin_ptp_caps = {
1029 .owner = THIS_MODULE,
1030 .name = "BF518 clock",
1037 .adjfreq = bfin_ptp_adjfreq,
1038 .adjtime = bfin_ptp_adjtime,
1039 .gettime64 = bfin_ptp_gettime,
1040 .settime64 = bfin_ptp_settime,
1041 .enable = bfin_ptp_enable,
1044 static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1046 struct bfin_mac_local *lp = netdev_priv(netdev);
1048 lp->caps = bfin_ptp_caps;
1049 lp->caps.max_adj = lp->max_ppb;
1050 lp->clock = ptp_clock_register(&lp->caps, dev);
1051 if (IS_ERR(lp->clock))
1052 return PTR_ERR(lp->clock);
1054 lp->phc_index = ptp_clock_index(lp->clock);
1055 spin_lock_init(&lp->phc_lock);
1060 static void bfin_phc_release(struct bfin_mac_local *lp)
1062 ptp_clock_unregister(lp->clock);
1066 # define bfin_mac_hwtstamp_is_none(cfg) 0
1067 # define bfin_mac_hwtstamp_init(dev)
1068 # define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
1069 # define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
1070 # define bfin_rx_hwtstamp(dev, skb)
1071 # define bfin_tx_hwtstamp(dev, skb)
1072 # define bfin_phc_init(netdev, dev) 0
1073 # define bfin_phc_release(lp)
1076 static inline void _tx_reclaim_skb(void)
1079 tx_list_head->desc_a.config &= ~DMAEN;
1080 tx_list_head->status.status_word = 0;
1081 if (tx_list_head->skb) {
1082 dev_consume_skb_any(tx_list_head->skb);
1083 tx_list_head->skb = NULL;
1085 tx_list_head = tx_list_head->next;
1087 } while (tx_list_head->status.status_word != 0);
1090 static void tx_reclaim_skb(struct bfin_mac_local *lp)
1092 int timeout_cnt = MAX_TIMEOUT_CNT;
1094 if (tx_list_head->status.status_word != 0)
1097 if (current_tx_ptr->next == tx_list_head) {
1098 while (tx_list_head->status.status_word == 0) {
1099 /* slow down polling to avoid too many queue stop. */
1101 /* reclaim skb if DMA is not running. */
1102 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1104 if (timeout_cnt-- < 0)
1108 if (timeout_cnt >= 0)
1111 netif_stop_queue(lp->ndev);
1114 if (current_tx_ptr->next != tx_list_head &&
1115 netif_queue_stopped(lp->ndev))
1116 netif_wake_queue(lp->ndev);
1118 if (tx_list_head != current_tx_ptr) {
1119 /* shorten the timer interval if tx queue is stopped */
1120 if (netif_queue_stopped(lp->ndev))
1121 lp->tx_reclaim_timer.expires =
1122 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1124 lp->tx_reclaim_timer.expires =
1125 jiffies + TX_RECLAIM_JIFFIES;
1127 mod_timer(&lp->tx_reclaim_timer,
1128 lp->tx_reclaim_timer.expires);
1134 static void tx_reclaim_skb_timeout(unsigned long lp)
1136 tx_reclaim_skb((struct bfin_mac_local *)lp);
1139 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
1140 struct net_device *dev)
1142 struct bfin_mac_local *lp = netdev_priv(dev);
1144 u32 data_align = (unsigned long)(skb->data) & 0x3;
1146 current_tx_ptr->skb = skb;
1148 if (data_align == 0x2) {
1149 /* move skb->data to current_tx_ptr payload */
1150 data = (u16 *)(skb->data) - 1;
1151 *data = (u16)(skb->len);
1153 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1154 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1155 * of this field are the length of the packet payload in bytes and the higher
1156 * 4 bits are the timestamping enable field.
1158 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1161 current_tx_ptr->desc_a.start_addr = (u32)data;
1162 /* this is important! */
1163 blackfin_dcache_flush_range((u32)data,
1164 (u32)((u8 *)data + skb->len + 4));
1166 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
1167 /* enable timestamping for the sent packet */
1168 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1169 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1170 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1172 current_tx_ptr->desc_a.start_addr =
1173 (u32)current_tx_ptr->packet;
1174 blackfin_dcache_flush_range(
1175 (u32)current_tx_ptr->packet,
1176 (u32)(current_tx_ptr->packet + skb->len + 2));
1179 /* make sure the internal data buffers in the core are drained
1180 * so that the DMA descriptors are completely written when the
1181 * DMA engine goes to fetch them below
1185 /* always clear status buffer before start tx dma */
1186 current_tx_ptr->status.status_word = 0;
1188 /* enable this packet's dma */
1189 current_tx_ptr->desc_a.config |= DMAEN;
1191 /* tx dma is running, just return */
1192 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1195 /* tx dma is not running */
1196 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1197 /* dma enabled, read from memory, size is 6 */
1198 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1199 /* Turn on the EMAC tx */
1200 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1203 bfin_tx_hwtstamp(dev, skb);
1205 current_tx_ptr = current_tx_ptr->next;
1206 dev->stats.tx_packets++;
1207 dev->stats.tx_bytes += (skb->len);
1211 return NETDEV_TX_OK;
1214 #define IP_HEADER_OFF 0
1215 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1216 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1218 static void bfin_mac_rx(struct bfin_mac_local *lp)
1220 struct net_device *dev = lp->ndev;
1221 struct sk_buff *skb, *new_skb;
1223 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1225 unsigned char fcs[ETH_FCS_LEN + 1];
1228 /* check if frame status word reports an error condition
1229 * we which case we simply drop the packet
1231 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1232 netdev_notice(dev, "rx: receive error - packet dropped\n");
1233 dev->stats.rx_dropped++;
1237 /* allocate a new skb for next time receive */
1238 skb = current_rx_ptr->skb;
1240 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1242 dev->stats.rx_dropped++;
1245 /* reserve 2 bytes for RXDWA padding */
1246 skb_reserve(new_skb, NET_IP_ALIGN);
1247 /* Invidate the data cache of skb->data range when it is write back
1248 * cache. It will prevent overwritting the new data from DMA
1250 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1251 (unsigned long)new_skb->end);
1253 current_rx_ptr->skb = new_skb;
1254 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1256 len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN);
1257 /* Deduce Ethernet FCS length from Ethernet payload length */
1261 skb->protocol = eth_type_trans(skb, dev);
1263 bfin_rx_hwtstamp(dev, skb);
1265 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1266 /* Checksum offloading only works for IPv4 packets with the standard IP header
1267 * length of 20 bytes, because the blackfin MAC checksum calculation is
1268 * based on that assumption. We must NOT use the calculated checksum if our
1269 * IP version or header break that assumption.
1271 if (skb->data[IP_HEADER_OFF] == 0x45) {
1272 skb->csum = current_rx_ptr->status.ip_payload_csum;
1274 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1275 * IP checksum is based on 16-bit one's complement algorithm.
1276 * To deduce a value from checksum is equal to add its inversion.
1277 * If the IP payload len is odd, the inversed FCS should also
1278 * begin from odd address and leave first byte zero.
1282 for (i = 0; i < ETH_FCS_LEN; i++)
1283 fcs[i + 1] = ~skb->data[skb->len + i];
1284 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1286 for (i = 0; i < ETH_FCS_LEN; i++)
1287 fcs[i] = ~skb->data[skb->len + i];
1288 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1290 skb->ip_summed = CHECKSUM_COMPLETE;
1294 napi_gro_receive(&lp->napi, skb);
1296 dev->stats.rx_packets++;
1297 dev->stats.rx_bytes += len;
1299 current_rx_ptr->status.status_word = 0x00000000;
1300 current_rx_ptr = current_rx_ptr->next;
1303 static int bfin_mac_poll(struct napi_struct *napi, int budget)
1306 struct bfin_mac_local *lp = container_of(napi,
1307 struct bfin_mac_local,
1310 while (current_rx_ptr->status.status_word != 0 && i < budget) {
1316 napi_complete(napi);
1317 if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags))
1318 enable_irq(IRQ_MAC_RX);
1324 /* interrupt routine to handle rx and error signal */
1325 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1327 struct bfin_mac_local *lp = netdev_priv(dev_id);
1330 status = bfin_read_DMA1_IRQ_STATUS();
1332 bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR);
1333 if (status & DMA_DONE) {
1334 disable_irq_nosync(IRQ_MAC_RX);
1335 set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags);
1336 napi_schedule(&lp->napi);
1342 #ifdef CONFIG_NET_POLL_CONTROLLER
1343 static void bfin_mac_poll_controller(struct net_device *dev)
1345 struct bfin_mac_local *lp = netdev_priv(dev);
1347 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1350 #endif /* CONFIG_NET_POLL_CONTROLLER */
1352 static void bfin_mac_disable(void)
1354 unsigned int opmode;
1356 opmode = bfin_read_EMAC_OPMODE();
1359 /* Turn off the EMAC */
1360 bfin_write_EMAC_OPMODE(opmode);
1364 * Enable Interrupts, Receive, and Transmit
1366 static int bfin_mac_enable(struct phy_device *phydev)
1371 pr_debug("%s\n", __func__);
1374 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1375 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1378 ret = bfin_mdio_poll();
1382 /* We enable only RX here */
1383 /* ASTP : Enable Automatic Pad Stripping
1384 PR : Promiscuous Mode for test
1385 PSF : Receive frames with total length less than 64 bytes.
1386 FDMODE : Full Duplex Mode
1387 LB : Internal Loopback for test
1388 RE : Receiver Enable */
1389 opmode = bfin_read_EMAC_OPMODE();
1390 if (opmode & FDMODE)
1393 opmode |= DRO | DC | PSF;
1396 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1397 opmode |= RMII; /* For Now only 100MBit are supported */
1398 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1399 if (__SILICON_REVISION__ < 3) {
1401 * This isn't publicly documented (fun times!), but in
1402 * silicon <=0.2, the RX and TX pins are clocked together.
1403 * So in order to recv, we must enable the transmit side
1404 * as well. This will cause a spurious TX interrupt too,
1405 * but we can easily consume that.
1412 /* Turn on the EMAC rx */
1413 bfin_write_EMAC_OPMODE(opmode);
1418 /* Our watchdog timed out. Called by the networking layer */
1419 static void bfin_mac_timeout(struct net_device *dev)
1421 struct bfin_mac_local *lp = netdev_priv(dev);
1423 pr_debug("%s: %s\n", dev->name, __func__);
1427 del_timer(&lp->tx_reclaim_timer);
1429 /* reset tx queue and free skb */
1430 while (tx_list_head != current_tx_ptr) {
1431 tx_list_head->desc_a.config &= ~DMAEN;
1432 tx_list_head->status.status_word = 0;
1433 if (tx_list_head->skb) {
1434 dev_kfree_skb(tx_list_head->skb);
1435 tx_list_head->skb = NULL;
1437 tx_list_head = tx_list_head->next;
1440 if (netif_queue_stopped(dev))
1441 netif_wake_queue(dev);
1443 bfin_mac_enable(lp->phydev);
1445 /* We can accept TX packets again */
1446 dev->trans_start = jiffies; /* prevent tx timeout */
1449 static void bfin_mac_multicast_hash(struct net_device *dev)
1451 u32 emac_hashhi, emac_hashlo;
1452 struct netdev_hw_addr *ha;
1455 emac_hashhi = emac_hashlo = 0;
1457 netdev_for_each_mc_addr(ha, dev) {
1458 crc = ether_crc(ETH_ALEN, ha->addr);
1462 emac_hashhi |= 1 << (crc & 0x1f);
1464 emac_hashlo |= 1 << (crc & 0x1f);
1467 bfin_write_EMAC_HASHHI(emac_hashhi);
1468 bfin_write_EMAC_HASHLO(emac_hashlo);
1472 * This routine will, depending on the values passed to it,
1473 * either make it accept multicast packets, go into
1474 * promiscuous mode (for TCPDUMP and cousins) or accept
1475 * a select set of multicast packets
1477 static void bfin_mac_set_multicast_list(struct net_device *dev)
1481 if (dev->flags & IFF_PROMISC) {
1482 netdev_info(dev, "set promisc mode\n");
1483 sysctl = bfin_read_EMAC_OPMODE();
1485 bfin_write_EMAC_OPMODE(sysctl);
1486 } else if (dev->flags & IFF_ALLMULTI) {
1487 /* accept all multicast */
1488 sysctl = bfin_read_EMAC_OPMODE();
1490 bfin_write_EMAC_OPMODE(sysctl);
1491 } else if (!netdev_mc_empty(dev)) {
1492 /* set up multicast hash table */
1493 sysctl = bfin_read_EMAC_OPMODE();
1495 bfin_write_EMAC_OPMODE(sysctl);
1496 bfin_mac_multicast_hash(dev);
1498 /* clear promisc or multicast mode */
1499 sysctl = bfin_read_EMAC_OPMODE();
1500 sysctl &= ~(RAF | PAM);
1501 bfin_write_EMAC_OPMODE(sysctl);
1505 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1507 struct bfin_mac_local *lp = netdev_priv(netdev);
1509 if (!netif_running(netdev))
1514 return bfin_mac_hwtstamp_set(netdev, ifr);
1516 return bfin_mac_hwtstamp_get(netdev, ifr);
1519 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1526 * this puts the device in an inactive state
1528 static void bfin_mac_shutdown(struct net_device *dev)
1530 /* Turn off the EMAC */
1531 bfin_write_EMAC_OPMODE(0x00000000);
1532 /* Turn off the EMAC RX DMA */
1533 bfin_write_DMA1_CONFIG(0x0000);
1534 bfin_write_DMA2_CONFIG(0x0000);
1538 * Open and Initialize the interface
1540 * Set up everything, reset the card, etc..
1542 static int bfin_mac_open(struct net_device *dev)
1544 struct bfin_mac_local *lp = netdev_priv(dev);
1546 pr_debug("%s: %s\n", dev->name, __func__);
1549 * Check that the address is valid. If its not, refuse
1550 * to bring the device up. The user must specify an
1551 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1553 if (!is_valid_ether_addr(dev->dev_addr)) {
1554 netdev_warn(dev, "no valid ethernet hw addr\n");
1558 /* initial rx and tx list */
1559 ret = desc_list_init(dev);
1563 phy_start(lp->phydev);
1564 setup_system_regs(dev);
1565 setup_mac_addr(dev->dev_addr);
1568 ret = bfin_mac_enable(lp->phydev);
1571 pr_debug("hardware init finished\n");
1573 napi_enable(&lp->napi);
1574 netif_start_queue(dev);
1575 netif_carrier_on(dev);
1581 * this makes the board clean up everything that it can
1582 * and not talk to the outside world. Caused by
1583 * an 'ifconfig ethX down'
1585 static int bfin_mac_close(struct net_device *dev)
1587 struct bfin_mac_local *lp = netdev_priv(dev);
1588 pr_debug("%s: %s\n", dev->name, __func__);
1590 netif_stop_queue(dev);
1591 napi_disable(&lp->napi);
1592 netif_carrier_off(dev);
1594 phy_stop(lp->phydev);
1595 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1597 /* clear everything */
1598 bfin_mac_shutdown(dev);
1600 /* free the rx/tx buffers */
1606 static const struct net_device_ops bfin_mac_netdev_ops = {
1607 .ndo_open = bfin_mac_open,
1608 .ndo_stop = bfin_mac_close,
1609 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1610 .ndo_set_mac_address = bfin_mac_set_mac_address,
1611 .ndo_tx_timeout = bfin_mac_timeout,
1612 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
1613 .ndo_do_ioctl = bfin_mac_ioctl,
1614 .ndo_validate_addr = eth_validate_addr,
1615 .ndo_change_mtu = eth_change_mtu,
1616 #ifdef CONFIG_NET_POLL_CONTROLLER
1617 .ndo_poll_controller = bfin_mac_poll_controller,
1621 static int bfin_mac_probe(struct platform_device *pdev)
1623 struct net_device *ndev;
1624 struct bfin_mac_local *lp;
1625 struct platform_device *pd;
1626 struct bfin_mii_bus_platform_data *mii_bus_data;
1629 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1633 SET_NETDEV_DEV(ndev, &pdev->dev);
1634 platform_set_drvdata(pdev, ndev);
1635 lp = netdev_priv(ndev);
1638 /* Grab the MAC address in the MAC */
1639 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1640 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1643 /*todo: how to proble? which is revision_register */
1644 bfin_write_EMAC_ADDRLO(0x12345678);
1645 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1646 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1648 goto out_err_probe_mac;
1653 * Is it valid? (Did bootloader initialize it?)
1654 * Grab the MAC from the board somehow
1655 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1657 if (!is_valid_ether_addr(ndev->dev_addr)) {
1658 if (bfin_get_ether_addr(ndev->dev_addr) ||
1659 !is_valid_ether_addr(ndev->dev_addr)) {
1660 /* Still not valid, get a random one */
1661 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1662 eth_hw_addr_random(ndev);
1666 setup_mac_addr(ndev->dev_addr);
1668 if (!dev_get_platdata(&pdev->dev)) {
1669 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1671 goto out_err_probe_mac;
1673 pd = dev_get_platdata(&pdev->dev);
1674 lp->mii_bus = platform_get_drvdata(pd);
1676 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1678 goto out_err_probe_mac;
1680 lp->mii_bus->priv = ndev;
1681 mii_bus_data = dev_get_platdata(&pd->dev);
1683 rc = mii_probe(ndev, mii_bus_data->phy_mode);
1685 dev_err(&pdev->dev, "MII Probe failed!\n");
1686 goto out_err_mii_probe;
1689 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1690 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1692 ndev->netdev_ops = &bfin_mac_netdev_ops;
1693 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1695 init_timer(&lp->tx_reclaim_timer);
1696 lp->tx_reclaim_timer.data = (unsigned long)lp;
1697 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1700 netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM);
1702 spin_lock_init(&lp->lock);
1704 /* now, enable interrupts */
1705 /* register irq handler */
1706 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1707 0, "EMAC_RX", ndev);
1709 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1711 goto out_err_request_irq;
1714 rc = register_netdev(ndev);
1716 dev_err(&pdev->dev, "Cannot register net device!\n");
1717 goto out_err_reg_ndev;
1720 bfin_mac_hwtstamp_init(ndev);
1721 rc = bfin_phc_init(ndev, &pdev->dev);
1723 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1727 /* now, print out the card info, in a short format.. */
1728 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1734 free_irq(IRQ_MAC_RX, ndev);
1735 out_err_request_irq:
1736 netif_napi_del(&lp->napi);
1738 mdiobus_unregister(lp->mii_bus);
1739 mdiobus_free(lp->mii_bus);
1746 static int bfin_mac_remove(struct platform_device *pdev)
1748 struct net_device *ndev = platform_get_drvdata(pdev);
1749 struct bfin_mac_local *lp = netdev_priv(ndev);
1751 bfin_phc_release(lp);
1753 lp->mii_bus->priv = NULL;
1755 unregister_netdev(ndev);
1757 netif_napi_del(&lp->napi);
1759 free_irq(IRQ_MAC_RX, ndev);
1767 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1769 struct net_device *net_dev = platform_get_drvdata(pdev);
1770 struct bfin_mac_local *lp = netdev_priv(net_dev);
1773 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1774 bfin_write_EMAC_WKUP_CTL(MPKE);
1775 enable_irq_wake(IRQ_MAC_WAKEDET);
1777 if (netif_running(net_dev))
1778 bfin_mac_close(net_dev);
1784 static int bfin_mac_resume(struct platform_device *pdev)
1786 struct net_device *net_dev = platform_get_drvdata(pdev);
1787 struct bfin_mac_local *lp = netdev_priv(net_dev);
1790 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1791 bfin_write_EMAC_WKUP_CTL(0);
1792 disable_irq_wake(IRQ_MAC_WAKEDET);
1794 if (netif_running(net_dev))
1795 bfin_mac_open(net_dev);
1801 #define bfin_mac_suspend NULL
1802 #define bfin_mac_resume NULL
1803 #endif /* CONFIG_PM */
1805 static int bfin_mii_bus_probe(struct platform_device *pdev)
1807 struct mii_bus *miibus;
1808 struct bfin_mii_bus_platform_data *mii_bus_pd;
1809 const unsigned short *pin_req;
1812 mii_bus_pd = dev_get_platdata(&pdev->dev);
1814 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1819 * We are setting up a network card,
1820 * so set the GPIO pins to Ethernet mode
1822 pin_req = mii_bus_pd->mac_peripherals;
1823 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
1825 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1830 miibus = mdiobus_alloc();
1833 miibus->read = bfin_mdiobus_read;
1834 miibus->write = bfin_mdiobus_write;
1836 miibus->parent = &pdev->dev;
1837 miibus->name = "bfin_mii_bus";
1838 miibus->phy_mask = mii_bus_pd->phy_mask;
1840 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1841 pdev->name, pdev->id);
1843 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1844 if (rc != mii_bus_pd->phydev_number)
1845 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1846 mii_bus_pd->phydev_number);
1847 for (i = 0; i < rc; ++i) {
1848 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1849 if (phyaddr < PHY_MAX_ADDR)
1850 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1853 "Invalid PHY address %i for phydev %i\n",
1857 rc = mdiobus_register(miibus);
1859 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1863 platform_set_drvdata(pdev, miibus);
1867 mdiobus_free(miibus);
1869 peripheral_free_list(pin_req);
1874 static int bfin_mii_bus_remove(struct platform_device *pdev)
1876 struct mii_bus *miibus = platform_get_drvdata(pdev);
1877 struct bfin_mii_bus_platform_data *mii_bus_pd =
1878 dev_get_platdata(&pdev->dev);
1880 mdiobus_unregister(miibus);
1881 mdiobus_free(miibus);
1882 peripheral_free_list(mii_bus_pd->mac_peripherals);
1887 static struct platform_driver bfin_mii_bus_driver = {
1888 .probe = bfin_mii_bus_probe,
1889 .remove = bfin_mii_bus_remove,
1891 .name = "bfin_mii_bus",
1895 static struct platform_driver bfin_mac_driver = {
1896 .probe = bfin_mac_probe,
1897 .remove = bfin_mac_remove,
1898 .resume = bfin_mac_resume,
1899 .suspend = bfin_mac_suspend,
1901 .name = KBUILD_MODNAME,
1905 static struct platform_driver * const drivers[] = {
1906 &bfin_mii_bus_driver,
1910 static int __init bfin_mac_init(void)
1912 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1915 module_init(bfin_mac_init);
1917 static void __exit bfin_mac_cleanup(void)
1919 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1922 module_exit(bfin_mac_cleanup);