2 * Blackfin On-Chip MAC Driver
4 * Copyright 2004-2010 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #define DRV_VERSION "1.1"
12 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
26 #include <linux/ioport.h>
27 #include <linux/crc32.h>
28 #include <linux/device.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
40 #include <asm/div64.h>
42 #include <asm/blackfin.h>
43 #include <asm/cacheflush.h>
44 #include <asm/portmux.h>
49 MODULE_AUTHOR("Bryan Wu, Luke Yang");
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56 # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
58 # define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
64 #define PKT_BUF_SZ 1580
66 #define MAX_TIMEOUT_CNT 500
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
78 static void desc_list_free(void)
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
83 #if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
92 dev_kfree_skb(t->skb);
98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
106 dev_kfree_skb(r->skb);
112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
116 static int desc_list_init(struct net_device *dev)
119 struct sk_buff *new_skb;
120 #if !defined(CONFIG_BFIN_MAC_USE_L1)
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
125 dma_addr_t dma_handle;
128 tx_desc = bfin_mac_alloc(&dma_handle,
129 sizeof(struct net_dma_desc_tx),
130 CONFIG_BFIN_TX_DESC_NUM);
134 rx_desc = bfin_mac_alloc(&dma_handle,
135 sizeof(struct net_dma_desc_rx),
136 CONFIG_BFIN_RX_DESC_NUM);
141 tx_list_head = tx_list_tail = tx_desc;
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
158 a->next_dma_desc = b;
162 * write to memory WNR = 1
163 * wordsize is 32 bits
165 * 6 half words is desc size
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
182 rx_list_head = rx_list_tail = rx_desc;
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
189 /* allocate a new skb for next time receive */
190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
194 skb_reserve(new_skb, NET_IP_ALIGN);
195 /* Invidate the data cache of skb->data range when it is write back
196 * cache. It will prevent overwritting the new data from DMA
198 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199 (unsigned long)new_skb->end);
204 * write to memory WNR = 1
205 * wordsize is 32 bits
207 * 6 half words is desc size
210 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211 /* since RXDWA is enabled */
212 a->start_addr = (unsigned long)new_skb->data - 2;
214 a->next_dma_desc = b;
218 * write to memory WNR = 1
219 * wordsize is 32 bits
221 * 6 half words is desc size
224 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225 NDSIZE_6 | DMAFLOW_LARGE;
226 b->start_addr = (unsigned long)(&(r->status));
229 rx_list_tail->desc_b.next_dma_desc = a;
230 rx_list_tail->next = r;
233 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
234 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235 current_rx_ptr = rx_list_head;
241 pr_err("kmalloc failed\n");
246 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
251 /* Wait until the previous MDC/MDIO transaction has completed */
252 static int bfin_mdio_poll(void)
254 int timeout_cnt = MAX_TIMEOUT_CNT;
256 /* poll the STABUSY bit */
257 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
259 if (timeout_cnt-- < 0) {
260 pr_err("wait MDC/MDIO transaction to complete timeout\n");
268 /* Read an off-chip register in a PHY through the MDC/MDIO port */
269 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
273 ret = bfin_mdio_poll();
278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
282 ret = bfin_mdio_poll();
286 return (int) bfin_read_EMAC_STADAT();
289 /* Write an off-chip register in a PHY through the MDC/MDIO port */
290 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
295 ret = bfin_mdio_poll();
299 bfin_write_EMAC_STADAT((u32) value);
302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
307 return bfin_mdio_poll();
310 static void bfin_mac_adjust_link(struct net_device *dev)
312 struct bfin_mac_local *lp = netdev_priv(dev);
313 struct phy_device *phydev = lp->phydev;
317 spin_lock_irqsave(&lp->lock, flags);
319 /* Now we make sure that we can be in full duplex mode.
320 * If not, we operate in half-duplex mode. */
321 if (phydev->duplex != lp->old_duplex) {
322 u32 opmode = bfin_read_EMAC_OPMODE();
330 bfin_write_EMAC_OPMODE(opmode);
331 lp->old_duplex = phydev->duplex;
334 if (phydev->speed != lp->old_speed) {
335 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
336 u32 opmode = bfin_read_EMAC_OPMODE();
337 switch (phydev->speed) {
346 "Ack! Speed (%d) is not 10/100!\n",
350 bfin_write_EMAC_OPMODE(opmode);
354 lp->old_speed = phydev->speed;
361 } else if (lp->old_link) {
369 u32 opmode = bfin_read_EMAC_OPMODE();
370 phy_print_status(phydev);
371 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
374 spin_unlock_irqrestore(&lp->lock, flags);
378 #define MDC_CLK 2500000
380 static int mii_probe(struct net_device *dev, int phy_mode)
382 struct bfin_mac_local *lp = netdev_priv(dev);
383 struct phy_device *phydev;
384 unsigned short sysctl;
387 /* Enable PHY output early */
388 if (!(bfin_read_VR_CTL() & CLKBUFOE))
389 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
392 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
394 sysctl = bfin_read_EMAC_SYSCTL();
395 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
396 bfin_write_EMAC_SYSCTL(sysctl);
398 phydev = phy_find_first(lp->mii_bus);
400 netdev_err(dev, "no phy device found\n");
404 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
405 phy_mode != PHY_INTERFACE_MODE_MII) {
406 netdev_err(dev, "invalid phy interface mode\n");
410 phydev = phy_connect(dev, phydev_name(phydev),
411 &bfin_mac_adjust_link, phy_mode);
413 if (IS_ERR(phydev)) {
414 netdev_err(dev, "could not attach PHY\n");
415 return PTR_ERR(phydev);
418 /* mask with MAC supported features */
419 phydev->supported &= (SUPPORTED_10baseT_Half
420 | SUPPORTED_10baseT_Full
421 | SUPPORTED_100baseT_Half
422 | SUPPORTED_100baseT_Full
424 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
428 phydev->advertising = phydev->supported;
435 phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
436 MDC_CLK, mdc_div, sclk / 1000000);
446 * interrupt routine for magic packet wakeup
448 static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
454 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
456 struct bfin_mac_local *lp = netdev_priv(dev);
459 return phy_ethtool_gset(lp->phydev, cmd);
465 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
467 struct bfin_mac_local *lp = netdev_priv(dev);
469 if (!capable(CAP_NET_ADMIN))
473 return phy_ethtool_sset(lp->phydev, cmd);
478 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
479 struct ethtool_drvinfo *info)
481 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
482 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
483 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
484 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
487 static void bfin_mac_ethtool_getwol(struct net_device *dev,
488 struct ethtool_wolinfo *wolinfo)
490 struct bfin_mac_local *lp = netdev_priv(dev);
492 wolinfo->supported = WAKE_MAGIC;
493 wolinfo->wolopts = lp->wol;
496 static int bfin_mac_ethtool_setwol(struct net_device *dev,
497 struct ethtool_wolinfo *wolinfo)
499 struct bfin_mac_local *lp = netdev_priv(dev);
502 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
509 lp->wol = wolinfo->wolopts;
511 if (lp->wol && !lp->irq_wake_requested) {
512 /* register wake irq handler */
513 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
514 0, "EMAC_WAKE", dev);
517 lp->irq_wake_requested = true;
520 if (!lp->wol && lp->irq_wake_requested) {
521 free_irq(IRQ_MAC_WAKEDET, dev);
522 lp->irq_wake_requested = false;
525 /* Make sure the PHY driver doesn't suspend */
526 device_init_wakeup(&dev->dev, lp->wol);
531 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
532 static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
533 struct ethtool_ts_info *info)
535 struct bfin_mac_local *lp = netdev_priv(dev);
537 info->so_timestamping =
538 SOF_TIMESTAMPING_TX_HARDWARE |
539 SOF_TIMESTAMPING_RX_HARDWARE |
540 SOF_TIMESTAMPING_RAW_HARDWARE;
541 info->phc_index = lp->phc_index;
543 (1 << HWTSTAMP_TX_OFF) |
544 (1 << HWTSTAMP_TX_ON);
546 (1 << HWTSTAMP_FILTER_NONE) |
547 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
548 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
549 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
554 static const struct ethtool_ops bfin_mac_ethtool_ops = {
555 .get_settings = bfin_mac_ethtool_getsettings,
556 .set_settings = bfin_mac_ethtool_setsettings,
557 .get_link = ethtool_op_get_link,
558 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
559 .get_wol = bfin_mac_ethtool_getwol,
560 .set_wol = bfin_mac_ethtool_setwol,
561 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
562 .get_ts_info = bfin_mac_ethtool_get_ts_info,
566 /**************************************************************************/
567 static void setup_system_regs(struct net_device *dev)
569 struct bfin_mac_local *lp = netdev_priv(dev);
571 unsigned short sysctl;
574 * Odd word alignment for Receive Frame DMA word
575 * Configure checksum support and rcve frame word alignment
577 sysctl = bfin_read_EMAC_SYSCTL();
579 * check if interrupt is requested for any PHY,
580 * enable PHY interrupt only if needed
582 for (i = 0; i < PHY_MAX_ADDR; ++i)
583 if (lp->mii_bus->irq[i] != PHY_POLL)
585 if (i < PHY_MAX_ADDR)
588 #if defined(BFIN_MAC_CSUM_OFFLOAD)
593 bfin_write_EMAC_SYSCTL(sysctl);
595 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
597 /* Set vlan regs to let 1522 bytes long packets pass through */
598 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
599 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
601 /* Initialize the TX DMA channel registers */
602 bfin_write_DMA2_X_COUNT(0);
603 bfin_write_DMA2_X_MODIFY(4);
604 bfin_write_DMA2_Y_COUNT(0);
605 bfin_write_DMA2_Y_MODIFY(0);
607 /* Initialize the RX DMA channel registers */
608 bfin_write_DMA1_X_COUNT(0);
609 bfin_write_DMA1_X_MODIFY(4);
610 bfin_write_DMA1_Y_COUNT(0);
611 bfin_write_DMA1_Y_MODIFY(0);
614 static void setup_mac_addr(u8 *mac_addr)
616 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
617 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
619 /* this depends on a little-endian machine */
620 bfin_write_EMAC_ADDRLO(addr_low);
621 bfin_write_EMAC_ADDRHI(addr_hi);
624 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
626 struct sockaddr *addr = p;
627 if (netif_running(dev))
629 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
630 setup_mac_addr(dev->dev_addr);
634 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
635 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
637 static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
639 u32 ipn = 1000000000UL / input_clk;
641 unsigned int shift = 0;
647 *shift_result = shift;
648 return 1000000000UL / ppn;
651 static int bfin_mac_hwtstamp_set(struct net_device *netdev,
654 struct hwtstamp_config config;
655 struct bfin_mac_local *lp = netdev_priv(netdev);
657 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
659 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
662 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
663 __func__, config.flags, config.tx_type, config.rx_filter);
665 /* reserved for future extensions */
669 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
670 (config.tx_type != HWTSTAMP_TX_ON))
673 ptpctl = bfin_read_EMAC_PTP_CTL();
675 switch (config.rx_filter) {
676 case HWTSTAMP_FILTER_NONE:
678 * Dont allow any timestamping
681 bfin_write_EMAC_PTP_FV3(ptpfv3);
683 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
684 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
685 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
687 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
688 * to enable all the field matches.
691 bfin_write_EMAC_PTP_CTL(ptpctl);
693 * Keep the default values of the EMAC_PTP_FOFF register.
695 ptpfoff = 0x4A24170C;
696 bfin_write_EMAC_PTP_FOFF(ptpfoff);
698 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
702 bfin_write_EMAC_PTP_FV1(ptpfv1);
704 bfin_write_EMAC_PTP_FV2(ptpfv2);
706 * The default value (0xFFFC) allows the timestamping of both
707 * received Sync messages and Delay_Req messages.
710 bfin_write_EMAC_PTP_FV3(ptpfv3);
712 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
714 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
715 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
716 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
717 /* Clear all five comparison mask bits (bits[12:8]) in the
718 * EMAC_PTP_CTL register to enable all the field matches.
721 bfin_write_EMAC_PTP_CTL(ptpctl);
723 * Keep the default values of the EMAC_PTP_FOFF register, except set
724 * the PTPCOF field to 0x2A.
726 ptpfoff = 0x2A24170C;
727 bfin_write_EMAC_PTP_FOFF(ptpfoff);
729 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
733 bfin_write_EMAC_PTP_FV1(ptpfv1);
735 bfin_write_EMAC_PTP_FV2(ptpfv2);
737 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
738 * the value to 0xFFF0.
741 bfin_write_EMAC_PTP_FV3(ptpfv3);
743 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
745 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
746 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
747 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
749 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
750 * EFTM and PTPCM field comparison.
753 bfin_write_EMAC_PTP_CTL(ptpctl);
755 * Keep the default values of all the fields of the EMAC_PTP_FOFF
756 * register, except set the PTPCOF field to 0x0E.
758 ptpfoff = 0x0E24170C;
759 bfin_write_EMAC_PTP_FOFF(ptpfoff);
761 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
762 * corresponds to PTP messages on the MAC layer.
765 bfin_write_EMAC_PTP_FV1(ptpfv1);
767 bfin_write_EMAC_PTP_FV2(ptpfv2);
769 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
770 * messages, set the value to 0xFFF0.
773 bfin_write_EMAC_PTP_FV3(ptpfv3);
775 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
781 if (config.tx_type == HWTSTAMP_TX_OFF &&
782 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
784 bfin_write_EMAC_PTP_CTL(ptpctl);
789 bfin_write_EMAC_PTP_CTL(ptpctl);
792 * clear any existing timestamp
794 bfin_read_EMAC_PTP_RXSNAPLO();
795 bfin_read_EMAC_PTP_RXSNAPHI();
797 bfin_read_EMAC_PTP_TXSNAPLO();
798 bfin_read_EMAC_PTP_TXSNAPHI();
803 lp->stamp_cfg = config;
804 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
808 static int bfin_mac_hwtstamp_get(struct net_device *netdev,
811 struct bfin_mac_local *lp = netdev_priv(netdev);
813 return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
814 sizeof(lp->stamp_cfg)) ?
818 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
820 struct bfin_mac_local *lp = netdev_priv(netdev);
822 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
823 int timeout_cnt = MAX_TIMEOUT_CNT;
825 /* When doing time stamping, keep the connection to the socket
828 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
831 * The timestamping is done at the EMAC module's MII/RMII interface
832 * when the module sees the Start of Frame of an event message packet. This
833 * interface is the closest possible place to the physical Ethernet transmission
834 * medium, providing the best timing accuracy.
836 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
838 if (timeout_cnt == 0)
839 netdev_err(netdev, "timestamp the TX packet failed\n");
841 struct skb_shared_hwtstamps shhwtstamps;
845 regval = bfin_read_EMAC_PTP_TXSNAPLO();
846 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
847 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
848 ns = regval << lp->shift;
849 shhwtstamps.hwtstamp = ns_to_ktime(ns);
850 skb_tstamp_tx(skb, &shhwtstamps);
855 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
857 struct bfin_mac_local *lp = netdev_priv(netdev);
860 struct skb_shared_hwtstamps *shhwtstamps;
862 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
865 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
869 shhwtstamps = skb_hwtstamps(skb);
871 regval = bfin_read_EMAC_PTP_RXSNAPLO();
872 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
873 ns = regval << lp->shift;
874 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
875 shhwtstamps->hwtstamp = ns_to_ktime(ns);
878 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
880 struct bfin_mac_local *lp = netdev_priv(netdev);
882 u32 input_clk, phc_clk;
884 /* Initialize hardware timer */
885 input_clk = get_sclk();
886 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
887 addend = phc_clk * (1ULL << 32);
888 do_div(addend, input_clk);
889 bfin_write_EMAC_PTP_ADDEND((u32)addend);
892 ppb = 1000000000ULL * input_clk;
893 do_div(ppb, phc_clk);
894 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
896 /* Initialize hwstamp config */
897 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
898 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
901 static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
906 lo = bfin_read_EMAC_PTP_TIMELO();
907 hi = bfin_read_EMAC_PTP_TIMEHI();
909 ns = ((u64) hi) << 32;
916 static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
922 lo = ns & 0xffffffff;
924 bfin_write_EMAC_PTP_TIMELO(lo);
925 bfin_write_EMAC_PTP_TIMEHI(hi);
928 /* PTP Hardware Clock operations */
930 static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
935 struct bfin_mac_local *lp =
936 container_of(ptp, struct bfin_mac_local, caps);
945 diff = div_u64(adj, 1000000000ULL);
947 addend = neg_adj ? addend - diff : addend + diff;
949 bfin_write_EMAC_PTP_ADDEND(addend);
954 static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
958 struct bfin_mac_local *lp =
959 container_of(ptp, struct bfin_mac_local, caps);
961 spin_lock_irqsave(&lp->phc_lock, flags);
963 now = bfin_ptp_time_read(lp);
965 bfin_ptp_time_write(lp, now);
967 spin_unlock_irqrestore(&lp->phc_lock, flags);
972 static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
976 struct bfin_mac_local *lp =
977 container_of(ptp, struct bfin_mac_local, caps);
979 spin_lock_irqsave(&lp->phc_lock, flags);
981 ns = bfin_ptp_time_read(lp);
983 spin_unlock_irqrestore(&lp->phc_lock, flags);
985 *ts = ns_to_timespec64(ns);
990 static int bfin_ptp_settime(struct ptp_clock_info *ptp,
991 const struct timespec64 *ts)
995 struct bfin_mac_local *lp =
996 container_of(ptp, struct bfin_mac_local, caps);
998 ns = timespec64_to_ns(ts);
1000 spin_lock_irqsave(&lp->phc_lock, flags);
1002 bfin_ptp_time_write(lp, ns);
1004 spin_unlock_irqrestore(&lp->phc_lock, flags);
1009 static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1010 struct ptp_clock_request *rq, int on)
1015 static struct ptp_clock_info bfin_ptp_caps = {
1016 .owner = THIS_MODULE,
1017 .name = "BF518 clock",
1024 .adjfreq = bfin_ptp_adjfreq,
1025 .adjtime = bfin_ptp_adjtime,
1026 .gettime64 = bfin_ptp_gettime,
1027 .settime64 = bfin_ptp_settime,
1028 .enable = bfin_ptp_enable,
1031 static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1033 struct bfin_mac_local *lp = netdev_priv(netdev);
1035 lp->caps = bfin_ptp_caps;
1036 lp->caps.max_adj = lp->max_ppb;
1037 lp->clock = ptp_clock_register(&lp->caps, dev);
1038 if (IS_ERR(lp->clock))
1039 return PTR_ERR(lp->clock);
1041 lp->phc_index = ptp_clock_index(lp->clock);
1042 spin_lock_init(&lp->phc_lock);
1047 static void bfin_phc_release(struct bfin_mac_local *lp)
1049 ptp_clock_unregister(lp->clock);
1053 # define bfin_mac_hwtstamp_is_none(cfg) 0
1054 # define bfin_mac_hwtstamp_init(dev)
1055 # define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
1056 # define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
1057 # define bfin_rx_hwtstamp(dev, skb)
1058 # define bfin_tx_hwtstamp(dev, skb)
1059 # define bfin_phc_init(netdev, dev) 0
1060 # define bfin_phc_release(lp)
1063 static inline void _tx_reclaim_skb(void)
1066 tx_list_head->desc_a.config &= ~DMAEN;
1067 tx_list_head->status.status_word = 0;
1068 if (tx_list_head->skb) {
1069 dev_consume_skb_any(tx_list_head->skb);
1070 tx_list_head->skb = NULL;
1072 tx_list_head = tx_list_head->next;
1074 } while (tx_list_head->status.status_word != 0);
1077 static void tx_reclaim_skb(struct bfin_mac_local *lp)
1079 int timeout_cnt = MAX_TIMEOUT_CNT;
1081 if (tx_list_head->status.status_word != 0)
1084 if (current_tx_ptr->next == tx_list_head) {
1085 while (tx_list_head->status.status_word == 0) {
1086 /* slow down polling to avoid too many queue stop. */
1088 /* reclaim skb if DMA is not running. */
1089 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1091 if (timeout_cnt-- < 0)
1095 if (timeout_cnt >= 0)
1098 netif_stop_queue(lp->ndev);
1101 if (current_tx_ptr->next != tx_list_head &&
1102 netif_queue_stopped(lp->ndev))
1103 netif_wake_queue(lp->ndev);
1105 if (tx_list_head != current_tx_ptr) {
1106 /* shorten the timer interval if tx queue is stopped */
1107 if (netif_queue_stopped(lp->ndev))
1108 lp->tx_reclaim_timer.expires =
1109 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1111 lp->tx_reclaim_timer.expires =
1112 jiffies + TX_RECLAIM_JIFFIES;
1114 mod_timer(&lp->tx_reclaim_timer,
1115 lp->tx_reclaim_timer.expires);
1121 static void tx_reclaim_skb_timeout(unsigned long lp)
1123 tx_reclaim_skb((struct bfin_mac_local *)lp);
1126 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
1127 struct net_device *dev)
1129 struct bfin_mac_local *lp = netdev_priv(dev);
1131 u32 data_align = (unsigned long)(skb->data) & 0x3;
1133 current_tx_ptr->skb = skb;
1135 if (data_align == 0x2) {
1136 /* move skb->data to current_tx_ptr payload */
1137 data = (u16 *)(skb->data) - 1;
1138 *data = (u16)(skb->len);
1140 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1141 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1142 * of this field are the length of the packet payload in bytes and the higher
1143 * 4 bits are the timestamping enable field.
1145 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1148 current_tx_ptr->desc_a.start_addr = (u32)data;
1149 /* this is important! */
1150 blackfin_dcache_flush_range((u32)data,
1151 (u32)((u8 *)data + skb->len + 4));
1153 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
1154 /* enable timestamping for the sent packet */
1155 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1156 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1157 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1159 current_tx_ptr->desc_a.start_addr =
1160 (u32)current_tx_ptr->packet;
1161 blackfin_dcache_flush_range(
1162 (u32)current_tx_ptr->packet,
1163 (u32)(current_tx_ptr->packet + skb->len + 2));
1166 /* make sure the internal data buffers in the core are drained
1167 * so that the DMA descriptors are completely written when the
1168 * DMA engine goes to fetch them below
1172 /* always clear status buffer before start tx dma */
1173 current_tx_ptr->status.status_word = 0;
1175 /* enable this packet's dma */
1176 current_tx_ptr->desc_a.config |= DMAEN;
1178 /* tx dma is running, just return */
1179 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1182 /* tx dma is not running */
1183 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1184 /* dma enabled, read from memory, size is 6 */
1185 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1186 /* Turn on the EMAC tx */
1187 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1190 bfin_tx_hwtstamp(dev, skb);
1192 current_tx_ptr = current_tx_ptr->next;
1193 dev->stats.tx_packets++;
1194 dev->stats.tx_bytes += (skb->len);
1198 return NETDEV_TX_OK;
1201 #define IP_HEADER_OFF 0
1202 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1203 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1205 static void bfin_mac_rx(struct bfin_mac_local *lp)
1207 struct net_device *dev = lp->ndev;
1208 struct sk_buff *skb, *new_skb;
1210 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1212 unsigned char fcs[ETH_FCS_LEN + 1];
1215 /* check if frame status word reports an error condition
1216 * we which case we simply drop the packet
1218 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1219 netdev_notice(dev, "rx: receive error - packet dropped\n");
1220 dev->stats.rx_dropped++;
1224 /* allocate a new skb for next time receive */
1225 skb = current_rx_ptr->skb;
1227 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1229 dev->stats.rx_dropped++;
1232 /* reserve 2 bytes for RXDWA padding */
1233 skb_reserve(new_skb, NET_IP_ALIGN);
1234 /* Invidate the data cache of skb->data range when it is write back
1235 * cache. It will prevent overwritting the new data from DMA
1237 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1238 (unsigned long)new_skb->end);
1240 current_rx_ptr->skb = new_skb;
1241 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1243 len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN);
1244 /* Deduce Ethernet FCS length from Ethernet payload length */
1248 skb->protocol = eth_type_trans(skb, dev);
1250 bfin_rx_hwtstamp(dev, skb);
1252 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1253 /* Checksum offloading only works for IPv4 packets with the standard IP header
1254 * length of 20 bytes, because the blackfin MAC checksum calculation is
1255 * based on that assumption. We must NOT use the calculated checksum if our
1256 * IP version or header break that assumption.
1258 if (skb->data[IP_HEADER_OFF] == 0x45) {
1259 skb->csum = current_rx_ptr->status.ip_payload_csum;
1261 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1262 * IP checksum is based on 16-bit one's complement algorithm.
1263 * To deduce a value from checksum is equal to add its inversion.
1264 * If the IP payload len is odd, the inversed FCS should also
1265 * begin from odd address and leave first byte zero.
1269 for (i = 0; i < ETH_FCS_LEN; i++)
1270 fcs[i + 1] = ~skb->data[skb->len + i];
1271 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1273 for (i = 0; i < ETH_FCS_LEN; i++)
1274 fcs[i] = ~skb->data[skb->len + i];
1275 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1277 skb->ip_summed = CHECKSUM_COMPLETE;
1281 napi_gro_receive(&lp->napi, skb);
1283 dev->stats.rx_packets++;
1284 dev->stats.rx_bytes += len;
1286 current_rx_ptr->status.status_word = 0x00000000;
1287 current_rx_ptr = current_rx_ptr->next;
1290 static int bfin_mac_poll(struct napi_struct *napi, int budget)
1293 struct bfin_mac_local *lp = container_of(napi,
1294 struct bfin_mac_local,
1297 while (current_rx_ptr->status.status_word != 0 && i < budget) {
1303 napi_complete(napi);
1304 if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags))
1305 enable_irq(IRQ_MAC_RX);
1311 /* interrupt routine to handle rx and error signal */
1312 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1314 struct bfin_mac_local *lp = netdev_priv(dev_id);
1317 status = bfin_read_DMA1_IRQ_STATUS();
1319 bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR);
1320 if (status & DMA_DONE) {
1321 disable_irq_nosync(IRQ_MAC_RX);
1322 set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags);
1323 napi_schedule(&lp->napi);
1329 #ifdef CONFIG_NET_POLL_CONTROLLER
1330 static void bfin_mac_poll_controller(struct net_device *dev)
1332 struct bfin_mac_local *lp = netdev_priv(dev);
1334 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1337 #endif /* CONFIG_NET_POLL_CONTROLLER */
1339 static void bfin_mac_disable(void)
1341 unsigned int opmode;
1343 opmode = bfin_read_EMAC_OPMODE();
1346 /* Turn off the EMAC */
1347 bfin_write_EMAC_OPMODE(opmode);
1351 * Enable Interrupts, Receive, and Transmit
1353 static int bfin_mac_enable(struct phy_device *phydev)
1358 pr_debug("%s\n", __func__);
1361 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1362 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1365 ret = bfin_mdio_poll();
1369 /* We enable only RX here */
1370 /* ASTP : Enable Automatic Pad Stripping
1371 PR : Promiscuous Mode for test
1372 PSF : Receive frames with total length less than 64 bytes.
1373 FDMODE : Full Duplex Mode
1374 LB : Internal Loopback for test
1375 RE : Receiver Enable */
1376 opmode = bfin_read_EMAC_OPMODE();
1377 if (opmode & FDMODE)
1380 opmode |= DRO | DC | PSF;
1383 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1384 opmode |= RMII; /* For Now only 100MBit are supported */
1385 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1386 if (__SILICON_REVISION__ < 3) {
1388 * This isn't publicly documented (fun times!), but in
1389 * silicon <=0.2, the RX and TX pins are clocked together.
1390 * So in order to recv, we must enable the transmit side
1391 * as well. This will cause a spurious TX interrupt too,
1392 * but we can easily consume that.
1399 /* Turn on the EMAC rx */
1400 bfin_write_EMAC_OPMODE(opmode);
1405 /* Our watchdog timed out. Called by the networking layer */
1406 static void bfin_mac_timeout(struct net_device *dev)
1408 struct bfin_mac_local *lp = netdev_priv(dev);
1410 pr_debug("%s: %s\n", dev->name, __func__);
1414 del_timer(&lp->tx_reclaim_timer);
1416 /* reset tx queue and free skb */
1417 while (tx_list_head != current_tx_ptr) {
1418 tx_list_head->desc_a.config &= ~DMAEN;
1419 tx_list_head->status.status_word = 0;
1420 if (tx_list_head->skb) {
1421 dev_kfree_skb(tx_list_head->skb);
1422 tx_list_head->skb = NULL;
1424 tx_list_head = tx_list_head->next;
1427 if (netif_queue_stopped(dev))
1428 netif_wake_queue(dev);
1430 bfin_mac_enable(lp->phydev);
1432 /* We can accept TX packets again */
1433 dev->trans_start = jiffies; /* prevent tx timeout */
1436 static void bfin_mac_multicast_hash(struct net_device *dev)
1438 u32 emac_hashhi, emac_hashlo;
1439 struct netdev_hw_addr *ha;
1442 emac_hashhi = emac_hashlo = 0;
1444 netdev_for_each_mc_addr(ha, dev) {
1445 crc = ether_crc(ETH_ALEN, ha->addr);
1449 emac_hashhi |= 1 << (crc & 0x1f);
1451 emac_hashlo |= 1 << (crc & 0x1f);
1454 bfin_write_EMAC_HASHHI(emac_hashhi);
1455 bfin_write_EMAC_HASHLO(emac_hashlo);
1459 * This routine will, depending on the values passed to it,
1460 * either make it accept multicast packets, go into
1461 * promiscuous mode (for TCPDUMP and cousins) or accept
1462 * a select set of multicast packets
1464 static void bfin_mac_set_multicast_list(struct net_device *dev)
1468 if (dev->flags & IFF_PROMISC) {
1469 netdev_info(dev, "set promisc mode\n");
1470 sysctl = bfin_read_EMAC_OPMODE();
1472 bfin_write_EMAC_OPMODE(sysctl);
1473 } else if (dev->flags & IFF_ALLMULTI) {
1474 /* accept all multicast */
1475 sysctl = bfin_read_EMAC_OPMODE();
1477 bfin_write_EMAC_OPMODE(sysctl);
1478 } else if (!netdev_mc_empty(dev)) {
1479 /* set up multicast hash table */
1480 sysctl = bfin_read_EMAC_OPMODE();
1482 bfin_write_EMAC_OPMODE(sysctl);
1483 bfin_mac_multicast_hash(dev);
1485 /* clear promisc or multicast mode */
1486 sysctl = bfin_read_EMAC_OPMODE();
1487 sysctl &= ~(RAF | PAM);
1488 bfin_write_EMAC_OPMODE(sysctl);
1492 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1494 struct bfin_mac_local *lp = netdev_priv(netdev);
1496 if (!netif_running(netdev))
1501 return bfin_mac_hwtstamp_set(netdev, ifr);
1503 return bfin_mac_hwtstamp_get(netdev, ifr);
1506 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1513 * this puts the device in an inactive state
1515 static void bfin_mac_shutdown(struct net_device *dev)
1517 /* Turn off the EMAC */
1518 bfin_write_EMAC_OPMODE(0x00000000);
1519 /* Turn off the EMAC RX DMA */
1520 bfin_write_DMA1_CONFIG(0x0000);
1521 bfin_write_DMA2_CONFIG(0x0000);
1525 * Open and Initialize the interface
1527 * Set up everything, reset the card, etc..
1529 static int bfin_mac_open(struct net_device *dev)
1531 struct bfin_mac_local *lp = netdev_priv(dev);
1533 pr_debug("%s: %s\n", dev->name, __func__);
1536 * Check that the address is valid. If its not, refuse
1537 * to bring the device up. The user must specify an
1538 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1540 if (!is_valid_ether_addr(dev->dev_addr)) {
1541 netdev_warn(dev, "no valid ethernet hw addr\n");
1545 /* initial rx and tx list */
1546 ret = desc_list_init(dev);
1550 phy_start(lp->phydev);
1551 setup_system_regs(dev);
1552 setup_mac_addr(dev->dev_addr);
1555 ret = bfin_mac_enable(lp->phydev);
1558 pr_debug("hardware init finished\n");
1560 napi_enable(&lp->napi);
1561 netif_start_queue(dev);
1562 netif_carrier_on(dev);
1568 * this makes the board clean up everything that it can
1569 * and not talk to the outside world. Caused by
1570 * an 'ifconfig ethX down'
1572 static int bfin_mac_close(struct net_device *dev)
1574 struct bfin_mac_local *lp = netdev_priv(dev);
1575 pr_debug("%s: %s\n", dev->name, __func__);
1577 netif_stop_queue(dev);
1578 napi_disable(&lp->napi);
1579 netif_carrier_off(dev);
1581 phy_stop(lp->phydev);
1582 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1584 /* clear everything */
1585 bfin_mac_shutdown(dev);
1587 /* free the rx/tx buffers */
1593 static const struct net_device_ops bfin_mac_netdev_ops = {
1594 .ndo_open = bfin_mac_open,
1595 .ndo_stop = bfin_mac_close,
1596 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1597 .ndo_set_mac_address = bfin_mac_set_mac_address,
1598 .ndo_tx_timeout = bfin_mac_timeout,
1599 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
1600 .ndo_do_ioctl = bfin_mac_ioctl,
1601 .ndo_validate_addr = eth_validate_addr,
1602 .ndo_change_mtu = eth_change_mtu,
1603 #ifdef CONFIG_NET_POLL_CONTROLLER
1604 .ndo_poll_controller = bfin_mac_poll_controller,
1608 static int bfin_mac_probe(struct platform_device *pdev)
1610 struct net_device *ndev;
1611 struct bfin_mac_local *lp;
1612 struct platform_device *pd;
1613 struct bfin_mii_bus_platform_data *mii_bus_data;
1616 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1620 SET_NETDEV_DEV(ndev, &pdev->dev);
1621 platform_set_drvdata(pdev, ndev);
1622 lp = netdev_priv(ndev);
1625 /* Grab the MAC address in the MAC */
1626 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1627 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1630 /*todo: how to proble? which is revision_register */
1631 bfin_write_EMAC_ADDRLO(0x12345678);
1632 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1633 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1635 goto out_err_probe_mac;
1640 * Is it valid? (Did bootloader initialize it?)
1641 * Grab the MAC from the board somehow
1642 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1644 if (!is_valid_ether_addr(ndev->dev_addr)) {
1645 if (bfin_get_ether_addr(ndev->dev_addr) ||
1646 !is_valid_ether_addr(ndev->dev_addr)) {
1647 /* Still not valid, get a random one */
1648 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1649 eth_hw_addr_random(ndev);
1653 setup_mac_addr(ndev->dev_addr);
1655 if (!dev_get_platdata(&pdev->dev)) {
1656 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1658 goto out_err_probe_mac;
1660 pd = dev_get_platdata(&pdev->dev);
1661 lp->mii_bus = platform_get_drvdata(pd);
1663 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1665 goto out_err_probe_mac;
1667 lp->mii_bus->priv = ndev;
1668 mii_bus_data = dev_get_platdata(&pd->dev);
1670 rc = mii_probe(ndev, mii_bus_data->phy_mode);
1672 dev_err(&pdev->dev, "MII Probe failed!\n");
1673 goto out_err_mii_probe;
1676 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1677 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1679 ndev->netdev_ops = &bfin_mac_netdev_ops;
1680 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1682 init_timer(&lp->tx_reclaim_timer);
1683 lp->tx_reclaim_timer.data = (unsigned long)lp;
1684 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1687 netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM);
1689 spin_lock_init(&lp->lock);
1691 /* now, enable interrupts */
1692 /* register irq handler */
1693 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1694 0, "EMAC_RX", ndev);
1696 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1698 goto out_err_request_irq;
1701 rc = register_netdev(ndev);
1703 dev_err(&pdev->dev, "Cannot register net device!\n");
1704 goto out_err_reg_ndev;
1707 bfin_mac_hwtstamp_init(ndev);
1708 rc = bfin_phc_init(ndev, &pdev->dev);
1710 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1714 /* now, print out the card info, in a short format.. */
1715 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1721 free_irq(IRQ_MAC_RX, ndev);
1722 out_err_request_irq:
1723 netif_napi_del(&lp->napi);
1725 mdiobus_unregister(lp->mii_bus);
1726 mdiobus_free(lp->mii_bus);
1733 static int bfin_mac_remove(struct platform_device *pdev)
1735 struct net_device *ndev = platform_get_drvdata(pdev);
1736 struct bfin_mac_local *lp = netdev_priv(ndev);
1738 bfin_phc_release(lp);
1740 lp->mii_bus->priv = NULL;
1742 unregister_netdev(ndev);
1744 netif_napi_del(&lp->napi);
1746 free_irq(IRQ_MAC_RX, ndev);
1754 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1756 struct net_device *net_dev = platform_get_drvdata(pdev);
1757 struct bfin_mac_local *lp = netdev_priv(net_dev);
1760 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1761 bfin_write_EMAC_WKUP_CTL(MPKE);
1762 enable_irq_wake(IRQ_MAC_WAKEDET);
1764 if (netif_running(net_dev))
1765 bfin_mac_close(net_dev);
1771 static int bfin_mac_resume(struct platform_device *pdev)
1773 struct net_device *net_dev = platform_get_drvdata(pdev);
1774 struct bfin_mac_local *lp = netdev_priv(net_dev);
1777 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1778 bfin_write_EMAC_WKUP_CTL(0);
1779 disable_irq_wake(IRQ_MAC_WAKEDET);
1781 if (netif_running(net_dev))
1782 bfin_mac_open(net_dev);
1788 #define bfin_mac_suspend NULL
1789 #define bfin_mac_resume NULL
1790 #endif /* CONFIG_PM */
1792 static int bfin_mii_bus_probe(struct platform_device *pdev)
1794 struct mii_bus *miibus;
1795 struct bfin_mii_bus_platform_data *mii_bus_pd;
1796 const unsigned short *pin_req;
1799 mii_bus_pd = dev_get_platdata(&pdev->dev);
1801 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1806 * We are setting up a network card,
1807 * so set the GPIO pins to Ethernet mode
1809 pin_req = mii_bus_pd->mac_peripherals;
1810 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
1812 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1817 miibus = mdiobus_alloc();
1820 miibus->read = bfin_mdiobus_read;
1821 miibus->write = bfin_mdiobus_write;
1823 miibus->parent = &pdev->dev;
1824 miibus->name = "bfin_mii_bus";
1825 miibus->phy_mask = mii_bus_pd->phy_mask;
1827 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1828 pdev->name, pdev->id);
1830 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1831 if (rc != mii_bus_pd->phydev_number)
1832 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1833 mii_bus_pd->phydev_number);
1834 for (i = 0; i < rc; ++i) {
1835 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1836 if (phyaddr < PHY_MAX_ADDR)
1837 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1840 "Invalid PHY address %i for phydev %i\n",
1844 rc = mdiobus_register(miibus);
1846 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1847 goto out_err_irq_alloc;
1850 platform_set_drvdata(pdev, miibus);
1854 mdiobus_free(miibus);
1856 peripheral_free_list(pin_req);
1861 static int bfin_mii_bus_remove(struct platform_device *pdev)
1863 struct mii_bus *miibus = platform_get_drvdata(pdev);
1864 struct bfin_mii_bus_platform_data *mii_bus_pd =
1865 dev_get_platdata(&pdev->dev);
1867 mdiobus_unregister(miibus);
1868 mdiobus_free(miibus);
1869 peripheral_free_list(mii_bus_pd->mac_peripherals);
1874 static struct platform_driver bfin_mii_bus_driver = {
1875 .probe = bfin_mii_bus_probe,
1876 .remove = bfin_mii_bus_remove,
1878 .name = "bfin_mii_bus",
1882 static struct platform_driver bfin_mac_driver = {
1883 .probe = bfin_mac_probe,
1884 .remove = bfin_mac_remove,
1885 .resume = bfin_mac_resume,
1886 .suspend = bfin_mac_suspend,
1888 .name = KBUILD_MODNAME,
1892 static struct platform_driver * const drivers[] = {
1893 &bfin_mii_bus_driver,
1897 static int __init bfin_mac_init(void)
1899 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1902 module_init(bfin_mac_init);
1904 static void __exit bfin_mac_cleanup(void)
1906 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1909 module_exit(bfin_mac_cleanup);