2 * Allwinner EMAC Fast Ethernet driver for Linux.
4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
7 * Based on the Linux driver provided by Allwinner:
8 * Copyright (C) 1997 Sten Wang
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/clk.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/gpio.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/mii.h>
22 #include <linux/module.h>
23 #include <linux/netdevice.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
32 #include "sun4i-emac.h"
34 #define DRV_NAME "sun4i-emac"
35 #define DRV_VERSION "1.02"
37 #define EMAC_MAX_FRAME_LEN 0x0600
39 /* Transmit timeout, default 5 seconds. */
40 static int watchdog = 5000;
41 module_param(watchdog, int, 0400);
42 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
44 /* EMAC register address locking.
46 * The EMAC uses an address register to control where data written
47 * to the data register goes. This means that the address register
48 * must be preserved over interrupts or similar calls.
50 * During interrupt and other critical calls, a spinlock is used to
51 * protect the system, but the calls themselves save the address
52 * in the address register in case they are interrupting another
53 * access to the device.
55 * For general accesses a lock is provided so that calls which are
56 * allowed to sleep are serialised so that the address register does
57 * not need to be saved. This lock also serves to serialise access
58 * to the EEPROM and PHY access registers which are shared between
62 /* The driver supports the original EMACE, and now the two newer
63 * devices, EMACA and EMACB.
66 struct emac_board_info {
69 struct platform_device *pdev;
71 void __iomem *membase;
73 struct net_device *ndev;
74 struct sk_buff *skb_last;
77 int emacrx_completed_flag;
79 struct phy_device *phy_dev;
80 struct device_node *phy_node;
85 phy_interface_t phy_interface;
88 static void emac_update_speed(struct net_device *dev)
90 struct emac_board_info *db = netdev_priv(dev);
93 /* set EMAC SPEED, depend on PHY */
94 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
95 reg_val &= ~(0x1 << 8);
96 if (db->speed == SPEED_100)
98 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
101 static void emac_update_duplex(struct net_device *dev)
103 struct emac_board_info *db = netdev_priv(dev);
104 unsigned int reg_val;
106 /* set duplex depend on phy */
107 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
108 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
110 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
111 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
114 static void emac_handle_link_change(struct net_device *dev)
116 struct emac_board_info *db = netdev_priv(dev);
117 struct phy_device *phydev = db->phy_dev;
119 int status_change = 0;
122 if (db->speed != phydev->speed) {
123 spin_lock_irqsave(&db->lock, flags);
124 db->speed = phydev->speed;
125 emac_update_speed(dev);
126 spin_unlock_irqrestore(&db->lock, flags);
130 if (db->duplex != phydev->duplex) {
131 spin_lock_irqsave(&db->lock, flags);
132 db->duplex = phydev->duplex;
133 emac_update_duplex(dev);
134 spin_unlock_irqrestore(&db->lock, flags);
139 if (phydev->link != db->link) {
144 db->link = phydev->link;
150 phy_print_status(phydev);
153 static int emac_mdio_probe(struct net_device *dev)
155 struct emac_board_info *db = netdev_priv(dev);
157 /* to-do: PHY interrupts are currently not supported */
159 /* attach the mac to the phy */
160 db->phy_dev = of_phy_connect(db->ndev, db->phy_node,
161 &emac_handle_link_change, 0,
164 netdev_err(db->ndev, "could not find the PHY\n");
168 /* mask with MAC supported features */
169 db->phy_dev->supported &= PHY_BASIC_FEATURES;
170 db->phy_dev->advertising = db->phy_dev->supported;
179 static void emac_mdio_remove(struct net_device *dev)
181 struct emac_board_info *db = netdev_priv(dev);
183 phy_disconnect(db->phy_dev);
187 static void emac_reset(struct emac_board_info *db)
189 dev_dbg(db->dev, "resetting device\n");
192 writel(0, db->membase + EMAC_CTL_REG);
194 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
198 static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
200 writesl(reg, data, round_up(count, 4) / 4);
203 static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
205 readsl(reg, data, round_up(count, 4) / 4);
208 static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
210 struct emac_board_info *dm = netdev_priv(dev);
211 struct phy_device *phydev = dm->phy_dev;
213 if (!netif_running(dev))
219 return phy_mii_ioctl(phydev, rq, cmd);
223 static void emac_get_drvinfo(struct net_device *dev,
224 struct ethtool_drvinfo *info)
226 strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME));
227 strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION));
228 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
231 static int emac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
233 struct emac_board_info *dm = netdev_priv(dev);
234 struct phy_device *phydev = dm->phy_dev;
239 return phy_ethtool_gset(phydev, cmd);
242 static int emac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
244 struct emac_board_info *dm = netdev_priv(dev);
245 struct phy_device *phydev = dm->phy_dev;
250 return phy_ethtool_sset(phydev, cmd);
253 static const struct ethtool_ops emac_ethtool_ops = {
254 .get_drvinfo = emac_get_drvinfo,
255 .get_settings = emac_get_settings,
256 .set_settings = emac_set_settings,
257 .get_link = ethtool_op_get_link,
260 static unsigned int emac_setup(struct net_device *ndev)
262 struct emac_board_info *db = netdev_priv(ndev);
263 unsigned int reg_val;
266 reg_val = readl(db->membase + EMAC_TX_MODE_REG);
268 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
269 db->membase + EMAC_TX_MODE_REG);
272 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
274 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
275 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
276 EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
277 EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
278 db->membase + EMAC_RX_CTL_REG);
282 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
283 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
284 EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
285 db->membase + EMAC_MAC_CTL0_REG);
288 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
289 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
290 reg_val |= EMAC_MAC_CTL1_CRC_EN;
291 reg_val |= EMAC_MAC_CTL1_PAD_EN;
292 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
295 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
298 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
299 db->membase + EMAC_MAC_IPGR_REG);
301 /* set up Collison window */
302 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
303 db->membase + EMAC_MAC_CLRT_REG);
305 /* set up Max Frame Length */
306 writel(EMAC_MAX_FRAME_LEN,
307 db->membase + EMAC_MAC_MAXF_REG);
312 static unsigned int emac_powerup(struct net_device *ndev)
314 struct emac_board_info *db = netdev_priv(ndev);
315 unsigned int reg_val;
319 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
321 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
326 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
327 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
328 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
331 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
332 reg_val &= (~(0xf << 2));
333 reg_val |= (0xD << 2);
334 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
336 /* clear RX counter */
337 writel(0x0, db->membase + EMAC_RX_FBC_REG);
339 /* disable all interrupt and clear interrupt status */
340 writel(0, db->membase + EMAC_INT_CTL_REG);
341 reg_val = readl(db->membase + EMAC_INT_STA_REG);
342 writel(reg_val, db->membase + EMAC_INT_STA_REG);
349 /* set mac_address to chip */
350 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
351 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
352 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
353 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
360 static int emac_set_mac_address(struct net_device *dev, void *p)
362 struct sockaddr *addr = p;
363 struct emac_board_info *db = netdev_priv(dev);
365 if (netif_running(dev))
368 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
370 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
371 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
372 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
373 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
378 /* Initialize emac board */
379 static void emac_init_device(struct net_device *dev)
381 struct emac_board_info *db = netdev_priv(dev);
383 unsigned int reg_val;
385 spin_lock_irqsave(&db->lock, flags);
387 emac_update_speed(dev);
388 emac_update_duplex(dev);
391 reg_val = readl(db->membase + EMAC_CTL_REG);
392 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
393 db->membase + EMAC_CTL_REG);
395 /* enable RX/TX0/RX Hlevel interrup */
396 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
397 reg_val |= (0xf << 0) | (0x01 << 8);
398 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
400 spin_unlock_irqrestore(&db->lock, flags);
403 /* Our watchdog timed out. Called by the networking layer */
404 static void emac_timeout(struct net_device *dev)
406 struct emac_board_info *db = netdev_priv(dev);
409 if (netif_msg_timer(db))
410 dev_err(db->dev, "tx time out.\n");
412 /* Save previous register address */
413 spin_lock_irqsave(&db->lock, flags);
415 netif_stop_queue(dev);
417 emac_init_device(dev);
418 /* We can accept TX packets again */
419 dev->trans_start = jiffies;
420 netif_wake_queue(dev);
422 /* Restore previous register address */
423 spin_unlock_irqrestore(&db->lock, flags);
426 /* Hardware start transmission.
427 * Send a packet to media from the upper layer.
429 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
431 struct emac_board_info *db = netdev_priv(dev);
432 unsigned long channel;
435 channel = db->tx_fifo_stat & 3;
439 channel = (channel == 1 ? 1 : 0);
441 spin_lock_irqsave(&db->lock, flags);
443 writel(channel, db->membase + EMAC_TX_INS_REG);
445 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
446 skb->data, skb->len);
447 dev->stats.tx_bytes += skb->len;
449 db->tx_fifo_stat |= 1 << channel;
450 /* TX control: First packet immediately send, second packet queue */
453 writel(skb->len, db->membase + EMAC_TX_PL0_REG);
454 /* start translate from fifo to phy */
455 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
456 db->membase + EMAC_TX_CTL0_REG);
458 /* save the time stamp */
459 dev->trans_start = jiffies;
460 } else if (channel == 1) {
462 writel(skb->len, db->membase + EMAC_TX_PL1_REG);
463 /* start translate from fifo to phy */
464 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
465 db->membase + EMAC_TX_CTL1_REG);
467 /* save the time stamp */
468 dev->trans_start = jiffies;
471 if ((db->tx_fifo_stat & 3) == 3) {
473 netif_stop_queue(dev);
476 spin_unlock_irqrestore(&db->lock, flags);
484 /* EMAC interrupt handler
485 * receive the packet to upper layer, free the transmitted packet
487 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
488 unsigned int tx_status)
490 /* One packet sent complete */
491 db->tx_fifo_stat &= ~(tx_status & 3);
492 if (3 == (tx_status & 3))
493 dev->stats.tx_packets += 2;
495 dev->stats.tx_packets++;
497 if (netif_msg_tx_done(db))
498 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
500 netif_wake_queue(dev);
503 /* Received a packet and pass to upper layer
505 static void emac_rx(struct net_device *dev)
507 struct emac_board_info *db = netdev_priv(dev);
511 static int rxlen_last;
512 unsigned int reg_val;
513 u32 rxhdr, rxstatus, rxcount, rxlen;
515 /* Check packet ready or not */
517 /* race warning: the first packet might arrive with
518 * the interrupts disabled, but the second will fix
521 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
523 if (netif_msg_rx_status(db))
524 dev_dbg(db->dev, "RXCount: %x\n", rxcount);
526 if ((db->skb_last != NULL) && (rxlen_last > 0)) {
527 dev->stats.rx_bytes += rxlen_last;
529 /* Pass to upper layer */
530 db->skb_last->protocol = eth_type_trans(db->skb_last,
532 netif_rx(db->skb_last);
533 dev->stats.rx_packets++;
537 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
538 reg_val &= ~EMAC_RX_CTL_DMA_EN;
539 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
543 db->emacrx_completed_flag = 1;
544 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
545 reg_val |= (0xf << 0) | (0x01 << 8);
546 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
549 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
554 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
555 if (netif_msg_rx_status(db))
556 dev_dbg(db->dev, "receive header: %x\n", reg_val);
557 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
559 reg_val = readl(db->membase + EMAC_CTL_REG);
560 writel(reg_val & ~EMAC_CTL_RX_EN,
561 db->membase + EMAC_CTL_REG);
564 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
565 writel(reg_val | (1 << 3),
566 db->membase + EMAC_RX_CTL_REG);
569 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
570 } while (reg_val & (1 << 3));
573 reg_val = readl(db->membase + EMAC_CTL_REG);
574 writel(reg_val | EMAC_CTL_RX_EN,
575 db->membase + EMAC_CTL_REG);
576 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
577 reg_val |= (0xf << 0) | (0x01 << 8);
578 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
580 db->emacrx_completed_flag = 1;
585 /* A packet ready now & Get status/length */
588 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
589 &rxhdr, sizeof(rxhdr));
591 if (netif_msg_rx_status(db))
592 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
594 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
595 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
597 if (netif_msg_rx_status(db))
598 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
601 /* Packet Status check */
604 if (netif_msg_rx_err(db))
605 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
608 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
611 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
612 if (netif_msg_rx_err(db))
613 dev_dbg(db->dev, "crc error\n");
614 dev->stats.rx_crc_errors++;
617 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
618 if (netif_msg_rx_err(db))
619 dev_dbg(db->dev, "length error\n");
620 dev->stats.rx_length_errors++;
624 /* Move data from EMAC */
625 skb = dev_alloc_skb(rxlen + 4);
626 if (good_packet && skb) {
628 rdptr = (u8 *) skb_put(skb, rxlen - 4);
630 /* Read received packet from RX SRAM */
631 if (netif_msg_rx_status(db))
632 dev_dbg(db->dev, "RxLen %x\n", rxlen);
634 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
636 dev->stats.rx_bytes += rxlen;
638 /* Pass to upper layer */
639 skb->protocol = eth_type_trans(skb, dev);
641 dev->stats.rx_packets++;
646 static irqreturn_t emac_interrupt(int irq, void *dev_id)
648 struct net_device *dev = dev_id;
649 struct emac_board_info *db = netdev_priv(dev);
652 unsigned int reg_val;
654 /* A real interrupt coming */
656 /* holders of db->lock must always block IRQs */
657 spin_lock_irqsave(&db->lock, flags);
659 /* Disable all interrupts */
660 writel(0, db->membase + EMAC_INT_CTL_REG);
662 /* Got EMAC interrupt status */
664 int_status = readl(db->membase + EMAC_INT_STA_REG);
665 /* Clear ISR status */
666 writel(int_status, db->membase + EMAC_INT_STA_REG);
668 if (netif_msg_intr(db))
669 dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
671 /* Received the coming packet */
672 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
674 db->emacrx_completed_flag = 0;
678 /* Transmit Interrupt check */
679 if (int_status & (0x01 | 0x02))
680 emac_tx_done(dev, db, int_status);
682 if (int_status & (0x04 | 0x08))
683 netdev_info(dev, " ab : %x\n", int_status);
685 /* Re-enable interrupt mask */
686 if (db->emacrx_completed_flag == 1) {
687 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
688 reg_val |= (0xf << 0) | (0x01 << 8);
689 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
691 spin_unlock_irqrestore(&db->lock, flags);
696 #ifdef CONFIG_NET_POLL_CONTROLLER
700 static void emac_poll_controller(struct net_device *dev)
702 disable_irq(dev->irq);
703 emac_interrupt(dev->irq, dev);
704 enable_irq(dev->irq);
708 /* Open the interface.
709 * The interface is opened whenever "ifconfig" actives it.
711 static int emac_open(struct net_device *dev)
713 struct emac_board_info *db = netdev_priv(dev);
716 if (netif_msg_ifup(db))
717 dev_dbg(db->dev, "enabling %s\n", dev->name);
719 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev))
722 /* Initialize EMAC board */
724 emac_init_device(dev);
726 ret = emac_mdio_probe(dev);
728 netdev_err(dev, "cannot probe MDIO bus\n");
732 phy_start(db->phy_dev);
733 netif_start_queue(dev);
738 static void emac_shutdown(struct net_device *dev)
740 unsigned int reg_val;
741 struct emac_board_info *db = netdev_priv(dev);
743 /* Disable all interrupt */
744 writel(0, db->membase + EMAC_INT_CTL_REG);
746 /* clear interupt status */
747 reg_val = readl(db->membase + EMAC_INT_STA_REG);
748 writel(reg_val, db->membase + EMAC_INT_STA_REG);
751 reg_val = readl(db->membase + EMAC_CTL_REG);
752 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
753 writel(reg_val, db->membase + EMAC_CTL_REG);
756 /* Stop the interface.
757 * The interface is stopped when it is brought.
759 static int emac_stop(struct net_device *ndev)
761 struct emac_board_info *db = netdev_priv(ndev);
763 if (netif_msg_ifdown(db))
764 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
766 netif_stop_queue(ndev);
767 netif_carrier_off(ndev);
769 phy_stop(db->phy_dev);
771 emac_mdio_remove(ndev);
775 free_irq(ndev->irq, ndev);
780 static const struct net_device_ops emac_netdev_ops = {
781 .ndo_open = emac_open,
782 .ndo_stop = emac_stop,
783 .ndo_start_xmit = emac_start_xmit,
784 .ndo_tx_timeout = emac_timeout,
785 .ndo_do_ioctl = emac_ioctl,
786 .ndo_change_mtu = eth_change_mtu,
787 .ndo_validate_addr = eth_validate_addr,
788 .ndo_set_mac_address = emac_set_mac_address,
789 #ifdef CONFIG_NET_POLL_CONTROLLER
790 .ndo_poll_controller = emac_poll_controller,
794 /* Search EMAC board, allocate space and register it
796 static int emac_probe(struct platform_device *pdev)
798 struct device_node *np = pdev->dev.of_node;
799 struct emac_board_info *db;
800 struct net_device *ndev;
802 const char *mac_addr;
804 ndev = alloc_etherdev(sizeof(struct emac_board_info));
806 dev_err(&pdev->dev, "could not allocate device.\n");
810 SET_NETDEV_DEV(ndev, &pdev->dev);
812 db = netdev_priv(ndev);
813 memset(db, 0, sizeof(*db));
815 db->dev = &pdev->dev;
819 spin_lock_init(&db->lock);
821 db->membase = of_iomap(np, 0);
823 dev_err(&pdev->dev, "failed to remap registers\n");
828 /* fill in parameters for net-dev structure */
829 ndev->base_addr = (unsigned long)db->membase;
830 ndev->irq = irq_of_parse_and_map(np, 0);
831 if (ndev->irq == -ENXIO) {
832 netdev_err(ndev, "No irq resource\n");
837 db->clk = devm_clk_get(&pdev->dev, NULL);
841 clk_prepare_enable(db->clk);
843 db->phy_node = of_parse_phandle(np, "phy", 0);
845 dev_err(&pdev->dev, "no associated PHY\n");
850 /* Read MAC-address from DT */
851 mac_addr = of_get_mac_address(np);
853 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
855 /* Check if the MAC address is valid, if not get a random one */
856 if (!is_valid_ether_addr(ndev->dev_addr)) {
857 eth_hw_addr_random(ndev);
858 dev_warn(&pdev->dev, "using random MAC address %pM\n",
862 db->emacrx_completed_flag = 1;
868 ndev->netdev_ops = &emac_netdev_ops;
869 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
870 ndev->ethtool_ops = &emac_ethtool_ops;
872 platform_set_drvdata(pdev, ndev);
874 /* Carrier starts down, phylib will bring it up */
875 netif_carrier_off(ndev);
877 ret = register_netdev(ndev);
879 dev_err(&pdev->dev, "Registering netdev failed!\n");
884 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
885 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
890 dev_err(db->dev, "not found (%d).\n", ret);
897 static int emac_remove(struct platform_device *pdev)
899 struct net_device *ndev = platform_get_drvdata(pdev);
901 unregister_netdev(ndev);
904 dev_dbg(&pdev->dev, "released and freed device\n");
908 static int emac_suspend(struct platform_device *dev, pm_message_t state)
910 struct net_device *ndev = platform_get_drvdata(dev);
912 netif_carrier_off(ndev);
913 netif_device_detach(ndev);
919 static int emac_resume(struct platform_device *dev)
921 struct net_device *ndev = platform_get_drvdata(dev);
922 struct emac_board_info *db = netdev_priv(ndev);
925 emac_init_device(ndev);
926 netif_device_attach(ndev);
931 static const struct of_device_id emac_of_match[] = {
932 {.compatible = "allwinner,sun4i-a10-emac",},
935 {.compatible = "allwinner,sun4i-emac",},
939 MODULE_DEVICE_TABLE(of, emac_of_match);
941 static struct platform_driver emac_driver = {
943 .name = "sun4i-emac",
944 .of_match_table = emac_of_match,
947 .remove = emac_remove,
948 .suspend = emac_suspend,
949 .resume = emac_resume,
952 module_platform_driver(emac_driver);
954 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
955 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
956 MODULE_DESCRIPTION("Allwinner A10 emac network driver");
957 MODULE_LICENSE("GPL");