1 /* Altera TSE SGDMA and MSGDMA Linux driver
2 * Copyright (C) 2014 Altera Corporation. All rights reserved
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/netdevice.h>
18 #include "altera_utils.h"
19 #include "altera_tse.h"
20 #include "altera_msgdmahw.h"
21 #include "altera_msgdma.h"
23 /* No initialization work to do for MSGDMA */
24 int msgdma_initialize(struct altera_tse_private *priv)
29 void msgdma_uninitialize(struct altera_tse_private *priv)
33 void msgdma_start_rxdma(struct altera_tse_private *priv)
37 void msgdma_reset(struct altera_tse_private *priv)
40 struct msgdma_csr *txcsr =
41 (struct msgdma_csr *)priv->tx_dma_csr;
42 struct msgdma_csr *rxcsr =
43 (struct msgdma_csr *)priv->rx_dma_csr;
46 iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);
47 iowrite32(MSGDMA_CSR_CTL_RESET, &rxcsr->control);
50 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
51 if (tse_bit_is_clear(&rxcsr->status,
52 MSGDMA_CSR_STAT_RESETTING))
57 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
58 netif_warn(priv, drv, priv->dev,
59 "TSE Rx mSGDMA resetting bit never cleared!\n");
61 /* clear all status bits */
62 iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);
65 iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);
66 iowrite32(MSGDMA_CSR_CTL_RESET, &txcsr->control);
69 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
70 if (tse_bit_is_clear(&txcsr->status,
71 MSGDMA_CSR_STAT_RESETTING))
76 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
77 netif_warn(priv, drv, priv->dev,
78 "TSE Tx mSGDMA resetting bit never cleared!\n");
80 /* clear all status bits */
81 iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);
84 void msgdma_disable_rxirq(struct altera_tse_private *priv)
86 struct msgdma_csr *csr = priv->rx_dma_csr;
87 tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
90 void msgdma_enable_rxirq(struct altera_tse_private *priv)
92 struct msgdma_csr *csr = priv->rx_dma_csr;
93 tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
96 void msgdma_disable_txirq(struct altera_tse_private *priv)
98 struct msgdma_csr *csr = priv->tx_dma_csr;
99 tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
102 void msgdma_enable_txirq(struct altera_tse_private *priv)
104 struct msgdma_csr *csr = priv->tx_dma_csr;
105 tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
108 void msgdma_clear_rxirq(struct altera_tse_private *priv)
110 struct msgdma_csr *csr = priv->rx_dma_csr;
111 iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
114 void msgdma_clear_txirq(struct altera_tse_private *priv)
116 struct msgdma_csr *csr = priv->tx_dma_csr;
117 iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
120 /* return 0 to indicate transmit is pending */
121 int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
123 struct msgdma_extended_desc *desc = priv->tx_dma_desc;
125 iowrite32(lower_32_bits(buffer->dma_addr), &desc->read_addr_lo);
126 iowrite32(upper_32_bits(buffer->dma_addr), &desc->read_addr_hi);
127 iowrite32(0, &desc->write_addr_lo);
128 iowrite32(0, &desc->write_addr_hi);
129 iowrite32(buffer->len, &desc->len);
130 iowrite32(0, &desc->burst_seq_num);
131 iowrite32(MSGDMA_DESC_TX_STRIDE, &desc->stride);
132 iowrite32(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
136 u32 msgdma_tx_completions(struct altera_tse_private *priv)
141 struct msgdma_csr *txcsr =
142 (struct msgdma_csr *)priv->tx_dma_csr;
144 /* Get number of sent descriptors */
145 inuse = ioread32(&txcsr->rw_fill_level) & 0xffff;
147 if (inuse) { /* Tx FIFO is not empty */
148 ready = priv->tx_prod - priv->tx_cons - inuse - 1;
150 /* Check for buffered last packet */
151 status = ioread32(&txcsr->status);
152 if (status & MSGDMA_CSR_STAT_BUSY)
153 ready = priv->tx_prod - priv->tx_cons - 1;
155 ready = priv->tx_prod - priv->tx_cons;
160 /* Put buffer to the mSGDMA RX FIFO
162 void msgdma_add_rx_desc(struct altera_tse_private *priv,
163 struct tse_buffer *rxbuffer)
165 struct msgdma_extended_desc *desc = priv->rx_dma_desc;
166 u32 len = priv->rx_dma_buf_sz;
167 dma_addr_t dma_addr = rxbuffer->dma_addr;
168 u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
169 | MSGDMA_DESC_CTL_END_ON_LEN
170 | MSGDMA_DESC_CTL_TR_COMP_IRQ
171 | MSGDMA_DESC_CTL_EARLY_IRQ
172 | MSGDMA_DESC_CTL_TR_ERR_IRQ
173 | MSGDMA_DESC_CTL_GO);
175 iowrite32(0, &desc->read_addr_lo);
176 iowrite32(0, &desc->read_addr_hi);
177 iowrite32(lower_32_bits(dma_addr), &desc->write_addr_lo);
178 iowrite32(upper_32_bits(dma_addr), &desc->write_addr_hi);
179 iowrite32(len, &desc->len);
180 iowrite32(0, &desc->burst_seq_num);
181 iowrite32(0x00010001, &desc->stride);
182 iowrite32(control, &desc->control);
185 /* status is returned on upper 16 bits,
186 * length is returned in lower 16 bits
188 u32 msgdma_rx_status(struct altera_tse_private *priv)
193 struct msgdma_csr *rxcsr =
194 (struct msgdma_csr *)priv->rx_dma_csr;
195 struct msgdma_response *rxresp =
196 (struct msgdma_response *)priv->rx_dma_resp;
198 if (ioread32(&rxcsr->resp_fill_level) & 0xffff) {
199 pktlength = ioread32(&rxresp->bytes_transferred);
200 pktstatus = ioread32(&rxresp->status);
201 rxstatus = pktstatus;
202 rxstatus = rxstatus << 16;
203 rxstatus |= (pktlength & 0xffff);