1 /* Altera TSE SGDMA and MSGDMA Linux driver
2 * Copyright (C) 2014 Altera Corporation. All rights reserved
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/list.h>
18 #include "altera_utils.h"
19 #include "altera_tse.h"
20 #include "altera_sgdmahw.h"
21 #include "altera_sgdma.h"
23 static void sgdma_setup_descrip(struct sgdma_descrip *desc,
24 struct sgdma_descrip *ndesc,
25 dma_addr_t ndesc_phys,
33 static int sgdma_async_write(struct altera_tse_private *priv,
34 struct sgdma_descrip *desc);
36 static int sgdma_async_read(struct altera_tse_private *priv);
39 sgdma_txphysaddr(struct altera_tse_private *priv,
40 struct sgdma_descrip *desc);
43 sgdma_rxphysaddr(struct altera_tse_private *priv,
44 struct sgdma_descrip *desc);
46 static int sgdma_txbusy(struct altera_tse_private *priv);
48 static int sgdma_rxbusy(struct altera_tse_private *priv);
51 queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer);
54 queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer);
56 static struct tse_buffer *
57 dequeue_tx(struct altera_tse_private *priv);
59 static struct tse_buffer *
60 dequeue_rx(struct altera_tse_private *priv);
62 static struct tse_buffer *
63 queue_rx_peekhead(struct altera_tse_private *priv);
65 int sgdma_initialize(struct altera_tse_private *priv)
67 priv->txctrlreg = SGDMA_CTRLREG_ILASTD |
70 priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP |
74 priv->sgdmadesclen = sizeof(struct sgdma_descrip);
76 INIT_LIST_HEAD(&priv->txlisthd);
77 INIT_LIST_HEAD(&priv->rxlisthd);
79 priv->rxdescphys = (dma_addr_t) 0;
80 priv->txdescphys = (dma_addr_t) 0;
82 priv->rxdescphys = dma_map_single(priv->device, priv->rx_dma_desc,
83 priv->rxdescmem, DMA_BIDIRECTIONAL);
85 if (dma_mapping_error(priv->device, priv->rxdescphys)) {
86 sgdma_uninitialize(priv);
87 netdev_err(priv->dev, "error mapping rx descriptor memory\n");
91 priv->txdescphys = dma_map_single(priv->device, priv->tx_dma_desc,
92 priv->txdescmem, DMA_TO_DEVICE);
94 if (dma_mapping_error(priv->device, priv->txdescphys)) {
95 sgdma_uninitialize(priv);
96 netdev_err(priv->dev, "error mapping tx descriptor memory\n");
100 /* Initialize descriptor memory to all 0's, sync memory to cache */
101 memset(priv->tx_dma_desc, 0, priv->txdescmem);
102 memset(priv->rx_dma_desc, 0, priv->rxdescmem);
104 dma_sync_single_for_device(priv->device, priv->txdescphys,
105 priv->txdescmem, DMA_TO_DEVICE);
107 dma_sync_single_for_device(priv->device, priv->rxdescphys,
108 priv->rxdescmem, DMA_TO_DEVICE);
113 void sgdma_uninitialize(struct altera_tse_private *priv)
115 if (priv->rxdescphys)
116 dma_unmap_single(priv->device, priv->rxdescphys,
117 priv->rxdescmem, DMA_BIDIRECTIONAL);
119 if (priv->txdescphys)
120 dma_unmap_single(priv->device, priv->txdescphys,
121 priv->txdescmem, DMA_TO_DEVICE);
124 /* This function resets the SGDMA controller and clears the
125 * descriptor memory used for transmits and receives.
127 void sgdma_reset(struct altera_tse_private *priv)
129 u32 *ptxdescripmem = (u32 *)priv->tx_dma_desc;
130 u32 txdescriplen = priv->txdescmem;
131 u32 *prxdescripmem = (u32 *)priv->rx_dma_desc;
132 u32 rxdescriplen = priv->rxdescmem;
133 struct sgdma_csr *ptxsgdma = (struct sgdma_csr *)priv->tx_dma_csr;
134 struct sgdma_csr *prxsgdma = (struct sgdma_csr *)priv->rx_dma_csr;
136 /* Initialize descriptor memory to 0 */
137 memset(ptxdescripmem, 0, txdescriplen);
138 memset(prxdescripmem, 0, rxdescriplen);
140 iowrite32(SGDMA_CTRLREG_RESET, &ptxsgdma->control);
141 iowrite32(0, &ptxsgdma->control);
143 iowrite32(SGDMA_CTRLREG_RESET, &prxsgdma->control);
144 iowrite32(0, &prxsgdma->control);
147 /* For SGDMA, interrupts remain enabled after initially enabling,
148 * so no need to provide implementations for abstract enable
152 void sgdma_enable_rxirq(struct altera_tse_private *priv)
156 void sgdma_enable_txirq(struct altera_tse_private *priv)
160 void sgdma_disable_rxirq(struct altera_tse_private *priv)
164 void sgdma_disable_txirq(struct altera_tse_private *priv)
168 void sgdma_clear_rxirq(struct altera_tse_private *priv)
170 struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
171 tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT);
174 void sgdma_clear_txirq(struct altera_tse_private *priv)
176 struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
177 tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT);
180 /* transmits buffer through SGDMA. Returns number of buffers
181 * transmitted, 0 if not possible.
183 * tx_lock is held by the caller
185 int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
188 struct sgdma_descrip *descbase =
189 (struct sgdma_descrip *)priv->tx_dma_desc;
191 struct sgdma_descrip *cdesc = &descbase[0];
192 struct sgdma_descrip *ndesc = &descbase[1];
194 /* wait 'til the tx sgdma is ready for the next transmit request */
195 if (sgdma_txbusy(priv))
198 sgdma_setup_descrip(cdesc, /* current descriptor */
199 ndesc, /* next descriptor */
200 sgdma_txphysaddr(priv, ndesc),
201 buffer->dma_addr, /* address of packet to xmit */
202 0, /* write addr 0 for tx dma */
203 buffer->len, /* length of packet */
204 SGDMA_CONTROL_EOP, /* Generate EOP */
206 SGDMA_CONTROL_WR_FIXED); /* Generate SOP */
208 pktstx = sgdma_async_write(priv, cdesc);
210 /* enqueue the request to the pending transmit queue */
211 queue_tx(priv, buffer);
217 /* tx_lock held to protect access to queued tx list
219 u32 sgdma_tx_completions(struct altera_tse_private *priv)
222 struct sgdma_descrip *desc = (struct sgdma_descrip *)priv->tx_dma_desc;
224 if (!sgdma_txbusy(priv) &&
225 ((desc->control & SGDMA_CONTROL_HW_OWNED) == 0) &&
226 (dequeue_tx(priv))) {
233 void sgdma_start_rxdma(struct altera_tse_private *priv)
235 sgdma_async_read(priv);
238 void sgdma_add_rx_desc(struct altera_tse_private *priv,
239 struct tse_buffer *rxbuffer)
241 queue_rx(priv, rxbuffer);
244 /* status is returned on upper 16 bits,
245 * length is returned in lower 16 bits
247 u32 sgdma_rx_status(struct altera_tse_private *priv)
249 struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
250 struct sgdma_descrip *base = (struct sgdma_descrip *)priv->rx_dma_desc;
251 struct sgdma_descrip *desc = NULL;
253 unsigned int rxstatus = 0;
254 unsigned int pktlength = 0;
255 unsigned int pktstatus = 0;
256 struct tse_buffer *rxbuffer = NULL;
258 u32 sts = ioread32(&csr->status);
261 if (sts & SGDMA_STSREG_EOP) {
262 dma_sync_single_for_cpu(priv->device,
267 pktlength = desc->bytes_xferred;
268 pktstatus = desc->status & 0x3f;
269 rxstatus = pktstatus;
270 rxstatus = rxstatus << 16;
271 rxstatus |= (pktlength & 0xffff);
276 rxbuffer = dequeue_rx(priv);
277 if (rxbuffer == NULL)
278 netdev_info(priv->dev,
279 "sgdma rx and rx queue empty!\n");
282 iowrite32(0, &csr->control);
284 iowrite32(0xf, &csr->status);
286 /* kick the rx sgdma after reaping this descriptor */
287 pktsrx = sgdma_async_read(priv);
290 /* If the SGDMA indicated an end of packet on recv,
291 * then it's expected that the rxstatus from the
292 * descriptor is non-zero - meaning a valid packet
293 * with a nonzero length, or an error has been
294 * indicated. if not, then all we can do is signal
295 * an error and return no packet received. Most likely
296 * there is a system design error, or an error in the
297 * underlying kernel (cache or cache management problem)
299 netdev_err(priv->dev,
300 "SGDMA RX Error Info: %x, %x, %x\n",
301 sts, desc->status, rxstatus);
303 } else if (sts == 0) {
304 pktsrx = sgdma_async_read(priv);
311 /* Private functions */
312 static void sgdma_setup_descrip(struct sgdma_descrip *desc,
313 struct sgdma_descrip *ndesc,
314 dma_addr_t ndesc_phys,
322 /* Clear the next descriptor as not owned by hardware */
323 u32 ctrl = ndesc->control;
324 ctrl &= ~SGDMA_CONTROL_HW_OWNED;
325 ndesc->control = ctrl;
328 ctrl = SGDMA_CONTROL_HW_OWNED;
329 ctrl |= generate_eop;
333 /* Channel is implicitly zero, initialized to 0 by default */
337 desc->next = lower_32_bits(ndesc_phys);
338 desc->control = ctrl;
342 desc->bytes = length;
343 desc->bytes_xferred = 0;
346 /* If hardware is busy, don't restart async read.
347 * if status register is 0 - meaning initial state, restart async read,
348 * probably for the first time when populating a receive buffer.
349 * If read status indicate not busy and a status, restart the async
352 static int sgdma_async_read(struct altera_tse_private *priv)
354 struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
355 struct sgdma_descrip *descbase =
356 (struct sgdma_descrip *)priv->rx_dma_desc;
358 struct sgdma_descrip *cdesc = &descbase[0];
359 struct sgdma_descrip *ndesc = &descbase[1];
361 struct tse_buffer *rxbuffer = NULL;
363 if (!sgdma_rxbusy(priv)) {
364 rxbuffer = queue_rx_peekhead(priv);
365 if (rxbuffer == NULL) {
366 netdev_err(priv->dev, "no rx buffers available\n");
370 sgdma_setup_descrip(cdesc, /* current descriptor */
371 ndesc, /* next descriptor */
372 sgdma_rxphysaddr(priv, ndesc),
373 0, /* read addr 0 for rx dma */
374 rxbuffer->dma_addr, /* write addr for rx dma */
375 0, /* read 'til EOP */
376 0, /* EOP: NA for rx dma */
377 0, /* read fixed: NA for rx dma */
378 0); /* SOP: NA for rx DMA */
380 dma_sync_single_for_device(priv->device,
385 iowrite32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
388 iowrite32((priv->rxctrlreg | SGDMA_CTRLREG_START),
397 static int sgdma_async_write(struct altera_tse_private *priv,
398 struct sgdma_descrip *desc)
400 struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
402 if (sgdma_txbusy(priv))
405 /* clear control and status */
406 iowrite32(0, &csr->control);
407 iowrite32(0x1f, &csr->status);
409 dma_sync_single_for_device(priv->device, priv->txdescphys,
410 priv->sgdmadesclen, DMA_TO_DEVICE);
412 iowrite32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
415 iowrite32((priv->txctrlreg | SGDMA_CTRLREG_START),
422 sgdma_txphysaddr(struct altera_tse_private *priv,
423 struct sgdma_descrip *desc)
425 dma_addr_t paddr = priv->txdescmem_busaddr;
426 uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->tx_dma_desc;
427 return (dma_addr_t)((uintptr_t)paddr + offs);
431 sgdma_rxphysaddr(struct altera_tse_private *priv,
432 struct sgdma_descrip *desc)
434 dma_addr_t paddr = priv->rxdescmem_busaddr;
435 uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->rx_dma_desc;
436 return (dma_addr_t)((uintptr_t)paddr + offs);
439 #define list_remove_head(list, entry, type, member) \
442 if (!list_empty(list)) { \
443 entry = list_entry((list)->next, type, member); \
444 list_del_init(&entry->member); \
448 #define list_peek_head(list, entry, type, member) \
451 if (!list_empty(list)) { \
452 entry = list_entry((list)->next, type, member); \
456 /* adds a tse_buffer to the tail of a tx buffer list.
457 * assumes the caller is managing and holding a mutual exclusion
458 * primitive to avoid simultaneous pushes/pops to the list.
461 queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer)
463 list_add_tail(&buffer->lh, &priv->txlisthd);
467 /* adds a tse_buffer to the tail of a rx buffer list
468 * assumes the caller is managing and holding a mutual exclusion
469 * primitive to avoid simultaneous pushes/pops to the list.
472 queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer)
474 list_add_tail(&buffer->lh, &priv->rxlisthd);
477 /* dequeues a tse_buffer from the transmit buffer list, otherwise
478 * returns NULL if empty.
479 * assumes the caller is managing and holding a mutual exclusion
480 * primitive to avoid simultaneous pushes/pops to the list.
482 static struct tse_buffer *
483 dequeue_tx(struct altera_tse_private *priv)
485 struct tse_buffer *buffer = NULL;
486 list_remove_head(&priv->txlisthd, buffer, struct tse_buffer, lh);
490 /* dequeues a tse_buffer from the receive buffer list, otherwise
491 * returns NULL if empty
492 * assumes the caller is managing and holding a mutual exclusion
493 * primitive to avoid simultaneous pushes/pops to the list.
495 static struct tse_buffer *
496 dequeue_rx(struct altera_tse_private *priv)
498 struct tse_buffer *buffer = NULL;
499 list_remove_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
503 /* dequeues a tse_buffer from the receive buffer list, otherwise
504 * returns NULL if empty
505 * assumes the caller is managing and holding a mutual exclusion
506 * primitive to avoid simultaneous pushes/pops to the list while the
507 * head is being examined.
509 static struct tse_buffer *
510 queue_rx_peekhead(struct altera_tse_private *priv)
512 struct tse_buffer *buffer = NULL;
513 list_peek_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
517 /* check and return rx sgdma status without polling
519 static int sgdma_rxbusy(struct altera_tse_private *priv)
521 struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
522 return ioread32(&csr->status) & SGDMA_STSREG_BUSY;
525 /* waits for the tx sgdma to finish it's current operation, returns 0
526 * when it transitions to nonbusy, returns 1 if the operation times out
528 static int sgdma_txbusy(struct altera_tse_private *priv)
531 struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
533 /* if DMA is busy, wait for current transactino to finish */
534 while ((ioread32(&csr->status) & SGDMA_STSREG_BUSY) && (delay++ < 100))
537 if (ioread32(&csr->status) & SGDMA_STSREG_BUSY) {
538 netdev_err(priv->dev, "timeout waiting for tx dma\n");