drivers/net/ethernet/amazon/ena/ena_com.c

   1 /*
   2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include "ena_com.h"
  34
  35 /*****************************************************************************/
  36 /*****************************************************************************/
  37
  38 /* Timeout in micro-sec */
  39 #define ADMIN_CMD_TIMEOUT_US (3000000)
  40
  41 #define ENA_ASYNC_QUEUE_DEPTH 16
  42 #define ENA_ADMIN_QUEUE_DEPTH 32
  43
  44 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
  45                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
  46                 | (ENA_COMMON_SPEC_VERSION_MINOR))
  47
  48 #define ENA_CTRL_MAJOR          0
  49 #define ENA_CTRL_MINOR          0
  50 #define ENA_CTRL_SUB_MINOR      1
  51
  52 #define MIN_ENA_CTRL_VER \
  53         (((ENA_CTRL_MAJOR) << \
  54         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  55         ((ENA_CTRL_MINOR) << \
  56         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  57         (ENA_CTRL_SUB_MINOR))
  58
  59 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  60 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  61
  62 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  63
  64 /*****************************************************************************/
  65 /*****************************************************************************/
  66 /*****************************************************************************/
  67
  68 enum ena_cmd_status {
  69         ENA_CMD_SUBMITTED,
  70         ENA_CMD_COMPLETED,
  71         /* Abort - canceled by the driver */
  72         ENA_CMD_ABORTED,
  73 };
  74
  75 struct ena_comp_ctx {
  76         struct completion wait_event;
  77         struct ena_admin_acq_entry *user_cqe;
  78         u32 comp_size;
  79         enum ena_cmd_status status;
  80         /* status from the device */
  81         u8 comp_status;
  82         u8 cmd_opcode;
  83         bool occupied;
  84 };
  85
  86 struct ena_com_stats_ctx {
  87         struct ena_admin_aq_get_stats_cmd get_cmd;
  88         struct ena_admin_acq_get_stats_resp get_resp;
  89 };
  90
  91 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  92                                        struct ena_common_mem_addr *ena_addr,
  93                                        dma_addr_t addr)
  94 {
  95         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  96                 pr_err("dma address has more bits that the device supports\n");
  97                 return -EINVAL;
  98         }
  99
 100         ena_addr->mem_addr_low = (u32)addr;
 101         ena_addr->mem_addr_high = (u64)addr >> 32;
 102
 103         return 0;
 104 }
 105
 106 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
 107 {
 108         struct ena_com_admin_sq *sq = &queue->sq;
 109         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
 110
 111         sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr,
 112                                           GFP_KERNEL);
 113
 114         if (!sq->entries) {
 115                 pr_err("memory allocation failed");
 116                 return -ENOMEM;
 117         }
 118
 119         sq->head = 0;
 120         sq->tail = 0;
 121         sq->phase = 1;
 122
 123         sq->db_addr = NULL;
 124
 125         return 0;
 126 }
 127
 128 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 129 {
 130         struct ena_com_admin_cq *cq = &queue->cq;
 131         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 132
 133         cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr,
 134                                           GFP_KERNEL);
 135
 136         if (!cq->entries) {
 137                 pr_err("memory allocation failed");
 138                 return -ENOMEM;
 139         }
 140
 141         cq->head = 0;
 142         cq->phase = 1;
 143
 144         return 0;
 145 }
 146
 147 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 148                                    struct ena_aenq_handlers *aenq_handlers)
 149 {
 150         struct ena_com_aenq *aenq = &dev->aenq;
 151         u32 addr_low, addr_high, aenq_caps;
 152         u16 size;
 153
 154         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 155         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 156         aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr,
 157                                             GFP_KERNEL);
 158
 159         if (!aenq->entries) {
 160                 pr_err("memory allocation failed");
 161                 return -ENOMEM;
 162         }
 163
 164         aenq->head = aenq->q_depth;
 165         aenq->phase = 1;
 166
 167         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 168         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 169
 170         writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 171         writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 172
 173         aenq_caps = 0;
 174         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 175         aenq_caps |= (sizeof(struct ena_admin_aenq_entry)
 176                       << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 177                      ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 178         writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 179
 180         if (unlikely(!aenq_handlers)) {
 181                 pr_err("aenq handlers pointer is NULL\n");
 182                 return -EINVAL;
 183         }
 184
 185         aenq->aenq_handlers = aenq_handlers;
 186
 187         return 0;
 188 }
 189
 190 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
 191                                      struct ena_comp_ctx *comp_ctx)
 192 {
 193         comp_ctx->occupied = false;
 194         atomic_dec(&queue->outstanding_cmds);
 195 }
 196
 197 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 198                                           u16 command_id, bool capture)
 199 {
 200         if (unlikely(command_id >= queue->q_depth)) {
 201                 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 202                        command_id, queue->q_depth);
 203                 return NULL;
 204         }
 205
 206         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 207                 pr_err("Completion context is occupied\n");
 208                 return NULL;
 209         }
 210
 211         if (capture) {
 212                 atomic_inc(&queue->outstanding_cmds);
 213                 queue->comp_ctx[command_id].occupied = true;
 214         }
 215
 216         return &queue->comp_ctx[command_id];
 217 }
 218
 219 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 220                                                        struct ena_admin_aq_entry *cmd,
 221                                                        size_t cmd_size_in_bytes,
 222                                                        struct ena_admin_acq_entry *comp,
 223                                                        size_t comp_size_in_bytes)
 224 {
 225         struct ena_comp_ctx *comp_ctx;
 226         u16 tail_masked, cmd_id;
 227         u16 queue_size_mask;
 228         u16 cnt;
 229
 230         queue_size_mask = admin_queue->q_depth - 1;
 231
 232         tail_masked = admin_queue->sq.tail & queue_size_mask;
 233
 234         /* In case of queue FULL */
 235         cnt = atomic_read(&admin_queue->outstanding_cmds);
 236         if (cnt >= admin_queue->q_depth) {
 237                 pr_debug("admin queue is full.\n");
 238                 admin_queue->stats.out_of_space++;
 239                 return ERR_PTR(-ENOSPC);
 240         }
 241
 242         cmd_id = admin_queue->curr_cmd_id;
 243
 244         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 245                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 246
 247         cmd->aq_common_descriptor.command_id |= cmd_id &
 248                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 249
 250         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 251         if (unlikely(!comp_ctx))
 252                 return ERR_PTR(-EINVAL);
 253
 254         comp_ctx->status = ENA_CMD_SUBMITTED;
 255         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 256         comp_ctx->user_cqe = comp;
 257         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 258
 259         reinit_completion(&comp_ctx->wait_event);
 260
 261         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 262
 263         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 264                 queue_size_mask;
 265
 266         admin_queue->sq.tail++;
 267         admin_queue->stats.submitted_cmd++;
 268
 269         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 270                 admin_queue->sq.phase = !admin_queue->sq.phase;
 271
 272         writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
 273
 274         return comp_ctx;
 275 }
 276
 277 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 278 {
 279         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 280         struct ena_comp_ctx *comp_ctx;
 281         u16 i;
 282
 283         queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL);
 284         if (unlikely(!queue->comp_ctx)) {
 285                 pr_err("memory allocation failed");
 286                 return -ENOMEM;
 287         }
 288
 289         for (i = 0; i < queue->q_depth; i++) {
 290                 comp_ctx = get_comp_ctxt(queue, i, false);
 291                 if (comp_ctx)
 292                         init_completion(&comp_ctx->wait_event);
 293         }
 294
 295         return 0;
 296 }
 297
 298 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 299                                                      struct ena_admin_aq_entry *cmd,
 300                                                      size_t cmd_size_in_bytes,
 301                                                      struct ena_admin_acq_entry *comp,
 302                                                      size_t comp_size_in_bytes)
 303 {
 304         unsigned long flags;
 305         struct ena_comp_ctx *comp_ctx;
 306
 307         spin_lock_irqsave(&admin_queue->q_lock, flags);
 308         if (unlikely(!admin_queue->running_state)) {
 309                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 310                 return ERR_PTR(-ENODEV);
 311         }
 312         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 313                                               cmd_size_in_bytes,
 314                                               comp,
 315                                               comp_size_in_bytes);
 316         if (unlikely(IS_ERR(comp_ctx)))
 317                 admin_queue->running_state = false;
 318         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 319
 320         return comp_ctx;
 321 }
 322
 323 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 324                               struct ena_com_create_io_ctx *ctx,
 325                               struct ena_com_io_sq *io_sq)
 326 {
 327         size_t size;
 328         int dev_node = 0;
 329
 330         memset(&io_sq->desc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
 331
 332         io_sq->desc_entry_size =
 333                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 334                 sizeof(struct ena_eth_io_tx_desc) :
 335                 sizeof(struct ena_eth_io_rx_desc);
 336
 337         size = io_sq->desc_entry_size * io_sq->q_depth;
 338
 339         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 340                 dev_node = dev_to_node(ena_dev->dmadev);
 341                 set_dev_node(ena_dev->dmadev, ctx->numa_node);
 342                 io_sq->desc_addr.virt_addr =
 343                         dma_zalloc_coherent(ena_dev->dmadev, size,
 344                                             &io_sq->desc_addr.phys_addr,
 345                                             GFP_KERNEL);
 346                 set_dev_node(ena_dev->dmadev, dev_node);
 347                 if (!io_sq->desc_addr.virt_addr) {
 348                         io_sq->desc_addr.virt_addr =
 349                                 dma_zalloc_coherent(ena_dev->dmadev, size,
 350                                                     &io_sq->desc_addr.phys_addr,
 351                                                     GFP_KERNEL);
 352                 }
 353         } else {
 354                 dev_node = dev_to_node(ena_dev->dmadev);
 355                 set_dev_node(ena_dev->dmadev, ctx->numa_node);
 356                 io_sq->desc_addr.virt_addr =
 357                         devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
 358                 set_dev_node(ena_dev->dmadev, dev_node);
 359                 if (!io_sq->desc_addr.virt_addr) {
 360                         io_sq->desc_addr.virt_addr =
 361                                 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
 362                 }
 363         }
 364
 365         if (!io_sq->desc_addr.virt_addr) {
 366                 pr_err("memory allocation failed");
 367                 return -ENOMEM;
 368         }
 369
 370         io_sq->tail = 0;
 371         io_sq->next_to_comp = 0;
 372         io_sq->phase = 1;
 373
 374         return 0;
 375 }
 376
 377 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 378                               struct ena_com_create_io_ctx *ctx,
 379                               struct ena_com_io_cq *io_cq)
 380 {
 381         size_t size;
 382         int prev_node = 0;
 383
 384         memset(&io_cq->cdesc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
 385
 386         /* Use the basic completion descriptor for Rx */
 387         io_cq->cdesc_entry_size_in_bytes =
 388                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 389                 sizeof(struct ena_eth_io_tx_cdesc) :
 390                 sizeof(struct ena_eth_io_rx_cdesc_base);
 391
 392         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 393
 394         prev_node = dev_to_node(ena_dev->dmadev);
 395         set_dev_node(ena_dev->dmadev, ctx->numa_node);
 396         io_cq->cdesc_addr.virt_addr =
 397                 dma_zalloc_coherent(ena_dev->dmadev, size,
 398                                     &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
 399         set_dev_node(ena_dev->dmadev, prev_node);
 400         if (!io_cq->cdesc_addr.virt_addr) {
 401                 io_cq->cdesc_addr.virt_addr =
 402                         dma_zalloc_coherent(ena_dev->dmadev, size,
 403                                             &io_cq->cdesc_addr.phys_addr,
 404                                             GFP_KERNEL);
 405         }
 406
 407         if (!io_cq->cdesc_addr.virt_addr) {
 408                 pr_err("memory allocation failed");
 409                 return -ENOMEM;
 410         }
 411
 412         io_cq->phase = 1;
 413         io_cq->head = 0;
 414
 415         return 0;
 416 }
 417
 418 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 419                                                    struct ena_admin_acq_entry *cqe)
 420 {
 421         struct ena_comp_ctx *comp_ctx;
 422         u16 cmd_id;
 423
 424         cmd_id = cqe->acq_common_descriptor.command &
 425                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 426
 427         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 428         if (unlikely(!comp_ctx)) {
 429                 pr_err("comp_ctx is NULL. Changing the admin queue running state\n");
 430                 admin_queue->running_state = false;
 431                 return;
 432         }
 433
 434         comp_ctx->status = ENA_CMD_COMPLETED;
 435         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 436
 437         if (comp_ctx->user_cqe)
 438                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 439
 440         if (!admin_queue->polling)
 441                 complete(&comp_ctx->wait_event);
 442 }
 443
 444 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 445 {
 446         struct ena_admin_acq_entry *cqe = NULL;
 447         u16 comp_num = 0;
 448         u16 head_masked;
 449         u8 phase;
 450
 451         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 452         phase = admin_queue->cq.phase;
 453
 454         cqe = &admin_queue->cq.entries[head_masked];
 455
 456         /* Go over all the completions */
 457         while ((cqe->acq_common_descriptor.flags &
 458                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 459                 /* Do not read the rest of the completion entry before the
 460                  * phase bit was validated
 461                  */
 462                 rmb();
 463                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 464
 465                 head_masked++;
 466                 comp_num++;
 467                 if (unlikely(head_masked == admin_queue->q_depth)) {
 468                         head_masked = 0;
 469                         phase = !phase;
 470                 }
 471
 472                 cqe = &admin_queue->cq.entries[head_masked];
 473         }
 474
 475         admin_queue->cq.head += comp_num;
 476         admin_queue->cq.phase = phase;
 477         admin_queue->sq.head += comp_num;
 478         admin_queue->stats.completed_cmd += comp_num;
 479 }
 480
 481 static int ena_com_comp_status_to_errno(u8 comp_status)
 482 {
 483         if (unlikely(comp_status != 0))
 484                 pr_err("admin command failed[%u]\n", comp_status);
 485
 486         if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
 487                 return -EINVAL;
 488
 489         switch (comp_status) {
 490         case ENA_ADMIN_SUCCESS:
 491                 return 0;
 492         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 493                 return -ENOMEM;
 494         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 495                 return -EPERM;
 496         case ENA_ADMIN_BAD_OPCODE:
 497         case ENA_ADMIN_MALFORMED_REQUEST:
 498         case ENA_ADMIN_ILLEGAL_PARAMETER:
 499         case ENA_ADMIN_UNKNOWN_ERROR:
 500                 return -EINVAL;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 507                                                      struct ena_com_admin_queue *admin_queue)
 508 {
 509         unsigned long flags, timeout;
 510         int ret;
 511
 512         timeout = jiffies + ADMIN_CMD_TIMEOUT_US;
 513
 514         while (1) {
 515                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 516                 ena_com_handle_admin_completion(admin_queue);
 517                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 518
 519                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 520                         break;
 521
 522                 if (time_is_before_jiffies(timeout)) {
 523                         pr_err("Wait for completion (polling) timeout\n");
 524                         /* ENA didn't have any completion */
 525                         spin_lock_irqsave(&admin_queue->q_lock, flags);
 526                         admin_queue->stats.no_completion++;
 527                         admin_queue->running_state = false;
 528                         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 529
 530                         ret = -ETIME;
 531                         goto err;
 532                 }
 533
 534                 msleep(100);
 535         }
 536
 537         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 538                 pr_err("Command was aborted\n");
 539                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 540                 admin_queue->stats.aborted_cmd++;
 541                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 542                 ret = -ENODEV;
 543                 goto err;
 544         }
 545
 546         WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n",
 547              comp_ctx->status);
 548
 549         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 550 err:
 551         comp_ctxt_release(admin_queue, comp_ctx);
 552         return ret;
 553 }
 554
 555 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 556                                                         struct ena_com_admin_queue *admin_queue)
 557 {
 558         unsigned long flags;
 559         int ret;
 560
 561         wait_for_completion_timeout(&comp_ctx->wait_event,
 562                                     usecs_to_jiffies(ADMIN_CMD_TIMEOUT_US));
 563
 564         /* In case the command wasn't completed find out the root cause.
 565          * There might be 2 kinds of errors
 566          * 1) No completion (timeout reached)
 567          * 2) There is completion but the device didn't get any msi-x interrupt.
 568          */
 569         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 570                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 571                 ena_com_handle_admin_completion(admin_queue);
 572                 admin_queue->stats.no_completion++;
 573                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 574
 575                 if (comp_ctx->status == ENA_CMD_COMPLETED)
 576                         pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
 577                                comp_ctx->cmd_opcode);
 578                 else
 579                         pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
 580                                comp_ctx->cmd_opcode, comp_ctx->status);
 581
 582                 admin_queue->running_state = false;
 583                 ret = -ETIME;
 584                 goto err;
 585         }
 586
 587         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 588 err:
 589         comp_ctxt_release(admin_queue, comp_ctx);
 590         return ret;
 591 }
 592
 593 /* This method read the hardware device register through posting writes
 594  * and waiting for response
 595  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 596  */
 597 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 598 {
 599         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 600         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 601                 mmio_read->read_resp;
 602         u32 mmio_read_reg, ret;
 603         unsigned long flags;
 604         int i;
 605
 606         might_sleep();
 607
 608         /* If readless is disabled, perform regular read */
 609         if (!mmio_read->readless_supported)
 610                 return readl(ena_dev->reg_bar + offset);
 611
 612         spin_lock_irqsave(&mmio_read->lock, flags);
 613         mmio_read->seq_num++;
 614
 615         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 616         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 617                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 618         mmio_read_reg |= mmio_read->seq_num &
 619                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 620
 621         /* make sure read_resp->req_id get updated before the hw can write
 622          * there
 623          */
 624         wmb();
 625
 626         writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 627
 628         for (i = 0; i < ENA_REG_READ_TIMEOUT; i++) {
 629                 if (read_resp->req_id == mmio_read->seq_num)
 630                         break;
 631
 632                 udelay(1);
 633         }
 634
 635         if (unlikely(i == ENA_REG_READ_TIMEOUT)) {
 636                 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 637                        mmio_read->seq_num, offset, read_resp->req_id,
 638                        read_resp->reg_off);
 639                 ret = ENA_MMIO_READ_TIMEOUT;
 640                 goto err;
 641         }
 642
 643         if (read_resp->reg_off != offset) {
 644                 pr_err("Read failure: wrong offset provided");
 645                 ret = ENA_MMIO_READ_TIMEOUT;
 646         } else {
 647                 ret = read_resp->reg_val;
 648         }
 649 err:
 650         spin_unlock_irqrestore(&mmio_read->lock, flags);
 651
 652         return ret;
 653 }
 654
 655 /* There are two types to wait for completion.
 656  * Polling mode - wait until the completion is available.
 657  * Async mode - wait on wait queue until the completion is ready
 658  * (or the timeout expired).
 659  * It is expected that the IRQ called ena_com_handle_admin_completion
 660  * to mark the completions.
 661  */
 662 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 663                                              struct ena_com_admin_queue *admin_queue)
 664 {
 665         if (admin_queue->polling)
 666                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 667                                                                  admin_queue);
 668
 669         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 670                                                             admin_queue);
 671 }
 672
 673 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 674                                  struct ena_com_io_sq *io_sq)
 675 {
 676         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 677         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 678         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 679         u8 direction;
 680         int ret;
 681
 682         memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));
 683
 684         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 685                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 686         else
 687                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 688
 689         destroy_cmd.sq.sq_identity |= (direction <<
 690                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 691                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 692
 693         destroy_cmd.sq.sq_idx = io_sq->idx;
 694         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 695
 696         ret = ena_com_execute_admin_command(admin_queue,
 697                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 698                                             sizeof(destroy_cmd),
 699                                             (struct ena_admin_acq_entry *)&destroy_resp,
 700                                             sizeof(destroy_resp));
 701
 702         if (unlikely(ret && (ret != -ENODEV)))
 703                 pr_err("failed to destroy io sq error: %d\n", ret);
 704
 705         return ret;
 706 }
 707
 708 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 709                                   struct ena_com_io_sq *io_sq,
 710                                   struct ena_com_io_cq *io_cq)
 711 {
 712         size_t size;
 713
 714         if (io_cq->cdesc_addr.virt_addr) {
 715                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 716
 717                 dma_free_coherent(ena_dev->dmadev, size,
 718                                   io_cq->cdesc_addr.virt_addr,
 719                                   io_cq->cdesc_addr.phys_addr);
 720
 721                 io_cq->cdesc_addr.virt_addr = NULL;
 722         }
 723
 724         if (io_sq->desc_addr.virt_addr) {
 725                 size = io_sq->desc_entry_size * io_sq->q_depth;
 726
 727                 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
 728                         dma_free_coherent(ena_dev->dmadev, size,
 729                                           io_sq->desc_addr.virt_addr,
 730                                           io_sq->desc_addr.phys_addr);
 731                 else
 732                         devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr);
 733
 734                 io_sq->desc_addr.virt_addr = NULL;
 735         }
 736 }
 737
 738 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 739                                 u16 exp_state)
 740 {
 741         u32 val, i;
 742
 743         for (i = 0; i < timeout; i++) {
 744                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 745
 746                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 747                         pr_err("Reg read timeout occurred\n");
 748                         return -ETIME;
 749                 }
 750
 751                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 752                         exp_state)
 753                         return 0;
 754
 755                 /* The resolution of the timeout is 100ms */
 756                 msleep(100);
 757         }
 758
 759         return -ETIME;
 760 }
 761
 762 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 763                                                enum ena_admin_aq_feature_id feature_id)
 764 {
 765         u32 feature_mask = 1 << feature_id;
 766
 767         /* Device attributes is always supported */
 768         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 769             !(ena_dev->supported_features & feature_mask))
 770                 return false;
 771
 772         return true;
 773 }
 774
 775 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 776                                   struct ena_admin_get_feat_resp *get_resp,
 777                                   enum ena_admin_aq_feature_id feature_id,
 778                                   dma_addr_t control_buf_dma_addr,
 779                                   u32 control_buff_size)
 780 {
 781         struct ena_com_admin_queue *admin_queue;
 782         struct ena_admin_get_feat_cmd get_cmd;
 783         int ret;
 784
 785         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
 786                 pr_debug("Feature %d isn't supported\n", feature_id);
 787                 return -EPERM;
 788         }
 789
 790         memset(&get_cmd, 0x0, sizeof(get_cmd));
 791         admin_queue = &ena_dev->admin_queue;
 792
 793         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
 794
 795         if (control_buff_size)
 796                 get_cmd.aq_common_descriptor.flags =
 797                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
 798         else
 799                 get_cmd.aq_common_descriptor.flags = 0;
 800
 801         ret = ena_com_mem_addr_set(ena_dev,
 802                                    &get_cmd.control_buffer.address,
 803                                    control_buf_dma_addr);
 804         if (unlikely(ret)) {
 805                 pr_err("memory address set failed\n");
 806                 return ret;
 807         }
 808
 809         get_cmd.control_buffer.length = control_buff_size;
 810
 811         get_cmd.feat_common.feature_id = feature_id;
 812
 813         ret = ena_com_execute_admin_command(admin_queue,
 814                                             (struct ena_admin_aq_entry *)
 815                                             &get_cmd,
 816                                             sizeof(get_cmd),
 817                                             (struct ena_admin_acq_entry *)
 818                                             get_resp,
 819                                             sizeof(*get_resp));
 820
 821         if (unlikely(ret))
 822                 pr_err("Failed to submit get_feature command %d error: %d\n",
 823                        feature_id, ret);
 824
 825         return ret;
 826 }
 827
 828 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
 829                                struct ena_admin_get_feat_resp *get_resp,
 830                                enum ena_admin_aq_feature_id feature_id)
 831 {
 832         return ena_com_get_feature_ex(ena_dev,
 833                                       get_resp,
 834                                       feature_id,
 835                                       0,
 836                                       0);
 837 }
 838
 839 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
 840 {
 841         struct ena_rss *rss = &ena_dev->rss;
 842
 843         rss->hash_key =
 844                 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
 845                                     &rss->hash_key_dma_addr, GFP_KERNEL);
 846
 847         if (unlikely(!rss->hash_key))
 848                 return -ENOMEM;
 849
 850         return 0;
 851 }
 852
 853 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
 854 {
 855         struct ena_rss *rss = &ena_dev->rss;
 856
 857         if (rss->hash_key)
 858                 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
 859                                   rss->hash_key, rss->hash_key_dma_addr);
 860         rss->hash_key = NULL;
 861 }
 862
 863 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
 864 {
 865         struct ena_rss *rss = &ena_dev->rss;
 866
 867         rss->hash_ctrl =
 868                 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
 869                                     &rss->hash_ctrl_dma_addr, GFP_KERNEL);
 870
 871         if (unlikely(!rss->hash_ctrl))
 872                 return -ENOMEM;
 873
 874         return 0;
 875 }
 876
 877 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
 878 {
 879         struct ena_rss *rss = &ena_dev->rss;
 880
 881         if (rss->hash_ctrl)
 882                 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
 883                                   rss->hash_ctrl, rss->hash_ctrl_dma_addr);
 884         rss->hash_ctrl = NULL;
 885 }
 886
 887 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
 888                                            u16 log_size)
 889 {
 890         struct ena_rss *rss = &ena_dev->rss;
 891         struct ena_admin_get_feat_resp get_resp;
 892         size_t tbl_size;
 893         int ret;
 894
 895         ret = ena_com_get_feature(ena_dev, &get_resp,
 896                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
 897         if (unlikely(ret))
 898                 return ret;
 899
 900         if ((get_resp.u.ind_table.min_size > log_size) ||
 901             (get_resp.u.ind_table.max_size < log_size)) {
 902                 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
 903                        1 << log_size, 1 << get_resp.u.ind_table.min_size,
 904                        1 << get_resp.u.ind_table.max_size);
 905                 return -EINVAL;
 906         }
 907
 908         tbl_size = (1ULL << log_size) *
 909                 sizeof(struct ena_admin_rss_ind_table_entry);
 910
 911         rss->rss_ind_tbl =
 912                 dma_zalloc_coherent(ena_dev->dmadev, tbl_size,
 913                                     &rss->rss_ind_tbl_dma_addr, GFP_KERNEL);
 914         if (unlikely(!rss->rss_ind_tbl))
 915                 goto mem_err1;
 916
 917         tbl_size = (1ULL << log_size) * sizeof(u16);
 918         rss->host_rss_ind_tbl =
 919                 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
 920         if (unlikely(!rss->host_rss_ind_tbl))
 921                 goto mem_err2;
 922
 923         rss->tbl_log_size = log_size;
 924
 925         return 0;
 926
 927 mem_err2:
 928         tbl_size = (1ULL << log_size) *
 929                 sizeof(struct ena_admin_rss_ind_table_entry);
 930
 931         dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
 932                           rss->rss_ind_tbl_dma_addr);
 933         rss->rss_ind_tbl = NULL;
 934 mem_err1:
 935         rss->tbl_log_size = 0;
 936         return -ENOMEM;
 937 }
 938
 939 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
 940 {
 941         struct ena_rss *rss = &ena_dev->rss;
 942         size_t tbl_size = (1ULL << rss->tbl_log_size) *
 943                 sizeof(struct ena_admin_rss_ind_table_entry);
 944
 945         if (rss->rss_ind_tbl)
 946                 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
 947                                   rss->rss_ind_tbl_dma_addr);
 948         rss->rss_ind_tbl = NULL;
 949
 950         if (rss->host_rss_ind_tbl)
 951                 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
 952         rss->host_rss_ind_tbl = NULL;
 953 }
 954
 955 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
 956                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
 957 {
 958         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 959         struct ena_admin_aq_create_sq_cmd create_cmd;
 960         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
 961         u8 direction;
 962         int ret;
 963
 964         memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_sq_cmd));
 965
 966         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
 967
 968         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 969                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 970         else
 971                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 972
 973         create_cmd.sq_identity |= (direction <<
 974                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
 975                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
 976
 977         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
 978                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
 979
 980         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
 981                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
 982                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
 983
 984         create_cmd.sq_caps_3 |=
 985                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
 986
 987         create_cmd.cq_idx = cq_idx;
 988         create_cmd.sq_depth = io_sq->q_depth;
 989
 990         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 991                 ret = ena_com_mem_addr_set(ena_dev,
 992                                            &create_cmd.sq_ba,
 993                                            io_sq->desc_addr.phys_addr);
 994                 if (unlikely(ret)) {
 995                         pr_err("memory address set failed\n");
 996                         return ret;
 997                 }
 998         }
 999
1000         ret = ena_com_execute_admin_command(admin_queue,
1001                                             (struct ena_admin_aq_entry *)&create_cmd,
1002                                             sizeof(create_cmd),
1003                                             (struct ena_admin_acq_entry *)&cmd_completion,
1004                                             sizeof(cmd_completion));
1005         if (unlikely(ret)) {
1006                 pr_err("Failed to create IO SQ. error: %d\n", ret);
1007                 return ret;
1008         }
1009
1010         io_sq->idx = cmd_completion.sq_idx;
1011
1012         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1013                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1014
1015         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1016                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1017                                 + cmd_completion.llq_headers_offset);
1018
1019                 io_sq->desc_addr.pbuf_dev_addr =
1020                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1021                         cmd_completion.llq_descriptors_offset);
1022         }
1023
1024         pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1025
1026         return ret;
1027 }
1028
1029 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1030 {
1031         struct ena_rss *rss = &ena_dev->rss;
1032         struct ena_com_io_sq *io_sq;
1033         u16 qid;
1034         int i;
1035
1036         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1037                 qid = rss->host_rss_ind_tbl[i];
1038                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1039                         return -EINVAL;
1040
1041                 io_sq = &ena_dev->io_sq_queues[qid];
1042
1043                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1044                         return -EINVAL;
1045
1046                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1047         }
1048
1049         return 0;
1050 }
1051
1052 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1053 {
1054         u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1055         struct ena_rss *rss = &ena_dev->rss;
1056         u8 idx;
1057         u16 i;
1058
1059         for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1060                 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1061
1062         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1063                 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1064                         return -EINVAL;
1065                 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1066
1067                 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1068                         return -EINVAL;
1069
1070                 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1071         }
1072
1073         return 0;
1074 }
1075
1076 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1077 {
1078         size_t size;
1079
1080         size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1081
1082         ena_dev->intr_moder_tbl =
1083                 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
1084         if (!ena_dev->intr_moder_tbl)
1085                 return -ENOMEM;
1086
1087         ena_com_config_default_interrupt_moderation_table(ena_dev);
1088
1089         return 0;
1090 }
1091
1092 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1093                                                  u16 intr_delay_resolution)
1094 {
1095         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1096         unsigned int i;
1097
1098         if (!intr_delay_resolution) {
1099                 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1100                 intr_delay_resolution = 1;
1101         }
1102         ena_dev->intr_delay_resolution = intr_delay_resolution;
1103
1104         /* update Rx */
1105         for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1106                 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1107
1108         /* update Tx */
1109         ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1110 }
1111
1112 /*****************************************************************************/
1113 /*******************************      API       ******************************/
1114 /*****************************************************************************/
1115
1116 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1117                                   struct ena_admin_aq_entry *cmd,
1118                                   size_t cmd_size,
1119                                   struct ena_admin_acq_entry *comp,
1120                                   size_t comp_size)
1121 {
1122         struct ena_comp_ctx *comp_ctx;
1123         int ret;
1124
1125         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1126                                             comp, comp_size);
1127         if (unlikely(IS_ERR(comp_ctx))) {
1128                 if (comp_ctx == ERR_PTR(-ENODEV))
1129                         pr_debug("Failed to submit command [%ld]\n",
1130                                  PTR_ERR(comp_ctx));
1131                 else
1132                         pr_err("Failed to submit command [%ld]\n",
1133                                PTR_ERR(comp_ctx));
1134
1135                 return PTR_ERR(comp_ctx);
1136         }
1137
1138         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1139         if (unlikely(ret)) {
1140                 if (admin_queue->running_state)
1141                         pr_err("Failed to process command. ret = %d\n", ret);
1142                 else
1143                         pr_debug("Failed to process command. ret = %d\n", ret);
1144         }
1145         return ret;
1146 }
1147
1148 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1149                          struct ena_com_io_cq *io_cq)
1150 {
1151         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1152         struct ena_admin_aq_create_cq_cmd create_cmd;
1153         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1154         int ret;
1155
1156         memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_cq_cmd));
1157
1158         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1159
1160         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1161                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1162         create_cmd.cq_caps_1 |=
1163                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1164
1165         create_cmd.msix_vector = io_cq->msix_vector;
1166         create_cmd.cq_depth = io_cq->q_depth;
1167
1168         ret = ena_com_mem_addr_set(ena_dev,
1169                                    &create_cmd.cq_ba,
1170                                    io_cq->cdesc_addr.phys_addr);
1171         if (unlikely(ret)) {
1172                 pr_err("memory address set failed\n");
1173                 return ret;
1174         }
1175
1176         ret = ena_com_execute_admin_command(admin_queue,
1177                                             (struct ena_admin_aq_entry *)&create_cmd,
1178                                             sizeof(create_cmd),
1179                                             (struct ena_admin_acq_entry *)&cmd_completion,
1180                                             sizeof(cmd_completion));
1181         if (unlikely(ret)) {
1182                 pr_err("Failed to create IO CQ. error: %d\n", ret);
1183                 return ret;
1184         }
1185
1186         io_cq->idx = cmd_completion.cq_idx;
1187
1188         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1189                 cmd_completion.cq_interrupt_unmask_register_offset);
1190
1191         if (cmd_completion.cq_head_db_register_offset)
1192                 io_cq->cq_head_db_reg =
1193                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1194                         cmd_completion.cq_head_db_register_offset);
1195
1196         if (cmd_completion.numa_node_register_offset)
1197                 io_cq->numa_node_cfg_reg =
1198                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1199                         cmd_completion.numa_node_register_offset);
1200
1201         pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1202
1203         return ret;
1204 }
1205
1206 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1207                             struct ena_com_io_sq **io_sq,
1208                             struct ena_com_io_cq **io_cq)
1209 {
1210         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1211                 pr_err("Invalid queue number %d but the max is %d\n", qid,
1212                        ENA_TOTAL_NUM_QUEUES);
1213                 return -EINVAL;
1214         }
1215
1216         *io_sq = &ena_dev->io_sq_queues[qid];
1217         *io_cq = &ena_dev->io_cq_queues[qid];
1218
1219         return 0;
1220 }
1221
1222 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1223 {
1224         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1225         struct ena_comp_ctx *comp_ctx;
1226         u16 i;
1227
1228         if (!admin_queue->comp_ctx)
1229                 return;
1230
1231         for (i = 0; i < admin_queue->q_depth; i++) {
1232                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1233                 if (unlikely(!comp_ctx))
1234                         break;
1235
1236                 comp_ctx->status = ENA_CMD_ABORTED;
1237
1238                 complete(&comp_ctx->wait_event);
1239         }
1240 }
1241
1242 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1243 {
1244         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1245         unsigned long flags;
1246
1247         spin_lock_irqsave(&admin_queue->q_lock, flags);
1248         while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1249                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1250                 msleep(20);
1251                 spin_lock_irqsave(&admin_queue->q_lock, flags);
1252         }
1253         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1254 }
1255
1256 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1257                           struct ena_com_io_cq *io_cq)
1258 {
1259         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1260         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1261         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1262         int ret;
1263
1264         memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));
1265
1266         destroy_cmd.cq_idx = io_cq->idx;
1267         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1268
1269         ret = ena_com_execute_admin_command(admin_queue,
1270                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1271                                             sizeof(destroy_cmd),
1272                                             (struct ena_admin_acq_entry *)&destroy_resp,
1273                                             sizeof(destroy_resp));
1274
1275         if (unlikely(ret && (ret != -ENODEV)))
1276                 pr_err("Failed to destroy IO CQ. error: %d\n", ret);
1277
1278         return ret;
1279 }
1280
1281 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1282 {
1283         return ena_dev->admin_queue.running_state;
1284 }
1285
1286 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1287 {
1288         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1289         unsigned long flags;
1290
1291         spin_lock_irqsave(&admin_queue->q_lock, flags);
1292         ena_dev->admin_queue.running_state = state;
1293         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1294 }
1295
1296 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1297 {
1298         u16 depth = ena_dev->aenq.q_depth;
1299
1300         WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1301
1302         /* Init head_db to mark that all entries in the queue
1303          * are initially available
1304          */
1305         writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1306 }
1307
1308 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1309 {
1310         struct ena_com_admin_queue *admin_queue;
1311         struct ena_admin_set_feat_cmd cmd;
1312         struct ena_admin_set_feat_resp resp;
1313         struct ena_admin_get_feat_resp get_resp;
1314         int ret;
1315
1316         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1317         if (ret) {
1318                 pr_info("Can't get aenq configuration\n");
1319                 return ret;
1320         }
1321
1322         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1323                 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1324                         get_resp.u.aenq.supported_groups, groups_flag);
1325                 return -EPERM;
1326         }
1327
1328         memset(&cmd, 0x0, sizeof(cmd));
1329         admin_queue = &ena_dev->admin_queue;
1330
1331         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1332         cmd.aq_common_descriptor.flags = 0;
1333         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1334         cmd.u.aenq.enabled_groups = groups_flag;
1335
1336         ret = ena_com_execute_admin_command(admin_queue,
1337                                             (struct ena_admin_aq_entry *)&cmd,
1338                                             sizeof(cmd),
1339                                             (struct ena_admin_acq_entry *)&resp,
1340                                             sizeof(resp));
1341
1342         if (unlikely(ret))
1343                 pr_err("Failed to config AENQ ret: %d\n", ret);
1344
1345         return ret;
1346 }
1347
1348 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1349 {
1350         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1351         int width;
1352
1353         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1354                 pr_err("Reg read timeout occurred\n");
1355                 return -ETIME;
1356         }
1357
1358         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1359                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1360
1361         pr_debug("ENA dma width: %d\n", width);
1362
1363         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1364                 pr_err("DMA width illegal value: %d\n", width);
1365                 return -EINVAL;
1366         }
1367
1368         ena_dev->dma_addr_bits = width;
1369
1370         return width;
1371 }
1372
1373 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1374 {
1375         u32 ver;
1376         u32 ctrl_ver;
1377         u32 ctrl_ver_masked;
1378
1379         /* Make sure the ENA version and the controller version are at least
1380          * as the driver expects
1381          */
1382         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1383         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1384                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1385
1386         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1387                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1388                 pr_err("Reg read timeout occurred\n");
1389                 return -ETIME;
1390         }
1391
1392         pr_info("ena device version: %d.%d\n",
1393                 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1394                         ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1395                 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1396
1397         if (ver < MIN_ENA_VER) {
1398                 pr_err("ENA version is lower than the minimal version the driver supports\n");
1399                 return -1;
1400         }
1401
1402         pr_info("ena controller version: %d.%d.%d implementation version %d\n",
1403                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1404                         ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1405                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1406                         ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1407                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1408                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1409                         ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1410
1411         ctrl_ver_masked =
1412                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1413                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1414                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1415
1416         /* Validate the ctrl version without the implementation ID */
1417         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1418                 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1419                 return -1;
1420         }
1421
1422         return 0;
1423 }
1424
1425 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1426 {
1427         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1428         struct ena_com_admin_cq *cq = &admin_queue->cq;
1429         struct ena_com_admin_sq *sq = &admin_queue->sq;
1430         struct ena_com_aenq *aenq = &ena_dev->aenq;
1431         u16 size;
1432
1433         if (admin_queue->comp_ctx)
1434                 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1435         admin_queue->comp_ctx = NULL;
1436         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1437         if (sq->entries)
1438                 dma_free_coherent(ena_dev->dmadev, size, sq->entries,
1439                                   sq->dma_addr);
1440         sq->entries = NULL;
1441
1442         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1443         if (cq->entries)
1444                 dma_free_coherent(ena_dev->dmadev, size, cq->entries,
1445                                   cq->dma_addr);
1446         cq->entries = NULL;
1447
1448         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1449         if (ena_dev->aenq.entries)
1450                 dma_free_coherent(ena_dev->dmadev, size, aenq->entries,
1451                                   aenq->dma_addr);
1452         aenq->entries = NULL;
1453 }
1454
1455 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1456 {
1457         ena_dev->admin_queue.polling = polling;
1458 }
1459
1460 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1461 {
1462         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1463
1464         spin_lock_init(&mmio_read->lock);
1465         mmio_read->read_resp =
1466                 dma_zalloc_coherent(ena_dev->dmadev,
1467                                     sizeof(*mmio_read->read_resp),
1468                                     &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1469         if (unlikely(!mmio_read->read_resp))
1470                 return -ENOMEM;
1471
1472         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1473
1474         mmio_read->read_resp->req_id = 0x0;
1475         mmio_read->seq_num = 0x0;
1476         mmio_read->readless_supported = true;
1477
1478         return 0;
1479 }
1480
1481 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1482 {
1483         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1484
1485         mmio_read->readless_supported = readless_supported;
1486 }
1487
1488 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1489 {
1490         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1491
1492         writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1493         writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1494
1495         dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1496                           mmio_read->read_resp, mmio_read->read_resp_dma_addr);
1497
1498         mmio_read->read_resp = NULL;
1499 }
1500
1501 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1502 {
1503         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1504         u32 addr_low, addr_high;
1505
1506         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1507         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1508
1509         writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1510         writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1511 }
1512
1513 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1514                        struct ena_aenq_handlers *aenq_handlers,
1515                        bool init_spinlock)
1516 {
1517         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1518         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1519         int ret;
1520
1521         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1522
1523         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1524                 pr_err("Reg read timeout occurred\n");
1525                 return -ETIME;
1526         }
1527
1528         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1529                 pr_err("Device isn't ready, abort com init\n");
1530                 return -ENODEV;
1531         }
1532
1533         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1534
1535         admin_queue->q_dmadev = ena_dev->dmadev;
1536         admin_queue->polling = false;
1537         admin_queue->curr_cmd_id = 0;
1538
1539         atomic_set(&admin_queue->outstanding_cmds, 0);
1540
1541         if (init_spinlock)
1542                 spin_lock_init(&admin_queue->q_lock);
1543
1544         ret = ena_com_init_comp_ctxt(admin_queue);
1545         if (ret)
1546                 goto error;
1547
1548         ret = ena_com_admin_init_sq(admin_queue);
1549         if (ret)
1550                 goto error;
1551
1552         ret = ena_com_admin_init_cq(admin_queue);
1553         if (ret)
1554                 goto error;
1555
1556         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1557                 ENA_REGS_AQ_DB_OFF);
1558
1559         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1560         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1561
1562         writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1563         writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1564
1565         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1566         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1567
1568         writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1569         writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1570
1571         aq_caps = 0;
1572         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1573         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1574                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1575                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1576
1577         acq_caps = 0;
1578         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1579         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1580                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1581                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1582
1583         writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1584         writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1585         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1586         if (ret)
1587                 goto error;
1588
1589         admin_queue->running_state = true;
1590
1591         return 0;
1592 error:
1593         ena_com_admin_destroy(ena_dev);
1594
1595         return ret;
1596 }
1597
1598 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1599                             struct ena_com_create_io_ctx *ctx)
1600 {
1601         struct ena_com_io_sq *io_sq;
1602         struct ena_com_io_cq *io_cq;
1603         int ret;
1604
1605         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1606                 pr_err("Qid (%d) is bigger than max num of queues (%d)\n",
1607                        ctx->qid, ENA_TOTAL_NUM_QUEUES);
1608                 return -EINVAL;
1609         }
1610
1611         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1612         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1613
1614         memset(io_sq, 0x0, sizeof(struct ena_com_io_sq));
1615         memset(io_cq, 0x0, sizeof(struct ena_com_io_cq));
1616
1617         /* Init CQ */
1618         io_cq->q_depth = ctx->queue_size;
1619         io_cq->direction = ctx->direction;
1620         io_cq->qid = ctx->qid;
1621
1622         io_cq->msix_vector = ctx->msix_vector;
1623
1624         io_sq->q_depth = ctx->queue_size;
1625         io_sq->direction = ctx->direction;
1626         io_sq->qid = ctx->qid;
1627
1628         io_sq->mem_queue_type = ctx->mem_queue_type;
1629
1630         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1631                 /* header length is limited to 8 bits */
1632                 io_sq->tx_max_header_size =
1633                         min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1634
1635         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1636         if (ret)
1637                 goto error;
1638         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1639         if (ret)
1640                 goto error;
1641
1642         ret = ena_com_create_io_cq(ena_dev, io_cq);
1643         if (ret)
1644                 goto error;
1645
1646         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1647         if (ret)
1648                 goto destroy_io_cq;
1649
1650         return 0;
1651
1652 destroy_io_cq:
1653         ena_com_destroy_io_cq(ena_dev, io_cq);
1654 error:
1655         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1656         return ret;
1657 }
1658
1659 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1660 {
1661         struct ena_com_io_sq *io_sq;
1662         struct ena_com_io_cq *io_cq;
1663
1664         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1665                 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid,
1666                        ENA_TOTAL_NUM_QUEUES);
1667                 return;
1668         }
1669
1670         io_sq = &ena_dev->io_sq_queues[qid];
1671         io_cq = &ena_dev->io_cq_queues[qid];
1672
1673         ena_com_destroy_io_sq(ena_dev, io_sq);
1674         ena_com_destroy_io_cq(ena_dev, io_cq);
1675
1676         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1677 }
1678
1679 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1680                             struct ena_admin_get_feat_resp *resp)
1681 {
1682         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1683 }
1684
1685 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1686                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1687 {
1688         struct ena_admin_get_feat_resp get_resp;
1689         int rc;
1690
1691         rc = ena_com_get_feature(ena_dev, &get_resp,
1692                                  ENA_ADMIN_DEVICE_ATTRIBUTES);
1693         if (rc)
1694                 return rc;
1695
1696         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1697                sizeof(get_resp.u.dev_attr));
1698         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1699
1700         rc = ena_com_get_feature(ena_dev, &get_resp,
1701                                  ENA_ADMIN_MAX_QUEUES_NUM);
1702         if (rc)
1703                 return rc;
1704
1705         memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1706                sizeof(get_resp.u.max_queue));
1707         ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1708
1709         rc = ena_com_get_feature(ena_dev, &get_resp,
1710                                  ENA_ADMIN_AENQ_CONFIG);
1711         if (rc)
1712                 return rc;
1713
1714         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1715                sizeof(get_resp.u.aenq));
1716
1717         rc = ena_com_get_feature(ena_dev, &get_resp,
1718                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1719         if (rc)
1720                 return rc;
1721
1722         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1723                sizeof(get_resp.u.offload));
1724
1725         return 0;
1726 }
1727
1728 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1729 {
1730         ena_com_handle_admin_completion(&ena_dev->admin_queue);
1731 }
1732
1733 /* ena_handle_specific_aenq_event:
1734  * return the handler that is relevant to the specific event group
1735  */
1736 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1737                                                      u16 group)
1738 {
1739         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1740
1741         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1742                 return aenq_handlers->handlers[group];
1743
1744         return aenq_handlers->unimplemented_handler;
1745 }
1746
1747 /* ena_aenq_intr_handler:
1748  * handles the aenq incoming events.
1749  * pop events from the queue and apply the specific handler
1750  */
1751 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1752 {
1753         struct ena_admin_aenq_entry *aenq_e;
1754         struct ena_admin_aenq_common_desc *aenq_common;
1755         struct ena_com_aenq *aenq  = &dev->aenq;
1756         ena_aenq_handler handler_cb;
1757         u16 masked_head, processed = 0;
1758         u8 phase;
1759
1760         masked_head = aenq->head & (aenq->q_depth - 1);
1761         phase = aenq->phase;
1762         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1763         aenq_common = &aenq_e->aenq_common_desc;
1764
1765         /* Go over all the events */
1766         while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) ==
1767                phase) {
1768                 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1769                          aenq_common->group, aenq_common->syndrom,
1770                          (u64)aenq_common->timestamp_low +
1771                                  ((u64)aenq_common->timestamp_high << 32));
1772
1773                 /* Handle specific event*/
1774                 handler_cb = ena_com_get_specific_aenq_cb(dev,
1775                                                           aenq_common->group);
1776                 handler_cb(data, aenq_e); /* call the actual event handler*/
1777
1778                 /* Get next event entry */
1779                 masked_head++;
1780                 processed++;
1781
1782                 if (unlikely(masked_head == aenq->q_depth)) {
1783                         masked_head = 0;
1784                         phase = !phase;
1785                 }
1786                 aenq_e = &aenq->entries[masked_head];
1787                 aenq_common = &aenq_e->aenq_common_desc;
1788         }
1789
1790         aenq->head += processed;
1791         aenq->phase = phase;
1792
1793         /* Don't update aenq doorbell if there weren't any processed events */
1794         if (!processed)
1795                 return;
1796
1797         /* write the aenq doorbell after all AENQ descriptors were read */
1798         mb();
1799         writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1800 }
1801
1802 int ena_com_dev_reset(struct ena_com_dev *ena_dev)
1803 {
1804         u32 stat, timeout, cap, reset_val;
1805         int rc;
1806
1807         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1808         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1809
1810         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
1811                      (cap == ENA_MMIO_READ_TIMEOUT))) {
1812                 pr_err("Reg read32 timeout occurred\n");
1813                 return -ETIME;
1814         }
1815
1816         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
1817                 pr_err("Device isn't ready, can't reset device\n");
1818                 return -EINVAL;
1819         }
1820
1821         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1822                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1823         if (timeout == 0) {
1824                 pr_err("Invalid timeout value\n");
1825                 return -EINVAL;
1826         }
1827
1828         /* start reset */
1829         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
1830         writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1831
1832         /* Write again the MMIO read request address */
1833         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1834
1835         rc = wait_for_reset_state(ena_dev, timeout,
1836                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1837         if (rc != 0) {
1838                 pr_err("Reset indication didn't turn on\n");
1839                 return rc;
1840         }
1841
1842         /* reset done */
1843         writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1844         rc = wait_for_reset_state(ena_dev, timeout, 0);
1845         if (rc != 0) {
1846                 pr_err("Reset indication didn't turn off\n");
1847                 return rc;
1848         }
1849
1850         return 0;
1851 }
1852
1853 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
1854                              struct ena_com_stats_ctx *ctx,
1855                              enum ena_admin_get_stats_type type)
1856 {
1857         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
1858         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
1859         struct ena_com_admin_queue *admin_queue;
1860         int ret;
1861
1862         admin_queue = &ena_dev->admin_queue;
1863
1864         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
1865         get_cmd->aq_common_descriptor.flags = 0;
1866         get_cmd->type = type;
1867
1868         ret =  ena_com_execute_admin_command(admin_queue,
1869                                              (struct ena_admin_aq_entry *)get_cmd,
1870                                              sizeof(*get_cmd),
1871                                              (struct ena_admin_acq_entry *)get_resp,
1872                                              sizeof(*get_resp));
1873
1874         if (unlikely(ret))
1875                 pr_err("Failed to get stats. error: %d\n", ret);
1876
1877         return ret;
1878 }
1879
1880 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
1881                                 struct ena_admin_basic_stats *stats)
1882 {
1883         struct ena_com_stats_ctx ctx;
1884         int ret;
1885
1886         memset(&ctx, 0x0, sizeof(ctx));
1887         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
1888         if (likely(ret == 0))
1889                 memcpy(stats, &ctx.get_resp.basic_stats,
1890                        sizeof(ctx.get_resp.basic_stats));
1891
1892         return ret;
1893 }
1894
1895 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
1896 {
1897         struct ena_com_admin_queue *admin_queue;
1898         struct ena_admin_set_feat_cmd cmd;
1899         struct ena_admin_set_feat_resp resp;
1900         int ret;
1901
1902         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
1903                 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU);
1904                 return -EPERM;
1905         }
1906
1907         memset(&cmd, 0x0, sizeof(cmd));
1908         admin_queue = &ena_dev->admin_queue;
1909
1910         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1911         cmd.aq_common_descriptor.flags = 0;
1912         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
1913         cmd.u.mtu.mtu = mtu;
1914
1915         ret = ena_com_execute_admin_command(admin_queue,
1916                                             (struct ena_admin_aq_entry *)&cmd,
1917                                             sizeof(cmd),
1918                                             (struct ena_admin_acq_entry *)&resp,
1919                                             sizeof(resp));
1920
1921         if (unlikely(ret))
1922                 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret);
1923
1924         return ret;
1925 }
1926
1927 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
1928                                  struct ena_admin_feature_offload_desc *offload)
1929 {
1930         int ret;
1931         struct ena_admin_get_feat_resp resp;
1932
1933         ret = ena_com_get_feature(ena_dev, &resp,
1934                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1935         if (unlikely(ret)) {
1936                 pr_err("Failed to get offload capabilities %d\n", ret);
1937                 return ret;
1938         }
1939
1940         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
1941
1942         return 0;
1943 }
1944
1945 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
1946 {
1947         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1948         struct ena_rss *rss = &ena_dev->rss;
1949         struct ena_admin_set_feat_cmd cmd;
1950         struct ena_admin_set_feat_resp resp;
1951         struct ena_admin_get_feat_resp get_resp;
1952         int ret;
1953
1954         if (!ena_com_check_supported_feature_id(ena_dev,
1955                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
1956                 pr_debug("Feature %d isn't supported\n",
1957                          ENA_ADMIN_RSS_HASH_FUNCTION);
1958                 return -EPERM;
1959         }
1960
1961         /* Validate hash function is supported */
1962         ret = ena_com_get_feature(ena_dev, &get_resp,
1963                                   ENA_ADMIN_RSS_HASH_FUNCTION);
1964         if (unlikely(ret))
1965                 return ret;
1966
1967         if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {
1968                 pr_err("Func hash %d isn't supported by device, abort\n",
1969                        rss->hash_func);
1970                 return -EPERM;
1971         }
1972
1973         memset(&cmd, 0x0, sizeof(cmd));
1974
1975         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1976         cmd.aq_common_descriptor.flags =
1977                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1978         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
1979         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
1980         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
1981
1982         ret = ena_com_mem_addr_set(ena_dev,
1983                                    &cmd.control_buffer.address,
1984                                    rss->hash_key_dma_addr);
1985         if (unlikely(ret)) {
1986                 pr_err("memory address set failed\n");
1987                 return ret;
1988         }
1989
1990         cmd.control_buffer.length = sizeof(*rss->hash_key);
1991
1992         ret = ena_com_execute_admin_command(admin_queue,
1993                                             (struct ena_admin_aq_entry *)&cmd,
1994                                             sizeof(cmd),
1995                                             (struct ena_admin_acq_entry *)&resp,
1996                                             sizeof(resp));
1997         if (unlikely(ret)) {
1998                 pr_err("Failed to set hash function %d. error: %d\n",
1999                        rss->hash_func, ret);
2000                 return -EINVAL;
2001         }
2002
2003         return 0;
2004 }
2005
2006 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2007                                enum ena_admin_hash_functions func,
2008                                const u8 *key, u16 key_len, u32 init_val)
2009 {
2010         struct ena_rss *rss = &ena_dev->rss;
2011         struct ena_admin_get_feat_resp get_resp;
2012         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2013                 rss->hash_key;
2014         int rc;
2015
2016         /* Make sure size is a mult of DWs */
2017         if (unlikely(key_len & 0x3))
2018                 return -EINVAL;
2019
2020         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2021                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2022                                     rss->hash_key_dma_addr,
2023                                     sizeof(*rss->hash_key));
2024         if (unlikely(rc))
2025                 return rc;
2026
2027         if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2028                 pr_err("Flow hash function %d isn't supported\n", func);
2029                 return -EPERM;
2030         }
2031
2032         switch (func) {
2033         case ENA_ADMIN_TOEPLITZ:
2034                 if (key_len > sizeof(hash_key->key)) {
2035                         pr_err("key len (%hu) is bigger than the max supported (%zu)\n",
2036                                key_len, sizeof(hash_key->key));
2037                         return -EINVAL;
2038                 }
2039
2040                 memcpy(hash_key->key, key, key_len);
2041                 rss->hash_init_val = init_val;
2042                 hash_key->keys_num = key_len >> 2;
2043                 break;
2044         case ENA_ADMIN_CRC32:
2045                 rss->hash_init_val = init_val;
2046                 break;
2047         default:
2048                 pr_err("Invalid hash function (%d)\n", func);
2049                 return -EINVAL;
2050         }
2051
2052         rc = ena_com_set_hash_function(ena_dev);
2053
2054         /* Restore the old function */
2055         if (unlikely(rc))
2056                 ena_com_get_hash_function(ena_dev, NULL, NULL);
2057
2058         return rc;
2059 }
2060
2061 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2062                               enum ena_admin_hash_functions *func,
2063                               u8 *key)
2064 {
2065         struct ena_rss *rss = &ena_dev->rss;
2066         struct ena_admin_get_feat_resp get_resp;
2067         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2068                 rss->hash_key;
2069         int rc;
2070
2071         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2072                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2073                                     rss->hash_key_dma_addr,
2074                                     sizeof(*rss->hash_key));
2075         if (unlikely(rc))
2076                 return rc;
2077
2078         rss->hash_func = get_resp.u.flow_hash_func.selected_func;
2079         if (func)
2080                 *func = rss->hash_func;
2081
2082         if (key)
2083                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2084
2085         return 0;
2086 }
2087
2088 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2089                           enum ena_admin_flow_hash_proto proto,
2090                           u16 *fields)
2091 {
2092         struct ena_rss *rss = &ena_dev->rss;
2093         struct ena_admin_get_feat_resp get_resp;
2094         int rc;
2095
2096         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2097                                     ENA_ADMIN_RSS_HASH_INPUT,
2098                                     rss->hash_ctrl_dma_addr,
2099                                     sizeof(*rss->hash_ctrl));
2100         if (unlikely(rc))
2101                 return rc;
2102
2103         if (fields)
2104                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2105
2106         return 0;
2107 }
2108
2109 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2110 {
2111         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2112         struct ena_rss *rss = &ena_dev->rss;
2113         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2114         struct ena_admin_set_feat_cmd cmd;
2115         struct ena_admin_set_feat_resp resp;
2116         int ret;
2117
2118         if (!ena_com_check_supported_feature_id(ena_dev,
2119                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2120                 pr_debug("Feature %d isn't supported\n",
2121                          ENA_ADMIN_RSS_HASH_INPUT);
2122                 return -EPERM;
2123         }
2124
2125         memset(&cmd, 0x0, sizeof(cmd));
2126
2127         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2128         cmd.aq_common_descriptor.flags =
2129                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2130         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2131         cmd.u.flow_hash_input.enabled_input_sort =
2132                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2133                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2134
2135         ret = ena_com_mem_addr_set(ena_dev,
2136                                    &cmd.control_buffer.address,
2137                                    rss->hash_ctrl_dma_addr);
2138         if (unlikely(ret)) {
2139                 pr_err("memory address set failed\n");
2140                 return ret;
2141         }
2142         cmd.control_buffer.length = sizeof(*hash_ctrl);
2143
2144         ret = ena_com_execute_admin_command(admin_queue,
2145                                             (struct ena_admin_aq_entry *)&cmd,
2146                                             sizeof(cmd),
2147                                             (struct ena_admin_acq_entry *)&resp,
2148                                             sizeof(resp));
2149         if (unlikely(ret))
2150                 pr_err("Failed to set hash input. error: %d\n", ret);
2151
2152         return ret;
2153 }
2154
2155 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2156 {
2157         struct ena_rss *rss = &ena_dev->rss;
2158         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2159                 rss->hash_ctrl;
2160         u16 available_fields = 0;
2161         int rc, i;
2162
2163         /* Get the supported hash input */
2164         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2165         if (unlikely(rc))
2166                 return rc;
2167
2168         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2169                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2170                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2171
2172         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2173                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2174                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2175
2176         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2177                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2178                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2179
2180         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2181                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2182                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2183
2184         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2185                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2186
2187         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2188                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2189
2190         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2191                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2192
2193         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2194                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2195
2196         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2197                 available_fields = hash_ctrl->selected_fields[i].fields &
2198                                 hash_ctrl->supported_fields[i].fields;
2199                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2200                         pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2201                                i, hash_ctrl->supported_fields[i].fields,
2202                                hash_ctrl->selected_fields[i].fields);
2203                         return -EPERM;
2204                 }
2205         }
2206
2207         rc = ena_com_set_hash_ctrl(ena_dev);
2208
2209         /* In case of failure, restore the old hash ctrl */
2210         if (unlikely(rc))
2211                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2212
2213         return rc;
2214 }
2215
2216 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2217                            enum ena_admin_flow_hash_proto proto,
2218                            u16 hash_fields)
2219 {
2220         struct ena_rss *rss = &ena_dev->rss;
2221         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2222         u16 supported_fields;
2223         int rc;
2224
2225         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2226                 pr_err("Invalid proto num (%u)\n", proto);
2227                 return -EINVAL;
2228         }
2229
2230         /* Get the ctrl table */
2231         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2232         if (unlikely(rc))
2233                 return rc;
2234
2235         /* Make sure all the fields are supported */
2236         supported_fields = hash_ctrl->supported_fields[proto].fields;
2237         if ((hash_fields & supported_fields) != hash_fields) {
2238                 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2239                        proto, hash_fields, supported_fields);
2240         }
2241
2242         hash_ctrl->selected_fields[proto].fields = hash_fields;
2243
2244         rc = ena_com_set_hash_ctrl(ena_dev);
2245
2246         /* In case of failure, restore the old hash ctrl */
2247         if (unlikely(rc))
2248                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2249
2250         return 0;
2251 }
2252
2253 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2254                                       u16 entry_idx, u16 entry_value)
2255 {
2256         struct ena_rss *rss = &ena_dev->rss;
2257
2258         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2259                 return -EINVAL;
2260
2261         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2262                 return -EINVAL;
2263
2264         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2265
2266         return 0;
2267 }
2268
2269 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2270 {
2271         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2272         struct ena_rss *rss = &ena_dev->rss;
2273         struct ena_admin_set_feat_cmd cmd;
2274         struct ena_admin_set_feat_resp resp;
2275         int ret;
2276
2277         if (!ena_com_check_supported_feature_id(
2278                     ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2279                 pr_debug("Feature %d isn't supported\n",
2280                          ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2281                 return -EPERM;
2282         }
2283
2284         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2285         if (ret) {
2286                 pr_err("Failed to convert host indirection table to device table\n");
2287                 return ret;
2288         }
2289
2290         memset(&cmd, 0x0, sizeof(cmd));
2291
2292         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2293         cmd.aq_common_descriptor.flags =
2294                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2295         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2296         cmd.u.ind_table.size = rss->tbl_log_size;
2297         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2298
2299         ret = ena_com_mem_addr_set(ena_dev,
2300                                    &cmd.control_buffer.address,
2301                                    rss->rss_ind_tbl_dma_addr);
2302         if (unlikely(ret)) {
2303                 pr_err("memory address set failed\n");
2304                 return ret;
2305         }
2306
2307         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2308                 sizeof(struct ena_admin_rss_ind_table_entry);
2309
2310         ret = ena_com_execute_admin_command(admin_queue,
2311                                             (struct ena_admin_aq_entry *)&cmd,
2312                                             sizeof(cmd),
2313                                             (struct ena_admin_acq_entry *)&resp,
2314                                             sizeof(resp));
2315
2316         if (unlikely(ret))
2317                 pr_err("Failed to set indirect table. error: %d\n", ret);
2318
2319         return ret;
2320 }
2321
2322 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2323 {
2324         struct ena_rss *rss = &ena_dev->rss;
2325         struct ena_admin_get_feat_resp get_resp;
2326         u32 tbl_size;
2327         int i, rc;
2328
2329         tbl_size = (1ULL << rss->tbl_log_size) *
2330                 sizeof(struct ena_admin_rss_ind_table_entry);
2331
2332         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2333                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2334                                     rss->rss_ind_tbl_dma_addr,
2335                                     tbl_size);
2336         if (unlikely(rc))
2337                 return rc;
2338
2339         if (!ind_tbl)
2340                 return 0;
2341
2342         rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2343         if (unlikely(rc))
2344                 return rc;
2345
2346         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2347                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2348
2349         return 0;
2350 }
2351
2352 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2353 {
2354         int rc;
2355
2356         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2357
2358         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2359         if (unlikely(rc))
2360                 goto err_indr_tbl;
2361
2362         rc = ena_com_hash_key_allocate(ena_dev);
2363         if (unlikely(rc))
2364                 goto err_hash_key;
2365
2366         rc = ena_com_hash_ctrl_init(ena_dev);
2367         if (unlikely(rc))
2368                 goto err_hash_ctrl;
2369
2370         return 0;
2371
2372 err_hash_ctrl:
2373         ena_com_hash_key_destroy(ena_dev);
2374 err_hash_key:
2375         ena_com_indirect_table_destroy(ena_dev);
2376 err_indr_tbl:
2377
2378         return rc;
2379 }
2380
2381 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2382 {
2383         ena_com_indirect_table_destroy(ena_dev);
2384         ena_com_hash_key_destroy(ena_dev);
2385         ena_com_hash_ctrl_destroy(ena_dev);
2386
2387         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2388 }
2389
2390 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2391 {
2392         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2393
2394         host_attr->host_info =
2395                 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K,
2396                                     &host_attr->host_info_dma_addr, GFP_KERNEL);
2397         if (unlikely(!host_attr->host_info))
2398                 return -ENOMEM;
2399
2400         return 0;
2401 }
2402
2403 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2404                                 u32 debug_area_size)
2405 {
2406         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2407
2408         host_attr->debug_area_virt_addr =
2409                 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size,
2410                                     &host_attr->debug_area_dma_addr, GFP_KERNEL);
2411         if (unlikely(!host_attr->debug_area_virt_addr)) {
2412                 host_attr->debug_area_size = 0;
2413                 return -ENOMEM;
2414         }
2415
2416         host_attr->debug_area_size = debug_area_size;
2417
2418         return 0;
2419 }
2420
2421 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2422 {
2423         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2424
2425         if (host_attr->host_info) {
2426                 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2427                                   host_attr->host_info_dma_addr);
2428                 host_attr->host_info = NULL;
2429         }
2430 }
2431
2432 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2433 {
2434         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2435
2436         if (host_attr->debug_area_virt_addr) {
2437                 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2438                                   host_attr->debug_area_virt_addr,
2439                                   host_attr->debug_area_dma_addr);
2440                 host_attr->debug_area_virt_addr = NULL;
2441         }
2442 }
2443
2444 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2445 {
2446         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2447         struct ena_com_admin_queue *admin_queue;
2448         struct ena_admin_set_feat_cmd cmd;
2449         struct ena_admin_set_feat_resp resp;
2450
2451         int ret;
2452
2453         /* Host attribute config is called before ena_com_get_dev_attr_feat
2454          * so ena_com can't check if the feature is supported.
2455          */
2456
2457         memset(&cmd, 0x0, sizeof(cmd));
2458         admin_queue = &ena_dev->admin_queue;
2459
2460         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2461         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2462
2463         ret = ena_com_mem_addr_set(ena_dev,
2464                                    &cmd.u.host_attr.debug_ba,
2465                                    host_attr->debug_area_dma_addr);
2466         if (unlikely(ret)) {
2467                 pr_err("memory address set failed\n");
2468                 return ret;
2469         }
2470
2471         ret = ena_com_mem_addr_set(ena_dev,
2472                                    &cmd.u.host_attr.os_info_ba,
2473                                    host_attr->host_info_dma_addr);
2474         if (unlikely(ret)) {
2475                 pr_err("memory address set failed\n");
2476                 return ret;
2477         }
2478
2479         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2480
2481         ret = ena_com_execute_admin_command(admin_queue,
2482                                             (struct ena_admin_aq_entry *)&cmd,
2483                                             sizeof(cmd),
2484                                             (struct ena_admin_acq_entry *)&resp,
2485                                             sizeof(resp));
2486
2487         if (unlikely(ret))
2488                 pr_err("Failed to set host attributes: %d\n", ret);
2489
2490         return ret;
2491 }
2492
2493 /* Interrupt moderation */
2494 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2495 {
2496         return ena_com_check_supported_feature_id(ena_dev,
2497                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2498 }
2499
2500 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2501                                                       u32 tx_coalesce_usecs)
2502 {
2503         if (!ena_dev->intr_delay_resolution) {
2504                 pr_err("Illegal interrupt delay granularity value\n");
2505                 return -EFAULT;
2506         }
2507
2508         ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2509                 ena_dev->intr_delay_resolution;
2510
2511         return 0;
2512 }
2513
2514 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2515                                                       u32 rx_coalesce_usecs)
2516 {
2517         if (!ena_dev->intr_delay_resolution) {
2518                 pr_err("Illegal interrupt delay granularity value\n");
2519                 return -EFAULT;
2520         }
2521
2522         /* We use LOWEST entry of moderation table for storing
2523          * nonadaptive interrupt coalescing values
2524          */
2525         ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2526                 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2527
2528         return 0;
2529 }
2530
2531 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2532 {
2533         if (ena_dev->intr_moder_tbl)
2534                 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2535         ena_dev->intr_moder_tbl = NULL;
2536 }
2537
2538 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2539 {
2540         struct ena_admin_get_feat_resp get_resp;
2541         u16 delay_resolution;
2542         int rc;
2543
2544         rc = ena_com_get_feature(ena_dev, &get_resp,
2545                                  ENA_ADMIN_INTERRUPT_MODERATION);
2546
2547         if (rc) {
2548                 if (rc == -EPERM) {
2549                         pr_debug("Feature %d isn't supported\n",
2550                                  ENA_ADMIN_INTERRUPT_MODERATION);
2551                         rc = 0;
2552                 } else {
2553                         pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2554                                rc);
2555                 }
2556
2557                 /* no moderation supported, disable adaptive support */
2558                 ena_com_disable_adaptive_moderation(ena_dev);
2559                 return rc;
2560         }
2561
2562         rc = ena_com_init_interrupt_moderation_table(ena_dev);
2563         if (rc)
2564                 goto err;
2565
2566         /* if moderation is supported by device we set adaptive moderation */
2567         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2568         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2569         ena_com_enable_adaptive_moderation(ena_dev);
2570
2571         return 0;
2572 err:
2573         ena_com_destroy_interrupt_moderation(ena_dev);
2574         return rc;
2575 }
2576
2577 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2578 {
2579         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2580
2581         if (!intr_moder_tbl)
2582                 return;
2583
2584         intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2585                 ENA_INTR_LOWEST_USECS;
2586         intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2587                 ENA_INTR_LOWEST_PKTS;
2588         intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2589                 ENA_INTR_LOWEST_BYTES;
2590
2591         intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2592                 ENA_INTR_LOW_USECS;
2593         intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2594                 ENA_INTR_LOW_PKTS;
2595         intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2596                 ENA_INTR_LOW_BYTES;
2597
2598         intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2599                 ENA_INTR_MID_USECS;
2600         intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2601                 ENA_INTR_MID_PKTS;
2602         intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2603                 ENA_INTR_MID_BYTES;
2604
2605         intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2606                 ENA_INTR_HIGH_USECS;
2607         intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2608                 ENA_INTR_HIGH_PKTS;
2609         intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2610                 ENA_INTR_HIGH_BYTES;
2611
2612         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2613                 ENA_INTR_HIGHEST_USECS;
2614         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2615                 ENA_INTR_HIGHEST_PKTS;
2616         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2617                 ENA_INTR_HIGHEST_BYTES;
2618 }
2619
2620 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2621 {
2622         return ena_dev->intr_moder_tx_interval;
2623 }
2624
2625 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2626 {
2627         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2628
2629         if (intr_moder_tbl)
2630                 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2631
2632         return 0;
2633 }
2634
2635 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2636                                         enum ena_intr_moder_level level,
2637                                         struct ena_intr_moder_entry *entry)
2638 {
2639         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2640
2641         if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2642                 return;
2643
2644         intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2645         if (ena_dev->intr_delay_resolution)
2646                 intr_moder_tbl[level].intr_moder_interval /=
2647                         ena_dev->intr_delay_resolution;
2648         intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2649
2650         /* use hardcoded value until ethtool supports bytecount parameter */
2651         if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
2652                 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2653 }
2654
2655 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2656                                        enum ena_intr_moder_level level,
2657                                        struct ena_intr_moder_entry *entry)
2658 {
2659         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2660
2661         if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2662                 return;
2663
2664         entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2665         if (ena_dev->intr_delay_resolution)
2666                 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2667         entry->pkts_per_interval =
2668         intr_moder_tbl[level].pkts_per_interval;
2669         entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2670 }