2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/kmod.h>
119 #include <linux/mdio.h>
120 #include <linux/phy.h>
121 #include <linux/of.h>
122 #include <linux/bitops.h>
123 #include <linux/jiffies.h>
126 #include "xgbe-common.h"
128 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
132 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
133 reg &= ~XGBE_AN_CL37_INT_MASK;
134 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
137 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
141 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
142 reg &= ~XGBE_AN_CL37_INT_MASK;
143 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
145 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
146 reg &= ~XGBE_PCS_CL37_BP;
147 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
150 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
154 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
155 reg |= XGBE_PCS_CL37_BP;
156 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
158 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
159 reg |= XGBE_AN_CL37_INT_MASK;
160 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
163 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
165 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
168 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
170 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
173 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
175 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
178 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
180 switch (pdata->an_mode) {
181 case XGBE_AN_MODE_CL73:
182 xgbe_an73_enable_interrupts(pdata);
184 case XGBE_AN_MODE_CL37:
185 case XGBE_AN_MODE_CL37_SGMII:
186 xgbe_an37_enable_interrupts(pdata);
193 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
195 xgbe_an73_clear_interrupts(pdata);
196 xgbe_an37_clear_interrupts(pdata);
199 static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata)
203 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
205 reg |= XGBE_KR_TRAINING_ENABLE;
206 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
209 static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata)
213 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
215 reg &= ~XGBE_KR_TRAINING_ENABLE;
216 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
221 /* Enable KR training */
222 xgbe_an73_enable_kr_training(pdata);
224 /* Set MAC to 10G speed */
225 pdata->hw_if.set_speed(pdata, SPEED_10000);
227 /* Call PHY implementation support to complete rate change */
228 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
231 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
233 /* Disable KR training */
234 xgbe_an73_disable_kr_training(pdata);
236 /* Set MAC to 2.5G speed */
237 pdata->hw_if.set_speed(pdata, SPEED_2500);
239 /* Call PHY implementation support to complete rate change */
240 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
243 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
245 /* Disable KR training */
246 xgbe_an73_disable_kr_training(pdata);
248 /* Set MAC to 1G speed */
249 pdata->hw_if.set_speed(pdata, SPEED_1000);
251 /* Call PHY implementation support to complete rate change */
252 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
255 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
257 /* Disable KR training */
258 xgbe_an73_disable_kr_training(pdata);
260 /* Set MAC to 10G speed */
261 pdata->hw_if.set_speed(pdata, SPEED_10000);
263 /* Call PHY implementation support to complete rate change */
264 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
267 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
269 /* Disable KR training */
270 xgbe_an73_disable_kr_training(pdata);
272 /* Set MAC to 1G speed */
273 pdata->hw_if.set_speed(pdata, SPEED_1000);
275 /* Call PHY implementation support to complete rate change */
276 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
279 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
281 /* Disable KR training */
282 xgbe_an73_disable_kr_training(pdata);
284 /* Set MAC to 1G speed */
285 pdata->hw_if.set_speed(pdata, SPEED_1000);
287 /* Call PHY implementation support to complete rate change */
288 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
291 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
293 /* Disable KR training */
294 xgbe_an73_disable_kr_training(pdata);
296 /* Set MAC to 1G speed */
297 pdata->hw_if.set_speed(pdata, SPEED_1000);
299 /* Call PHY implementation support to complete rate change */
300 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
303 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
305 return pdata->phy_if.phy_impl.cur_mode(pdata);
308 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
310 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
313 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
317 case XGBE_MODE_KX_1000:
318 xgbe_kx_1000_mode(pdata);
320 case XGBE_MODE_KX_2500:
321 xgbe_kx_2500_mode(pdata);
326 case XGBE_MODE_SGMII_100:
327 xgbe_sgmii_100_mode(pdata);
329 case XGBE_MODE_SGMII_1000:
330 xgbe_sgmii_1000_mode(pdata);
336 xgbe_sfi_mode(pdata);
338 case XGBE_MODE_UNKNOWN:
341 netif_dbg(pdata, link, pdata->netdev,
342 "invalid operation mode requested (%u)\n", mode);
346 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
348 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
351 static void xgbe_set_mode(struct xgbe_prv_data *pdata,
354 if (mode == xgbe_cur_mode(pdata))
357 xgbe_change_mode(pdata, mode);
360 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
363 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
366 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
371 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
372 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
375 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
378 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
380 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
383 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
385 xgbe_an37_enable_interrupts(pdata);
386 xgbe_an37_set(pdata, true, true);
388 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
391 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
393 xgbe_an37_set(pdata, false, false);
394 xgbe_an37_disable_interrupts(pdata);
396 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
399 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
404 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
405 reg &= ~MDIO_AN_CTRL1_ENABLE;
408 reg |= MDIO_AN_CTRL1_ENABLE;
411 reg |= MDIO_AN_CTRL1_RESTART;
413 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
416 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
418 xgbe_an73_enable_interrupts(pdata);
419 xgbe_an73_set(pdata, true, true);
421 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
424 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
426 xgbe_an73_set(pdata, false, false);
427 xgbe_an73_disable_interrupts(pdata);
429 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
432 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
434 switch (pdata->an_mode) {
435 case XGBE_AN_MODE_CL73:
436 xgbe_an73_restart(pdata);
438 case XGBE_AN_MODE_CL37:
439 case XGBE_AN_MODE_CL37_SGMII:
440 xgbe_an37_restart(pdata);
447 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
449 switch (pdata->an_mode) {
450 case XGBE_AN_MODE_CL73:
451 xgbe_an73_disable(pdata);
453 case XGBE_AN_MODE_CL37:
454 case XGBE_AN_MODE_CL37_SGMII:
455 xgbe_an37_disable(pdata);
462 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
464 xgbe_an73_disable(pdata);
465 xgbe_an37_disable(pdata);
468 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
471 unsigned int ad_reg, lp_reg, reg;
473 *state = XGBE_RX_COMPLETE;
475 /* If we're not in KR mode then we're done */
476 if (!xgbe_in_kr_mode(pdata))
477 return XGBE_AN_PAGE_RECEIVED;
479 /* Enable/Disable FEC */
480 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
481 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
483 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
484 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
485 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
486 reg |= pdata->fec_ability;
488 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
490 /* Start KR training */
491 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
492 if (reg & XGBE_KR_TRAINING_ENABLE) {
493 if (pdata->phy_if.phy_impl.kr_training_pre)
494 pdata->phy_if.phy_impl.kr_training_pre(pdata);
496 reg |= XGBE_KR_TRAINING_START;
497 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
500 if (pdata->phy_if.phy_impl.kr_training_post)
501 pdata->phy_if.phy_impl.kr_training_post(pdata);
503 netif_dbg(pdata, link, pdata->netdev,
504 "KR training initiated\n");
507 return XGBE_AN_PAGE_RECEIVED;
510 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
515 *state = XGBE_RX_XNP;
517 msg = XGBE_XNP_MCF_NULL_MESSAGE;
518 msg |= XGBE_XNP_MP_FORMATTED;
520 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
521 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
522 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
524 return XGBE_AN_PAGE_RECEIVED;
527 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
530 unsigned int link_support;
531 unsigned int reg, ad_reg, lp_reg;
533 /* Read Base Ability register 2 first */
534 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
536 /* Check for a supported mode, otherwise restart in a different one */
537 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
538 if (!(reg & link_support))
539 return XGBE_AN_INCOMPAT_LINK;
541 /* Check Extended Next Page support */
542 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
543 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
545 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
546 (lp_reg & XGBE_XNP_NP_EXCHANGE))
547 ? xgbe_an73_tx_xnp(pdata, state)
548 : xgbe_an73_tx_training(pdata, state);
551 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
554 unsigned int ad_reg, lp_reg;
556 /* Check Extended Next Page support */
557 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
558 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
560 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
561 (lp_reg & XGBE_XNP_NP_EXCHANGE))
562 ? xgbe_an73_tx_xnp(pdata, state)
563 : xgbe_an73_tx_training(pdata, state);
566 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
569 unsigned long an_timeout;
572 if (!pdata->an_start) {
573 pdata->an_start = jiffies;
575 an_timeout = pdata->an_start +
576 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
577 if (time_after(jiffies, an_timeout)) {
578 /* Auto-negotiation timed out, reset state */
579 pdata->kr_state = XGBE_RX_BPA;
580 pdata->kx_state = XGBE_RX_BPA;
582 pdata->an_start = jiffies;
584 netif_dbg(pdata, link, pdata->netdev,
585 "CL73 AN timed out, resetting state\n");
589 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
594 ret = xgbe_an73_rx_bpa(pdata, state);
598 ret = xgbe_an73_rx_xnp(pdata, state);
608 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
610 /* Be sure we aren't looping trying to negotiate */
611 if (xgbe_in_kr_mode(pdata)) {
612 pdata->kr_state = XGBE_RX_ERROR;
614 if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) &&
615 !(pdata->phy.advertising & ADVERTISED_2500baseX_Full))
616 return XGBE_AN_NO_LINK;
618 if (pdata->kx_state != XGBE_RX_BPA)
619 return XGBE_AN_NO_LINK;
621 pdata->kx_state = XGBE_RX_ERROR;
623 if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full))
624 return XGBE_AN_NO_LINK;
626 if (pdata->kr_state != XGBE_RX_BPA)
627 return XGBE_AN_NO_LINK;
630 xgbe_an73_disable(pdata);
632 xgbe_switch_mode(pdata);
634 xgbe_an73_restart(pdata);
636 return XGBE_AN_INCOMPAT_LINK;
639 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
643 /* Disable AN interrupts */
644 xgbe_an37_disable_interrupts(pdata);
646 /* Save the interrupt(s) that fired */
647 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
648 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
649 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
652 /* Clear the interrupt(s) that fired and process them */
653 reg &= ~XGBE_AN_CL37_INT_MASK;
654 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
656 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
658 /* Enable AN interrupts */
659 xgbe_an37_enable_interrupts(pdata);
663 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
665 /* Disable AN interrupts */
666 xgbe_an73_disable_interrupts(pdata);
668 /* Save the interrupt(s) that fired */
669 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
672 /* Clear the interrupt(s) that fired and process them */
673 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
675 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
677 /* Enable AN interrupts */
678 xgbe_an73_enable_interrupts(pdata);
682 static irqreturn_t xgbe_an_isr(int irq, void *data)
684 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
686 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
688 switch (pdata->an_mode) {
689 case XGBE_AN_MODE_CL73:
690 xgbe_an73_isr(pdata);
692 case XGBE_AN_MODE_CL37:
693 case XGBE_AN_MODE_CL37_SGMII:
694 xgbe_an37_isr(pdata);
703 static irqreturn_t xgbe_an_combined_isr(int irq, struct xgbe_prv_data *pdata)
705 return xgbe_an_isr(irq, pdata);
708 static void xgbe_an_irq_work(struct work_struct *work)
710 struct xgbe_prv_data *pdata = container_of(work,
711 struct xgbe_prv_data,
714 /* Avoid a race between enabling the IRQ and exiting the work by
715 * waiting for the work to finish and then queueing it
717 flush_work(&pdata->an_work);
718 queue_work(pdata->an_workqueue, &pdata->an_work);
721 static const char *xgbe_state_as_string(enum xgbe_an state)
726 case XGBE_AN_PAGE_RECEIVED:
727 return "Page-Received";
728 case XGBE_AN_INCOMPAT_LINK:
729 return "Incompatible-Link";
730 case XGBE_AN_COMPLETE:
732 case XGBE_AN_NO_LINK:
741 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
743 enum xgbe_an cur_state = pdata->an_state;
748 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
749 pdata->an_state = XGBE_AN_COMPLETE;
750 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
752 /* If SGMII is enabled, check the link status */
753 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
754 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
755 pdata->an_state = XGBE_AN_NO_LINK;
758 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
759 xgbe_state_as_string(pdata->an_state));
761 cur_state = pdata->an_state;
763 switch (pdata->an_state) {
767 case XGBE_AN_COMPLETE:
768 netif_dbg(pdata, link, pdata->netdev,
769 "Auto negotiation successful\n");
772 case XGBE_AN_NO_LINK:
776 pdata->an_state = XGBE_AN_ERROR;
779 if (pdata->an_state == XGBE_AN_ERROR) {
780 netdev_err(pdata->netdev,
781 "error during auto-negotiation, state=%u\n",
785 xgbe_an37_clear_interrupts(pdata);
788 if (pdata->an_state >= XGBE_AN_COMPLETE) {
789 pdata->an_result = pdata->an_state;
790 pdata->an_state = XGBE_AN_READY;
792 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
793 xgbe_state_as_string(pdata->an_result));
796 xgbe_an37_enable_interrupts(pdata);
799 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
801 enum xgbe_an cur_state = pdata->an_state;
807 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
808 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
809 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
810 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
811 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
812 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
813 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
814 pdata->an_state = XGBE_AN_COMPLETE;
815 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
817 pdata->an_state = XGBE_AN_ERROR;
821 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
822 xgbe_state_as_string(pdata->an_state));
824 cur_state = pdata->an_state;
826 switch (pdata->an_state) {
828 pdata->an_supported = 0;
831 case XGBE_AN_PAGE_RECEIVED:
832 pdata->an_state = xgbe_an73_page_received(pdata);
833 pdata->an_supported++;
836 case XGBE_AN_INCOMPAT_LINK:
837 pdata->an_supported = 0;
838 pdata->parallel_detect = 0;
839 pdata->an_state = xgbe_an73_incompat_link(pdata);
842 case XGBE_AN_COMPLETE:
843 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
844 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
845 pdata->an_supported ? "Auto negotiation"
846 : "Parallel detection");
849 case XGBE_AN_NO_LINK:
853 pdata->an_state = XGBE_AN_ERROR;
856 if (pdata->an_state == XGBE_AN_NO_LINK) {
858 xgbe_an73_clear_interrupts(pdata);
859 } else if (pdata->an_state == XGBE_AN_ERROR) {
860 netdev_err(pdata->netdev,
861 "error during auto-negotiation, state=%u\n",
865 xgbe_an73_clear_interrupts(pdata);
868 if (pdata->an_state >= XGBE_AN_COMPLETE) {
869 pdata->an_result = pdata->an_state;
870 pdata->an_state = XGBE_AN_READY;
871 pdata->kr_state = XGBE_RX_BPA;
872 pdata->kx_state = XGBE_RX_BPA;
875 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
876 xgbe_state_as_string(pdata->an_result));
879 if (cur_state != pdata->an_state)
885 xgbe_an73_enable_interrupts(pdata);
888 static void xgbe_an_state_machine(struct work_struct *work)
890 struct xgbe_prv_data *pdata = container_of(work,
891 struct xgbe_prv_data,
894 mutex_lock(&pdata->an_mutex);
896 switch (pdata->an_mode) {
897 case XGBE_AN_MODE_CL73:
898 xgbe_an73_state_machine(pdata);
900 case XGBE_AN_MODE_CL37:
901 case XGBE_AN_MODE_CL37_SGMII:
902 xgbe_an37_state_machine(pdata);
908 mutex_unlock(&pdata->an_mutex);
911 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
915 /* Set up Advertisement register */
916 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
917 if (pdata->phy.advertising & ADVERTISED_Pause)
922 if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
927 /* Full duplex, but not half */
928 reg |= XGBE_AN_CL37_FD_MASK;
929 reg &= ~XGBE_AN_CL37_HD_MASK;
931 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
933 /* Set up the Control register */
934 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
935 reg &= XGBE_AN_CL37_TX_CONFIG_MASK;
936 reg &= XGBE_AN_CL37_PCS_MODE_MASK;
938 switch (pdata->an_mode) {
939 case XGBE_AN_MODE_CL37:
940 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
942 case XGBE_AN_MODE_CL37_SGMII:
943 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
949 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
951 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
952 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
955 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
959 /* Set up Advertisement register 3 first */
960 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
961 if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC)
966 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
968 /* Set up Advertisement register 2 next */
969 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
970 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
975 if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
976 (pdata->phy.advertising & ADVERTISED_2500baseX_Full))
981 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
983 /* Set up Advertisement register 1 last */
984 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
985 if (pdata->phy.advertising & ADVERTISED_Pause)
990 if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
995 /* We don't intend to perform XNP */
996 reg &= ~XGBE_XNP_NP_EXCHANGE;
998 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1000 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1003 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1005 /* Set up advertisement registers based on current settings */
1006 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1007 switch (pdata->an_mode) {
1008 case XGBE_AN_MODE_CL73:
1009 xgbe_an73_init(pdata);
1011 case XGBE_AN_MODE_CL37:
1012 case XGBE_AN_MODE_CL37_SGMII:
1013 xgbe_an37_init(pdata);
1020 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1022 if (pdata->tx_pause && pdata->rx_pause)
1024 else if (pdata->rx_pause)
1026 else if (pdata->tx_pause)
1032 static const char *xgbe_phy_speed_string(int speed)
1046 return "Unsupported";
1050 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1052 if (pdata->phy.link)
1053 netdev_info(pdata->netdev,
1054 "Link is Up - %s/%s - flow control %s\n",
1055 xgbe_phy_speed_string(pdata->phy.speed),
1056 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1057 xgbe_phy_fc_string(pdata));
1059 netdev_info(pdata->netdev, "Link is Down\n");
1062 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1066 if (pdata->phy.link) {
1067 /* Flow control support */
1068 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1070 if (pdata->tx_pause != pdata->phy.tx_pause) {
1072 pdata->hw_if.config_tx_flow_control(pdata);
1073 pdata->tx_pause = pdata->phy.tx_pause;
1076 if (pdata->rx_pause != pdata->phy.rx_pause) {
1078 pdata->hw_if.config_rx_flow_control(pdata);
1079 pdata->rx_pause = pdata->phy.rx_pause;
1083 if (pdata->phy_speed != pdata->phy.speed) {
1085 pdata->phy_speed = pdata->phy.speed;
1088 if (pdata->phy_link != pdata->phy.link) {
1090 pdata->phy_link = pdata->phy.link;
1092 } else if (pdata->phy_link) {
1094 pdata->phy_link = 0;
1095 pdata->phy_speed = SPEED_UNKNOWN;
1098 if (new_state && netif_msg_link(pdata))
1099 xgbe_phy_print_status(pdata);
1102 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1104 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1107 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1109 enum xgbe_mode mode;
1111 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1113 /* Disable auto-negotiation */
1114 xgbe_an_disable(pdata);
1116 /* Set specified mode for specified speed */
1117 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1119 case XGBE_MODE_KX_1000:
1120 case XGBE_MODE_KX_2500:
1122 case XGBE_MODE_SGMII_100:
1123 case XGBE_MODE_SGMII_1000:
1127 case XGBE_MODE_UNKNOWN:
1132 /* Validate duplex mode */
1133 if (pdata->phy.duplex != DUPLEX_FULL)
1136 xgbe_set_mode(pdata, mode);
1141 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1145 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1146 pdata->link_check = jiffies;
1148 ret = pdata->phy_if.phy_impl.an_config(pdata);
1152 if (pdata->phy.autoneg != AUTONEG_ENABLE)
1153 return xgbe_phy_config_fixed(pdata);
1155 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1157 /* Disable auto-negotiation interrupt */
1158 disable_irq(pdata->an_irq);
1160 /* Start auto-negotiation in a supported mode */
1161 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1162 xgbe_set_mode(pdata, XGBE_MODE_KR);
1163 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1164 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1165 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1166 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1167 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1168 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1169 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1170 xgbe_set_mode(pdata, XGBE_MODE_X);
1171 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1172 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1173 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1174 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1176 enable_irq(pdata->an_irq);
1180 /* Disable and stop any in progress auto-negotiation */
1181 xgbe_an_disable_all(pdata);
1183 /* Clear any auto-negotitation interrupts */
1184 xgbe_an_clear_interrupts_all(pdata);
1186 pdata->an_result = XGBE_AN_READY;
1187 pdata->an_state = XGBE_AN_READY;
1188 pdata->kr_state = XGBE_RX_BPA;
1189 pdata->kx_state = XGBE_RX_BPA;
1191 /* Re-enable auto-negotiation interrupt */
1192 enable_irq(pdata->an_irq);
1194 xgbe_an_init(pdata);
1195 xgbe_an_restart(pdata);
1200 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1204 mutex_lock(&pdata->an_mutex);
1206 ret = __xgbe_phy_config_aneg(pdata);
1208 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1210 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1212 mutex_unlock(&pdata->an_mutex);
1217 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1219 return (pdata->an_result == XGBE_AN_COMPLETE);
1222 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1224 unsigned long link_timeout;
1226 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1227 if (time_after(jiffies, link_timeout)) {
1228 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1229 xgbe_phy_config_aneg(pdata);
1233 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1235 return pdata->phy_if.phy_impl.an_outcome(pdata);
1238 static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1240 enum xgbe_mode mode;
1242 pdata->phy.lp_advertising = 0;
1244 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1245 mode = xgbe_cur_mode(pdata);
1247 mode = xgbe_phy_status_aneg(pdata);
1250 case XGBE_MODE_SGMII_100:
1251 pdata->phy.speed = SPEED_100;
1254 case XGBE_MODE_KX_1000:
1255 case XGBE_MODE_SGMII_1000:
1256 pdata->phy.speed = SPEED_1000;
1258 case XGBE_MODE_KX_2500:
1259 pdata->phy.speed = SPEED_2500;
1263 pdata->phy.speed = SPEED_10000;
1265 case XGBE_MODE_UNKNOWN:
1267 pdata->phy.speed = SPEED_UNKNOWN;
1270 pdata->phy.duplex = DUPLEX_FULL;
1272 xgbe_set_mode(pdata, mode);
1275 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1277 unsigned int link_aneg;
1280 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1281 netif_carrier_off(pdata->netdev);
1283 pdata->phy.link = 0;
1287 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1289 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1292 xgbe_phy_config_aneg(pdata);
1296 if (pdata->phy.link) {
1297 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1298 xgbe_check_link_timeout(pdata);
1302 xgbe_phy_status_result(pdata);
1304 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1305 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1307 netif_carrier_on(pdata->netdev);
1309 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1310 xgbe_check_link_timeout(pdata);
1316 xgbe_phy_status_result(pdata);
1318 netif_carrier_off(pdata->netdev);
1322 xgbe_phy_adjust_link(pdata);
1325 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1327 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1329 if (!pdata->phy_started)
1332 /* Indicate the PHY is down */
1333 pdata->phy_started = 0;
1335 /* Disable auto-negotiation */
1336 xgbe_an_disable_all(pdata);
1338 if (pdata->dev_irq != pdata->an_irq)
1339 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1341 pdata->phy_if.phy_impl.stop(pdata);
1343 pdata->phy.link = 0;
1344 netif_carrier_off(pdata->netdev);
1346 xgbe_phy_adjust_link(pdata);
1349 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1351 struct net_device *netdev = pdata->netdev;
1354 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1356 ret = pdata->phy_if.phy_impl.start(pdata);
1360 /* If we have a separate AN irq, enable it */
1361 if (pdata->dev_irq != pdata->an_irq) {
1362 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1363 xgbe_an_isr, 0, pdata->an_name,
1366 netdev_err(netdev, "phy irq request failed\n");
1371 /* Set initial mode - call the mode setting routines
1372 * directly to insure we are properly configured
1374 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1375 xgbe_kr_mode(pdata);
1376 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1377 xgbe_kx_2500_mode(pdata);
1378 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1379 xgbe_kx_1000_mode(pdata);
1380 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1381 xgbe_sfi_mode(pdata);
1382 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1384 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1385 xgbe_sgmii_1000_mode(pdata);
1386 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1387 xgbe_sgmii_100_mode(pdata);
1393 /* Indicate the PHY is up and running */
1394 pdata->phy_started = 1;
1396 xgbe_an_init(pdata);
1397 xgbe_an_enable_interrupts(pdata);
1399 return xgbe_phy_config_aneg(pdata);
1402 if (pdata->dev_irq != pdata->an_irq)
1403 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1406 pdata->phy_if.phy_impl.stop(pdata);
1411 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1415 ret = pdata->phy_if.phy_impl.reset(pdata);
1419 /* Disable auto-negotiation for now */
1420 xgbe_an_disable_all(pdata);
1422 /* Clear auto-negotiation interrupts */
1423 xgbe_an_clear_interrupts_all(pdata);
1428 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1430 struct device *dev = pdata->dev;
1432 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1434 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1435 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1436 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1437 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1438 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1439 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1440 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1441 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1442 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1443 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1444 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1445 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1447 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1448 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1449 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1450 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1451 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1453 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1454 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1455 MDIO_AN_ADVERTISE + 1,
1456 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1457 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1458 MDIO_AN_ADVERTISE + 2,
1459 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1460 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1462 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1464 dev_dbg(dev, "\n*************************************************\n");
1467 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1469 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
1471 else if (pdata->phy.advertising & ADVERTISED_10000baseT_Full)
1473 else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full)
1475 else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full)
1477 else if (pdata->phy.advertising & ADVERTISED_1000baseT_Full)
1479 else if (pdata->phy.advertising & ADVERTISED_100baseT_Full)
1482 return SPEED_UNKNOWN;
1485 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1487 xgbe_phy_stop(pdata);
1489 pdata->phy_if.phy_impl.exit(pdata);
1492 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1496 mutex_init(&pdata->an_mutex);
1497 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1498 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1499 pdata->mdio_mmd = MDIO_MMD_PCS;
1501 /* Check for FEC support */
1502 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1503 MDIO_PMA_10GBR_FECABLE);
1504 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1505 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1507 /* Setup the phy (including supported features) */
1508 ret = pdata->phy_if.phy_impl.init(pdata);
1511 pdata->phy.advertising = pdata->phy.supported;
1513 pdata->phy.address = 0;
1515 if (pdata->phy.advertising & ADVERTISED_Autoneg) {
1516 pdata->phy.autoneg = AUTONEG_ENABLE;
1517 pdata->phy.speed = SPEED_UNKNOWN;
1518 pdata->phy.duplex = DUPLEX_UNKNOWN;
1520 pdata->phy.autoneg = AUTONEG_DISABLE;
1521 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1522 pdata->phy.duplex = DUPLEX_FULL;
1525 pdata->phy.link = 0;
1527 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1528 pdata->phy.tx_pause = pdata->tx_pause;
1529 pdata->phy.rx_pause = pdata->rx_pause;
1531 /* Fix up Flow Control advertising */
1532 pdata->phy.advertising &= ~ADVERTISED_Pause;
1533 pdata->phy.advertising &= ~ADVERTISED_Asym_Pause;
1535 if (pdata->rx_pause) {
1536 pdata->phy.advertising |= ADVERTISED_Pause;
1537 pdata->phy.advertising |= ADVERTISED_Asym_Pause;
1540 if (pdata->tx_pause)
1541 pdata->phy.advertising ^= ADVERTISED_Asym_Pause;
1543 if (netif_msg_drv(pdata))
1544 xgbe_dump_phy_registers(pdata);
1549 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1551 phy_if->phy_init = xgbe_phy_init;
1552 phy_if->phy_exit = xgbe_phy_exit;
1554 phy_if->phy_reset = xgbe_phy_reset;
1555 phy_if->phy_start = xgbe_phy_start;
1556 phy_if->phy_stop = xgbe_phy_stop;
1558 phy_if->phy_status = xgbe_phy_status;
1559 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1561 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1563 phy_if->an_isr = xgbe_an_combined_isr;