2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/timecounter.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
131 #define XGBE_DRV_NAME "amd-xgbe"
132 #define XGBE_DRV_VERSION "1.0.2"
133 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
135 /* Descriptor related defines */
136 #define XGBE_TX_DESC_CNT 512
137 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139 #define XGBE_RX_DESC_CNT 512
141 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
143 /* Descriptors required for maximum contigous TSO/GSO packet */
144 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
146 /* Maximum possible descriptors needed for an SKB:
147 * - Maximum number of SKB frags
148 * - Maximum descriptors for contiguous TSO/GSO packet
149 * - Possible context descriptor
150 * - Possible TSO header descriptor
152 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
154 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
155 #define XGBE_RX_BUF_ALIGN 64
156 #define XGBE_SKB_ALLOC_SIZE 256
157 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
159 #define XGBE_MAX_DMA_CHANNELS 16
160 #define XGBE_MAX_QUEUES 16
161 #define XGBE_DMA_STOP_TIMEOUT 5
163 /* DMA cache settings - Outer sharable, write-back, write-allocate */
164 #define XGBE_DMA_OS_AXDOMAIN 0x2
165 #define XGBE_DMA_OS_ARCACHE 0xb
166 #define XGBE_DMA_OS_AWCACHE 0xf
168 /* DMA cache settings - System, no caches used */
169 #define XGBE_DMA_SYS_AXDOMAIN 0x3
170 #define XGBE_DMA_SYS_ARCACHE 0x0
171 #define XGBE_DMA_SYS_AWCACHE 0x0
173 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
175 #define XGMAC_MIN_PACKET 60
176 #define XGMAC_STD_PACKET_MTU 1500
177 #define XGMAC_MAX_STD_PACKET 1518
178 #define XGMAC_JUMBO_PACKET_MTU 9000
179 #define XGMAC_MAX_JUMBO_PACKET 9018
181 /* Common property names */
182 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
183 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
184 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
185 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
186 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
187 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
188 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
189 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
190 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
191 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
193 /* Device-tree clock names */
194 #define XGBE_DMA_CLOCK "dma_clk"
195 #define XGBE_PTP_CLOCK "ptp_clk"
197 /* ACPI property names */
198 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
199 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
201 /* Timestamp support - values based on 50MHz PTP clock
204 #define XGBE_TSTAMP_SSINC 20
205 #define XGBE_TSTAMP_SNSINC 0
207 /* Driver PMT macros */
208 #define XGMAC_DRIVER_CONTEXT 1
209 #define XGMAC_IOCTL_CONTEXT 2
211 #define XGBE_FIFO_MAX 81920
212 #define XGBE_FIFO_SIZE_B(x) (x)
213 #define XGBE_FIFO_SIZE_KB(x) (x * 1024)
215 #define XGBE_TC_MIN_QUANTUM 10
217 /* Helper macro for descriptor handling
218 * Always use XGBE_GET_DESC_DATA to access the descriptor data
219 * since the index is free-running and needs to be and-ed
220 * with the descriptor count value of the ring to index to
221 * the proper descriptor data.
223 #define XGBE_GET_DESC_DATA(_ring, _idx) \
225 ((_idx) & ((_ring)->rdesc_count - 1)))
227 /* Default coalescing parameters */
228 #define XGMAC_INIT_DMA_TX_USECS 1000
229 #define XGMAC_INIT_DMA_TX_FRAMES 25
231 #define XGMAC_MAX_DMA_RIWT 0xff
232 #define XGMAC_INIT_DMA_RX_USECS 30
233 #define XGMAC_INIT_DMA_RX_FRAMES 25
235 /* Flow control queue count */
236 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
238 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
239 #define XGBE_MAC_HASH_TABLE_SIZE 8
241 /* Receive Side Scaling */
242 #define XGBE_RSS_HASH_KEY_SIZE 40
243 #define XGBE_RSS_MAX_TABLE_SIZE 256
244 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
245 #define XGBE_RSS_HASH_KEY_TYPE 1
247 /* Auto-negotiation */
248 #define XGBE_AN_MS_TIMEOUT 500
249 #define XGBE_LINK_TIMEOUT 10
251 #define XGBE_AN_INT_CMPLT 0x01
252 #define XGBE_AN_INC_LINK 0x02
253 #define XGBE_AN_PG_RCV 0x04
254 #define XGBE_AN_INT_MASK 0x07
256 /* Rate-change complete wait/retry count */
257 #define XGBE_RATECHANGE_COUNT 500
259 /* Default SerDes settings */
260 #define XGBE_SPEED_10000_BLWC 0
261 #define XGBE_SPEED_10000_CDR 0x7
262 #define XGBE_SPEED_10000_PLL 0x1
263 #define XGBE_SPEED_10000_PQ 0x12
264 #define XGBE_SPEED_10000_RATE 0x0
265 #define XGBE_SPEED_10000_TXAMP 0xa
266 #define XGBE_SPEED_10000_WORD 0x7
267 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
268 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
270 #define XGBE_SPEED_2500_BLWC 1
271 #define XGBE_SPEED_2500_CDR 0x2
272 #define XGBE_SPEED_2500_PLL 0x0
273 #define XGBE_SPEED_2500_PQ 0xa
274 #define XGBE_SPEED_2500_RATE 0x1
275 #define XGBE_SPEED_2500_TXAMP 0xf
276 #define XGBE_SPEED_2500_WORD 0x1
277 #define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3
278 #define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0
280 #define XGBE_SPEED_1000_BLWC 1
281 #define XGBE_SPEED_1000_CDR 0x2
282 #define XGBE_SPEED_1000_PLL 0x0
283 #define XGBE_SPEED_1000_PQ 0xa
284 #define XGBE_SPEED_1000_RATE 0x3
285 #define XGBE_SPEED_1000_TXAMP 0xf
286 #define XGBE_SPEED_1000_WORD 0x1
287 #define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3
288 #define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0
290 struct xgbe_prv_data;
292 struct xgbe_packet_data {
295 unsigned int attributes;
299 unsigned int rdesc_count;
302 unsigned int header_len;
303 unsigned int tcp_header_len;
304 unsigned int tcp_payload_len;
307 unsigned short vlan_ctag;
312 enum pkt_hash_types rss_hash_type;
314 unsigned int tx_packets;
315 unsigned int tx_bytes;
318 /* Common Rx and Tx descriptor mapping */
319 struct xgbe_ring_desc {
326 /* Page allocation related values */
327 struct xgbe_page_alloc {
329 unsigned int pages_len;
330 unsigned int pages_offset;
332 dma_addr_t pages_dma;
335 /* Ring entry buffer data */
336 struct xgbe_buffer_data {
337 struct xgbe_page_alloc pa;
338 struct xgbe_page_alloc pa_unmap;
341 unsigned long dma_off;
342 unsigned int dma_len;
345 /* Tx-related ring data */
346 struct xgbe_tx_ring_data {
347 unsigned int packets; /* BQL packet count */
348 unsigned int bytes; /* BQL byte count */
351 /* Rx-related ring data */
352 struct xgbe_rx_ring_data {
353 struct xgbe_buffer_data hdr; /* Header locations */
354 struct xgbe_buffer_data buf; /* Payload locations */
356 unsigned short hdr_len; /* Length of received header */
357 unsigned short len; /* Length of received packet */
360 /* Structure used to hold information related to the descriptor
361 * and the packet associated with the descriptor (always use
362 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
364 struct xgbe_ring_data {
365 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
366 dma_addr_t rdesc_dma; /* DMA address of descriptor */
368 struct sk_buff *skb; /* Virtual address of SKB */
369 dma_addr_t skb_dma; /* DMA address of SKB data */
370 unsigned int skb_dma_len; /* Length of SKB DMA area */
372 struct xgbe_tx_ring_data tx; /* Tx-related data */
373 struct xgbe_rx_ring_data rx; /* Rx-related data */
375 unsigned int mapped_as_page;
377 /* Incomplete receive save location. If the budget is exhausted
378 * or the last descriptor (last normal descriptor or a following
379 * context descriptor) has not been DMA'd yet the current state
380 * of the receive processing needs to be saved.
382 unsigned int state_saved;
391 /* Ring lock - used just for TX rings at the moment */
394 /* Per packet related information */
395 struct xgbe_packet_data packet_data;
397 /* Virtual/DMA addresses and count of allocated descriptor memory */
398 struct xgbe_ring_desc *rdesc;
399 dma_addr_t rdesc_dma;
400 unsigned int rdesc_count;
402 /* Array of descriptor data corresponding the descriptor memory
403 * (always use the XGBE_GET_DESC_DATA macro to access this data)
405 struct xgbe_ring_data *rdata;
407 /* Page allocation for RX buffers */
408 struct xgbe_page_alloc rx_hdr_pa;
409 struct xgbe_page_alloc rx_buf_pa;
412 * cur - Tx: index of descriptor to be used for current transfer
413 * Rx: index of descriptor to check for packet availability
414 * dirty - Tx: index of descriptor to check for transfer complete
415 * Rx: index of descriptor to check for buffer reallocation
420 /* Coalesce frame count used for interrupt bit setting */
421 unsigned int coalesce_count;
425 unsigned int queue_stopped;
426 unsigned int xmit_more;
427 unsigned short cur_mss;
428 unsigned short cur_vlan_ctag;
431 } ____cacheline_aligned;
433 /* Structure used to describe the descriptor rings associated with
436 struct xgbe_channel {
439 /* Address of private data area for device */
440 struct xgbe_prv_data *pdata;
442 /* Queue index and base address of queue's DMA registers */
443 unsigned int queue_index;
444 void __iomem *dma_regs;
446 /* Per channel interrupt irq number */
448 char dma_irq_name[IFNAMSIZ + 32];
450 /* Netdev related settings */
451 struct napi_struct napi;
453 unsigned int saved_ier;
455 unsigned int tx_timer_active;
456 struct timer_list tx_timer;
458 struct xgbe_ring *tx_ring;
459 struct xgbe_ring *rx_ring;
460 } ____cacheline_aligned;
470 XGMAC_INT_DMA_CH_SR_TI,
471 XGMAC_INT_DMA_CH_SR_TPS,
472 XGMAC_INT_DMA_CH_SR_TBU,
473 XGMAC_INT_DMA_CH_SR_RI,
474 XGMAC_INT_DMA_CH_SR_RBU,
475 XGMAC_INT_DMA_CH_SR_RPS,
476 XGMAC_INT_DMA_CH_SR_TI_RI,
477 XGMAC_INT_DMA_CH_SR_FBE,
481 enum xgbe_int_state {
482 XGMAC_INT_STATE_SAVE,
483 XGMAC_INT_STATE_RESTORE,
486 enum xgbe_mtl_fifo_size {
487 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
488 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
489 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
490 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
491 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
492 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
493 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
494 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
495 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
496 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
497 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
509 XGBE_AN_PAGE_RECEIVED,
510 XGBE_AN_INCOMPAT_LINK,
529 XGBE_SPEEDSET_1000_10000 = 0,
530 XGBE_SPEEDSET_2500_10000,
551 struct xgbe_mmc_stats {
555 u64 txbroadcastframes_g;
556 u64 txmulticastframes_g;
558 u64 tx65to127octets_gb;
559 u64 tx128to255octets_gb;
560 u64 tx256to511octets_gb;
561 u64 tx512to1023octets_gb;
562 u64 tx1024tomaxoctets_gb;
563 u64 txunicastframes_gb;
564 u64 txmulticastframes_gb;
565 u64 txbroadcastframes_gb;
566 u64 txunderflowerror;
576 u64 rxbroadcastframes_g;
577 u64 rxmulticastframes_g;
584 u64 rx65to127octets_gb;
585 u64 rx128to255octets_gb;
586 u64 rx256to511octets_gb;
587 u64 rx512to1023octets_gb;
588 u64 rx1024tomaxoctets_gb;
589 u64 rxunicastframes_g;
591 u64 rxoutofrangetype;
598 struct xgbe_ext_stats {
600 u64 rx_split_header_packets;
604 int (*tx_complete)(struct xgbe_ring_desc *);
606 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
607 int (*config_rx_mode)(struct xgbe_prv_data *);
609 int (*enable_rx_csum)(struct xgbe_prv_data *);
610 int (*disable_rx_csum)(struct xgbe_prv_data *);
612 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
613 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
614 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
615 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
616 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
618 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
619 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
620 int (*set_gmii_speed)(struct xgbe_prv_data *);
621 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
622 int (*set_xgmii_speed)(struct xgbe_prv_data *);
624 void (*enable_tx)(struct xgbe_prv_data *);
625 void (*disable_tx)(struct xgbe_prv_data *);
626 void (*enable_rx)(struct xgbe_prv_data *);
627 void (*disable_rx)(struct xgbe_prv_data *);
629 void (*powerup_tx)(struct xgbe_prv_data *);
630 void (*powerdown_tx)(struct xgbe_prv_data *);
631 void (*powerup_rx)(struct xgbe_prv_data *);
632 void (*powerdown_rx)(struct xgbe_prv_data *);
634 int (*init)(struct xgbe_prv_data *);
635 int (*exit)(struct xgbe_prv_data *);
637 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
638 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
639 void (*dev_xmit)(struct xgbe_channel *);
640 int (*dev_read)(struct xgbe_channel *);
641 void (*tx_desc_init)(struct xgbe_channel *);
642 void (*rx_desc_init)(struct xgbe_channel *);
643 void (*tx_desc_reset)(struct xgbe_ring_data *);
644 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
646 int (*is_last_desc)(struct xgbe_ring_desc *);
647 int (*is_context_desc)(struct xgbe_ring_desc *);
648 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
651 int (*config_tx_flow_control)(struct xgbe_prv_data *);
652 int (*config_rx_flow_control)(struct xgbe_prv_data *);
654 /* For RX coalescing */
655 int (*config_rx_coalesce)(struct xgbe_prv_data *);
656 int (*config_tx_coalesce)(struct xgbe_prv_data *);
657 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
658 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
660 /* For RX and TX threshold config */
661 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
662 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
664 /* For RX and TX Store and Forward Mode config */
665 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
666 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
668 /* For TX DMA Operate on Second Frame config */
669 int (*config_osp_mode)(struct xgbe_prv_data *);
671 /* For RX and TX PBL config */
672 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
673 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
674 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
675 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
676 int (*config_pblx8)(struct xgbe_prv_data *);
678 /* For MMC statistics */
679 void (*rx_mmc_int)(struct xgbe_prv_data *);
680 void (*tx_mmc_int)(struct xgbe_prv_data *);
681 void (*read_mmc_stats)(struct xgbe_prv_data *);
683 /* For Timestamp config */
684 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
685 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
686 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
688 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
689 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
691 /* For Data Center Bridging config */
692 void (*config_dcb_tc)(struct xgbe_prv_data *);
693 void (*config_dcb_pfc)(struct xgbe_prv_data *);
695 /* For Receive Side Scaling */
696 int (*enable_rss)(struct xgbe_prv_data *);
697 int (*disable_rss)(struct xgbe_prv_data *);
698 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
699 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
703 /* For initial PHY setup */
704 void (*phy_init)(struct xgbe_prv_data *);
706 /* For PHY support when setting device up/down */
707 int (*phy_reset)(struct xgbe_prv_data *);
708 int (*phy_start)(struct xgbe_prv_data *);
709 void (*phy_stop)(struct xgbe_prv_data *);
711 /* For PHY support while device is up */
712 void (*phy_status)(struct xgbe_prv_data *);
713 int (*phy_config_aneg)(struct xgbe_prv_data *);
716 struct xgbe_desc_if {
717 int (*alloc_ring_resources)(struct xgbe_prv_data *);
718 void (*free_ring_resources)(struct xgbe_prv_data *);
719 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
720 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
721 struct xgbe_ring_data *);
722 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
723 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
724 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
727 /* This structure contains flags that indicate what hardware features
728 * or configurations are present in the device.
730 struct xgbe_hw_features {
732 unsigned int version;
734 /* HW Feature Register0 */
735 unsigned int gmii; /* 1000 Mbps support */
736 unsigned int vlhash; /* VLAN Hash Filter */
737 unsigned int sma; /* SMA(MDIO) Interface */
738 unsigned int rwk; /* PMT remote wake-up packet */
739 unsigned int mgk; /* PMT magic packet */
740 unsigned int mmc; /* RMON module */
741 unsigned int aoe; /* ARP Offload */
742 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
743 unsigned int eee; /* Energy Efficient Ethernet */
744 unsigned int tx_coe; /* Tx Checksum Offload */
745 unsigned int rx_coe; /* Rx Checksum Offload */
746 unsigned int addn_mac; /* Additional MAC Addresses */
747 unsigned int ts_src; /* Timestamp Source */
748 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
750 /* HW Feature Register1 */
751 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
752 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
753 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
754 unsigned int dma_width; /* DMA width */
755 unsigned int dcb; /* DCB Feature */
756 unsigned int sph; /* Split Header Feature */
757 unsigned int tso; /* TCP Segmentation Offload */
758 unsigned int dma_debug; /* DMA Debug Registers */
759 unsigned int rss; /* Receive Side Scaling */
760 unsigned int tc_cnt; /* Number of Traffic Classes */
761 unsigned int hash_table_size; /* Hash Table Size */
762 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
764 /* HW Feature Register2 */
765 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
766 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
767 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
768 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
769 unsigned int pps_out_num; /* Number of PPS outputs */
770 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
773 struct xgbe_prv_data {
774 struct net_device *netdev;
775 struct platform_device *pdev;
776 struct acpi_device *adev;
779 /* ACPI or DT flag */
780 unsigned int use_acpi;
782 /* XGMAC/XPCS related mmio registers */
783 void __iomem *xgmac_regs; /* XGMAC CSRs */
784 void __iomem *xpcs_regs; /* XPCS MMD registers */
785 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
786 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
787 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
789 /* Overall device lock */
792 /* XPCS indirect addressing mutex */
793 struct mutex xpcs_mutex;
795 /* RSS addressing mutex */
796 struct mutex rss_mutex;
798 /* Flags representing xgbe_state */
799 unsigned long dev_state;
802 unsigned int per_channel_irq;
804 struct xgbe_hw_if hw_if;
805 struct xgbe_phy_if phy_if;
806 struct xgbe_desc_if desc_if;
808 /* AXI DMA settings */
809 unsigned int coherent;
810 unsigned int axdomain;
811 unsigned int arcache;
812 unsigned int awcache;
814 /* Service routine support */
815 struct workqueue_struct *dev_workqueue;
816 struct work_struct service_work;
817 struct timer_list service_timer;
819 /* Rings for Tx/Rx on a DMA channel */
820 struct xgbe_channel *channel;
821 unsigned int channel_count;
822 unsigned int tx_ring_count;
823 unsigned int tx_desc_count;
824 unsigned int rx_ring_count;
825 unsigned int rx_desc_count;
827 unsigned int tx_q_count;
828 unsigned int rx_q_count;
830 /* Tx/Rx common settings */
834 unsigned int tx_sf_mode;
835 unsigned int tx_threshold;
837 unsigned int tx_osp_mode;
840 unsigned int rx_sf_mode;
841 unsigned int rx_threshold;
844 /* Tx coalescing settings */
845 unsigned int tx_usecs;
846 unsigned int tx_frames;
848 /* Rx coalescing settings */
849 unsigned int rx_riwt;
850 unsigned int rx_usecs;
851 unsigned int rx_frames;
853 /* Current Rx buffer size */
854 unsigned int rx_buf_size;
856 /* Flow control settings */
857 unsigned int pause_autoneg;
858 unsigned int tx_pause;
859 unsigned int rx_pause;
861 /* Receive Side Scaling settings */
862 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
863 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
866 /* Netdev related settings */
867 unsigned char mac_addr[ETH_ALEN];
868 netdev_features_t netdev_features;
869 struct napi_struct napi;
870 struct xgbe_mmc_stats mmc_stats;
871 struct xgbe_ext_stats ext_stats;
873 /* Filtering support */
874 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
878 unsigned long sysclk_rate;
880 unsigned long ptpclk_rate;
882 /* Timestamp support */
883 spinlock_t tstamp_lock;
884 struct ptp_clock_info ptp_clock_info;
885 struct ptp_clock *ptp_clock;
886 struct hwtstamp_config tstamp_config;
887 struct cyclecounter tstamp_cc;
888 struct timecounter tstamp_tc;
889 unsigned int tstamp_addend;
890 struct work_struct tx_tstamp_work;
891 struct sk_buff *tx_tstamp_skb;
895 struct ieee_ets *ets;
896 struct ieee_pfc *pfc;
897 unsigned int q2tc_map[XGBE_MAX_QUEUES];
898 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
900 /* Hardware features of the device */
901 struct xgbe_hw_features hw_feat;
903 /* Device restart work structure */
904 struct work_struct restart_work;
906 /* Keeps track of power mode */
907 unsigned int power_down;
909 /* Network interface message level setting */
912 /* Current PHY settings */
913 phy_interface_t phy_mode;
917 /* MDIO/PHY related settings */
920 unsigned long link_check;
922 char an_name[IFNAMSIZ + 32];
923 struct workqueue_struct *an_workqueue;
926 struct work_struct an_irq_work;
928 unsigned int speed_set;
930 /* SerDes UEFI configurable settings.
931 * Switching between modes/speeds requires new values for some
932 * SerDes settings. The values can be supplied as device
933 * properties in array format. The first array entry is for
934 * 1GbE, second for 2.5GbE and third for 10GbE
936 u32 serdes_blwc[XGBE_SPEEDS];
937 u32 serdes_cdr_rate[XGBE_SPEEDS];
938 u32 serdes_pq_skew[XGBE_SPEEDS];
939 u32 serdes_tx_amp[XGBE_SPEEDS];
940 u32 serdes_dfe_tap_cfg[XGBE_SPEEDS];
941 u32 serdes_dfe_tap_ena[XGBE_SPEEDS];
943 /* Auto-negotiation state machine support */
944 struct mutex an_mutex;
945 enum xgbe_an an_result;
946 enum xgbe_an an_state;
947 enum xgbe_rx kr_state;
948 enum xgbe_rx kx_state;
949 struct work_struct an_work;
950 unsigned int an_supported;
951 unsigned int parallel_detect;
952 unsigned int fec_ability;
953 unsigned long an_start;
955 unsigned int lpm_ctrl; /* CTRL1 for resume */
957 #ifdef CONFIG_DEBUG_FS
958 struct dentry *xgbe_debugfs;
960 unsigned int debugfs_xgmac_reg;
962 unsigned int debugfs_xpcs_mmd;
963 unsigned int debugfs_xpcs_reg;
967 /* Function prototypes*/
969 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
970 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
971 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
972 struct net_device_ops *xgbe_get_netdev_ops(void);
973 struct ethtool_ops *xgbe_get_ethtool_ops(void);
974 #ifdef CONFIG_AMD_XGBE_DCB
975 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
978 void xgbe_ptp_register(struct xgbe_prv_data *);
979 void xgbe_ptp_unregister(struct xgbe_prv_data *);
980 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
981 unsigned int, unsigned int, unsigned int);
982 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
984 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
985 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
986 int xgbe_powerup(struct net_device *, unsigned int);
987 int xgbe_powerdown(struct net_device *, unsigned int);
988 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
989 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
991 #ifdef CONFIG_DEBUG_FS
992 void xgbe_debugfs_init(struct xgbe_prv_data *);
993 void xgbe_debugfs_exit(struct xgbe_prv_data *);
995 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
996 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
997 #endif /* CONFIG_DEBUG_FS */
999 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
1005 /* For debug prints */
1007 #define DBGPR(x...) pr_alert(x)
1009 #define DBGPR(x...) do { } while (0)
1013 #define DBGPR_MDIO(x...) pr_alert(x)
1015 #define DBGPR_MDIO(x...) do { } while (0)