2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/clocksource.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
131 #define XGBE_DRV_NAME "amd-xgbe"
132 #define XGBE_DRV_VERSION "1.0.0-a"
133 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
135 /* Descriptor related defines */
136 #define XGBE_TX_DESC_CNT 512
137 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139 #define XGBE_RX_DESC_CNT 512
141 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
143 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144 #define XGBE_RX_BUF_ALIGN 64
146 #define XGBE_MAX_DMA_CHANNELS 16
147 #define XGBE_MAX_QUEUES 16
149 /* DMA cache settings - Outer sharable, write-back, write-allocate */
150 #define XGBE_DMA_OS_AXDOMAIN 0x2
151 #define XGBE_DMA_OS_ARCACHE 0xb
152 #define XGBE_DMA_OS_AWCACHE 0xf
154 /* DMA cache settings - System, no caches used */
155 #define XGBE_DMA_SYS_AXDOMAIN 0x3
156 #define XGBE_DMA_SYS_ARCACHE 0x0
157 #define XGBE_DMA_SYS_AWCACHE 0x0
159 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
161 #define XGMAC_MIN_PACKET 60
162 #define XGMAC_STD_PACKET_MTU 1500
163 #define XGMAC_MAX_STD_PACKET 1518
164 #define XGMAC_JUMBO_PACKET_MTU 9000
165 #define XGMAC_MAX_JUMBO_PACKET 9018
167 /* MDIO bus phy name */
168 #define XGBE_PHY_NAME "amd_xgbe_phy"
171 /* Device-tree clock names */
172 #define XGBE_DMA_CLOCK "dma_clk"
173 #define XGBE_PTP_CLOCK "ptp_clk"
175 /* Timestamp support - values based on 50MHz PTP clock
178 #define XGBE_TSTAMP_SSINC 20
179 #define XGBE_TSTAMP_SNSINC 0
181 /* Driver PMT macros */
182 #define XGMAC_DRIVER_CONTEXT 1
183 #define XGMAC_IOCTL_CONTEXT 2
185 #define XGBE_FIFO_SIZE_B(x) (x)
186 #define XGBE_FIFO_SIZE_KB(x) (x * 1024)
188 #define XGBE_TC_MIN_QUANTUM 10
190 /* Helper macro for descriptor handling
191 * Always use XGBE_GET_DESC_DATA to access the descriptor data
192 * since the index is free-running and needs to be and-ed
193 * with the descriptor count value of the ring to index to
194 * the proper descriptor data.
196 #define XGBE_GET_DESC_DATA(_ring, _idx) \
198 ((_idx) & ((_ring)->rdesc_count - 1)))
200 /* Default coalescing parameters */
201 #define XGMAC_INIT_DMA_TX_USECS 50
202 #define XGMAC_INIT_DMA_TX_FRAMES 25
204 #define XGMAC_MAX_DMA_RIWT 0xff
205 #define XGMAC_INIT_DMA_RX_USECS 30
206 #define XGMAC_INIT_DMA_RX_FRAMES 25
208 /* Flow control queue count */
209 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
211 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
212 #define XGBE_MAC_HASH_TABLE_SIZE 8
214 struct xgbe_prv_data;
216 struct xgbe_packet_data {
217 unsigned int attributes;
221 unsigned int rdesc_count;
224 unsigned int header_len;
225 unsigned int tcp_header_len;
226 unsigned int tcp_payload_len;
229 unsigned short vlan_ctag;
234 /* Common Rx and Tx descriptor mapping */
235 struct xgbe_ring_desc {
242 /* Structure used to hold information related to the descriptor
243 * and the packet associated with the descriptor (always use
244 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
246 struct xgbe_ring_data {
247 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
248 dma_addr_t rdesc_dma; /* DMA address of descriptor */
250 struct sk_buff *skb; /* Virtual address of SKB */
251 dma_addr_t skb_dma; /* DMA address of SKB data */
252 unsigned int skb_dma_len; /* Length of SKB DMA area */
253 unsigned int tso_header; /* TSO header indicator */
255 unsigned short len; /* Length of received Rx packet */
257 unsigned int interrupt; /* Interrupt indicator */
259 unsigned int mapped_as_page;
261 /* Incomplete receive save location. If the budget is exhausted
262 * or the last descriptor (last normal descriptor or a following
263 * context descriptor) has not been DMA'd yet the current state
264 * of the receive processing needs to be saved.
266 unsigned int state_saved;
268 unsigned int incomplete;
269 unsigned int context_next;
277 /* Ring lock - used just for TX rings at the moment */
280 /* Per packet related information */
281 struct xgbe_packet_data packet_data;
283 /* Virtual/DMA addresses and count of allocated descriptor memory */
284 struct xgbe_ring_desc *rdesc;
285 dma_addr_t rdesc_dma;
286 unsigned int rdesc_count;
288 /* Array of descriptor data corresponding the descriptor memory
289 * (always use the XGBE_GET_DESC_DATA macro to access this data)
291 struct xgbe_ring_data *rdata;
294 * cur - Tx: index of descriptor to be used for current transfer
295 * Rx: index of descriptor to check for packet availability
296 * dirty - Tx: index of descriptor to check for transfer complete
297 * Rx: count of descriptors in which a packet has been received
298 * (used with skb_realloc_index to refresh the ring)
303 /* Coalesce frame count used for interrupt bit setting */
304 unsigned int coalesce_count;
308 unsigned int queue_stopped;
309 unsigned short cur_mss;
310 unsigned short cur_vlan_ctag;
314 unsigned int realloc_index;
315 unsigned int realloc_threshold;
318 } ____cacheline_aligned;
320 /* Structure used to describe the descriptor rings associated with
323 struct xgbe_channel {
326 /* Address of private data area for device */
327 struct xgbe_prv_data *pdata;
329 /* Queue index and base address of queue's DMA registers */
330 unsigned int queue_index;
331 void __iomem *dma_regs;
333 unsigned int saved_ier;
335 unsigned int tx_timer_active;
336 struct hrtimer tx_timer;
338 struct xgbe_ring *tx_ring;
339 struct xgbe_ring *rx_ring;
340 } ____cacheline_aligned;
343 XGMAC_INT_DMA_CH_SR_TI,
344 XGMAC_INT_DMA_CH_SR_TPS,
345 XGMAC_INT_DMA_CH_SR_TBU,
346 XGMAC_INT_DMA_CH_SR_RI,
347 XGMAC_INT_DMA_CH_SR_RBU,
348 XGMAC_INT_DMA_CH_SR_RPS,
349 XGMAC_INT_DMA_CH_SR_TI_RI,
350 XGMAC_INT_DMA_CH_SR_FBE,
354 enum xgbe_int_state {
355 XGMAC_INT_STATE_SAVE,
356 XGMAC_INT_STATE_RESTORE,
359 enum xgbe_mtl_fifo_size {
360 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
361 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
362 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
363 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
364 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
365 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
366 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
367 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
368 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
369 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
370 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
373 struct xgbe_mmc_stats {
377 u64 txbroadcastframes_g;
378 u64 txmulticastframes_g;
380 u64 tx65to127octets_gb;
381 u64 tx128to255octets_gb;
382 u64 tx256to511octets_gb;
383 u64 tx512to1023octets_gb;
384 u64 tx1024tomaxoctets_gb;
385 u64 txunicastframes_gb;
386 u64 txmulticastframes_gb;
387 u64 txbroadcastframes_gb;
388 u64 txunderflowerror;
398 u64 rxbroadcastframes_g;
399 u64 rxmulticastframes_g;
406 u64 rx65to127octets_gb;
407 u64 rx128to255octets_gb;
408 u64 rx256to511octets_gb;
409 u64 rx512to1023octets_gb;
410 u64 rx1024tomaxoctets_gb;
411 u64 rxunicastframes_g;
413 u64 rxoutofrangetype;
421 int (*tx_complete)(struct xgbe_ring_desc *);
423 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
424 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
425 int (*add_mac_addresses)(struct xgbe_prv_data *);
426 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
428 int (*enable_rx_csum)(struct xgbe_prv_data *);
429 int (*disable_rx_csum)(struct xgbe_prv_data *);
431 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
432 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
433 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
434 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
435 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
437 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
438 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
439 int (*set_gmii_speed)(struct xgbe_prv_data *);
440 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
441 int (*set_xgmii_speed)(struct xgbe_prv_data *);
443 void (*enable_tx)(struct xgbe_prv_data *);
444 void (*disable_tx)(struct xgbe_prv_data *);
445 void (*enable_rx)(struct xgbe_prv_data *);
446 void (*disable_rx)(struct xgbe_prv_data *);
448 void (*powerup_tx)(struct xgbe_prv_data *);
449 void (*powerdown_tx)(struct xgbe_prv_data *);
450 void (*powerup_rx)(struct xgbe_prv_data *);
451 void (*powerdown_rx)(struct xgbe_prv_data *);
453 int (*init)(struct xgbe_prv_data *);
454 int (*exit)(struct xgbe_prv_data *);
456 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
457 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
458 void (*pre_xmit)(struct xgbe_channel *);
459 int (*dev_read)(struct xgbe_channel *);
460 void (*tx_desc_init)(struct xgbe_channel *);
461 void (*rx_desc_init)(struct xgbe_channel *);
462 void (*rx_desc_reset)(struct xgbe_ring_data *);
463 void (*tx_desc_reset)(struct xgbe_ring_data *);
464 int (*is_last_desc)(struct xgbe_ring_desc *);
465 int (*is_context_desc)(struct xgbe_ring_desc *);
468 int (*config_tx_flow_control)(struct xgbe_prv_data *);
469 int (*config_rx_flow_control)(struct xgbe_prv_data *);
471 /* For RX coalescing */
472 int (*config_rx_coalesce)(struct xgbe_prv_data *);
473 int (*config_tx_coalesce)(struct xgbe_prv_data *);
474 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
475 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
477 /* For RX and TX threshold config */
478 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
479 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
481 /* For RX and TX Store and Forward Mode config */
482 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
483 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
485 /* For TX DMA Operate on Second Frame config */
486 int (*config_osp_mode)(struct xgbe_prv_data *);
488 /* For RX and TX PBL config */
489 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
490 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
491 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
492 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
493 int (*config_pblx8)(struct xgbe_prv_data *);
495 /* For MMC statistics */
496 void (*rx_mmc_int)(struct xgbe_prv_data *);
497 void (*tx_mmc_int)(struct xgbe_prv_data *);
498 void (*read_mmc_stats)(struct xgbe_prv_data *);
500 /* For Timestamp config */
501 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
502 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
503 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
505 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
506 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
508 /* For Data Center Bridging config */
509 void (*config_dcb_tc)(struct xgbe_prv_data *);
510 void (*config_dcb_pfc)(struct xgbe_prv_data *);
513 struct xgbe_desc_if {
514 int (*alloc_ring_resources)(struct xgbe_prv_data *);
515 void (*free_ring_resources)(struct xgbe_prv_data *);
516 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
517 void (*realloc_skb)(struct xgbe_channel *);
518 void (*unmap_skb)(struct xgbe_prv_data *, struct xgbe_ring_data *);
519 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
520 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
523 /* This structure contains flags that indicate what hardware features
524 * or configurations are present in the device.
526 struct xgbe_hw_features {
527 /* HW Feature Register0 */
528 unsigned int gmii; /* 1000 Mbps support */
529 unsigned int vlhash; /* VLAN Hash Filter */
530 unsigned int sma; /* SMA(MDIO) Interface */
531 unsigned int rwk; /* PMT remote wake-up packet */
532 unsigned int mgk; /* PMT magic packet */
533 unsigned int mmc; /* RMON module */
534 unsigned int aoe; /* ARP Offload */
535 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
536 unsigned int eee; /* Energy Efficient Ethernet */
537 unsigned int tx_coe; /* Tx Checksum Offload */
538 unsigned int rx_coe; /* Rx Checksum Offload */
539 unsigned int addn_mac; /* Additional MAC Addresses */
540 unsigned int ts_src; /* Timestamp Source */
541 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
543 /* HW Feature Register1 */
544 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
545 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
546 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
547 unsigned int dcb; /* DCB Feature */
548 unsigned int sph; /* Split Header Feature */
549 unsigned int tso; /* TCP Segmentation Offload */
550 unsigned int dma_debug; /* DMA Debug Registers */
551 unsigned int rss; /* Receive Side Scaling */
552 unsigned int tc_cnt; /* Number of Traffic Classes */
553 unsigned int hash_table_size; /* Hash Table Size */
554 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
556 /* HW Feature Register2 */
557 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
558 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
559 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
560 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
561 unsigned int pps_out_num; /* Number of PPS outputs */
562 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
565 struct xgbe_prv_data {
566 struct net_device *netdev;
567 struct platform_device *pdev;
570 /* XGMAC/XPCS related mmio registers */
571 void __iomem *xgmac_regs; /* XGMAC CSRs */
572 void __iomem *xpcs_regs; /* XPCS MMD registers */
574 /* Overall device lock */
577 /* XPCS indirect addressing mutex */
578 struct mutex xpcs_mutex;
582 struct xgbe_hw_if hw_if;
583 struct xgbe_desc_if desc_if;
585 /* AXI DMA settings */
586 unsigned int axdomain;
587 unsigned int arcache;
588 unsigned int awcache;
590 /* Rings for Tx/Rx on a DMA channel */
591 struct xgbe_channel *channel;
592 unsigned int channel_count;
593 unsigned int tx_ring_count;
594 unsigned int tx_desc_count;
595 unsigned int rx_ring_count;
596 unsigned int rx_desc_count;
598 unsigned int tx_q_count;
599 unsigned int rx_q_count;
601 /* Tx/Rx common settings */
605 unsigned int tx_sf_mode;
606 unsigned int tx_threshold;
608 unsigned int tx_osp_mode;
611 unsigned int rx_sf_mode;
612 unsigned int rx_threshold;
615 /* Tx coalescing settings */
616 unsigned int tx_usecs;
617 unsigned int tx_frames;
619 /* Rx coalescing settings */
620 unsigned int rx_riwt;
621 unsigned int rx_frames;
624 unsigned int rx_buf_size;
626 /* Flow control settings */
627 unsigned int pause_autoneg;
628 unsigned int tx_pause;
629 unsigned int rx_pause;
632 struct module *phy_module;
636 struct phy_device *phydev;
640 /* Current PHY settings */
641 phy_interface_t phy_mode;
644 unsigned int phy_tx_pause;
645 unsigned int phy_rx_pause;
647 /* Netdev related settings */
648 netdev_features_t netdev_features;
649 struct napi_struct napi;
650 struct xgbe_mmc_stats mmc_stats;
652 /* Filtering support */
653 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
659 /* Timestamp support */
660 spinlock_t tstamp_lock;
661 struct ptp_clock_info ptp_clock_info;
662 struct ptp_clock *ptp_clock;
663 struct hwtstamp_config tstamp_config;
664 struct cyclecounter tstamp_cc;
665 struct timecounter tstamp_tc;
666 unsigned int tstamp_addend;
667 struct work_struct tx_tstamp_work;
668 struct sk_buff *tx_tstamp_skb;
672 struct ieee_ets *ets;
673 struct ieee_pfc *pfc;
674 unsigned int q2tc_map[XGBE_MAX_QUEUES];
675 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
677 /* Hardware features of the device */
678 struct xgbe_hw_features hw_feat;
680 /* Device restart work structure */
681 struct work_struct restart_work;
683 /* Keeps track of power mode */
684 unsigned int power_down;
686 #ifdef CONFIG_DEBUG_FS
687 struct dentry *xgbe_debugfs;
689 unsigned int debugfs_xgmac_reg;
691 unsigned int debugfs_xpcs_mmd;
692 unsigned int debugfs_xpcs_reg;
696 /* Function prototypes*/
698 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
699 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
700 struct net_device_ops *xgbe_get_netdev_ops(void);
701 struct ethtool_ops *xgbe_get_ethtool_ops(void);
702 #ifdef CONFIG_AMD_XGBE_DCB
703 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
706 int xgbe_mdio_register(struct xgbe_prv_data *);
707 void xgbe_mdio_unregister(struct xgbe_prv_data *);
708 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
709 void xgbe_ptp_register(struct xgbe_prv_data *);
710 void xgbe_ptp_unregister(struct xgbe_prv_data *);
711 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
713 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
715 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
716 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
717 int xgbe_powerup(struct net_device *, unsigned int);
718 int xgbe_powerdown(struct net_device *, unsigned int);
719 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
720 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
722 #ifdef CONFIG_DEBUG_FS
723 void xgbe_debugfs_init(struct xgbe_prv_data *);
724 void xgbe_debugfs_exit(struct xgbe_prv_data *);
726 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
727 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
728 #endif /* CONFIG_DEBUG_FS */
730 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
732 #define XGMAC_ENABLE_TX_DESC_DUMP
733 #define XGMAC_ENABLE_RX_DESC_DUMP
736 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
738 #define XGMAC_ENABLE_TX_PKT_DUMP
739 #define XGMAC_ENABLE_RX_PKT_DUMP
742 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
748 /* For debug prints */
750 #define DBGPR(x...) pr_alert(x)
751 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
753 #define DBGPR(x...) do { } while (0)
754 #define DBGPHY_REGS(x...) do { } while (0)
758 #define DBGPR_MDIO(x...) pr_alert(x)
760 #define DBGPR_MDIO(x...) do { } while (0)