2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific
14 #ifndef HW_ATL_B0_INTERNAL_H
15 #define HW_ATL_B0_INTERNAL_H
17 #include "../aq_common.h"
19 #define HW_ATL_B0_MTU_JUMBO (16000U)
20 #define HW_ATL_B0_MTU 1514U
22 #define HW_ATL_B0_TX_RINGS 4U
23 #define HW_ATL_B0_RX_RINGS 4U
25 #define HW_ATL_B0_RINGS_MAX 32U
26 #define HW_ATL_B0_TXD_SIZE (16U)
27 #define HW_ATL_B0_RXD_SIZE (16U)
29 #define HW_ATL_B0_MAC 0U
30 #define HW_ATL_B0_MAC_MIN 1U
31 #define HW_ATL_B0_MAC_MAX 33U
33 /* UCAST/MCAST filters */
34 #define HW_ATL_B0_UCAST_FILTERS_MAX 38
35 #define HW_ATL_B0_MCAST_FILTERS_MAX 8
38 #define HW_ATL_B0_ERR_INT 8U
39 #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
41 #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
42 #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
43 #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
45 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
46 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
47 #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
48 #define HW_ATL_B0_TXD_CTL_DD (0x00100000)
49 #define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
51 #define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)
53 #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
54 #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
55 #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
56 #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
57 #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
58 #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
59 #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
61 #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
62 #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
64 #define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U
65 #define HW_ATL_B0_MPI_STATE_ADR 0x036CU
67 #define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
68 #define HW_ATL_B0_MPI_SPEED_SHIFT 16U
70 #define HW_ATL_B0_RATE_10G BIT(0)
71 #define HW_ATL_B0_RATE_5G BIT(1)
72 #define HW_ATL_B0_RATE_2G5 BIT(3)
73 #define HW_ATL_B0_RATE_1G BIT(4)
74 #define HW_ATL_B0_RATE_100M BIT(5)
76 #define HW_ATL_B0_TXBUF_MAX 160U
77 #define HW_ATL_B0_RXBUF_MAX 320U
79 #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U
80 #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U
81 #define HW_ATL_B0_RSS_HASHKEY_BITS 320U
83 #define HW_ATL_B0_TCRSS_4_8 1
84 #define HW_ATL_B0_TC_MAX 1U
85 #define HW_ATL_B0_RSS_MAX 8U
87 #define HW_ATL_B0_LRO_RXD_MAX 2U
88 #define HW_ATL_B0_RS_SLIP_ENABLED 0U
90 /* (256k -1(max pay_len) - 54(header)) */
91 #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U
93 /* (256k -1(max pay_len) - 74(header)) */
94 #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U
96 #define HW_ATL_B0_CHIP_REVISION_B0 0xA0U
97 #define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU
99 #define HW_ATL_B0_FW_SEMA_RAM 0x2U
101 #define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)
102 #define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)
104 #define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)
105 #define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)
106 #define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)
107 #define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)
108 #define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)
110 #define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */
111 #define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */
112 #define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)
113 #define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)
115 #define HW_ATL_B0_RXD_DD (0x1)
116 #define HW_ATL_B0_RXD_NCEA0 (0x1)
118 #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
119 #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
120 #define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)
121 #define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)
122 #define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)
124 #define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)
125 #define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)
126 #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)
127 #define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)
128 #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)
129 #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)
130 #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)
131 #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)
133 #define L2_FILTER_ACTION_DISCARD (0x0)
134 #define L2_FILTER_ACTION_HOST (0x1)
136 #define HW_ATL_B0_UCP_0X370_REG (0x370)
138 #define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)
140 #define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U
142 /* Hardware tx descriptor */
143 struct __packed hw_atl_txd_s {
146 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
149 /* Hardware tx context descriptor */
150 struct __packed hw_atl_txc_s {
157 /* Hardware rx descriptor */
158 struct __packed hw_atl_rxd_s {
163 /* Hardware rx descriptor writeback */
164 struct __packed hw_atl_rxd_wb_s {
173 /* HW layer capabilities */
174 static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
179 .vecs = HW_ATL_B0_RSS_MAX,
180 .tcs = HW_ATL_B0_TC_MAX,
182 .rxd_size = HW_ATL_B0_RXD_SIZE,
185 .txd_size = HW_ATL_B0_TXD_SIZE,
187 .txhwb_alignment = 4096U,
188 .tx_rings = HW_ATL_B0_TX_RINGS,
189 .rx_rings = HW_ATL_B0_RX_RINGS,
190 .hw_features = NETIF_F_HW_CSUM |
196 .hw_priv_flags = IFF_UNICAST_FLT,
197 .link_speed_msk = (HW_ATL_B0_RATE_10G |
201 HW_ATL_B0_RATE_100M),
202 .flow_control = true,
203 .mtu = HW_ATL_B0_MTU_JUMBO,
204 .mac_regs_count = 88,
205 .fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED,
208 #endif /* HW_ATL_B0_INTERNAL_H */