1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
20 /* compilation time flags */
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
26 #define DRV_MODULE_VERSION "1.70.00-0"
27 #define DRV_MODULE_RELDATE "2011/06/13"
28 #define BNX2X_BC_VER 0x040200
30 #if defined(CONFIG_DCB)
33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
35 #include "../cnic_if.h"
39 #define BNX2X_MIN_MSIX_VEC_CNT 3
40 #define BNX2X_MSIX_VEC_FP_START 2
42 #define BNX2X_MIN_MSIX_VEC_CNT 2
43 #define BNX2X_MSIX_VEC_FP_START 1
46 #include <linux/mdio.h>
48 #include "bnx2x_reg.h"
49 #include "bnx2x_fw_defs.h"
50 #include "bnx2x_hsi.h"
51 #include "bnx2x_link.h"
53 #include "bnx2x_dcb.h"
54 #include "bnx2x_stats.h"
56 /* error/debug prints */
58 #define DRV_MODULE_NAME "bnx2x"
60 /* for messages that are currently off */
61 #define BNX2X_MSG_OFF 0
62 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
64 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
67 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
69 /* regular debug print */
70 #define DP(__mask, fmt, ...) \
72 if (bp->msg_enable & (__mask)) \
73 pr_notice("[%s:%d(%s)]" fmt, \
75 bp->dev ? (bp->dev->name) : "?", \
79 #define DP_CONT(__mask, fmt, ...) \
81 if (bp->msg_enable & (__mask)) \
82 pr_cont(fmt, ##__VA_ARGS__); \
85 /* errors debug print */
86 #define BNX2X_DBG_ERR(fmt, ...) \
88 if (netif_msg_probe(bp)) \
89 pr_err("[%s:%d(%s)]" fmt, \
91 bp->dev ? (bp->dev->name) : "?", \
95 /* for errors (never masked) */
96 #define BNX2X_ERR(fmt, ...) \
98 pr_err("[%s:%d(%s)]" fmt, \
100 bp->dev ? (bp->dev->name) : "?", \
104 #define BNX2X_ERROR(fmt, ...) \
105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
108 /* before we have a dev->name use dev_info() */
109 #define BNX2X_DEV_INFO(fmt, ...) \
111 if (netif_msg_probe(bp)) \
112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
115 #ifdef BNX2X_STOP_ON_ERROR
116 void bnx2x_int_disable(struct bnx2x *bp);
117 #define bnx2x_panic() \
120 BNX2X_ERR("driver assert\n"); \
121 bnx2x_int_disable(bp); \
122 bnx2x_panic_dump(bp); \
125 #define bnx2x_panic() \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp); \
133 #define bnx2x_mc_addr(ha) ((ha)->addr)
134 #define bnx2x_uc_addr(ha) ((ha)->addr)
136 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
137 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
138 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
141 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
143 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
144 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
145 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
147 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
148 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
149 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
151 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
152 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
154 #define REG_RD_DMAE(bp, offset, valp, len32) \
156 bnx2x_read_dmae(bp, offset, len32);\
157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
160 #define REG_WR_DMAE(bp, offset, valp, len32) \
162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
167 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
168 REG_WR_DMAE(bp, offset, valp, len32)
170 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
173 bnx2x_write_big_buf_wb(bp, addr, len32); \
176 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
177 offsetof(struct shmem_region, field))
178 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
179 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
181 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
182 offsetof(struct shmem2_region, field))
183 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
184 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
185 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
186 offsetof(struct mf_cfg, field))
187 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
188 offsetof(struct mf2_cfg, field))
190 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
191 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
192 MF_CFG_ADDR(bp, field), (val))
193 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
195 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
196 (SHMEM2_RD((bp), size) > \
197 offsetof(struct shmem2_region, field)))
199 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
200 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
204 /* General SP events - stats query, cfc delete, etc */
205 #define HC_SP_INDEX_ETH_DEF_CONS 3
208 #define HC_SP_INDEX_EQ_CONS 7
210 /* FCoE L2 connection completions */
211 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
212 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
214 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
215 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
217 /* Special clients parameters */
221 #define BNX2X_FCOE_L2_RX_INDEX \
222 (&bp->def_status_blk->sp_sb.\
223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
225 #define BNX2X_FCOE_L2_TX_INDEX \
226 (&bp->def_status_blk->sp_sb.\
227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
231 * CLIDs below is a CLID for func 0, then the CLID for other
232 * functions will be calculated by the formula:
234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
238 #define BNX2X_ISCSI_ETH_CL_ID_IDX 1
239 #define BNX2X_ISCSI_ETH_CID 49
242 #define BNX2X_FCOE_ETH_CL_ID_IDX 2
243 #define BNX2X_FCOE_ETH_CID 50
245 /** Additional rings budgeting */
247 #define CNIC_PRESENT 1
248 #define FCOE_PRESENT 1
250 #define CNIC_PRESENT 0
251 #define FCOE_PRESENT 0
252 #endif /* BCM_CNIC */
253 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
255 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
256 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
261 /* defines for multiple tx priority indices */
262 #define FIRST_TX_ONLY_COS_INDEX 1
263 #define FIRST_TX_COS_INDEX 0
265 /* defines for decodeing the fastpath index and the cos index out of the
266 * transmission queue index
268 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x
270 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
271 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
273 /* rules for calculating the cids of tx-only connections */
274 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
275 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
277 /* fp index inside class of service range */
278 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
282 * 16..31 eth cos1 if applicable
283 * 32..47 eth cos2 If applicable
284 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
286 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
287 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
292 DEFINE_DMA_UNMAP_ADDR(mapping);
299 /* Set on the first BD descriptor when there is a split BD */
300 #define BNX2X_TSO_SPLIT_BD (1<<0)
305 DEFINE_DMA_UNMAP_ADDR(mapping);
309 struct doorbell_set_prod data;
313 /* dropless fc FW/HW related params */
314 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
315 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
316 ETH_MAX_AGGREGATION_QUEUES_E1 :\
317 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
318 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
319 #define FW_PREFETCH_CNT 16
320 #define DROPLESS_FC_HEADROOM 100
323 #define BCM_PAGE_SHIFT 12
324 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
325 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
326 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
328 #define PAGES_PER_SGE_SHIFT 0
329 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
330 #define SGE_PAGE_SIZE PAGE_SIZE
331 #define SGE_PAGE_SHIFT PAGE_SHIFT
332 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
334 /* SGE ring related macros */
335 #define NUM_RX_SGE_PAGES 2
336 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
337 #define NEXT_PAGE_SGE_DESC_CNT 2
338 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
339 /* RX_SGE_CNT is promised to be a power of 2 */
340 #define RX_SGE_MASK (RX_SGE_CNT - 1)
341 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
342 #define MAX_RX_SGE (NUM_RX_SGE - 1)
343 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
344 (MAX_RX_SGE_CNT - 1)) ? \
345 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
347 #define RX_SGE(x) ((x) & MAX_RX_SGE)
350 * Number of required SGEs is the sum of two:
351 * 1. Number of possible opened aggregations (next packet for
352 * these aggregations will probably consume SGE immidiatelly)
353 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
354 * after placement on BD for new TPA aggregation)
356 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
358 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
359 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
360 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
362 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
363 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
364 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
366 /* Manipulate a bit vector defined as an array of u64 */
368 /* Number of bits in one sge_mask array element */
369 #define BIT_VEC64_ELEM_SZ 64
370 #define BIT_VEC64_ELEM_SHIFT 6
371 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
374 #define __BIT_VEC64_SET_BIT(el, bit) \
376 el = ((el) | ((u64)0x1 << (bit))); \
379 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
381 el = ((el) & (~((u64)0x1 << (bit)))); \
385 #define BIT_VEC64_SET_BIT(vec64, idx) \
386 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
387 (idx) & BIT_VEC64_ELEM_MASK)
389 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
390 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
391 (idx) & BIT_VEC64_ELEM_MASK)
393 #define BIT_VEC64_TEST_BIT(vec64, idx) \
394 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
395 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
397 /* Creates a bitmask of all ones in less significant bits.
398 idx - index of the most significant bit in the created mask */
399 #define BIT_VEC64_ONES_MASK(idx) \
400 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
401 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
403 /*******************************************************/
407 /* Number of u64 elements in SGE mask array */
408 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
410 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
411 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
413 union host_hc_status_block {
414 /* pointer to fp status block e1x */
415 struct host_hc_status_block_e1x *e1x_sb;
416 /* pointer to fp status block e2 */
417 struct host_hc_status_block_e2 *e2_sb;
420 struct bnx2x_agg_info {
422 * First aggregation buffer is an skb, the following - are pages.
423 * We will preallocate the skbs for each aggregation when
424 * we open the interface and will replace the BD at the consumer
425 * with this one when we receive the TPA_START CQE in order to
426 * keep the Rx BD ring consistent.
428 struct sw_rx_bd first_buf;
430 #define BNX2X_TPA_START 1
431 #define BNX2X_TPA_STOP 2
432 #define BNX2X_TPA_ERROR 3
439 #define Q_STATS_OFFSET32(stat_name) \
440 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
442 struct bnx2x_fp_txdata {
444 struct sw_tx_bd *tx_buf_ring;
446 union eth_tx_bd_types *tx_desc_ring;
447 dma_addr_t tx_desc_mapping;
458 unsigned long tx_pkt;
465 struct bnx2x_fastpath {
466 struct bnx2x *bp; /* parent */
468 #define BNX2X_NAPI_WEIGHT 128
469 struct napi_struct napi;
470 union host_hc_status_block status_blk;
471 /* chip independed shortcuts into sb structure */
472 __le16 *sb_index_values;
473 __le16 *sb_running_index;
474 /* chip independed shortcut into rx_prods_offset memory */
475 u32 ustorm_rx_prods_offset;
479 dma_addr_t status_blk_mapping;
481 u8 max_cos; /* actual number of active tx coses */
482 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
484 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
485 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
487 struct eth_rx_bd *rx_desc_ring;
488 dma_addr_t rx_desc_mapping;
490 union eth_rx_cqe *rx_comp_ring;
491 dma_addr_t rx_comp_mapping;
494 struct eth_rx_sge *rx_sge_ring;
495 dma_addr_t rx_sge_mapping;
497 u64 sge_mask[RX_SGE_MASK_LEN];
503 u8 index; /* number in fp array */
504 u8 cl_id; /* eth client id */
506 u8 fw_sb_id; /* status block number in FW */
507 u8 igu_sb_id; /* status block number in HW */
514 /* The last maximal completed SGE */
517 unsigned long rx_pkt,
521 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
523 #ifdef BNX2X_STOP_ON_ERROR
527 struct tstorm_per_queue_stats old_tclient;
528 struct ustorm_per_queue_stats old_uclient;
529 struct xstorm_per_queue_stats old_xclient;
530 struct bnx2x_eth_q_stats eth_q_stats;
532 /* The size is calculated using the following:
533 sizeof name field from netdev structure +
535 4 (for the digits and to make it DWORD aligned) */
536 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
537 char name[FP_NAME_SIZE];
540 struct bnx2x_vlan_mac_obj mac_obj;
542 /* Queue State object */
543 struct bnx2x_queue_sp_obj q_obj;
547 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
549 /* Use 2500 as a mini-jumbo MTU for FCoE */
550 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
552 /* FCoE L2 `fastpath' entry is right after the eth entries */
553 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
554 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
555 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
556 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
557 txdata[FIRST_TX_COS_INDEX].var)
560 #define IS_ETH_FP(fp) (fp->index < \
561 BNX2X_NUM_ETH_QUEUES(fp->bp))
563 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
564 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
566 #define IS_FCOE_FP(fp) false
567 #define IS_FCOE_IDX(idx) false
572 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
573 #define RX_COPY_THRESH 92
575 #define NUM_TX_RINGS 16
576 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
577 #define NEXT_PAGE_TX_DESC_CNT 1
578 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
579 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
580 #define MAX_TX_BD (NUM_TX_BD - 1)
581 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
582 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
583 (MAX_TX_DESC_CNT - 1)) ? \
584 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
586 #define TX_BD(x) ((x) & MAX_TX_BD)
587 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
589 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
590 #define NUM_RX_RINGS 8
591 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
592 #define NEXT_PAGE_RX_DESC_CNT 2
593 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
594 #define RX_DESC_MASK (RX_DESC_CNT - 1)
595 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
596 #define MAX_RX_BD (NUM_RX_BD - 1)
597 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
599 /* dropless fc calculations for BDs
601 * Number of BDs should as number of buffers in BRB:
602 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
603 * "next" elements on each page
605 #define NUM_BD_REQ BRB_SIZE(bp)
606 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
608 #define BD_TH_LO(bp) (NUM_BD_REQ + \
609 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
611 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
613 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
615 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
616 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
617 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
618 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
619 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
620 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
623 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
624 (MAX_RX_DESC_CNT - 1)) ? \
625 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
627 #define RX_BD(x) ((x) & MAX_RX_BD)
630 * As long as CQE is X times bigger than BD entry we have to allocate X times
631 * more pages for CQ ring in order to keep it balanced with BD ring
633 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
634 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
635 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
636 #define NEXT_PAGE_RCQ_DESC_CNT 1
637 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
638 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
639 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
640 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
641 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
642 (MAX_RCQ_DESC_CNT - 1)) ? \
643 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
645 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
647 /* dropless fc calculations for RCQs
649 * Number of RCQs should be as number of buffers in BRB:
650 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
651 * "next" elements on each page
653 #define NUM_RCQ_REQ BRB_SIZE(bp)
654 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
656 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
657 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
659 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
662 /* This is needed for determining of last_max */
663 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
664 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
667 #define BNX2X_SWCID_SHIFT 17
668 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
670 /* used on a CID received from the HW */
671 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
672 #define CQE_CMD(x) (le32_to_cpu(x) >> \
673 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
675 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
676 le32_to_cpu((bd)->addr_lo))
677 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
679 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
680 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
681 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
682 #error "Min DB doorbell stride is 8"
684 #define DPM_TRIGER_TYPE 0x40
685 #define DOORBELL(bp, cid, val) \
687 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
692 /* TX CSUM helpers */
693 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
695 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
698 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
701 #define XMIT_CSUM_V4 0x1
702 #define XMIT_CSUM_V6 0x2
703 #define XMIT_CSUM_TCP 0x4
704 #define XMIT_GSO_V4 0x8
705 #define XMIT_GSO_V6 0x10
707 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
708 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
711 /* stuff added to make the code fit 80Col */
712 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
713 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
714 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
715 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
716 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
718 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
720 #define BNX2X_IP_CSUM_ERR(cqe) \
721 (!((cqe)->fast_path_cqe.status_flags & \
722 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
723 ((cqe)->fast_path_cqe.type_error_flags & \
724 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
726 #define BNX2X_L4_CSUM_ERR(cqe) \
727 (!((cqe)->fast_path_cqe.status_flags & \
728 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
729 ((cqe)->fast_path_cqe.type_error_flags & \
730 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
732 #define BNX2X_RX_CSUM_OK(cqe) \
733 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
735 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
736 (((le16_to_cpu(flags) & \
737 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
738 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
739 == PRS_FLAG_OVERETH_IPV4)
740 #define BNX2X_RX_SUM_FIX(cqe) \
741 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
744 #define FP_USB_FUNC_OFF \
745 offsetof(struct cstorm_status_block_u, func)
746 #define FP_CSB_FUNC_OFF \
747 offsetof(struct cstorm_status_block_c, func)
749 #define HC_INDEX_ETH_RX_CQ_CONS 1
751 #define HC_INDEX_OOO_TX_CQ_CONS 4
753 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
755 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
757 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
759 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
761 #define BNX2X_RX_SB_INDEX \
762 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
764 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
766 #define BNX2X_TX_SB_INDEX_COS0 \
767 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
769 /* end of fast path */
773 struct bnx2x_common {
776 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
777 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
779 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
780 #define CHIP_NUM_57710 0x164e
781 #define CHIP_NUM_57711 0x164f
782 #define CHIP_NUM_57711E 0x1650
783 #define CHIP_NUM_57712 0x1662
784 #define CHIP_NUM_57712_MF 0x1663
785 #define CHIP_NUM_57713 0x1651
786 #define CHIP_NUM_57713E 0x1652
787 #define CHIP_NUM_57800 0x168a
788 #define CHIP_NUM_57800_MF 0x16a5
789 #define CHIP_NUM_57810 0x168e
790 #define CHIP_NUM_57810_MF 0x16ae
791 #define CHIP_NUM_57840 0x168d
792 #define CHIP_NUM_57840_MF 0x16ab
793 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
794 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
795 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
796 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
797 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
798 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
799 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
800 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
801 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
802 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
803 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
804 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
806 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
807 CHIP_IS_57712_MF(bp))
808 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
809 CHIP_IS_57800_MF(bp) || \
810 CHIP_IS_57810(bp) || \
811 CHIP_IS_57810_MF(bp) || \
812 CHIP_IS_57840(bp) || \
813 CHIP_IS_57840_MF(bp))
814 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
815 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
816 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
818 #define CHIP_REV_SHIFT 12
819 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
820 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
821 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
822 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
823 /* assume maximum 5 revisions */
824 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
825 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
826 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
827 !(CHIP_REV_VAL(bp) & 0x00001000))
828 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
829 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
830 (CHIP_REV_VAL(bp) & 0x00001000))
832 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
833 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
835 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
836 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
837 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
838 (CHIP_REV_SHIFT + 1)) \
840 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
843 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
844 (CHIP_REV(bp) == CHIP_REV_Bx))
845 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
846 (CHIP_REV(bp) == CHIP_REV_Ax))
849 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
850 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
851 #define BNX2X_NVRAM_PAGE_SIZE 256
863 #define INT_BLOCK_HC 0
864 #define INT_BLOCK_IGU 1
865 #define INT_BLOCK_MODE_NORMAL 0
866 #define INT_BLOCK_MODE_BW_COMP 2
867 #define CHIP_INT_MODE_IS_NBC(bp) \
868 (!CHIP_IS_E1x(bp) && \
869 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
870 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
873 #define CHIP_4_PORT_MODE 0x0
874 #define CHIP_2_PORT_MODE 0x1
875 #define CHIP_PORT_MODE_NONE 0x2
876 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
877 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
880 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
881 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
882 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
891 u32 link_config[LINK_CONFIG_SIZE];
893 u32 supported[LINK_CONFIG_SIZE];
894 /* link settings - missing defines */
895 #define SUPPORTED_2500baseX_Full (1 << 15)
897 u32 advertising[LINK_CONFIG_SIZE];
898 /* link settings - missing defines */
899 #define ADVERTISED_2500baseX_Full (1 << 15)
903 /* used to synchronize phy accesses */
904 struct mutex phy_mutex;
909 struct nig_stats old_nig_stats;
914 #define STATS_OFFSET32(stat_name) \
915 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
919 /* slow path work-queue */
920 extern struct workqueue_struct *bnx2x_wq;
922 #define BNX2X_MAX_NUM_OF_VFS 64
923 #define BNX2X_VF_ID_INVALID 0xFF
926 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
927 * control by the number of fast-path status blocks supported by the
928 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
929 * status block represents an independent interrupts context that can
930 * serve a regular L2 networking queue. However special L2 queues such
931 * as the FCoE queue do not require a FP-SB and other components like
932 * the CNIC may consume FP-SB reducing the number of possible L2 queues
934 * If the maximum number of FP-SB available is X then:
935 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
936 * regular L2 queues is Y=X-1
937 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
938 * c. If the FCoE L2 queue is supported the actual number of L2 queues
940 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
941 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
942 * FP interrupt context for the CNIC).
943 * e. The number of HW context (CID count) is always X or X+1 if FCoE
944 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
947 /* fast-path interrupt contexts E1x */
948 #define FP_SB_MAX_E1x 16
949 /* fast-path interrupt contexts E2 */
950 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
953 struct eth_context eth;
957 /* CDU host DB constants */
958 #define CDU_ILT_PAGE_SZ_HW 3
959 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
960 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
963 #define CNIC_ISCSI_CID_MAX 256
964 #define CNIC_FCOE_CID_MAX 2048
965 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
966 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
969 #define QM_ILT_PAGE_SZ_HW 0
970 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
971 #define QM_CID_ROUND 1024
974 /* TM (timers) host DB constants */
975 #define TM_ILT_PAGE_SZ_HW 0
976 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
977 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
978 #define TM_CONN_NUM 1024
979 #define TM_ILT_SZ (8 * TM_CONN_NUM)
980 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
982 /* SRC (Searcher) host DB constants */
983 #define SRC_ILT_PAGE_SZ_HW 0
984 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
985 #define SRC_HASH_BITS 10
986 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
987 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
988 #define SRC_T2_SZ SRC_ILT_SZ
989 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
995 /* DMA memory not used in fastpath */
996 struct bnx2x_slowpath {
998 struct mac_configuration_cmd e1x;
999 struct eth_classify_rules_ramrod_data e2;
1004 struct tstorm_eth_mac_filter_config e1x;
1005 struct eth_filter_rules_ramrod_data e2;
1009 struct mac_configuration_cmd e1;
1010 struct eth_multicast_rules_ramrod_data e2;
1013 struct eth_rss_update_ramrod_data rss_rdata;
1015 /* Queue State related ramrods are always sent under rtnl_lock */
1017 struct client_init_ramrod_data init_data;
1018 struct client_update_ramrod_data update_data;
1022 struct function_start_data func_start;
1023 /* pfc configuration for DCBX ramrod */
1024 struct flow_control_configuration pfc_config;
1027 /* used by dmae command executer */
1028 struct dmae_command dmae[MAX_DMAE_C];
1031 union mac_stats mac_stats;
1032 struct nig_stats nig_stats;
1033 struct host_port_stats port_stats;
1034 struct host_func_stats func_stats;
1035 struct host_func_stats func_stats_base;
1041 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1042 #define bnx2x_sp_mapping(bp, var) \
1043 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1046 /* attn group wiring */
1047 #define MAX_DYNAMIC_ATTN_GRPS 8
1062 union cdu_context *vcxt;
1063 dma_addr_t cxt_mapping;
1071 enum bnx2x_recovery_state {
1072 BNX2X_RECOVERY_DONE,
1073 BNX2X_RECOVERY_INIT,
1074 BNX2X_RECOVERY_WAIT,
1075 BNX2X_RECOVERY_FAILED
1079 * Event queue (EQ or event ring) MC hsi
1080 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1082 #define NUM_EQ_PAGES 1
1083 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1084 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1085 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1086 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1087 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1089 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1090 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1091 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1093 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1094 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1096 #define BNX2X_EQ_INDEX \
1097 (&bp->def_status_blk->sp_sb.\
1098 index_values[HC_SP_INDEX_EQ_CONS])
1100 /* This is a data that will be used to create a link report message.
1101 * We will keep the data used for the last link report in order
1102 * to prevent reporting the same link parameters twice.
1104 struct bnx2x_link_report_data {
1105 u16 line_speed; /* Effective line speed */
1106 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1110 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1111 BNX2X_LINK_REPORT_LINK_DOWN,
1112 BNX2X_LINK_REPORT_RX_FC_ON,
1113 BNX2X_LINK_REPORT_TX_FC_ON,
1117 BNX2X_PORT_QUERY_IDX,
1119 BNX2X_FIRST_QUEUE_QUERY_IDX,
1122 struct bnx2x_fw_stats_req {
1123 struct stats_query_header hdr;
1124 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1127 struct bnx2x_fw_stats_data {
1128 struct stats_counter storm_counters;
1129 struct per_port_stats port;
1130 struct per_pf_stats pf;
1131 struct per_queue_stats queue_stats[1];
1134 /* Public slow path states */
1136 BNX2X_SP_RTNL_SETUP_TC,
1137 BNX2X_SP_RTNL_TX_TIMEOUT,
1142 /* Fields used in the tx and intr/napi performance paths
1143 * are grouped together in the beginning of the structure
1145 struct bnx2x_fastpath *fp;
1146 void __iomem *regview;
1147 void __iomem *doorbells;
1150 u8 pf_num; /* absolute PF number */
1151 u8 pfid; /* per-path PF number */
1152 int base_fw_ndsb; /**/
1153 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1154 #define BP_PORT(bp) (bp->pfid & 1)
1155 #define BP_FUNC(bp) (bp->pfid)
1156 #define BP_ABS_FUNC(bp) (bp->pf_num)
1157 #define BP_VN(bp) ((bp)->pfid >> 1)
1158 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1159 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1160 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1161 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1162 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1164 struct net_device *dev;
1165 struct pci_dev *pdev;
1167 const struct iro *iro_arr;
1168 #define IRO (bp->iro_arr)
1170 enum bnx2x_recovery_state recovery_state;
1172 struct msix_entry *msix_table;
1176 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1177 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1178 #define ETH_MIN_PACKET_SIZE 60
1179 #define ETH_MAX_PACKET_SIZE 1500
1180 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1182 /* Max supported alignment is 256 (8 shift) */
1183 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
1185 /* FW use 2 Cache lines Alignment for start packet and size */
1186 #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT)
1187 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1189 struct host_sp_status_block *def_status_blk;
1190 #define DEF_SB_IGU_ID 16
1191 #define DEF_SB_ID HC_SP_SB_ID
1195 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1197 /* slow path ring */
1198 struct eth_spe *spq;
1199 dma_addr_t spq_mapping;
1201 struct eth_spe *spq_prod_bd;
1202 struct eth_spe *spq_last_bd;
1203 __le16 *dsb_sp_prod;
1204 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1205 /* used to synchronize spq accesses */
1206 spinlock_t spq_lock;
1209 union event_ring_elem *eq_ring;
1210 dma_addr_t eq_mapping;
1214 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1218 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1220 /* Counter for completed statistics ramrods */
1223 /* End of fields used in the performance code paths */
1229 #define PCIX_FLAG (1 << 0)
1230 #define PCI_32BIT_FLAG (1 << 1)
1231 #define ONE_PORT_FLAG (1 << 2)
1232 #define NO_WOL_FLAG (1 << 3)
1233 #define USING_DAC_FLAG (1 << 4)
1234 #define USING_MSIX_FLAG (1 << 5)
1235 #define USING_MSI_FLAG (1 << 6)
1236 #define DISABLE_MSI_FLAG (1 << 7)
1237 #define TPA_ENABLE_FLAG (1 << 8)
1238 #define NO_MCP_FLAG (1 << 9)
1240 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1241 #define MF_FUNC_DIS (1 << 11)
1242 #define OWN_CNIC_IRQ (1 << 12)
1243 #define NO_ISCSI_OOO_FLAG (1 << 13)
1244 #define NO_ISCSI_FLAG (1 << 14)
1245 #define NO_FCOE_FLAG (1 << 15)
1247 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1248 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1249 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1254 struct delayed_work sp_task;
1255 struct delayed_work sp_rtnl_task;
1257 struct delayed_work period_task;
1258 struct timer_list timer;
1259 int current_interval;
1262 u16 fw_drv_pulse_wr_seq;
1265 struct link_params link_params;
1266 struct link_vars link_vars;
1268 struct bnx2x_link_report_data last_reported_link;
1270 struct mdio_if_info mdio;
1272 struct bnx2x_common common;
1273 struct bnx2x_port port;
1275 struct cmng_struct_per_port cmng;
1277 u32 mf_config[E1HVN_MAX];
1278 u32 mf2_config[E2_FUNC_MAX];
1279 u32 path_has_ovlan; /* E3 */
1282 #define IS_MF(bp) (bp->mf_mode != 0)
1283 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1284 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1290 u16 tx_quick_cons_trip_int;
1291 u16 tx_quick_cons_trip;
1295 u16 rx_quick_cons_trip_int;
1296 u16 rx_quick_cons_trip;
1299 /* Maximal coalescing timeout in us */
1300 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1305 #define BNX2X_STATE_CLOSED 0
1306 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1307 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1308 #define BNX2X_STATE_OPEN 0x3000
1309 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1310 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1312 #define BNX2X_STATE_DIAG 0xe000
1313 #define BNX2X_STATE_ERROR 0xf000
1316 #define BNX2X_MAX_PRIORITY 8
1317 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1318 #define BNX2X_MAX_COS 3
1319 #define BNX2X_MAX_TX_COS 2
1324 #define BNX2X_RX_MODE_NONE 0
1325 #define BNX2X_RX_MODE_NORMAL 1
1326 #define BNX2X_RX_MODE_ALLMULTI 2
1327 #define BNX2X_RX_MODE_PROMISC 3
1328 #define BNX2X_MAX_MULTICAST 64
1333 dma_addr_t def_status_blk_mapping;
1335 struct bnx2x_slowpath *slowpath;
1336 dma_addr_t slowpath_mapping;
1338 /* Total number of FW statistics requests */
1342 * This is a memory buffer that will contain both statistics
1343 * ramrod request and data.
1346 dma_addr_t fw_stats_mapping;
1349 * FW statistics request shortcut (points at the
1350 * beginning of fw_stats buffer).
1352 struct bnx2x_fw_stats_req *fw_stats_req;
1353 dma_addr_t fw_stats_req_mapping;
1354 int fw_stats_req_sz;
1357 * FW statistics data shortcut (points at the begining of
1358 * fw_stats buffer + fw_stats_req_sz).
1360 struct bnx2x_fw_stats_data *fw_stats_data;
1361 dma_addr_t fw_stats_data_mapping;
1362 int fw_stats_data_sz;
1364 struct hw_context context;
1366 struct bnx2x_ilt *ilt;
1367 #define BP_ILT(bp) ((bp)->ilt)
1368 #define ILT_MAX_LINES 256
1370 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1373 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1376 * Maximum CID count that might be required by the bnx2x:
1377 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1379 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1380 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1381 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1383 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1391 #define BNX2X_CNIC_FLAG_MAC_SET 1
1393 dma_addr_t t2_mapping;
1394 struct cnic_ops __rcu *cnic_ops;
1397 struct cnic_eth_dev cnic_eth_dev;
1398 union host_hc_status_block cnic_sb;
1399 dma_addr_t cnic_sb_mapping;
1400 struct eth_spe *cnic_kwq;
1401 struct eth_spe *cnic_kwq_prod;
1402 struct eth_spe *cnic_kwq_cons;
1403 struct eth_spe *cnic_kwq_last;
1404 u16 cnic_kwq_pending;
1405 u16 cnic_spq_pending;
1406 u8 fip_mac[ETH_ALEN];
1407 struct mutex cnic_mutex;
1408 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1410 /* Start index of the "special" (CNIC related) L2 cleints */
1415 /* used to synchronize dmae accesses */
1416 spinlock_t dmae_lock;
1418 /* used to protect the FW mail box */
1419 struct mutex fw_mb_mutex;
1421 /* used to synchronize stats collecting */
1424 /* used for synchronization of concurrent threads statistics handling */
1425 spinlock_t stats_lock;
1427 /* used by dmae command loader */
1428 struct dmae_command stats_dmae;
1432 struct bnx2x_eth_stats eth_stats;
1434 struct z_stream_s *strm;
1436 dma_addr_t gunzip_mapping;
1438 #define FW_BUF_SIZE 0x8000
1439 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1440 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1441 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1443 struct raw_op *init_ops;
1444 /* Init blocks offsets inside init_ops */
1445 u16 *init_ops_offsets;
1446 /* Data blob - has 32 bit granularity */
1448 u32 init_mode_flags;
1449 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1450 /* Zipped PRAM blobs - raw data */
1451 const u8 *tsem_int_table_data;
1452 const u8 *tsem_pram_data;
1453 const u8 *usem_int_table_data;
1454 const u8 *usem_pram_data;
1455 const u8 *xsem_int_table_data;
1456 const u8 *xsem_pram_data;
1457 const u8 *csem_int_table_data;
1458 const u8 *csem_pram_data;
1459 #define INIT_OPS(bp) (bp->init_ops)
1460 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1461 #define INIT_DATA(bp) (bp->init_data)
1462 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1463 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1464 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1465 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1466 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1467 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1468 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1469 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1471 #define PHY_FW_VER_LEN 20
1473 const struct firmware *firmware;
1475 /* DCB support on/off */
1477 #define BNX2X_DCB_STATE_OFF 0
1478 #define BNX2X_DCB_STATE_ON 1
1480 /* DCBX engine mode */
1482 #define BNX2X_DCBX_ENABLED_OFF 0
1483 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1484 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1485 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1487 bool dcbx_mode_uset;
1489 struct bnx2x_config_dcbx_params dcbx_config_params;
1490 struct bnx2x_dcbx_port_params dcbx_port_params;
1493 /* CAM credit pools */
1494 struct bnx2x_credit_pool_obj macs_pool;
1496 /* RX_MODE object */
1497 struct bnx2x_rx_mode_obj rx_mode_obj;
1500 struct bnx2x_mcast_obj mcast_obj;
1502 /* RSS configuration object */
1503 struct bnx2x_rss_config_obj rss_conf_obj;
1505 /* Function State controlling object */
1506 struct bnx2x_func_sp_obj func_obj;
1508 unsigned long sp_state;
1510 /* operation indication for the sp_rtnl task */
1511 unsigned long sp_rtnl_state;
1513 /* DCBX Negotation results */
1514 struct dcbx_features dcbx_local_feat;
1518 struct dcbx_features dcbx_remote_feat;
1519 u32 dcbx_remote_flags;
1523 /* multiple tx classes of service */
1526 /* priority to cos mapping */
1530 /* Tx queues may be less or equal to Rx queues */
1531 extern int num_queues;
1532 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1533 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1534 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1536 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1538 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1539 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1541 #define RSS_IPV4_CAP_MASK \
1542 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1544 #define RSS_IPV4_TCP_CAP_MASK \
1545 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1547 #define RSS_IPV6_CAP_MASK \
1548 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1550 #define RSS_IPV6_TCP_CAP_MASK \
1551 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1553 /* func init flags */
1554 #define FUNC_FLG_RSS 0x0001
1555 #define FUNC_FLG_STATS 0x0002
1556 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1557 #define FUNC_FLG_TPA 0x0008
1558 #define FUNC_FLG_SPQ 0x0010
1559 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1562 struct bnx2x_func_init_params {
1564 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1565 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1568 u16 func_id; /* abs fid */
1570 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1573 #define for_each_eth_queue(bp, var) \
1574 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1576 #define for_each_nondefault_eth_queue(bp, var) \
1577 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1579 #define for_each_queue(bp, var) \
1580 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1581 if (skip_queue(bp, var)) \
1585 /* Skip forwarding FP */
1586 #define for_each_rx_queue(bp, var) \
1587 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1588 if (skip_rx_queue(bp, var)) \
1593 #define for_each_tx_queue(bp, var) \
1594 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1595 if (skip_tx_queue(bp, var)) \
1599 #define for_each_nondefault_queue(bp, var) \
1600 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1601 if (skip_queue(bp, var)) \
1605 #define for_each_cos_in_tx_queue(fp, var) \
1606 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1609 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1611 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1614 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1616 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1618 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1624 * bnx2x_set_mac_one - configure a single MAC address
1626 * @bp: driver handle
1627 * @mac: MAC to configure
1628 * @obj: MAC object handle
1629 * @set: if 'true' add a new MAC, otherwise - delete
1630 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1631 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1633 * Configures one MAC according to provided parameters or continues the
1634 * execution of previously scheduled commands if RAMROD_CONT is set in
1637 * Returns zero if operation has successfully completed, a positive value if the
1638 * operation has been successfully scheduled and a negative - if a requested
1639 * operations has failed.
1641 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1642 struct bnx2x_vlan_mac_obj *obj, bool set,
1643 int mac_type, unsigned long *ramrod_flags);
1645 * Deletes all MACs configured for the specific MAC object.
1647 * @param bp Function driver instance
1648 * @param mac_obj MAC object to cleanup
1650 * @return zero if all MACs were cleaned
1654 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1656 * @bp: driver handle
1657 * @mac_obj: MAC object handle
1658 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1659 * @wait_for_comp: if 'true' block until completion
1661 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1663 * Returns zero if operation has successfully completed, a positive value if the
1664 * operation has been successfully scheduled and a negative - if a requested
1665 * operations has failed.
1667 int bnx2x_del_all_macs(struct bnx2x *bp,
1668 struct bnx2x_vlan_mac_obj *mac_obj,
1669 int mac_type, bool wait_for_comp);
1671 /* Init Function API */
1672 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1673 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1674 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1675 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1676 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1677 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1681 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1682 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1684 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1685 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1686 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1687 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1688 bool with_comp, u8 comp_type);
1691 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1692 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1693 u32 data_hi, u32 data_lo, int cmd_type);
1694 void bnx2x_update_coalesce(struct bnx2x *bp);
1695 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1697 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1703 val = REG_RD(bp, reg);
1704 if (val == expected)
1714 #define BNX2X_ILT_ZALLOC(x, y, size) \
1716 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1718 memset(x, 0, size); \
1721 #define BNX2X_ILT_FREE(x, y, size) \
1724 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1730 #define ILOG2(x) (ilog2((x)))
1732 #define ILT_NUM_PAGE_ENTRIES (3072)
1733 /* In 57710/11 we use whole table since we have 8 func
1734 * In 57712 we have only 4 func, but use same size per func, then only half of
1737 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1739 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1741 * the phys address is shifted right 12 bits and has an added
1742 * 1=valid bit added to the 53rd bit
1743 * then since this is a wide register(TM)
1744 * we split it into two 32 bit writes
1746 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1747 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1749 /* load/unload mode */
1750 #define LOAD_NORMAL 0
1753 #define UNLOAD_NORMAL 0
1754 #define UNLOAD_CLOSE 1
1755 #define UNLOAD_RECOVERY 2
1758 /* DMAE command defines */
1759 #define DMAE_TIMEOUT -1
1760 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1761 #define DMAE_NOT_RDY -3
1762 #define DMAE_PCI_ERR_FLAG 0x80000000
1764 #define DMAE_SRC_PCI 0
1765 #define DMAE_SRC_GRC 1
1767 #define DMAE_DST_NONE 0
1768 #define DMAE_DST_PCI 1
1769 #define DMAE_DST_GRC 2
1771 #define DMAE_COMP_PCI 0
1772 #define DMAE_COMP_GRC 1
1774 /* E2 and onward - PCI error handling in the completion */
1776 #define DMAE_COMP_REGULAR 0
1777 #define DMAE_COM_SET_ERR 1
1779 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1780 DMAE_COMMAND_SRC_SHIFT)
1781 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1782 DMAE_COMMAND_SRC_SHIFT)
1784 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1785 DMAE_COMMAND_DST_SHIFT)
1786 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1787 DMAE_COMMAND_DST_SHIFT)
1789 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1790 DMAE_COMMAND_C_DST_SHIFT)
1791 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1792 DMAE_COMMAND_C_DST_SHIFT)
1794 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1796 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1797 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1798 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1799 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1801 #define DMAE_CMD_PORT_0 0
1802 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1804 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1805 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1806 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1808 #define DMAE_SRC_PF 0
1809 #define DMAE_SRC_VF 1
1811 #define DMAE_DST_PF 0
1812 #define DMAE_DST_VF 1
1814 #define DMAE_C_SRC 0
1815 #define DMAE_C_DST 1
1817 #define DMAE_LEN32_RD_MAX 0x80
1818 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1820 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1823 #define MAX_DMAE_C_PER_PORT 8
1824 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1826 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1829 /* PCIE link and speed */
1830 #define PCICFG_LINK_WIDTH 0x1f00000
1831 #define PCICFG_LINK_WIDTH_SHIFT 20
1832 #define PCICFG_LINK_SPEED 0xf0000
1833 #define PCICFG_LINK_SPEED_SHIFT 16
1836 #define BNX2X_NUM_TESTS 7
1838 #define BNX2X_PHY_LOOPBACK 0
1839 #define BNX2X_MAC_LOOPBACK 1
1840 #define BNX2X_PHY_LOOPBACK_FAILED 1
1841 #define BNX2X_MAC_LOOPBACK_FAILED 2
1842 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1843 BNX2X_PHY_LOOPBACK_FAILED)
1846 #define STROM_ASSERT_ARRAY_SIZE 50
1849 /* must be used on a CID before placing it on a HW ring */
1850 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1851 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1854 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1855 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1859 #define MAX_SPQ_PENDING 8
1861 /* CMNG constants, as derived from system spec calculations */
1862 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1863 #define DEF_MIN_RATE 100
1864 /* resolution of the rate shaping timer - 400 usec */
1865 #define RS_PERIODIC_TIMEOUT_USEC 400
1866 /* number of bytes in single QM arbitration cycle -
1867 * coefficient for calculating the fairness timer */
1868 #define QM_ARB_BYTES 160000
1869 /* resolution of Min algorithm 1:100 */
1871 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1872 #define MIN_ABOVE_THRESH 32768
1873 /* Fairness algorithm integration time coefficient -
1874 * for calculating the actual Tfair */
1875 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1876 /* Memory of fairness algorithm . 2 cycles */
1880 #define ATTN_NIG_FOR_FUNC (1L << 8)
1881 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1882 #define GPIO_2_FUNC (1L << 10)
1883 #define GPIO_3_FUNC (1L << 11)
1884 #define GPIO_4_FUNC (1L << 12)
1885 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1886 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1887 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1888 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1889 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1890 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1892 #define ATTN_HARD_WIRED_MASK 0xff00
1893 #define ATTENTION_ID 4
1896 /* stuff added to make the code fit 80Col */
1898 #define BNX2X_PMF_LINK_ASSERT \
1899 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1901 #define BNX2X_MC_ASSERT_BITS \
1902 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1903 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1904 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1905 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1907 #define BNX2X_MCP_ASSERT \
1908 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1910 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1911 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1912 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1913 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1914 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1915 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1916 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1918 #define HW_INTERRUT_ASSERT_SET_0 \
1919 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1920 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1921 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1922 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1923 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1924 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1925 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1926 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1927 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1928 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1929 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1930 #define HW_INTERRUT_ASSERT_SET_1 \
1931 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1932 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1933 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1934 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1935 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1936 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1937 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1938 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1939 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1940 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1941 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1942 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1943 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1944 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1945 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1946 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1947 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1948 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1949 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1950 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1951 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1952 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1953 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1954 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1955 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1956 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1957 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1958 #define HW_INTERRUT_ASSERT_SET_2 \
1959 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1960 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1961 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1962 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1963 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1964 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1965 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1966 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1967 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1968 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1969 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1970 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1971 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1973 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1974 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1975 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1976 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1978 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1979 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1981 #define RSS_FLAGS(bp) \
1982 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1983 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1984 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1985 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1986 (bp->multi_mode << \
1987 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1988 #define MULTI_MASK 0x7f
1991 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
1992 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
1993 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
1994 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
1996 #define DEF_USB_IGU_INDEX_OFF \
1997 offsetof(struct cstorm_def_status_block_u, igu_index)
1998 #define DEF_CSB_IGU_INDEX_OFF \
1999 offsetof(struct cstorm_def_status_block_c, igu_index)
2000 #define DEF_XSB_IGU_INDEX_OFF \
2001 offsetof(struct xstorm_def_status_block, igu_index)
2002 #define DEF_TSB_IGU_INDEX_OFF \
2003 offsetof(struct tstorm_def_status_block, igu_index)
2005 #define DEF_USB_SEGMENT_OFF \
2006 offsetof(struct cstorm_def_status_block_u, segment)
2007 #define DEF_CSB_SEGMENT_OFF \
2008 offsetof(struct cstorm_def_status_block_c, segment)
2009 #define DEF_XSB_SEGMENT_OFF \
2010 offsetof(struct xstorm_def_status_block, segment)
2011 #define DEF_TSB_SEGMENT_OFF \
2012 offsetof(struct tstorm_def_status_block, segment)
2014 #define BNX2X_SP_DSB_INDEX \
2015 (&bp->def_status_blk->sp_sb.\
2016 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2018 #define SET_FLAG(value, mask, flag) \
2020 (value) &= ~(mask);\
2021 (value) |= ((flag) << (mask##_SHIFT));\
2024 #define GET_FLAG(value, mask) \
2025 (((value) & (mask)) >> (mask##_SHIFT))
2027 #define GET_FIELD(value, fname) \
2028 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2030 #define CAM_IS_INVALID(x) \
2031 (GET_FLAG(x.flags, \
2032 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2033 (T_ETH_MAC_COMMAND_INVALIDATE))
2035 /* Number of u32 elements in MC hash array */
2036 #define MC_HASH_SIZE 8
2037 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2038 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2041 #ifndef PXP2_REG_PXP2_INT_STS
2042 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2045 #ifndef ETH_MAX_RX_CLIENTS_E2
2046 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2049 #define BNX2X_VPD_LEN 128
2050 #define VENDOR_ID_LEN 4
2052 /* Congestion management fairness mode */
2053 #define CMNG_FNS_NONE 0
2054 #define CMNG_FNS_MINMAX 1
2056 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2057 #define HC_SEG_ACCESS_ATTN 4
2058 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2060 static const u32 dmae_reg_go_c[] = {
2061 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2062 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2063 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2064 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2067 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2068 void bnx2x_notify_link_changed(struct bnx2x *bp);
2069 #endif /* bnx2x.h */