drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29 #include "bnx2x_dump.h"
  30 #include "bnx2x_init.h"
  31 #include "bnx2x_sp.h"
  32
  33 /* Note: in the format strings below %s is replaced by the queue-name which is
  34  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  35  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  36  */
  37 #define MAX_QUEUE_NAME_LEN      4
  38 static const struct {
  39         long offset;
  40         int size;
  41         char string[ETH_GSTRING_LEN];
  42 } bnx2x_q_stats_arr[] = {
  43 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  44         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  45                                                 8, "[%s]: rx_ucast_packets" },
  46         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  47                                                 8, "[%s]: rx_mcast_packets" },
  48         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  49                                                 8, "[%s]: rx_bcast_packets" },
  50         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  51         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  52                                          4, "[%s]: rx_phy_ip_err_discards"},
  53         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  54                                          4, "[%s]: rx_skb_alloc_discard" },
  55         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  56
  57         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  58 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  59                                                 8, "[%s]: tx_ucast_packets" },
  60         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  61                                                 8, "[%s]: tx_mcast_packets" },
  62         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  63                                                 8, "[%s]: tx_bcast_packets" },
  64         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  65                                                 8, "[%s]: tpa_aggregations" },
  66         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  67                                         8, "[%s]: tpa_aggregated_frames"},
  68         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  69 };
  70
  71 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  72
  73 static const struct {
  74         long offset;
  75         int size;
  76         u32 flags;
  77 #define STATS_FLAGS_PORT                1
  78 #define STATS_FLAGS_FUNC                2
  79 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  80         char string[ETH_GSTRING_LEN];
  81 } bnx2x_stats_arr[] = {
  82 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  83                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  84         { STATS_OFFSET32(error_bytes_received_hi),
  85                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  86         { STATS_OFFSET32(total_unicast_packets_received_hi),
  87                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  88         { STATS_OFFSET32(total_multicast_packets_received_hi),
  89                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  90         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  91                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  92         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  93                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  94         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  95                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  96         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  97                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  98         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  99                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
 100 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 101                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 102         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 103                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 104         { STATS_OFFSET32(no_buff_discard_hi),
 105                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 106         { STATS_OFFSET32(mac_filter_discard),
 107                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 108         { STATS_OFFSET32(mf_tag_discard),
 109                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 110         { STATS_OFFSET32(pfc_frames_received_hi),
 111                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 112         { STATS_OFFSET32(pfc_frames_sent_hi),
 113                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 114         { STATS_OFFSET32(brb_drop_hi),
 115                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 116         { STATS_OFFSET32(brb_truncate_hi),
 117                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 118         { STATS_OFFSET32(pause_frames_received_hi),
 119                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 120         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 121                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 122         { STATS_OFFSET32(nig_timer_max),
 123                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 124 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 125                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 126         { STATS_OFFSET32(rx_skb_alloc_failed),
 127                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 128         { STATS_OFFSET32(hw_csum_err),
 129                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 130
 131         { STATS_OFFSET32(total_bytes_transmitted_hi),
 132                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 133         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 134                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 135         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 136                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 137         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 138                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 139         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 140                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 141         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 142                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 143         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 144                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 145 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 146                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 147         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 148                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 149         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 150                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 151         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 152                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 153         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 154                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 155         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 156                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 157         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 158                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 159         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 160                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 161         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 162                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 163         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 164                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 165 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 166                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 167         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 168                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 169         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 170                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 171         { STATS_OFFSET32(pause_frames_sent_hi),
 172                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 173         { STATS_OFFSET32(total_tpa_aggregations_hi),
 174                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 175         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 176                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 177         { STATS_OFFSET32(total_tpa_bytes_hi),
 178                         8, STATS_FLAGS_FUNC, "tpa_bytes"}
 179 };
 180
 181 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 182 static int bnx2x_get_port_type(struct bnx2x *bp)
 183 {
 184         int port_type;
 185         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 186         switch (bp->link_params.phy[phy_idx].media_type) {
 187         case ETH_PHY_SFP_FIBER:
 188         case ETH_PHY_XFP_FIBER:
 189         case ETH_PHY_KR:
 190         case ETH_PHY_CX4:
 191                 port_type = PORT_FIBRE;
 192                 break;
 193         case ETH_PHY_DA_TWINAX:
 194                 port_type = PORT_DA;
 195                 break;
 196         case ETH_PHY_BASE_T:
 197                 port_type = PORT_TP;
 198                 break;
 199         case ETH_PHY_NOT_PRESENT:
 200                 port_type = PORT_NONE;
 201                 break;
 202         case ETH_PHY_UNSPECIFIED:
 203         default:
 204                 port_type = PORT_OTHER;
 205                 break;
 206         }
 207         return port_type;
 208 }
 209
 210 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 211 {
 212         struct bnx2x *bp = netdev_priv(dev);
 213         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 214
 215         /* Dual Media boards present all available port types */
 216         cmd->supported = bp->port.supported[cfg_idx] |
 217                 (bp->port.supported[cfg_idx ^ 1] &
 218                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 219         cmd->advertising = bp->port.advertising[cfg_idx];
 220
 221         if ((bp->state == BNX2X_STATE_OPEN) &&
 222             !(bp->flags & MF_FUNC_DIS) &&
 223             (bp->link_vars.link_up)) {
 224                 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 225                 cmd->duplex = bp->link_vars.duplex;
 226         } else {
 227                 ethtool_cmd_speed_set(
 228                         cmd, bp->link_params.req_line_speed[cfg_idx]);
 229                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 230         }
 231
 232         if (IS_MF(bp))
 233                 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 234
 235         cmd->port = bnx2x_get_port_type(bp);
 236
 237         cmd->phy_address = bp->mdio.prtad;
 238         cmd->transceiver = XCVR_INTERNAL;
 239
 240         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 241                 cmd->autoneg = AUTONEG_ENABLE;
 242         else
 243                 cmd->autoneg = AUTONEG_DISABLE;
 244
 245         cmd->maxtxpkt = 0;
 246         cmd->maxrxpkt = 0;
 247
 248         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 249            "  supported 0x%x  advertising 0x%x  speed %u\n"
 250            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 251            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 252            cmd->cmd, cmd->supported, cmd->advertising,
 253            ethtool_cmd_speed(cmd),
 254            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 255            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 256
 257         return 0;
 258 }
 259
 260 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 261 {
 262         struct bnx2x *bp = netdev_priv(dev);
 263         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 264         u32 speed;
 265
 266         if (IS_MF_SD(bp))
 267                 return 0;
 268
 269         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 270            "  supported 0x%x  advertising 0x%x  speed %u\n"
 271            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 272            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 273            cmd->cmd, cmd->supported, cmd->advertising,
 274            ethtool_cmd_speed(cmd),
 275            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 276            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 277
 278         speed = ethtool_cmd_speed(cmd);
 279
 280         if (IS_MF_SI(bp)) {
 281                 u32 part;
 282                 u32 line_speed = bp->link_vars.line_speed;
 283
 284                 /* use 10G if no link detected */
 285                 if (!line_speed)
 286                         line_speed = 10000;
 287
 288                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 289                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 290                                        "is required, please upgrade BC\n",
 291                                        REQ_BC_VER_4_SET_MF_BW);
 292                         return -EINVAL;
 293                 }
 294
 295                 part = (speed * 100) / line_speed;
 296
 297                 if (line_speed < speed || !part) {
 298                         BNX2X_DEV_INFO("Speed setting should be in a range "
 299                                        "from 1%% to 100%% "
 300                                        "of actual line speed\n");
 301                         return -EINVAL;
 302                 }
 303
 304                 if (bp->state != BNX2X_STATE_OPEN)
 305                         /* store value for following "load" */
 306                         bp->pending_max = part;
 307                 else
 308                         bnx2x_update_max_mf_config(bp, part);
 309
 310                 return 0;
 311         }
 312
 313         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 314         old_multi_phy_config = bp->link_params.multi_phy_config;
 315         switch (cmd->port) {
 316         case PORT_TP:
 317                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 318                         break; /* no port change */
 319
 320                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 321                       bp->port.supported[1] & SUPPORTED_TP)) {
 322                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 323                         return -EINVAL;
 324                 }
 325                 bp->link_params.multi_phy_config &=
 326                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 327                 if (bp->link_params.multi_phy_config &
 328                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 329                         bp->link_params.multi_phy_config |=
 330                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 331                 else
 332                         bp->link_params.multi_phy_config |=
 333                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 334                 break;
 335         case PORT_FIBRE:
 336         case PORT_DA:
 337                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 338                         break; /* no port change */
 339
 340                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 341                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 342                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 343                         return -EINVAL;
 344                 }
 345                 bp->link_params.multi_phy_config &=
 346                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 347                 if (bp->link_params.multi_phy_config &
 348                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 349                         bp->link_params.multi_phy_config |=
 350                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 351                 else
 352                         bp->link_params.multi_phy_config |=
 353                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 354                 break;
 355         default:
 356                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 357                 return -EINVAL;
 358         }
 359         /* Save new config in case command complete successully */
 360         new_multi_phy_config = bp->link_params.multi_phy_config;
 361         /* Get the new cfg_idx */
 362         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 363         /* Restore old config in case command failed */
 364         bp->link_params.multi_phy_config = old_multi_phy_config;
 365         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 366
 367         if (cmd->autoneg == AUTONEG_ENABLE) {
 368                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 369                 if (bp->link_params.phy[EXT_PHY1].type ==
 370                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 371                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 372                                                SUPPORTED_100baseT_Full);
 373                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 374                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 375                         return -EINVAL;
 376                 }
 377
 378                 /* advertise the requested speed and duplex if supported */
 379                 if (cmd->advertising & ~an_supported_speed) {
 380                         DP(NETIF_MSG_LINK, "Advertisement parameters "
 381                                            "are not supported\n");
 382                         return -EINVAL;
 383                 }
 384
 385                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 386                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 387                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 388                                          cmd->advertising);
 389                 if (cmd->advertising) {
 390
 391                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 392                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 393                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 394                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 395                         }
 396                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 397                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 398                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 399
 400                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 401                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 402                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 403
 404                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 405                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 406                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 407                         }
 408                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 409                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 410                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 411                         }
 412                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 413                                                 ADVERTISED_1000baseKX_Full))
 414                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 415                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 416
 417                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 418                                                 ADVERTISED_10000baseKX4_Full |
 419                                                 ADVERTISED_10000baseKR_Full))
 420                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 421                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 422                 }
 423         } else { /* forced speed */
 424                 /* advertise the requested speed and duplex if supported */
 425                 switch (speed) {
 426                 case SPEED_10:
 427                         if (cmd->duplex == DUPLEX_FULL) {
 428                                 if (!(bp->port.supported[cfg_idx] &
 429                                       SUPPORTED_10baseT_Full)) {
 430                                         DP(NETIF_MSG_LINK,
 431                                            "10M full not supported\n");
 432                                         return -EINVAL;
 433                                 }
 434
 435                                 advertising = (ADVERTISED_10baseT_Full |
 436                                                ADVERTISED_TP);
 437                         } else {
 438                                 if (!(bp->port.supported[cfg_idx] &
 439                                       SUPPORTED_10baseT_Half)) {
 440                                         DP(NETIF_MSG_LINK,
 441                                            "10M half not supported\n");
 442                                         return -EINVAL;
 443                                 }
 444
 445                                 advertising = (ADVERTISED_10baseT_Half |
 446                                                ADVERTISED_TP);
 447                         }
 448                         break;
 449
 450                 case SPEED_100:
 451                         if (cmd->duplex == DUPLEX_FULL) {
 452                                 if (!(bp->port.supported[cfg_idx] &
 453                                                 SUPPORTED_100baseT_Full)) {
 454                                         DP(NETIF_MSG_LINK,
 455                                            "100M full not supported\n");
 456                                         return -EINVAL;
 457                                 }
 458
 459                                 advertising = (ADVERTISED_100baseT_Full |
 460                                                ADVERTISED_TP);
 461                         } else {
 462                                 if (!(bp->port.supported[cfg_idx] &
 463                                                 SUPPORTED_100baseT_Half)) {
 464                                         DP(NETIF_MSG_LINK,
 465                                            "100M half not supported\n");
 466                                         return -EINVAL;
 467                                 }
 468
 469                                 advertising = (ADVERTISED_100baseT_Half |
 470                                                ADVERTISED_TP);
 471                         }
 472                         break;
 473
 474                 case SPEED_1000:
 475                         if (cmd->duplex != DUPLEX_FULL) {
 476                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 477                                 return -EINVAL;
 478                         }
 479
 480                         if (!(bp->port.supported[cfg_idx] &
 481                               SUPPORTED_1000baseT_Full)) {
 482                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 483                                 return -EINVAL;
 484                         }
 485
 486                         advertising = (ADVERTISED_1000baseT_Full |
 487                                        ADVERTISED_TP);
 488                         break;
 489
 490                 case SPEED_2500:
 491                         if (cmd->duplex != DUPLEX_FULL) {
 492                                 DP(NETIF_MSG_LINK,
 493                                    "2.5G half not supported\n");
 494                                 return -EINVAL;
 495                         }
 496
 497                         if (!(bp->port.supported[cfg_idx]
 498                               & SUPPORTED_2500baseX_Full)) {
 499                                 DP(NETIF_MSG_LINK,
 500                                    "2.5G full not supported\n");
 501                                 return -EINVAL;
 502                         }
 503
 504                         advertising = (ADVERTISED_2500baseX_Full |
 505                                        ADVERTISED_TP);
 506                         break;
 507
 508                 case SPEED_10000:
 509                         if (cmd->duplex != DUPLEX_FULL) {
 510                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 511                                 return -EINVAL;
 512                         }
 513
 514                         if (!(bp->port.supported[cfg_idx]
 515                               & SUPPORTED_10000baseT_Full)) {
 516                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 517                                 return -EINVAL;
 518                         }
 519
 520                         advertising = (ADVERTISED_10000baseT_Full |
 521                                        ADVERTISED_FIBRE);
 522                         break;
 523
 524                 default:
 525                         DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
 526                         return -EINVAL;
 527                 }
 528
 529                 bp->link_params.req_line_speed[cfg_idx] = speed;
 530                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 531                 bp->port.advertising[cfg_idx] = advertising;
 532         }
 533
 534         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 535            "  req_duplex %d  advertising 0x%x\n",
 536            bp->link_params.req_line_speed[cfg_idx],
 537            bp->link_params.req_duplex[cfg_idx],
 538            bp->port.advertising[cfg_idx]);
 539
 540         /* Set new config */
 541         bp->link_params.multi_phy_config = new_multi_phy_config;
 542         if (netif_running(dev)) {
 543                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 544                 bnx2x_link_set(bp);
 545         }
 546
 547         return 0;
 548 }
 549
 550 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 551 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 552 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 553 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 554 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 555
 556 static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
 557                                        const struct reg_addr *reg_info)
 558 {
 559         if (CHIP_IS_E1(bp))
 560                 return IS_E1_ONLINE(reg_info->info);
 561         else if (CHIP_IS_E1H(bp))
 562                 return IS_E1H_ONLINE(reg_info->info);
 563         else if (CHIP_IS_E2(bp))
 564                 return IS_E2_ONLINE(reg_info->info);
 565         else if (CHIP_IS_E3A0(bp))
 566                 return IS_E3_ONLINE(reg_info->info);
 567         else if (CHIP_IS_E3B0(bp))
 568                 return IS_E3B0_ONLINE(reg_info->info);
 569         else
 570                 return false;
 571 }
 572
 573 /******* Paged registers info selectors ********/
 574 static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 575 {
 576         if (CHIP_IS_E2(bp))
 577                 return page_vals_e2;
 578         else if (CHIP_IS_E3(bp))
 579                 return page_vals_e3;
 580         else
 581                 return NULL;
 582 }
 583
 584 static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 585 {
 586         if (CHIP_IS_E2(bp))
 587                 return PAGE_MODE_VALUES_E2;
 588         else if (CHIP_IS_E3(bp))
 589                 return PAGE_MODE_VALUES_E3;
 590         else
 591                 return 0;
 592 }
 593
 594 static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 595 {
 596         if (CHIP_IS_E2(bp))
 597                 return page_write_regs_e2;
 598         else if (CHIP_IS_E3(bp))
 599                 return page_write_regs_e3;
 600         else
 601                 return NULL;
 602 }
 603
 604 static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 605 {
 606         if (CHIP_IS_E2(bp))
 607                 return PAGE_WRITE_REGS_E2;
 608         else if (CHIP_IS_E3(bp))
 609                 return PAGE_WRITE_REGS_E3;
 610         else
 611                 return 0;
 612 }
 613
 614 static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 615 {
 616         if (CHIP_IS_E2(bp))
 617                 return page_read_regs_e2;
 618         else if (CHIP_IS_E3(bp))
 619                 return page_read_regs_e3;
 620         else
 621                 return NULL;
 622 }
 623
 624 static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 625 {
 626         if (CHIP_IS_E2(bp))
 627                 return PAGE_READ_REGS_E2;
 628         else if (CHIP_IS_E3(bp))
 629                 return PAGE_READ_REGS_E3;
 630         else
 631                 return 0;
 632 }
 633
 634 static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
 635 {
 636         int num_pages = __bnx2x_get_page_reg_num(bp);
 637         int page_write_num = __bnx2x_get_page_write_num(bp);
 638         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 639         int page_read_num = __bnx2x_get_page_read_num(bp);
 640         int regdump_len = 0;
 641         int i, j, k;
 642
 643         for (i = 0; i < REGS_COUNT; i++)
 644                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 645                         regdump_len += reg_addrs[i].size;
 646
 647         for (i = 0; i < num_pages; i++)
 648                 for (j = 0; j < page_write_num; j++)
 649                         for (k = 0; k < page_read_num; k++)
 650                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 651                                         regdump_len += page_read_addr[k].size;
 652
 653         return regdump_len;
 654 }
 655
 656 static int bnx2x_get_regs_len(struct net_device *dev)
 657 {
 658         struct bnx2x *bp = netdev_priv(dev);
 659         int regdump_len = 0;
 660
 661         regdump_len = __bnx2x_get_regs_len(bp);
 662         regdump_len *= 4;
 663         regdump_len += sizeof(struct dump_hdr);
 664
 665         return regdump_len;
 666 }
 667
 668 /**
 669  * bnx2x_read_pages_regs - read "paged" registers
 670  *
 671  * @bp          device handle
 672  * @p           output buffer
 673  *
 674  * Reads "paged" memories: memories that may only be read by first writing to a
 675  * specific address ("write address") and then reading from a specific address
 676  * ("read address"). There may be more than one write address per "page" and
 677  * more than one read address per write address.
 678  */
 679 static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 680 {
 681         u32 i, j, k, n;
 682         /* addresses of the paged registers */
 683         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 684         /* number of paged registers */
 685         int num_pages = __bnx2x_get_page_reg_num(bp);
 686         /* write addresses */
 687         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 688         /* number of write addresses */
 689         int write_num = __bnx2x_get_page_write_num(bp);
 690         /* read addresses info */
 691         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 692         /* number of read addresses */
 693         int read_num = __bnx2x_get_page_read_num(bp);
 694
 695         for (i = 0; i < num_pages; i++) {
 696                 for (j = 0; j < write_num; j++) {
 697                         REG_WR(bp, write_addr[j], page_addr[i]);
 698                         for (k = 0; k < read_num; k++)
 699                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 700                                         for (n = 0; n <
 701                                               read_addr[k].size; n++)
 702                                                 *p++ = REG_RD(bp,
 703                                                        read_addr[k].addr + n*4);
 704                 }
 705         }
 706 }
 707
 708 static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 709 {
 710         u32 i, j;
 711
 712         /* Read the regular registers */
 713         for (i = 0; i < REGS_COUNT; i++)
 714                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 715                         for (j = 0; j < reg_addrs[i].size; j++)
 716                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 717
 718         /* Read "paged" registes */
 719         bnx2x_read_pages_regs(bp, p);
 720 }
 721
 722 static void bnx2x_get_regs(struct net_device *dev,
 723                            struct ethtool_regs *regs, void *_p)
 724 {
 725         u32 *p = _p;
 726         struct bnx2x *bp = netdev_priv(dev);
 727         struct dump_hdr dump_hdr = {0};
 728
 729         regs->version = 0;
 730         memset(p, 0, regs->len);
 731
 732         if (!netif_running(bp->dev))
 733                 return;
 734
 735         /* Disable parity attentions as long as following dump may
 736          * cause false alarms by reading never written registers. We
 737          * will re-enable parity attentions right after the dump.
 738          */
 739         bnx2x_disable_blocks_parity(bp);
 740
 741         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 742         dump_hdr.dump_sign = dump_sign_all;
 743         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 744         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 745         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 746         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 747
 748         if (CHIP_IS_E1(bp))
 749                 dump_hdr.info = RI_E1_ONLINE;
 750         else if (CHIP_IS_E1H(bp))
 751                 dump_hdr.info = RI_E1H_ONLINE;
 752         else if (!CHIP_IS_E1x(bp))
 753                 dump_hdr.info = RI_E2_ONLINE |
 754                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 755
 756         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 757         p += dump_hdr.hdr_size + 1;
 758
 759         /* Actually read the registers */
 760         __bnx2x_get_regs(bp, p);
 761
 762         /* Re-enable parity attentions */
 763         bnx2x_clear_blocks_parity(bp);
 764         bnx2x_enable_blocks_parity(bp);
 765 }
 766
 767 static void bnx2x_get_drvinfo(struct net_device *dev,
 768                               struct ethtool_drvinfo *info)
 769 {
 770         struct bnx2x *bp = netdev_priv(dev);
 771         u8 phy_fw_ver[PHY_FW_VER_LEN];
 772
 773         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
 774         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
 775
 776         phy_fw_ver[0] = '\0';
 777         if (bp->port.pmf) {
 778                 bnx2x_acquire_phy_lock(bp);
 779                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 780                                              (bp->state != BNX2X_STATE_CLOSED),
 781                                              phy_fw_ver, PHY_FW_VER_LEN);
 782                 bnx2x_release_phy_lock(bp);
 783         }
 784
 785         strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
 786         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 787                  "bc %d.%d.%d%s%s",
 788                  (bp->common.bc_ver & 0xff0000) >> 16,
 789                  (bp->common.bc_ver & 0xff00) >> 8,
 790                  (bp->common.bc_ver & 0xff),
 791                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 792         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
 793         info->n_stats = BNX2X_NUM_STATS;
 794         info->testinfo_len = BNX2X_NUM_TESTS;
 795         info->eedump_len = bp->common.flash_size;
 796         info->regdump_len = bnx2x_get_regs_len(dev);
 797 }
 798
 799 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 800 {
 801         struct bnx2x *bp = netdev_priv(dev);
 802
 803         if (bp->flags & NO_WOL_FLAG) {
 804                 wol->supported = 0;
 805                 wol->wolopts = 0;
 806         } else {
 807                 wol->supported = WAKE_MAGIC;
 808                 if (bp->wol)
 809                         wol->wolopts = WAKE_MAGIC;
 810                 else
 811                         wol->wolopts = 0;
 812         }
 813         memset(&wol->sopass, 0, sizeof(wol->sopass));
 814 }
 815
 816 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 817 {
 818         struct bnx2x *bp = netdev_priv(dev);
 819
 820         if (wol->wolopts & ~WAKE_MAGIC)
 821                 return -EINVAL;
 822
 823         if (wol->wolopts & WAKE_MAGIC) {
 824                 if (bp->flags & NO_WOL_FLAG)
 825                         return -EINVAL;
 826
 827                 bp->wol = 1;
 828         } else
 829                 bp->wol = 0;
 830
 831         return 0;
 832 }
 833
 834 static u32 bnx2x_get_msglevel(struct net_device *dev)
 835 {
 836         struct bnx2x *bp = netdev_priv(dev);
 837
 838         return bp->msg_enable;
 839 }
 840
 841 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 842 {
 843         struct bnx2x *bp = netdev_priv(dev);
 844
 845         if (capable(CAP_NET_ADMIN)) {
 846                 /* dump MCP trace */
 847                 if (level & BNX2X_MSG_MCP)
 848                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 849                 bp->msg_enable = level;
 850         }
 851 }
 852
 853 static int bnx2x_nway_reset(struct net_device *dev)
 854 {
 855         struct bnx2x *bp = netdev_priv(dev);
 856
 857         if (!bp->port.pmf)
 858                 return 0;
 859
 860         if (netif_running(dev)) {
 861                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 862                 bnx2x_link_set(bp);
 863         }
 864
 865         return 0;
 866 }
 867
 868 static u32 bnx2x_get_link(struct net_device *dev)
 869 {
 870         struct bnx2x *bp = netdev_priv(dev);
 871
 872         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 873                 return 0;
 874
 875         return bp->link_vars.link_up;
 876 }
 877
 878 static int bnx2x_get_eeprom_len(struct net_device *dev)
 879 {
 880         struct bnx2x *bp = netdev_priv(dev);
 881
 882         return bp->common.flash_size;
 883 }
 884
 885 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 886 {
 887         int port = BP_PORT(bp);
 888         int count, i;
 889         u32 val = 0;
 890
 891         /* adjust timeout for emulation/FPGA */
 892         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 893         if (CHIP_REV_IS_SLOW(bp))
 894                 count *= 100;
 895
 896         /* request access to nvram interface */
 897         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 898                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 899
 900         for (i = 0; i < count*10; i++) {
 901                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 902                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 903                         break;
 904
 905                 udelay(5);
 906         }
 907
 908         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 909                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 910                 return -EBUSY;
 911         }
 912
 913         return 0;
 914 }
 915
 916 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 917 {
 918         int port = BP_PORT(bp);
 919         int count, i;
 920         u32 val = 0;
 921
 922         /* adjust timeout for emulation/FPGA */
 923         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 924         if (CHIP_REV_IS_SLOW(bp))
 925                 count *= 100;
 926
 927         /* relinquish nvram interface */
 928         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 929                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 930
 931         for (i = 0; i < count*10; i++) {
 932                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 933                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 934                         break;
 935
 936                 udelay(5);
 937         }
 938
 939         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 940                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 941                 return -EBUSY;
 942         }
 943
 944         return 0;
 945 }
 946
 947 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 948 {
 949         u32 val;
 950
 951         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 952
 953         /* enable both bits, even on read */
 954         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 955                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 956                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 957 }
 958
 959 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 960 {
 961         u32 val;
 962
 963         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 964
 965         /* disable both bits, even after read */
 966         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 967                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 968                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 969 }
 970
 971 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 972                                   u32 cmd_flags)
 973 {
 974         int count, i, rc;
 975         u32 val;
 976
 977         /* build the command word */
 978         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 979
 980         /* need to clear DONE bit separately */
 981         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 982
 983         /* address of the NVRAM to read from */
 984         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 985                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 986
 987         /* issue a read command */
 988         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 989
 990         /* adjust timeout for emulation/FPGA */
 991         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 992         if (CHIP_REV_IS_SLOW(bp))
 993                 count *= 100;
 994
 995         /* wait for completion */
 996         *ret_val = 0;
 997         rc = -EBUSY;
 998         for (i = 0; i < count; i++) {
 999                 udelay(5);
1000                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1001
1002                 if (val & MCPR_NVM_COMMAND_DONE) {
1003                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1004                         /* we read nvram data in cpu order
1005                          * but ethtool sees it as an array of bytes
1006                          * converting to big-endian will do the work */
1007                         *ret_val = cpu_to_be32(val);
1008                         rc = 0;
1009                         break;
1010                 }
1011         }
1012
1013         return rc;
1014 }
1015
1016 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1017                             int buf_size)
1018 {
1019         int rc;
1020         u32 cmd_flags;
1021         __be32 val;
1022
1023         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1024                 DP(BNX2X_MSG_NVM,
1025                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1026                    offset, buf_size);
1027                 return -EINVAL;
1028         }
1029
1030         if (offset + buf_size > bp->common.flash_size) {
1031                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1032                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1033                    offset, buf_size, bp->common.flash_size);
1034                 return -EINVAL;
1035         }
1036
1037         /* request access to nvram interface */
1038         rc = bnx2x_acquire_nvram_lock(bp);
1039         if (rc)
1040                 return rc;
1041
1042         /* enable access to nvram interface */
1043         bnx2x_enable_nvram_access(bp);
1044
1045         /* read the first word(s) */
1046         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1047         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1048                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1049                 memcpy(ret_buf, &val, 4);
1050
1051                 /* advance to the next dword */
1052                 offset += sizeof(u32);
1053                 ret_buf += sizeof(u32);
1054                 buf_size -= sizeof(u32);
1055                 cmd_flags = 0;
1056         }
1057
1058         if (rc == 0) {
1059                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1060                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1061                 memcpy(ret_buf, &val, 4);
1062         }
1063
1064         /* disable access to nvram interface */
1065         bnx2x_disable_nvram_access(bp);
1066         bnx2x_release_nvram_lock(bp);
1067
1068         return rc;
1069 }
1070
1071 static int bnx2x_get_eeprom(struct net_device *dev,
1072                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1073 {
1074         struct bnx2x *bp = netdev_priv(dev);
1075         int rc;
1076
1077         if (!netif_running(dev))
1078                 return -EAGAIN;
1079
1080         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1081            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1082            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1083            eeprom->len, eeprom->len);
1084
1085         /* parameters already validated in ethtool_get_eeprom */
1086
1087         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1088
1089         return rc;
1090 }
1091
1092 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1093                                    u32 cmd_flags)
1094 {
1095         int count, i, rc;
1096
1097         /* build the command word */
1098         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1099
1100         /* need to clear DONE bit separately */
1101         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1102
1103         /* write the data */
1104         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1105
1106         /* address of the NVRAM to write to */
1107         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1108                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1109
1110         /* issue the write command */
1111         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1112
1113         /* adjust timeout for emulation/FPGA */
1114         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1115         if (CHIP_REV_IS_SLOW(bp))
1116                 count *= 100;
1117
1118         /* wait for completion */
1119         rc = -EBUSY;
1120         for (i = 0; i < count; i++) {
1121                 udelay(5);
1122                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1123                 if (val & MCPR_NVM_COMMAND_DONE) {
1124                         rc = 0;
1125                         break;
1126                 }
1127         }
1128
1129         return rc;
1130 }
1131
1132 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1133
1134 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1135                               int buf_size)
1136 {
1137         int rc;
1138         u32 cmd_flags;
1139         u32 align_offset;
1140         __be32 val;
1141
1142         if (offset + buf_size > bp->common.flash_size) {
1143                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1144                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1145                    offset, buf_size, bp->common.flash_size);
1146                 return -EINVAL;
1147         }
1148
1149         /* request access to nvram interface */
1150         rc = bnx2x_acquire_nvram_lock(bp);
1151         if (rc)
1152                 return rc;
1153
1154         /* enable access to nvram interface */
1155         bnx2x_enable_nvram_access(bp);
1156
1157         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1158         align_offset = (offset & ~0x03);
1159         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1160
1161         if (rc == 0) {
1162                 val &= ~(0xff << BYTE_OFFSET(offset));
1163                 val |= (*data_buf << BYTE_OFFSET(offset));
1164
1165                 /* nvram data is returned as an array of bytes
1166                  * convert it back to cpu order */
1167                 val = be32_to_cpu(val);
1168
1169                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1170                                              cmd_flags);
1171         }
1172
1173         /* disable access to nvram interface */
1174         bnx2x_disable_nvram_access(bp);
1175         bnx2x_release_nvram_lock(bp);
1176
1177         return rc;
1178 }
1179
1180 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1181                              int buf_size)
1182 {
1183         int rc;
1184         u32 cmd_flags;
1185         u32 val;
1186         u32 written_so_far;
1187
1188         if (buf_size == 1)      /* ethtool */
1189                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1190
1191         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1192                 DP(BNX2X_MSG_NVM,
1193                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1194                    offset, buf_size);
1195                 return -EINVAL;
1196         }
1197
1198         if (offset + buf_size > bp->common.flash_size) {
1199                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1200                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1201                    offset, buf_size, bp->common.flash_size);
1202                 return -EINVAL;
1203         }
1204
1205         /* request access to nvram interface */
1206         rc = bnx2x_acquire_nvram_lock(bp);
1207         if (rc)
1208                 return rc;
1209
1210         /* enable access to nvram interface */
1211         bnx2x_enable_nvram_access(bp);
1212
1213         written_so_far = 0;
1214         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1215         while ((written_so_far < buf_size) && (rc == 0)) {
1216                 if (written_so_far == (buf_size - sizeof(u32)))
1217                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1218                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1219                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1220                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1221                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1222
1223                 memcpy(&val, data_buf, 4);
1224
1225                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1226
1227                 /* advance to the next dword */
1228                 offset += sizeof(u32);
1229                 data_buf += sizeof(u32);
1230                 written_so_far += sizeof(u32);
1231                 cmd_flags = 0;
1232         }
1233
1234         /* disable access to nvram interface */
1235         bnx2x_disable_nvram_access(bp);
1236         bnx2x_release_nvram_lock(bp);
1237
1238         return rc;
1239 }
1240
1241 static int bnx2x_set_eeprom(struct net_device *dev,
1242                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1243 {
1244         struct bnx2x *bp = netdev_priv(dev);
1245         int port = BP_PORT(bp);
1246         int rc = 0;
1247         u32 ext_phy_config;
1248         if (!netif_running(dev))
1249                 return -EAGAIN;
1250
1251         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1252            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1253            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1254            eeprom->len, eeprom->len);
1255
1256         /* parameters already validated in ethtool_set_eeprom */
1257
1258         /* PHY eeprom can be accessed only by the PMF */
1259         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1260             !bp->port.pmf)
1261                 return -EINVAL;
1262
1263         ext_phy_config =
1264                 SHMEM_RD(bp,
1265                          dev_info.port_hw_config[port].external_phy_config);
1266
1267         if (eeprom->magic == 0x50485950) {
1268                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1269                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1270
1271                 bnx2x_acquire_phy_lock(bp);
1272                 rc |= bnx2x_link_reset(&bp->link_params,
1273                                        &bp->link_vars, 0);
1274                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1275                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1276                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1277                                        MISC_REGISTERS_GPIO_HIGH, port);
1278                 bnx2x_release_phy_lock(bp);
1279                 bnx2x_link_report(bp);
1280
1281         } else if (eeprom->magic == 0x50485952) {
1282                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1283                 if (bp->state == BNX2X_STATE_OPEN) {
1284                         bnx2x_acquire_phy_lock(bp);
1285                         rc |= bnx2x_link_reset(&bp->link_params,
1286                                                &bp->link_vars, 1);
1287
1288                         rc |= bnx2x_phy_init(&bp->link_params,
1289                                              &bp->link_vars);
1290                         bnx2x_release_phy_lock(bp);
1291                         bnx2x_calc_fc_adv(bp);
1292                 }
1293         } else if (eeprom->magic == 0x53985943) {
1294                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1295                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1296                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1297
1298                         /* DSP Remove Download Mode */
1299                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1300                                        MISC_REGISTERS_GPIO_LOW, port);
1301
1302                         bnx2x_acquire_phy_lock(bp);
1303
1304                         bnx2x_sfx7101_sp_sw_reset(bp,
1305                                                 &bp->link_params.phy[EXT_PHY1]);
1306
1307                         /* wait 0.5 sec to allow it to run */
1308                         msleep(500);
1309                         bnx2x_ext_phy_hw_reset(bp, port);
1310                         msleep(500);
1311                         bnx2x_release_phy_lock(bp);
1312                 }
1313         } else
1314                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1315
1316         return rc;
1317 }
1318
1319 static int bnx2x_get_coalesce(struct net_device *dev,
1320                               struct ethtool_coalesce *coal)
1321 {
1322         struct bnx2x *bp = netdev_priv(dev);
1323
1324         memset(coal, 0, sizeof(struct ethtool_coalesce));
1325
1326         coal->rx_coalesce_usecs = bp->rx_ticks;
1327         coal->tx_coalesce_usecs = bp->tx_ticks;
1328
1329         return 0;
1330 }
1331
1332 static int bnx2x_set_coalesce(struct net_device *dev,
1333                               struct ethtool_coalesce *coal)
1334 {
1335         struct bnx2x *bp = netdev_priv(dev);
1336
1337         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1338         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1339                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1340
1341         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1342         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1343                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1344
1345         if (netif_running(dev))
1346                 bnx2x_update_coalesce(bp);
1347
1348         return 0;
1349 }
1350
1351 static void bnx2x_get_ringparam(struct net_device *dev,
1352                                 struct ethtool_ringparam *ering)
1353 {
1354         struct bnx2x *bp = netdev_priv(dev);
1355
1356         ering->rx_max_pending = MAX_RX_AVAIL;
1357
1358         if (bp->rx_ring_size)
1359                 ering->rx_pending = bp->rx_ring_size;
1360         else
1361                 ering->rx_pending = MAX_RX_AVAIL;
1362
1363         ering->tx_max_pending = MAX_TX_AVAIL;
1364         ering->tx_pending = bp->tx_ring_size;
1365 }
1366
1367 static int bnx2x_set_ringparam(struct net_device *dev,
1368                                struct ethtool_ringparam *ering)
1369 {
1370         struct bnx2x *bp = netdev_priv(dev);
1371
1372         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1373                 pr_err("Handling parity error recovery. Try again later\n");
1374                 return -EAGAIN;
1375         }
1376
1377         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1378             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1379                                                     MIN_RX_SIZE_TPA)) ||
1380             (ering->tx_pending > MAX_TX_AVAIL) ||
1381             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1382                 return -EINVAL;
1383
1384         bp->rx_ring_size = ering->rx_pending;
1385         bp->tx_ring_size = ering->tx_pending;
1386
1387         return bnx2x_reload_if_running(dev);
1388 }
1389
1390 static void bnx2x_get_pauseparam(struct net_device *dev,
1391                                  struct ethtool_pauseparam *epause)
1392 {
1393         struct bnx2x *bp = netdev_priv(dev);
1394         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1395         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1396                            BNX2X_FLOW_CTRL_AUTO);
1397
1398         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1399                             BNX2X_FLOW_CTRL_RX);
1400         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1401                             BNX2X_FLOW_CTRL_TX);
1402
1403         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1404            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1405            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1406 }
1407
1408 static int bnx2x_set_pauseparam(struct net_device *dev,
1409                                 struct ethtool_pauseparam *epause)
1410 {
1411         struct bnx2x *bp = netdev_priv(dev);
1412         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1413         if (IS_MF(bp))
1414                 return 0;
1415
1416         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1417            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1418            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1419
1420         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1421
1422         if (epause->rx_pause)
1423                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1424
1425         if (epause->tx_pause)
1426                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1427
1428         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1429                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1430
1431         if (epause->autoneg) {
1432                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1433                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1434                         return -EINVAL;
1435                 }
1436
1437                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1438                         bp->link_params.req_flow_ctrl[cfg_idx] =
1439                                 BNX2X_FLOW_CTRL_AUTO;
1440                 }
1441         }
1442
1443         DP(NETIF_MSG_LINK,
1444            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1445
1446         if (netif_running(dev)) {
1447                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1448                 bnx2x_link_set(bp);
1449         }
1450
1451         return 0;
1452 }
1453
1454 static const struct {
1455         char string[ETH_GSTRING_LEN];
1456 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1457         { "register_test (offline)" },
1458         { "memory_test (offline)" },
1459         { "loopback_test (offline)" },
1460         { "nvram_test (online)" },
1461         { "interrupt_test (online)" },
1462         { "link_test (online)" },
1463         { "idle check (online)" }
1464 };
1465
1466 enum {
1467         BNX2X_CHIP_E1_OFST = 0,
1468         BNX2X_CHIP_E1H_OFST,
1469         BNX2X_CHIP_E2_OFST,
1470         BNX2X_CHIP_E3_OFST,
1471         BNX2X_CHIP_E3B0_OFST,
1472         BNX2X_CHIP_MAX_OFST
1473 };
1474
1475 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1476 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1477 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1478 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1479 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1480
1481 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1482 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1483
1484 static int bnx2x_test_registers(struct bnx2x *bp)
1485 {
1486         int idx, i, rc = -ENODEV;
1487         u32 wr_val = 0, hw;
1488         int port = BP_PORT(bp);
1489         static const struct {
1490                 u32 hw;
1491                 u32 offset0;
1492                 u32 offset1;
1493                 u32 mask;
1494         } reg_tbl[] = {
1495 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1496                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1497                 { BNX2X_CHIP_MASK_ALL,
1498                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1499                 { BNX2X_CHIP_MASK_E1X,
1500                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1501                 { BNX2X_CHIP_MASK_ALL,
1502                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1503                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1504                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1505                 { BNX2X_CHIP_MASK_E3B0,
1506                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1507                 { BNX2X_CHIP_MASK_ALL,
1508                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1509                 { BNX2X_CHIP_MASK_ALL,
1510                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1511                 { BNX2X_CHIP_MASK_ALL,
1512                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1513                 { BNX2X_CHIP_MASK_ALL,
1514                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1515 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1516                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1517                 { BNX2X_CHIP_MASK_ALL,
1518                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1519                 { BNX2X_CHIP_MASK_ALL,
1520                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1521                 { BNX2X_CHIP_MASK_ALL,
1522                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1523                 { BNX2X_CHIP_MASK_ALL,
1524                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1525                 { BNX2X_CHIP_MASK_ALL,
1526                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1527                 { BNX2X_CHIP_MASK_ALL,
1528                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1529                 { BNX2X_CHIP_MASK_ALL,
1530                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1531                 { BNX2X_CHIP_MASK_ALL,
1532                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1533                 { BNX2X_CHIP_MASK_ALL,
1534                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1535 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1536                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1537                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1538                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1539                 { BNX2X_CHIP_MASK_ALL,
1540                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1541                 { BNX2X_CHIP_MASK_ALL,
1542                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1543                 { BNX2X_CHIP_MASK_ALL,
1544                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1545                 { BNX2X_CHIP_MASK_ALL,
1546                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1547                 { BNX2X_CHIP_MASK_ALL,
1548                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1549                 { BNX2X_CHIP_MASK_ALL,
1550                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1551                 { BNX2X_CHIP_MASK_ALL,
1552                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1553                 { BNX2X_CHIP_MASK_ALL,
1554                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1555 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1556                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1557                 { BNX2X_CHIP_MASK_ALL,
1558                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1559                 { BNX2X_CHIP_MASK_ALL,
1560                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1561                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1562                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1563                 { BNX2X_CHIP_MASK_ALL,
1564                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1565                 { BNX2X_CHIP_MASK_ALL,
1566                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1567                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1568                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1569                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1570                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1571
1572                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1573         };
1574
1575         if (!netif_running(bp->dev))
1576                 return rc;
1577
1578         if (CHIP_IS_E1(bp))
1579                 hw = BNX2X_CHIP_MASK_E1;
1580         else if (CHIP_IS_E1H(bp))
1581                 hw = BNX2X_CHIP_MASK_E1H;
1582         else if (CHIP_IS_E2(bp))
1583                 hw = BNX2X_CHIP_MASK_E2;
1584         else if (CHIP_IS_E3B0(bp))
1585                 hw = BNX2X_CHIP_MASK_E3B0;
1586         else /* e3 A0 */
1587                 hw = BNX2X_CHIP_MASK_E3;
1588
1589         /* Repeat the test twice:
1590            First by writing 0x00000000, second by writing 0xffffffff */
1591         for (idx = 0; idx < 2; idx++) {
1592
1593                 switch (idx) {
1594                 case 0:
1595                         wr_val = 0;
1596                         break;
1597                 case 1:
1598                         wr_val = 0xffffffff;
1599                         break;
1600                 }
1601
1602                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1603                         u32 offset, mask, save_val, val;
1604                         if (!(hw & reg_tbl[i].hw))
1605                                 continue;
1606
1607                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1608                         mask = reg_tbl[i].mask;
1609
1610                         save_val = REG_RD(bp, offset);
1611
1612                         REG_WR(bp, offset, wr_val & mask);
1613
1614                         val = REG_RD(bp, offset);
1615
1616                         /* Restore the original register's value */
1617                         REG_WR(bp, offset, save_val);
1618
1619                         /* verify value is as expected */
1620                         if ((val & mask) != (wr_val & mask)) {
1621                                 DP(NETIF_MSG_HW,
1622                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1623                                    offset, val, wr_val, mask);
1624                                 goto test_reg_exit;
1625                         }
1626                 }
1627         }
1628
1629         rc = 0;
1630
1631 test_reg_exit:
1632         return rc;
1633 }
1634
1635 static int bnx2x_test_memory(struct bnx2x *bp)
1636 {
1637         int i, j, rc = -ENODEV;
1638         u32 val, index;
1639         static const struct {
1640                 u32 offset;
1641                 int size;
1642         } mem_tbl[] = {
1643                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1644                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1645                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1646                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1647                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1648                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1649                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1650
1651                 { 0xffffffff, 0 }
1652         };
1653
1654         static const struct {
1655                 char *name;
1656                 u32 offset;
1657                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1658         } prty_tbl[] = {
1659                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1660                         {0x3ffc0, 0,   0, 0} },
1661                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1662                         {0x2,     0x2, 0, 0} },
1663                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1664                         {0,       0,   0, 0} },
1665                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1666                         {0x3ffc0, 0,   0, 0} },
1667                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1668                         {0x3ffc0, 0,   0, 0} },
1669                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1670                         {0x3ffc1, 0,   0, 0} },
1671
1672                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1673         };
1674
1675         if (!netif_running(bp->dev))
1676                 return rc;
1677
1678         if (CHIP_IS_E1(bp))
1679                 index = BNX2X_CHIP_E1_OFST;
1680         else if (CHIP_IS_E1H(bp))
1681                 index = BNX2X_CHIP_E1H_OFST;
1682         else if (CHIP_IS_E2(bp))
1683                 index = BNX2X_CHIP_E2_OFST;
1684         else /* e3 */
1685                 index = BNX2X_CHIP_E3_OFST;
1686
1687         /* pre-Check the parity status */
1688         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1689                 val = REG_RD(bp, prty_tbl[i].offset);
1690                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1691                         DP(NETIF_MSG_HW,
1692                            "%s is 0x%x\n", prty_tbl[i].name, val);
1693                         goto test_mem_exit;
1694                 }
1695         }
1696
1697         /* Go through all the memories */
1698         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1699                 for (j = 0; j < mem_tbl[i].size; j++)
1700                         REG_RD(bp, mem_tbl[i].offset + j*4);
1701
1702         /* Check the parity status */
1703         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1704                 val = REG_RD(bp, prty_tbl[i].offset);
1705                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1706                         DP(NETIF_MSG_HW,
1707                            "%s is 0x%x\n", prty_tbl[i].name, val);
1708                         goto test_mem_exit;
1709                 }
1710         }
1711
1712         rc = 0;
1713
1714 test_mem_exit:
1715         return rc;
1716 }
1717
1718 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1719 {
1720         int cnt = 1400;
1721
1722         if (link_up) {
1723                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1724                         msleep(20);
1725
1726                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1727                         DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1728         }
1729 }
1730
1731 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1732 {
1733         unsigned int pkt_size, num_pkts, i;
1734         struct sk_buff *skb;
1735         unsigned char *packet;
1736         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1737         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1738         struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
1739         u16 tx_start_idx, tx_idx;
1740         u16 rx_start_idx, rx_idx;
1741         u16 pkt_prod, bd_prod, rx_comp_cons;
1742         struct sw_tx_bd *tx_buf;
1743         struct eth_tx_start_bd *tx_start_bd;
1744         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1745         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1746         dma_addr_t mapping;
1747         union eth_rx_cqe *cqe;
1748         u8 cqe_fp_flags, cqe_fp_type;
1749         struct sw_rx_bd *rx_buf;
1750         u16 len;
1751         int rc = -ENODEV;
1752         u8 *data;
1753         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
1754
1755         /* check the loopback mode */
1756         switch (loopback_mode) {
1757         case BNX2X_PHY_LOOPBACK:
1758                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1759                         return -EINVAL;
1760                 break;
1761         case BNX2X_MAC_LOOPBACK:
1762                 if (CHIP_IS_E3(bp)) {
1763                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1764                         if (bp->port.supported[cfg_idx] &
1765                             (SUPPORTED_10000baseT_Full |
1766                              SUPPORTED_20000baseMLD2_Full |
1767                              SUPPORTED_20000baseKR2_Full))
1768                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1769                         else
1770                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1771                 } else
1772                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
1773
1774                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1775                 break;
1776         default:
1777                 return -EINVAL;
1778         }
1779
1780         /* prepare the loopback packet */
1781         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1782                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1783         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1784         if (!skb) {
1785                 rc = -ENOMEM;
1786                 goto test_loopback_exit;
1787         }
1788         packet = skb_put(skb, pkt_size);
1789         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1790         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1791         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1792         for (i = ETH_HLEN; i < pkt_size; i++)
1793                 packet[i] = (unsigned char) (i & 0xff);
1794         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1795                                  skb_headlen(skb), DMA_TO_DEVICE);
1796         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1797                 rc = -ENOMEM;
1798                 dev_kfree_skb(skb);
1799                 BNX2X_ERR("Unable to map SKB\n");
1800                 goto test_loopback_exit;
1801         }
1802
1803         /* send the loopback packet */
1804         num_pkts = 0;
1805         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
1806         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1807
1808         netdev_tx_sent_queue(txq, skb->len);
1809
1810         pkt_prod = txdata->tx_pkt_prod++;
1811         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1812         tx_buf->first_bd = txdata->tx_bd_prod;
1813         tx_buf->skb = skb;
1814         tx_buf->flags = 0;
1815
1816         bd_prod = TX_BD(txdata->tx_bd_prod);
1817         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
1818         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1819         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1820         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1821         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1822         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1823         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1824         SET_FLAG(tx_start_bd->general_data,
1825                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1826                  UNICAST_ADDRESS);
1827         SET_FLAG(tx_start_bd->general_data,
1828                  ETH_TX_START_BD_HDR_NBDS,
1829                  1);
1830
1831         /* turn on parsing and get a BD */
1832         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1833
1834         pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1835         pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
1836
1837         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1838         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1839
1840         wmb();
1841
1842         txdata->tx_db.data.prod += 2;
1843         barrier();
1844         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
1845
1846         mmiowb();
1847         barrier();
1848
1849         num_pkts++;
1850         txdata->tx_bd_prod += 2; /* start + pbd */
1851
1852         udelay(100);
1853
1854         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
1855         if (tx_idx != tx_start_idx + num_pkts)
1856                 goto test_loopback_exit;
1857
1858         /* Unlike HC IGU won't generate an interrupt for status block
1859          * updates that have been performed while interrupts were
1860          * disabled.
1861          */
1862         if (bp->common.int_block == INT_BLOCK_IGU) {
1863                 /* Disable local BHes to prevent a dead-lock situation between
1864                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1865                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1866                  */
1867                 local_bh_disable();
1868                 bnx2x_tx_int(bp, txdata);
1869                 local_bh_enable();
1870         }
1871
1872         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1873         if (rx_idx != rx_start_idx + num_pkts)
1874                 goto test_loopback_exit;
1875
1876         rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1877         cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
1878         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1879         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1880         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1881                 goto test_loopback_rx_exit;
1882
1883         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1884         if (len != pkt_size)
1885                 goto test_loopback_rx_exit;
1886
1887         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1888         dma_sync_single_for_cpu(&bp->pdev->dev,
1889                                    dma_unmap_addr(rx_buf, mapping),
1890                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
1891         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
1892         for (i = ETH_HLEN; i < pkt_size; i++)
1893                 if (*(data + i) != (unsigned char) (i & 0xff))
1894                         goto test_loopback_rx_exit;
1895
1896         rc = 0;
1897
1898 test_loopback_rx_exit:
1899
1900         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1901         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1902         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1903         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1904
1905         /* Update producers */
1906         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1907                              fp_rx->rx_sge_prod);
1908
1909 test_loopback_exit:
1910         bp->link_params.loopback_mode = LOOPBACK_NONE;
1911
1912         return rc;
1913 }
1914
1915 static int bnx2x_test_loopback(struct bnx2x *bp)
1916 {
1917         int rc = 0, res;
1918
1919         if (BP_NOMCP(bp))
1920                 return rc;
1921
1922         if (!netif_running(bp->dev))
1923                 return BNX2X_LOOPBACK_FAILED;
1924
1925         bnx2x_netif_stop(bp, 1);
1926         bnx2x_acquire_phy_lock(bp);
1927
1928         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1929         if (res) {
1930                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1931                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1932         }
1933
1934         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1935         if (res) {
1936                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1937                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1938         }
1939
1940         bnx2x_release_phy_lock(bp);
1941         bnx2x_netif_start(bp);
1942
1943         return rc;
1944 }
1945
1946 #define CRC32_RESIDUAL                  0xdebb20e3
1947
1948 static int bnx2x_test_nvram(struct bnx2x *bp)
1949 {
1950         static const struct {
1951                 int offset;
1952                 int size;
1953         } nvram_tbl[] = {
1954                 {     0,  0x14 }, /* bootstrap */
1955                 {  0x14,  0xec }, /* dir */
1956                 { 0x100, 0x350 }, /* manuf_info */
1957                 { 0x450,  0xf0 }, /* feature_info */
1958                 { 0x640,  0x64 }, /* upgrade_key_info */
1959                 { 0x708,  0x70 }, /* manuf_key_info */
1960                 {     0,     0 }
1961         };
1962         __be32 buf[0x350 / 4];
1963         u8 *data = (u8 *)buf;
1964         int i, rc;
1965         u32 magic, crc;
1966
1967         if (BP_NOMCP(bp))
1968                 return 0;
1969
1970         rc = bnx2x_nvram_read(bp, 0, data, 4);
1971         if (rc) {
1972                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1973                 goto test_nvram_exit;
1974         }
1975
1976         magic = be32_to_cpu(buf[0]);
1977         if (magic != 0x669955aa) {
1978                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1979                 rc = -ENODEV;
1980                 goto test_nvram_exit;
1981         }
1982
1983         for (i = 0; nvram_tbl[i].size; i++) {
1984
1985                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1986                                       nvram_tbl[i].size);
1987                 if (rc) {
1988                         DP(NETIF_MSG_PROBE,
1989                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1990                         goto test_nvram_exit;
1991                 }
1992
1993                 crc = ether_crc_le(nvram_tbl[i].size, data);
1994                 if (crc != CRC32_RESIDUAL) {
1995                         DP(NETIF_MSG_PROBE,
1996                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1997                         rc = -ENODEV;
1998                         goto test_nvram_exit;
1999                 }
2000         }
2001
2002 test_nvram_exit:
2003         return rc;
2004 }
2005
2006 /* Send an EMPTY ramrod on the first queue */
2007 static int bnx2x_test_intr(struct bnx2x *bp)
2008 {
2009         struct bnx2x_queue_state_params params = {0};
2010
2011         if (!netif_running(bp->dev))
2012                 return -ENODEV;
2013
2014         params.q_obj = &bp->fp->q_obj;
2015         params.cmd = BNX2X_Q_CMD_EMPTY;
2016
2017         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2018
2019         return bnx2x_queue_state_change(bp, &params);
2020 }
2021
2022 static void bnx2x_self_test(struct net_device *dev,
2023                             struct ethtool_test *etest, u64 *buf)
2024 {
2025         struct bnx2x *bp = netdev_priv(dev);
2026         u8 is_serdes;
2027         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2028                 pr_err("Handling parity error recovery. Try again later\n");
2029                 etest->flags |= ETH_TEST_FL_FAILED;
2030                 return;
2031         }
2032
2033         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2034
2035         if (!netif_running(dev))
2036                 return;
2037
2038         /* offline tests are not supported in MF mode */
2039         if (IS_MF(bp))
2040                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
2041         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2042
2043         if (etest->flags & ETH_TEST_FL_OFFLINE) {
2044                 int port = BP_PORT(bp);
2045                 u32 val;
2046                 u8 link_up;
2047
2048                 /* save current value of input enable for TX port IF */
2049                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2050                 /* disable input for TX port IF */
2051                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2052
2053                 link_up = bp->link_vars.link_up;
2054
2055                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2056                 bnx2x_nic_load(bp, LOAD_DIAG);
2057                 /* wait until link state is restored */
2058                 bnx2x_wait_for_link(bp, 1, is_serdes);
2059
2060                 if (bnx2x_test_registers(bp) != 0) {
2061                         buf[0] = 1;
2062                         etest->flags |= ETH_TEST_FL_FAILED;
2063                 }
2064                 if (bnx2x_test_memory(bp) != 0) {
2065                         buf[1] = 1;
2066                         etest->flags |= ETH_TEST_FL_FAILED;
2067                 }
2068
2069                 buf[2] = bnx2x_test_loopback(bp);
2070                 if (buf[2] != 0)
2071                         etest->flags |= ETH_TEST_FL_FAILED;
2072
2073                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2074
2075                 /* restore input for TX port IF */
2076                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2077
2078                 bnx2x_nic_load(bp, LOAD_NORMAL);
2079                 /* wait until link state is restored */
2080                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2081         }
2082         if (bnx2x_test_nvram(bp) != 0) {
2083                 buf[3] = 1;
2084                 etest->flags |= ETH_TEST_FL_FAILED;
2085         }
2086         if (bnx2x_test_intr(bp) != 0) {
2087                 buf[4] = 1;
2088                 etest->flags |= ETH_TEST_FL_FAILED;
2089         }
2090
2091         if (bnx2x_link_test(bp, is_serdes) != 0) {
2092                 buf[5] = 1;
2093                 etest->flags |= ETH_TEST_FL_FAILED;
2094         }
2095
2096 #ifdef BNX2X_EXTRA_DEBUG
2097         bnx2x_panic_dump(bp);
2098 #endif
2099 }
2100
2101 #define IS_PORT_STAT(i) \
2102         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2103 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2104 #define IS_MF_MODE_STAT(bp) \
2105                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2106
2107 /* ethtool statistics are displayed for all regular ethernet queues and the
2108  * fcoe L2 queue if not disabled
2109  */
2110 static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2111 {
2112         return BNX2X_NUM_ETH_QUEUES(bp);
2113 }
2114
2115 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2116 {
2117         struct bnx2x *bp = netdev_priv(dev);
2118         int i, num_stats;
2119
2120         switch (stringset) {
2121         case ETH_SS_STATS:
2122                 if (is_multi(bp)) {
2123                         num_stats = bnx2x_num_stat_queues(bp) *
2124                                 BNX2X_NUM_Q_STATS;
2125                         if (!IS_MF_MODE_STAT(bp))
2126                                 num_stats += BNX2X_NUM_STATS;
2127                 } else {
2128                         if (IS_MF_MODE_STAT(bp)) {
2129                                 num_stats = 0;
2130                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
2131                                         if (IS_FUNC_STAT(i))
2132                                                 num_stats++;
2133                         } else
2134                                 num_stats = BNX2X_NUM_STATS;
2135                 }
2136                 return num_stats;
2137
2138         case ETH_SS_TEST:
2139                 return BNX2X_NUM_TESTS;
2140
2141         default:
2142                 return -EINVAL;
2143         }
2144 }
2145
2146 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2147 {
2148         struct bnx2x *bp = netdev_priv(dev);
2149         int i, j, k;
2150         char queue_name[MAX_QUEUE_NAME_LEN+1];
2151
2152         switch (stringset) {
2153         case ETH_SS_STATS:
2154                 if (is_multi(bp)) {
2155                         k = 0;
2156                         for_each_eth_queue(bp, i) {
2157                                 memset(queue_name, 0, sizeof(queue_name));
2158                                 sprintf(queue_name, "%d", i);
2159                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2160                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2161                                                 ETH_GSTRING_LEN,
2162                                                 bnx2x_q_stats_arr[j].string,
2163                                                 queue_name);
2164                                 k += BNX2X_NUM_Q_STATS;
2165                         }
2166                         if (IS_MF_MODE_STAT(bp))
2167                                 break;
2168                         for (j = 0; j < BNX2X_NUM_STATS; j++)
2169                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2170                                        bnx2x_stats_arr[j].string);
2171                 } else {
2172                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2173                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2174                                         continue;
2175                                 strcpy(buf + j*ETH_GSTRING_LEN,
2176                                        bnx2x_stats_arr[i].string);
2177                                 j++;
2178                         }
2179                 }
2180                 break;
2181
2182         case ETH_SS_TEST:
2183                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2184                 break;
2185         }
2186 }
2187
2188 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2189                                     struct ethtool_stats *stats, u64 *buf)
2190 {
2191         struct bnx2x *bp = netdev_priv(dev);
2192         u32 *hw_stats, *offset;
2193         int i, j, k;
2194
2195         if (is_multi(bp)) {
2196                 k = 0;
2197                 for_each_eth_queue(bp, i) {
2198                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2199                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2200                                 if (bnx2x_q_stats_arr[j].size == 0) {
2201                                         /* skip this counter */
2202                                         buf[k + j] = 0;
2203                                         continue;
2204                                 }
2205                                 offset = (hw_stats +
2206                                           bnx2x_q_stats_arr[j].offset);
2207                                 if (bnx2x_q_stats_arr[j].size == 4) {
2208                                         /* 4-byte counter */
2209                                         buf[k + j] = (u64) *offset;
2210                                         continue;
2211                                 }
2212                                 /* 8-byte counter */
2213                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2214                         }
2215                         k += BNX2X_NUM_Q_STATS;
2216                 }
2217                 if (IS_MF_MODE_STAT(bp))
2218                         return;
2219                 hw_stats = (u32 *)&bp->eth_stats;
2220                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2221                         if (bnx2x_stats_arr[j].size == 0) {
2222                                 /* skip this counter */
2223                                 buf[k + j] = 0;
2224                                 continue;
2225                         }
2226                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2227                         if (bnx2x_stats_arr[j].size == 4) {
2228                                 /* 4-byte counter */
2229                                 buf[k + j] = (u64) *offset;
2230                                 continue;
2231                         }
2232                         /* 8-byte counter */
2233                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2234                 }
2235         } else {
2236                 hw_stats = (u32 *)&bp->eth_stats;
2237                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2238                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2239                                 continue;
2240                         if (bnx2x_stats_arr[i].size == 0) {
2241                                 /* skip this counter */
2242                                 buf[j] = 0;
2243                                 j++;
2244                                 continue;
2245                         }
2246                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2247                         if (bnx2x_stats_arr[i].size == 4) {
2248                                 /* 4-byte counter */
2249                                 buf[j] = (u64) *offset;
2250                                 j++;
2251                                 continue;
2252                         }
2253                         /* 8-byte counter */
2254                         buf[j] = HILO_U64(*offset, *(offset + 1));
2255                         j++;
2256                 }
2257         }
2258 }
2259
2260 static int bnx2x_set_phys_id(struct net_device *dev,
2261                              enum ethtool_phys_id_state state)
2262 {
2263         struct bnx2x *bp = netdev_priv(dev);
2264
2265         if (!netif_running(dev))
2266                 return -EAGAIN;
2267
2268         if (!bp->port.pmf)
2269                 return -EOPNOTSUPP;
2270
2271         switch (state) {
2272         case ETHTOOL_ID_ACTIVE:
2273                 return 1;       /* cycle on/off once per second */
2274
2275         case ETHTOOL_ID_ON:
2276                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2277                               LED_MODE_ON, SPEED_1000);
2278                 break;
2279
2280         case ETHTOOL_ID_OFF:
2281                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2282                               LED_MODE_FRONT_PANEL_OFF, 0);
2283
2284                 break;
2285
2286         case ETHTOOL_ID_INACTIVE:
2287                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2288                               LED_MODE_OPER,
2289                               bp->link_vars.line_speed);
2290         }
2291
2292         return 0;
2293 }
2294
2295 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2296                            u32 *rules __always_unused)
2297 {
2298         struct bnx2x *bp = netdev_priv(dev);
2299
2300         switch (info->cmd) {
2301         case ETHTOOL_GRXRINGS:
2302                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2303                 return 0;
2304
2305         default:
2306                 return -EOPNOTSUPP;
2307         }
2308 }
2309
2310 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2311 {
2312         struct bnx2x *bp = netdev_priv(dev);
2313
2314         return (bp->multi_mode == ETH_RSS_MODE_DISABLED ?
2315                 0 : T_ETH_INDIRECTION_TABLE_SIZE);
2316 }
2317
2318 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
2319 {
2320         struct bnx2x *bp = netdev_priv(dev);
2321         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2322         size_t i;
2323
2324         /* Get the current configuration of the RSS indirection table */
2325         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2326
2327         /*
2328          * We can't use a memcpy() as an internal storage of an
2329          * indirection table is a u8 array while indir->ring_index
2330          * points to an array of u32.
2331          *
2332          * Indirection table contains the FW Client IDs, so we need to
2333          * align the returned table to the Client ID of the leading RSS
2334          * queue.
2335          */
2336         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2337                 indir[i] = ind_table[i] - bp->fp->cl_id;
2338
2339         return 0;
2340 }
2341
2342 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
2343 {
2344         struct bnx2x *bp = netdev_priv(dev);
2345         size_t i;
2346         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2347
2348         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2349                 /*
2350                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2351                  * as an internal storage of an indirection table is a u8 array
2352                  * while indir->ring_index points to an array of u32.
2353                  *
2354                  * Indirection table contains the FW Client IDs, so we need to
2355                  * align the received table to the Client ID of the leading RSS
2356                  * queue
2357                  */
2358                 ind_table[i] = indir[i] + bp->fp->cl_id;
2359         }
2360
2361         return bnx2x_config_rss_pf(bp, ind_table, false);
2362 }
2363
2364 static const struct ethtool_ops bnx2x_ethtool_ops = {
2365         .get_settings           = bnx2x_get_settings,
2366         .set_settings           = bnx2x_set_settings,
2367         .get_drvinfo            = bnx2x_get_drvinfo,
2368         .get_regs_len           = bnx2x_get_regs_len,
2369         .get_regs               = bnx2x_get_regs,
2370         .get_wol                = bnx2x_get_wol,
2371         .set_wol                = bnx2x_set_wol,
2372         .get_msglevel           = bnx2x_get_msglevel,
2373         .set_msglevel           = bnx2x_set_msglevel,
2374         .nway_reset             = bnx2x_nway_reset,
2375         .get_link               = bnx2x_get_link,
2376         .get_eeprom_len         = bnx2x_get_eeprom_len,
2377         .get_eeprom             = bnx2x_get_eeprom,
2378         .set_eeprom             = bnx2x_set_eeprom,
2379         .get_coalesce           = bnx2x_get_coalesce,
2380         .set_coalesce           = bnx2x_set_coalesce,
2381         .get_ringparam          = bnx2x_get_ringparam,
2382         .set_ringparam          = bnx2x_set_ringparam,
2383         .get_pauseparam         = bnx2x_get_pauseparam,
2384         .set_pauseparam         = bnx2x_set_pauseparam,
2385         .self_test              = bnx2x_self_test,
2386         .get_sset_count         = bnx2x_get_sset_count,
2387         .get_strings            = bnx2x_get_strings,
2388         .set_phys_id            = bnx2x_set_phys_id,
2389         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2390         .get_rxnfc              = bnx2x_get_rxnfc,
2391         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
2392         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2393         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2394 };
2395
2396 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2397 {
2398         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2399 }