drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  66         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  67                                         4, "[%s]: driver_filtered_tx_pkt" }
  68 };
  69
  70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  71
  72 static const struct {
  73         long offset;
  74         int size;
  75         u32 flags;
  76 #define STATS_FLAGS_PORT                1
  77 #define STATS_FLAGS_FUNC                2
  78 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  79         char string[ETH_GSTRING_LEN];
  80 } bnx2x_stats_arr[] = {
  81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  83         { STATS_OFFSET32(error_bytes_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  85         { STATS_OFFSET32(total_unicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  87         { STATS_OFFSET32(total_multicast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  89         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  90                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  91         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  93         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  95         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  97         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 101         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 102                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 103         { STATS_OFFSET32(no_buff_discard_hi),
 104                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 105         { STATS_OFFSET32(mac_filter_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 107         { STATS_OFFSET32(mf_tag_discard),
 108                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 109         { STATS_OFFSET32(pfc_frames_received_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 111         { STATS_OFFSET32(pfc_frames_sent_hi),
 112                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 113         { STATS_OFFSET32(brb_drop_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 115         { STATS_OFFSET32(brb_truncate_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 117         { STATS_OFFSET32(pause_frames_received_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 119         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 120                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 121         { STATS_OFFSET32(nig_timer_max),
 122                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 124                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 125         { STATS_OFFSET32(rx_skb_alloc_failed),
 126                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 127         { STATS_OFFSET32(hw_csum_err),
 128                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 129
 130         { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 132         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 134         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 136         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 138         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 140         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 142         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 150         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 152         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 166         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 168         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 170         { STATS_OFFSET32(pause_frames_sent_hi),
 171                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 172         { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 174         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 176         { STATS_OFFSET32(total_tpa_bytes_hi),
 177                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 178         { STATS_OFFSET32(recoverable_error),
 179                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 180         { STATS_OFFSET32(unrecoverable_error),
 181                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 182         { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
 184         { STATS_OFFSET32(eee_tx_lpi),
 185                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 186 };
 187
 188 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 189
 190 static int bnx2x_get_port_type(struct bnx2x *bp)
 191 {
 192         int port_type;
 193         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 194         switch (bp->link_params.phy[phy_idx].media_type) {
 195         case ETH_PHY_SFPP_10G_FIBER:
 196         case ETH_PHY_SFP_1G_FIBER:
 197         case ETH_PHY_XFP_FIBER:
 198         case ETH_PHY_KR:
 199         case ETH_PHY_CX4:
 200                 port_type = PORT_FIBRE;
 201                 break;
 202         case ETH_PHY_DA_TWINAX:
 203                 port_type = PORT_DA;
 204                 break;
 205         case ETH_PHY_BASE_T:
 206                 port_type = PORT_TP;
 207                 break;
 208         case ETH_PHY_NOT_PRESENT:
 209                 port_type = PORT_NONE;
 210                 break;
 211         case ETH_PHY_UNSPECIFIED:
 212         default:
 213                 port_type = PORT_OTHER;
 214                 break;
 215         }
 216         return port_type;
 217 }
 218
 219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 220 {
 221         struct bnx2x *bp = netdev_priv(dev);
 222         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 223
 224         /* Dual Media boards present all available port types */
 225         cmd->supported = bp->port.supported[cfg_idx] |
 226                 (bp->port.supported[cfg_idx ^ 1] &
 227                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 228         cmd->advertising = bp->port.advertising[cfg_idx];
 229         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 230             ETH_PHY_SFP_1G_FIBER) {
 231                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 232                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 233         }
 234
 235         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 236             !(bp->flags & MF_FUNC_DIS)) {
 237                 cmd->duplex = bp->link_vars.duplex;
 238
 239                 if (IS_MF(bp) && !BP_NOMCP(bp))
 240                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 241                 else
 242                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 243         } else {
 244                 cmd->duplex = DUPLEX_UNKNOWN;
 245                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 246         }
 247
 248         cmd->port = bnx2x_get_port_type(bp);
 249
 250         cmd->phy_address = bp->mdio.prtad;
 251         cmd->transceiver = XCVR_INTERNAL;
 252
 253         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 254                 cmd->autoneg = AUTONEG_ENABLE;
 255         else
 256                 cmd->autoneg = AUTONEG_DISABLE;
 257
 258         /* Publish LP advertised speeds and FC */
 259         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 260                 u32 status = bp->link_vars.link_status;
 261
 262                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 263                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 264                         cmd->lp_advertising |= ADVERTISED_Pause;
 265                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 266                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 267
 268                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 269                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 270                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 271                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 272                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 273                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 274                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 275                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 276                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 277                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 278                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 279                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 280                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 281                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 282                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 283                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 284         }
 285
 286         cmd->maxtxpkt = 0;
 287         cmd->maxrxpkt = 0;
 288
 289         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 290            "  supported 0x%x  advertising 0x%x  speed %u\n"
 291            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 292            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 293            cmd->cmd, cmd->supported, cmd->advertising,
 294            ethtool_cmd_speed(cmd),
 295            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 296            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 297
 298         return 0;
 299 }
 300
 301 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 302 {
 303         struct bnx2x *bp = netdev_priv(dev);
 304         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 305         u32 speed, phy_idx;
 306
 307         if (IS_MF_SD(bp))
 308                 return 0;
 309
 310         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 311            "  supported 0x%x  advertising 0x%x  speed %u\n"
 312            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 313            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 314            cmd->cmd, cmd->supported, cmd->advertising,
 315            ethtool_cmd_speed(cmd),
 316            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 317            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 318
 319         speed = ethtool_cmd_speed(cmd);
 320
 321         /* If recieved a request for an unknown duplex, assume full*/
 322         if (cmd->duplex == DUPLEX_UNKNOWN)
 323                 cmd->duplex = DUPLEX_FULL;
 324
 325         if (IS_MF_SI(bp)) {
 326                 u32 part;
 327                 u32 line_speed = bp->link_vars.line_speed;
 328
 329                 /* use 10G if no link detected */
 330                 if (!line_speed)
 331                         line_speed = 10000;
 332
 333                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 334                         DP(BNX2X_MSG_ETHTOOL,
 335                            "To set speed BC %X or higher is required, please upgrade BC\n",
 336                            REQ_BC_VER_4_SET_MF_BW);
 337                         return -EINVAL;
 338                 }
 339
 340                 part = (speed * 100) / line_speed;
 341
 342                 if (line_speed < speed || !part) {
 343                         DP(BNX2X_MSG_ETHTOOL,
 344                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 345                         return -EINVAL;
 346                 }
 347
 348                 if (bp->state != BNX2X_STATE_OPEN)
 349                         /* store value for following "load" */
 350                         bp->pending_max = part;
 351                 else
 352                         bnx2x_update_max_mf_config(bp, part);
 353
 354                 return 0;
 355         }
 356
 357         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 358         old_multi_phy_config = bp->link_params.multi_phy_config;
 359         switch (cmd->port) {
 360         case PORT_TP:
 361                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 362                         break; /* no port change */
 363
 364                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 365                       bp->port.supported[1] & SUPPORTED_TP)) {
 366                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 367                         return -EINVAL;
 368                 }
 369                 bp->link_params.multi_phy_config &=
 370                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 371                 if (bp->link_params.multi_phy_config &
 372                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 373                         bp->link_params.multi_phy_config |=
 374                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 375                 else
 376                         bp->link_params.multi_phy_config |=
 377                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 378                 break;
 379         case PORT_FIBRE:
 380         case PORT_DA:
 381                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 382                         break; /* no port change */
 383
 384                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 385                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 386                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 387                         return -EINVAL;
 388                 }
 389                 bp->link_params.multi_phy_config &=
 390                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 391                 if (bp->link_params.multi_phy_config &
 392                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 393                         bp->link_params.multi_phy_config |=
 394                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 395                 else
 396                         bp->link_params.multi_phy_config |=
 397                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 398                 break;
 399         default:
 400                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 401                 return -EINVAL;
 402         }
 403         /* Save new config in case command complete successfully */
 404         new_multi_phy_config = bp->link_params.multi_phy_config;
 405         /* Get the new cfg_idx */
 406         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 407         /* Restore old config in case command failed */
 408         bp->link_params.multi_phy_config = old_multi_phy_config;
 409         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 410
 411         if (cmd->autoneg == AUTONEG_ENABLE) {
 412                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 413                 if (bp->link_params.phy[EXT_PHY1].type ==
 414                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 415                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 416                                                SUPPORTED_100baseT_Full);
 417                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 418                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 419                         return -EINVAL;
 420                 }
 421
 422                 /* advertise the requested speed and duplex if supported */
 423                 if (cmd->advertising & ~an_supported_speed) {
 424                         DP(BNX2X_MSG_ETHTOOL,
 425                            "Advertisement parameters are not supported\n");
 426                         return -EINVAL;
 427                 }
 428
 429                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 430                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 431                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 432                                          cmd->advertising);
 433                 if (cmd->advertising) {
 434
 435                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 436                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 437                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 438                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 439                         }
 440                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 441                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 442                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 443
 444                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 445                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 446                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 447
 448                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 449                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 450                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 451                         }
 452                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 453                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 454                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 455                         }
 456                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 457                                                 ADVERTISED_1000baseKX_Full))
 458                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 459                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 460
 461                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 462                                                 ADVERTISED_10000baseKX4_Full |
 463                                                 ADVERTISED_10000baseKR_Full))
 464                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 465                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 466                 }
 467         } else { /* forced speed */
 468                 /* advertise the requested speed and duplex if supported */
 469                 switch (speed) {
 470                 case SPEED_10:
 471                         if (cmd->duplex == DUPLEX_FULL) {
 472                                 if (!(bp->port.supported[cfg_idx] &
 473                                       SUPPORTED_10baseT_Full)) {
 474                                         DP(BNX2X_MSG_ETHTOOL,
 475                                            "10M full not supported\n");
 476                                         return -EINVAL;
 477                                 }
 478
 479                                 advertising = (ADVERTISED_10baseT_Full |
 480                                                ADVERTISED_TP);
 481                         } else {
 482                                 if (!(bp->port.supported[cfg_idx] &
 483                                       SUPPORTED_10baseT_Half)) {
 484                                         DP(BNX2X_MSG_ETHTOOL,
 485                                            "10M half not supported\n");
 486                                         return -EINVAL;
 487                                 }
 488
 489                                 advertising = (ADVERTISED_10baseT_Half |
 490                                                ADVERTISED_TP);
 491                         }
 492                         break;
 493
 494                 case SPEED_100:
 495                         if (cmd->duplex == DUPLEX_FULL) {
 496                                 if (!(bp->port.supported[cfg_idx] &
 497                                                 SUPPORTED_100baseT_Full)) {
 498                                         DP(BNX2X_MSG_ETHTOOL,
 499                                            "100M full not supported\n");
 500                                         return -EINVAL;
 501                                 }
 502
 503                                 advertising = (ADVERTISED_100baseT_Full |
 504                                                ADVERTISED_TP);
 505                         } else {
 506                                 if (!(bp->port.supported[cfg_idx] &
 507                                                 SUPPORTED_100baseT_Half)) {
 508                                         DP(BNX2X_MSG_ETHTOOL,
 509                                            "100M half not supported\n");
 510                                         return -EINVAL;
 511                                 }
 512
 513                                 advertising = (ADVERTISED_100baseT_Half |
 514                                                ADVERTISED_TP);
 515                         }
 516                         break;
 517
 518                 case SPEED_1000:
 519                         if (cmd->duplex != DUPLEX_FULL) {
 520                                 DP(BNX2X_MSG_ETHTOOL,
 521                                    "1G half not supported\n");
 522                                 return -EINVAL;
 523                         }
 524
 525                         if (!(bp->port.supported[cfg_idx] &
 526                               SUPPORTED_1000baseT_Full)) {
 527                                 DP(BNX2X_MSG_ETHTOOL,
 528                                    "1G full not supported\n");
 529                                 return -EINVAL;
 530                         }
 531
 532                         advertising = (ADVERTISED_1000baseT_Full |
 533                                        ADVERTISED_TP);
 534                         break;
 535
 536                 case SPEED_2500:
 537                         if (cmd->duplex != DUPLEX_FULL) {
 538                                 DP(BNX2X_MSG_ETHTOOL,
 539                                    "2.5G half not supported\n");
 540                                 return -EINVAL;
 541                         }
 542
 543                         if (!(bp->port.supported[cfg_idx]
 544                               & SUPPORTED_2500baseX_Full)) {
 545                                 DP(BNX2X_MSG_ETHTOOL,
 546                                    "2.5G full not supported\n");
 547                                 return -EINVAL;
 548                         }
 549
 550                         advertising = (ADVERTISED_2500baseX_Full |
 551                                        ADVERTISED_TP);
 552                         break;
 553
 554                 case SPEED_10000:
 555                         if (cmd->duplex != DUPLEX_FULL) {
 556                                 DP(BNX2X_MSG_ETHTOOL,
 557                                    "10G half not supported\n");
 558                                 return -EINVAL;
 559                         }
 560                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 561                         if (!(bp->port.supported[cfg_idx]
 562                               & SUPPORTED_10000baseT_Full) ||
 563                             (bp->link_params.phy[phy_idx].media_type ==
 564                              ETH_PHY_SFP_1G_FIBER)) {
 565                                 DP(BNX2X_MSG_ETHTOOL,
 566                                    "10G full not supported\n");
 567                                 return -EINVAL;
 568                         }
 569
 570                         advertising = (ADVERTISED_10000baseT_Full |
 571                                        ADVERTISED_FIBRE);
 572                         break;
 573
 574                 default:
 575                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 576                         return -EINVAL;
 577                 }
 578
 579                 bp->link_params.req_line_speed[cfg_idx] = speed;
 580                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 581                 bp->port.advertising[cfg_idx] = advertising;
 582         }
 583
 584         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 585            "  req_duplex %d  advertising 0x%x\n",
 586            bp->link_params.req_line_speed[cfg_idx],
 587            bp->link_params.req_duplex[cfg_idx],
 588            bp->port.advertising[cfg_idx]);
 589
 590         /* Set new config */
 591         bp->link_params.multi_phy_config = new_multi_phy_config;
 592         if (netif_running(dev)) {
 593                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 594                 bnx2x_link_set(bp);
 595         }
 596
 597         return 0;
 598 }
 599
 600 #define DUMP_ALL_PRESETS                0x1FFF
 601 #define DUMP_MAX_PRESETS                13
 602
 603 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 604 {
 605         if (CHIP_IS_E1(bp))
 606                 return dump_num_registers[0][preset-1];
 607         else if (CHIP_IS_E1H(bp))
 608                 return dump_num_registers[1][preset-1];
 609         else if (CHIP_IS_E2(bp))
 610                 return dump_num_registers[2][preset-1];
 611         else if (CHIP_IS_E3A0(bp))
 612                 return dump_num_registers[3][preset-1];
 613         else if (CHIP_IS_E3B0(bp))
 614                 return dump_num_registers[4][preset-1];
 615         else
 616                 return 0;
 617 }
 618
 619 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 620 {
 621         u32 preset_idx;
 622         int regdump_len = 0;
 623
 624         /* Calculate the total preset regs length */
 625         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 626                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 627
 628         return regdump_len;
 629 }
 630
 631 static int bnx2x_get_regs_len(struct net_device *dev)
 632 {
 633         struct bnx2x *bp = netdev_priv(dev);
 634         int regdump_len = 0;
 635
 636         regdump_len = __bnx2x_get_regs_len(bp);
 637         regdump_len *= 4;
 638         regdump_len += sizeof(struct dump_header);
 639
 640         return regdump_len;
 641 }
 642
 643 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 644 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 645 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 646 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 647 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 648
 649 #define IS_REG_IN_PRESET(presets, idx)  \
 650                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 651
 652 /******* Paged registers info selectors ********/
 653 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 654 {
 655         if (CHIP_IS_E2(bp))
 656                 return page_vals_e2;
 657         else if (CHIP_IS_E3(bp))
 658                 return page_vals_e3;
 659         else
 660                 return NULL;
 661 }
 662
 663 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 664 {
 665         if (CHIP_IS_E2(bp))
 666                 return PAGE_MODE_VALUES_E2;
 667         else if (CHIP_IS_E3(bp))
 668                 return PAGE_MODE_VALUES_E3;
 669         else
 670                 return 0;
 671 }
 672
 673 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 674 {
 675         if (CHIP_IS_E2(bp))
 676                 return page_write_regs_e2;
 677         else if (CHIP_IS_E3(bp))
 678                 return page_write_regs_e3;
 679         else
 680                 return NULL;
 681 }
 682
 683 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 684 {
 685         if (CHIP_IS_E2(bp))
 686                 return PAGE_WRITE_REGS_E2;
 687         else if (CHIP_IS_E3(bp))
 688                 return PAGE_WRITE_REGS_E3;
 689         else
 690                 return 0;
 691 }
 692
 693 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 694 {
 695         if (CHIP_IS_E2(bp))
 696                 return page_read_regs_e2;
 697         else if (CHIP_IS_E3(bp))
 698                 return page_read_regs_e3;
 699         else
 700                 return NULL;
 701 }
 702
 703 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 704 {
 705         if (CHIP_IS_E2(bp))
 706                 return PAGE_READ_REGS_E2;
 707         else if (CHIP_IS_E3(bp))
 708                 return PAGE_READ_REGS_E3;
 709         else
 710                 return 0;
 711 }
 712
 713 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 714                                        const struct reg_addr *reg_info)
 715 {
 716         if (CHIP_IS_E1(bp))
 717                 return IS_E1_REG(reg_info->chips);
 718         else if (CHIP_IS_E1H(bp))
 719                 return IS_E1H_REG(reg_info->chips);
 720         else if (CHIP_IS_E2(bp))
 721                 return IS_E2_REG(reg_info->chips);
 722         else if (CHIP_IS_E3A0(bp))
 723                 return IS_E3A0_REG(reg_info->chips);
 724         else if (CHIP_IS_E3B0(bp))
 725                 return IS_E3B0_REG(reg_info->chips);
 726         else
 727                 return false;
 728 }
 729
 730
 731 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 732         const struct wreg_addr *wreg_info)
 733 {
 734         if (CHIP_IS_E1(bp))
 735                 return IS_E1_REG(wreg_info->chips);
 736         else if (CHIP_IS_E1H(bp))
 737                 return IS_E1H_REG(wreg_info->chips);
 738         else if (CHIP_IS_E2(bp))
 739                 return IS_E2_REG(wreg_info->chips);
 740         else if (CHIP_IS_E3A0(bp))
 741                 return IS_E3A0_REG(wreg_info->chips);
 742         else if (CHIP_IS_E3B0(bp))
 743                 return IS_E3B0_REG(wreg_info->chips);
 744         else
 745                 return false;
 746 }
 747
 748 /**
 749  * bnx2x_read_pages_regs - read "paged" registers
 750  *
 751  * @bp          device handle
 752  * @p           output buffer
 753  *
 754  * Reads "paged" memories: memories that may only be read by first writing to a
 755  * specific address ("write address") and then reading from a specific address
 756  * ("read address"). There may be more than one write address per "page" and
 757  * more than one read address per write address.
 758  */
 759 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 760 {
 761         u32 i, j, k, n;
 762
 763         /* addresses of the paged registers */
 764         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 765         /* number of paged registers */
 766         int num_pages = __bnx2x_get_page_reg_num(bp);
 767         /* write addresses */
 768         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 769         /* number of write addresses */
 770         int write_num = __bnx2x_get_page_write_num(bp);
 771         /* read addresses info */
 772         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 773         /* number of read addresses */
 774         int read_num = __bnx2x_get_page_read_num(bp);
 775         u32 addr, size;
 776
 777         for (i = 0; i < num_pages; i++) {
 778                 for (j = 0; j < write_num; j++) {
 779                         REG_WR(bp, write_addr[j], page_addr[i]);
 780
 781                         for (k = 0; k < read_num; k++) {
 782                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 783                                                      preset)) {
 784                                         size = read_addr[k].size;
 785                                         for (n = 0; n < size; n++) {
 786                                                 addr = read_addr[k].addr + n*4;
 787                                                 *p++ = REG_RD(bp, addr);
 788                                         }
 789                                 }
 790                         }
 791                 }
 792         }
 793 }
 794
 795 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 796 {
 797         u32 i, j, addr;
 798         const struct wreg_addr *wreg_addr_p = NULL;
 799
 800         if (CHIP_IS_E1(bp))
 801                 wreg_addr_p = &wreg_addr_e1;
 802         else if (CHIP_IS_E1H(bp))
 803                 wreg_addr_p = &wreg_addr_e1h;
 804         else if (CHIP_IS_E2(bp))
 805                 wreg_addr_p = &wreg_addr_e2;
 806         else if (CHIP_IS_E3A0(bp))
 807                 wreg_addr_p = &wreg_addr_e3;
 808         else if (CHIP_IS_E3B0(bp))
 809                 wreg_addr_p = &wreg_addr_e3b0;
 810
 811         /* Read the idle_chk registers */
 812         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 813                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 814                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 815                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 816                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 817                 }
 818         }
 819
 820         /* Read the regular registers */
 821         for (i = 0; i < REGS_COUNT; i++) {
 822                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 823                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 824                         for (j = 0; j < reg_addrs[i].size; j++)
 825                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 826                 }
 827         }
 828
 829         /* Read the CAM registers */
 830         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 831             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 832                 for (i = 0; i < wreg_addr_p->size; i++) {
 833                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 834
 835                         /* In case of wreg_addr register, read additional
 836                            registers from read_regs array
 837                         */
 838                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 839                                 addr = *(wreg_addr_p->read_regs);
 840                                 *p++ = REG_RD(bp, addr + j*4);
 841                         }
 842                 }
 843         }
 844
 845         /* Paged registers are supported in E2 & E3 only */
 846         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 847                 /* Read "paged" registes */
 848                 bnx2x_read_pages_regs(bp, p, preset);
 849         }
 850
 851         return 0;
 852 }
 853
 854 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 855 {
 856         u32 preset_idx;
 857
 858         /* Read all registers, by reading all preset registers */
 859         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 860                 /* Skip presets with IOR */
 861                 if ((preset_idx == 2) ||
 862                     (preset_idx == 5) ||
 863                     (preset_idx == 8) ||
 864                     (preset_idx == 11))
 865                         continue;
 866                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 867                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 868         }
 869 }
 870
 871 static void bnx2x_get_regs(struct net_device *dev,
 872                            struct ethtool_regs *regs, void *_p)
 873 {
 874         u32 *p = _p;
 875         struct bnx2x *bp = netdev_priv(dev);
 876         struct dump_header dump_hdr = {0};
 877
 878         regs->version = 2;
 879         memset(p, 0, regs->len);
 880
 881         if (!netif_running(bp->dev))
 882                 return;
 883
 884         /* Disable parity attentions as long as following dump may
 885          * cause false alarms by reading never written registers. We
 886          * will re-enable parity attentions right after the dump.
 887          */
 888
 889         /* Disable parity on path 0 */
 890         bnx2x_pretend_func(bp, 0);
 891         bnx2x_disable_blocks_parity(bp);
 892
 893         /* Disable parity on path 1 */
 894         bnx2x_pretend_func(bp, 1);
 895         bnx2x_disable_blocks_parity(bp);
 896
 897         /* Return to current function */
 898         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
 899
 900         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 901         dump_hdr.preset = DUMP_ALL_PRESETS;
 902         dump_hdr.version = BNX2X_DUMP_VERSION;
 903
 904         /* dump_meta_data presents OR of CHIP and PATH. */
 905         if (CHIP_IS_E1(bp)) {
 906                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 907         } else if (CHIP_IS_E1H(bp)) {
 908                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 909         } else if (CHIP_IS_E2(bp)) {
 910                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 911                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 912         } else if (CHIP_IS_E3A0(bp)) {
 913                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 914                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 915         } else if (CHIP_IS_E3B0(bp)) {
 916                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 917                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 918         }
 919
 920         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 921         p += dump_hdr.header_size + 1;
 922
 923         /* Actually read the registers */
 924         __bnx2x_get_regs(bp, p);
 925
 926         /* Re-enable parity attentions on path 0 */
 927         bnx2x_pretend_func(bp, 0);
 928         bnx2x_clear_blocks_parity(bp);
 929         bnx2x_enable_blocks_parity(bp);
 930
 931         /* Re-enable parity attentions on path 1 */
 932         bnx2x_pretend_func(bp, 1);
 933         bnx2x_clear_blocks_parity(bp);
 934         bnx2x_enable_blocks_parity(bp);
 935
 936         /* Return to current function */
 937         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
 938 }
 939
 940 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 941 {
 942         struct bnx2x *bp = netdev_priv(dev);
 943         int regdump_len = 0;
 944
 945         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
 946         regdump_len *= 4;
 947         regdump_len += sizeof(struct dump_header);
 948
 949         return regdump_len;
 950 }
 951
 952 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
 953 {
 954         struct bnx2x *bp = netdev_priv(dev);
 955
 956         /* Use the ethtool_dump "flag" field as the dump preset index */
 957         bp->dump_preset_idx = val->flag;
 958         return 0;
 959 }
 960
 961 static int bnx2x_get_dump_flag(struct net_device *dev,
 962                                struct ethtool_dump *dump)
 963 {
 964         struct bnx2x *bp = netdev_priv(dev);
 965
 966         /* Calculate the requested preset idx length */
 967         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
 968         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
 969            bp->dump_preset_idx, dump->len);
 970
 971         dump->flag = ETHTOOL_GET_DUMP_DATA;
 972         return 0;
 973 }
 974
 975 static int bnx2x_get_dump_data(struct net_device *dev,
 976                                struct ethtool_dump *dump,
 977                                void *buffer)
 978 {
 979         u32 *p = buffer;
 980         struct bnx2x *bp = netdev_priv(dev);
 981         struct dump_header dump_hdr = {0};
 982
 983         memset(p, 0, dump->len);
 984
 985         /* Disable parity attentions as long as following dump may
 986          * cause false alarms by reading never written registers. We
 987          * will re-enable parity attentions right after the dump.
 988          */
 989
 990         /* Disable parity on path 0 */
 991         bnx2x_pretend_func(bp, 0);
 992         bnx2x_disable_blocks_parity(bp);
 993
 994         /* Disable parity on path 1 */
 995         bnx2x_pretend_func(bp, 1);
 996         bnx2x_disable_blocks_parity(bp);
 997
 998         /* Return to current function */
 999         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1000
1001         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1002         dump_hdr.preset = bp->dump_preset_idx;
1003         dump_hdr.version = BNX2X_DUMP_VERSION;
1004
1005         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1006
1007         /* dump_meta_data presents OR of CHIP and PATH. */
1008         if (CHIP_IS_E1(bp)) {
1009                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1010         } else if (CHIP_IS_E1H(bp)) {
1011                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1012         } else if (CHIP_IS_E2(bp)) {
1013                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1014                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1015         } else if (CHIP_IS_E3A0(bp)) {
1016                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1017                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1018         } else if (CHIP_IS_E3B0(bp)) {
1019                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1020                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1021         }
1022
1023         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1024         p += dump_hdr.header_size + 1;
1025
1026         /* Actually read the registers */
1027         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1028
1029         /* Re-enable parity attentions on path 0 */
1030         bnx2x_pretend_func(bp, 0);
1031         bnx2x_clear_blocks_parity(bp);
1032         bnx2x_enable_blocks_parity(bp);
1033
1034         /* Re-enable parity attentions on path 1 */
1035         bnx2x_pretend_func(bp, 1);
1036         bnx2x_clear_blocks_parity(bp);
1037         bnx2x_enable_blocks_parity(bp);
1038
1039         /* Return to current function */
1040         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1041
1042         return 0;
1043 }
1044
1045 static void bnx2x_get_drvinfo(struct net_device *dev,
1046                               struct ethtool_drvinfo *info)
1047 {
1048         struct bnx2x *bp = netdev_priv(dev);
1049
1050         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1051         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1052
1053         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1054
1055         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1056         info->n_stats = BNX2X_NUM_STATS;
1057         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1058         info->eedump_len = bp->common.flash_size;
1059         info->regdump_len = bnx2x_get_regs_len(dev);
1060 }
1061
1062 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1063 {
1064         struct bnx2x *bp = netdev_priv(dev);
1065
1066         if (bp->flags & NO_WOL_FLAG) {
1067                 wol->supported = 0;
1068                 wol->wolopts = 0;
1069         } else {
1070                 wol->supported = WAKE_MAGIC;
1071                 if (bp->wol)
1072                         wol->wolopts = WAKE_MAGIC;
1073                 else
1074                         wol->wolopts = 0;
1075         }
1076         memset(&wol->sopass, 0, sizeof(wol->sopass));
1077 }
1078
1079 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1080 {
1081         struct bnx2x *bp = netdev_priv(dev);
1082
1083         if (wol->wolopts & ~WAKE_MAGIC) {
1084                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1085                 return -EINVAL;
1086         }
1087
1088         if (wol->wolopts & WAKE_MAGIC) {
1089                 if (bp->flags & NO_WOL_FLAG) {
1090                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1091                         return -EINVAL;
1092                 }
1093                 bp->wol = 1;
1094         } else
1095                 bp->wol = 0;
1096
1097         return 0;
1098 }
1099
1100 static u32 bnx2x_get_msglevel(struct net_device *dev)
1101 {
1102         struct bnx2x *bp = netdev_priv(dev);
1103
1104         return bp->msg_enable;
1105 }
1106
1107 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1108 {
1109         struct bnx2x *bp = netdev_priv(dev);
1110
1111         if (capable(CAP_NET_ADMIN)) {
1112                 /* dump MCP trace */
1113                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1114                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1115                 bp->msg_enable = level;
1116         }
1117 }
1118
1119 static int bnx2x_nway_reset(struct net_device *dev)
1120 {
1121         struct bnx2x *bp = netdev_priv(dev);
1122
1123         if (!bp->port.pmf)
1124                 return 0;
1125
1126         if (netif_running(dev)) {
1127                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1128                 bnx2x_force_link_reset(bp);
1129                 bnx2x_link_set(bp);
1130         }
1131
1132         return 0;
1133 }
1134
1135 static u32 bnx2x_get_link(struct net_device *dev)
1136 {
1137         struct bnx2x *bp = netdev_priv(dev);
1138
1139         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1140                 return 0;
1141
1142         return bp->link_vars.link_up;
1143 }
1144
1145 static int bnx2x_get_eeprom_len(struct net_device *dev)
1146 {
1147         struct bnx2x *bp = netdev_priv(dev);
1148
1149         return bp->common.flash_size;
1150 }
1151
1152 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1153  * we done things the other way around, if two pfs from the same port would
1154  * attempt to access nvram at the same time, we could run into a scenario such
1155  * as:
1156  * pf A takes the port lock.
1157  * pf B succeeds in taking the same lock since they are from the same port.
1158  * pf A takes the per pf misc lock. Performs eeprom access.
1159  * pf A finishes. Unlocks the per pf misc lock.
1160  * Pf B takes the lock and proceeds to perform it's own access.
1161  * pf A unlocks the per port lock, while pf B is still working (!).
1162  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1163  * access corrupted by pf B)
1164  */
1165 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1166 {
1167         int port = BP_PORT(bp);
1168         int count, i;
1169         u32 val;
1170
1171         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1172         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1173
1174         /* adjust timeout for emulation/FPGA */
1175         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1176         if (CHIP_REV_IS_SLOW(bp))
1177                 count *= 100;
1178
1179         /* request access to nvram interface */
1180         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1181                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1182
1183         for (i = 0; i < count*10; i++) {
1184                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1185                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1186                         break;
1187
1188                 udelay(5);
1189         }
1190
1191         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1192                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1193                    "cannot get access to nvram interface\n");
1194                 return -EBUSY;
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1201 {
1202         int port = BP_PORT(bp);
1203         int count, i;
1204         u32 val;
1205
1206         /* adjust timeout for emulation/FPGA */
1207         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1208         if (CHIP_REV_IS_SLOW(bp))
1209                 count *= 100;
1210
1211         /* relinquish nvram interface */
1212         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1213                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1214
1215         for (i = 0; i < count*10; i++) {
1216                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1217                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1218                         break;
1219
1220                 udelay(5);
1221         }
1222
1223         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1224                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1225                    "cannot free access to nvram interface\n");
1226                 return -EBUSY;
1227         }
1228
1229         /* release HW lock: protect against other PFs in PF Direct Assignment */
1230         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1231         return 0;
1232 }
1233
1234 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1235 {
1236         u32 val;
1237
1238         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1239
1240         /* enable both bits, even on read */
1241         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1242                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1243                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1244 }
1245
1246 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1247 {
1248         u32 val;
1249
1250         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1251
1252         /* disable both bits, even after read */
1253         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1254                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1255                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1256 }
1257
1258 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1259                                   u32 cmd_flags)
1260 {
1261         int count, i, rc;
1262         u32 val;
1263
1264         /* build the command word */
1265         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1266
1267         /* need to clear DONE bit separately */
1268         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1269
1270         /* address of the NVRAM to read from */
1271         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1272                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1273
1274         /* issue a read command */
1275         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1276
1277         /* adjust timeout for emulation/FPGA */
1278         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1279         if (CHIP_REV_IS_SLOW(bp))
1280                 count *= 100;
1281
1282         /* wait for completion */
1283         *ret_val = 0;
1284         rc = -EBUSY;
1285         for (i = 0; i < count; i++) {
1286                 udelay(5);
1287                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1288
1289                 if (val & MCPR_NVM_COMMAND_DONE) {
1290                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1291                         /* we read nvram data in cpu order
1292                          * but ethtool sees it as an array of bytes
1293                          * converting to big-endian will do the work
1294                          */
1295                         *ret_val = cpu_to_be32(val);
1296                         rc = 0;
1297                         break;
1298                 }
1299         }
1300         if (rc == -EBUSY)
1301                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1302                    "nvram read timeout expired\n");
1303         return rc;
1304 }
1305
1306 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1307                             int buf_size)
1308 {
1309         int rc;
1310         u32 cmd_flags;
1311         __be32 val;
1312
1313         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1314                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1315                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1316                    offset, buf_size);
1317                 return -EINVAL;
1318         }
1319
1320         if (offset + buf_size > bp->common.flash_size) {
1321                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1322                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1323                    offset, buf_size, bp->common.flash_size);
1324                 return -EINVAL;
1325         }
1326
1327         /* request access to nvram interface */
1328         rc = bnx2x_acquire_nvram_lock(bp);
1329         if (rc)
1330                 return rc;
1331
1332         /* enable access to nvram interface */
1333         bnx2x_enable_nvram_access(bp);
1334
1335         /* read the first word(s) */
1336         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1337         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1338                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1339                 memcpy(ret_buf, &val, 4);
1340
1341                 /* advance to the next dword */
1342                 offset += sizeof(u32);
1343                 ret_buf += sizeof(u32);
1344                 buf_size -= sizeof(u32);
1345                 cmd_flags = 0;
1346         }
1347
1348         if (rc == 0) {
1349                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1350                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1351                 memcpy(ret_buf, &val, 4);
1352         }
1353
1354         /* disable access to nvram interface */
1355         bnx2x_disable_nvram_access(bp);
1356         bnx2x_release_nvram_lock(bp);
1357
1358         return rc;
1359 }
1360
1361 static int bnx2x_get_eeprom(struct net_device *dev,
1362                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1363 {
1364         struct bnx2x *bp = netdev_priv(dev);
1365         int rc;
1366
1367         if (!netif_running(dev)) {
1368                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1369                    "cannot access eeprom when the interface is down\n");
1370                 return -EAGAIN;
1371         }
1372
1373         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1374            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1375            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1376            eeprom->len, eeprom->len);
1377
1378         /* parameters already validated in ethtool_get_eeprom */
1379
1380         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1381
1382         return rc;
1383 }
1384
1385 static int bnx2x_get_module_eeprom(struct net_device *dev,
1386                                    struct ethtool_eeprom *ee,
1387                                    u8 *data)
1388 {
1389         struct bnx2x *bp = netdev_priv(dev);
1390         int rc = 0, phy_idx;
1391         u8 *user_data = data;
1392         int remaining_len = ee->len, xfer_size;
1393         unsigned int page_off = ee->offset;
1394
1395         if (!netif_running(dev)) {
1396                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1397                    "cannot access eeprom when the interface is down\n");
1398                 return -EAGAIN;
1399         }
1400
1401         phy_idx = bnx2x_get_cur_phy_idx(bp);
1402         bnx2x_acquire_phy_lock(bp);
1403         while (!rc && remaining_len > 0) {
1404                 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1405                         SFP_EEPROM_PAGE_SIZE : remaining_len;
1406                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1407                                                   &bp->link_params,
1408                                                   page_off,
1409                                                   xfer_size,
1410                                                   user_data);
1411                 remaining_len -= xfer_size;
1412                 user_data += xfer_size;
1413                 page_off += xfer_size;
1414         }
1415
1416         bnx2x_release_phy_lock(bp);
1417         return rc;
1418 }
1419
1420 static int bnx2x_get_module_info(struct net_device *dev,
1421                                  struct ethtool_modinfo *modinfo)
1422 {
1423         struct bnx2x *bp = netdev_priv(dev);
1424         int phy_idx;
1425         if (!netif_running(dev)) {
1426                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1427                    "cannot access eeprom when the interface is down\n");
1428                 return -EAGAIN;
1429         }
1430
1431         phy_idx = bnx2x_get_cur_phy_idx(bp);
1432         switch (bp->link_params.phy[phy_idx].media_type) {
1433         case ETH_PHY_SFPP_10G_FIBER:
1434         case ETH_PHY_SFP_1G_FIBER:
1435         case ETH_PHY_DA_TWINAX:
1436                 modinfo->type = ETH_MODULE_SFF_8079;
1437                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1438                 return 0;
1439         default:
1440                 return -EOPNOTSUPP;
1441         }
1442 }
1443
1444 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1445                                    u32 cmd_flags)
1446 {
1447         int count, i, rc;
1448
1449         /* build the command word */
1450         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1451
1452         /* need to clear DONE bit separately */
1453         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1454
1455         /* write the data */
1456         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1457
1458         /* address of the NVRAM to write to */
1459         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1460                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1461
1462         /* issue the write command */
1463         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1464
1465         /* adjust timeout for emulation/FPGA */
1466         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1467         if (CHIP_REV_IS_SLOW(bp))
1468                 count *= 100;
1469
1470         /* wait for completion */
1471         rc = -EBUSY;
1472         for (i = 0; i < count; i++) {
1473                 udelay(5);
1474                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1475                 if (val & MCPR_NVM_COMMAND_DONE) {
1476                         rc = 0;
1477                         break;
1478                 }
1479         }
1480
1481         if (rc == -EBUSY)
1482                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1483                    "nvram write timeout expired\n");
1484         return rc;
1485 }
1486
1487 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1488
1489 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1490                               int buf_size)
1491 {
1492         int rc;
1493         u32 cmd_flags;
1494         u32 align_offset;
1495         __be32 val;
1496
1497         if (offset + buf_size > bp->common.flash_size) {
1498                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1499                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1500                    offset, buf_size, bp->common.flash_size);
1501                 return -EINVAL;
1502         }
1503
1504         /* request access to nvram interface */
1505         rc = bnx2x_acquire_nvram_lock(bp);
1506         if (rc)
1507                 return rc;
1508
1509         /* enable access to nvram interface */
1510         bnx2x_enable_nvram_access(bp);
1511
1512         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1513         align_offset = (offset & ~0x03);
1514         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1515
1516         if (rc == 0) {
1517                 val &= ~(0xff << BYTE_OFFSET(offset));
1518                 val |= (*data_buf << BYTE_OFFSET(offset));
1519
1520                 /* nvram data is returned as an array of bytes
1521                  * convert it back to cpu order
1522                  */
1523                 val = be32_to_cpu(val);
1524
1525                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1526                                              cmd_flags);
1527         }
1528
1529         /* disable access to nvram interface */
1530         bnx2x_disable_nvram_access(bp);
1531         bnx2x_release_nvram_lock(bp);
1532
1533         return rc;
1534 }
1535
1536 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1537                              int buf_size)
1538 {
1539         int rc;
1540         u32 cmd_flags;
1541         u32 val;
1542         u32 written_so_far;
1543
1544         if (buf_size == 1)      /* ethtool */
1545                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1546
1547         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1548                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1549                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1550                    offset, buf_size);
1551                 return -EINVAL;
1552         }
1553
1554         if (offset + buf_size > bp->common.flash_size) {
1555                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1556                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1557                    offset, buf_size, bp->common.flash_size);
1558                 return -EINVAL;
1559         }
1560
1561         /* request access to nvram interface */
1562         rc = bnx2x_acquire_nvram_lock(bp);
1563         if (rc)
1564                 return rc;
1565
1566         /* enable access to nvram interface */
1567         bnx2x_enable_nvram_access(bp);
1568
1569         written_so_far = 0;
1570         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1571         while ((written_so_far < buf_size) && (rc == 0)) {
1572                 if (written_so_far == (buf_size - sizeof(u32)))
1573                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1574                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1575                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1576                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1577                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1578
1579                 memcpy(&val, data_buf, 4);
1580
1581                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1582
1583                 /* advance to the next dword */
1584                 offset += sizeof(u32);
1585                 data_buf += sizeof(u32);
1586                 written_so_far += sizeof(u32);
1587                 cmd_flags = 0;
1588         }
1589
1590         /* disable access to nvram interface */
1591         bnx2x_disable_nvram_access(bp);
1592         bnx2x_release_nvram_lock(bp);
1593
1594         return rc;
1595 }
1596
1597 static int bnx2x_set_eeprom(struct net_device *dev,
1598                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1599 {
1600         struct bnx2x *bp = netdev_priv(dev);
1601         int port = BP_PORT(bp);
1602         int rc = 0;
1603         u32 ext_phy_config;
1604         if (!netif_running(dev)) {
1605                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1606                    "cannot access eeprom when the interface is down\n");
1607                 return -EAGAIN;
1608         }
1609
1610         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1611            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1612            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1613            eeprom->len, eeprom->len);
1614
1615         /* parameters already validated in ethtool_set_eeprom */
1616
1617         /* PHY eeprom can be accessed only by the PMF */
1618         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1619             !bp->port.pmf) {
1620                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1621                    "wrong magic or interface is not pmf\n");
1622                 return -EINVAL;
1623         }
1624
1625         ext_phy_config =
1626                 SHMEM_RD(bp,
1627                          dev_info.port_hw_config[port].external_phy_config);
1628
1629         if (eeprom->magic == 0x50485950) {
1630                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1631                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1632
1633                 bnx2x_acquire_phy_lock(bp);
1634                 rc |= bnx2x_link_reset(&bp->link_params,
1635                                        &bp->link_vars, 0);
1636                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1637                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1638                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1639                                        MISC_REGISTERS_GPIO_HIGH, port);
1640                 bnx2x_release_phy_lock(bp);
1641                 bnx2x_link_report(bp);
1642
1643         } else if (eeprom->magic == 0x50485952) {
1644                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1645                 if (bp->state == BNX2X_STATE_OPEN) {
1646                         bnx2x_acquire_phy_lock(bp);
1647                         rc |= bnx2x_link_reset(&bp->link_params,
1648                                                &bp->link_vars, 1);
1649
1650                         rc |= bnx2x_phy_init(&bp->link_params,
1651                                              &bp->link_vars);
1652                         bnx2x_release_phy_lock(bp);
1653                         bnx2x_calc_fc_adv(bp);
1654                 }
1655         } else if (eeprom->magic == 0x53985943) {
1656                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1657                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1658                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1659
1660                         /* DSP Remove Download Mode */
1661                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1662                                        MISC_REGISTERS_GPIO_LOW, port);
1663
1664                         bnx2x_acquire_phy_lock(bp);
1665
1666                         bnx2x_sfx7101_sp_sw_reset(bp,
1667                                                 &bp->link_params.phy[EXT_PHY1]);
1668
1669                         /* wait 0.5 sec to allow it to run */
1670                         msleep(500);
1671                         bnx2x_ext_phy_hw_reset(bp, port);
1672                         msleep(500);
1673                         bnx2x_release_phy_lock(bp);
1674                 }
1675         } else
1676                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1677
1678         return rc;
1679 }
1680
1681 static int bnx2x_get_coalesce(struct net_device *dev,
1682                               struct ethtool_coalesce *coal)
1683 {
1684         struct bnx2x *bp = netdev_priv(dev);
1685
1686         memset(coal, 0, sizeof(struct ethtool_coalesce));
1687
1688         coal->rx_coalesce_usecs = bp->rx_ticks;
1689         coal->tx_coalesce_usecs = bp->tx_ticks;
1690
1691         return 0;
1692 }
1693
1694 static int bnx2x_set_coalesce(struct net_device *dev,
1695                               struct ethtool_coalesce *coal)
1696 {
1697         struct bnx2x *bp = netdev_priv(dev);
1698
1699         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1700         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1701                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1702
1703         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1704         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1705                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1706
1707         if (netif_running(dev))
1708                 bnx2x_update_coalesce(bp);
1709
1710         return 0;
1711 }
1712
1713 static void bnx2x_get_ringparam(struct net_device *dev,
1714                                 struct ethtool_ringparam *ering)
1715 {
1716         struct bnx2x *bp = netdev_priv(dev);
1717
1718         ering->rx_max_pending = MAX_RX_AVAIL;
1719
1720         if (bp->rx_ring_size)
1721                 ering->rx_pending = bp->rx_ring_size;
1722         else
1723                 ering->rx_pending = MAX_RX_AVAIL;
1724
1725         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1726         ering->tx_pending = bp->tx_ring_size;
1727 }
1728
1729 static int bnx2x_set_ringparam(struct net_device *dev,
1730                                struct ethtool_ringparam *ering)
1731 {
1732         struct bnx2x *bp = netdev_priv(dev);
1733
1734         DP(BNX2X_MSG_ETHTOOL,
1735            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1736            ering->rx_pending, ering->tx_pending);
1737
1738         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1739                 DP(BNX2X_MSG_ETHTOOL,
1740                    "Handling parity error recovery. Try again later\n");
1741                 return -EAGAIN;
1742         }
1743
1744         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1745             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1746                                                     MIN_RX_SIZE_TPA)) ||
1747             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1748             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1749                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1750                 return -EINVAL;
1751         }
1752
1753         bp->rx_ring_size = ering->rx_pending;
1754         bp->tx_ring_size = ering->tx_pending;
1755
1756         return bnx2x_reload_if_running(dev);
1757 }
1758
1759 static void bnx2x_get_pauseparam(struct net_device *dev,
1760                                  struct ethtool_pauseparam *epause)
1761 {
1762         struct bnx2x *bp = netdev_priv(dev);
1763         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1764         int cfg_reg;
1765
1766         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1767                            BNX2X_FLOW_CTRL_AUTO);
1768
1769         if (!epause->autoneg)
1770                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1771         else
1772                 cfg_reg = bp->link_params.req_fc_auto_adv;
1773
1774         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1775                             BNX2X_FLOW_CTRL_RX);
1776         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1777                             BNX2X_FLOW_CTRL_TX);
1778
1779         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1780            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1781            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1782 }
1783
1784 static int bnx2x_set_pauseparam(struct net_device *dev,
1785                                 struct ethtool_pauseparam *epause)
1786 {
1787         struct bnx2x *bp = netdev_priv(dev);
1788         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1789         if (IS_MF(bp))
1790                 return 0;
1791
1792         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1793            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1794            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1795
1796         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1797
1798         if (epause->rx_pause)
1799                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1800
1801         if (epause->tx_pause)
1802                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1803
1804         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1805                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1806
1807         if (epause->autoneg) {
1808                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1809                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1810                         return -EINVAL;
1811                 }
1812
1813                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1814                         bp->link_params.req_flow_ctrl[cfg_idx] =
1815                                 BNX2X_FLOW_CTRL_AUTO;
1816                 }
1817                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1818                 if (epause->rx_pause)
1819                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1820
1821                 if (epause->tx_pause)
1822                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1823         }
1824
1825         DP(BNX2X_MSG_ETHTOOL,
1826            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1827
1828         if (netif_running(dev)) {
1829                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1830                 bnx2x_link_set(bp);
1831         }
1832
1833         return 0;
1834 }
1835
1836 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1837         "register_test (offline)    ",
1838         "memory_test (offline)      ",
1839         "int_loopback_test (offline)",
1840         "ext_loopback_test (offline)",
1841         "nvram_test (online)        ",
1842         "interrupt_test (online)    ",
1843         "link_test (online)         "
1844 };
1845
1846 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1847 {
1848         u32 modes = 0;
1849
1850         if (eee_adv & SHMEM_EEE_100M_ADV)
1851                 modes |= ADVERTISED_100baseT_Full;
1852         if (eee_adv & SHMEM_EEE_1G_ADV)
1853                 modes |= ADVERTISED_1000baseT_Full;
1854         if (eee_adv & SHMEM_EEE_10G_ADV)
1855                 modes |= ADVERTISED_10000baseT_Full;
1856
1857         return modes;
1858 }
1859
1860 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1861 {
1862         u32 eee_adv = 0;
1863         if (modes & ADVERTISED_100baseT_Full)
1864                 eee_adv |= SHMEM_EEE_100M_ADV;
1865         if (modes & ADVERTISED_1000baseT_Full)
1866                 eee_adv |= SHMEM_EEE_1G_ADV;
1867         if (modes & ADVERTISED_10000baseT_Full)
1868                 eee_adv |= SHMEM_EEE_10G_ADV;
1869
1870         return eee_adv << shift;
1871 }
1872
1873 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1874 {
1875         struct bnx2x *bp = netdev_priv(dev);
1876         u32 eee_cfg;
1877
1878         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1879                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1880                 return -EOPNOTSUPP;
1881         }
1882
1883         eee_cfg = bp->link_vars.eee_status;
1884
1885         edata->supported =
1886                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1887                                  SHMEM_EEE_SUPPORTED_SHIFT);
1888
1889         edata->advertised =
1890                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1891                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1892         edata->lp_advertised =
1893                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1894                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1895
1896         /* SHMEM value is in 16u units --> Convert to 1u units. */
1897         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1898
1899         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1900         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1901         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1902
1903         return 0;
1904 }
1905
1906 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1907 {
1908         struct bnx2x *bp = netdev_priv(dev);
1909         u32 eee_cfg;
1910         u32 advertised;
1911
1912         if (IS_MF(bp))
1913                 return 0;
1914
1915         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1916                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1917                 return -EOPNOTSUPP;
1918         }
1919
1920         eee_cfg = bp->link_vars.eee_status;
1921
1922         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1923                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1924                 return -EOPNOTSUPP;
1925         }
1926
1927         advertised = bnx2x_adv_to_eee(edata->advertised,
1928                                       SHMEM_EEE_ADV_STATUS_SHIFT);
1929         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1930                 DP(BNX2X_MSG_ETHTOOL,
1931                    "Direct manipulation of EEE advertisement is not supported\n");
1932                 return -EINVAL;
1933         }
1934
1935         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1936                 DP(BNX2X_MSG_ETHTOOL,
1937                    "Maximal Tx Lpi timer supported is %x(u)\n",
1938                    EEE_MODE_TIMER_MASK);
1939                 return -EINVAL;
1940         }
1941         if (edata->tx_lpi_enabled &&
1942             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1943                 DP(BNX2X_MSG_ETHTOOL,
1944                    "Minimal Tx Lpi timer supported is %d(u)\n",
1945                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1946                 return -EINVAL;
1947         }
1948
1949         /* All is well; Apply changes*/
1950         if (edata->eee_enabled)
1951                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1952         else
1953                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1954
1955         if (edata->tx_lpi_enabled)
1956                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1957         else
1958                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1959
1960         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1961         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1962                                     EEE_MODE_TIMER_MASK) |
1963                                     EEE_MODE_OVERRIDE_NVRAM |
1964                                     EEE_MODE_OUTPUT_TIME;
1965
1966         /* Restart link to propogate changes */
1967         if (netif_running(dev)) {
1968                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1969                 bnx2x_force_link_reset(bp);
1970                 bnx2x_link_set(bp);
1971         }
1972
1973         return 0;
1974 }
1975
1976 enum {
1977         BNX2X_CHIP_E1_OFST = 0,
1978         BNX2X_CHIP_E1H_OFST,
1979         BNX2X_CHIP_E2_OFST,
1980         BNX2X_CHIP_E3_OFST,
1981         BNX2X_CHIP_E3B0_OFST,
1982         BNX2X_CHIP_MAX_OFST
1983 };
1984
1985 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1986 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1987 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1988 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1989 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1990
1991 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1992 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1993
1994 static int bnx2x_test_registers(struct bnx2x *bp)
1995 {
1996         int idx, i, rc = -ENODEV;
1997         u32 wr_val = 0, hw;
1998         int port = BP_PORT(bp);
1999         static const struct {
2000                 u32 hw;
2001                 u32 offset0;
2002                 u32 offset1;
2003                 u32 mask;
2004         } reg_tbl[] = {
2005 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2006                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2007                 { BNX2X_CHIP_MASK_ALL,
2008                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2009                 { BNX2X_CHIP_MASK_E1X,
2010                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2011                 { BNX2X_CHIP_MASK_ALL,
2012                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2013                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2014                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2015                 { BNX2X_CHIP_MASK_E3B0,
2016                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2017                 { BNX2X_CHIP_MASK_ALL,
2018                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2019                 { BNX2X_CHIP_MASK_ALL,
2020                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2021                 { BNX2X_CHIP_MASK_ALL,
2022                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2023                 { BNX2X_CHIP_MASK_ALL,
2024                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2025 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2026                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2027                 { BNX2X_CHIP_MASK_ALL,
2028                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2029                 { BNX2X_CHIP_MASK_ALL,
2030                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2031                 { BNX2X_CHIP_MASK_ALL,
2032                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2033                 { BNX2X_CHIP_MASK_ALL,
2034                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2035                 { BNX2X_CHIP_MASK_ALL,
2036                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2037                 { BNX2X_CHIP_MASK_ALL,
2038                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2039                 { BNX2X_CHIP_MASK_ALL,
2040                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2041                 { BNX2X_CHIP_MASK_ALL,
2042                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2043                 { BNX2X_CHIP_MASK_ALL,
2044                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2045 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2046                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2047                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2048                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2049                 { BNX2X_CHIP_MASK_ALL,
2050                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2051                 { BNX2X_CHIP_MASK_ALL,
2052                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2053                 { BNX2X_CHIP_MASK_ALL,
2054                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2055                 { BNX2X_CHIP_MASK_ALL,
2056                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2057                 { BNX2X_CHIP_MASK_ALL,
2058                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2059                 { BNX2X_CHIP_MASK_ALL,
2060                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2061                 { BNX2X_CHIP_MASK_ALL,
2062                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2063                 { BNX2X_CHIP_MASK_ALL,
2064                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2065 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2066                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2067                 { BNX2X_CHIP_MASK_ALL,
2068                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2069                 { BNX2X_CHIP_MASK_ALL,
2070                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2071                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2072                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2073                 { BNX2X_CHIP_MASK_ALL,
2074                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2075                 { BNX2X_CHIP_MASK_ALL,
2076                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2077                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2078                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2079                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2080                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2081
2082                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2083         };
2084
2085         if (!netif_running(bp->dev)) {
2086                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2087                    "cannot access eeprom when the interface is down\n");
2088                 return rc;
2089         }
2090
2091         if (CHIP_IS_E1(bp))
2092                 hw = BNX2X_CHIP_MASK_E1;
2093         else if (CHIP_IS_E1H(bp))
2094                 hw = BNX2X_CHIP_MASK_E1H;
2095         else if (CHIP_IS_E2(bp))
2096                 hw = BNX2X_CHIP_MASK_E2;
2097         else if (CHIP_IS_E3B0(bp))
2098                 hw = BNX2X_CHIP_MASK_E3B0;
2099         else /* e3 A0 */
2100                 hw = BNX2X_CHIP_MASK_E3;
2101
2102         /* Repeat the test twice:
2103          * First by writing 0x00000000, second by writing 0xffffffff
2104          */
2105         for (idx = 0; idx < 2; idx++) {
2106
2107                 switch (idx) {
2108                 case 0:
2109                         wr_val = 0;
2110                         break;
2111                 case 1:
2112                         wr_val = 0xffffffff;
2113                         break;
2114                 }
2115
2116                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2117                         u32 offset, mask, save_val, val;
2118                         if (!(hw & reg_tbl[i].hw))
2119                                 continue;
2120
2121                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2122                         mask = reg_tbl[i].mask;
2123
2124                         save_val = REG_RD(bp, offset);
2125
2126                         REG_WR(bp, offset, wr_val & mask);
2127
2128                         val = REG_RD(bp, offset);
2129
2130                         /* Restore the original register's value */
2131                         REG_WR(bp, offset, save_val);
2132
2133                         /* verify value is as expected */
2134                         if ((val & mask) != (wr_val & mask)) {
2135                                 DP(BNX2X_MSG_ETHTOOL,
2136                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2137                                    offset, val, wr_val, mask);
2138                                 goto test_reg_exit;
2139                         }
2140                 }
2141         }
2142
2143         rc = 0;
2144
2145 test_reg_exit:
2146         return rc;
2147 }
2148
2149 static int bnx2x_test_memory(struct bnx2x *bp)
2150 {
2151         int i, j, rc = -ENODEV;
2152         u32 val, index;
2153         static const struct {
2154                 u32 offset;
2155                 int size;
2156         } mem_tbl[] = {
2157                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2158                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2159                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2160                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2161                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2162                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2163                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2164
2165                 { 0xffffffff, 0 }
2166         };
2167
2168         static const struct {
2169                 char *name;
2170                 u32 offset;
2171                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2172         } prty_tbl[] = {
2173                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2174                         {0x3ffc0, 0,   0, 0} },
2175                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2176                         {0x2,     0x2, 0, 0} },
2177                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2178                         {0,       0,   0, 0} },
2179                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2180                         {0x3ffc0, 0,   0, 0} },
2181                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2182                         {0x3ffc0, 0,   0, 0} },
2183                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2184                         {0x3ffc1, 0,   0, 0} },
2185
2186                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2187         };
2188
2189         if (!netif_running(bp->dev)) {
2190                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2191                    "cannot access eeprom when the interface is down\n");
2192                 return rc;
2193         }
2194
2195         if (CHIP_IS_E1(bp))
2196                 index = BNX2X_CHIP_E1_OFST;
2197         else if (CHIP_IS_E1H(bp))
2198                 index = BNX2X_CHIP_E1H_OFST;
2199         else if (CHIP_IS_E2(bp))
2200                 index = BNX2X_CHIP_E2_OFST;
2201         else /* e3 */
2202                 index = BNX2X_CHIP_E3_OFST;
2203
2204         /* pre-Check the parity status */
2205         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2206                 val = REG_RD(bp, prty_tbl[i].offset);
2207                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2208                         DP(BNX2X_MSG_ETHTOOL,
2209                            "%s is 0x%x\n", prty_tbl[i].name, val);
2210                         goto test_mem_exit;
2211                 }
2212         }
2213
2214         /* Go through all the memories */
2215         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2216                 for (j = 0; j < mem_tbl[i].size; j++)
2217                         REG_RD(bp, mem_tbl[i].offset + j*4);
2218
2219         /* Check the parity status */
2220         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2221                 val = REG_RD(bp, prty_tbl[i].offset);
2222                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2223                         DP(BNX2X_MSG_ETHTOOL,
2224                            "%s is 0x%x\n", prty_tbl[i].name, val);
2225                         goto test_mem_exit;
2226                 }
2227         }
2228
2229         rc = 0;
2230
2231 test_mem_exit:
2232         return rc;
2233 }
2234
2235 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2236 {
2237         int cnt = 1400;
2238
2239         if (link_up) {
2240                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2241                         msleep(20);
2242
2243                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2244                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2245
2246                 cnt = 1400;
2247                 while (!bp->link_vars.link_up && cnt--)
2248                         msleep(20);
2249
2250                 if (cnt <= 0 && !bp->link_vars.link_up)
2251                         DP(BNX2X_MSG_ETHTOOL,
2252                            "Timeout waiting for link init\n");
2253         }
2254 }
2255
2256 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2257 {
2258         unsigned int pkt_size, num_pkts, i;
2259         struct sk_buff *skb;
2260         unsigned char *packet;
2261         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2262         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2263         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2264         u16 tx_start_idx, tx_idx;
2265         u16 rx_start_idx, rx_idx;
2266         u16 pkt_prod, bd_prod;
2267         struct sw_tx_bd *tx_buf;
2268         struct eth_tx_start_bd *tx_start_bd;
2269         dma_addr_t mapping;
2270         union eth_rx_cqe *cqe;
2271         u8 cqe_fp_flags, cqe_fp_type;
2272         struct sw_rx_bd *rx_buf;
2273         u16 len;
2274         int rc = -ENODEV;
2275         u8 *data;
2276         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2277                                                        txdata->txq_index);
2278
2279         /* check the loopback mode */
2280         switch (loopback_mode) {
2281         case BNX2X_PHY_LOOPBACK:
2282                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2283                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2284                         return -EINVAL;
2285                 }
2286                 break;
2287         case BNX2X_MAC_LOOPBACK:
2288                 if (CHIP_IS_E3(bp)) {
2289                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2290                         if (bp->port.supported[cfg_idx] &
2291                             (SUPPORTED_10000baseT_Full |
2292                              SUPPORTED_20000baseMLD2_Full |
2293                              SUPPORTED_20000baseKR2_Full))
2294                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2295                         else
2296                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2297                 } else
2298                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2299
2300                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2301                 break;
2302         case BNX2X_EXT_LOOPBACK:
2303                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2304                         DP(BNX2X_MSG_ETHTOOL,
2305                            "Can't configure external loopback\n");
2306                         return -EINVAL;
2307                 }
2308                 break;
2309         default:
2310                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2311                 return -EINVAL;
2312         }
2313
2314         /* prepare the loopback packet */
2315         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2316                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2317         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2318         if (!skb) {
2319                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2320                 rc = -ENOMEM;
2321                 goto test_loopback_exit;
2322         }
2323         packet = skb_put(skb, pkt_size);
2324         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2325         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2326         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2327         for (i = ETH_HLEN; i < pkt_size; i++)
2328                 packet[i] = (unsigned char) (i & 0xff);
2329         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2330                                  skb_headlen(skb), DMA_TO_DEVICE);
2331         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2332                 rc = -ENOMEM;
2333                 dev_kfree_skb(skb);
2334                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2335                 goto test_loopback_exit;
2336         }
2337
2338         /* send the loopback packet */
2339         num_pkts = 0;
2340         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2341         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2342
2343         netdev_tx_sent_queue(txq, skb->len);
2344
2345         pkt_prod = txdata->tx_pkt_prod++;
2346         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2347         tx_buf->first_bd = txdata->tx_bd_prod;
2348         tx_buf->skb = skb;
2349         tx_buf->flags = 0;
2350
2351         bd_prod = TX_BD(txdata->tx_bd_prod);
2352         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2353         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2354         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2355         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2356         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2357         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2358         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2359         SET_FLAG(tx_start_bd->general_data,
2360                  ETH_TX_START_BD_HDR_NBDS,
2361                  1);
2362         SET_FLAG(tx_start_bd->general_data,
2363                  ETH_TX_START_BD_PARSE_NBDS,
2364                  0);
2365
2366         /* turn on parsing and get a BD */
2367         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2368
2369         if (CHIP_IS_E1x(bp)) {
2370                 u16 global_data = 0;
2371                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2372                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2373                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2374                 SET_FLAG(global_data,
2375                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2376                 pbd_e1x->global_data = cpu_to_le16(global_data);
2377         } else {
2378                 u32 parsing_data = 0;
2379                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2380                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2381                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2382                 SET_FLAG(parsing_data,
2383                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2384                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2385         }
2386         wmb();
2387
2388         txdata->tx_db.data.prod += 2;
2389         barrier();
2390         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2391
2392         mmiowb();
2393         barrier();
2394
2395         num_pkts++;
2396         txdata->tx_bd_prod += 2; /* start + pbd */
2397
2398         udelay(100);
2399
2400         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2401         if (tx_idx != tx_start_idx + num_pkts)
2402                 goto test_loopback_exit;
2403
2404         /* Unlike HC IGU won't generate an interrupt for status block
2405          * updates that have been performed while interrupts were
2406          * disabled.
2407          */
2408         if (bp->common.int_block == INT_BLOCK_IGU) {
2409                 /* Disable local BHes to prevent a dead-lock situation between
2410                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2411                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2412                  */
2413                 local_bh_disable();
2414                 bnx2x_tx_int(bp, txdata);
2415                 local_bh_enable();
2416         }
2417
2418         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2419         if (rx_idx != rx_start_idx + num_pkts)
2420                 goto test_loopback_exit;
2421
2422         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2423         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2424         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2425         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2426                 goto test_loopback_rx_exit;
2427
2428         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2429         if (len != pkt_size)
2430                 goto test_loopback_rx_exit;
2431
2432         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2433         dma_sync_single_for_cpu(&bp->pdev->dev,
2434                                    dma_unmap_addr(rx_buf, mapping),
2435                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2436         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2437         for (i = ETH_HLEN; i < pkt_size; i++)
2438                 if (*(data + i) != (unsigned char) (i & 0xff))
2439                         goto test_loopback_rx_exit;
2440
2441         rc = 0;
2442
2443 test_loopback_rx_exit:
2444
2445         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2446         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2447         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2448         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2449
2450         /* Update producers */
2451         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2452                              fp_rx->rx_sge_prod);
2453
2454 test_loopback_exit:
2455         bp->link_params.loopback_mode = LOOPBACK_NONE;
2456
2457         return rc;
2458 }
2459
2460 static int bnx2x_test_loopback(struct bnx2x *bp)
2461 {
2462         int rc = 0, res;
2463
2464         if (BP_NOMCP(bp))
2465                 return rc;
2466
2467         if (!netif_running(bp->dev))
2468                 return BNX2X_LOOPBACK_FAILED;
2469
2470         bnx2x_netif_stop(bp, 1);
2471         bnx2x_acquire_phy_lock(bp);
2472
2473         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2474         if (res) {
2475                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2476                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2477         }
2478
2479         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2480         if (res) {
2481                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2482                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2483         }
2484
2485         bnx2x_release_phy_lock(bp);
2486         bnx2x_netif_start(bp);
2487
2488         return rc;
2489 }
2490
2491 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2492 {
2493         int rc;
2494         u8 is_serdes =
2495                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2496
2497         if (BP_NOMCP(bp))
2498                 return -ENODEV;
2499
2500         if (!netif_running(bp->dev))
2501                 return BNX2X_EXT_LOOPBACK_FAILED;
2502
2503         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2504         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2505         if (rc) {
2506                 DP(BNX2X_MSG_ETHTOOL,
2507                    "Can't perform self-test, nic_load (for external lb) failed\n");
2508                 return -ENODEV;
2509         }
2510         bnx2x_wait_for_link(bp, 1, is_serdes);
2511
2512         bnx2x_netif_stop(bp, 1);
2513
2514         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2515         if (rc)
2516                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2517
2518         bnx2x_netif_start(bp);
2519
2520         return rc;
2521 }
2522
2523 #define CRC32_RESIDUAL                  0xdebb20e3
2524
2525 static int bnx2x_test_nvram(struct bnx2x *bp)
2526 {
2527         static const struct {
2528                 int offset;
2529                 int size;
2530         } nvram_tbl[] = {
2531                 {     0,  0x14 }, /* bootstrap */
2532                 {  0x14,  0xec }, /* dir */
2533                 { 0x100, 0x350 }, /* manuf_info */
2534                 { 0x450,  0xf0 }, /* feature_info */
2535                 { 0x640,  0x64 }, /* upgrade_key_info */
2536                 { 0x708,  0x70 }, /* manuf_key_info */
2537                 {     0,     0 }
2538         };
2539         __be32 *buf;
2540         u8 *data;
2541         int i, rc;
2542         u32 magic, crc;
2543
2544         if (BP_NOMCP(bp))
2545                 return 0;
2546
2547         buf = kmalloc(0x350, GFP_KERNEL);
2548         if (!buf) {
2549                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2550                 rc = -ENOMEM;
2551                 goto test_nvram_exit;
2552         }
2553         data = (u8 *)buf;
2554
2555         rc = bnx2x_nvram_read(bp, 0, data, 4);
2556         if (rc) {
2557                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2558                    "magic value read (rc %d)\n", rc);
2559                 goto test_nvram_exit;
2560         }
2561
2562         magic = be32_to_cpu(buf[0]);
2563         if (magic != 0x669955aa) {
2564                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2565                    "wrong magic value (0x%08x)\n", magic);
2566                 rc = -ENODEV;
2567                 goto test_nvram_exit;
2568         }
2569
2570         for (i = 0; nvram_tbl[i].size; i++) {
2571
2572                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2573                                       nvram_tbl[i].size);
2574                 if (rc) {
2575                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2576                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2577                         goto test_nvram_exit;
2578                 }
2579
2580                 crc = ether_crc_le(nvram_tbl[i].size, data);
2581                 if (crc != CRC32_RESIDUAL) {
2582                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2583                            "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2584                         rc = -ENODEV;
2585                         goto test_nvram_exit;
2586                 }
2587         }
2588
2589 test_nvram_exit:
2590         kfree(buf);
2591         return rc;
2592 }
2593
2594 /* Send an EMPTY ramrod on the first queue */
2595 static int bnx2x_test_intr(struct bnx2x *bp)
2596 {
2597         struct bnx2x_queue_state_params params = {NULL};
2598
2599         if (!netif_running(bp->dev)) {
2600                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2601                    "cannot access eeprom when the interface is down\n");
2602                 return -ENODEV;
2603         }
2604
2605         params.q_obj = &bp->sp_objs->q_obj;
2606         params.cmd = BNX2X_Q_CMD_EMPTY;
2607
2608         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2609
2610         return bnx2x_queue_state_change(bp, &params);
2611 }
2612
2613 static void bnx2x_self_test(struct net_device *dev,
2614                             struct ethtool_test *etest, u64 *buf)
2615 {
2616         struct bnx2x *bp = netdev_priv(dev);
2617         u8 is_serdes, link_up;
2618         int rc, cnt = 0;
2619
2620         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2621                 netdev_err(bp->dev,
2622                            "Handling parity error recovery. Try again later\n");
2623                 etest->flags |= ETH_TEST_FL_FAILED;
2624                 return;
2625         }
2626
2627         DP(BNX2X_MSG_ETHTOOL,
2628            "Self-test command parameters: offline = %d, external_lb = %d\n",
2629            (etest->flags & ETH_TEST_FL_OFFLINE),
2630            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2631
2632         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2633
2634         if (!netif_running(dev)) {
2635                 DP(BNX2X_MSG_ETHTOOL,
2636                    "Can't perform self-test when interface is down\n");
2637                 return;
2638         }
2639
2640         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2641         link_up = bp->link_vars.link_up;
2642         /* offline tests are not supported in MF mode */
2643         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2644                 int port = BP_PORT(bp);
2645                 u32 val;
2646
2647                 /* save current value of input enable for TX port IF */
2648                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2649                 /* disable input for TX port IF */
2650                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2651
2652                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2653                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2654                 if (rc) {
2655                         etest->flags |= ETH_TEST_FL_FAILED;
2656                         DP(BNX2X_MSG_ETHTOOL,
2657                            "Can't perform self-test, nic_load (for offline) failed\n");
2658                         return;
2659                 }
2660
2661                 /* wait until link state is restored */
2662                 bnx2x_wait_for_link(bp, 1, is_serdes);
2663
2664                 if (bnx2x_test_registers(bp) != 0) {
2665                         buf[0] = 1;
2666                         etest->flags |= ETH_TEST_FL_FAILED;
2667                 }
2668                 if (bnx2x_test_memory(bp) != 0) {
2669                         buf[1] = 1;
2670                         etest->flags |= ETH_TEST_FL_FAILED;
2671                 }
2672
2673                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2674                 if (buf[2] != 0)
2675                         etest->flags |= ETH_TEST_FL_FAILED;
2676
2677                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2678                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2679                         if (buf[3] != 0)
2680                                 etest->flags |= ETH_TEST_FL_FAILED;
2681                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2682                 }
2683
2684                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2685
2686                 /* restore input for TX port IF */
2687                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2688                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2689                 if (rc) {
2690                         etest->flags |= ETH_TEST_FL_FAILED;
2691                         DP(BNX2X_MSG_ETHTOOL,
2692                            "Can't perform self-test, nic_load (for online) failed\n");
2693                         return;
2694                 }
2695                 /* wait until link state is restored */
2696                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2697         }
2698         if (bnx2x_test_nvram(bp) != 0) {
2699                 if (!IS_MF(bp))
2700                         buf[4] = 1;
2701                 else
2702                         buf[0] = 1;
2703                 etest->flags |= ETH_TEST_FL_FAILED;
2704         }
2705         if (bnx2x_test_intr(bp) != 0) {
2706                 if (!IS_MF(bp))
2707                         buf[5] = 1;
2708                 else
2709                         buf[1] = 1;
2710                 etest->flags |= ETH_TEST_FL_FAILED;
2711         }
2712
2713         if (link_up) {
2714                 cnt = 100;
2715                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2716                         msleep(20);
2717         }
2718
2719         if (!cnt) {
2720                 if (!IS_MF(bp))
2721                         buf[6] = 1;
2722                 else
2723                         buf[2] = 1;
2724                 etest->flags |= ETH_TEST_FL_FAILED;
2725         }
2726 }
2727
2728 #define IS_PORT_STAT(i) \
2729         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2730 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2731 #define IS_MF_MODE_STAT(bp) \
2732                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2733
2734 /* ethtool statistics are displayed for all regular ethernet queues and the
2735  * fcoe L2 queue if not disabled
2736  */
2737 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2738 {
2739         return BNX2X_NUM_ETH_QUEUES(bp);
2740 }
2741
2742 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2743 {
2744         struct bnx2x *bp = netdev_priv(dev);
2745         int i, num_stats;
2746
2747         switch (stringset) {
2748         case ETH_SS_STATS:
2749                 if (is_multi(bp)) {
2750                         num_stats = bnx2x_num_stat_queues(bp) *
2751                                                 BNX2X_NUM_Q_STATS;
2752                 } else
2753                         num_stats = 0;
2754                 if (IS_MF_MODE_STAT(bp)) {
2755                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2756                                 if (IS_FUNC_STAT(i))
2757                                         num_stats++;
2758                 } else
2759                         num_stats += BNX2X_NUM_STATS;
2760
2761                 return num_stats;
2762
2763         case ETH_SS_TEST:
2764                 return BNX2X_NUM_TESTS(bp);
2765
2766         default:
2767                 return -EINVAL;
2768         }
2769 }
2770
2771 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2772 {
2773         struct bnx2x *bp = netdev_priv(dev);
2774         int i, j, k, start;
2775         char queue_name[MAX_QUEUE_NAME_LEN+1];
2776
2777         switch (stringset) {
2778         case ETH_SS_STATS:
2779                 k = 0;
2780                 if (is_multi(bp)) {
2781                         for_each_eth_queue(bp, i) {
2782                                 memset(queue_name, 0, sizeof(queue_name));
2783                                 sprintf(queue_name, "%d", i);
2784                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2785                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2786                                                 ETH_GSTRING_LEN,
2787                                                 bnx2x_q_stats_arr[j].string,
2788                                                 queue_name);
2789                                 k += BNX2X_NUM_Q_STATS;
2790                         }
2791                 }
2792
2793
2794                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2795                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2796                                 continue;
2797                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2798                                    bnx2x_stats_arr[i].string);
2799                         j++;
2800                 }
2801
2802                 break;
2803
2804         case ETH_SS_TEST:
2805                 /* First 4 tests cannot be done in MF mode */
2806                 if (!IS_MF(bp))
2807                         start = 0;
2808                 else
2809                         start = 4;
2810                 memcpy(buf, bnx2x_tests_str_arr + start,
2811                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
2812         }
2813 }
2814
2815 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2816                                     struct ethtool_stats *stats, u64 *buf)
2817 {
2818         struct bnx2x *bp = netdev_priv(dev);
2819         u32 *hw_stats, *offset;
2820         int i, j, k = 0;
2821
2822         if (is_multi(bp)) {
2823                 for_each_eth_queue(bp, i) {
2824                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
2825                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2826                                 if (bnx2x_q_stats_arr[j].size == 0) {
2827                                         /* skip this counter */
2828                                         buf[k + j] = 0;
2829                                         continue;
2830                                 }
2831                                 offset = (hw_stats +
2832                                           bnx2x_q_stats_arr[j].offset);
2833                                 if (bnx2x_q_stats_arr[j].size == 4) {
2834                                         /* 4-byte counter */
2835                                         buf[k + j] = (u64) *offset;
2836                                         continue;
2837                                 }
2838                                 /* 8-byte counter */
2839                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2840                         }
2841                         k += BNX2X_NUM_Q_STATS;
2842                 }
2843         }
2844
2845         hw_stats = (u32 *)&bp->eth_stats;
2846         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2847                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2848                         continue;
2849                 if (bnx2x_stats_arr[i].size == 0) {
2850                         /* skip this counter */
2851                         buf[k + j] = 0;
2852                         j++;
2853                         continue;
2854                 }
2855                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2856                 if (bnx2x_stats_arr[i].size == 4) {
2857                         /* 4-byte counter */
2858                         buf[k + j] = (u64) *offset;
2859                         j++;
2860                         continue;
2861                 }
2862                 /* 8-byte counter */
2863                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2864                 j++;
2865         }
2866 }
2867
2868 static int bnx2x_set_phys_id(struct net_device *dev,
2869                              enum ethtool_phys_id_state state)
2870 {
2871         struct bnx2x *bp = netdev_priv(dev);
2872
2873         if (!netif_running(dev)) {
2874                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2875                    "cannot access eeprom when the interface is down\n");
2876                 return -EAGAIN;
2877         }
2878
2879         if (!bp->port.pmf) {
2880                 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2881                 return -EOPNOTSUPP;
2882         }
2883
2884         switch (state) {
2885         case ETHTOOL_ID_ACTIVE:
2886                 return 1;       /* cycle on/off once per second */
2887
2888         case ETHTOOL_ID_ON:
2889                 bnx2x_acquire_phy_lock(bp);
2890                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2891                               LED_MODE_ON, SPEED_1000);
2892                 bnx2x_release_phy_lock(bp);
2893                 break;
2894
2895         case ETHTOOL_ID_OFF:
2896                 bnx2x_acquire_phy_lock(bp);
2897                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2898                               LED_MODE_FRONT_PANEL_OFF, 0);
2899                 bnx2x_release_phy_lock(bp);
2900                 break;
2901
2902         case ETHTOOL_ID_INACTIVE:
2903                 bnx2x_acquire_phy_lock(bp);
2904                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2905                               LED_MODE_OPER,
2906                               bp->link_vars.line_speed);
2907                 bnx2x_release_phy_lock(bp);
2908         }
2909
2910         return 0;
2911 }
2912
2913 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2914 {
2915
2916         switch (info->flow_type) {
2917         case TCP_V4_FLOW:
2918         case TCP_V6_FLOW:
2919                 info->data = RXH_IP_SRC | RXH_IP_DST |
2920                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2921                 break;
2922         case UDP_V4_FLOW:
2923                 if (bp->rss_conf_obj.udp_rss_v4)
2924                         info->data = RXH_IP_SRC | RXH_IP_DST |
2925                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2926                 else
2927                         info->data = RXH_IP_SRC | RXH_IP_DST;
2928                 break;
2929         case UDP_V6_FLOW:
2930                 if (bp->rss_conf_obj.udp_rss_v6)
2931                         info->data = RXH_IP_SRC | RXH_IP_DST |
2932                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2933                 else
2934                         info->data = RXH_IP_SRC | RXH_IP_DST;
2935                 break;
2936         case IPV4_FLOW:
2937         case IPV6_FLOW:
2938                 info->data = RXH_IP_SRC | RXH_IP_DST;
2939                 break;
2940         default:
2941                 info->data = 0;
2942                 break;
2943         }
2944
2945         return 0;
2946 }
2947
2948 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2949                            u32 *rules __always_unused)
2950 {
2951         struct bnx2x *bp = netdev_priv(dev);
2952
2953         switch (info->cmd) {
2954         case ETHTOOL_GRXRINGS:
2955                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2956                 return 0;
2957         case ETHTOOL_GRXFH:
2958                 return bnx2x_get_rss_flags(bp, info);
2959         default:
2960                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2961                 return -EOPNOTSUPP;
2962         }
2963 }
2964
2965 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2966 {
2967         int udp_rss_requested;
2968
2969         DP(BNX2X_MSG_ETHTOOL,
2970            "Set rss flags command parameters: flow type = %d, data = %llu\n",
2971            info->flow_type, info->data);
2972
2973         switch (info->flow_type) {
2974         case TCP_V4_FLOW:
2975         case TCP_V6_FLOW:
2976                 /* For TCP only 4-tupple hash is supported */
2977                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2978                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2979                         DP(BNX2X_MSG_ETHTOOL,
2980                            "Command parameters not supported\n");
2981                         return -EINVAL;
2982                 }
2983                 return 0;
2984
2985         case UDP_V4_FLOW:
2986         case UDP_V6_FLOW:
2987                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2988                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2989                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
2990                         udp_rss_requested = 1;
2991                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2992                         udp_rss_requested = 0;
2993                 else
2994                         return -EINVAL;
2995                 if ((info->flow_type == UDP_V4_FLOW) &&
2996                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2997                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2998                         DP(BNX2X_MSG_ETHTOOL,
2999                            "rss re-configured, UDP 4-tupple %s\n",
3000                            udp_rss_requested ? "enabled" : "disabled");
3001                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3002                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3003                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3004                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3005                         DP(BNX2X_MSG_ETHTOOL,
3006                            "rss re-configured, UDP 4-tupple %s\n",
3007                            udp_rss_requested ? "enabled" : "disabled");
3008                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3009                 }
3010                 return 0;
3011
3012         case IPV4_FLOW:
3013         case IPV6_FLOW:
3014                 /* For IP only 2-tupple hash is supported */
3015                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3016                         DP(BNX2X_MSG_ETHTOOL,
3017                            "Command parameters not supported\n");
3018                         return -EINVAL;
3019                 }
3020                 return 0;
3021
3022         case SCTP_V4_FLOW:
3023         case AH_ESP_V4_FLOW:
3024         case AH_V4_FLOW:
3025         case ESP_V4_FLOW:
3026         case SCTP_V6_FLOW:
3027         case AH_ESP_V6_FLOW:
3028         case AH_V6_FLOW:
3029         case ESP_V6_FLOW:
3030         case IP_USER_FLOW:
3031         case ETHER_FLOW:
3032                 /* RSS is not supported for these protocols */
3033                 if (info->data) {
3034                         DP(BNX2X_MSG_ETHTOOL,
3035                            "Command parameters not supported\n");
3036                         return -EINVAL;
3037                 }
3038                 return 0;
3039
3040         default:
3041                 return -EINVAL;
3042         }
3043 }
3044
3045 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3046 {
3047         struct bnx2x *bp = netdev_priv(dev);
3048
3049         switch (info->cmd) {
3050         case ETHTOOL_SRXFH:
3051                 return bnx2x_set_rss_flags(bp, info);
3052         default:
3053                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3054                 return -EOPNOTSUPP;
3055         }
3056 }
3057
3058 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3059 {
3060         return T_ETH_INDIRECTION_TABLE_SIZE;
3061 }
3062
3063 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
3064 {
3065         struct bnx2x *bp = netdev_priv(dev);
3066         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3067         size_t i;
3068
3069         /* Get the current configuration of the RSS indirection table */
3070         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3071
3072         /*
3073          * We can't use a memcpy() as an internal storage of an
3074          * indirection table is a u8 array while indir->ring_index
3075          * points to an array of u32.
3076          *
3077          * Indirection table contains the FW Client IDs, so we need to
3078          * align the returned table to the Client ID of the leading RSS
3079          * queue.
3080          */
3081         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3082                 indir[i] = ind_table[i] - bp->fp->cl_id;
3083
3084         return 0;
3085 }
3086
3087 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
3088 {
3089         struct bnx2x *bp = netdev_priv(dev);
3090         size_t i;
3091
3092         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3093                 /*
3094                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3095                  * as an internal storage of an indirection table is a u8 array
3096                  * while indir->ring_index points to an array of u32.
3097                  *
3098                  * Indirection table contains the FW Client IDs, so we need to
3099                  * align the received table to the Client ID of the leading RSS
3100                  * queue
3101                  */
3102                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3103         }
3104
3105         return bnx2x_config_rss_eth(bp, false);
3106 }
3107
3108 /**
3109  * bnx2x_get_channels - gets the number of RSS queues.
3110  *
3111  * @dev:                net device
3112  * @channels:           returns the number of max / current queues
3113  */
3114 static void bnx2x_get_channels(struct net_device *dev,
3115                                struct ethtool_channels *channels)
3116 {
3117         struct bnx2x *bp = netdev_priv(dev);
3118
3119         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3120         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3121 }
3122
3123 /**
3124  * bnx2x_change_num_queues - change the number of RSS queues.
3125  *
3126  * @bp:                 bnx2x private structure
3127  *
3128  * Re-configure interrupt mode to get the new number of MSI-X
3129  * vectors and re-add NAPI objects.
3130  */
3131 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3132 {
3133         bnx2x_disable_msi(bp);
3134         bp->num_ethernet_queues = num_rss;
3135         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3136         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3137         bnx2x_set_int_mode(bp);
3138 }
3139
3140 /**
3141  * bnx2x_set_channels - sets the number of RSS queues.
3142  *
3143  * @dev:                net device
3144  * @channels:           includes the number of queues requested
3145  */
3146 static int bnx2x_set_channels(struct net_device *dev,
3147                               struct ethtool_channels *channels)
3148 {
3149         struct bnx2x *bp = netdev_priv(dev);
3150
3151
3152         DP(BNX2X_MSG_ETHTOOL,
3153            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3154            channels->rx_count, channels->tx_count, channels->other_count,
3155            channels->combined_count);
3156
3157         /* We don't support separate rx / tx channels.
3158          * We don't allow setting 'other' channels.
3159          */
3160         if (channels->rx_count || channels->tx_count || channels->other_count
3161             || (channels->combined_count == 0) ||
3162             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3163                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3164                 return -EINVAL;
3165         }
3166
3167         /* Check if there was a change in the active parameters */
3168         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3169                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3170                 return 0;
3171         }
3172
3173         /* Set the requested number of queues in bp context.
3174          * Note that the actual number of queues created during load may be
3175          * less than requested if memory is low.
3176          */
3177         if (unlikely(!netif_running(dev))) {
3178                 bnx2x_change_num_queues(bp, channels->combined_count);
3179                 return 0;
3180         }
3181         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3182         bnx2x_change_num_queues(bp, channels->combined_count);
3183         return bnx2x_nic_load(bp, LOAD_NORMAL);
3184 }
3185
3186 static const struct ethtool_ops bnx2x_ethtool_ops = {
3187         .get_settings           = bnx2x_get_settings,
3188         .set_settings           = bnx2x_set_settings,
3189         .get_drvinfo            = bnx2x_get_drvinfo,
3190         .get_regs_len           = bnx2x_get_regs_len,
3191         .get_regs               = bnx2x_get_regs,
3192         .get_dump_flag          = bnx2x_get_dump_flag,
3193         .get_dump_data          = bnx2x_get_dump_data,
3194         .set_dump               = bnx2x_set_dump,
3195         .get_wol                = bnx2x_get_wol,
3196         .set_wol                = bnx2x_set_wol,
3197         .get_msglevel           = bnx2x_get_msglevel,
3198         .set_msglevel           = bnx2x_set_msglevel,
3199         .nway_reset             = bnx2x_nway_reset,
3200         .get_link               = bnx2x_get_link,
3201         .get_eeprom_len         = bnx2x_get_eeprom_len,
3202         .get_eeprom             = bnx2x_get_eeprom,
3203         .set_eeprom             = bnx2x_set_eeprom,
3204         .get_coalesce           = bnx2x_get_coalesce,
3205         .set_coalesce           = bnx2x_set_coalesce,
3206         .get_ringparam          = bnx2x_get_ringparam,
3207         .set_ringparam          = bnx2x_set_ringparam,
3208         .get_pauseparam         = bnx2x_get_pauseparam,
3209         .set_pauseparam         = bnx2x_set_pauseparam,
3210         .self_test              = bnx2x_self_test,
3211         .get_sset_count         = bnx2x_get_sset_count,
3212         .get_strings            = bnx2x_get_strings,
3213         .set_phys_id            = bnx2x_set_phys_id,
3214         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3215         .get_rxnfc              = bnx2x_get_rxnfc,
3216         .set_rxnfc              = bnx2x_set_rxnfc,
3217         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3218         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
3219         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
3220         .get_channels           = bnx2x_get_channels,
3221         .set_channels           = bnx2x_set_channels,
3222         .get_module_info        = bnx2x_get_module_info,
3223         .get_module_eeprom      = bnx2x_get_module_eeprom,
3224         .get_eee                = bnx2x_get_eee,
3225         .set_eee                = bnx2x_set_eee,
3226         .get_ts_info            = ethtool_op_get_ts_info,
3227 };
3228
3229 void bnx2x_set_ethtool_ops(struct net_device *netdev)
3230 {
3231         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3232 }