drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  66         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  67                                         4, "[%s]: driver_filtered_tx_pkt" }
  68 };
  69
  70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  71
  72 static const struct {
  73         long offset;
  74         int size;
  75         u32 flags;
  76 #define STATS_FLAGS_PORT                1
  77 #define STATS_FLAGS_FUNC                2
  78 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  79         char string[ETH_GSTRING_LEN];
  80 } bnx2x_stats_arr[] = {
  81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  83         { STATS_OFFSET32(error_bytes_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  85         { STATS_OFFSET32(total_unicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  87         { STATS_OFFSET32(total_multicast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  89         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  90                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  91         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  93         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  95         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  97         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 101         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 102                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 103         { STATS_OFFSET32(no_buff_discard_hi),
 104                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 105         { STATS_OFFSET32(mac_filter_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 107         { STATS_OFFSET32(mf_tag_discard),
 108                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 109         { STATS_OFFSET32(pfc_frames_received_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 111         { STATS_OFFSET32(pfc_frames_sent_hi),
 112                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 113         { STATS_OFFSET32(brb_drop_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 115         { STATS_OFFSET32(brb_truncate_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 117         { STATS_OFFSET32(pause_frames_received_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 119         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 120                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 121         { STATS_OFFSET32(nig_timer_max),
 122                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 124                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 125         { STATS_OFFSET32(rx_skb_alloc_failed),
 126                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 127         { STATS_OFFSET32(hw_csum_err),
 128                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 129
 130         { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 132         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 134         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 136         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 138         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 140         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 142         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 150         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 152         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 166         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 168         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 170         { STATS_OFFSET32(pause_frames_sent_hi),
 171                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 172         { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 174         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 176         { STATS_OFFSET32(total_tpa_bytes_hi),
 177                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 178         { STATS_OFFSET32(recoverable_error),
 179                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 180         { STATS_OFFSET32(unrecoverable_error),
 181                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 182         { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
 184         { STATS_OFFSET32(eee_tx_lpi),
 185                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 186 };
 187
 188 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 189
 190 static int bnx2x_get_port_type(struct bnx2x *bp)
 191 {
 192         int port_type;
 193         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 194         switch (bp->link_params.phy[phy_idx].media_type) {
 195         case ETH_PHY_SFPP_10G_FIBER:
 196         case ETH_PHY_SFP_1G_FIBER:
 197         case ETH_PHY_XFP_FIBER:
 198         case ETH_PHY_KR:
 199         case ETH_PHY_CX4:
 200                 port_type = PORT_FIBRE;
 201                 break;
 202         case ETH_PHY_DA_TWINAX:
 203                 port_type = PORT_DA;
 204                 break;
 205         case ETH_PHY_BASE_T:
 206                 port_type = PORT_TP;
 207                 break;
 208         case ETH_PHY_NOT_PRESENT:
 209                 port_type = PORT_NONE;
 210                 break;
 211         case ETH_PHY_UNSPECIFIED:
 212         default:
 213                 port_type = PORT_OTHER;
 214                 break;
 215         }
 216         return port_type;
 217 }
 218
 219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 220 {
 221         struct bnx2x *bp = netdev_priv(dev);
 222         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 223
 224         /* Dual Media boards present all available port types */
 225         cmd->supported = bp->port.supported[cfg_idx] |
 226                 (bp->port.supported[cfg_idx ^ 1] &
 227                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 228         cmd->advertising = bp->port.advertising[cfg_idx];
 229         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 230             ETH_PHY_SFP_1G_FIBER) {
 231                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 232                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 233         }
 234
 235         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 236             !(bp->flags & MF_FUNC_DIS)) {
 237                 cmd->duplex = bp->link_vars.duplex;
 238
 239                 if (IS_MF(bp) && !BP_NOMCP(bp))
 240                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 241                 else
 242                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 243         } else {
 244                 cmd->duplex = DUPLEX_UNKNOWN;
 245                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 246         }
 247
 248         cmd->port = bnx2x_get_port_type(bp);
 249
 250         cmd->phy_address = bp->mdio.prtad;
 251         cmd->transceiver = XCVR_INTERNAL;
 252
 253         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 254                 cmd->autoneg = AUTONEG_ENABLE;
 255         else
 256                 cmd->autoneg = AUTONEG_DISABLE;
 257
 258         /* Publish LP advertised speeds and FC */
 259         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 260                 u32 status = bp->link_vars.link_status;
 261
 262                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 263                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 264                         cmd->lp_advertising |= ADVERTISED_Pause;
 265                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 266                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 267
 268                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 269                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 270                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 271                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 272                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 273                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 274                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 275                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 276                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 277                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 278                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 279                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 280                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 281                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 282                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 283                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 284                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 285                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
 286         }
 287
 288         cmd->maxtxpkt = 0;
 289         cmd->maxrxpkt = 0;
 290
 291         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 292            "  supported 0x%x  advertising 0x%x  speed %u\n"
 293            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 294            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 295            cmd->cmd, cmd->supported, cmd->advertising,
 296            ethtool_cmd_speed(cmd),
 297            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 298            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 299
 300         return 0;
 301 }
 302
 303 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 304 {
 305         struct bnx2x *bp = netdev_priv(dev);
 306         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 307         u32 speed, phy_idx;
 308
 309         if (IS_MF_SD(bp))
 310                 return 0;
 311
 312         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 313            "  supported 0x%x  advertising 0x%x  speed %u\n"
 314            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 315            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 316            cmd->cmd, cmd->supported, cmd->advertising,
 317            ethtool_cmd_speed(cmd),
 318            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 319            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 320
 321         speed = ethtool_cmd_speed(cmd);
 322
 323         /* If received a request for an unknown duplex, assume full*/
 324         if (cmd->duplex == DUPLEX_UNKNOWN)
 325                 cmd->duplex = DUPLEX_FULL;
 326
 327         if (IS_MF_SI(bp)) {
 328                 u32 part;
 329                 u32 line_speed = bp->link_vars.line_speed;
 330
 331                 /* use 10G if no link detected */
 332                 if (!line_speed)
 333                         line_speed = 10000;
 334
 335                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 336                         DP(BNX2X_MSG_ETHTOOL,
 337                            "To set speed BC %X or higher is required, please upgrade BC\n",
 338                            REQ_BC_VER_4_SET_MF_BW);
 339                         return -EINVAL;
 340                 }
 341
 342                 part = (speed * 100) / line_speed;
 343
 344                 if (line_speed < speed || !part) {
 345                         DP(BNX2X_MSG_ETHTOOL,
 346                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 347                         return -EINVAL;
 348                 }
 349
 350                 if (bp->state != BNX2X_STATE_OPEN)
 351                         /* store value for following "load" */
 352                         bp->pending_max = part;
 353                 else
 354                         bnx2x_update_max_mf_config(bp, part);
 355
 356                 return 0;
 357         }
 358
 359         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 360         old_multi_phy_config = bp->link_params.multi_phy_config;
 361         switch (cmd->port) {
 362         case PORT_TP:
 363                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 364                         break; /* no port change */
 365
 366                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 367                       bp->port.supported[1] & SUPPORTED_TP)) {
 368                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 369                         return -EINVAL;
 370                 }
 371                 bp->link_params.multi_phy_config &=
 372                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 373                 if (bp->link_params.multi_phy_config &
 374                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 375                         bp->link_params.multi_phy_config |=
 376                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 377                 else
 378                         bp->link_params.multi_phy_config |=
 379                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 380                 break;
 381         case PORT_FIBRE:
 382         case PORT_DA:
 383                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 384                         break; /* no port change */
 385
 386                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 387                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 388                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 389                         return -EINVAL;
 390                 }
 391                 bp->link_params.multi_phy_config &=
 392                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 393                 if (bp->link_params.multi_phy_config &
 394                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 395                         bp->link_params.multi_phy_config |=
 396                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 397                 else
 398                         bp->link_params.multi_phy_config |=
 399                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 400                 break;
 401         default:
 402                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 403                 return -EINVAL;
 404         }
 405         /* Save new config in case command complete successfully */
 406         new_multi_phy_config = bp->link_params.multi_phy_config;
 407         /* Get the new cfg_idx */
 408         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 409         /* Restore old config in case command failed */
 410         bp->link_params.multi_phy_config = old_multi_phy_config;
 411         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 412
 413         if (cmd->autoneg == AUTONEG_ENABLE) {
 414                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 415                 if (bp->link_params.phy[EXT_PHY1].type ==
 416                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 417                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 418                                                SUPPORTED_100baseT_Full);
 419                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 420                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 421                         return -EINVAL;
 422                 }
 423
 424                 /* advertise the requested speed and duplex if supported */
 425                 if (cmd->advertising & ~an_supported_speed) {
 426                         DP(BNX2X_MSG_ETHTOOL,
 427                            "Advertisement parameters are not supported\n");
 428                         return -EINVAL;
 429                 }
 430
 431                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 432                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 433                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 434                                          cmd->advertising);
 435                 if (cmd->advertising) {
 436
 437                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 438                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 439                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 440                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 441                         }
 442                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 443                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 444                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 445
 446                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 447                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 448                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 449
 450                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 451                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 452                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 453                         }
 454                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 455                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 456                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 457                         }
 458                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 459                                                 ADVERTISED_1000baseKX_Full))
 460                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 461                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 462
 463                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 464                                                 ADVERTISED_10000baseKX4_Full |
 465                                                 ADVERTISED_10000baseKR_Full))
 466                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 467                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 468
 469                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
 470                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 471                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 472                 }
 473         } else { /* forced speed */
 474                 /* advertise the requested speed and duplex if supported */
 475                 switch (speed) {
 476                 case SPEED_10:
 477                         if (cmd->duplex == DUPLEX_FULL) {
 478                                 if (!(bp->port.supported[cfg_idx] &
 479                                       SUPPORTED_10baseT_Full)) {
 480                                         DP(BNX2X_MSG_ETHTOOL,
 481                                            "10M full not supported\n");
 482                                         return -EINVAL;
 483                                 }
 484
 485                                 advertising = (ADVERTISED_10baseT_Full |
 486                                                ADVERTISED_TP);
 487                         } else {
 488                                 if (!(bp->port.supported[cfg_idx] &
 489                                       SUPPORTED_10baseT_Half)) {
 490                                         DP(BNX2X_MSG_ETHTOOL,
 491                                            "10M half not supported\n");
 492                                         return -EINVAL;
 493                                 }
 494
 495                                 advertising = (ADVERTISED_10baseT_Half |
 496                                                ADVERTISED_TP);
 497                         }
 498                         break;
 499
 500                 case SPEED_100:
 501                         if (cmd->duplex == DUPLEX_FULL) {
 502                                 if (!(bp->port.supported[cfg_idx] &
 503                                                 SUPPORTED_100baseT_Full)) {
 504                                         DP(BNX2X_MSG_ETHTOOL,
 505                                            "100M full not supported\n");
 506                                         return -EINVAL;
 507                                 }
 508
 509                                 advertising = (ADVERTISED_100baseT_Full |
 510                                                ADVERTISED_TP);
 511                         } else {
 512                                 if (!(bp->port.supported[cfg_idx] &
 513                                                 SUPPORTED_100baseT_Half)) {
 514                                         DP(BNX2X_MSG_ETHTOOL,
 515                                            "100M half not supported\n");
 516                                         return -EINVAL;
 517                                 }
 518
 519                                 advertising = (ADVERTISED_100baseT_Half |
 520                                                ADVERTISED_TP);
 521                         }
 522                         break;
 523
 524                 case SPEED_1000:
 525                         if (cmd->duplex != DUPLEX_FULL) {
 526                                 DP(BNX2X_MSG_ETHTOOL,
 527                                    "1G half not supported\n");
 528                                 return -EINVAL;
 529                         }
 530
 531                         if (!(bp->port.supported[cfg_idx] &
 532                               SUPPORTED_1000baseT_Full)) {
 533                                 DP(BNX2X_MSG_ETHTOOL,
 534                                    "1G full not supported\n");
 535                                 return -EINVAL;
 536                         }
 537
 538                         advertising = (ADVERTISED_1000baseT_Full |
 539                                        ADVERTISED_TP);
 540                         break;
 541
 542                 case SPEED_2500:
 543                         if (cmd->duplex != DUPLEX_FULL) {
 544                                 DP(BNX2X_MSG_ETHTOOL,
 545                                    "2.5G half not supported\n");
 546                                 return -EINVAL;
 547                         }
 548
 549                         if (!(bp->port.supported[cfg_idx]
 550                               & SUPPORTED_2500baseX_Full)) {
 551                                 DP(BNX2X_MSG_ETHTOOL,
 552                                    "2.5G full not supported\n");
 553                                 return -EINVAL;
 554                         }
 555
 556                         advertising = (ADVERTISED_2500baseX_Full |
 557                                        ADVERTISED_TP);
 558                         break;
 559
 560                 case SPEED_10000:
 561                         if (cmd->duplex != DUPLEX_FULL) {
 562                                 DP(BNX2X_MSG_ETHTOOL,
 563                                    "10G half not supported\n");
 564                                 return -EINVAL;
 565                         }
 566                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 567                         if (!(bp->port.supported[cfg_idx]
 568                               & SUPPORTED_10000baseT_Full) ||
 569                             (bp->link_params.phy[phy_idx].media_type ==
 570                              ETH_PHY_SFP_1G_FIBER)) {
 571                                 DP(BNX2X_MSG_ETHTOOL,
 572                                    "10G full not supported\n");
 573                                 return -EINVAL;
 574                         }
 575
 576                         advertising = (ADVERTISED_10000baseT_Full |
 577                                        ADVERTISED_FIBRE);
 578                         break;
 579
 580                 default:
 581                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 582                         return -EINVAL;
 583                 }
 584
 585                 bp->link_params.req_line_speed[cfg_idx] = speed;
 586                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 587                 bp->port.advertising[cfg_idx] = advertising;
 588         }
 589
 590         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 591            "  req_duplex %d  advertising 0x%x\n",
 592            bp->link_params.req_line_speed[cfg_idx],
 593            bp->link_params.req_duplex[cfg_idx],
 594            bp->port.advertising[cfg_idx]);
 595
 596         /* Set new config */
 597         bp->link_params.multi_phy_config = new_multi_phy_config;
 598         if (netif_running(dev)) {
 599                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 600                 bnx2x_link_set(bp);
 601         }
 602
 603         return 0;
 604 }
 605
 606 #define DUMP_ALL_PRESETS                0x1FFF
 607 #define DUMP_MAX_PRESETS                13
 608
 609 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 610 {
 611         if (CHIP_IS_E1(bp))
 612                 return dump_num_registers[0][preset-1];
 613         else if (CHIP_IS_E1H(bp))
 614                 return dump_num_registers[1][preset-1];
 615         else if (CHIP_IS_E2(bp))
 616                 return dump_num_registers[2][preset-1];
 617         else if (CHIP_IS_E3A0(bp))
 618                 return dump_num_registers[3][preset-1];
 619         else if (CHIP_IS_E3B0(bp))
 620                 return dump_num_registers[4][preset-1];
 621         else
 622                 return 0;
 623 }
 624
 625 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 626 {
 627         u32 preset_idx;
 628         int regdump_len = 0;
 629
 630         /* Calculate the total preset regs length */
 631         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 632                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 633
 634         return regdump_len;
 635 }
 636
 637 static int bnx2x_get_regs_len(struct net_device *dev)
 638 {
 639         struct bnx2x *bp = netdev_priv(dev);
 640         int regdump_len = 0;
 641
 642         if (IS_VF(bp))
 643                 return 0;
 644
 645         regdump_len = __bnx2x_get_regs_len(bp);
 646         regdump_len *= 4;
 647         regdump_len += sizeof(struct dump_header);
 648
 649         return regdump_len;
 650 }
 651
 652 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 653 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 654 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 655 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 656 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 657
 658 #define IS_REG_IN_PRESET(presets, idx)  \
 659                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 660
 661 /******* Paged registers info selectors ********/
 662 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 663 {
 664         if (CHIP_IS_E2(bp))
 665                 return page_vals_e2;
 666         else if (CHIP_IS_E3(bp))
 667                 return page_vals_e3;
 668         else
 669                 return NULL;
 670 }
 671
 672 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 673 {
 674         if (CHIP_IS_E2(bp))
 675                 return PAGE_MODE_VALUES_E2;
 676         else if (CHIP_IS_E3(bp))
 677                 return PAGE_MODE_VALUES_E3;
 678         else
 679                 return 0;
 680 }
 681
 682 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 683 {
 684         if (CHIP_IS_E2(bp))
 685                 return page_write_regs_e2;
 686         else if (CHIP_IS_E3(bp))
 687                 return page_write_regs_e3;
 688         else
 689                 return NULL;
 690 }
 691
 692 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 693 {
 694         if (CHIP_IS_E2(bp))
 695                 return PAGE_WRITE_REGS_E2;
 696         else if (CHIP_IS_E3(bp))
 697                 return PAGE_WRITE_REGS_E3;
 698         else
 699                 return 0;
 700 }
 701
 702 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 703 {
 704         if (CHIP_IS_E2(bp))
 705                 return page_read_regs_e2;
 706         else if (CHIP_IS_E3(bp))
 707                 return page_read_regs_e3;
 708         else
 709                 return NULL;
 710 }
 711
 712 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 713 {
 714         if (CHIP_IS_E2(bp))
 715                 return PAGE_READ_REGS_E2;
 716         else if (CHIP_IS_E3(bp))
 717                 return PAGE_READ_REGS_E3;
 718         else
 719                 return 0;
 720 }
 721
 722 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 723                                        const struct reg_addr *reg_info)
 724 {
 725         if (CHIP_IS_E1(bp))
 726                 return IS_E1_REG(reg_info->chips);
 727         else if (CHIP_IS_E1H(bp))
 728                 return IS_E1H_REG(reg_info->chips);
 729         else if (CHIP_IS_E2(bp))
 730                 return IS_E2_REG(reg_info->chips);
 731         else if (CHIP_IS_E3A0(bp))
 732                 return IS_E3A0_REG(reg_info->chips);
 733         else if (CHIP_IS_E3B0(bp))
 734                 return IS_E3B0_REG(reg_info->chips);
 735         else
 736                 return false;
 737 }
 738
 739 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 740         const struct wreg_addr *wreg_info)
 741 {
 742         if (CHIP_IS_E1(bp))
 743                 return IS_E1_REG(wreg_info->chips);
 744         else if (CHIP_IS_E1H(bp))
 745                 return IS_E1H_REG(wreg_info->chips);
 746         else if (CHIP_IS_E2(bp))
 747                 return IS_E2_REG(wreg_info->chips);
 748         else if (CHIP_IS_E3A0(bp))
 749                 return IS_E3A0_REG(wreg_info->chips);
 750         else if (CHIP_IS_E3B0(bp))
 751                 return IS_E3B0_REG(wreg_info->chips);
 752         else
 753                 return false;
 754 }
 755
 756 /**
 757  * bnx2x_read_pages_regs - read "paged" registers
 758  *
 759  * @bp          device handle
 760  * @p           output buffer
 761  *
 762  * Reads "paged" memories: memories that may only be read by first writing to a
 763  * specific address ("write address") and then reading from a specific address
 764  * ("read address"). There may be more than one write address per "page" and
 765  * more than one read address per write address.
 766  */
 767 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 768 {
 769         u32 i, j, k, n;
 770
 771         /* addresses of the paged registers */
 772         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 773         /* number of paged registers */
 774         int num_pages = __bnx2x_get_page_reg_num(bp);
 775         /* write addresses */
 776         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 777         /* number of write addresses */
 778         int write_num = __bnx2x_get_page_write_num(bp);
 779         /* read addresses info */
 780         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 781         /* number of read addresses */
 782         int read_num = __bnx2x_get_page_read_num(bp);
 783         u32 addr, size;
 784
 785         for (i = 0; i < num_pages; i++) {
 786                 for (j = 0; j < write_num; j++) {
 787                         REG_WR(bp, write_addr[j], page_addr[i]);
 788
 789                         for (k = 0; k < read_num; k++) {
 790                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 791                                                      preset)) {
 792                                         size = read_addr[k].size;
 793                                         for (n = 0; n < size; n++) {
 794                                                 addr = read_addr[k].addr + n*4;
 795                                                 *p++ = REG_RD(bp, addr);
 796                                         }
 797                                 }
 798                         }
 799                 }
 800         }
 801 }
 802
 803 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 804 {
 805         u32 i, j, addr;
 806         const struct wreg_addr *wreg_addr_p = NULL;
 807
 808         if (CHIP_IS_E1(bp))
 809                 wreg_addr_p = &wreg_addr_e1;
 810         else if (CHIP_IS_E1H(bp))
 811                 wreg_addr_p = &wreg_addr_e1h;
 812         else if (CHIP_IS_E2(bp))
 813                 wreg_addr_p = &wreg_addr_e2;
 814         else if (CHIP_IS_E3A0(bp))
 815                 wreg_addr_p = &wreg_addr_e3;
 816         else if (CHIP_IS_E3B0(bp))
 817                 wreg_addr_p = &wreg_addr_e3b0;
 818
 819         /* Read the idle_chk registers */
 820         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 821                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 822                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 823                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 824                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 825                 }
 826         }
 827
 828         /* Read the regular registers */
 829         for (i = 0; i < REGS_COUNT; i++) {
 830                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 831                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 832                         for (j = 0; j < reg_addrs[i].size; j++)
 833                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 834                 }
 835         }
 836
 837         /* Read the CAM registers */
 838         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 839             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 840                 for (i = 0; i < wreg_addr_p->size; i++) {
 841                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 842
 843                         /* In case of wreg_addr register, read additional
 844                            registers from read_regs array
 845                         */
 846                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 847                                 addr = *(wreg_addr_p->read_regs);
 848                                 *p++ = REG_RD(bp, addr + j*4);
 849                         }
 850                 }
 851         }
 852
 853         /* Paged registers are supported in E2 & E3 only */
 854         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 855                 /* Read "paged" registers */
 856                 bnx2x_read_pages_regs(bp, p, preset);
 857         }
 858
 859         return 0;
 860 }
 861
 862 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 863 {
 864         u32 preset_idx;
 865
 866         /* Read all registers, by reading all preset registers */
 867         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 868                 /* Skip presets with IOR */
 869                 if ((preset_idx == 2) ||
 870                     (preset_idx == 5) ||
 871                     (preset_idx == 8) ||
 872                     (preset_idx == 11))
 873                         continue;
 874                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 875                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 876         }
 877 }
 878
 879 static void bnx2x_get_regs(struct net_device *dev,
 880                            struct ethtool_regs *regs, void *_p)
 881 {
 882         u32 *p = _p;
 883         struct bnx2x *bp = netdev_priv(dev);
 884         struct dump_header dump_hdr = {0};
 885
 886         regs->version = 2;
 887         memset(p, 0, regs->len);
 888
 889         if (!netif_running(bp->dev))
 890                 return;
 891
 892         /* Disable parity attentions as long as following dump may
 893          * cause false alarms by reading never written registers. We
 894          * will re-enable parity attentions right after the dump.
 895          */
 896
 897         /* Disable parity on path 0 */
 898         bnx2x_pretend_func(bp, 0);
 899         bnx2x_disable_blocks_parity(bp);
 900
 901         /* Disable parity on path 1 */
 902         bnx2x_pretend_func(bp, 1);
 903         bnx2x_disable_blocks_parity(bp);
 904
 905         /* Return to current function */
 906         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
 907
 908         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 909         dump_hdr.preset = DUMP_ALL_PRESETS;
 910         dump_hdr.version = BNX2X_DUMP_VERSION;
 911
 912         /* dump_meta_data presents OR of CHIP and PATH. */
 913         if (CHIP_IS_E1(bp)) {
 914                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 915         } else if (CHIP_IS_E1H(bp)) {
 916                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 917         } else if (CHIP_IS_E2(bp)) {
 918                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 919                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 920         } else if (CHIP_IS_E3A0(bp)) {
 921                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 922                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 923         } else if (CHIP_IS_E3B0(bp)) {
 924                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 925                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 926         }
 927
 928         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 929         p += dump_hdr.header_size + 1;
 930
 931         /* Actually read the registers */
 932         __bnx2x_get_regs(bp, p);
 933
 934         /* Re-enable parity attentions on path 0 */
 935         bnx2x_pretend_func(bp, 0);
 936         bnx2x_clear_blocks_parity(bp);
 937         bnx2x_enable_blocks_parity(bp);
 938
 939         /* Re-enable parity attentions on path 1 */
 940         bnx2x_pretend_func(bp, 1);
 941         bnx2x_clear_blocks_parity(bp);
 942         bnx2x_enable_blocks_parity(bp);
 943
 944         /* Return to current function */
 945         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
 946 }
 947
 948 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 949 {
 950         struct bnx2x *bp = netdev_priv(dev);
 951         int regdump_len = 0;
 952
 953         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
 954         regdump_len *= 4;
 955         regdump_len += sizeof(struct dump_header);
 956
 957         return regdump_len;
 958 }
 959
 960 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
 961 {
 962         struct bnx2x *bp = netdev_priv(dev);
 963
 964         /* Use the ethtool_dump "flag" field as the dump preset index */
 965         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
 966                 return -EINVAL;
 967
 968         bp->dump_preset_idx = val->flag;
 969         return 0;
 970 }
 971
 972 static int bnx2x_get_dump_flag(struct net_device *dev,
 973                                struct ethtool_dump *dump)
 974 {
 975         struct bnx2x *bp = netdev_priv(dev);
 976
 977         dump->version = BNX2X_DUMP_VERSION;
 978         dump->flag = bp->dump_preset_idx;
 979         /* Calculate the requested preset idx length */
 980         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
 981         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
 982            bp->dump_preset_idx, dump->len);
 983         return 0;
 984 }
 985
 986 static int bnx2x_get_dump_data(struct net_device *dev,
 987                                struct ethtool_dump *dump,
 988                                void *buffer)
 989 {
 990         u32 *p = buffer;
 991         struct bnx2x *bp = netdev_priv(dev);
 992         struct dump_header dump_hdr = {0};
 993
 994         /* Disable parity attentions as long as following dump may
 995          * cause false alarms by reading never written registers. We
 996          * will re-enable parity attentions right after the dump.
 997          */
 998
 999         /* Disable parity on path 0 */
1000         bnx2x_pretend_func(bp, 0);
1001         bnx2x_disable_blocks_parity(bp);
1002
1003         /* Disable parity on path 1 */
1004         bnx2x_pretend_func(bp, 1);
1005         bnx2x_disable_blocks_parity(bp);
1006
1007         /* Return to current function */
1008         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1009
1010         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1011         dump_hdr.preset = bp->dump_preset_idx;
1012         dump_hdr.version = BNX2X_DUMP_VERSION;
1013
1014         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1015
1016         /* dump_meta_data presents OR of CHIP and PATH. */
1017         if (CHIP_IS_E1(bp)) {
1018                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1019         } else if (CHIP_IS_E1H(bp)) {
1020                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1021         } else if (CHIP_IS_E2(bp)) {
1022                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1023                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1024         } else if (CHIP_IS_E3A0(bp)) {
1025                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1026                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1027         } else if (CHIP_IS_E3B0(bp)) {
1028                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1029                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1030         }
1031
1032         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1033         p += dump_hdr.header_size + 1;
1034
1035         /* Actually read the registers */
1036         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1037
1038         /* Re-enable parity attentions on path 0 */
1039         bnx2x_pretend_func(bp, 0);
1040         bnx2x_clear_blocks_parity(bp);
1041         bnx2x_enable_blocks_parity(bp);
1042
1043         /* Re-enable parity attentions on path 1 */
1044         bnx2x_pretend_func(bp, 1);
1045         bnx2x_clear_blocks_parity(bp);
1046         bnx2x_enable_blocks_parity(bp);
1047
1048         /* Return to current function */
1049         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1050
1051         return 0;
1052 }
1053
1054 static void bnx2x_get_drvinfo(struct net_device *dev,
1055                               struct ethtool_drvinfo *info)
1056 {
1057         struct bnx2x *bp = netdev_priv(dev);
1058
1059         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1060         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1061
1062         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1063
1064         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1065         info->n_stats = BNX2X_NUM_STATS;
1066         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1067         info->eedump_len = bp->common.flash_size;
1068         info->regdump_len = bnx2x_get_regs_len(dev);
1069 }
1070
1071 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1072 {
1073         struct bnx2x *bp = netdev_priv(dev);
1074
1075         if (bp->flags & NO_WOL_FLAG) {
1076                 wol->supported = 0;
1077                 wol->wolopts = 0;
1078         } else {
1079                 wol->supported = WAKE_MAGIC;
1080                 if (bp->wol)
1081                         wol->wolopts = WAKE_MAGIC;
1082                 else
1083                         wol->wolopts = 0;
1084         }
1085         memset(&wol->sopass, 0, sizeof(wol->sopass));
1086 }
1087
1088 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1089 {
1090         struct bnx2x *bp = netdev_priv(dev);
1091
1092         if (wol->wolopts & ~WAKE_MAGIC) {
1093                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1094                 return -EINVAL;
1095         }
1096
1097         if (wol->wolopts & WAKE_MAGIC) {
1098                 if (bp->flags & NO_WOL_FLAG) {
1099                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1100                         return -EINVAL;
1101                 }
1102                 bp->wol = 1;
1103         } else
1104                 bp->wol = 0;
1105
1106         return 0;
1107 }
1108
1109 static u32 bnx2x_get_msglevel(struct net_device *dev)
1110 {
1111         struct bnx2x *bp = netdev_priv(dev);
1112
1113         return bp->msg_enable;
1114 }
1115
1116 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1117 {
1118         struct bnx2x *bp = netdev_priv(dev);
1119
1120         if (capable(CAP_NET_ADMIN)) {
1121                 /* dump MCP trace */
1122                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1123                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1124                 bp->msg_enable = level;
1125         }
1126 }
1127
1128 static int bnx2x_nway_reset(struct net_device *dev)
1129 {
1130         struct bnx2x *bp = netdev_priv(dev);
1131
1132         if (!bp->port.pmf)
1133                 return 0;
1134
1135         if (netif_running(dev)) {
1136                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1137                 bnx2x_force_link_reset(bp);
1138                 bnx2x_link_set(bp);
1139         }
1140
1141         return 0;
1142 }
1143
1144 static u32 bnx2x_get_link(struct net_device *dev)
1145 {
1146         struct bnx2x *bp = netdev_priv(dev);
1147
1148         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1149                 return 0;
1150
1151         return bp->link_vars.link_up;
1152 }
1153
1154 static int bnx2x_get_eeprom_len(struct net_device *dev)
1155 {
1156         struct bnx2x *bp = netdev_priv(dev);
1157
1158         return bp->common.flash_size;
1159 }
1160
1161 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1162  * had we done things the other way around, if two pfs from the same port would
1163  * attempt to access nvram at the same time, we could run into a scenario such
1164  * as:
1165  * pf A takes the port lock.
1166  * pf B succeeds in taking the same lock since they are from the same port.
1167  * pf A takes the per pf misc lock. Performs eeprom access.
1168  * pf A finishes. Unlocks the per pf misc lock.
1169  * Pf B takes the lock and proceeds to perform it's own access.
1170  * pf A unlocks the per port lock, while pf B is still working (!).
1171  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1172  * access corrupted by pf B)
1173  */
1174 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1175 {
1176         int port = BP_PORT(bp);
1177         int count, i;
1178         u32 val;
1179
1180         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1181         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1182
1183         /* adjust timeout for emulation/FPGA */
1184         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1185         if (CHIP_REV_IS_SLOW(bp))
1186                 count *= 100;
1187
1188         /* request access to nvram interface */
1189         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1190                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1191
1192         for (i = 0; i < count*10; i++) {
1193                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1194                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1195                         break;
1196
1197                 udelay(5);
1198         }
1199
1200         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1201                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1202                    "cannot get access to nvram interface\n");
1203                 return -EBUSY;
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1210 {
1211         int port = BP_PORT(bp);
1212         int count, i;
1213         u32 val;
1214
1215         /* adjust timeout for emulation/FPGA */
1216         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1217         if (CHIP_REV_IS_SLOW(bp))
1218                 count *= 100;
1219
1220         /* relinquish nvram interface */
1221         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1222                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1223
1224         for (i = 0; i < count*10; i++) {
1225                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1226                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1227                         break;
1228
1229                 udelay(5);
1230         }
1231
1232         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1233                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1234                    "cannot free access to nvram interface\n");
1235                 return -EBUSY;
1236         }
1237
1238         /* release HW lock: protect against other PFs in PF Direct Assignment */
1239         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1240         return 0;
1241 }
1242
1243 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1244 {
1245         u32 val;
1246
1247         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1248
1249         /* enable both bits, even on read */
1250         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1251                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1252                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1253 }
1254
1255 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1256 {
1257         u32 val;
1258
1259         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1260
1261         /* disable both bits, even after read */
1262         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1263                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1264                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1265 }
1266
1267 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1268                                   u32 cmd_flags)
1269 {
1270         int count, i, rc;
1271         u32 val;
1272
1273         /* build the command word */
1274         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1275
1276         /* need to clear DONE bit separately */
1277         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1278
1279         /* address of the NVRAM to read from */
1280         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1281                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1282
1283         /* issue a read command */
1284         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1285
1286         /* adjust timeout for emulation/FPGA */
1287         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1288         if (CHIP_REV_IS_SLOW(bp))
1289                 count *= 100;
1290
1291         /* wait for completion */
1292         *ret_val = 0;
1293         rc = -EBUSY;
1294         for (i = 0; i < count; i++) {
1295                 udelay(5);
1296                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1297
1298                 if (val & MCPR_NVM_COMMAND_DONE) {
1299                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1300                         /* we read nvram data in cpu order
1301                          * but ethtool sees it as an array of bytes
1302                          * converting to big-endian will do the work
1303                          */
1304                         *ret_val = cpu_to_be32(val);
1305                         rc = 0;
1306                         break;
1307                 }
1308         }
1309         if (rc == -EBUSY)
1310                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1311                    "nvram read timeout expired\n");
1312         return rc;
1313 }
1314
1315 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1316                             int buf_size)
1317 {
1318         int rc;
1319         u32 cmd_flags;
1320         __be32 val;
1321
1322         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1323                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1324                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1325                    offset, buf_size);
1326                 return -EINVAL;
1327         }
1328
1329         if (offset + buf_size > bp->common.flash_size) {
1330                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1331                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1332                    offset, buf_size, bp->common.flash_size);
1333                 return -EINVAL;
1334         }
1335
1336         /* request access to nvram interface */
1337         rc = bnx2x_acquire_nvram_lock(bp);
1338         if (rc)
1339                 return rc;
1340
1341         /* enable access to nvram interface */
1342         bnx2x_enable_nvram_access(bp);
1343
1344         /* read the first word(s) */
1345         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1346         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1347                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1348                 memcpy(ret_buf, &val, 4);
1349
1350                 /* advance to the next dword */
1351                 offset += sizeof(u32);
1352                 ret_buf += sizeof(u32);
1353                 buf_size -= sizeof(u32);
1354                 cmd_flags = 0;
1355         }
1356
1357         if (rc == 0) {
1358                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1359                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1360                 memcpy(ret_buf, &val, 4);
1361         }
1362
1363         /* disable access to nvram interface */
1364         bnx2x_disable_nvram_access(bp);
1365         bnx2x_release_nvram_lock(bp);
1366
1367         return rc;
1368 }
1369
1370 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1371                               int buf_size)
1372 {
1373         int rc;
1374
1375         rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1376
1377         if (!rc) {
1378                 __be32 *be = (__be32 *)buf;
1379
1380                 while ((buf_size -= 4) >= 0)
1381                         *buf++ = be32_to_cpu(*be++);
1382         }
1383
1384         return rc;
1385 }
1386
1387 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1388 {
1389         int rc = 1;
1390         u16 pm = 0;
1391         struct net_device *dev = pci_get_drvdata(bp->pdev);
1392
1393         if (bp->pdev->pm_cap)
1394                 rc = pci_read_config_word(bp->pdev,
1395                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1396
1397         if ((rc && !netif_running(dev)) ||
1398             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1399                 return false;
1400
1401         return true;
1402 }
1403
1404 static int bnx2x_get_eeprom(struct net_device *dev,
1405                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1406 {
1407         struct bnx2x *bp = netdev_priv(dev);
1408
1409         if (!bnx2x_is_nvm_accessible(bp)) {
1410                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1411                    "cannot access eeprom when the interface is down\n");
1412                 return -EAGAIN;
1413         }
1414
1415         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1416            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1417            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1418            eeprom->len, eeprom->len);
1419
1420         /* parameters already validated in ethtool_get_eeprom */
1421
1422         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1423 }
1424
1425 static int bnx2x_get_module_eeprom(struct net_device *dev,
1426                                    struct ethtool_eeprom *ee,
1427                                    u8 *data)
1428 {
1429         struct bnx2x *bp = netdev_priv(dev);
1430         int rc = -EINVAL, phy_idx;
1431         u8 *user_data = data;
1432         unsigned int start_addr = ee->offset, xfer_size = 0;
1433
1434         if (!bnx2x_is_nvm_accessible(bp)) {
1435                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1436                    "cannot access eeprom when the interface is down\n");
1437                 return -EAGAIN;
1438         }
1439
1440         phy_idx = bnx2x_get_cur_phy_idx(bp);
1441
1442         /* Read A0 section */
1443         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1444                 /* Limit transfer size to the A0 section boundary */
1445                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1446                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1447                 else
1448                         xfer_size = ee->len;
1449                 bnx2x_acquire_phy_lock(bp);
1450                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1451                                                   &bp->link_params,
1452                                                   I2C_DEV_ADDR_A0,
1453                                                   start_addr,
1454                                                   xfer_size,
1455                                                   user_data);
1456                 bnx2x_release_phy_lock(bp);
1457                 if (rc) {
1458                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1459
1460                         return -EINVAL;
1461                 }
1462                 user_data += xfer_size;
1463                 start_addr += xfer_size;
1464         }
1465
1466         /* Read A2 section */
1467         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1468             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1469                 xfer_size = ee->len - xfer_size;
1470                 /* Limit transfer size to the A2 section boundary */
1471                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1472                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1473                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1474                 bnx2x_acquire_phy_lock(bp);
1475                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1476                                                   &bp->link_params,
1477                                                   I2C_DEV_ADDR_A2,
1478                                                   start_addr,
1479                                                   xfer_size,
1480                                                   user_data);
1481                 bnx2x_release_phy_lock(bp);
1482                 if (rc) {
1483                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1484                         return -EINVAL;
1485                 }
1486         }
1487         return rc;
1488 }
1489
1490 static int bnx2x_get_module_info(struct net_device *dev,
1491                                  struct ethtool_modinfo *modinfo)
1492 {
1493         struct bnx2x *bp = netdev_priv(dev);
1494         int phy_idx, rc;
1495         u8 sff8472_comp, diag_type;
1496
1497         if (!bnx2x_is_nvm_accessible(bp)) {
1498                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1499                    "cannot access eeprom when the interface is down\n");
1500                 return -EAGAIN;
1501         }
1502         phy_idx = bnx2x_get_cur_phy_idx(bp);
1503         bnx2x_acquire_phy_lock(bp);
1504         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1505                                           &bp->link_params,
1506                                           I2C_DEV_ADDR_A0,
1507                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1508                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1509                                           &sff8472_comp);
1510         bnx2x_release_phy_lock(bp);
1511         if (rc) {
1512                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1513                 return -EINVAL;
1514         }
1515
1516         bnx2x_acquire_phy_lock(bp);
1517         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1518                                           &bp->link_params,
1519                                           I2C_DEV_ADDR_A0,
1520                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1521                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1522                                           &diag_type);
1523         bnx2x_release_phy_lock(bp);
1524         if (rc) {
1525                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1526                 return -EINVAL;
1527         }
1528
1529         if (!sff8472_comp ||
1530             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1531                 modinfo->type = ETH_MODULE_SFF_8079;
1532                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1533         } else {
1534                 modinfo->type = ETH_MODULE_SFF_8472;
1535                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1536         }
1537         return 0;
1538 }
1539
1540 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1541                                    u32 cmd_flags)
1542 {
1543         int count, i, rc;
1544
1545         /* build the command word */
1546         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1547
1548         /* need to clear DONE bit separately */
1549         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1550
1551         /* write the data */
1552         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1553
1554         /* address of the NVRAM to write to */
1555         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1556                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1557
1558         /* issue the write command */
1559         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1560
1561         /* adjust timeout for emulation/FPGA */
1562         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1563         if (CHIP_REV_IS_SLOW(bp))
1564                 count *= 100;
1565
1566         /* wait for completion */
1567         rc = -EBUSY;
1568         for (i = 0; i < count; i++) {
1569                 udelay(5);
1570                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1571                 if (val & MCPR_NVM_COMMAND_DONE) {
1572                         rc = 0;
1573                         break;
1574                 }
1575         }
1576
1577         if (rc == -EBUSY)
1578                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1579                    "nvram write timeout expired\n");
1580         return rc;
1581 }
1582
1583 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1584
1585 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1586                               int buf_size)
1587 {
1588         int rc;
1589         u32 cmd_flags, align_offset, val;
1590         __be32 val_be;
1591
1592         if (offset + buf_size > bp->common.flash_size) {
1593                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1594                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1595                    offset, buf_size, bp->common.flash_size);
1596                 return -EINVAL;
1597         }
1598
1599         /* request access to nvram interface */
1600         rc = bnx2x_acquire_nvram_lock(bp);
1601         if (rc)
1602                 return rc;
1603
1604         /* enable access to nvram interface */
1605         bnx2x_enable_nvram_access(bp);
1606
1607         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1608         align_offset = (offset & ~0x03);
1609         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1610
1611         if (rc == 0) {
1612                 /* nvram data is returned as an array of bytes
1613                  * convert it back to cpu order
1614                  */
1615                 val = be32_to_cpu(val_be);
1616
1617                 val &= ~le32_to_cpu((__force __le32)
1618                                     (0xff << BYTE_OFFSET(offset)));
1619                 val |= le32_to_cpu((__force __le32)
1620                                    (*data_buf << BYTE_OFFSET(offset)));
1621
1622                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1623                                              cmd_flags);
1624         }
1625
1626         /* disable access to nvram interface */
1627         bnx2x_disable_nvram_access(bp);
1628         bnx2x_release_nvram_lock(bp);
1629
1630         return rc;
1631 }
1632
1633 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1634                              int buf_size)
1635 {
1636         int rc;
1637         u32 cmd_flags;
1638         u32 val;
1639         u32 written_so_far;
1640
1641         if (buf_size == 1)      /* ethtool */
1642                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1643
1644         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1645                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1646                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1647                    offset, buf_size);
1648                 return -EINVAL;
1649         }
1650
1651         if (offset + buf_size > bp->common.flash_size) {
1652                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1653                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1654                    offset, buf_size, bp->common.flash_size);
1655                 return -EINVAL;
1656         }
1657
1658         /* request access to nvram interface */
1659         rc = bnx2x_acquire_nvram_lock(bp);
1660         if (rc)
1661                 return rc;
1662
1663         /* enable access to nvram interface */
1664         bnx2x_enable_nvram_access(bp);
1665
1666         written_so_far = 0;
1667         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1668         while ((written_so_far < buf_size) && (rc == 0)) {
1669                 if (written_so_far == (buf_size - sizeof(u32)))
1670                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1671                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1672                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1673                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1674                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1675
1676                 memcpy(&val, data_buf, 4);
1677
1678                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1679
1680                 /* advance to the next dword */
1681                 offset += sizeof(u32);
1682                 data_buf += sizeof(u32);
1683                 written_so_far += sizeof(u32);
1684                 cmd_flags = 0;
1685         }
1686
1687         /* disable access to nvram interface */
1688         bnx2x_disable_nvram_access(bp);
1689         bnx2x_release_nvram_lock(bp);
1690
1691         return rc;
1692 }
1693
1694 static int bnx2x_set_eeprom(struct net_device *dev,
1695                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1696 {
1697         struct bnx2x *bp = netdev_priv(dev);
1698         int port = BP_PORT(bp);
1699         int rc = 0;
1700         u32 ext_phy_config;
1701
1702         if (!bnx2x_is_nvm_accessible(bp)) {
1703                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1704                    "cannot access eeprom when the interface is down\n");
1705                 return -EAGAIN;
1706         }
1707
1708         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1709            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1710            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1711            eeprom->len, eeprom->len);
1712
1713         /* parameters already validated in ethtool_set_eeprom */
1714
1715         /* PHY eeprom can be accessed only by the PMF */
1716         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1717             !bp->port.pmf) {
1718                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1719                    "wrong magic or interface is not pmf\n");
1720                 return -EINVAL;
1721         }
1722
1723         ext_phy_config =
1724                 SHMEM_RD(bp,
1725                          dev_info.port_hw_config[port].external_phy_config);
1726
1727         if (eeprom->magic == 0x50485950) {
1728                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1729                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1730
1731                 bnx2x_acquire_phy_lock(bp);
1732                 rc |= bnx2x_link_reset(&bp->link_params,
1733                                        &bp->link_vars, 0);
1734                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1735                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1736                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1737                                        MISC_REGISTERS_GPIO_HIGH, port);
1738                 bnx2x_release_phy_lock(bp);
1739                 bnx2x_link_report(bp);
1740
1741         } else if (eeprom->magic == 0x50485952) {
1742                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1743                 if (bp->state == BNX2X_STATE_OPEN) {
1744                         bnx2x_acquire_phy_lock(bp);
1745                         rc |= bnx2x_link_reset(&bp->link_params,
1746                                                &bp->link_vars, 1);
1747
1748                         rc |= bnx2x_phy_init(&bp->link_params,
1749                                              &bp->link_vars);
1750                         bnx2x_release_phy_lock(bp);
1751                         bnx2x_calc_fc_adv(bp);
1752                 }
1753         } else if (eeprom->magic == 0x53985943) {
1754                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1755                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1756                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1757
1758                         /* DSP Remove Download Mode */
1759                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1760                                        MISC_REGISTERS_GPIO_LOW, port);
1761
1762                         bnx2x_acquire_phy_lock(bp);
1763
1764                         bnx2x_sfx7101_sp_sw_reset(bp,
1765                                                 &bp->link_params.phy[EXT_PHY1]);
1766
1767                         /* wait 0.5 sec to allow it to run */
1768                         msleep(500);
1769                         bnx2x_ext_phy_hw_reset(bp, port);
1770                         msleep(500);
1771                         bnx2x_release_phy_lock(bp);
1772                 }
1773         } else
1774                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1775
1776         return rc;
1777 }
1778
1779 static int bnx2x_get_coalesce(struct net_device *dev,
1780                               struct ethtool_coalesce *coal)
1781 {
1782         struct bnx2x *bp = netdev_priv(dev);
1783
1784         memset(coal, 0, sizeof(struct ethtool_coalesce));
1785
1786         coal->rx_coalesce_usecs = bp->rx_ticks;
1787         coal->tx_coalesce_usecs = bp->tx_ticks;
1788
1789         return 0;
1790 }
1791
1792 static int bnx2x_set_coalesce(struct net_device *dev,
1793                               struct ethtool_coalesce *coal)
1794 {
1795         struct bnx2x *bp = netdev_priv(dev);
1796
1797         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1798         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1799                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1800
1801         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1802         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1803                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1804
1805         if (netif_running(dev))
1806                 bnx2x_update_coalesce(bp);
1807
1808         return 0;
1809 }
1810
1811 static void bnx2x_get_ringparam(struct net_device *dev,
1812                                 struct ethtool_ringparam *ering)
1813 {
1814         struct bnx2x *bp = netdev_priv(dev);
1815
1816         ering->rx_max_pending = MAX_RX_AVAIL;
1817
1818         if (bp->rx_ring_size)
1819                 ering->rx_pending = bp->rx_ring_size;
1820         else
1821                 ering->rx_pending = MAX_RX_AVAIL;
1822
1823         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1824         ering->tx_pending = bp->tx_ring_size;
1825 }
1826
1827 static int bnx2x_set_ringparam(struct net_device *dev,
1828                                struct ethtool_ringparam *ering)
1829 {
1830         struct bnx2x *bp = netdev_priv(dev);
1831
1832         DP(BNX2X_MSG_ETHTOOL,
1833            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1834            ering->rx_pending, ering->tx_pending);
1835
1836         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1837                 DP(BNX2X_MSG_ETHTOOL,
1838                    "Handling parity error recovery. Try again later\n");
1839                 return -EAGAIN;
1840         }
1841
1842         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1843             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1844                                                     MIN_RX_SIZE_TPA)) ||
1845             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1846             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1847                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1848                 return -EINVAL;
1849         }
1850
1851         bp->rx_ring_size = ering->rx_pending;
1852         bp->tx_ring_size = ering->tx_pending;
1853
1854         return bnx2x_reload_if_running(dev);
1855 }
1856
1857 static void bnx2x_get_pauseparam(struct net_device *dev,
1858                                  struct ethtool_pauseparam *epause)
1859 {
1860         struct bnx2x *bp = netdev_priv(dev);
1861         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1862         int cfg_reg;
1863
1864         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1865                            BNX2X_FLOW_CTRL_AUTO);
1866
1867         if (!epause->autoneg)
1868                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1869         else
1870                 cfg_reg = bp->link_params.req_fc_auto_adv;
1871
1872         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1873                             BNX2X_FLOW_CTRL_RX);
1874         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1875                             BNX2X_FLOW_CTRL_TX);
1876
1877         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1878            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1879            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1880 }
1881
1882 static int bnx2x_set_pauseparam(struct net_device *dev,
1883                                 struct ethtool_pauseparam *epause)
1884 {
1885         struct bnx2x *bp = netdev_priv(dev);
1886         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1887         if (IS_MF(bp))
1888                 return 0;
1889
1890         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1891            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1892            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1893
1894         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1895
1896         if (epause->rx_pause)
1897                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1898
1899         if (epause->tx_pause)
1900                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1901
1902         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1903                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1904
1905         if (epause->autoneg) {
1906                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1907                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1908                         return -EINVAL;
1909                 }
1910
1911                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1912                         bp->link_params.req_flow_ctrl[cfg_idx] =
1913                                 BNX2X_FLOW_CTRL_AUTO;
1914                 }
1915                 bp->link_params.req_fc_auto_adv = 0;
1916                 if (epause->rx_pause)
1917                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1918
1919                 if (epause->tx_pause)
1920                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1921
1922                 if (!bp->link_params.req_fc_auto_adv)
1923                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1924         }
1925
1926         DP(BNX2X_MSG_ETHTOOL,
1927            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1928
1929         if (netif_running(dev)) {
1930                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1931                 bnx2x_link_set(bp);
1932         }
1933
1934         return 0;
1935 }
1936
1937 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1938         "register_test (offline)    ",
1939         "memory_test (offline)      ",
1940         "int_loopback_test (offline)",
1941         "ext_loopback_test (offline)",
1942         "nvram_test (online)        ",
1943         "interrupt_test (online)    ",
1944         "link_test (online)         "
1945 };
1946
1947 enum {
1948         BNX2X_PRI_FLAG_ISCSI,
1949         BNX2X_PRI_FLAG_FCOE,
1950         BNX2X_PRI_FLAG_STORAGE,
1951         BNX2X_PRI_FLAG_LEN,
1952 };
1953
1954 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1955         "iSCSI offload support",
1956         "FCoE offload support",
1957         "Storage only interface"
1958 };
1959
1960 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1961 {
1962         u32 modes = 0;
1963
1964         if (eee_adv & SHMEM_EEE_100M_ADV)
1965                 modes |= ADVERTISED_100baseT_Full;
1966         if (eee_adv & SHMEM_EEE_1G_ADV)
1967                 modes |= ADVERTISED_1000baseT_Full;
1968         if (eee_adv & SHMEM_EEE_10G_ADV)
1969                 modes |= ADVERTISED_10000baseT_Full;
1970
1971         return modes;
1972 }
1973
1974 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1975 {
1976         u32 eee_adv = 0;
1977         if (modes & ADVERTISED_100baseT_Full)
1978                 eee_adv |= SHMEM_EEE_100M_ADV;
1979         if (modes & ADVERTISED_1000baseT_Full)
1980                 eee_adv |= SHMEM_EEE_1G_ADV;
1981         if (modes & ADVERTISED_10000baseT_Full)
1982                 eee_adv |= SHMEM_EEE_10G_ADV;
1983
1984         return eee_adv << shift;
1985 }
1986
1987 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1988 {
1989         struct bnx2x *bp = netdev_priv(dev);
1990         u32 eee_cfg;
1991
1992         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1993                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1994                 return -EOPNOTSUPP;
1995         }
1996
1997         eee_cfg = bp->link_vars.eee_status;
1998
1999         edata->supported =
2000                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2001                                  SHMEM_EEE_SUPPORTED_SHIFT);
2002
2003         edata->advertised =
2004                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2005                                  SHMEM_EEE_ADV_STATUS_SHIFT);
2006         edata->lp_advertised =
2007                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2008                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2009
2010         /* SHMEM value is in 16u units --> Convert to 1u units. */
2011         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2012
2013         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2014         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2015         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2016
2017         return 0;
2018 }
2019
2020 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2021 {
2022         struct bnx2x *bp = netdev_priv(dev);
2023         u32 eee_cfg;
2024         u32 advertised;
2025
2026         if (IS_MF(bp))
2027                 return 0;
2028
2029         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2030                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2031                 return -EOPNOTSUPP;
2032         }
2033
2034         eee_cfg = bp->link_vars.eee_status;
2035
2036         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2037                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2038                 return -EOPNOTSUPP;
2039         }
2040
2041         advertised = bnx2x_adv_to_eee(edata->advertised,
2042                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2043         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2044                 DP(BNX2X_MSG_ETHTOOL,
2045                    "Direct manipulation of EEE advertisement is not supported\n");
2046                 return -EINVAL;
2047         }
2048
2049         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2050                 DP(BNX2X_MSG_ETHTOOL,
2051                    "Maximal Tx Lpi timer supported is %x(u)\n",
2052                    EEE_MODE_TIMER_MASK);
2053                 return -EINVAL;
2054         }
2055         if (edata->tx_lpi_enabled &&
2056             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2057                 DP(BNX2X_MSG_ETHTOOL,
2058                    "Minimal Tx Lpi timer supported is %d(u)\n",
2059                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2060                 return -EINVAL;
2061         }
2062
2063         /* All is well; Apply changes*/
2064         if (edata->eee_enabled)
2065                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2066         else
2067                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2068
2069         if (edata->tx_lpi_enabled)
2070                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2071         else
2072                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2073
2074         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2075         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2076                                     EEE_MODE_TIMER_MASK) |
2077                                     EEE_MODE_OVERRIDE_NVRAM |
2078                                     EEE_MODE_OUTPUT_TIME;
2079
2080         /* Restart link to propagate changes */
2081         if (netif_running(dev)) {
2082                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2083                 bnx2x_force_link_reset(bp);
2084                 bnx2x_link_set(bp);
2085         }
2086
2087         return 0;
2088 }
2089
2090 enum {
2091         BNX2X_CHIP_E1_OFST = 0,
2092         BNX2X_CHIP_E1H_OFST,
2093         BNX2X_CHIP_E2_OFST,
2094         BNX2X_CHIP_E3_OFST,
2095         BNX2X_CHIP_E3B0_OFST,
2096         BNX2X_CHIP_MAX_OFST
2097 };
2098
2099 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2100 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2101 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2102 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2103 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2104
2105 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2106 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2107
2108 static int bnx2x_test_registers(struct bnx2x *bp)
2109 {
2110         int idx, i, rc = -ENODEV;
2111         u32 wr_val = 0, hw;
2112         int port = BP_PORT(bp);
2113         static const struct {
2114                 u32 hw;
2115                 u32 offset0;
2116                 u32 offset1;
2117                 u32 mask;
2118         } reg_tbl[] = {
2119 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2120                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2121                 { BNX2X_CHIP_MASK_ALL,
2122                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2123                 { BNX2X_CHIP_MASK_E1X,
2124                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2125                 { BNX2X_CHIP_MASK_ALL,
2126                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2127                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2128                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2129                 { BNX2X_CHIP_MASK_E3B0,
2130                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2131                 { BNX2X_CHIP_MASK_ALL,
2132                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2133                 { BNX2X_CHIP_MASK_ALL,
2134                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2135                 { BNX2X_CHIP_MASK_ALL,
2136                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2137                 { BNX2X_CHIP_MASK_ALL,
2138                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2139 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2140                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2141                 { BNX2X_CHIP_MASK_ALL,
2142                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2143                 { BNX2X_CHIP_MASK_ALL,
2144                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2145                 { BNX2X_CHIP_MASK_ALL,
2146                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2147                 { BNX2X_CHIP_MASK_ALL,
2148                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2149                 { BNX2X_CHIP_MASK_ALL,
2150                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2151                 { BNX2X_CHIP_MASK_ALL,
2152                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2153                 { BNX2X_CHIP_MASK_ALL,
2154                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2155                 { BNX2X_CHIP_MASK_ALL,
2156                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2157                 { BNX2X_CHIP_MASK_ALL,
2158                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2159 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2160                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2161                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2162                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2163                 { BNX2X_CHIP_MASK_ALL,
2164                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2165                 { BNX2X_CHIP_MASK_ALL,
2166                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2167                 { BNX2X_CHIP_MASK_ALL,
2168                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2169                 { BNX2X_CHIP_MASK_ALL,
2170                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2171                 { BNX2X_CHIP_MASK_ALL,
2172                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2173                 { BNX2X_CHIP_MASK_ALL,
2174                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2175                 { BNX2X_CHIP_MASK_ALL,
2176                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2177                 { BNX2X_CHIP_MASK_ALL,
2178                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2179 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2180                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2181                 { BNX2X_CHIP_MASK_ALL,
2182                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2183                 { BNX2X_CHIP_MASK_ALL,
2184                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2185                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2186                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2187                 { BNX2X_CHIP_MASK_ALL,
2188                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2189                 { BNX2X_CHIP_MASK_ALL,
2190                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2191                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2192                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2193                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2194                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2195
2196                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2197         };
2198
2199         if (!bnx2x_is_nvm_accessible(bp)) {
2200                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2201                    "cannot access eeprom when the interface is down\n");
2202                 return rc;
2203         }
2204
2205         if (CHIP_IS_E1(bp))
2206                 hw = BNX2X_CHIP_MASK_E1;
2207         else if (CHIP_IS_E1H(bp))
2208                 hw = BNX2X_CHIP_MASK_E1H;
2209         else if (CHIP_IS_E2(bp))
2210                 hw = BNX2X_CHIP_MASK_E2;
2211         else if (CHIP_IS_E3B0(bp))
2212                 hw = BNX2X_CHIP_MASK_E3B0;
2213         else /* e3 A0 */
2214                 hw = BNX2X_CHIP_MASK_E3;
2215
2216         /* Repeat the test twice:
2217          * First by writing 0x00000000, second by writing 0xffffffff
2218          */
2219         for (idx = 0; idx < 2; idx++) {
2220
2221                 switch (idx) {
2222                 case 0:
2223                         wr_val = 0;
2224                         break;
2225                 case 1:
2226                         wr_val = 0xffffffff;
2227                         break;
2228                 }
2229
2230                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2231                         u32 offset, mask, save_val, val;
2232                         if (!(hw & reg_tbl[i].hw))
2233                                 continue;
2234
2235                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2236                         mask = reg_tbl[i].mask;
2237
2238                         save_val = REG_RD(bp, offset);
2239
2240                         REG_WR(bp, offset, wr_val & mask);
2241
2242                         val = REG_RD(bp, offset);
2243
2244                         /* Restore the original register's value */
2245                         REG_WR(bp, offset, save_val);
2246
2247                         /* verify value is as expected */
2248                         if ((val & mask) != (wr_val & mask)) {
2249                                 DP(BNX2X_MSG_ETHTOOL,
2250                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2251                                    offset, val, wr_val, mask);
2252                                 goto test_reg_exit;
2253                         }
2254                 }
2255         }
2256
2257         rc = 0;
2258
2259 test_reg_exit:
2260         return rc;
2261 }
2262
2263 static int bnx2x_test_memory(struct bnx2x *bp)
2264 {
2265         int i, j, rc = -ENODEV;
2266         u32 val, index;
2267         static const struct {
2268                 u32 offset;
2269                 int size;
2270         } mem_tbl[] = {
2271                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2272                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2273                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2274                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2275                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2276                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2277                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2278
2279                 { 0xffffffff, 0 }
2280         };
2281
2282         static const struct {
2283                 char *name;
2284                 u32 offset;
2285                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2286         } prty_tbl[] = {
2287                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2288                         {0x3ffc0, 0,   0, 0} },
2289                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2290                         {0x2,     0x2, 0, 0} },
2291                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2292                         {0,       0,   0, 0} },
2293                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2294                         {0x3ffc0, 0,   0, 0} },
2295                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2296                         {0x3ffc0, 0,   0, 0} },
2297                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2298                         {0x3ffc1, 0,   0, 0} },
2299
2300                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2301         };
2302
2303         if (!bnx2x_is_nvm_accessible(bp)) {
2304                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2305                    "cannot access eeprom when the interface is down\n");
2306                 return rc;
2307         }
2308
2309         if (CHIP_IS_E1(bp))
2310                 index = BNX2X_CHIP_E1_OFST;
2311         else if (CHIP_IS_E1H(bp))
2312                 index = BNX2X_CHIP_E1H_OFST;
2313         else if (CHIP_IS_E2(bp))
2314                 index = BNX2X_CHIP_E2_OFST;
2315         else /* e3 */
2316                 index = BNX2X_CHIP_E3_OFST;
2317
2318         /* pre-Check the parity status */
2319         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2320                 val = REG_RD(bp, prty_tbl[i].offset);
2321                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2322                         DP(BNX2X_MSG_ETHTOOL,
2323                            "%s is 0x%x\n", prty_tbl[i].name, val);
2324                         goto test_mem_exit;
2325                 }
2326         }
2327
2328         /* Go through all the memories */
2329         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2330                 for (j = 0; j < mem_tbl[i].size; j++)
2331                         REG_RD(bp, mem_tbl[i].offset + j*4);
2332
2333         /* Check the parity status */
2334         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2335                 val = REG_RD(bp, prty_tbl[i].offset);
2336                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2337                         DP(BNX2X_MSG_ETHTOOL,
2338                            "%s is 0x%x\n", prty_tbl[i].name, val);
2339                         goto test_mem_exit;
2340                 }
2341         }
2342
2343         rc = 0;
2344
2345 test_mem_exit:
2346         return rc;
2347 }
2348
2349 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2350 {
2351         int cnt = 1400;
2352
2353         if (link_up) {
2354                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2355                         msleep(20);
2356
2357                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2358                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2359
2360                 cnt = 1400;
2361                 while (!bp->link_vars.link_up && cnt--)
2362                         msleep(20);
2363
2364                 if (cnt <= 0 && !bp->link_vars.link_up)
2365                         DP(BNX2X_MSG_ETHTOOL,
2366                            "Timeout waiting for link init\n");
2367         }
2368 }
2369
2370 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2371 {
2372         unsigned int pkt_size, num_pkts, i;
2373         struct sk_buff *skb;
2374         unsigned char *packet;
2375         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2376         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2377         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2378         u16 tx_start_idx, tx_idx;
2379         u16 rx_start_idx, rx_idx;
2380         u16 pkt_prod, bd_prod;
2381         struct sw_tx_bd *tx_buf;
2382         struct eth_tx_start_bd *tx_start_bd;
2383         dma_addr_t mapping;
2384         union eth_rx_cqe *cqe;
2385         u8 cqe_fp_flags, cqe_fp_type;
2386         struct sw_rx_bd *rx_buf;
2387         u16 len;
2388         int rc = -ENODEV;
2389         u8 *data;
2390         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2391                                                        txdata->txq_index);
2392
2393         /* check the loopback mode */
2394         switch (loopback_mode) {
2395         case BNX2X_PHY_LOOPBACK:
2396                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2397                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2398                         return -EINVAL;
2399                 }
2400                 break;
2401         case BNX2X_MAC_LOOPBACK:
2402                 if (CHIP_IS_E3(bp)) {
2403                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2404                         if (bp->port.supported[cfg_idx] &
2405                             (SUPPORTED_10000baseT_Full |
2406                              SUPPORTED_20000baseMLD2_Full |
2407                              SUPPORTED_20000baseKR2_Full))
2408                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2409                         else
2410                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2411                 } else
2412                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2413
2414                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2415                 break;
2416         case BNX2X_EXT_LOOPBACK:
2417                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2418                         DP(BNX2X_MSG_ETHTOOL,
2419                            "Can't configure external loopback\n");
2420                         return -EINVAL;
2421                 }
2422                 break;
2423         default:
2424                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2425                 return -EINVAL;
2426         }
2427
2428         /* prepare the loopback packet */
2429         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2430                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2431         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2432         if (!skb) {
2433                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2434                 rc = -ENOMEM;
2435                 goto test_loopback_exit;
2436         }
2437         packet = skb_put(skb, pkt_size);
2438         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2439         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2440         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2441         for (i = ETH_HLEN; i < pkt_size; i++)
2442                 packet[i] = (unsigned char) (i & 0xff);
2443         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2444                                  skb_headlen(skb), DMA_TO_DEVICE);
2445         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2446                 rc = -ENOMEM;
2447                 dev_kfree_skb(skb);
2448                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2449                 goto test_loopback_exit;
2450         }
2451
2452         /* send the loopback packet */
2453         num_pkts = 0;
2454         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2455         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2456
2457         netdev_tx_sent_queue(txq, skb->len);
2458
2459         pkt_prod = txdata->tx_pkt_prod++;
2460         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2461         tx_buf->first_bd = txdata->tx_bd_prod;
2462         tx_buf->skb = skb;
2463         tx_buf->flags = 0;
2464
2465         bd_prod = TX_BD(txdata->tx_bd_prod);
2466         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2467         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2468         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2469         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2470         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2471         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2472         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2473         SET_FLAG(tx_start_bd->general_data,
2474                  ETH_TX_START_BD_HDR_NBDS,
2475                  1);
2476         SET_FLAG(tx_start_bd->general_data,
2477                  ETH_TX_START_BD_PARSE_NBDS,
2478                  0);
2479
2480         /* turn on parsing and get a BD */
2481         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2482
2483         if (CHIP_IS_E1x(bp)) {
2484                 u16 global_data = 0;
2485                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2486                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2487                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2488                 SET_FLAG(global_data,
2489                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2490                 pbd_e1x->global_data = cpu_to_le16(global_data);
2491         } else {
2492                 u32 parsing_data = 0;
2493                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2494                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2495                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2496                 SET_FLAG(parsing_data,
2497                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2498                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2499         }
2500         wmb();
2501
2502         txdata->tx_db.data.prod += 2;
2503         barrier();
2504         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2505
2506         mmiowb();
2507         barrier();
2508
2509         num_pkts++;
2510         txdata->tx_bd_prod += 2; /* start + pbd */
2511
2512         udelay(100);
2513
2514         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2515         if (tx_idx != tx_start_idx + num_pkts)
2516                 goto test_loopback_exit;
2517
2518         /* Unlike HC IGU won't generate an interrupt for status block
2519          * updates that have been performed while interrupts were
2520          * disabled.
2521          */
2522         if (bp->common.int_block == INT_BLOCK_IGU) {
2523                 /* Disable local BHes to prevent a dead-lock situation between
2524                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2525                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2526                  */
2527                 local_bh_disable();
2528                 bnx2x_tx_int(bp, txdata);
2529                 local_bh_enable();
2530         }
2531
2532         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2533         if (rx_idx != rx_start_idx + num_pkts)
2534                 goto test_loopback_exit;
2535
2536         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2537         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2538         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2539         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2540                 goto test_loopback_rx_exit;
2541
2542         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2543         if (len != pkt_size)
2544                 goto test_loopback_rx_exit;
2545
2546         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2547         dma_sync_single_for_cpu(&bp->pdev->dev,
2548                                    dma_unmap_addr(rx_buf, mapping),
2549                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2550         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2551         for (i = ETH_HLEN; i < pkt_size; i++)
2552                 if (*(data + i) != (unsigned char) (i & 0xff))
2553                         goto test_loopback_rx_exit;
2554
2555         rc = 0;
2556
2557 test_loopback_rx_exit:
2558
2559         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2560         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2561         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2562         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2563
2564         /* Update producers */
2565         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2566                              fp_rx->rx_sge_prod);
2567
2568 test_loopback_exit:
2569         bp->link_params.loopback_mode = LOOPBACK_NONE;
2570
2571         return rc;
2572 }
2573
2574 static int bnx2x_test_loopback(struct bnx2x *bp)
2575 {
2576         int rc = 0, res;
2577
2578         if (BP_NOMCP(bp))
2579                 return rc;
2580
2581         if (!netif_running(bp->dev))
2582                 return BNX2X_LOOPBACK_FAILED;
2583
2584         bnx2x_netif_stop(bp, 1);
2585         bnx2x_acquire_phy_lock(bp);
2586
2587         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2588         if (res) {
2589                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2590                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2591         }
2592
2593         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2594         if (res) {
2595                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2596                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2597         }
2598
2599         bnx2x_release_phy_lock(bp);
2600         bnx2x_netif_start(bp);
2601
2602         return rc;
2603 }
2604
2605 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2606 {
2607         int rc;
2608         u8 is_serdes =
2609                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2610
2611         if (BP_NOMCP(bp))
2612                 return -ENODEV;
2613
2614         if (!netif_running(bp->dev))
2615                 return BNX2X_EXT_LOOPBACK_FAILED;
2616
2617         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2618         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2619         if (rc) {
2620                 DP(BNX2X_MSG_ETHTOOL,
2621                    "Can't perform self-test, nic_load (for external lb) failed\n");
2622                 return -ENODEV;
2623         }
2624         bnx2x_wait_for_link(bp, 1, is_serdes);
2625
2626         bnx2x_netif_stop(bp, 1);
2627
2628         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2629         if (rc)
2630                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2631
2632         bnx2x_netif_start(bp);
2633
2634         return rc;
2635 }
2636
2637 struct code_entry {
2638         u32 sram_start_addr;
2639         u32 code_attribute;
2640 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2641 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2642 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2643 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2644         u32 nvm_start_addr;
2645 };
2646
2647 #define CODE_ENTRY_MAX                  16
2648 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2649 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2650 #define NVRAM_DIR_OFFSET                0x14
2651
2652 #define EXTENDED_DIR_EXISTS(code)                                         \
2653         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2654          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2655
2656 #define CRC32_RESIDUAL                  0xdebb20e3
2657 #define CRC_BUFF_SIZE                   256
2658
2659 static int bnx2x_nvram_crc(struct bnx2x *bp,
2660                            int offset,
2661                            int size,
2662                            u8 *buff)
2663 {
2664         u32 crc = ~0;
2665         int rc = 0, done = 0;
2666
2667         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2668            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2669
2670         while (done < size) {
2671                 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2672
2673                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2674
2675                 if (rc)
2676                         return rc;
2677
2678                 crc = crc32_le(crc, buff, count);
2679                 done += count;
2680         }
2681
2682         if (crc != CRC32_RESIDUAL)
2683                 rc = -EINVAL;
2684
2685         return rc;
2686 }
2687
2688 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2689                                 struct code_entry *entry,
2690                                 u8 *buff)
2691 {
2692         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2693         u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2694         int rc;
2695
2696         /* Zero-length images and AFEX profiles do not have CRC */
2697         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2698                 return 0;
2699
2700         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2701         if (rc)
2702                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2703                    "image %x has failed crc test (rc %d)\n", type, rc);
2704
2705         return rc;
2706 }
2707
2708 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2709 {
2710         int rc;
2711         struct code_entry entry;
2712
2713         rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2714         if (rc)
2715                 return rc;
2716
2717         return bnx2x_test_nvram_dir(bp, &entry, buff);
2718 }
2719
2720 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2721 {
2722         u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2723         struct code_entry entry;
2724         int i;
2725
2726         rc = bnx2x_nvram_read32(bp,
2727                                 dir_offset +
2728                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2729                                 (u32 *)&entry, sizeof(entry));
2730         if (rc)
2731                 return rc;
2732
2733         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2734                 return 0;
2735
2736         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2737                                 &cnt, sizeof(u32));
2738         if (rc)
2739                 return rc;
2740
2741         dir_offset = entry.nvm_start_addr + 8;
2742
2743         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2744                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2745                                               sizeof(struct code_entry) * i,
2746                                           buff);
2747                 if (rc)
2748                         return rc;
2749         }
2750
2751         return 0;
2752 }
2753
2754 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2755 {
2756         u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2757         int i;
2758
2759         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2760
2761         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2762                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2763                                               sizeof(struct code_entry) * i,
2764                                           buff);
2765                 if (rc)
2766                         return rc;
2767         }
2768
2769         return bnx2x_test_nvram_ext_dirs(bp, buff);
2770 }
2771
2772 struct crc_pair {
2773         int offset;
2774         int size;
2775 };
2776
2777 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2778                                 const struct crc_pair *nvram_tbl, u8 *buf)
2779 {
2780         int i;
2781
2782         for (i = 0; nvram_tbl[i].size; i++) {
2783                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2784                                          nvram_tbl[i].size, buf);
2785                 if (rc) {
2786                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2787                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2788                            i, rc);
2789                         return rc;
2790                 }
2791         }
2792
2793         return 0;
2794 }
2795
2796 static int bnx2x_test_nvram(struct bnx2x *bp)
2797 {
2798         const struct crc_pair nvram_tbl[] = {
2799                 {     0,  0x14 }, /* bootstrap */
2800                 {  0x14,  0xec }, /* dir */
2801                 { 0x100, 0x350 }, /* manuf_info */
2802                 { 0x450,  0xf0 }, /* feature_info */
2803                 { 0x640,  0x64 }, /* upgrade_key_info */
2804                 { 0x708,  0x70 }, /* manuf_key_info */
2805                 {     0,     0 }
2806         };
2807         const struct crc_pair nvram_tbl2[] = {
2808                 { 0x7e8, 0x350 }, /* manuf_info2 */
2809                 { 0xb38,  0xf0 }, /* feature_info */
2810                 {     0,     0 }
2811         };
2812
2813         u8 *buf;
2814         int rc;
2815         u32 magic;
2816
2817         if (BP_NOMCP(bp))
2818                 return 0;
2819
2820         buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2821         if (!buf) {
2822                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2823                 rc = -ENOMEM;
2824                 goto test_nvram_exit;
2825         }
2826
2827         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2828         if (rc) {
2829                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2830                    "magic value read (rc %d)\n", rc);
2831                 goto test_nvram_exit;
2832         }
2833
2834         if (magic != 0x669955aa) {
2835                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2836                    "wrong magic value (0x%08x)\n", magic);
2837                 rc = -ENODEV;
2838                 goto test_nvram_exit;
2839         }
2840
2841         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2842         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2843         if (rc)
2844                 goto test_nvram_exit;
2845
2846         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2847                 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2848                            SHARED_HW_CFG_HIDE_PORT1;
2849
2850                 if (!hide) {
2851                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2852                            "Port 1 CRC test-set\n");
2853                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2854                         if (rc)
2855                                 goto test_nvram_exit;
2856                 }
2857         }
2858
2859         rc = bnx2x_test_nvram_dirs(bp, buf);
2860
2861 test_nvram_exit:
2862         kfree(buf);
2863         return rc;
2864 }
2865
2866 /* Send an EMPTY ramrod on the first queue */
2867 static int bnx2x_test_intr(struct bnx2x *bp)
2868 {
2869         struct bnx2x_queue_state_params params = {NULL};
2870
2871         if (!netif_running(bp->dev)) {
2872                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2873                    "cannot access eeprom when the interface is down\n");
2874                 return -ENODEV;
2875         }
2876
2877         params.q_obj = &bp->sp_objs->q_obj;
2878         params.cmd = BNX2X_Q_CMD_EMPTY;
2879
2880         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2881
2882         return bnx2x_queue_state_change(bp, &params);
2883 }
2884
2885 static void bnx2x_self_test(struct net_device *dev,
2886                             struct ethtool_test *etest, u64 *buf)
2887 {
2888         struct bnx2x *bp = netdev_priv(dev);
2889         u8 is_serdes, link_up;
2890         int rc, cnt = 0;
2891
2892         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2893                 netdev_err(bp->dev,
2894                            "Handling parity error recovery. Try again later\n");
2895                 etest->flags |= ETH_TEST_FL_FAILED;
2896                 return;
2897         }
2898
2899         DP(BNX2X_MSG_ETHTOOL,
2900            "Self-test command parameters: offline = %d, external_lb = %d\n",
2901            (etest->flags & ETH_TEST_FL_OFFLINE),
2902            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2903
2904         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2905
2906         if (bnx2x_test_nvram(bp) != 0) {
2907                 if (!IS_MF(bp))
2908                         buf[4] = 1;
2909                 else
2910                         buf[0] = 1;
2911                 etest->flags |= ETH_TEST_FL_FAILED;
2912         }
2913
2914         if (!netif_running(dev)) {
2915                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2916                 return;
2917         }
2918
2919         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2920         link_up = bp->link_vars.link_up;
2921         /* offline tests are not supported in MF mode */
2922         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2923                 int port = BP_PORT(bp);
2924                 u32 val;
2925
2926                 /* save current value of input enable for TX port IF */
2927                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2928                 /* disable input for TX port IF */
2929                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2930
2931                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2932                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2933                 if (rc) {
2934                         etest->flags |= ETH_TEST_FL_FAILED;
2935                         DP(BNX2X_MSG_ETHTOOL,
2936                            "Can't perform self-test, nic_load (for offline) failed\n");
2937                         return;
2938                 }
2939
2940                 /* wait until link state is restored */
2941                 bnx2x_wait_for_link(bp, 1, is_serdes);
2942
2943                 if (bnx2x_test_registers(bp) != 0) {
2944                         buf[0] = 1;
2945                         etest->flags |= ETH_TEST_FL_FAILED;
2946                 }
2947                 if (bnx2x_test_memory(bp) != 0) {
2948                         buf[1] = 1;
2949                         etest->flags |= ETH_TEST_FL_FAILED;
2950                 }
2951
2952                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2953                 if (buf[2] != 0)
2954                         etest->flags |= ETH_TEST_FL_FAILED;
2955
2956                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2957                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2958                         if (buf[3] != 0)
2959                                 etest->flags |= ETH_TEST_FL_FAILED;
2960                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2961                 }
2962
2963                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2964
2965                 /* restore input for TX port IF */
2966                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2967                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2968                 if (rc) {
2969                         etest->flags |= ETH_TEST_FL_FAILED;
2970                         DP(BNX2X_MSG_ETHTOOL,
2971                            "Can't perform self-test, nic_load (for online) failed\n");
2972                         return;
2973                 }
2974                 /* wait until link state is restored */
2975                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2976         }
2977
2978         if (bnx2x_test_intr(bp) != 0) {
2979                 if (!IS_MF(bp))
2980                         buf[5] = 1;
2981                 else
2982                         buf[1] = 1;
2983                 etest->flags |= ETH_TEST_FL_FAILED;
2984         }
2985
2986         if (link_up) {
2987                 cnt = 100;
2988                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2989                         msleep(20);
2990         }
2991
2992         if (!cnt) {
2993                 if (!IS_MF(bp))
2994                         buf[6] = 1;
2995                 else
2996                         buf[2] = 1;
2997                 etest->flags |= ETH_TEST_FL_FAILED;
2998         }
2999 }
3000
3001 #define IS_PORT_STAT(i) \
3002         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3003 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3004 #define IS_MF_MODE_STAT(bp) \
3005                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
3006
3007 /* ethtool statistics are displayed for all regular ethernet queues and the
3008  * fcoe L2 queue if not disabled
3009  */
3010 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3011 {
3012         return BNX2X_NUM_ETH_QUEUES(bp);
3013 }
3014
3015 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3016 {
3017         struct bnx2x *bp = netdev_priv(dev);
3018         int i, num_strings = 0;
3019
3020         switch (stringset) {
3021         case ETH_SS_STATS:
3022                 if (is_multi(bp)) {
3023                         num_strings = bnx2x_num_stat_queues(bp) *
3024                                       BNX2X_NUM_Q_STATS;
3025                 } else
3026                         num_strings = 0;
3027                 if (IS_MF_MODE_STAT(bp)) {
3028                         for (i = 0; i < BNX2X_NUM_STATS; i++)
3029                                 if (IS_FUNC_STAT(i))
3030                                         num_strings++;
3031                 } else
3032                         num_strings += BNX2X_NUM_STATS;
3033
3034                 return num_strings;
3035
3036         case ETH_SS_TEST:
3037                 return BNX2X_NUM_TESTS(bp);
3038
3039         case ETH_SS_PRIV_FLAGS:
3040                 return BNX2X_PRI_FLAG_LEN;
3041
3042         default:
3043                 return -EINVAL;
3044         }
3045 }
3046
3047 static u32 bnx2x_get_private_flags(struct net_device *dev)
3048 {
3049         struct bnx2x *bp = netdev_priv(dev);
3050         u32 flags = 0;
3051
3052         flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3053         flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3054         flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3055
3056         return flags;
3057 }
3058
3059 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3060 {
3061         struct bnx2x *bp = netdev_priv(dev);
3062         int i, j, k, start;
3063         char queue_name[MAX_QUEUE_NAME_LEN+1];
3064
3065         switch (stringset) {
3066         case ETH_SS_STATS:
3067                 k = 0;
3068                 if (is_multi(bp)) {
3069                         for_each_eth_queue(bp, i) {
3070                                 memset(queue_name, 0, sizeof(queue_name));
3071                                 sprintf(queue_name, "%d", i);
3072                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3073                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3074                                                 ETH_GSTRING_LEN,
3075                                                 bnx2x_q_stats_arr[j].string,
3076                                                 queue_name);
3077                                 k += BNX2X_NUM_Q_STATS;
3078                         }
3079                 }
3080
3081                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3082                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
3083                                 continue;
3084                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3085                                    bnx2x_stats_arr[i].string);
3086                         j++;
3087                 }
3088
3089                 break;
3090
3091         case ETH_SS_TEST:
3092                 /* First 4 tests cannot be done in MF mode */
3093                 if (!IS_MF(bp))
3094                         start = 0;
3095                 else
3096                         start = 4;
3097                 memcpy(buf, bnx2x_tests_str_arr + start,
3098                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3099                 break;
3100
3101         case ETH_SS_PRIV_FLAGS:
3102                 memcpy(buf, bnx2x_private_arr,
3103                        ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3104                 break;
3105         }
3106 }
3107
3108 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3109                                     struct ethtool_stats *stats, u64 *buf)
3110 {
3111         struct bnx2x *bp = netdev_priv(dev);
3112         u32 *hw_stats, *offset;
3113         int i, j, k = 0;
3114
3115         if (is_multi(bp)) {
3116                 for_each_eth_queue(bp, i) {
3117                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3118                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3119                                 if (bnx2x_q_stats_arr[j].size == 0) {
3120                                         /* skip this counter */
3121                                         buf[k + j] = 0;
3122                                         continue;
3123                                 }
3124                                 offset = (hw_stats +
3125                                           bnx2x_q_stats_arr[j].offset);
3126                                 if (bnx2x_q_stats_arr[j].size == 4) {
3127                                         /* 4-byte counter */
3128                                         buf[k + j] = (u64) *offset;
3129                                         continue;
3130                                 }
3131                                 /* 8-byte counter */
3132                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3133                         }
3134                         k += BNX2X_NUM_Q_STATS;
3135                 }
3136         }
3137
3138         hw_stats = (u32 *)&bp->eth_stats;
3139         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3140                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
3141                         continue;
3142                 if (bnx2x_stats_arr[i].size == 0) {
3143                         /* skip this counter */
3144                         buf[k + j] = 0;
3145                         j++;
3146                         continue;
3147                 }
3148                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3149                 if (bnx2x_stats_arr[i].size == 4) {
3150                         /* 4-byte counter */
3151                         buf[k + j] = (u64) *offset;
3152                         j++;
3153                         continue;
3154                 }
3155                 /* 8-byte counter */
3156                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3157                 j++;
3158         }
3159 }
3160
3161 static int bnx2x_set_phys_id(struct net_device *dev,
3162                              enum ethtool_phys_id_state state)
3163 {
3164         struct bnx2x *bp = netdev_priv(dev);
3165
3166         if (!bnx2x_is_nvm_accessible(bp)) {
3167                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3168                    "cannot access eeprom when the interface is down\n");
3169                 return -EAGAIN;
3170         }
3171
3172         switch (state) {
3173         case ETHTOOL_ID_ACTIVE:
3174                 return 1;       /* cycle on/off once per second */
3175
3176         case ETHTOOL_ID_ON:
3177                 bnx2x_acquire_phy_lock(bp);
3178                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3179                               LED_MODE_ON, SPEED_1000);
3180                 bnx2x_release_phy_lock(bp);
3181                 break;
3182
3183         case ETHTOOL_ID_OFF:
3184                 bnx2x_acquire_phy_lock(bp);
3185                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3186                               LED_MODE_FRONT_PANEL_OFF, 0);
3187                 bnx2x_release_phy_lock(bp);
3188                 break;
3189
3190         case ETHTOOL_ID_INACTIVE:
3191                 bnx2x_acquire_phy_lock(bp);
3192                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3193                               LED_MODE_OPER,
3194                               bp->link_vars.line_speed);
3195                 bnx2x_release_phy_lock(bp);
3196         }
3197
3198         return 0;
3199 }
3200
3201 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3202 {
3203         switch (info->flow_type) {
3204         case TCP_V4_FLOW:
3205         case TCP_V6_FLOW:
3206                 info->data = RXH_IP_SRC | RXH_IP_DST |
3207                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3208                 break;
3209         case UDP_V4_FLOW:
3210                 if (bp->rss_conf_obj.udp_rss_v4)
3211                         info->data = RXH_IP_SRC | RXH_IP_DST |
3212                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3213                 else
3214                         info->data = RXH_IP_SRC | RXH_IP_DST;
3215                 break;
3216         case UDP_V6_FLOW:
3217                 if (bp->rss_conf_obj.udp_rss_v6)
3218                         info->data = RXH_IP_SRC | RXH_IP_DST |
3219                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3220                 else
3221                         info->data = RXH_IP_SRC | RXH_IP_DST;
3222                 break;
3223         case IPV4_FLOW:
3224         case IPV6_FLOW:
3225                 info->data = RXH_IP_SRC | RXH_IP_DST;
3226                 break;
3227         default:
3228                 info->data = 0;
3229                 break;
3230         }
3231
3232         return 0;
3233 }
3234
3235 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3236                            u32 *rules __always_unused)
3237 {
3238         struct bnx2x *bp = netdev_priv(dev);
3239
3240         switch (info->cmd) {
3241         case ETHTOOL_GRXRINGS:
3242                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3243                 return 0;
3244         case ETHTOOL_GRXFH:
3245                 return bnx2x_get_rss_flags(bp, info);
3246         default:
3247                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3248                 return -EOPNOTSUPP;
3249         }
3250 }
3251
3252 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3253 {
3254         int udp_rss_requested;
3255
3256         DP(BNX2X_MSG_ETHTOOL,
3257            "Set rss flags command parameters: flow type = %d, data = %llu\n",
3258            info->flow_type, info->data);
3259
3260         switch (info->flow_type) {
3261         case TCP_V4_FLOW:
3262         case TCP_V6_FLOW:
3263                 /* For TCP only 4-tupple hash is supported */
3264                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3265                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3266                         DP(BNX2X_MSG_ETHTOOL,
3267                            "Command parameters not supported\n");
3268                         return -EINVAL;
3269                 }
3270                 return 0;
3271
3272         case UDP_V4_FLOW:
3273         case UDP_V6_FLOW:
3274                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3275                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3276                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
3277                         udp_rss_requested = 1;
3278                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3279                         udp_rss_requested = 0;
3280                 else
3281                         return -EINVAL;
3282                 if ((info->flow_type == UDP_V4_FLOW) &&
3283                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3284                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3285                         DP(BNX2X_MSG_ETHTOOL,
3286                            "rss re-configured, UDP 4-tupple %s\n",
3287                            udp_rss_requested ? "enabled" : "disabled");
3288                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3289                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3290                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3291                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3292                         DP(BNX2X_MSG_ETHTOOL,
3293                            "rss re-configured, UDP 4-tupple %s\n",
3294                            udp_rss_requested ? "enabled" : "disabled");
3295                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3296                 }
3297                 return 0;
3298
3299         case IPV4_FLOW:
3300         case IPV6_FLOW:
3301                 /* For IP only 2-tupple hash is supported */
3302                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3303                         DP(BNX2X_MSG_ETHTOOL,
3304                            "Command parameters not supported\n");
3305                         return -EINVAL;
3306                 }
3307                 return 0;
3308
3309         case SCTP_V4_FLOW:
3310         case AH_ESP_V4_FLOW:
3311         case AH_V4_FLOW:
3312         case ESP_V4_FLOW:
3313         case SCTP_V6_FLOW:
3314         case AH_ESP_V6_FLOW:
3315         case AH_V6_FLOW:
3316         case ESP_V6_FLOW:
3317         case IP_USER_FLOW:
3318         case ETHER_FLOW:
3319                 /* RSS is not supported for these protocols */
3320                 if (info->data) {
3321                         DP(BNX2X_MSG_ETHTOOL,
3322                            "Command parameters not supported\n");
3323                         return -EINVAL;
3324                 }
3325                 return 0;
3326
3327         default:
3328                 return -EINVAL;
3329         }
3330 }
3331
3332 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3333 {
3334         struct bnx2x *bp = netdev_priv(dev);
3335
3336         switch (info->cmd) {
3337         case ETHTOOL_SRXFH:
3338                 return bnx2x_set_rss_flags(bp, info);
3339         default:
3340                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3341                 return -EOPNOTSUPP;
3342         }
3343 }
3344
3345 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3346 {
3347         return T_ETH_INDIRECTION_TABLE_SIZE;
3348 }
3349
3350 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
3351 {
3352         struct bnx2x *bp = netdev_priv(dev);
3353         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3354         size_t i;
3355
3356         /* Get the current configuration of the RSS indirection table */
3357         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3358
3359         /*
3360          * We can't use a memcpy() as an internal storage of an
3361          * indirection table is a u8 array while indir->ring_index
3362          * points to an array of u32.
3363          *
3364          * Indirection table contains the FW Client IDs, so we need to
3365          * align the returned table to the Client ID of the leading RSS
3366          * queue.
3367          */
3368         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3369                 indir[i] = ind_table[i] - bp->fp->cl_id;
3370
3371         return 0;
3372 }
3373
3374 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
3375 {
3376         struct bnx2x *bp = netdev_priv(dev);
3377         size_t i;
3378
3379         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3380                 /*
3381                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3382                  * as an internal storage of an indirection table is a u8 array
3383                  * while indir->ring_index points to an array of u32.
3384                  *
3385                  * Indirection table contains the FW Client IDs, so we need to
3386                  * align the received table to the Client ID of the leading RSS
3387                  * queue
3388                  */
3389                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3390         }
3391
3392         return bnx2x_config_rss_eth(bp, false);
3393 }
3394
3395 /**
3396  * bnx2x_get_channels - gets the number of RSS queues.
3397  *
3398  * @dev:                net device
3399  * @channels:           returns the number of max / current queues
3400  */
3401 static void bnx2x_get_channels(struct net_device *dev,
3402                                struct ethtool_channels *channels)
3403 {
3404         struct bnx2x *bp = netdev_priv(dev);
3405
3406         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3407         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3408 }
3409
3410 /**
3411  * bnx2x_change_num_queues - change the number of RSS queues.
3412  *
3413  * @bp:                 bnx2x private structure
3414  *
3415  * Re-configure interrupt mode to get the new number of MSI-X
3416  * vectors and re-add NAPI objects.
3417  */
3418 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3419 {
3420         bnx2x_disable_msi(bp);
3421         bp->num_ethernet_queues = num_rss;
3422         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3423         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3424         bnx2x_set_int_mode(bp);
3425 }
3426
3427 /**
3428  * bnx2x_set_channels - sets the number of RSS queues.
3429  *
3430  * @dev:                net device
3431  * @channels:           includes the number of queues requested
3432  */
3433 static int bnx2x_set_channels(struct net_device *dev,
3434                               struct ethtool_channels *channels)
3435 {
3436         struct bnx2x *bp = netdev_priv(dev);
3437
3438         DP(BNX2X_MSG_ETHTOOL,
3439            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3440            channels->rx_count, channels->tx_count, channels->other_count,
3441            channels->combined_count);
3442
3443         /* We don't support separate rx / tx channels.
3444          * We don't allow setting 'other' channels.
3445          */
3446         if (channels->rx_count || channels->tx_count || channels->other_count
3447             || (channels->combined_count == 0) ||
3448             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3449                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3450                 return -EINVAL;
3451         }
3452
3453         /* Check if there was a change in the active parameters */
3454         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3455                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3456                 return 0;
3457         }
3458
3459         /* Set the requested number of queues in bp context.
3460          * Note that the actual number of queues created during load may be
3461          * less than requested if memory is low.
3462          */
3463         if (unlikely(!netif_running(dev))) {
3464                 bnx2x_change_num_queues(bp, channels->combined_count);
3465                 return 0;
3466         }
3467         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3468         bnx2x_change_num_queues(bp, channels->combined_count);
3469         return bnx2x_nic_load(bp, LOAD_NORMAL);
3470 }
3471
3472 static const struct ethtool_ops bnx2x_ethtool_ops = {
3473         .get_settings           = bnx2x_get_settings,
3474         .set_settings           = bnx2x_set_settings,
3475         .get_drvinfo            = bnx2x_get_drvinfo,
3476         .get_regs_len           = bnx2x_get_regs_len,
3477         .get_regs               = bnx2x_get_regs,
3478         .get_dump_flag          = bnx2x_get_dump_flag,
3479         .get_dump_data          = bnx2x_get_dump_data,
3480         .set_dump               = bnx2x_set_dump,
3481         .get_wol                = bnx2x_get_wol,
3482         .set_wol                = bnx2x_set_wol,
3483         .get_msglevel           = bnx2x_get_msglevel,
3484         .set_msglevel           = bnx2x_set_msglevel,
3485         .nway_reset             = bnx2x_nway_reset,
3486         .get_link               = bnx2x_get_link,
3487         .get_eeprom_len         = bnx2x_get_eeprom_len,
3488         .get_eeprom             = bnx2x_get_eeprom,
3489         .set_eeprom             = bnx2x_set_eeprom,
3490         .get_coalesce           = bnx2x_get_coalesce,
3491         .set_coalesce           = bnx2x_set_coalesce,
3492         .get_ringparam          = bnx2x_get_ringparam,
3493         .set_ringparam          = bnx2x_set_ringparam,
3494         .get_pauseparam         = bnx2x_get_pauseparam,
3495         .set_pauseparam         = bnx2x_set_pauseparam,
3496         .self_test              = bnx2x_self_test,
3497         .get_sset_count         = bnx2x_get_sset_count,
3498         .get_priv_flags         = bnx2x_get_private_flags,
3499         .get_strings            = bnx2x_get_strings,
3500         .set_phys_id            = bnx2x_set_phys_id,
3501         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3502         .get_rxnfc              = bnx2x_get_rxnfc,
3503         .set_rxnfc              = bnx2x_set_rxnfc,
3504         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3505         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
3506         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
3507         .get_channels           = bnx2x_get_channels,
3508         .set_channels           = bnx2x_set_channels,
3509         .get_module_info        = bnx2x_get_module_info,
3510         .get_module_eeprom      = bnx2x_get_module_eeprom,
3511         .get_eee                = bnx2x_get_eee,
3512         .set_eee                = bnx2x_set_eee,
3513         .get_ts_info            = ethtool_op_get_ts_info,
3514 };
3515
3516 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3517         .get_settings           = bnx2x_get_settings,
3518         .set_settings           = bnx2x_set_settings,
3519         .get_drvinfo            = bnx2x_get_drvinfo,
3520         .get_msglevel           = bnx2x_get_msglevel,
3521         .set_msglevel           = bnx2x_set_msglevel,
3522         .get_link               = bnx2x_get_link,
3523         .get_coalesce           = bnx2x_get_coalesce,
3524         .get_ringparam          = bnx2x_get_ringparam,
3525         .set_ringparam          = bnx2x_set_ringparam,
3526         .get_sset_count         = bnx2x_get_sset_count,
3527         .get_strings            = bnx2x_get_strings,
3528         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3529         .get_rxnfc              = bnx2x_get_rxnfc,
3530         .set_rxnfc              = bnx2x_set_rxnfc,
3531         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3532         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
3533         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
3534         .get_channels           = bnx2x_get_channels,
3535         .set_channels           = bnx2x_set_channels,
3536 };
3537
3538 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3539 {
3540         if (IS_PF(bp))
3541                 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3542         else /* vf */
3543                 SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops);
3544 }