drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h

   1 /* bnx2x_hsi.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9 #ifndef BNX2X_HSI_H
  10 #define BNX2X_HSI_H
  11
  12 #include "bnx2x_fw_defs.h"
  13
  14 #define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
  15
  16 struct license_key {
  17         u32 reserved[6];
  18
  19         u32 max_iscsi_conn;
  20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK  0xFFFF
  21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
  22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK  0xFFFF0000
  23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
  24
  25         u32 reserved_a;
  26
  27         u32 max_fcoe_conn;
  28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK   0xFFFF
  29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT  0
  30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK   0xFFFF0000
  31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT  16
  32
  33         u32 reserved_b[4];
  34 };
  35
  36
  37 #define PORT_0                  0
  38 #define PORT_1                  1
  39 #define PORT_MAX                2
  40 #define NVM_PATH_MAX            2
  41
  42 /****************************************************************************
  43  * Shared HW configuration                                                  *
  44  ****************************************************************************/
  45 #define PIN_CFG_NA                          0x00000000
  46 #define PIN_CFG_GPIO0_P0                    0x00000001
  47 #define PIN_CFG_GPIO1_P0                    0x00000002
  48 #define PIN_CFG_GPIO2_P0                    0x00000003
  49 #define PIN_CFG_GPIO3_P0                    0x00000004
  50 #define PIN_CFG_GPIO0_P1                    0x00000005
  51 #define PIN_CFG_GPIO1_P1                    0x00000006
  52 #define PIN_CFG_GPIO2_P1                    0x00000007
  53 #define PIN_CFG_GPIO3_P1                    0x00000008
  54 #define PIN_CFG_EPIO0                       0x00000009
  55 #define PIN_CFG_EPIO1                       0x0000000a
  56 #define PIN_CFG_EPIO2                       0x0000000b
  57 #define PIN_CFG_EPIO3                       0x0000000c
  58 #define PIN_CFG_EPIO4                       0x0000000d
  59 #define PIN_CFG_EPIO5                       0x0000000e
  60 #define PIN_CFG_EPIO6                       0x0000000f
  61 #define PIN_CFG_EPIO7                       0x00000010
  62 #define PIN_CFG_EPIO8                       0x00000011
  63 #define PIN_CFG_EPIO9                       0x00000012
  64 #define PIN_CFG_EPIO10                      0x00000013
  65 #define PIN_CFG_EPIO11                      0x00000014
  66 #define PIN_CFG_EPIO12                      0x00000015
  67 #define PIN_CFG_EPIO13                      0x00000016
  68 #define PIN_CFG_EPIO14                      0x00000017
  69 #define PIN_CFG_EPIO15                      0x00000018
  70 #define PIN_CFG_EPIO16                      0x00000019
  71 #define PIN_CFG_EPIO17                      0x0000001a
  72 #define PIN_CFG_EPIO18                      0x0000001b
  73 #define PIN_CFG_EPIO19                      0x0000001c
  74 #define PIN_CFG_EPIO20                      0x0000001d
  75 #define PIN_CFG_EPIO21                      0x0000001e
  76 #define PIN_CFG_EPIO22                      0x0000001f
  77 #define PIN_CFG_EPIO23                      0x00000020
  78 #define PIN_CFG_EPIO24                      0x00000021
  79 #define PIN_CFG_EPIO25                      0x00000022
  80 #define PIN_CFG_EPIO26                      0x00000023
  81 #define PIN_CFG_EPIO27                      0x00000024
  82 #define PIN_CFG_EPIO28                      0x00000025
  83 #define PIN_CFG_EPIO29                      0x00000026
  84 #define PIN_CFG_EPIO30                      0x00000027
  85 #define PIN_CFG_EPIO31                      0x00000028
  86
  87 /* EPIO definition */
  88 #define EPIO_CFG_NA                         0x00000000
  89 #define EPIO_CFG_EPIO0                      0x00000001
  90 #define EPIO_CFG_EPIO1                      0x00000002
  91 #define EPIO_CFG_EPIO2                      0x00000003
  92 #define EPIO_CFG_EPIO3                      0x00000004
  93 #define EPIO_CFG_EPIO4                      0x00000005
  94 #define EPIO_CFG_EPIO5                      0x00000006
  95 #define EPIO_CFG_EPIO6                      0x00000007
  96 #define EPIO_CFG_EPIO7                      0x00000008
  97 #define EPIO_CFG_EPIO8                      0x00000009
  98 #define EPIO_CFG_EPIO9                      0x0000000a
  99 #define EPIO_CFG_EPIO10                     0x0000000b
 100 #define EPIO_CFG_EPIO11                     0x0000000c
 101 #define EPIO_CFG_EPIO12                     0x0000000d
 102 #define EPIO_CFG_EPIO13                     0x0000000e
 103 #define EPIO_CFG_EPIO14                     0x0000000f
 104 #define EPIO_CFG_EPIO15                     0x00000010
 105 #define EPIO_CFG_EPIO16                     0x00000011
 106 #define EPIO_CFG_EPIO17                     0x00000012
 107 #define EPIO_CFG_EPIO18                     0x00000013
 108 #define EPIO_CFG_EPIO19                     0x00000014
 109 #define EPIO_CFG_EPIO20                     0x00000015
 110 #define EPIO_CFG_EPIO21                     0x00000016
 111 #define EPIO_CFG_EPIO22                     0x00000017
 112 #define EPIO_CFG_EPIO23                     0x00000018
 113 #define EPIO_CFG_EPIO24                     0x00000019
 114 #define EPIO_CFG_EPIO25                     0x0000001a
 115 #define EPIO_CFG_EPIO26                     0x0000001b
 116 #define EPIO_CFG_EPIO27                     0x0000001c
 117 #define EPIO_CFG_EPIO28                     0x0000001d
 118 #define EPIO_CFG_EPIO29                     0x0000001e
 119 #define EPIO_CFG_EPIO30                     0x0000001f
 120 #define EPIO_CFG_EPIO31                     0x00000020
 121
 122
 123 struct shared_hw_cfg {                   /* NVRAM Offset */
 124         /* Up to 16 bytes of NULL-terminated string */
 125         u8  part_num[16];                   /* 0x104 */
 126
 127         u32 config;                     /* 0x114 */
 128         #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
 129                 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
 130                 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
 131                 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
 132         #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
 133
 134         #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
 135
 136         #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
 137
 138         #define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
 139         #define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
 140
 141         #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
 142                 #define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
 143         /* Whatever MFW found in NVM
 144            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
 145                 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
 146                 #define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
 147                 #define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
 148                 #define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
 149         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
 150           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 151                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
 152         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
 153           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 154                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
 155         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
 156           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 157                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
 158
 159         #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
 160                 #define SHARED_HW_CFG_LED_MODE_SHIFT                 16
 161                 #define SHARED_HW_CFG_LED_MAC1                       0x00000000
 162                 #define SHARED_HW_CFG_LED_PHY1                       0x00010000
 163                 #define SHARED_HW_CFG_LED_PHY2                       0x00020000
 164                 #define SHARED_HW_CFG_LED_PHY3                       0x00030000
 165                 #define SHARED_HW_CFG_LED_MAC2                       0x00040000
 166                 #define SHARED_HW_CFG_LED_PHY4                       0x00050000
 167                 #define SHARED_HW_CFG_LED_PHY5                       0x00060000
 168                 #define SHARED_HW_CFG_LED_PHY6                       0x00070000
 169                 #define SHARED_HW_CFG_LED_MAC3                       0x00080000
 170                 #define SHARED_HW_CFG_LED_PHY7                       0x00090000
 171                 #define SHARED_HW_CFG_LED_PHY9                       0x000a0000
 172                 #define SHARED_HW_CFG_LED_PHY11                      0x000b0000
 173                 #define SHARED_HW_CFG_LED_MAC4                       0x000c0000
 174                 #define SHARED_HW_CFG_LED_PHY8                       0x000d0000
 175                 #define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
 176
 177
 178         #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
 179                 #define SHARED_HW_CFG_AN_ENABLE_SHIFT                24
 180                 #define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000
 181                 #define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000
 182                 #define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000
 183                 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000
 184                 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000
 185                 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000
 186
 187         #define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
 188                 #define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
 189                 #define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
 190
 191         #define SHARED_HW_CFG_ATC_MASK                      0x80000000
 192                 #define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
 193                 #define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
 194
 195         u32 config2;                        /* 0x118 */
 196         /* one time auto detect grace period (in sec) */
 197         #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
 198         #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
 199
 200         #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
 201         #define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000
 202
 203         /* The default value for the core clock is 250MHz and it is
 204            achieved by setting the clock change to 4 */
 205         #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
 206         #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9
 207
 208         #define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
 209                 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
 210                 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
 211
 212         #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
 213
 214         #define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000
 215                 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000
 216                 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000
 217
 218                 /* Output low when PERST is asserted */
 219         #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
 220                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
 221                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
 222
 223         #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
 224                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
 225                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
 226                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
 227                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
 228                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
 229
 230         /*  The fan failure mechanism is usually related to the PHY type
 231               since the power consumption of the board is determined by the PHY.
 232               Currently, fan is required for most designs with SFX7101, BCM8727
 233               and BCM8481. If a fan is not required for a board which uses one
 234               of those PHYs, this field should be set to "Disabled". If a fan is
 235               required for a different PHY type, this option should be set to
 236               "Enabled". The fan failure indication is expected on SPIO5 */
 237         #define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
 238                 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
 239                 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
 240                 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
 241                 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
 242
 243                 /* ASPM Power Management support */
 244         #define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
 245                 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
 246                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
 247                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
 248                 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
 249                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
 250
 251         /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
 252            tl_control_0 (register 0x2800) */
 253         #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
 254                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
 255                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
 256
 257         #define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000
 258                 #define SHARED_HW_CFG_PORT_MODE_2                    0x00000000
 259                 #define SHARED_HW_CFG_PORT_MODE_4                    0x01000000
 260
 261         #define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000
 262                 #define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000
 263                 #define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000
 264
 265         /*  Set the MDC/MDIO access for the first external phy */
 266         #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
 267                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
 268                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
 269                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
 270                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
 271                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
 272                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
 273
 274         /*  Set the MDC/MDIO access for the second external phy */
 275         #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
 276                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
 277                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
 278                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
 279                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
 280                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
 281                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
 282
 283
 284         u32 power_dissipated;                   /* 0x11c */
 285         #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
 286                 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT         16
 287                 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE       0x00000000
 288                 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT          0x00010000
 289                 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT         0x00020000
 290                 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT        0x00030000
 291
 292         #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
 293         #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT                    24
 294
 295         u32 ump_nc_si_config;                   /* 0x120 */
 296         #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
 297                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
 298                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
 299                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
 300                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
 301                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
 302
 303         #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
 304                 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8
 305
 306         #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
 307                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16
 308                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
 309                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
 310
 311         u32 board;                      /* 0x124 */
 312         #define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
 313         #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
 314         #define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
 315         #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
 316         /* Use the PIN_CFG_XXX defines on top */
 317         #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
 318         #define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
 319
 320         #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000
 321         #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
 322
 323         #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
 324         #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
 325
 326         u32 wc_lane_config;                                 /* 0x128 */
 327         #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
 328                 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
 329                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
 330                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
 331                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
 332                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
 333         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
 334         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
 335         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
 336         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
 337
 338         /* TX lane Polarity swap */
 339         #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
 340         #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
 341         #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
 342         #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
 343         /* TX lane Polarity swap */
 344         #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
 345         #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
 346         #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
 347         #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
 348
 349         /*  Selects the port layout of the board */
 350         #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
 351                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
 352                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
 353                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
 354                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
 355                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
 356                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
 357                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
 358 };
 359
 360
 361 /****************************************************************************
 362  * Port HW configuration                                                    *
 363  ****************************************************************************/
 364 struct port_hw_cfg {                /* port 0: 0x12c  port 1: 0x2bc */
 365
 366         u32 pci_id;
 367         #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
 368         #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
 369
 370         u32 pci_sub_id;
 371         #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
 372         #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
 373
 374         u32 power_dissipated;
 375         #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
 376         #define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
 377         #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
 378         #define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
 379         #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
 380         #define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
 381         #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
 382         #define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
 383
 384         u32 power_consumed;
 385         #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
 386         #define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
 387         #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
 388         #define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
 389         #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
 390         #define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
 391         #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
 392         #define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
 393
 394         u32 mac_upper;
 395         #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
 396         #define PORT_HW_CFG_UPPERMAC_SHIFT                           0
 397         u32 mac_lower;
 398
 399         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
 400         u32 iscsi_mac_lower;
 401
 402         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
 403         u32 rdma_mac_lower;
 404
 405         u32 serdes_config;
 406         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
 407         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
 408
 409         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
 410         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
 411
 412
 413         /*  Default values: 2P-64, 4P-32 */
 414         u32 pf_config;                                      /* 0x158 */
 415         #define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
 416         #define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
 417
 418         /*  Default values: 17 */
 419         #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00
 420         #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8
 421
 422         #define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
 423         #define PORT_HW_CFG_FLR_ENABLED                     0x00010000
 424
 425         u32 vf_config;                                      /* 0x15C */
 426         #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
 427         #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
 428
 429         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
 430         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
 431
 432         u32 mf_pci_id;                                      /* 0x160 */
 433         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
 434         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
 435
 436         /*  Controls the TX laser of the SFP+ module */
 437         u32 sfp_ctrl;                                       /* 0x164 */
 438         #define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
 439                 #define PORT_HW_CFG_TX_LASER_SHIFT                   0
 440                 #define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
 441                 #define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
 442                 #define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
 443                 #define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
 444                 #define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
 445
 446         /*  Controls the fault module LED of the SFP+ */
 447         #define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
 448                 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
 449                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
 450                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
 451                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
 452                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
 453                 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
 454
 455         /*  The output pin TX_DIS that controls the TX laser of the SFP+
 456           module. Use the PIN_CFG_XXX defines on top */
 457         u32 e3_sfp_ctrl;                                    /* 0x168 */
 458         #define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
 459         #define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
 460
 461         /*  The output pin for SFPP_TYPE which turns on the Fault module LED */
 462         #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
 463         #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
 464
 465         /*  The input pin MOD_ABS that indicates whether SFP+ module is
 466           present or not. Use the PIN_CFG_XXX defines on top */
 467         #define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
 468         #define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
 469
 470         /*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
 471           module. Use the PIN_CFG_XXX defines on top */
 472         #define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
 473         #define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
 474
 475         /*
 476          * The input pin which signals module transmit fault. Use the
 477          * PIN_CFG_XXX defines on top
 478          */
 479         u32 e3_cmn_pin_cfg;                                 /* 0x16C */
 480         #define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
 481         #define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
 482
 483         /*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
 484          top */
 485         #define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
 486         #define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
 487
 488         /*
 489          * The output pin which powers down the PHY. Use the PIN_CFG_XXX
 490          * defines on top
 491          */
 492         #define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
 493         #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
 494
 495         /*  The output pin values BSC_SEL which selects the I2C for this port
 496           in the I2C Mux */
 497         #define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
 498         #define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
 499
 500
 501         /*
 502          * The input pin I_FAULT which indicate over-current has occurred.
 503          * Use the PIN_CFG_XXX defines on top
 504          */
 505         u32 e3_cmn_pin_cfg1;                                /* 0x170 */
 506         #define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
 507         #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
 508         u32 reserved0[7];                                   /* 0x174 */
 509
 510         u32 aeu_int_mask;                                   /* 0x190 */
 511
 512         u32 media_type;                                     /* 0x194 */
 513         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
 514         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
 515
 516         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
 517         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
 518
 519         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
 520         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
 521
 522         /*  4 times 16 bits for all 4 lanes. In case external PHY is present
 523               (not direct mode), those values will not take effect on the 4 XGXS
 524               lanes. For some external PHYs (such as 8706 and 8726) the values
 525               will be used to configure the external PHY  in those cases, not
 526               all 4 values are needed. */
 527         u16 xgxs_config_rx[4];                  /* 0x198 */
 528         u16 xgxs_config_tx[4];                  /* 0x1A0 */
 529
 530         /* For storing FCOE mac on shared memory */
 531         u32 fcoe_fip_mac_upper;
 532         #define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
 533         #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
 534         u32 fcoe_fip_mac_lower;
 535
 536         u32 fcoe_wwn_port_name_upper;
 537         u32 fcoe_wwn_port_name_lower;
 538
 539         u32 fcoe_wwn_node_name_upper;
 540         u32 fcoe_wwn_node_name_lower;
 541
 542         u32 Reserved1[49];                                  /* 0x1C0 */
 543
 544         /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
 545               84833 only */
 546         u32 xgbt_phy_cfg;                                   /* 0x284 */
 547         #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
 548         #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
 549
 550                 u32 default_cfg;                            /* 0x288 */
 551         #define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
 552                 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
 553                 #define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
 554                 #define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
 555                 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
 556                 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
 557
 558         #define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
 559                 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
 560                 #define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
 561                 #define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
 562                 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
 563                 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
 564
 565         #define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
 566                 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
 567                 #define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
 568                 #define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
 569                 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
 570                 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
 571
 572         #define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
 573                 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
 574                 #define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
 575                 #define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
 576                 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
 577                 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
 578
 579         /*  When KR link is required to be set to force which is not
 580               KR-compliant, this parameter determine what is the trigger for it.
 581               When GPIO is selected, low input will force the speed. Currently
 582               default speed is 1G. In the future, it may be widen to select the
 583               forced speed in with another parameter. Note when force-1G is
 584               enabled, it override option 56: Link Speed option. */
 585         #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
 586                 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
 587                 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
 588                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
 589                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
 590                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
 591                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
 592                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
 593                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
 594                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
 595                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
 596                 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
 597         /*  Enable to determine with which GPIO to reset the external phy */
 598         #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
 599                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
 600                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
 601                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
 602                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
 603                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
 604                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
 605                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
 606                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
 607                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
 608                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
 609
 610         /*  Enable BAM on KR */
 611         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
 612         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
 613         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
 614         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
 615
 616         /*  Enable Common Mode Sense */
 617         #define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
 618         #define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
 619         #define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
 620         #define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
 621
 622         /*  Determine the Serdes electrical interface   */
 623         #define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
 624         #define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
 625         #define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
 626         #define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
 627         #define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
 628         #define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
 629         #define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
 630         #define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
 631
 632
 633         u32 speed_capability_mask2;                         /* 0x28C */
 634         #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
 635                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
 636                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
 637                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002
 638                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004
 639                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
 640                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
 641                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020
 642                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
 643                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
 644
 645         #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
 646                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
 647                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
 648                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000
 649                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000
 650                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
 651                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
 652                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000
 653                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
 654                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
 655
 656
 657         /*  In the case where two media types (e.g. copper and fiber) are
 658               present and electrically active at the same time, PHY Selection
 659               will determine which of the two PHYs will be designated as the
 660               Active PHY and used for a connection to the network.  */
 661         u32 multi_phy_config;                               /* 0x290 */
 662         #define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
 663                 #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
 664                 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
 665                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
 666                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
 667                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
 668                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
 669
 670         /*  When enabled, all second phy nvram parameters will be swapped
 671               with the first phy parameters */
 672         #define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
 673                 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
 674                 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
 675                 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
 676
 677
 678         /*  Address of the second external phy */
 679         u32 external_phy_config2;                           /* 0x294 */
 680         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
 681         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
 682
 683         /*  The second XGXS external PHY type */
 684         #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
 685                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
 686                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
 687                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
 688                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
 689                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
 690                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
 691                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
 692                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
 693                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
 694                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
 695                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
 696                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
 697                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
 698                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
 699                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
 700                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
 701                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
 702                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
 703                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
 704                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
 705
 706
 707         /*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
 708               8706, 8726 and 8727) not all 4 values are needed. */
 709         u16 xgxs_config2_rx[4];                             /* 0x296 */
 710         u16 xgxs_config2_tx[4];                             /* 0x2A0 */
 711
 712         u32 lane_config;
 713         #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
 714                 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
 715                 /* AN and forced */
 716                 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
 717                 /* forced only */
 718                 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
 719                 /* forced only */
 720                 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
 721                 /* forced only */
 722                 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
 723         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
 724         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
 725         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
 726         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
 727         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
 728         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
 729
 730         /*  Indicate whether to swap the external phy polarity */
 731         #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
 732                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
 733                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
 734
 735
 736         u32 external_phy_config;
 737         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
 738         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
 739
 740         #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
 741                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
 742                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
 743                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
 744                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
 745                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
 746                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
 747                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
 748                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
 749                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
 750                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
 751                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
 752                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
 753                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
 754                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
 755                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
 756                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
 757                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
 758                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
 759                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
 760                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
 761                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
 762
 763         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
 764         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
 765
 766         #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
 767                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
 768                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
 769                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
 770                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
 771                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
 772
 773         u32 speed_capability_mask;
 774         #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
 775                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
 776                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
 777                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
 778                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
 779                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
 780                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
 781                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
 782                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
 783                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
 784                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
 785
 786         #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
 787                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
 788                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
 789                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
 790                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
 791                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
 792                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
 793                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
 794                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
 795                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
 796                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
 797
 798         /*  A place to hold the original MAC address as a backup */
 799         u32 backup_mac_upper;                   /* 0x2B4 */
 800         u32 backup_mac_lower;                   /* 0x2B8 */
 801
 802 };
 803
 804
 805 /****************************************************************************
 806  * Shared Feature configuration                                             *
 807  ****************************************************************************/
 808 struct shared_feat_cfg {                 /* NVRAM Offset */
 809
 810         u32 config;                     /* 0x450 */
 811         #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
 812
 813         /* Use NVRAM values instead of HW default values */
 814         #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
 815                                                             0x00000002
 816                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
 817                                                                      0x00000000
 818                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
 819                                                                      0x00000002
 820
 821         #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
 822                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
 823                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
 824
 825         #define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
 826         #define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
 827
 828         /*  Override the OTP back to single function mode. When using GPIO,
 829               high means only SF, 0 is according to CLP configuration */
 830         #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
 831                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
 832                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
 833                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
 834                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
 835                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
 836                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
 837
 838         /* The interval in seconds between sending LLDP packets. Set to zero
 839            to disable the feature */
 840         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000
 841         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
 842
 843         /* The assigned device type ID for LLDP usage */
 844         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000
 845         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
 846
 847 };
 848
 849
 850 /****************************************************************************
 851  * Port Feature configuration                                               *
 852  ****************************************************************************/
 853 struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
 854
 855         u32 config;
 856         #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
 857                 #define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
 858                 #define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
 859                 #define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001
 860                 #define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002
 861                 #define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003
 862                 #define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004
 863                 #define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005
 864                 #define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006
 865                 #define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007
 866                 #define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008
 867                 #define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009
 868                 #define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a
 869                 #define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b
 870                 #define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c
 871                 #define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d
 872                 #define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e
 873                 #define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f
 874         #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
 875                 #define PORT_FEATURE_BAR2_SIZE_SHIFT                 4
 876                 #define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000
 877                 #define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010
 878                 #define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020
 879                 #define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030
 880                 #define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040
 881                 #define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050
 882                 #define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060
 883                 #define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070
 884                 #define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080
 885                 #define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090
 886                 #define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0
 887                 #define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0
 888                 #define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0
 889                 #define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0
 890                 #define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0
 891                 #define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0
 892
 893         #define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
 894                 #define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
 895                 #define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
 896
 897         #define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
 898         #define PORT_FEATURE_EN_SIZE_SHIFT                           24
 899         #define PORT_FEATURE_WOL_ENABLED                             0x01000000
 900         #define PORT_FEATURE_MBA_ENABLED                             0x02000000
 901         #define PORT_FEATURE_MFW_ENABLED                             0x04000000
 902
 903         /* Advertise expansion ROM even if MBA is disabled */
 904         #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
 905                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
 906                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
 907
 908         /* Check the optic vendor via i2c against a list of approved modules
 909            in a separate nvram image */
 910         #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000
 911                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
 912                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
 913                                                                      0x00000000
 914                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
 915                                                                      0x20000000
 916                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
 917                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
 918
 919         u32 wol_config;
 920         /* Default is used when driver sets to "auto" mode */
 921         #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
 922                 #define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
 923                 #define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000
 924                 #define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001
 925                 #define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002
 926                 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003
 927         #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
 928         #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
 929         #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
 930
 931         u32 mba_config;
 932         #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
 933                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
 934                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
 935                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
 936                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
 937                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
 938                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
 939                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
 940
 941         #define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
 942         #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
 943
 944         #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
 945         #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
 946         #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
 947         #define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
 948                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
 949                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
 950         #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
 951                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
 952                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
 953                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
 954                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
 955                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
 956                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
 957                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
 958                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
 959                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
 960                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
 961                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
 962                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
 963                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
 964                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
 965                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
 966                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
 967                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
 968         #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
 969         #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
 970         #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
 971                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
 972                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
 973                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
 974                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
 975                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
 976         #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
 977                 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
 978                 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
 979                 #define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x04000000
 980                 #define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x08000000
 981                 #define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c000000
 982                 #define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x10000000
 983                 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x14000000
 984                 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
 985                 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
 986                 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
 987         u32 bmc_config;
 988         #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
 989                 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
 990                 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
 991
 992         u32 mba_vlan_cfg;
 993         #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
 994         #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
 995         #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
 996
 997         u32 resource_cfg;
 998         #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
 999         #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
1000         #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
1001         #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
1002         #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
1003
1004         u32 smbus_config;
1005         #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1006         #define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1007
1008         u32 vf_config;
1009         #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
1010                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1011                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1012                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1013                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1014                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1015                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1016                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1017                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1018                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1019                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1020                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1021                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1022                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1023                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1024                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1025                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1026                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1027
1028         u32 link_config;    /* Used as HW defaults for the driver */
1029         #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1030                 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1031                 /* (forced) low speed switch (< 10G) */
1032                 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1033                 /* (forced) high speed switch (>= 10G) */
1034                 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1035                 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1036                 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1037
1038         #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
1039                 #define PORT_FEATURE_LINK_SPEED_SHIFT                16
1040                 #define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1041                 #define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
1042                 #define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
1043                 #define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1044                 #define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1045                 #define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1046                 #define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1047                 #define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1048                 #define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1049
1050         #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1051                 #define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1052                 #define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1053                 #define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1054                 #define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1055                 #define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1056                 #define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1057
1058         /* The default for MCP link configuration,
1059            uses the same defines as link_config */
1060         u32 mfw_wol_link_cfg;
1061
1062         /* The default for the driver of the second external phy,
1063            uses the same defines as link_config */
1064         u32 link_config2;                                   /* 0x47C */
1065
1066         /* The default for MCP of the second external phy,
1067            uses the same defines as link_config */
1068         u32 mfw_wol_link_cfg2;                              /* 0x480 */
1069
1070
1071         /*  EEE power saving mode */
1072         u32 eee_power_mode;                                 /* 0x484 */
1073         #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
1074         #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
1075         #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
1076         #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
1077         #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
1078         #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
1079
1080
1081         u32 Reserved2[16];                                  /* 0x488 */
1082 };
1083
1084
1085 /****************************************************************************
1086  * Device Information                                                       *
1087  ****************************************************************************/
1088 struct shm_dev_info {                           /* size */
1089
1090         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
1091
1092         struct shared_hw_cfg     shared_hw_config;            /* 40 */
1093
1094         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1095
1096         struct shared_feat_cfg   shared_feature_config;            /* 4 */
1097
1098         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1099
1100 };
1101
1102
1103 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1104         #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1105 #endif
1106
1107 #define FUNC_0              0
1108 #define FUNC_1              1
1109 #define FUNC_2              2
1110 #define FUNC_3              3
1111 #define FUNC_4              4
1112 #define FUNC_5              5
1113 #define FUNC_6              6
1114 #define FUNC_7              7
1115 #define E1_FUNC_MAX         2
1116 #define E1H_FUNC_MAX            8
1117 #define E2_FUNC_MAX         4   /* per path */
1118
1119 #define VN_0                0
1120 #define VN_1                1
1121 #define VN_2                2
1122 #define VN_3                3
1123 #define E1VN_MAX            1
1124 #define E1HVN_MAX           4
1125
1126 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1127 /* This value (in milliseconds) determines the frequency of the driver
1128  * issuing the PULSE message code.  The firmware monitors this periodic
1129  * pulse to determine when to switch to an OS-absent mode. */
1130 #define DRV_PULSE_PERIOD_MS     250
1131
1132 /* This value (in milliseconds) determines how long the driver should
1133  * wait for an acknowledgement from the firmware before timing out.  Once
1134  * the firmware has timed out, the driver will assume there is no firmware
1135  * running and there won't be any firmware-driver synchronization during a
1136  * driver reset. */
1137 #define FW_ACK_TIME_OUT_MS      5000
1138
1139 #define FW_ACK_POLL_TIME_MS     1
1140
1141 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1142
1143 #define MFW_TRACE_SIGNATURE     0x54524342
1144
1145 /****************************************************************************
1146  * Driver <-> FW Mailbox                                                    *
1147  ****************************************************************************/
1148 struct drv_port_mb {
1149
1150         u32 link_status;
1151         /* Driver should update this field on any link change event */
1152
1153         #define LINK_STATUS_NONE                                (0<<0)
1154         #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
1155         #define LINK_STATUS_LINK_UP                             0x00000001
1156         #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
1157         #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
1158         #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
1159         #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
1160         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
1161         #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
1162         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
1163         #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
1164         #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
1165         #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
1166         #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
1167         #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
1168         #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
1169         #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
1170         #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
1171         #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD             (11<<1)
1172         #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD             (11<<1)
1173
1174         #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
1175         #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
1176
1177         #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
1178         #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
1179         #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
1180
1181         #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
1182         #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
1183         #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
1184         #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
1185         #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
1186         #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
1187         #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
1188
1189         #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
1190         #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
1191
1192         #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
1193         #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
1194
1195         #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
1196         #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
1197         #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
1198         #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
1199         #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
1200
1201         #define LINK_STATUS_SERDES_LINK                         0x00100000
1202
1203         #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
1204         #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
1205         #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
1206         #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE         0x10000000
1207
1208         #define LINK_STATUS_PFC_ENABLED                         0x20000000
1209
1210         #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
1211         #define LINK_STATUS_SFP_TX_FAULT                        0x80000000
1212
1213         u32 port_stx;
1214
1215         u32 stat_nig_timer;
1216
1217         /* MCP firmware does not use this field */
1218         u32 ext_phy_fw_version;
1219
1220 };
1221
1222
1223 struct drv_func_mb {
1224
1225         u32 drv_mb_header;
1226         #define DRV_MSG_CODE_MASK                       0xffff0000
1227         #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1228         #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1229         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1230         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1231         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1232         #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1233         #define DRV_MSG_CODE_DCC_OK                     0x30000000
1234         #define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1235         #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1236         #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1237         #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1238         #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1239         #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1240         #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1241         #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1242         /*
1243          * The optic module verification command requires bootcode
1244          * v5.0.6 or later, te specific optic module verification command
1245          * requires bootcode v5.2.12 or later
1246          */
1247         #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1248         #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1249         #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1250         #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1251         #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
1252         #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
1253         #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1254         #define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
1255
1256         #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1257         #define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1258         #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
1259
1260         #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1261
1262         #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
1263         #define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
1264         #define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
1265         #define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
1266         #define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
1267
1268         #define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
1269         #define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
1270
1271         #define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
1272
1273         #define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1274         #define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1275         #define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1276
1277         #define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1278
1279         #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
1280         #define REQ_BC_VER_4_INITIATE_FLR               0x00070213
1281
1282         #define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1283         #define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1284         #define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1285         #define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1286
1287         #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1288
1289         u32 drv_mb_param;
1290         #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1291         #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1292
1293         u32 fw_mb_header;
1294         #define FW_MSG_CODE_MASK                        0xffff0000
1295         #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1296         #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1297         #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1298         /* Load common chip is supported from bc 6.0.0  */
1299         #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1300         #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1301
1302         #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1303         #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1304         #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1305         #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1306         #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1307         #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1308         #define FW_MSG_CODE_DCC_DONE                    0x30100000
1309         #define FW_MSG_CODE_LLDP_DONE                   0x40100000
1310         #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1311         #define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1312         #define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1313         #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1314         #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1315         #define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1316         #define FW_MSG_CODE_NO_KEY                      0x80f00000
1317         #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1318         #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1319         #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1320         #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1321         #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1322         #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1323         #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1324         #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1325         #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1326         #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1327         #define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
1328
1329         #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
1330         #define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
1331         #define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
1332         #define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
1333         #define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
1334
1335         #define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
1336         #define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
1337
1338         #define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
1339
1340         #define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1341         #define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1342
1343         #define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1344
1345         #define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1346         #define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1347         #define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1348         #define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1349
1350         #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1351
1352         u32 fw_mb_param;
1353
1354         u32 drv_pulse_mb;
1355         #define DRV_PULSE_SEQ_MASK                      0x00007fff
1356         #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1357         /*
1358          * The system time is in the format of
1359          * (year-2001)*12*32 + month*32 + day.
1360          */
1361         #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1362         /*
1363          * Indicate to the firmware not to go into the
1364          * OS-absent when it is not getting driver pulse.
1365          * This is used for debugging as well for PXE(MBA).
1366          */
1367
1368         u32 mcp_pulse_mb;
1369         #define MCP_PULSE_SEQ_MASK                      0x00007fff
1370         #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1371         /* Indicates to the driver not to assert due to lack
1372          * of MCP response */
1373         #define MCP_EVENT_MASK                          0xffff0000
1374         #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1375
1376         u32 iscsi_boot_signature;
1377         u32 iscsi_boot_block_offset;
1378
1379         u32 drv_status;
1380         #define DRV_STATUS_PMF                          0x00000001
1381         #define DRV_STATUS_VF_DISABLED                  0x00000002
1382         #define DRV_STATUS_SET_MF_BW                    0x00000004
1383         #define DRV_STATUS_LINK_EVENT                   0x00000008
1384
1385         #define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1386         #define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1387         #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1388         #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1389         #define DRV_STATUS_DCC_RESERVED1                0x00000800
1390         #define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1391         #define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1392
1393         #define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1394         #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1395         #define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
1396         #define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
1397         #define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
1398         #define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
1399         #define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
1400
1401         #define DRV_STATUS_DRV_INFO_REQ                 0x04000000
1402
1403         #define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
1404
1405         u32 virt_mac_upper;
1406         #define VIRT_MAC_SIGN_MASK                      0xffff0000
1407         #define VIRT_MAC_SIGNATURE                      0x564d0000
1408         u32 virt_mac_lower;
1409
1410 };
1411
1412
1413 /****************************************************************************
1414  * Management firmware state                                                *
1415  ****************************************************************************/
1416 /* Allocate 440 bytes for management firmware */
1417 #define MGMTFW_STATE_WORD_SIZE                          110
1418
1419 struct mgmtfw_state {
1420         u32 opaque[MGMTFW_STATE_WORD_SIZE];
1421 };
1422
1423
1424 /****************************************************************************
1425  * Multi-Function configuration                                             *
1426  ****************************************************************************/
1427 struct shared_mf_cfg {
1428
1429         u32 clp_mb;
1430         #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1431         /* set by CLP */
1432         #define SHARED_MF_CLP_EXIT                      0x00000001
1433         /* set by MCP */
1434         #define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1435
1436 };
1437
1438 struct port_mf_cfg {
1439
1440         u32 dynamic_cfg;    /* device control channel */
1441         #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1442         #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1443         #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1444
1445         u32 reserved[1];
1446
1447 };
1448
1449 struct func_mf_cfg {
1450
1451         u32 config;
1452         /* E/R/I/D */
1453         /* function 0 of each port cannot be hidden */
1454         #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1455
1456         #define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1457         #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1458         #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1459         #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1460         #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1461         #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1462                                 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1463
1464         #define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1465         #define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1466
1467         /* PRI */
1468         /* 0 - low priority, 3 - high priority */
1469         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1470         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1471         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1472
1473         /* MINBW, MAXBW */
1474         /* value range - 0..100, increments in 100Mbps */
1475         #define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1476         #define FUNC_MF_CFG_MIN_BW_SHIFT                16
1477         #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1478         #define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1479         #define FUNC_MF_CFG_MAX_BW_SHIFT                24
1480         #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1481
1482         u32 mac_upper;      /* MAC */
1483         #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1484         #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1485         #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1486         u32 mac_lower;
1487         #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1488
1489         u32 e1hov_tag;  /* VNI */
1490         #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1491         #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1492         #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1493
1494         /* afex default VLAN ID - 12 bits */
1495         #define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
1496         #define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
1497
1498         u32 afex_config;
1499         #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
1500         #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
1501         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
1502         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
1503         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
1504         #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
1505         #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
1506
1507         u32 reserved;
1508 };
1509
1510 enum mf_cfg_afex_vlan_mode {
1511         FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1512         FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1513         FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1514 };
1515
1516 /* This structure is not applicable and should not be accessed on 57711 */
1517 struct func_ext_cfg {
1518         u32 func_cfg;
1519         #define MACP_FUNC_CFG_FLAGS_MASK                0x000000FF
1520         #define MACP_FUNC_CFG_FLAGS_SHIFT               0
1521         #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1522         #define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1523         #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1524         #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1525
1526         u32 iscsi_mac_addr_upper;
1527         u32 iscsi_mac_addr_lower;
1528
1529         u32 fcoe_mac_addr_upper;
1530         u32 fcoe_mac_addr_lower;
1531
1532         u32 fcoe_wwn_port_name_upper;
1533         u32 fcoe_wwn_port_name_lower;
1534
1535         u32 fcoe_wwn_node_name_upper;
1536         u32 fcoe_wwn_node_name_lower;
1537
1538         u32 preserve_data;
1539         #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1540         #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1541         #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1542         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1543         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1544         #define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1545 };
1546
1547 struct mf_cfg {
1548
1549         struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1550                                                         /* 0x8*2*2=0x20 */
1551         struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
1552         /* for all chips, there are 8 mf functions */
1553         struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1554         /*
1555          * Extended configuration per function  - this array does not exist and
1556          * should not be accessed on 57711
1557          */
1558         struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1559 }; /* 0x224 */
1560
1561 /****************************************************************************
1562  * Shared Memory Region                                                     *
1563  ****************************************************************************/
1564 struct shmem_region {                  /*   SharedMem Offset (size) */
1565
1566         u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1567         #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1568         #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1569         /* validity bits */
1570         #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1571         #define SHR_MEM_VALIDITY_MB                         0x00200000
1572         #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1573         #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1574         /* One licensing bit should be set */
1575         #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1576         #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1577         #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1578         #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1579         /* Active MFW */
1580         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1581         #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1582         #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1583         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1584         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1585         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1586
1587         struct shm_dev_info dev_info;        /* 0x8     (0x438) */
1588
1589         struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1590
1591         /* FW information (for internal FW use) */
1592         u32         fw_info_fio_offset;         /* 0x4a8       (0x4) */
1593         struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */
1594
1595         struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */
1596
1597 #ifdef BMAPI
1598         /* This is a variable length array */
1599         /* the number of function depends on the chip type */
1600         struct drv_func_mb func_mb[1];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1601 #else
1602         /* the number of function depends on the chip type */
1603         struct drv_func_mb  func_mb[];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1604 #endif /* BMAPI */
1605
1606 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1607
1608 /****************************************************************************
1609  * Shared Memory 2 Region                                                   *
1610  ****************************************************************************/
1611 /* The fw_flr_ack is actually built in the following way:                   */
1612 /* 8 bit:  PF ack                                                           */
1613 /* 64 bit: VF ack                                                           */
1614 /* 8 bit:  ios_dis_ack                                                      */
1615 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1616 /* u32. The fw must have the VF right after the PF since this is how it     */
1617 /* access arrays(it expects always the VF to reside after the PF, and that  */
1618 /* makes the calculation much easier for it. )                              */
1619 /* In order to answer both limitations, and keep the struct small, the code */
1620 /* will abuse the structure defined here to achieve the actual partition    */
1621 /* above                                                                    */
1622 /****************************************************************************/
1623 struct fw_flr_ack {
1624         u32         pf_ack;
1625         u32         vf_ack[1];
1626         u32         iov_dis_ack;
1627 };
1628
1629 struct fw_flr_mb {
1630         u32         aggint;
1631         u32         opgen_addr;
1632         struct fw_flr_ack ack;
1633 };
1634
1635 struct eee_remote_vals {
1636         u32         tx_tw;
1637         u32         rx_tw;
1638 };
1639
1640 /**** SUPPORT FOR SHMEM ARRRAYS ***
1641  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1642  * define arrays with storage types smaller then unsigned dwords.
1643  * The macros below add generic support for SHMEM arrays with numeric elements
1644  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1645  * array with individual bit-filed elements accessed using shifts and masks.
1646  *
1647  */
1648
1649 /* eb is the bitwidth of a single element */
1650 #define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
1651 #define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
1652
1653 /* the bit-position macro allows the used to flip the order of the arrays
1654  * elements on a per byte or word boundary.
1655  *
1656  * example: an array with 8 entries each 4 bit wide. This array will fit into
1657  * a single dword. The diagrmas below show the array order of the nibbles.
1658  *
1659  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1660  *
1661  *                |                |                |               |
1662  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
1663  *                |                |                |               |
1664  *
1665  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1666  *
1667  *                |                |                |               |
1668  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
1669  *                |                |                |               |
1670  *
1671  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1672  *
1673  *                |                |                |               |
1674  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
1675  *                |                |                |               |
1676  */
1677 #define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
1678         ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1679         (((i)%((fb)/(eb))) * (eb)))
1680
1681 #define SHMEM_ARRAY_GET(a, i, eb, fb)                                   \
1682         ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1683         SHMEM_ARRAY_MASK(eb))
1684
1685 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)                              \
1686 do {                                                                       \
1687         a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
1688         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1689         a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1690         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1691 } while (0)
1692
1693
1694 /****START OF DCBX STRUCTURES DECLARATIONS****/
1695 #define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
1696 #define DCBX_PRI_PG_BITWIDTH            4
1697 #define DCBX_PRI_PG_FBITS               8
1698 #define DCBX_PRI_PG_GET(a, i)           \
1699         SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1700 #define DCBX_PRI_PG_SET(a, i, val)      \
1701         SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1702 #define DCBX_MAX_NUM_PG_BW_ENTRIES      8
1703 #define DCBX_BW_PG_BITWIDTH             8
1704 #define DCBX_PG_BW_GET(a, i)            \
1705         SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1706 #define DCBX_PG_BW_SET(a, i, val)       \
1707         SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1708 #define DCBX_STRICT_PRI_PG              15
1709 #define DCBX_MAX_APP_PROTOCOL           16
1710 #define FCOE_APP_IDX                    0
1711 #define ISCSI_APP_IDX                   1
1712 #define PREDEFINED_APP_IDX_MAX          2
1713
1714
1715 /* Big/Little endian have the same representation. */
1716 struct dcbx_ets_feature {
1717         /*
1718          * For Admin MIB - is this feature supported by the
1719          * driver | For Local MIB - should this feature be enabled.
1720          */
1721         u32 enabled;
1722         u32  pg_bw_tbl[2];
1723         u32  pri_pg_tbl[1];
1724 };
1725
1726 /* Driver structure in LE */
1727 struct dcbx_pfc_feature {
1728 #ifdef __BIG_ENDIAN
1729         u8 pri_en_bitmap;
1730         #define DCBX_PFC_PRI_0 0x01
1731         #define DCBX_PFC_PRI_1 0x02
1732         #define DCBX_PFC_PRI_2 0x04
1733         #define DCBX_PFC_PRI_3 0x08
1734         #define DCBX_PFC_PRI_4 0x10
1735         #define DCBX_PFC_PRI_5 0x20
1736         #define DCBX_PFC_PRI_6 0x40
1737         #define DCBX_PFC_PRI_7 0x80
1738         u8 pfc_caps;
1739         u8 reserved;
1740         u8 enabled;
1741 #elif defined(__LITTLE_ENDIAN)
1742         u8 enabled;
1743         u8 reserved;
1744         u8 pfc_caps;
1745         u8 pri_en_bitmap;
1746         #define DCBX_PFC_PRI_0 0x01
1747         #define DCBX_PFC_PRI_1 0x02
1748         #define DCBX_PFC_PRI_2 0x04
1749         #define DCBX_PFC_PRI_3 0x08
1750         #define DCBX_PFC_PRI_4 0x10
1751         #define DCBX_PFC_PRI_5 0x20
1752         #define DCBX_PFC_PRI_6 0x40
1753         #define DCBX_PFC_PRI_7 0x80
1754 #endif
1755 };
1756
1757 struct dcbx_app_priority_entry {
1758 #ifdef __BIG_ENDIAN
1759         u16  app_id;
1760         u8  pri_bitmap;
1761         u8  appBitfield;
1762         #define DCBX_APP_ENTRY_VALID         0x01
1763         #define DCBX_APP_ENTRY_SF_MASK       0x30
1764         #define DCBX_APP_ENTRY_SF_SHIFT      4
1765         #define DCBX_APP_SF_ETH_TYPE         0x10
1766         #define DCBX_APP_SF_PORT             0x20
1767 #elif defined(__LITTLE_ENDIAN)
1768         u8 appBitfield;
1769         #define DCBX_APP_ENTRY_VALID         0x01
1770         #define DCBX_APP_ENTRY_SF_MASK       0x30
1771         #define DCBX_APP_ENTRY_SF_SHIFT      4
1772         #define DCBX_APP_SF_ETH_TYPE         0x10
1773         #define DCBX_APP_SF_PORT             0x20
1774         u8  pri_bitmap;
1775         u16  app_id;
1776 #endif
1777 };
1778
1779
1780 /* FW structure in BE */
1781 struct dcbx_app_priority_feature {
1782 #ifdef __BIG_ENDIAN
1783         u8 reserved;
1784         u8 default_pri;
1785         u8 tc_supported;
1786         u8 enabled;
1787 #elif defined(__LITTLE_ENDIAN)
1788         u8 enabled;
1789         u8 tc_supported;
1790         u8 default_pri;
1791         u8 reserved;
1792 #endif
1793         struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1794 };
1795
1796 /* FW structure in BE */
1797 struct dcbx_features {
1798         /* PG feature */
1799         struct dcbx_ets_feature ets;
1800         /* PFC feature */
1801         struct dcbx_pfc_feature pfc;
1802         /* APP feature */
1803         struct dcbx_app_priority_feature app;
1804 };
1805
1806 /* LLDP protocol parameters */
1807 /* FW structure in BE */
1808 struct lldp_params {
1809 #ifdef __BIG_ENDIAN
1810         u8  msg_fast_tx_interval;
1811         u8  msg_tx_hold;
1812         u8  msg_tx_interval;
1813         u8  admin_status;
1814         #define LLDP_TX_ONLY  0x01
1815         #define LLDP_RX_ONLY  0x02
1816         #define LLDP_TX_RX    0x03
1817         #define LLDP_DISABLED 0x04
1818         u8  reserved1;
1819         u8  tx_fast;
1820         u8  tx_crd_max;
1821         u8  tx_crd;
1822 #elif defined(__LITTLE_ENDIAN)
1823         u8  admin_status;
1824         #define LLDP_TX_ONLY  0x01
1825         #define LLDP_RX_ONLY  0x02
1826         #define LLDP_TX_RX    0x03
1827         #define LLDP_DISABLED 0x04
1828         u8  msg_tx_interval;
1829         u8  msg_tx_hold;
1830         u8  msg_fast_tx_interval;
1831         u8  tx_crd;
1832         u8  tx_crd_max;
1833         u8  tx_fast;
1834         u8  reserved1;
1835 #endif
1836         #define REM_CHASSIS_ID_STAT_LEN 4
1837         #define REM_PORT_ID_STAT_LEN 4
1838         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1839         u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1840         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1841         u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1842 };
1843
1844 struct lldp_dcbx_stat {
1845         #define LOCAL_CHASSIS_ID_STAT_LEN 2
1846         #define LOCAL_PORT_ID_STAT_LEN 2
1847         /* Holds local Chassis ID 8B payload of constant subtype 4. */
1848         u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1849         /* Holds local Port ID 8B payload of constant subtype 3. */
1850         u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1851         /* Number of DCBX frames transmitted. */
1852         u32 num_tx_dcbx_pkts;
1853         /* Number of DCBX frames received. */
1854         u32 num_rx_dcbx_pkts;
1855 };
1856
1857 /* ADMIN MIB - DCBX local machine default configuration. */
1858 struct lldp_admin_mib {
1859         u32     ver_cfg_flags;
1860         #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
1861         #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
1862         #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
1863         #define DCBX_ETS_RECO_TX_ENABLED         0x00000008
1864         #define DCBX_ETS_RECO_VALID              0x00000010
1865         #define DCBX_ETS_WILLING                 0x00000020
1866         #define DCBX_PFC_WILLING                 0x00000040
1867         #define DCBX_APP_WILLING                 0x00000080
1868         #define DCBX_VERSION_CEE                 0x00000100
1869         #define DCBX_VERSION_IEEE                0x00000200
1870         #define DCBX_DCBX_ENABLED                0x00000400
1871         #define DCBX_CEE_VERSION_MASK            0x0000f000
1872         #define DCBX_CEE_VERSION_SHIFT           12
1873         #define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
1874         #define DCBX_CEE_MAX_VERSION_SHIFT       16
1875         struct dcbx_features     features;
1876 };
1877
1878 /* REMOTE MIB - remote machine DCBX configuration. */
1879 struct lldp_remote_mib {
1880         u32 prefix_seq_num;
1881         u32 flags;
1882         #define DCBX_ETS_TLV_RX                  0x00000001
1883         #define DCBX_PFC_TLV_RX                  0x00000002
1884         #define DCBX_APP_TLV_RX                  0x00000004
1885         #define DCBX_ETS_RX_ERROR                0x00000010
1886         #define DCBX_PFC_RX_ERROR                0x00000020
1887         #define DCBX_APP_RX_ERROR                0x00000040
1888         #define DCBX_ETS_REM_WILLING             0x00000100
1889         #define DCBX_PFC_REM_WILLING             0x00000200
1890         #define DCBX_APP_REM_WILLING             0x00000400
1891         #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
1892         #define DCBX_REMOTE_MIB_VALID            0x00002000
1893         struct dcbx_features features;
1894         u32 suffix_seq_num;
1895 };
1896
1897 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1898 struct lldp_local_mib {
1899         u32 prefix_seq_num;
1900         /* Indicates if there is mismatch with negotiation results. */
1901         u32 error;
1902         #define DCBX_LOCAL_ETS_ERROR             0x00000001
1903         #define DCBX_LOCAL_PFC_ERROR             0x00000002
1904         #define DCBX_LOCAL_APP_ERROR             0x00000004
1905         #define DCBX_LOCAL_PFC_MISMATCH          0x00000010
1906         #define DCBX_LOCAL_APP_MISMATCH          0x00000020
1907         #define DCBX_REMOTE_MIB_ERROR            0x00000040
1908         #define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
1909         #define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
1910         #define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
1911         struct dcbx_features   features;
1912         u32 suffix_seq_num;
1913 };
1914 /***END OF DCBX STRUCTURES DECLARATIONS***/
1915
1916 struct ncsi_oem_fcoe_features {
1917         u32 fcoe_features1;
1918         #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
1919         #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
1920
1921         #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
1922         #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
1923
1924         u32 fcoe_features2;
1925         #define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
1926         #define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
1927
1928         #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
1929         #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
1930
1931         u32 fcoe_features3;
1932         #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
1933         #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
1934
1935         #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
1936         #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
1937
1938         u32 fcoe_features4;
1939         #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
1940         #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
1941 };
1942
1943 struct ncsi_oem_data {
1944         u32 driver_version[4];
1945         struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1946 };
1947
1948 struct shmem2_region {
1949
1950         u32 size;                                       /* 0x0000 */
1951
1952         u32 dcc_support;                                /* 0x0004 */
1953         #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
1954         #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
1955         #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
1956         #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
1957         #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
1958         #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
1959
1960         u32 ext_phy_fw_version2[PORT_MAX];              /* 0x0008 */
1961         /*
1962          * For backwards compatibility, if the mf_cfg_addr does not exist
1963          * (the size filed is smaller than 0xc) the mf_cfg resides at the
1964          * end of struct shmem_region
1965          */
1966         u32 mf_cfg_addr;                                /* 0x0010 */
1967         #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
1968
1969         struct fw_flr_mb flr_mb;                        /* 0x0014 */
1970         u32 dcbx_lldp_params_offset;                    /* 0x0028 */
1971         #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
1972         u32 dcbx_neg_res_offset;                        /* 0x002c */
1973         #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
1974         u32 dcbx_remote_mib_offset;                     /* 0x0030 */
1975         #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
1976         /*
1977          * The other shmemX_base_addr holds the other path's shmem address
1978          * required for example in case of common phy init, or for path1 to know
1979          * the address of mcp debug trace which is located in offset from shmem
1980          * of path0
1981          */
1982         u32 other_shmem_base_addr;                      /* 0x0034 */
1983         u32 other_shmem2_base_addr;                     /* 0x0038 */
1984         /*
1985          * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
1986          * which were disabled/flred
1987          */
1988         u32 mcp_vf_disabled[E2_VF_MAX / 32];            /* 0x003c */
1989
1990         /*
1991          * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
1992          * VFs
1993          */
1994         u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
1995
1996         u32 dcbx_lldp_dcbx_stat_offset;                 /* 0x0064 */
1997         #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
1998
1999         /*
2000          * edebug_driver_if field is used to transfer messages between edebug
2001          * app to the driver through shmem2.
2002          *
2003          * message format:
2004          * bits 0-2 -  function number / instance of driver to perform request
2005          * bits 3-5 -  op code / is_ack?
2006          * bits 6-63 - data
2007          */
2008         u32 edebug_driver_if[2];                        /* 0x0068 */
2009         #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
2010         #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
2011         #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
2012
2013         u32 nvm_retain_bitmap_addr;                     /* 0x0070 */
2014
2015         /* afex support of that driver */
2016         u32 afex_driver_support;                        /* 0x0074 */
2017         #define SHMEM_AFEX_VERSION_MASK                  0x100f
2018         #define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
2019         #define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
2020
2021         /* driver receives addr in scratchpad to which it should respond */
2022         u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2023
2024         /* generic params from MCP to driver (value depends on the msg sent
2025          * to driver
2026          */
2027         u32 afex_param1_to_driver[E2_FUNC_MAX];         /* 0x0088 */
2028         u32 afex_param2_to_driver[E2_FUNC_MAX];         /* 0x0098 */
2029
2030         u32 swim_base_addr;                             /* 0x0108 */
2031         u32 swim_funcs;
2032         u32 swim_main_cb;
2033
2034         /* bitmap notifying which VIF profiles stored in nvram are enabled by
2035          * switch
2036          */
2037         u32 afex_profiles_enabled[2];
2038
2039         /* generic flags controlled by the driver */
2040         u32 drv_flags;
2041         #define DRV_FLAGS_DCB_CONFIGURED                0x1
2042
2043         /* pointer to extended dev_info shared data copied from nvm image */
2044         u32 extended_dev_info_shared_addr;
2045         u32 ncsi_oem_data_addr;
2046
2047         u32 ocsd_host_addr; /* initialized by option ROM */
2048         u32 ocbb_host_addr; /* initialized by option ROM */
2049         u32 ocsd_req_update_interval; /* initialized by option ROM */
2050         u32 temperature_in_half_celsius;
2051         u32 glob_struct_in_host;
2052
2053         u32 dcbx_neg_res_ext_offset;
2054 #define SHMEM_DCBX_NEG_RES_EXT_NONE                     0x00000000
2055
2056         u32 drv_capabilities_flag[E2_FUNC_MAX];
2057 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2058 #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
2059 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
2060 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
2061
2062         u32 extended_dev_info_shared_cfg_size;
2063
2064         u32 dcbx_en[PORT_MAX];
2065
2066         /* The offset points to the multi threaded meta structure */
2067         u32 multi_thread_data_offset;
2068
2069         /* address of DMAable host address holding values from the drivers */
2070         u32 drv_info_host_addr_lo;
2071         u32 drv_info_host_addr_hi;
2072
2073         /* general values written by the MFW (such as current version) */
2074         u32 drv_info_control;
2075 #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
2076 #define DRV_INFO_CONTROL_VER_SHIFT         0
2077 #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
2078 #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
2079         u32 ibft_host_addr; /* initialized by option ROM */
2080         struct eee_remote_vals eee_remote_vals[PORT_MAX];
2081         u32 reserved[E2_FUNC_MAX];
2082
2083
2084         /* the status of EEE auto-negotiation
2085          * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2086          * bits 19:16 the supported modes for EEE.
2087          * bits 23:20 the speeds advertised for EEE.
2088          * bits 27:24 the speeds the Link partner advertised for EEE.
2089          * The supported/adv. modes in bits 27:19 originate from the
2090          * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2091          * bit 28 when 1'b1 EEE was requested.
2092          * bit 29 when 1'b1 tx lpi was requested.
2093          * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2094          * 30:29 are 2'b11.
2095          * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2096          * value. When 1'b1 those bits contains a value times 16 microseconds.
2097          */
2098         u32 eee_status[PORT_MAX];
2099         #define SHMEM_EEE_TIMER_MASK               0x0000ffff
2100         #define SHMEM_EEE_SUPPORTED_MASK           0x000f0000
2101         #define SHMEM_EEE_SUPPORTED_SHIFT          16
2102         #define SHMEM_EEE_ADV_STATUS_MASK          0x00f00000
2103                 #define SHMEM_EEE_100M_ADV         (1<<0)
2104                 #define SHMEM_EEE_1G_ADV           (1<<1)
2105                 #define SHMEM_EEE_10G_ADV          (1<<2)
2106         #define SHMEM_EEE_ADV_STATUS_SHIFT         20
2107         #define SHMEM_EEE_LP_ADV_STATUS_MASK       0x0f000000
2108         #define SHMEM_EEE_LP_ADV_STATUS_SHIFT      24
2109         #define SHMEM_EEE_REQUESTED_BIT            0x10000000
2110         #define SHMEM_EEE_LPI_REQUESTED_BIT        0x20000000
2111         #define SHMEM_EEE_ACTIVE_BIT               0x40000000
2112         #define SHMEM_EEE_TIME_OUTPUT_BIT          0x80000000
2113
2114         u32 sizeof_port_stats;
2115 };
2116
2117
2118 struct emac_stats {
2119         u32     rx_stat_ifhcinoctets;
2120         u32     rx_stat_ifhcinbadoctets;
2121         u32     rx_stat_etherstatsfragments;
2122         u32     rx_stat_ifhcinucastpkts;
2123         u32     rx_stat_ifhcinmulticastpkts;
2124         u32     rx_stat_ifhcinbroadcastpkts;
2125         u32     rx_stat_dot3statsfcserrors;
2126         u32     rx_stat_dot3statsalignmenterrors;
2127         u32     rx_stat_dot3statscarriersenseerrors;
2128         u32     rx_stat_xonpauseframesreceived;
2129         u32     rx_stat_xoffpauseframesreceived;
2130         u32     rx_stat_maccontrolframesreceived;
2131         u32     rx_stat_xoffstateentered;
2132         u32     rx_stat_dot3statsframestoolong;
2133         u32     rx_stat_etherstatsjabbers;
2134         u32     rx_stat_etherstatsundersizepkts;
2135         u32     rx_stat_etherstatspkts64octets;
2136         u32     rx_stat_etherstatspkts65octetsto127octets;
2137         u32     rx_stat_etherstatspkts128octetsto255octets;
2138         u32     rx_stat_etherstatspkts256octetsto511octets;
2139         u32     rx_stat_etherstatspkts512octetsto1023octets;
2140         u32     rx_stat_etherstatspkts1024octetsto1522octets;
2141         u32     rx_stat_etherstatspktsover1522octets;
2142
2143         u32     rx_stat_falsecarriererrors;
2144
2145         u32     tx_stat_ifhcoutoctets;
2146         u32     tx_stat_ifhcoutbadoctets;
2147         u32     tx_stat_etherstatscollisions;
2148         u32     tx_stat_outxonsent;
2149         u32     tx_stat_outxoffsent;
2150         u32     tx_stat_flowcontroldone;
2151         u32     tx_stat_dot3statssinglecollisionframes;
2152         u32     tx_stat_dot3statsmultiplecollisionframes;
2153         u32     tx_stat_dot3statsdeferredtransmissions;
2154         u32     tx_stat_dot3statsexcessivecollisions;
2155         u32     tx_stat_dot3statslatecollisions;
2156         u32     tx_stat_ifhcoutucastpkts;
2157         u32     tx_stat_ifhcoutmulticastpkts;
2158         u32     tx_stat_ifhcoutbroadcastpkts;
2159         u32     tx_stat_etherstatspkts64octets;
2160         u32     tx_stat_etherstatspkts65octetsto127octets;
2161         u32     tx_stat_etherstatspkts128octetsto255octets;
2162         u32     tx_stat_etherstatspkts256octetsto511octets;
2163         u32     tx_stat_etherstatspkts512octetsto1023octets;
2164         u32     tx_stat_etherstatspkts1024octetsto1522octets;
2165         u32     tx_stat_etherstatspktsover1522octets;
2166         u32     tx_stat_dot3statsinternalmactransmiterrors;
2167 };
2168
2169
2170 struct bmac1_stats {
2171         u32     tx_stat_gtpkt_lo;
2172         u32     tx_stat_gtpkt_hi;
2173         u32     tx_stat_gtxpf_lo;
2174         u32     tx_stat_gtxpf_hi;
2175         u32     tx_stat_gtfcs_lo;
2176         u32     tx_stat_gtfcs_hi;
2177         u32     tx_stat_gtmca_lo;
2178         u32     tx_stat_gtmca_hi;
2179         u32     tx_stat_gtbca_lo;
2180         u32     tx_stat_gtbca_hi;
2181         u32     tx_stat_gtfrg_lo;
2182         u32     tx_stat_gtfrg_hi;
2183         u32     tx_stat_gtovr_lo;
2184         u32     tx_stat_gtovr_hi;
2185         u32     tx_stat_gt64_lo;
2186         u32     tx_stat_gt64_hi;
2187         u32     tx_stat_gt127_lo;
2188         u32     tx_stat_gt127_hi;
2189         u32     tx_stat_gt255_lo;
2190         u32     tx_stat_gt255_hi;
2191         u32     tx_stat_gt511_lo;
2192         u32     tx_stat_gt511_hi;
2193         u32     tx_stat_gt1023_lo;
2194         u32     tx_stat_gt1023_hi;
2195         u32     tx_stat_gt1518_lo;
2196         u32     tx_stat_gt1518_hi;
2197         u32     tx_stat_gt2047_lo;
2198         u32     tx_stat_gt2047_hi;
2199         u32     tx_stat_gt4095_lo;
2200         u32     tx_stat_gt4095_hi;
2201         u32     tx_stat_gt9216_lo;
2202         u32     tx_stat_gt9216_hi;
2203         u32     tx_stat_gt16383_lo;
2204         u32     tx_stat_gt16383_hi;
2205         u32     tx_stat_gtmax_lo;
2206         u32     tx_stat_gtmax_hi;
2207         u32     tx_stat_gtufl_lo;
2208         u32     tx_stat_gtufl_hi;
2209         u32     tx_stat_gterr_lo;
2210         u32     tx_stat_gterr_hi;
2211         u32     tx_stat_gtbyt_lo;
2212         u32     tx_stat_gtbyt_hi;
2213
2214         u32     rx_stat_gr64_lo;
2215         u32     rx_stat_gr64_hi;
2216         u32     rx_stat_gr127_lo;
2217         u32     rx_stat_gr127_hi;
2218         u32     rx_stat_gr255_lo;
2219         u32     rx_stat_gr255_hi;
2220         u32     rx_stat_gr511_lo;
2221         u32     rx_stat_gr511_hi;
2222         u32     rx_stat_gr1023_lo;
2223         u32     rx_stat_gr1023_hi;
2224         u32     rx_stat_gr1518_lo;
2225         u32     rx_stat_gr1518_hi;
2226         u32     rx_stat_gr2047_lo;
2227         u32     rx_stat_gr2047_hi;
2228         u32     rx_stat_gr4095_lo;
2229         u32     rx_stat_gr4095_hi;
2230         u32     rx_stat_gr9216_lo;
2231         u32     rx_stat_gr9216_hi;
2232         u32     rx_stat_gr16383_lo;
2233         u32     rx_stat_gr16383_hi;
2234         u32     rx_stat_grmax_lo;
2235         u32     rx_stat_grmax_hi;
2236         u32     rx_stat_grpkt_lo;
2237         u32     rx_stat_grpkt_hi;
2238         u32     rx_stat_grfcs_lo;
2239         u32     rx_stat_grfcs_hi;
2240         u32     rx_stat_grmca_lo;
2241         u32     rx_stat_grmca_hi;
2242         u32     rx_stat_grbca_lo;
2243         u32     rx_stat_grbca_hi;
2244         u32     rx_stat_grxcf_lo;
2245         u32     rx_stat_grxcf_hi;
2246         u32     rx_stat_grxpf_lo;
2247         u32     rx_stat_grxpf_hi;
2248         u32     rx_stat_grxuo_lo;
2249         u32     rx_stat_grxuo_hi;
2250         u32     rx_stat_grjbr_lo;
2251         u32     rx_stat_grjbr_hi;
2252         u32     rx_stat_grovr_lo;
2253         u32     rx_stat_grovr_hi;
2254         u32     rx_stat_grflr_lo;
2255         u32     rx_stat_grflr_hi;
2256         u32     rx_stat_grmeg_lo;
2257         u32     rx_stat_grmeg_hi;
2258         u32     rx_stat_grmeb_lo;
2259         u32     rx_stat_grmeb_hi;
2260         u32     rx_stat_grbyt_lo;
2261         u32     rx_stat_grbyt_hi;
2262         u32     rx_stat_grund_lo;
2263         u32     rx_stat_grund_hi;
2264         u32     rx_stat_grfrg_lo;
2265         u32     rx_stat_grfrg_hi;
2266         u32     rx_stat_grerb_lo;
2267         u32     rx_stat_grerb_hi;
2268         u32     rx_stat_grfre_lo;
2269         u32     rx_stat_grfre_hi;
2270         u32     rx_stat_gripj_lo;
2271         u32     rx_stat_gripj_hi;
2272 };
2273
2274 struct bmac2_stats {
2275         u32     tx_stat_gtpk_lo; /* gtpok */
2276         u32     tx_stat_gtpk_hi; /* gtpok */
2277         u32     tx_stat_gtxpf_lo; /* gtpf */
2278         u32     tx_stat_gtxpf_hi; /* gtpf */
2279         u32     tx_stat_gtpp_lo; /* NEW BMAC2 */
2280         u32     tx_stat_gtpp_hi; /* NEW BMAC2 */
2281         u32     tx_stat_gtfcs_lo;
2282         u32     tx_stat_gtfcs_hi;
2283         u32     tx_stat_gtuca_lo; /* NEW BMAC2 */
2284         u32     tx_stat_gtuca_hi; /* NEW BMAC2 */
2285         u32     tx_stat_gtmca_lo;
2286         u32     tx_stat_gtmca_hi;
2287         u32     tx_stat_gtbca_lo;
2288         u32     tx_stat_gtbca_hi;
2289         u32     tx_stat_gtovr_lo;
2290         u32     tx_stat_gtovr_hi;
2291         u32     tx_stat_gtfrg_lo;
2292         u32     tx_stat_gtfrg_hi;
2293         u32     tx_stat_gtpkt1_lo; /* gtpkt */
2294         u32     tx_stat_gtpkt1_hi; /* gtpkt */
2295         u32     tx_stat_gt64_lo;
2296         u32     tx_stat_gt64_hi;
2297         u32     tx_stat_gt127_lo;
2298         u32     tx_stat_gt127_hi;
2299         u32     tx_stat_gt255_lo;
2300         u32     tx_stat_gt255_hi;
2301         u32     tx_stat_gt511_lo;
2302         u32     tx_stat_gt511_hi;
2303         u32     tx_stat_gt1023_lo;
2304         u32     tx_stat_gt1023_hi;
2305         u32     tx_stat_gt1518_lo;
2306         u32     tx_stat_gt1518_hi;
2307         u32     tx_stat_gt2047_lo;
2308         u32     tx_stat_gt2047_hi;
2309         u32     tx_stat_gt4095_lo;
2310         u32     tx_stat_gt4095_hi;
2311         u32     tx_stat_gt9216_lo;
2312         u32     tx_stat_gt9216_hi;
2313         u32     tx_stat_gt16383_lo;
2314         u32     tx_stat_gt16383_hi;
2315         u32     tx_stat_gtmax_lo;
2316         u32     tx_stat_gtmax_hi;
2317         u32     tx_stat_gtufl_lo;
2318         u32     tx_stat_gtufl_hi;
2319         u32     tx_stat_gterr_lo;
2320         u32     tx_stat_gterr_hi;
2321         u32     tx_stat_gtbyt_lo;
2322         u32     tx_stat_gtbyt_hi;
2323
2324         u32     rx_stat_gr64_lo;
2325         u32     rx_stat_gr64_hi;
2326         u32     rx_stat_gr127_lo;
2327         u32     rx_stat_gr127_hi;
2328         u32     rx_stat_gr255_lo;
2329         u32     rx_stat_gr255_hi;
2330         u32     rx_stat_gr511_lo;
2331         u32     rx_stat_gr511_hi;
2332         u32     rx_stat_gr1023_lo;
2333         u32     rx_stat_gr1023_hi;
2334         u32     rx_stat_gr1518_lo;
2335         u32     rx_stat_gr1518_hi;
2336         u32     rx_stat_gr2047_lo;
2337         u32     rx_stat_gr2047_hi;
2338         u32     rx_stat_gr4095_lo;
2339         u32     rx_stat_gr4095_hi;
2340         u32     rx_stat_gr9216_lo;
2341         u32     rx_stat_gr9216_hi;
2342         u32     rx_stat_gr16383_lo;
2343         u32     rx_stat_gr16383_hi;
2344         u32     rx_stat_grmax_lo;
2345         u32     rx_stat_grmax_hi;
2346         u32     rx_stat_grpkt_lo;
2347         u32     rx_stat_grpkt_hi;
2348         u32     rx_stat_grfcs_lo;
2349         u32     rx_stat_grfcs_hi;
2350         u32     rx_stat_gruca_lo;
2351         u32     rx_stat_gruca_hi;
2352         u32     rx_stat_grmca_lo;
2353         u32     rx_stat_grmca_hi;
2354         u32     rx_stat_grbca_lo;
2355         u32     rx_stat_grbca_hi;
2356         u32     rx_stat_grxpf_lo; /* grpf */
2357         u32     rx_stat_grxpf_hi; /* grpf */
2358         u32     rx_stat_grpp_lo;
2359         u32     rx_stat_grpp_hi;
2360         u32     rx_stat_grxuo_lo; /* gruo */
2361         u32     rx_stat_grxuo_hi; /* gruo */
2362         u32     rx_stat_grjbr_lo;
2363         u32     rx_stat_grjbr_hi;
2364         u32     rx_stat_grovr_lo;
2365         u32     rx_stat_grovr_hi;
2366         u32     rx_stat_grxcf_lo; /* grcf */
2367         u32     rx_stat_grxcf_hi; /* grcf */
2368         u32     rx_stat_grflr_lo;
2369         u32     rx_stat_grflr_hi;
2370         u32     rx_stat_grpok_lo;
2371         u32     rx_stat_grpok_hi;
2372         u32     rx_stat_grmeg_lo;
2373         u32     rx_stat_grmeg_hi;
2374         u32     rx_stat_grmeb_lo;
2375         u32     rx_stat_grmeb_hi;
2376         u32     rx_stat_grbyt_lo;
2377         u32     rx_stat_grbyt_hi;
2378         u32     rx_stat_grund_lo;
2379         u32     rx_stat_grund_hi;
2380         u32     rx_stat_grfrg_lo;
2381         u32     rx_stat_grfrg_hi;
2382         u32     rx_stat_grerb_lo; /* grerrbyt */
2383         u32     rx_stat_grerb_hi; /* grerrbyt */
2384         u32     rx_stat_grfre_lo; /* grfrerr */
2385         u32     rx_stat_grfre_hi; /* grfrerr */
2386         u32     rx_stat_gripj_lo;
2387         u32     rx_stat_gripj_hi;
2388 };
2389
2390 struct mstat_stats {
2391         struct {
2392                 /* OTE MSTAT on E3 has a bug where this register's contents are
2393                  * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2394                  */
2395                 u32 tx_gtxpok_lo;
2396                 u32 tx_gtxpok_hi;
2397                 u32 tx_gtxpf_lo;
2398                 u32 tx_gtxpf_hi;
2399                 u32 tx_gtxpp_lo;
2400                 u32 tx_gtxpp_hi;
2401                 u32 tx_gtfcs_lo;
2402                 u32 tx_gtfcs_hi;
2403                 u32 tx_gtuca_lo;
2404                 u32 tx_gtuca_hi;
2405                 u32 tx_gtmca_lo;
2406                 u32 tx_gtmca_hi;
2407                 u32 tx_gtgca_lo;
2408                 u32 tx_gtgca_hi;
2409                 u32 tx_gtpkt_lo;
2410                 u32 tx_gtpkt_hi;
2411                 u32 tx_gt64_lo;
2412                 u32 tx_gt64_hi;
2413                 u32 tx_gt127_lo;
2414                 u32 tx_gt127_hi;
2415                 u32 tx_gt255_lo;
2416                 u32 tx_gt255_hi;
2417                 u32 tx_gt511_lo;
2418                 u32 tx_gt511_hi;
2419                 u32 tx_gt1023_lo;
2420                 u32 tx_gt1023_hi;
2421                 u32 tx_gt1518_lo;
2422                 u32 tx_gt1518_hi;
2423                 u32 tx_gt2047_lo;
2424                 u32 tx_gt2047_hi;
2425                 u32 tx_gt4095_lo;
2426                 u32 tx_gt4095_hi;
2427                 u32 tx_gt9216_lo;
2428                 u32 tx_gt9216_hi;
2429                 u32 tx_gt16383_lo;
2430                 u32 tx_gt16383_hi;
2431                 u32 tx_gtufl_lo;
2432                 u32 tx_gtufl_hi;
2433                 u32 tx_gterr_lo;
2434                 u32 tx_gterr_hi;
2435                 u32 tx_gtbyt_lo;
2436                 u32 tx_gtbyt_hi;
2437                 u32 tx_collisions_lo;
2438                 u32 tx_collisions_hi;
2439                 u32 tx_singlecollision_lo;
2440                 u32 tx_singlecollision_hi;
2441                 u32 tx_multiplecollisions_lo;
2442                 u32 tx_multiplecollisions_hi;
2443                 u32 tx_deferred_lo;
2444                 u32 tx_deferred_hi;
2445                 u32 tx_excessivecollisions_lo;
2446                 u32 tx_excessivecollisions_hi;
2447                 u32 tx_latecollisions_lo;
2448                 u32 tx_latecollisions_hi;
2449         } stats_tx;
2450
2451         struct {
2452                 u32 rx_gr64_lo;
2453                 u32 rx_gr64_hi;
2454                 u32 rx_gr127_lo;
2455                 u32 rx_gr127_hi;
2456                 u32 rx_gr255_lo;
2457                 u32 rx_gr255_hi;
2458                 u32 rx_gr511_lo;
2459                 u32 rx_gr511_hi;
2460                 u32 rx_gr1023_lo;
2461                 u32 rx_gr1023_hi;
2462                 u32 rx_gr1518_lo;
2463                 u32 rx_gr1518_hi;
2464                 u32 rx_gr2047_lo;
2465                 u32 rx_gr2047_hi;
2466                 u32 rx_gr4095_lo;
2467                 u32 rx_gr4095_hi;
2468                 u32 rx_gr9216_lo;
2469                 u32 rx_gr9216_hi;
2470                 u32 rx_gr16383_lo;
2471                 u32 rx_gr16383_hi;
2472                 u32 rx_grpkt_lo;
2473                 u32 rx_grpkt_hi;
2474                 u32 rx_grfcs_lo;
2475                 u32 rx_grfcs_hi;
2476                 u32 rx_gruca_lo;
2477                 u32 rx_gruca_hi;
2478                 u32 rx_grmca_lo;
2479                 u32 rx_grmca_hi;
2480                 u32 rx_grbca_lo;
2481                 u32 rx_grbca_hi;
2482                 u32 rx_grxpf_lo;
2483                 u32 rx_grxpf_hi;
2484                 u32 rx_grxpp_lo;
2485                 u32 rx_grxpp_hi;
2486                 u32 rx_grxuo_lo;
2487                 u32 rx_grxuo_hi;
2488                 u32 rx_grovr_lo;
2489                 u32 rx_grovr_hi;
2490                 u32 rx_grxcf_lo;
2491                 u32 rx_grxcf_hi;
2492                 u32 rx_grflr_lo;
2493                 u32 rx_grflr_hi;
2494                 u32 rx_grpok_lo;
2495                 u32 rx_grpok_hi;
2496                 u32 rx_grbyt_lo;
2497                 u32 rx_grbyt_hi;
2498                 u32 rx_grund_lo;
2499                 u32 rx_grund_hi;
2500                 u32 rx_grfrg_lo;
2501                 u32 rx_grfrg_hi;
2502                 u32 rx_grerb_lo;
2503                 u32 rx_grerb_hi;
2504                 u32 rx_grfre_lo;
2505                 u32 rx_grfre_hi;
2506
2507                 u32 rx_alignmenterrors_lo;
2508                 u32 rx_alignmenterrors_hi;
2509                 u32 rx_falsecarrier_lo;
2510                 u32 rx_falsecarrier_hi;
2511                 u32 rx_llfcmsgcnt_lo;
2512                 u32 rx_llfcmsgcnt_hi;
2513         } stats_rx;
2514 };
2515
2516 union mac_stats {
2517         struct emac_stats       emac_stats;
2518         struct bmac1_stats      bmac1_stats;
2519         struct bmac2_stats      bmac2_stats;
2520         struct mstat_stats      mstat_stats;
2521 };
2522
2523
2524 struct mac_stx {
2525         /* in_bad_octets */
2526         u32     rx_stat_ifhcinbadoctets_hi;
2527         u32     rx_stat_ifhcinbadoctets_lo;
2528
2529         /* out_bad_octets */
2530         u32     tx_stat_ifhcoutbadoctets_hi;
2531         u32     tx_stat_ifhcoutbadoctets_lo;
2532
2533         /* crc_receive_errors */
2534         u32     rx_stat_dot3statsfcserrors_hi;
2535         u32     rx_stat_dot3statsfcserrors_lo;
2536         /* alignment_errors */
2537         u32     rx_stat_dot3statsalignmenterrors_hi;
2538         u32     rx_stat_dot3statsalignmenterrors_lo;
2539         /* carrier_sense_errors */
2540         u32     rx_stat_dot3statscarriersenseerrors_hi;
2541         u32     rx_stat_dot3statscarriersenseerrors_lo;
2542         /* false_carrier_detections */
2543         u32     rx_stat_falsecarriererrors_hi;
2544         u32     rx_stat_falsecarriererrors_lo;
2545
2546         /* runt_packets_received */
2547         u32     rx_stat_etherstatsundersizepkts_hi;
2548         u32     rx_stat_etherstatsundersizepkts_lo;
2549         /* jabber_packets_received */
2550         u32     rx_stat_dot3statsframestoolong_hi;
2551         u32     rx_stat_dot3statsframestoolong_lo;
2552
2553         /* error_runt_packets_received */
2554         u32     rx_stat_etherstatsfragments_hi;
2555         u32     rx_stat_etherstatsfragments_lo;
2556         /* error_jabber_packets_received */
2557         u32     rx_stat_etherstatsjabbers_hi;
2558         u32     rx_stat_etherstatsjabbers_lo;
2559
2560         /* control_frames_received */
2561         u32     rx_stat_maccontrolframesreceived_hi;
2562         u32     rx_stat_maccontrolframesreceived_lo;
2563         u32     rx_stat_mac_xpf_hi;
2564         u32     rx_stat_mac_xpf_lo;
2565         u32     rx_stat_mac_xcf_hi;
2566         u32     rx_stat_mac_xcf_lo;
2567
2568         /* xoff_state_entered */
2569         u32     rx_stat_xoffstateentered_hi;
2570         u32     rx_stat_xoffstateentered_lo;
2571         /* pause_xon_frames_received */
2572         u32     rx_stat_xonpauseframesreceived_hi;
2573         u32     rx_stat_xonpauseframesreceived_lo;
2574         /* pause_xoff_frames_received */
2575         u32     rx_stat_xoffpauseframesreceived_hi;
2576         u32     rx_stat_xoffpauseframesreceived_lo;
2577         /* pause_xon_frames_transmitted */
2578         u32     tx_stat_outxonsent_hi;
2579         u32     tx_stat_outxonsent_lo;
2580         /* pause_xoff_frames_transmitted */
2581         u32     tx_stat_outxoffsent_hi;
2582         u32     tx_stat_outxoffsent_lo;
2583         /* flow_control_done */
2584         u32     tx_stat_flowcontroldone_hi;
2585         u32     tx_stat_flowcontroldone_lo;
2586
2587         /* ether_stats_collisions */
2588         u32     tx_stat_etherstatscollisions_hi;
2589         u32     tx_stat_etherstatscollisions_lo;
2590         /* single_collision_transmit_frames */
2591         u32     tx_stat_dot3statssinglecollisionframes_hi;
2592         u32     tx_stat_dot3statssinglecollisionframes_lo;
2593         /* multiple_collision_transmit_frames */
2594         u32     tx_stat_dot3statsmultiplecollisionframes_hi;
2595         u32     tx_stat_dot3statsmultiplecollisionframes_lo;
2596         /* deferred_transmissions */
2597         u32     tx_stat_dot3statsdeferredtransmissions_hi;
2598         u32     tx_stat_dot3statsdeferredtransmissions_lo;
2599         /* excessive_collision_frames */
2600         u32     tx_stat_dot3statsexcessivecollisions_hi;
2601         u32     tx_stat_dot3statsexcessivecollisions_lo;
2602         /* late_collision_frames */
2603         u32     tx_stat_dot3statslatecollisions_hi;
2604         u32     tx_stat_dot3statslatecollisions_lo;
2605
2606         /* frames_transmitted_64_bytes */
2607         u32     tx_stat_etherstatspkts64octets_hi;
2608         u32     tx_stat_etherstatspkts64octets_lo;
2609         /* frames_transmitted_65_127_bytes */
2610         u32     tx_stat_etherstatspkts65octetsto127octets_hi;
2611         u32     tx_stat_etherstatspkts65octetsto127octets_lo;
2612         /* frames_transmitted_128_255_bytes */
2613         u32     tx_stat_etherstatspkts128octetsto255octets_hi;
2614         u32     tx_stat_etherstatspkts128octetsto255octets_lo;
2615         /* frames_transmitted_256_511_bytes */
2616         u32     tx_stat_etherstatspkts256octetsto511octets_hi;
2617         u32     tx_stat_etherstatspkts256octetsto511octets_lo;
2618         /* frames_transmitted_512_1023_bytes */
2619         u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
2620         u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
2621         /* frames_transmitted_1024_1522_bytes */
2622         u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
2623         u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
2624         /* frames_transmitted_1523_9022_bytes */
2625         u32     tx_stat_etherstatspktsover1522octets_hi;
2626         u32     tx_stat_etherstatspktsover1522octets_lo;
2627         u32     tx_stat_mac_2047_hi;
2628         u32     tx_stat_mac_2047_lo;
2629         u32     tx_stat_mac_4095_hi;
2630         u32     tx_stat_mac_4095_lo;
2631         u32     tx_stat_mac_9216_hi;
2632         u32     tx_stat_mac_9216_lo;
2633         u32     tx_stat_mac_16383_hi;
2634         u32     tx_stat_mac_16383_lo;
2635
2636         /* internal_mac_transmit_errors */
2637         u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
2638         u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
2639
2640         /* if_out_discards */
2641         u32     tx_stat_mac_ufl_hi;
2642         u32     tx_stat_mac_ufl_lo;
2643 };
2644
2645
2646 #define MAC_STX_IDX_MAX                     2
2647
2648 struct host_port_stats {
2649         u32            host_port_stats_counter;
2650
2651         struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2652
2653         u32            brb_drop_hi;
2654         u32            brb_drop_lo;
2655
2656         u32            not_used; /* obsolete */
2657         u32            pfc_frames_tx_hi;
2658         u32            pfc_frames_tx_lo;
2659         u32            pfc_frames_rx_hi;
2660         u32            pfc_frames_rx_lo;
2661
2662         u32            eee_lpi_count_hi;
2663         u32            eee_lpi_count_lo;
2664 };
2665
2666
2667 struct host_func_stats {
2668         u32     host_func_stats_start;
2669
2670         u32     total_bytes_received_hi;
2671         u32     total_bytes_received_lo;
2672
2673         u32     total_bytes_transmitted_hi;
2674         u32     total_bytes_transmitted_lo;
2675
2676         u32     total_unicast_packets_received_hi;
2677         u32     total_unicast_packets_received_lo;
2678
2679         u32     total_multicast_packets_received_hi;
2680         u32     total_multicast_packets_received_lo;
2681
2682         u32     total_broadcast_packets_received_hi;
2683         u32     total_broadcast_packets_received_lo;
2684
2685         u32     total_unicast_packets_transmitted_hi;
2686         u32     total_unicast_packets_transmitted_lo;
2687
2688         u32     total_multicast_packets_transmitted_hi;
2689         u32     total_multicast_packets_transmitted_lo;
2690
2691         u32     total_broadcast_packets_transmitted_hi;
2692         u32     total_broadcast_packets_transmitted_lo;
2693
2694         u32     valid_bytes_received_hi;
2695         u32     valid_bytes_received_lo;
2696
2697         u32     host_func_stats_end;
2698 };
2699
2700 /* VIC definitions */
2701 #define VICSTATST_UIF_INDEX 2
2702
2703 /* current drv_info version */
2704 #define DRV_INFO_CUR_VER 1
2705
2706 /* drv_info op codes supported */
2707 enum drv_info_opcode {
2708         ETH_STATS_OPCODE,
2709         FCOE_STATS_OPCODE,
2710         ISCSI_STATS_OPCODE
2711 };
2712
2713 #define ETH_STAT_INFO_VERSION_LEN       12
2714 /*  Per PCI Function Ethernet Statistics required from the driver */
2715 struct eth_stats_info {
2716         /* Function's Driver Version. padded to 12 */
2717         u8 version[ETH_STAT_INFO_VERSION_LEN];
2718         /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
2719         u8 mac_local[8];
2720         u8 mac_add1[8];         /* Additional Programmed MAC Addr 1. */
2721         u8 mac_add2[8];         /* Additional Programmed MAC Addr 2. */
2722         u32 mtu_size;           /* MTU Size. Note   : Negotiated MTU */
2723         u32 feature_flags;      /* Feature_Flags. */
2724 #define FEATURE_ETH_CHKSUM_OFFLOAD_MASK         0x01
2725 #define FEATURE_ETH_LSO_MASK                    0x02
2726 #define FEATURE_ETH_BOOTMODE_MASK               0x1C
2727 #define FEATURE_ETH_BOOTMODE_SHIFT              2
2728 #define FEATURE_ETH_BOOTMODE_NONE               (0x0 << 2)
2729 #define FEATURE_ETH_BOOTMODE_PXE                (0x1 << 2)
2730 #define FEATURE_ETH_BOOTMODE_ISCSI              (0x2 << 2)
2731 #define FEATURE_ETH_BOOTMODE_FCOE               (0x3 << 2)
2732 #define FEATURE_ETH_TOE_MASK                    0x20
2733         u32 lso_max_size;       /* LSO MaxOffloadSize. */
2734         u32 lso_min_seg_cnt;    /* LSO MinSegmentCount. */
2735         /* Num Offloaded Connections TCP_IPv4. */
2736         u32 ipv4_ofld_cnt;
2737         /* Num Offloaded Connections TCP_IPv6. */
2738         u32 ipv6_ofld_cnt;
2739         u32 promiscuous_mode;   /* Promiscuous Mode. non-zero true */
2740         u32 txq_size;           /* TX Descriptors Queue Size */
2741         u32 rxq_size;           /* RX Descriptors Queue Size */
2742         /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
2743         u32 txq_avg_depth;
2744         /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
2745         u32 rxq_avg_depth;
2746         /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
2747         u32 iov_offload;
2748         /* Number of NetQueue/VMQ Config'd. */
2749         u32 netq_cnt;
2750         u32 vf_cnt;             /* Num VF assigned to this PF. */
2751 };
2752
2753 /*  Per PCI Function FCOE Statistics required from the driver */
2754 struct fcoe_stats_info {
2755         u8 version[12];         /* Function's Driver Version. */
2756         u8 mac_local[8];        /* Locally Admin Addr. */
2757         u8 mac_add1[8];         /* Additional Programmed MAC Addr 1. */
2758         u8 mac_add2[8];         /* Additional Programmed MAC Addr 2. */
2759         /* QoS Priority (per 802.1p). 0-7255 */
2760         u32 qos_priority;
2761         u32 txq_size;           /* FCoE TX Descriptors Queue Size. */
2762         u32 rxq_size;           /* FCoE RX Descriptors Queue Size. */
2763         /* FCoE TX Descriptor Queue Avg Depth. */
2764         u32 txq_avg_depth;
2765         /* FCoE RX Descriptors Queue Avg Depth. */
2766         u32 rxq_avg_depth;
2767         u32 rx_frames_lo;       /* FCoE RX Frames received. */
2768         u32 rx_frames_hi;       /* FCoE RX Frames received. */
2769         u32 rx_bytes_lo;        /* FCoE RX Bytes received. */
2770         u32 rx_bytes_hi;        /* FCoE RX Bytes received. */
2771         u32 tx_frames_lo;       /* FCoE TX Frames sent. */
2772         u32 tx_frames_hi;       /* FCoE TX Frames sent. */
2773         u32 tx_bytes_lo;        /* FCoE TX Bytes sent. */
2774         u32 tx_bytes_hi;        /* FCoE TX Bytes sent. */
2775 };
2776
2777 /* Per PCI  Function iSCSI Statistics required from the driver*/
2778 struct iscsi_stats_info {
2779         u8 version[12];         /* Function's Driver Version. */
2780         u8 mac_local[8];        /* Locally Admin iSCSI MAC Addr. */
2781         u8 mac_add1[8];         /* Additional Programmed MAC Addr 1. */
2782         /* QoS Priority (per 802.1p). 0-7255 */
2783         u32 qos_priority;
2784         u8 initiator_name[64];  /* iSCSI Boot Initiator Node name. */
2785         u8 ww_port_name[64];    /* iSCSI World wide port name */
2786         u8 boot_target_name[64];/* iSCSI Boot Target Name. */
2787         u8 boot_target_ip[16];  /* iSCSI Boot Target IP. */
2788         u32 boot_target_portal; /* iSCSI Boot Target Portal. */
2789         u8 boot_init_ip[16];    /* iSCSI Boot Initiator IP Address. */
2790         u32 max_frame_size;     /* Max Frame Size. bytes */
2791         u32 txq_size;           /* PDU TX Descriptors Queue Size. */
2792         u32 rxq_size;           /* PDU RX Descriptors Queue Size. */
2793         u32 txq_avg_depth;      /* PDU TX Descriptor Queue Avg Depth. */
2794         u32 rxq_avg_depth;      /* PDU RX Descriptors Queue Avg Depth. */
2795         u32 rx_pdus_lo;         /* iSCSI PDUs received. */
2796         u32 rx_pdus_hi;         /* iSCSI PDUs received. */
2797         u32 rx_bytes_lo;        /* iSCSI RX Bytes received. */
2798         u32 rx_bytes_hi;        /* iSCSI RX Bytes received. */
2799         u32 tx_pdus_lo;         /* iSCSI PDUs sent. */
2800         u32 tx_pdus_hi;         /* iSCSI PDUs sent. */
2801         u32 tx_bytes_lo;        /* iSCSI PDU TX Bytes sent. */
2802         u32 tx_bytes_hi;        /* iSCSI PDU TX Bytes sent. */
2803         u32 pcp_prior_map_tbl;  /* C-PCP to S-PCP Priority MapTable.
2804                                  * 9 nibbles, the position of each nibble
2805                                  * represents the C-PCP value, the value
2806                                  * of the nibble = S-PCP value.
2807                                  */
2808 };
2809
2810 union drv_info_to_mcp {
2811         struct eth_stats_info   ether_stat;
2812         struct fcoe_stats_info  fcoe_stat;
2813         struct iscsi_stats_info iscsi_stat;
2814 };
2815
2816 /* stats collected for afex.
2817  * NOTE: structure is exactly as expected to be received by the switch.
2818  *       order must remain exactly as is unless protocol changes !
2819  */
2820 struct afex_stats {
2821         u32 tx_unicast_frames_hi;
2822         u32 tx_unicast_frames_lo;
2823         u32 tx_unicast_bytes_hi;
2824         u32 tx_unicast_bytes_lo;
2825         u32 tx_multicast_frames_hi;
2826         u32 tx_multicast_frames_lo;
2827         u32 tx_multicast_bytes_hi;
2828         u32 tx_multicast_bytes_lo;
2829         u32 tx_broadcast_frames_hi;
2830         u32 tx_broadcast_frames_lo;
2831         u32 tx_broadcast_bytes_hi;
2832         u32 tx_broadcast_bytes_lo;
2833         u32 tx_frames_discarded_hi;
2834         u32 tx_frames_discarded_lo;
2835         u32 tx_frames_dropped_hi;
2836         u32 tx_frames_dropped_lo;
2837
2838         u32 rx_unicast_frames_hi;
2839         u32 rx_unicast_frames_lo;
2840         u32 rx_unicast_bytes_hi;
2841         u32 rx_unicast_bytes_lo;
2842         u32 rx_multicast_frames_hi;
2843         u32 rx_multicast_frames_lo;
2844         u32 rx_multicast_bytes_hi;
2845         u32 rx_multicast_bytes_lo;
2846         u32 rx_broadcast_frames_hi;
2847         u32 rx_broadcast_frames_lo;
2848         u32 rx_broadcast_bytes_hi;
2849         u32 rx_broadcast_bytes_lo;
2850         u32 rx_frames_discarded_hi;
2851         u32 rx_frames_discarded_lo;
2852         u32 rx_frames_dropped_hi;
2853         u32 rx_frames_dropped_lo;
2854 };
2855
2856 #define BCM_5710_FW_MAJOR_VERSION                       7
2857 #define BCM_5710_FW_MINOR_VERSION                       2
2858 #define BCM_5710_FW_REVISION_VERSION                    51
2859 #define BCM_5710_FW_ENGINEERING_VERSION                 0
2860 #define BCM_5710_FW_COMPILE_FLAGS                       1
2861
2862
2863 /*
2864  * attention bits
2865  */
2866 struct atten_sp_status_block {
2867         __le32 attn_bits;
2868         __le32 attn_bits_ack;
2869         u8 status_block_id;
2870         u8 reserved0;
2871         __le16 attn_bits_index;
2872         __le32 reserved1;
2873 };
2874
2875
2876 /*
2877  * The eth aggregative context of Cstorm
2878  */
2879 struct cstorm_eth_ag_context {
2880         u32 __reserved0[10];
2881 };
2882
2883
2884 /*
2885  * dmae command structure
2886  */
2887 struct dmae_command {
2888         u32 opcode;
2889 #define DMAE_COMMAND_SRC (0x1<<0)
2890 #define DMAE_COMMAND_SRC_SHIFT 0
2891 #define DMAE_COMMAND_DST (0x3<<1)
2892 #define DMAE_COMMAND_DST_SHIFT 1
2893 #define DMAE_COMMAND_C_DST (0x1<<3)
2894 #define DMAE_COMMAND_C_DST_SHIFT 3
2895 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2896 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2897 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2898 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2899 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2900 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2901 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2902 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2903 #define DMAE_COMMAND_PORT (0x1<<11)
2904 #define DMAE_COMMAND_PORT_SHIFT 11
2905 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2906 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2907 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2908 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2909 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2910 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2911 #define DMAE_COMMAND_E1HVN (0x3<<15)
2912 #define DMAE_COMMAND_E1HVN_SHIFT 15
2913 #define DMAE_COMMAND_DST_VN (0x3<<17)
2914 #define DMAE_COMMAND_DST_VN_SHIFT 17
2915 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2916 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2917 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2918 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2919 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2920 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2921         u32 src_addr_lo;
2922         u32 src_addr_hi;
2923         u32 dst_addr_lo;
2924         u32 dst_addr_hi;
2925 #if defined(__BIG_ENDIAN)
2926         u16 opcode_iov;
2927 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2928 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2929 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2930 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2931 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2932 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2933 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2934 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2935 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2936 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2937 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2938 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2939         u16 len;
2940 #elif defined(__LITTLE_ENDIAN)
2941         u16 len;
2942         u16 opcode_iov;
2943 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2944 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2945 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2946 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2947 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2948 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2949 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2950 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2951 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2952 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2953 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2954 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2955 #endif
2956         u32 comp_addr_lo;
2957         u32 comp_addr_hi;
2958         u32 comp_val;
2959         u32 crc32;
2960         u32 crc32_c;
2961 #if defined(__BIG_ENDIAN)
2962         u16 crc16_c;
2963         u16 crc16;
2964 #elif defined(__LITTLE_ENDIAN)
2965         u16 crc16;
2966         u16 crc16_c;
2967 #endif
2968 #if defined(__BIG_ENDIAN)
2969         u16 reserved3;
2970         u16 crc_t10;
2971 #elif defined(__LITTLE_ENDIAN)
2972         u16 crc_t10;
2973         u16 reserved3;
2974 #endif
2975 #if defined(__BIG_ENDIAN)
2976         u16 xsum8;
2977         u16 xsum16;
2978 #elif defined(__LITTLE_ENDIAN)
2979         u16 xsum16;
2980         u16 xsum8;
2981 #endif
2982 };
2983
2984
2985 /*
2986  * common data for all protocols
2987  */
2988 struct doorbell_hdr {
2989         u8 header;
2990 #define DOORBELL_HDR_RX (0x1<<0)
2991 #define DOORBELL_HDR_RX_SHIFT 0
2992 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2993 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2994 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2995 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2996 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2997 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2998 };
2999
3000 /*
3001  * Ethernet doorbell
3002  */
3003 struct eth_tx_doorbell {
3004 #if defined(__BIG_ENDIAN)
3005         u16 npackets;
3006         u8 params;
3007 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3008 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3009 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3010 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3011 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3012 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3013         struct doorbell_hdr hdr;
3014 #elif defined(__LITTLE_ENDIAN)
3015         struct doorbell_hdr hdr;
3016         u8 params;
3017 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3018 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3019 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3020 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3021 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3022 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3023         u16 npackets;
3024 #endif
3025 };
3026
3027
3028 /*
3029  * 3 lines. status block
3030  */
3031 struct hc_status_block_e1x {
3032         __le16 index_values[HC_SB_MAX_INDICES_E1X];
3033         __le16 running_index[HC_SB_MAX_SM];
3034         __le32 rsrv[11];
3035 };
3036
3037 /*
3038  * host status block
3039  */
3040 struct host_hc_status_block_e1x {
3041         struct hc_status_block_e1x sb;
3042 };
3043
3044
3045 /*
3046  * 3 lines. status block
3047  */
3048 struct hc_status_block_e2 {
3049         __le16 index_values[HC_SB_MAX_INDICES_E2];
3050         __le16 running_index[HC_SB_MAX_SM];
3051         __le32 reserved[11];
3052 };
3053
3054 /*
3055  * host status block
3056  */
3057 struct host_hc_status_block_e2 {
3058         struct hc_status_block_e2 sb;
3059 };
3060
3061
3062 /*
3063  * 5 lines. slow-path status block
3064  */
3065 struct hc_sp_status_block {
3066         __le16 index_values[HC_SP_SB_MAX_INDICES];
3067         __le16 running_index;
3068         __le16 rsrv;
3069         u32 rsrv1;
3070 };
3071
3072 /*
3073  * host status block
3074  */
3075 struct host_sp_status_block {
3076         struct atten_sp_status_block atten_status_block;
3077         struct hc_sp_status_block sp_sb;
3078 };
3079
3080
3081 /*
3082  * IGU driver acknowledgment register
3083  */
3084 struct igu_ack_register {
3085 #if defined(__BIG_ENDIAN)
3086         u16 sb_id_and_flags;
3087 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3088 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3089 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3090 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3091 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3092 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3093 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3094 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3095 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3096 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3097         u16 status_block_index;
3098 #elif defined(__LITTLE_ENDIAN)
3099         u16 status_block_index;
3100         u16 sb_id_and_flags;
3101 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3102 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3103 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3104 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3105 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3106 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3107 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3108 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3109 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3110 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3111 #endif
3112 };
3113
3114
3115 /*
3116  * IGU driver acknowledgement register
3117  */
3118 struct igu_backward_compatible {
3119         u32 sb_id_and_flags;
3120 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3121 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3122 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3123 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3124 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3125 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3126 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3127 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3128 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3129 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3130 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3131 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3132         u32 reserved_2;
3133 };
3134
3135
3136 /*
3137  * IGU driver acknowledgement register
3138  */
3139 struct igu_regular {
3140         u32 sb_id_and_flags;
3141 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3142 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3143 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3144 #define IGU_REGULAR_RESERVED0_SHIFT 20
3145 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3146 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3147 #define IGU_REGULAR_BUPDATE (0x1<<24)
3148 #define IGU_REGULAR_BUPDATE_SHIFT 24
3149 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3150 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3151 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3152 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3153 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3154 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3155 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3156 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3157 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3158 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3159         u32 reserved_2;
3160 };
3161
3162 /*
3163  * IGU driver acknowledgement register
3164  */
3165 union igu_consprod_reg {
3166         struct igu_regular regular;
3167         struct igu_backward_compatible backward_compatible;
3168 };
3169
3170
3171 /*
3172  * Igu control commands
3173  */
3174 enum igu_ctrl_cmd {
3175         IGU_CTRL_CMD_TYPE_RD,
3176         IGU_CTRL_CMD_TYPE_WR,
3177         MAX_IGU_CTRL_CMD
3178 };
3179
3180
3181 /*
3182  * Control register for the IGU command register
3183  */
3184 struct igu_ctrl_reg {
3185         u32 ctrl_data;
3186 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3187 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3188 #define IGU_CTRL_REG_FID (0x7F<<12)
3189 #define IGU_CTRL_REG_FID_SHIFT 12
3190 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3191 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3192 #define IGU_CTRL_REG_TYPE (0x1<<20)
3193 #define IGU_CTRL_REG_TYPE_SHIFT 20
3194 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3195 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3196 };
3197
3198
3199 /*
3200  * Igu interrupt command
3201  */
3202 enum igu_int_cmd {
3203         IGU_INT_ENABLE,
3204         IGU_INT_DISABLE,
3205         IGU_INT_NOP,
3206         IGU_INT_NOP2,
3207         MAX_IGU_INT_CMD
3208 };
3209
3210
3211 /*
3212  * Igu segments
3213  */
3214 enum igu_seg_access {
3215         IGU_SEG_ACCESS_NORM,
3216         IGU_SEG_ACCESS_DEF,
3217         IGU_SEG_ACCESS_ATTN,
3218         MAX_IGU_SEG_ACCESS
3219 };
3220
3221
3222 /*
3223  * Parser parsing flags field
3224  */
3225 struct parsing_flags {
3226         __le16 flags;
3227 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3228 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3229 #define PARSING_FLAGS_VLAN (0x1<<1)
3230 #define PARSING_FLAGS_VLAN_SHIFT 1
3231 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3232 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3233 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3234 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3235 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3236 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3237 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3238 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3239 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3240 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3241 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3242 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3243 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3244 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3245 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3246 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3247 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3248 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3249 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3250 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3251 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3252 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3253 };
3254
3255
3256 /*
3257  * Parsing flags for TCP ACK type
3258  */
3259 enum prs_flags_ack_type {
3260         PRS_FLAG_PUREACK_PIGGY,
3261         PRS_FLAG_PUREACK_PURE,
3262         MAX_PRS_FLAGS_ACK_TYPE
3263 };
3264
3265
3266 /*
3267  * Parsing flags for Ethernet address type
3268  */
3269 enum prs_flags_eth_addr_type {
3270         PRS_FLAG_ETHTYPE_NON_UNICAST,
3271         PRS_FLAG_ETHTYPE_UNICAST,
3272         MAX_PRS_FLAGS_ETH_ADDR_TYPE
3273 };
3274
3275
3276 /*
3277  * Parsing flags for over-ethernet protocol
3278  */
3279 enum prs_flags_over_eth {
3280         PRS_FLAG_OVERETH_UNKNOWN,
3281         PRS_FLAG_OVERETH_IPV4,
3282         PRS_FLAG_OVERETH_IPV6,
3283         PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3284         MAX_PRS_FLAGS_OVER_ETH
3285 };
3286
3287
3288 /*
3289  * Parsing flags for over-IP protocol
3290  */
3291 enum prs_flags_over_ip {
3292         PRS_FLAG_OVERIP_UNKNOWN,
3293         PRS_FLAG_OVERIP_TCP,
3294         PRS_FLAG_OVERIP_UDP,
3295         MAX_PRS_FLAGS_OVER_IP
3296 };
3297
3298
3299 /*
3300  * SDM operation gen command (generate aggregative interrupt)
3301  */
3302 struct sdm_op_gen {
3303         __le32 command;
3304 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3305 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3306 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3307 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3308 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3309 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3310 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3311 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3312 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3313 #define SDM_OP_GEN_RESERVED_SHIFT 17
3314 };
3315
3316
3317 /*
3318  * Timers connection context
3319  */
3320 struct timers_block_context {
3321         u32 __reserved_0;
3322         u32 __reserved_1;
3323         u32 __reserved_2;
3324         u32 flags;
3325 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3326 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3327 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3328 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3329 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3330 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3331 };
3332
3333
3334 /*
3335  * The eth aggregative context of Tstorm
3336  */
3337 struct tstorm_eth_ag_context {
3338         u32 __reserved0[14];
3339 };
3340
3341
3342 /*
3343  * The eth aggregative context of Ustorm
3344  */
3345 struct ustorm_eth_ag_context {
3346         u32 __reserved0;
3347 #if defined(__BIG_ENDIAN)
3348         u8 cdu_usage;
3349         u8 __reserved2;
3350         u16 __reserved1;
3351 #elif defined(__LITTLE_ENDIAN)
3352         u16 __reserved1;
3353         u8 __reserved2;
3354         u8 cdu_usage;
3355 #endif
3356         u32 __reserved3[6];
3357 };
3358
3359
3360 /*
3361  * The eth aggregative context of Xstorm
3362  */
3363 struct xstorm_eth_ag_context {
3364         u32 reserved0;
3365 #if defined(__BIG_ENDIAN)
3366         u8 cdu_reserved;
3367         u8 reserved2;
3368         u16 reserved1;
3369 #elif defined(__LITTLE_ENDIAN)
3370         u16 reserved1;
3371         u8 reserved2;
3372         u8 cdu_reserved;
3373 #endif
3374         u32 reserved3[30];
3375 };
3376
3377
3378 /*
3379  * doorbell message sent to the chip
3380  */
3381 struct doorbell {
3382 #if defined(__BIG_ENDIAN)
3383         u16 zero_fill2;
3384         u8 zero_fill1;
3385         struct doorbell_hdr header;
3386 #elif defined(__LITTLE_ENDIAN)
3387         struct doorbell_hdr header;
3388         u8 zero_fill1;
3389         u16 zero_fill2;
3390 #endif
3391 };
3392
3393
3394 /*
3395  * doorbell message sent to the chip
3396  */
3397 struct doorbell_set_prod {
3398 #if defined(__BIG_ENDIAN)
3399         u16 prod;
3400         u8 zero_fill1;
3401         struct doorbell_hdr header;
3402 #elif defined(__LITTLE_ENDIAN)
3403         struct doorbell_hdr header;
3404         u8 zero_fill1;
3405         u16 prod;
3406 #endif
3407 };
3408
3409
3410 struct regpair {
3411         __le32 lo;
3412         __le32 hi;
3413 };
3414
3415
3416 /*
3417  * Classify rule opcodes in E2/E3
3418  */
3419 enum classify_rule {
3420         CLASSIFY_RULE_OPCODE_MAC,
3421         CLASSIFY_RULE_OPCODE_VLAN,
3422         CLASSIFY_RULE_OPCODE_PAIR,
3423         MAX_CLASSIFY_RULE
3424 };
3425
3426
3427 /*
3428  * Classify rule types in E2/E3
3429  */
3430 enum classify_rule_action_type {
3431         CLASSIFY_RULE_REMOVE,
3432         CLASSIFY_RULE_ADD,
3433         MAX_CLASSIFY_RULE_ACTION_TYPE
3434 };
3435
3436
3437 /*
3438  * client init ramrod data
3439  */
3440 struct client_init_general_data {
3441         u8 client_id;
3442         u8 statistics_counter_id;
3443         u8 statistics_en_flg;
3444         u8 is_fcoe_flg;
3445         u8 activate_flg;
3446         u8 sp_client_id;
3447         __le16 mtu;
3448         u8 statistics_zero_flg;
3449         u8 func_id;
3450         u8 cos;
3451         u8 traffic_type;
3452         u32 reserved0;
3453 };
3454
3455
3456 /*
3457  * client init rx data
3458  */
3459 struct client_init_rx_data {
3460         u8 tpa_en;
3461 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3462 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3463 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3464 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3465 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3466 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3467 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3468 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3469         u8 vmqueue_mode_en_flg;
3470         u8 extra_data_over_sgl_en_flg;
3471         u8 cache_line_alignment_log_size;
3472         u8 enable_dynamic_hc;
3473         u8 max_sges_for_packet;
3474         u8 client_qzone_id;
3475         u8 drop_ip_cs_err_flg;
3476         u8 drop_tcp_cs_err_flg;
3477         u8 drop_ttl0_flg;
3478         u8 drop_udp_cs_err_flg;
3479         u8 inner_vlan_removal_enable_flg;
3480         u8 outer_vlan_removal_enable_flg;
3481         u8 status_block_id;
3482         u8 rx_sb_index_number;
3483         u8 dont_verify_rings_pause_thr_flg;
3484         u8 max_tpa_queues;
3485         u8 silent_vlan_removal_flg;
3486         __le16 max_bytes_on_bd;
3487         __le16 sge_buff_size;
3488         u8 approx_mcast_engine_id;
3489         u8 rss_engine_id;
3490         struct regpair bd_page_base;
3491         struct regpair sge_page_base;
3492         struct regpair cqe_page_base;
3493         u8 is_leading_rss;
3494         u8 is_approx_mcast;
3495         __le16 max_agg_size;
3496         __le16 state;
3497 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3498 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3499 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3500 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3501 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3502 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3503 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3504 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3505 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3506 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3507 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3508 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3509 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3510 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3511 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3512 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3513         __le16 cqe_pause_thr_low;
3514         __le16 cqe_pause_thr_high;
3515         __le16 bd_pause_thr_low;
3516         __le16 bd_pause_thr_high;
3517         __le16 sge_pause_thr_low;
3518         __le16 sge_pause_thr_high;
3519         __le16 rx_cos_mask;
3520         __le16 silent_vlan_value;
3521         __le16 silent_vlan_mask;
3522         __le32 reserved6[2];
3523 };
3524
3525 /*
3526  * client init tx data
3527  */
3528 struct client_init_tx_data {
3529         u8 enforce_security_flg;
3530         u8 tx_status_block_id;
3531         u8 tx_sb_index_number;
3532         u8 tss_leading_client_id;
3533         u8 tx_switching_flg;
3534         u8 anti_spoofing_flg;
3535         __le16 default_vlan;
3536         struct regpair tx_bd_page_base;
3537         __le16 state;
3538 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3539 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3540 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3541 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3542 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3543 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3544 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3545 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3546 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3547 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3548         u8 default_vlan_flg;
3549         u8 force_default_pri_flg;
3550         __le32 reserved3;
3551 };
3552
3553 /*
3554  * client init ramrod data
3555  */
3556 struct client_init_ramrod_data {
3557         struct client_init_general_data general;
3558         struct client_init_rx_data rx;
3559         struct client_init_tx_data tx;
3560 };
3561
3562
3563 /*
3564  * client update ramrod data
3565  */
3566 struct client_update_ramrod_data {
3567         u8 client_id;
3568         u8 func_id;
3569         u8 inner_vlan_removal_enable_flg;
3570         u8 inner_vlan_removal_change_flg;
3571         u8 outer_vlan_removal_enable_flg;
3572         u8 outer_vlan_removal_change_flg;
3573         u8 anti_spoofing_enable_flg;
3574         u8 anti_spoofing_change_flg;
3575         u8 activate_flg;
3576         u8 activate_change_flg;
3577         __le16 default_vlan;
3578         u8 default_vlan_enable_flg;
3579         u8 default_vlan_change_flg;
3580         __le16 silent_vlan_value;
3581         __le16 silent_vlan_mask;
3582         u8 silent_vlan_removal_flg;
3583         u8 silent_vlan_change_flg;
3584         __le32 echo;
3585 };
3586
3587
3588 /*
3589  * The eth storm context of Cstorm
3590  */
3591 struct cstorm_eth_st_context {
3592         u32 __reserved0[4];
3593 };
3594
3595
3596 struct double_regpair {
3597         u32 regpair0_lo;
3598         u32 regpair0_hi;
3599         u32 regpair1_lo;
3600         u32 regpair1_hi;
3601 };
3602
3603
3604 /*
3605  * Ethernet address typesm used in ethernet tx BDs
3606  */
3607 enum eth_addr_type {
3608         UNKNOWN_ADDRESS,
3609         UNICAST_ADDRESS,
3610         MULTICAST_ADDRESS,
3611         BROADCAST_ADDRESS,
3612         MAX_ETH_ADDR_TYPE
3613 };
3614
3615
3616 /*
3617  *
3618  */
3619 struct eth_classify_cmd_header {
3620         u8 cmd_general_data;
3621 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3622 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3623 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3624 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3625 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3626 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3627 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3628 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3629 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3630 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3631         u8 func_id;
3632         u8 client_id;
3633         u8 reserved1;
3634 };
3635
3636
3637 /*
3638  * header for eth classification config ramrod
3639  */
3640 struct eth_classify_header {
3641         u8 rule_cnt;
3642         u8 reserved0;
3643         __le16 reserved1;
3644         __le32 echo;
3645 };
3646
3647
3648 /*
3649  * Command for adding/removing a MAC classification rule
3650  */
3651 struct eth_classify_mac_cmd {
3652         struct eth_classify_cmd_header header;
3653         __le32 reserved0;
3654         __le16 mac_lsb;
3655         __le16 mac_mid;
3656         __le16 mac_msb;
3657         __le16 reserved1;
3658 };
3659
3660
3661 /*
3662  * Command for adding/removing a MAC-VLAN pair classification rule
3663  */
3664 struct eth_classify_pair_cmd {
3665         struct eth_classify_cmd_header header;
3666         __le32 reserved0;
3667         __le16 mac_lsb;
3668         __le16 mac_mid;
3669         __le16 mac_msb;
3670         __le16 vlan;
3671 };
3672
3673
3674 /*
3675  * Command for adding/removing a VLAN classification rule
3676  */
3677 struct eth_classify_vlan_cmd {
3678         struct eth_classify_cmd_header header;
3679         __le32 reserved0;
3680         __le32 reserved1;
3681         __le16 reserved2;
3682         __le16 vlan;
3683 };
3684
3685 /*
3686  * union for eth classification rule
3687  */
3688 union eth_classify_rule_cmd {
3689         struct eth_classify_mac_cmd mac;
3690         struct eth_classify_vlan_cmd vlan;
3691         struct eth_classify_pair_cmd pair;
3692 };
3693
3694 /*
3695  * parameters for eth classification configuration ramrod
3696  */
3697 struct eth_classify_rules_ramrod_data {
3698         struct eth_classify_header header;
3699         union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3700 };
3701
3702
3703 /*
3704  * The data contain client ID need to the ramrod
3705  */
3706 struct eth_common_ramrod_data {
3707         __le32 client_id;
3708         __le32 reserved1;
3709 };
3710
3711
3712 /*
3713  * The eth storm context of Ustorm
3714  */
3715 struct ustorm_eth_st_context {
3716         u32 reserved0[52];
3717 };
3718
3719 /*
3720  * The eth storm context of Tstorm
3721  */
3722 struct tstorm_eth_st_context {
3723         u32 __reserved0[28];
3724 };
3725
3726 /*
3727  * The eth storm context of Xstorm
3728  */
3729 struct xstorm_eth_st_context {
3730         u32 reserved0[60];
3731 };
3732
3733 /*
3734  * Ethernet connection context
3735  */
3736 struct eth_context {
3737         struct ustorm_eth_st_context ustorm_st_context;
3738         struct tstorm_eth_st_context tstorm_st_context;
3739         struct xstorm_eth_ag_context xstorm_ag_context;
3740         struct tstorm_eth_ag_context tstorm_ag_context;
3741         struct cstorm_eth_ag_context cstorm_ag_context;
3742         struct ustorm_eth_ag_context ustorm_ag_context;
3743         struct timers_block_context timers_context;
3744         struct xstorm_eth_st_context xstorm_st_context;
3745         struct cstorm_eth_st_context cstorm_st_context;
3746 };
3747
3748
3749 /*
3750  * union for sgl and raw data.
3751  */
3752 union eth_sgl_or_raw_data {
3753         __le16 sgl[8];
3754         u32 raw_data[4];
3755 };
3756
3757 /*
3758  * eth FP end aggregation CQE parameters struct
3759  */
3760 struct eth_end_agg_rx_cqe {
3761         u8 type_error_flags;
3762 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3763 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3764 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3765 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3766 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3767 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3768         u8 reserved1;
3769         u8 queue_index;
3770         u8 reserved2;
3771         __le32 timestamp_delta;
3772         __le16 num_of_coalesced_segs;
3773         __le16 pkt_len;
3774         u8 pure_ack_count;
3775         u8 reserved3;
3776         __le16 reserved4;
3777         union eth_sgl_or_raw_data sgl_or_raw_data;
3778         __le32 reserved5[8];
3779 };
3780
3781
3782 /*
3783  * regular eth FP CQE parameters struct
3784  */
3785 struct eth_fast_path_rx_cqe {
3786         u8 type_error_flags;
3787 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3788 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3789 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3790 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3791 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3792 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3793 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3794 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3795 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3796 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3797 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3798 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3799         u8 status_flags;
3800 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3801 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3802 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3803 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3804 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3805 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3806 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3807 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3808 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3809 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3810 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3811 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3812         u8 queue_index;
3813         u8 placement_offset;
3814         __le32 rss_hash_result;
3815         __le16 vlan_tag;
3816         __le16 pkt_len_or_gro_seg_len;
3817         __le16 len_on_bd;
3818         struct parsing_flags pars_flags;
3819         union eth_sgl_or_raw_data sgl_or_raw_data;
3820         __le32 reserved1[8];
3821 };
3822
3823
3824 /*
3825  * Command for setting classification flags for a client
3826  */
3827 struct eth_filter_rules_cmd {
3828         u8 cmd_general_data;
3829 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3830 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3831 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3832 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3833 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3834 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3835         u8 func_id;
3836         u8 client_id;
3837         u8 reserved1;
3838         __le16 state;
3839 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3840 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3841 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3842 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3843 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3844 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3845 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3846 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3847 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3848 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3849 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3850 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3851 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3852 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3853 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3854 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3855         __le16 reserved3;
3856         struct regpair reserved4;
3857 };
3858
3859
3860 /*
3861  * parameters for eth classification filters ramrod
3862  */
3863 struct eth_filter_rules_ramrod_data {
3864         struct eth_classify_header header;
3865         struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3866 };
3867
3868
3869 /*
3870  * parameters for eth classification configuration ramrod
3871  */
3872 struct eth_general_rules_ramrod_data {
3873         struct eth_classify_header header;
3874         union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3875 };
3876
3877
3878 /*
3879  * The data for Halt ramrod
3880  */
3881 struct eth_halt_ramrod_data {
3882         __le32 client_id;
3883         __le32 reserved0;
3884 };
3885
3886
3887 /*
3888  * Command for setting multicast classification for a client
3889  */
3890 struct eth_multicast_rules_cmd {
3891         u8 cmd_general_data;
3892 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3893 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3894 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3895 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3896 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3897 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3898 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3899 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3900         u8 func_id;
3901         u8 bin_id;
3902         u8 engine_id;
3903         __le32 reserved2;
3904         struct regpair reserved3;
3905 };
3906
3907
3908 /*
3909  * parameters for multicast classification ramrod
3910  */
3911 struct eth_multicast_rules_ramrod_data {
3912         struct eth_classify_header header;
3913         struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3914 };
3915
3916
3917 /*
3918  * Place holder for ramrods protocol specific data
3919  */
3920 struct ramrod_data {
3921         __le32 data_lo;
3922         __le32 data_hi;
3923 };
3924
3925 /*
3926  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3927  */
3928 union eth_ramrod_data {
3929         struct ramrod_data general;
3930 };
3931
3932
3933 /*
3934  * RSS toeplitz hash type, as reported in CQE
3935  */
3936 enum eth_rss_hash_type {
3937         DEFAULT_HASH_TYPE,
3938         IPV4_HASH_TYPE,
3939         TCP_IPV4_HASH_TYPE,
3940         IPV6_HASH_TYPE,
3941         TCP_IPV6_HASH_TYPE,
3942         VLAN_PRI_HASH_TYPE,
3943         E1HOV_PRI_HASH_TYPE,
3944         DSCP_HASH_TYPE,
3945         MAX_ETH_RSS_HASH_TYPE
3946 };
3947
3948
3949 /*
3950  * Ethernet RSS mode
3951  */
3952 enum eth_rss_mode {
3953         ETH_RSS_MODE_DISABLED,
3954         ETH_RSS_MODE_REGULAR,
3955         ETH_RSS_MODE_VLAN_PRI,
3956         ETH_RSS_MODE_E1HOV_PRI,
3957         ETH_RSS_MODE_IP_DSCP,
3958         MAX_ETH_RSS_MODE
3959 };
3960
3961
3962 /*
3963  * parameters for RSS update ramrod (E2)
3964  */
3965 struct eth_rss_update_ramrod_data {
3966         u8 rss_engine_id;
3967         u8 capabilities;
3968 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3969 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3970 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3971 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3972 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3973 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3974 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3975 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3976 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3977 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3978 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3979 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3980 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3981 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3982 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3983 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3984         u8 rss_result_mask;
3985         u8 rss_mode;
3986         __le32 __reserved2;
3987         u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3988         __le32 rss_key[T_ETH_RSS_KEY];
3989         __le32 echo;
3990         __le32 reserved3;
3991 };
3992
3993
3994 /*
3995  * The eth Rx Buffer Descriptor
3996  */
3997 struct eth_rx_bd {
3998         __le32 addr_lo;
3999         __le32 addr_hi;
4000 };
4001
4002
4003 /*
4004  * Eth Rx Cqe structure- general structure for ramrods
4005  */
4006 struct common_ramrod_eth_rx_cqe {
4007         u8 ramrod_type;
4008 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4009 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4010 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4011 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4012 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4013 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4014         u8 conn_type;
4015         __le16 reserved1;
4016         __le32 conn_and_cmd_data;
4017 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4018 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4019 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4020 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4021         struct ramrod_data protocol_data;
4022         __le32 echo;
4023         __le32 reserved2[11];
4024 };
4025
4026 /*
4027  * Rx Last CQE in page (in ETH)
4028  */
4029 struct eth_rx_cqe_next_page {
4030         __le32 addr_lo;
4031         __le32 addr_hi;
4032         __le32 reserved[14];
4033 };
4034
4035 /*
4036  * union for all eth rx cqe types (fix their sizes)
4037  */
4038 union eth_rx_cqe {
4039         struct eth_fast_path_rx_cqe fast_path_cqe;
4040         struct common_ramrod_eth_rx_cqe ramrod_cqe;
4041         struct eth_rx_cqe_next_page next_page_cqe;
4042         struct eth_end_agg_rx_cqe end_agg_cqe;
4043 };
4044
4045
4046 /*
4047  * Values for RX ETH CQE type field
4048  */
4049 enum eth_rx_cqe_type {
4050         RX_ETH_CQE_TYPE_ETH_FASTPATH,
4051         RX_ETH_CQE_TYPE_ETH_RAMROD,
4052         RX_ETH_CQE_TYPE_ETH_START_AGG,
4053         RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4054         MAX_ETH_RX_CQE_TYPE
4055 };
4056
4057
4058 /*
4059  * Type of SGL/Raw field in ETH RX fast path CQE
4060  */
4061 enum eth_rx_fp_sel {
4062         ETH_FP_CQE_REGULAR,
4063         ETH_FP_CQE_RAW,
4064         MAX_ETH_RX_FP_SEL
4065 };
4066
4067
4068 /*
4069  * The eth Rx SGE Descriptor
4070  */
4071 struct eth_rx_sge {
4072         __le32 addr_lo;
4073         __le32 addr_hi;
4074 };
4075
4076
4077 /*
4078  * common data for all protocols
4079  */
4080 struct spe_hdr {
4081         __le32 conn_and_cmd_data;
4082 #define SPE_HDR_CID (0xFFFFFF<<0)
4083 #define SPE_HDR_CID_SHIFT 0
4084 #define SPE_HDR_CMD_ID (0xFF<<24)
4085 #define SPE_HDR_CMD_ID_SHIFT 24
4086         __le16 type;
4087 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4088 #define SPE_HDR_CONN_TYPE_SHIFT 0
4089 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4090 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4091         __le16 reserved1;
4092 };
4093
4094 /*
4095  * specific data for ethernet slow path element
4096  */
4097 union eth_specific_data {
4098         u8 protocol_data[8];
4099         struct regpair client_update_ramrod_data;
4100         struct regpair client_init_ramrod_init_data;
4101         struct eth_halt_ramrod_data halt_ramrod_data;
4102         struct regpair update_data_addr;
4103         struct eth_common_ramrod_data common_ramrod_data;
4104         struct regpair classify_cfg_addr;
4105         struct regpair filter_cfg_addr;
4106         struct regpair mcast_cfg_addr;
4107 };
4108
4109 /*
4110  * Ethernet slow path element
4111  */
4112 struct eth_spe {
4113         struct spe_hdr hdr;
4114         union eth_specific_data data;
4115 };
4116
4117
4118 /*
4119  * Ethernet command ID for slow path elements
4120  */
4121 enum eth_spqe_cmd_id {
4122         RAMROD_CMD_ID_ETH_UNUSED,
4123         RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4124         RAMROD_CMD_ID_ETH_HALT,
4125         RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4126         RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4127         RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4128         RAMROD_CMD_ID_ETH_EMPTY,
4129         RAMROD_CMD_ID_ETH_TERMINATE,
4130         RAMROD_CMD_ID_ETH_TPA_UPDATE,
4131         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4132         RAMROD_CMD_ID_ETH_FILTER_RULES,
4133         RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4134         RAMROD_CMD_ID_ETH_RSS_UPDATE,
4135         RAMROD_CMD_ID_ETH_SET_MAC,
4136         MAX_ETH_SPQE_CMD_ID
4137 };
4138
4139
4140 /*
4141  * eth tpa update command
4142  */
4143 enum eth_tpa_update_command {
4144         TPA_UPDATE_NONE_COMMAND,
4145         TPA_UPDATE_ENABLE_COMMAND,
4146         TPA_UPDATE_DISABLE_COMMAND,
4147         MAX_ETH_TPA_UPDATE_COMMAND
4148 };
4149
4150
4151 /*
4152  * Tx regular BD structure
4153  */
4154 struct eth_tx_bd {
4155         __le32 addr_lo;
4156         __le32 addr_hi;
4157         __le16 total_pkt_bytes;
4158         __le16 nbytes;
4159         u8 reserved[4];
4160 };
4161
4162
4163 /*
4164  * structure for easy accessibility to assembler
4165  */
4166 struct eth_tx_bd_flags {
4167         u8 as_bitfield;
4168 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4169 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4170 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4171 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4172 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4173 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4174 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4175 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4176 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4177 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4178 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4179 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4180 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4181 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4182 };
4183
4184 /*
4185  * The eth Tx Buffer Descriptor
4186  */
4187 struct eth_tx_start_bd {
4188         __le32 addr_lo;
4189         __le32 addr_hi;
4190         __le16 nbd;
4191         __le16 nbytes;
4192         __le16 vlan_or_ethertype;
4193         struct eth_tx_bd_flags bd_flags;
4194         u8 general_data;
4195 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4196 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4197 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4198 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4199 #define ETH_TX_START_BD_RESREVED (0x1<<5)
4200 #define ETH_TX_START_BD_RESREVED_SHIFT 5
4201 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
4202 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
4203 };
4204
4205 /*
4206  * Tx parsing BD structure for ETH E1/E1h
4207  */
4208 struct eth_tx_parse_bd_e1x {
4209         u8 global_data;
4210 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4211 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4212 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
4213 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
4214 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
4215 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
4216 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
4217 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
4218 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
4219 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
4220         u8 tcp_flags;
4221 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4222 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4223 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4224 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4225 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4226 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4227 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4228 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4229 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4230 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4231 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4232 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4233 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4234 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4235 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4236 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4237         u8 ip_hlen_w;
4238         s8 reserved;
4239         __le16 total_hlen_w;
4240         __le16 tcp_pseudo_csum;
4241         __le16 lso_mss;
4242         __le16 ip_id;
4243         __le32 tcp_send_seq;
4244 };
4245
4246 /*
4247  * Tx parsing BD structure for ETH E2
4248  */
4249 struct eth_tx_parse_bd_e2 {
4250         __le16 dst_mac_addr_lo;
4251         __le16 dst_mac_addr_mid;
4252         __le16 dst_mac_addr_hi;
4253         __le16 src_mac_addr_lo;
4254         __le16 src_mac_addr_mid;
4255         __le16 src_mac_addr_hi;
4256         __le32 parsing_data;
4257 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
4258 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4259 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
4260 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
4261 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
4262 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
4263 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
4264 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
4265 };
4266
4267 /*
4268  * The last BD in the BD memory will hold a pointer to the next BD memory
4269  */
4270 struct eth_tx_next_bd {
4271         __le32 addr_lo;
4272         __le32 addr_hi;
4273         u8 reserved[8];
4274 };
4275
4276 /*
4277  * union for 4 Bd types
4278  */
4279 union eth_tx_bd_types {
4280         struct eth_tx_start_bd start_bd;
4281         struct eth_tx_bd reg_bd;
4282         struct eth_tx_parse_bd_e1x parse_bd_e1x;
4283         struct eth_tx_parse_bd_e2 parse_bd_e2;
4284         struct eth_tx_next_bd next_bd;
4285 };
4286
4287 /*
4288  * array of 13 bds as appears in the eth xstorm context
4289  */
4290 struct eth_tx_bds_array {
4291         union eth_tx_bd_types bds[13];
4292 };
4293
4294
4295 /*
4296  * VLAN mode on TX BDs
4297  */
4298 enum eth_tx_vlan_type {
4299         X_ETH_NO_VLAN,
4300         X_ETH_OUTBAND_VLAN,
4301         X_ETH_INBAND_VLAN,
4302         X_ETH_FW_ADDED_VLAN,
4303         MAX_ETH_TX_VLAN_TYPE
4304 };
4305
4306
4307 /*
4308  * Ethernet VLAN filtering mode in E1x
4309  */
4310 enum eth_vlan_filter_mode {
4311         ETH_VLAN_FILTER_ANY_VLAN,
4312         ETH_VLAN_FILTER_SPECIFIC_VLAN,
4313         ETH_VLAN_FILTER_CLASSIFY,
4314         MAX_ETH_VLAN_FILTER_MODE
4315 };
4316
4317
4318 /*
4319  * MAC filtering configuration command header
4320  */
4321 struct mac_configuration_hdr {
4322         u8 length;
4323         u8 offset;
4324         __le16 client_id;
4325         __le32 echo;
4326 };
4327
4328 /*
4329  * MAC address in list for ramrod
4330  */
4331 struct mac_configuration_entry {
4332         __le16 lsb_mac_addr;
4333         __le16 middle_mac_addr;
4334         __le16 msb_mac_addr;
4335         __le16 vlan_id;
4336         u8 pf_id;
4337         u8 flags;
4338 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4339 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4340 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4341 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4342 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4343 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4344 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4345 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4346 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4347 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4348 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4349 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4350         __le16 reserved0;
4351         __le32 clients_bit_vector;
4352 };
4353
4354 /*
4355  * MAC filtering configuration command
4356  */
4357 struct mac_configuration_cmd {
4358         struct mac_configuration_hdr hdr;
4359         struct mac_configuration_entry config_table[64];
4360 };
4361
4362
4363 /*
4364  * Set-MAC command type (in E1x)
4365  */
4366 enum set_mac_action_type {
4367         T_ETH_MAC_COMMAND_INVALIDATE,
4368         T_ETH_MAC_COMMAND_SET,
4369         MAX_SET_MAC_ACTION_TYPE
4370 };
4371
4372
4373 /*
4374  * Ethernet TPA Modes
4375  */
4376 enum tpa_mode {
4377         TPA_LRO,
4378         TPA_GRO,
4379         MAX_TPA_MODE};
4380
4381
4382 /*
4383  * tpa update ramrod data
4384  */
4385 struct tpa_update_ramrod_data {
4386         u8 update_ipv4;
4387         u8 update_ipv6;
4388         u8 client_id;
4389         u8 max_tpa_queues;
4390         u8 max_sges_for_packet;
4391         u8 complete_on_both_clients;
4392         u8 dont_verify_rings_pause_thr_flg;
4393         u8 tpa_mode;
4394         __le16 sge_buff_size;
4395         __le16 max_agg_size;
4396         __le32 sge_page_base_lo;
4397         __le32 sge_page_base_hi;
4398         __le16 sge_pause_thr_low;
4399         __le16 sge_pause_thr_high;
4400 };
4401
4402
4403 /*
4404  * approximate-match multicast filtering for E1H per function in Tstorm
4405  */
4406 struct tstorm_eth_approximate_match_multicast_filtering {
4407         u32 mcast_add_hash_bit_array[8];
4408 };
4409
4410
4411 /*
4412  * Common configuration parameters per function in Tstorm
4413  */
4414 struct tstorm_eth_function_common_config {
4415         __le16 config_flags;
4416 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4417 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4418 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4419 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4420 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4421 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4422 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4423 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4424 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4425 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4426 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4427 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4428 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4429 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4430         u8 rss_result_mask;
4431         u8 reserved1;
4432         __le16 vlan_id[2];
4433 };
4434
4435
4436 /*
4437  * MAC filtering configuration parameters per port in Tstorm
4438  */
4439 struct tstorm_eth_mac_filter_config {
4440         __le32 ucast_drop_all;
4441         __le32 ucast_accept_all;
4442         __le32 mcast_drop_all;
4443         __le32 mcast_accept_all;
4444         __le32 bcast_accept_all;
4445         __le32 vlan_filter[2];
4446         __le32 unmatched_unicast;
4447 };
4448
4449
4450 /*
4451  * tx only queue init ramrod data
4452  */
4453 struct tx_queue_init_ramrod_data {
4454         struct client_init_general_data general;
4455         struct client_init_tx_data tx;
4456 };
4457
4458
4459 /*
4460  * Three RX producers for ETH
4461  */
4462 struct ustorm_eth_rx_producers {
4463 #if defined(__BIG_ENDIAN)
4464         u16 bd_prod;
4465         u16 cqe_prod;
4466 #elif defined(__LITTLE_ENDIAN)
4467         u16 cqe_prod;
4468         u16 bd_prod;
4469 #endif
4470 #if defined(__BIG_ENDIAN)
4471         u16 reserved;
4472         u16 sge_prod;
4473 #elif defined(__LITTLE_ENDIAN)
4474         u16 sge_prod;
4475         u16 reserved;
4476 #endif
4477 };
4478
4479
4480 /*
4481  * FCoE RX statistics parameters section#0
4482  */
4483 struct fcoe_rx_stat_params_section0 {
4484         __le32 fcoe_rx_pkt_cnt;
4485         __le32 fcoe_rx_byte_cnt;
4486 };
4487
4488
4489 /*
4490  * FCoE RX statistics parameters section#1
4491  */
4492 struct fcoe_rx_stat_params_section1 {
4493         __le32 fcoe_ver_cnt;
4494         __le32 fcoe_rx_drop_pkt_cnt;
4495 };
4496
4497
4498 /*
4499  * FCoE RX statistics parameters section#2
4500  */
4501 struct fcoe_rx_stat_params_section2 {
4502         __le32 fc_crc_cnt;
4503         __le32 eofa_del_cnt;
4504         __le32 miss_frame_cnt;
4505         __le32 seq_timeout_cnt;
4506         __le32 drop_seq_cnt;
4507         __le32 fcoe_rx_drop_pkt_cnt;
4508         __le32 fcp_rx_pkt_cnt;
4509         __le32 reserved0;
4510 };
4511
4512
4513 /*
4514  * FCoE TX statistics parameters
4515  */
4516 struct fcoe_tx_stat_params {
4517         __le32 fcoe_tx_pkt_cnt;
4518         __le32 fcoe_tx_byte_cnt;
4519         __le32 fcp_tx_pkt_cnt;
4520         __le32 reserved0;
4521 };
4522
4523 /*
4524  * FCoE statistics parameters
4525  */
4526 struct fcoe_statistics_params {
4527         struct fcoe_tx_stat_params tx_stat;
4528         struct fcoe_rx_stat_params_section0 rx_stat0;
4529         struct fcoe_rx_stat_params_section1 rx_stat1;
4530         struct fcoe_rx_stat_params_section2 rx_stat2;
4531 };
4532
4533
4534 /*
4535  * The data afex vif list ramrod need
4536  */
4537 struct afex_vif_list_ramrod_data {
4538         u8 afex_vif_list_command;
4539         u8 func_bit_map;
4540         __le16 vif_list_index;
4541         u8 func_to_clear;
4542         u8 echo;
4543         __le16 reserved1;
4544 };
4545
4546
4547 /*
4548  * cfc delete event data
4549  */
4550 struct cfc_del_event_data {
4551         u32 cid;
4552         u32 reserved0;
4553         u32 reserved1;
4554 };
4555
4556
4557 /*
4558  * per-port SAFC demo variables
4559  */
4560 struct cmng_flags_per_port {
4561         u32 cmng_enables;
4562 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4563 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4564 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4565 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4566 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4567 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4568 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4569 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4570 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4571 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4572         u32 __reserved1;
4573 };
4574
4575
4576 /*
4577  * per-port rate shaping variables
4578  */
4579 struct rate_shaping_vars_per_port {
4580         u32 rs_periodic_timeout;
4581         u32 rs_threshold;
4582 };
4583
4584 /*
4585  * per-port fairness variables
4586  */
4587 struct fairness_vars_per_port {
4588         u32 upper_bound;
4589         u32 fair_threshold;
4590         u32 fairness_timeout;
4591         u32 reserved0;
4592 };
4593
4594 /*
4595  * per-port SAFC variables
4596  */
4597 struct safc_struct_per_port {
4598 #if defined(__BIG_ENDIAN)
4599         u16 __reserved1;
4600         u8 __reserved0;
4601         u8 safc_timeout_usec;
4602 #elif defined(__LITTLE_ENDIAN)
4603         u8 safc_timeout_usec;
4604         u8 __reserved0;
4605         u16 __reserved1;
4606 #endif
4607         u8 cos_to_traffic_types[MAX_COS_NUMBER];
4608         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4609 };
4610
4611 /*
4612  * Per-port congestion management variables
4613  */
4614 struct cmng_struct_per_port {
4615         struct rate_shaping_vars_per_port rs_vars;
4616         struct fairness_vars_per_port fair_vars;
4617         struct safc_struct_per_port safc_vars;
4618         struct cmng_flags_per_port flags;
4619 };
4620
4621 /*
4622  * a single rate shaping counter. can be used as protocol or vnic counter
4623  */
4624 struct rate_shaping_counter {
4625         u32 quota;
4626 #if defined(__BIG_ENDIAN)
4627         u16 __reserved0;
4628         u16 rate;
4629 #elif defined(__LITTLE_ENDIAN)
4630         u16 rate;
4631         u16 __reserved0;
4632 #endif
4633 };
4634
4635 /*
4636  * per-vnic rate shaping variables
4637  */
4638 struct rate_shaping_vars_per_vn {
4639         struct rate_shaping_counter vn_counter;
4640 };
4641
4642 /*
4643  * per-vnic fairness variables
4644  */
4645 struct fairness_vars_per_vn {
4646         u32 cos_credit_delta[MAX_COS_NUMBER];
4647         u32 vn_credit_delta;
4648         u32 __reserved0;
4649 };
4650
4651 /*
4652  * cmng port init state
4653  */
4654 struct cmng_vnic {
4655         struct rate_shaping_vars_per_vn vnic_max_rate[4];
4656         struct fairness_vars_per_vn vnic_min_rate[4];
4657 };
4658
4659 /*
4660  * cmng port init state
4661  */
4662 struct cmng_init {
4663         struct cmng_struct_per_port port;
4664         struct cmng_vnic vnic;
4665 };
4666
4667
4668 /*
4669  * driver parameters for congestion management init, all rates are in Mbps
4670  */
4671 struct cmng_init_input {
4672         u32 port_rate;
4673         u16 vnic_min_rate[4];
4674         u16 vnic_max_rate[4];
4675         u16 cos_min_rate[MAX_COS_NUMBER];
4676         u16 cos_to_pause_mask[MAX_COS_NUMBER];
4677         struct cmng_flags_per_port flags;
4678 };
4679
4680
4681 /*
4682  * Protocol-common command ID for slow path elements
4683  */
4684 enum common_spqe_cmd_id {
4685         RAMROD_CMD_ID_COMMON_UNUSED,
4686         RAMROD_CMD_ID_COMMON_FUNCTION_START,
4687         RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4688         RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4689         RAMROD_CMD_ID_COMMON_CFC_DEL,
4690         RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4691         RAMROD_CMD_ID_COMMON_STAT_QUERY,
4692         RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4693         RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4694         RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4695         MAX_COMMON_SPQE_CMD_ID
4696 };
4697
4698
4699 /*
4700  * Per-protocol connection types
4701  */
4702 enum connection_type {
4703         ETH_CONNECTION_TYPE,
4704         TOE_CONNECTION_TYPE,
4705         RDMA_CONNECTION_TYPE,
4706         ISCSI_CONNECTION_TYPE,
4707         FCOE_CONNECTION_TYPE,
4708         RESERVED_CONNECTION_TYPE_0,
4709         RESERVED_CONNECTION_TYPE_1,
4710         RESERVED_CONNECTION_TYPE_2,
4711         NONE_CONNECTION_TYPE,
4712         MAX_CONNECTION_TYPE
4713 };
4714
4715
4716 /*
4717  * Cos modes
4718  */
4719 enum cos_mode {
4720         OVERRIDE_COS,
4721         STATIC_COS,
4722         FW_WRR,
4723         MAX_COS_MODE
4724 };
4725
4726
4727 /*
4728  * Dynamic HC counters set by the driver
4729  */
4730 struct hc_dynamic_drv_counter {
4731         u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4732 };
4733
4734 /*
4735  * zone A per-queue data
4736  */
4737 struct cstorm_queue_zone_data {
4738         struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4739         struct regpair reserved[2];
4740 };
4741
4742
4743 /*
4744  * Vf-PF channel data in cstorm ram (non-triggered zone)
4745  */
4746 struct vf_pf_channel_zone_data {
4747         u32 msg_addr_lo;
4748         u32 msg_addr_hi;
4749 };
4750
4751 /*
4752  * zone for VF non-triggered data
4753  */
4754 struct non_trigger_vf_zone {
4755         struct vf_pf_channel_zone_data vf_pf_channel;
4756 };
4757
4758 /*
4759  * Vf-PF channel trigger zone in cstorm ram
4760  */
4761 struct vf_pf_channel_zone_trigger {
4762         u8 addr_valid;
4763 };
4764
4765 /*
4766  * zone that triggers the in-bound interrupt
4767  */
4768 struct trigger_vf_zone {
4769 #if defined(__BIG_ENDIAN)
4770         u16 reserved1;
4771         u8 reserved0;
4772         struct vf_pf_channel_zone_trigger vf_pf_channel;
4773 #elif defined(__LITTLE_ENDIAN)
4774         struct vf_pf_channel_zone_trigger vf_pf_channel;
4775         u8 reserved0;
4776         u16 reserved1;
4777 #endif
4778         u32 reserved2;
4779 };
4780
4781 /*
4782  * zone B per-VF data
4783  */
4784 struct cstorm_vf_zone_data {
4785         struct non_trigger_vf_zone non_trigger;
4786         struct trigger_vf_zone trigger;
4787 };
4788
4789
4790 /*
4791  * Dynamic host coalescing init parameters, per state machine
4792  */
4793 struct dynamic_hc_sm_config {
4794         u32 threshold[3];
4795         u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4796         u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4797         u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4798         u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4799         u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4800 };
4801
4802 /*
4803  * Dynamic host coalescing init parameters
4804  */
4805 struct dynamic_hc_config {
4806         struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4807 };
4808
4809
4810 struct e2_integ_data {
4811 #if defined(__BIG_ENDIAN)
4812         u8 flags;
4813 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4814 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4815 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4816 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4817 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4818 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4819 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4820 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4821 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4822 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4823 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4824 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4825         u8 cos;
4826         u8 voq;
4827         u8 pbf_queue;
4828 #elif defined(__LITTLE_ENDIAN)
4829         u8 pbf_queue;
4830         u8 voq;
4831         u8 cos;
4832         u8 flags;
4833 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4834 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4835 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4836 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4837 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4838 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4839 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4840 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4841 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4842 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4843 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4844 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4845 #endif
4846 #if defined(__BIG_ENDIAN)
4847         u16 reserved3;
4848         u8 reserved2;
4849         u8 ramEn;
4850 #elif defined(__LITTLE_ENDIAN)
4851         u8 ramEn;
4852         u8 reserved2;
4853         u16 reserved3;
4854 #endif
4855 };
4856
4857
4858 /*
4859  * set mac event data
4860  */
4861 struct eth_event_data {
4862         u32 echo;
4863         u32 reserved0;
4864         u32 reserved1;
4865 };
4866
4867
4868 /*
4869  * pf-vf event data
4870  */
4871 struct vf_pf_event_data {
4872         u8 vf_id;
4873         u8 reserved0;
4874         u16 reserved1;
4875         u32 msg_addr_lo;
4876         u32 msg_addr_hi;
4877 };
4878
4879 /*
4880  * VF FLR event data
4881  */
4882 struct vf_flr_event_data {
4883         u8 vf_id;
4884         u8 reserved0;
4885         u16 reserved1;
4886         u32 reserved2;
4887         u32 reserved3;
4888 };
4889
4890 /*
4891  * malicious VF event data
4892  */
4893 struct malicious_vf_event_data {
4894         u8 vf_id;
4895         u8 reserved0;
4896         u16 reserved1;
4897         u32 reserved2;
4898         u32 reserved3;
4899 };
4900
4901 /*
4902  * vif list event data
4903  */
4904 struct vif_list_event_data {
4905         u8 func_bit_map;
4906         u8 echo;
4907         __le16 reserved0;
4908         __le32 reserved1;
4909         __le32 reserved2;
4910 };
4911
4912 /*
4913  * union for all event ring message types
4914  */
4915 union event_data {
4916         struct vf_pf_event_data vf_pf_event;
4917         struct eth_event_data eth_event;
4918         struct cfc_del_event_data cfc_del_event;
4919         struct vf_flr_event_data vf_flr_event;
4920         struct malicious_vf_event_data malicious_vf_event;
4921         struct vif_list_event_data vif_list_event;
4922 };
4923
4924
4925 /*
4926  * per PF event ring data
4927  */
4928 struct event_ring_data {
4929         struct regpair base_addr;
4930 #if defined(__BIG_ENDIAN)
4931         u8 index_id;
4932         u8 sb_id;
4933         u16 producer;
4934 #elif defined(__LITTLE_ENDIAN)
4935         u16 producer;
4936         u8 sb_id;
4937         u8 index_id;
4938 #endif
4939         u32 reserved0;
4940 };
4941
4942
4943 /*
4944  * event ring message element (each element is 128 bits)
4945  */
4946 struct event_ring_msg {
4947         u8 opcode;
4948         u8 error;
4949         u16 reserved1;
4950         union event_data data;
4951 };
4952
4953 /*
4954  * event ring next page element (128 bits)
4955  */
4956 struct event_ring_next {
4957         struct regpair addr;
4958         u32 reserved[2];
4959 };
4960
4961 /*
4962  * union for event ring element types (each element is 128 bits)
4963  */
4964 union event_ring_elem {
4965         struct event_ring_msg message;
4966         struct event_ring_next next_page;
4967 };
4968
4969
4970 /*
4971  * Common event ring opcodes
4972  */
4973 enum event_ring_opcode {
4974         EVENT_RING_OPCODE_VF_PF_CHANNEL,
4975         EVENT_RING_OPCODE_FUNCTION_START,
4976         EVENT_RING_OPCODE_FUNCTION_STOP,
4977         EVENT_RING_OPCODE_CFC_DEL,
4978         EVENT_RING_OPCODE_CFC_DEL_WB,
4979         EVENT_RING_OPCODE_STAT_QUERY,
4980         EVENT_RING_OPCODE_STOP_TRAFFIC,
4981         EVENT_RING_OPCODE_START_TRAFFIC,
4982         EVENT_RING_OPCODE_VF_FLR,
4983         EVENT_RING_OPCODE_MALICIOUS_VF,
4984         EVENT_RING_OPCODE_FORWARD_SETUP,
4985         EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4986         EVENT_RING_OPCODE_FUNCTION_UPDATE,
4987         EVENT_RING_OPCODE_AFEX_VIF_LISTS,
4988         EVENT_RING_OPCODE_SET_MAC,
4989         EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4990         EVENT_RING_OPCODE_FILTERS_RULES,
4991         EVENT_RING_OPCODE_MULTICAST_RULES,
4992         MAX_EVENT_RING_OPCODE
4993 };
4994
4995
4996 /*
4997  * Modes for fairness algorithm
4998  */
4999 enum fairness_mode {
5000         FAIRNESS_COS_WRR_MODE,
5001         FAIRNESS_COS_ETS_MODE,
5002         MAX_FAIRNESS_MODE
5003 };
5004
5005
5006 /*
5007  * Priority and cos
5008  */
5009 struct priority_cos {
5010         u8 priority;
5011         u8 cos;
5012         __le16 reserved1;
5013 };
5014
5015 /*
5016  * The data for flow control configuration
5017  */
5018 struct flow_control_configuration {
5019         struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5020         u8 dcb_enabled;
5021         u8 dcb_version;
5022         u8 dont_add_pri_0_en;
5023         u8 reserved1;
5024         __le32 reserved2;
5025 };
5026
5027
5028 /*
5029  *
5030  */
5031 struct function_start_data {
5032         __le16 function_mode;
5033         __le16 sd_vlan_tag;
5034         __le16 vif_id;
5035         u8 path_id;
5036         u8 network_cos_mode;
5037 };
5038
5039
5040 struct function_update_data {
5041         u8 vif_id_change_flg;
5042         u8 afex_default_vlan_change_flg;
5043         u8 allowed_priorities_change_flg;
5044         u8 network_cos_mode_change_flg;
5045         __le16 vif_id;
5046         __le16 afex_default_vlan;
5047         u8 allowed_priorities;
5048         u8 network_cos_mode;
5049         u8 lb_mode_en;
5050         u8 reserved0;
5051         __le32 reserved1;
5052 };
5053
5054
5055 /*
5056  * FW version stored in the Xstorm RAM
5057  */
5058 struct fw_version {
5059 #if defined(__BIG_ENDIAN)
5060         u8 engineering;
5061         u8 revision;
5062         u8 minor;
5063         u8 major;
5064 #elif defined(__LITTLE_ENDIAN)
5065         u8 major;
5066         u8 minor;
5067         u8 revision;
5068         u8 engineering;
5069 #endif
5070         u32 flags;
5071 #define FW_VERSION_OPTIMIZED (0x1<<0)
5072 #define FW_VERSION_OPTIMIZED_SHIFT 0
5073 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5074 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5075 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5076 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5077 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5078 #define __FW_VERSION_RESERVED_SHIFT 4
5079 };
5080
5081
5082 /*
5083  * Dynamic Host-Coalescing - Driver(host) counters
5084  */
5085 struct hc_dynamic_sb_drv_counters {
5086         u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5087 };
5088
5089
5090 /*
5091  * 2 bytes. configuration/state parameters for a single protocol index
5092  */
5093 struct hc_index_data {
5094 #if defined(__BIG_ENDIAN)
5095         u8 flags;
5096 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5097 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5098 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5099 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5100 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5101 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5102 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5103 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5104         u8 timeout;
5105 #elif defined(__LITTLE_ENDIAN)
5106         u8 timeout;
5107         u8 flags;
5108 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5109 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5110 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5111 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5112 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5113 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5114 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5115 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5116 #endif
5117 };
5118
5119
5120 /*
5121  * HC state-machine
5122  */
5123 struct hc_status_block_sm {
5124 #if defined(__BIG_ENDIAN)
5125         u8 igu_seg_id;
5126         u8 igu_sb_id;
5127         u8 timer_value;
5128         u8 __flags;
5129 #elif defined(__LITTLE_ENDIAN)
5130         u8 __flags;
5131         u8 timer_value;
5132         u8 igu_sb_id;
5133         u8 igu_seg_id;
5134 #endif
5135         u32 time_to_expire;
5136 };
5137
5138 /*
5139  * hold PCI identification variables- used in various places in firmware
5140  */
5141 struct pci_entity {
5142 #if defined(__BIG_ENDIAN)
5143         u8 vf_valid;
5144         u8 vf_id;
5145         u8 vnic_id;
5146         u8 pf_id;
5147 #elif defined(__LITTLE_ENDIAN)
5148         u8 pf_id;
5149         u8 vnic_id;
5150         u8 vf_id;
5151         u8 vf_valid;
5152 #endif
5153 };
5154
5155 /*
5156  * The fast-path status block meta-data, common to all chips
5157  */
5158 struct hc_sb_data {
5159         struct regpair host_sb_addr;
5160         struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5161         struct pci_entity p_func;
5162 #if defined(__BIG_ENDIAN)
5163         u8 rsrv0;
5164         u8 state;
5165         u8 dhc_qzone_id;
5166         u8 same_igu_sb_1b;
5167 #elif defined(__LITTLE_ENDIAN)
5168         u8 same_igu_sb_1b;
5169         u8 dhc_qzone_id;
5170         u8 state;
5171         u8 rsrv0;
5172 #endif
5173         struct regpair rsrv1[2];
5174 };
5175
5176
5177 /*
5178  * Segment types for host coaslescing
5179  */
5180 enum hc_segment {
5181         HC_REGULAR_SEGMENT,
5182         HC_DEFAULT_SEGMENT,
5183         MAX_HC_SEGMENT
5184 };
5185
5186
5187 /*
5188  * The fast-path status block meta-data
5189  */
5190 struct hc_sp_status_block_data {
5191         struct regpair host_sb_addr;
5192 #if defined(__BIG_ENDIAN)
5193         u8 rsrv1;
5194         u8 state;
5195         u8 igu_seg_id;
5196         u8 igu_sb_id;
5197 #elif defined(__LITTLE_ENDIAN)
5198         u8 igu_sb_id;
5199         u8 igu_seg_id;
5200         u8 state;
5201         u8 rsrv1;
5202 #endif
5203         struct pci_entity p_func;
5204 };
5205
5206
5207 /*
5208  * The fast-path status block meta-data
5209  */
5210 struct hc_status_block_data_e1x {
5211         struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5212         struct hc_sb_data common;
5213 };
5214
5215
5216 /*
5217  * The fast-path status block meta-data
5218  */
5219 struct hc_status_block_data_e2 {
5220         struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5221         struct hc_sb_data common;
5222 };
5223
5224
5225 /*
5226  * IGU block operartion modes (in Everest2)
5227  */
5228 enum igu_mode {
5229         HC_IGU_BC_MODE,
5230         HC_IGU_NBC_MODE,
5231         MAX_IGU_MODE
5232 };
5233
5234
5235 /*
5236  * IP versions
5237  */
5238 enum ip_ver {
5239         IP_V4,
5240         IP_V6,
5241         MAX_IP_VER
5242 };
5243
5244
5245 /*
5246  * Multi-function modes
5247  */
5248 enum mf_mode {
5249         SINGLE_FUNCTION,
5250         MULTI_FUNCTION_SD,
5251         MULTI_FUNCTION_SI,
5252         MULTI_FUNCTION_AFEX,
5253         MAX_MF_MODE
5254 };
5255
5256 /*
5257  * Protocol-common statistics collected by the Tstorm (per pf)
5258  */
5259 struct tstorm_per_pf_stats {
5260         struct regpair rcv_error_bytes;
5261 };
5262
5263 /*
5264  *
5265  */
5266 struct per_pf_stats {
5267         struct tstorm_per_pf_stats tstorm_pf_statistics;
5268 };
5269
5270
5271 /*
5272  * Protocol-common statistics collected by the Tstorm (per port)
5273  */
5274 struct tstorm_per_port_stats {
5275         __le32 mac_discard;
5276         __le32 mac_filter_discard;
5277         __le32 brb_truncate_discard;
5278         __le32 mf_tag_discard;
5279         __le32 packet_drop;
5280         __le32 reserved;
5281 };
5282
5283 /*
5284  *
5285  */
5286 struct per_port_stats {
5287         struct tstorm_per_port_stats tstorm_port_statistics;
5288 };
5289
5290
5291 /*
5292  * Protocol-common statistics collected by the Tstorm (per client)
5293  */
5294 struct tstorm_per_queue_stats {
5295         struct regpair rcv_ucast_bytes;
5296         __le32 rcv_ucast_pkts;
5297         __le32 checksum_discard;
5298         struct regpair rcv_bcast_bytes;
5299         __le32 rcv_bcast_pkts;
5300         __le32 pkts_too_big_discard;
5301         struct regpair rcv_mcast_bytes;
5302         __le32 rcv_mcast_pkts;
5303         __le32 ttl0_discard;
5304         __le16 no_buff_discard;
5305         __le16 reserved0;
5306         __le32 reserved1;
5307 };
5308
5309 /*
5310  * Protocol-common statistics collected by the Ustorm (per client)
5311  */
5312 struct ustorm_per_queue_stats {
5313         struct regpair ucast_no_buff_bytes;
5314         struct regpair mcast_no_buff_bytes;
5315         struct regpair bcast_no_buff_bytes;
5316         __le32 ucast_no_buff_pkts;
5317         __le32 mcast_no_buff_pkts;
5318         __le32 bcast_no_buff_pkts;
5319         __le32 coalesced_pkts;
5320         struct regpair coalesced_bytes;
5321         __le32 coalesced_events;
5322         __le32 coalesced_aborts;
5323 };
5324
5325 /*
5326  * Protocol-common statistics collected by the Xstorm (per client)
5327  */
5328 struct xstorm_per_queue_stats {
5329         struct regpair ucast_bytes_sent;
5330         struct regpair mcast_bytes_sent;
5331         struct regpair bcast_bytes_sent;
5332         __le32 ucast_pkts_sent;
5333         __le32 mcast_pkts_sent;
5334         __le32 bcast_pkts_sent;
5335         __le32 error_drop_pkts;
5336 };
5337
5338 /*
5339  *
5340  */
5341 struct per_queue_stats {
5342         struct tstorm_per_queue_stats tstorm_queue_statistics;
5343         struct ustorm_per_queue_stats ustorm_queue_statistics;
5344         struct xstorm_per_queue_stats xstorm_queue_statistics;
5345 };
5346
5347
5348 /*
5349  * FW version stored in first line of pram
5350  */
5351 struct pram_fw_version {
5352         u8 major;
5353         u8 minor;
5354         u8 revision;
5355         u8 engineering;
5356         u8 flags;
5357 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5358 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5359 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5360 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5361 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5362 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5363 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5364 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5365 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5366 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5367 };
5368
5369
5370 /*
5371  * Ethernet slow path element
5372  */
5373 union protocol_common_specific_data {
5374         u8 protocol_data[8];
5375         struct regpair phy_address;
5376         struct regpair mac_config_addr;
5377         struct afex_vif_list_ramrod_data afex_vif_list_data;
5378 };
5379
5380 /*
5381  * The send queue element
5382  */
5383 struct protocol_common_spe {
5384         struct spe_hdr hdr;
5385         union protocol_common_specific_data data;
5386 };
5387
5388
5389 /*
5390  * The send queue element
5391  */
5392 struct slow_path_element {
5393         struct spe_hdr hdr;
5394         struct regpair protocol_data;
5395 };
5396
5397
5398 /*
5399  * Protocol-common statistics counter
5400  */
5401 struct stats_counter {
5402         __le16 xstats_counter;
5403         __le16 reserved0;
5404         __le32 reserved1;
5405         __le16 tstats_counter;
5406         __le16 reserved2;
5407         __le32 reserved3;
5408         __le16 ustats_counter;
5409         __le16 reserved4;
5410         __le32 reserved5;
5411         __le16 cstats_counter;
5412         __le16 reserved6;
5413         __le32 reserved7;
5414 };
5415
5416
5417 /*
5418  *
5419  */
5420 struct stats_query_entry {
5421         u8 kind;
5422         u8 index;
5423         __le16 funcID;
5424         __le32 reserved;
5425         struct regpair address;
5426 };
5427
5428 /*
5429  * statistic command
5430  */
5431 struct stats_query_cmd_group {
5432         struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5433 };
5434
5435
5436 /*
5437  * statistic command header
5438  */
5439 struct stats_query_header {
5440         u8 cmd_num;
5441         u8 reserved0;
5442         __le16 drv_stats_counter;
5443         __le32 reserved1;
5444         struct regpair stats_counters_addrs;
5445 };
5446
5447
5448 /*
5449  * Types of statistcis query entry
5450  */
5451 enum stats_query_type {
5452         STATS_TYPE_QUEUE,
5453         STATS_TYPE_PORT,
5454         STATS_TYPE_PF,
5455         STATS_TYPE_TOE,
5456         STATS_TYPE_FCOE,
5457         MAX_STATS_QUERY_TYPE
5458 };
5459
5460
5461 /*
5462  * Indicate of the function status block state
5463  */
5464 enum status_block_state {
5465         SB_DISABLED,
5466         SB_ENABLED,
5467         SB_CLEANED,
5468         MAX_STATUS_BLOCK_STATE
5469 };
5470
5471
5472 /*
5473  * Storm IDs (including attentions for IGU related enums)
5474  */
5475 enum storm_id {
5476         USTORM_ID,
5477         CSTORM_ID,
5478         XSTORM_ID,
5479         TSTORM_ID,
5480         ATTENTION_ID,
5481         MAX_STORM_ID
5482 };
5483
5484
5485 /*
5486  * Taffic types used in ETS and flow control algorithms
5487  */
5488 enum traffic_type {
5489         LLFC_TRAFFIC_TYPE_NW,
5490         LLFC_TRAFFIC_TYPE_FCOE,
5491         LLFC_TRAFFIC_TYPE_ISCSI,
5492         MAX_TRAFFIC_TYPE
5493 };
5494
5495
5496 /*
5497  * zone A per-queue data
5498  */
5499 struct tstorm_queue_zone_data {
5500         struct regpair reserved[4];
5501 };
5502
5503
5504 /*
5505  * zone B per-VF data
5506  */
5507 struct tstorm_vf_zone_data {
5508         struct regpair reserved;
5509 };
5510
5511
5512 /*
5513  * zone A per-queue data
5514  */
5515 struct ustorm_queue_zone_data {
5516         struct ustorm_eth_rx_producers eth_rx_producers;
5517         struct regpair reserved[3];
5518 };
5519
5520
5521 /*
5522  * zone B per-VF data
5523  */
5524 struct ustorm_vf_zone_data {
5525         struct regpair reserved;
5526 };
5527
5528
5529 /*
5530  * data per VF-PF channel
5531  */
5532 struct vf_pf_channel_data {
5533 #if defined(__BIG_ENDIAN)
5534         u16 reserved0;
5535         u8 valid;
5536         u8 state;
5537 #elif defined(__LITTLE_ENDIAN)
5538         u8 state;
5539         u8 valid;
5540         u16 reserved0;
5541 #endif
5542         u32 reserved1;
5543 };
5544
5545
5546 /*
5547  * State of VF-PF channel
5548  */
5549 enum vf_pf_channel_state {
5550         VF_PF_CHANNEL_STATE_READY,
5551         VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5552         MAX_VF_PF_CHANNEL_STATE
5553 };
5554
5555
5556 /*
5557  * vif_list_rule_kind
5558  */
5559 enum vif_list_rule_kind {
5560         VIF_LIST_RULE_SET,
5561         VIF_LIST_RULE_GET,
5562         VIF_LIST_RULE_CLEAR_ALL,
5563         VIF_LIST_RULE_CLEAR_FUNC,
5564         MAX_VIF_LIST_RULE_KIND
5565 };
5566
5567
5568 /*
5569  * zone A per-queue data
5570  */
5571 struct xstorm_queue_zone_data {
5572         struct regpair reserved[4];
5573 };
5574
5575
5576 /*
5577  * zone B per-VF data
5578  */
5579 struct xstorm_vf_zone_data {
5580         struct regpair reserved;
5581 };
5582
5583 #endif /* BNX2X_HSI_H */