1 /* bnx2x_init.h: Broadcom Everest network driver.
2 * Structures and macroes needed during the initialization.
4 * Copyright (c) 2007-2013 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
10 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
11 * Written by: Eliezer Tamir
12 * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
18 /* Init operation types and structures */
20 OP_RD = 0x1, /* read a single register */
21 OP_WR, /* write a single register */
22 OP_SW, /* copy a string to the device */
23 OP_ZR, /* clear memory */
24 OP_ZP, /* unzip then copy with DMAE */
25 OP_WR_64, /* write 64 bit pattern */
26 OP_WB, /* copy a string using DMAE */
27 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
28 /* Skip the following ops if all of the init modes don't match */
30 /* Skip the following ops if any of the init modes don't match */
40 /* Returns the index of start or end of a specific block stage in ops array*/
41 #define BLOCK_OPS_IDX(block, stage, end) \
42 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
45 /* structs for the various opcodes */
70 #else /* __LITTLE_ENDIAN */
91 struct op_write write;
92 struct op_arr_write arr_wr;
95 struct op_if_mode if_mode;
117 MODE_ASIC = 0x00000001,
118 MODE_FPGA = 0x00000002,
119 MODE_EMUL = 0x00000004,
120 MODE_E2 = 0x00000008,
121 MODE_E3 = 0x00000010,
122 MODE_PORT2 = 0x00000020,
123 MODE_PORT4 = 0x00000040,
124 MODE_SF = 0x00000080,
125 MODE_MF = 0x00000100,
126 MODE_MF_SD = 0x00000200,
127 MODE_MF_SI = 0x00000400,
128 MODE_MF_AFEX = 0x00000800,
129 MODE_E3_A0 = 0x00001000,
130 MODE_E3_B0 = 0x00002000,
131 MODE_COS3 = 0x00004000,
132 MODE_COS6 = 0x00008000,
133 MODE_LITTLE_ENDIAN = 0x00010000,
134 MODE_BIG_ENDIAN = 0x00020000,
176 /* QM queue numbers */
177 #define BNX2X_ETH_Q 0
178 #define BNX2X_TOE_Q 3
179 #define BNX2X_TOE_ACK_Q 6
180 #define BNX2X_ISCSI_Q 9
181 #define BNX2X_ISCSI_ACK_Q 11
182 #define BNX2X_FCOE_Q 10
185 #define BNX2X_PORT2_MODE_NUM_VNICS 4
186 #define BNX2X_PORT4_MODE_NUM_VNICS 2
188 /* COS offset for port1 in E3 B0 4port mode */
189 #define BNX2X_E3B0_PORT1_COS_OFFSET 3
191 /* QM Register addresses */
192 #define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
193 (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
194 #define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
195 (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
196 #define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
197 (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
199 /* extracts the QM queue number for the specified port and vnic */
200 #define BNX2X_PF_Q_NUM(q_num, port, vnic)\
201 ((((port) << 1) | (vnic)) * 16 + (q_num))
204 /* Maps the specified queue to the specified COS */
205 static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)
207 /* find current COS mapping */
208 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
210 /* check if queue->COS mapping has changed */
211 if (curr_cos != new_cos) {
212 u32 num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
213 u32 reg_addr, reg_bit_map, vnic;
215 /* update parameters for 4port mode */
216 if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
217 num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
219 curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
220 new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
224 /* change queue mapping for each VNIC */
225 for (vnic = 0; vnic < num_vnics; vnic++) {
227 BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
228 u32 q_bit_map = 1 << (pf_q_num & 0x1f);
230 /* overwrite queue->VOQ mapping */
231 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
233 /* clear queue bit from current COS bit map */
234 reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
235 reg_bit_map = REG_RD(bp, reg_addr);
236 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
238 /* set queue bit in new COS bit map */
239 reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
240 reg_bit_map = REG_RD(bp, reg_addr);
241 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
243 /* set/clear queue bit in command-queue bit map
244 * (E2/E3A0 only, valid COS values are 0/1)
246 if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
247 reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
248 reg_bit_map = REG_RD(bp, reg_addr);
249 q_bit_map = 1 << (2 * (pf_q_num & 0xf));
250 reg_bit_map = new_cos ?
251 (reg_bit_map | q_bit_map) :
252 (reg_bit_map & (~q_bit_map));
253 REG_WR(bp, reg_addr, reg_bit_map);
259 /* Configures the QM according to the specified per-traffic-type COSes */
260 static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,
261 struct priority_cos *traffic_cos)
263 bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
264 traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
265 bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
266 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
267 bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
268 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
269 if (mode != STATIC_COS) {
270 /* required only in backward compatible COS mode */
271 bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
272 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
273 bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
274 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
275 bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
276 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
281 /* congestion managment port init api description
282 * the api works as follows:
283 * the driver should pass the cmng_init_input struct, the port_init function
284 * will prepare the required internal ram structure which will be passed back
285 * to the driver (cmng_init) that will write it into the internal ram.
288 * 1. the cmng_init struct does not represent the contiguous internal ram
289 * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
290 * offset in order to write the port sub struct and the
291 * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
292 * words - don't use memcpy!).
293 * 2. although the cmng_init struct is filled for the maximal vnic number
294 * possible, the driver should only write the valid vnics into the internal
295 * ram according to the appropriate port mode.
297 #define BITS_TO_BYTES(x) ((x)/8)
299 /* CMNG constants, as derived from system spec calculations */
301 /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
302 #define DEF_MIN_RATE 100
304 /* resolution of the rate shaping timer - 400 usec */
305 #define RS_PERIODIC_TIMEOUT_USEC 400
307 /* number of bytes in single QM arbitration cycle -
308 * coefficient for calculating the fairness timer
310 #define QM_ARB_BYTES 160000
312 /* resolution of Min algorithm 1:100 */
315 /* how many bytes above threshold for
316 * the minimal credit of Min algorithm
318 #define MIN_ABOVE_THRESH 32768
320 /* Fairness algorithm integration time coefficient -
321 * for calculating the actual Tfair
323 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
325 /* Memory of fairness algorithm - 2 cycles */
327 #define SAFC_TIMEOUT_USEC 52
332 static inline void bnx2x_init_max(const struct cmng_init_input *input_data,
333 u32 r_param, struct cmng_init *ram_data)
336 struct cmng_vnic *vdata = &ram_data->vnic;
337 struct cmng_struct_per_port *pdata = &ram_data->port;
338 /* rate shaping per-port variables
339 * 100 micro seconds in SDM ticks = 25
340 * since each tick is 4 microSeconds
343 pdata->rs_vars.rs_periodic_timeout =
344 RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
346 /* this is the threshold below which no timer arming will occur.
347 * 1.25 coefficient is for the threshold to be a little bigger
348 * then the real time to compensate for timer in-accuracy
350 pdata->rs_vars.rs_threshold =
351 (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
353 /* rate shaping per-vnic variables */
354 for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
355 /* global vnic counter */
356 vdata->vnic_max_rate[vnic].vn_counter.rate =
357 input_data->vnic_max_rate[vnic];
358 /* maximal Mbps for this vnic
359 * the quota in each timer period - number of bytes
360 * transmitted in this period
362 vdata->vnic_max_rate[vnic].vn_counter.quota =
363 RS_PERIODIC_TIMEOUT_USEC *
364 (u32)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
369 static inline void bnx2x_init_min(const struct cmng_init_input *input_data,
370 u32 r_param, struct cmng_init *ram_data)
372 u32 vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
373 struct cmng_vnic *vdata = &ram_data->vnic;
374 struct cmng_struct_per_port *pdata = &ram_data->port;
376 /* this is the resolution of the fairness timer */
377 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
379 /* fairness per-port variables
380 * for 10G it is 1000usec. for 1G it is 10000usec.
382 tFair = T_FAIR_COEF / input_data->port_rate;
384 /* this is the threshold below which we won't arm the timer anymore */
385 pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
387 /* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
388 * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
390 pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
392 /* since each tick is 4 microSeconds */
393 pdata->fair_vars.fairness_timeout =
394 fair_periodic_timeout_usec / SDM_TICKS;
396 /* calculate sum of weights */
399 for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++)
400 vnicWeightSum += input_data->vnic_min_rate[vnic];
402 /* global vnic counter */
403 if (vnicWeightSum > 0) {
404 /* fairness per-vnic variables */
405 for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
406 /* this is the credit for each period of the fairness
407 * algorithm - number of bytes in T_FAIR (this vnic
408 * share of the port rate)
410 vdata->vnic_min_rate[vnic].vn_credit_delta =
411 (u32)input_data->vnic_min_rate[vnic] * 100 *
412 (T_FAIR_COEF / (8 * 100 * vnicWeightSum));
413 if (vdata->vnic_min_rate[vnic].vn_credit_delta <
414 pdata->fair_vars.fair_threshold +
416 vdata->vnic_min_rate[vnic].vn_credit_delta =
417 pdata->fair_vars.fair_threshold +
424 static inline void bnx2x_init_fw_wrr(const struct cmng_init_input *input_data,
425 u32 r_param, struct cmng_init *ram_data)
428 u32 cosWeightSum = 0;
429 struct cmng_vnic *vdata = &ram_data->vnic;
430 struct cmng_struct_per_port *pdata = &ram_data->port;
432 for (cos = 0; cos < MAX_COS_NUMBER; cos++)
433 cosWeightSum += input_data->cos_min_rate[cos];
435 if (cosWeightSum > 0) {
437 for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
438 /* Since cos and vnic shouldn't work together the rate
439 * to divide between the coses is the port rate.
441 u32 *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
442 for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
443 /* this is the credit for each period of
444 * the fairness algorithm - number of bytes
445 * in T_FAIR (this cos share of the vnic rate)
448 (u32)input_data->cos_min_rate[cos] * 100 *
449 (T_FAIR_COEF / (8 * 100 * cosWeightSum));
450 if (ccd[cos] < pdata->fair_vars.fair_threshold
451 + MIN_ABOVE_THRESH) {
453 pdata->fair_vars.fair_threshold +
461 static inline void bnx2x_init_safc(const struct cmng_init_input *input_data,
462 struct cmng_init *ram_data)
464 /* in microSeconds */
465 ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
468 /* Congestion management port init */
469 static inline void bnx2x_init_cmng(const struct cmng_init_input *input_data,
470 struct cmng_init *ram_data)
473 memset(ram_data, 0, sizeof(struct cmng_init));
475 ram_data->port.flags = input_data->flags;
477 /* number of bytes transmitted in a rate of 10Gbps
478 * in one usec = 1.25KB.
480 r_param = BITS_TO_BYTES(input_data->port_rate);
481 bnx2x_init_max(input_data, r_param, ram_data);
482 bnx2x_init_min(input_data, r_param, ram_data);
483 bnx2x_init_fw_wrr(input_data, r_param, ram_data);
484 bnx2x_init_safc(input_data, ram_data);
489 /* Returns the index of start or end of a specific block stage in ops array */
490 #define BLOCK_OPS_IDX(block, stage, end) \
491 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
494 #define INITOP_SET 0 /* set the HW directly */
495 #define INITOP_CLEAR 1 /* clear the HW directly */
496 #define INITOP_INIT 2 /* set the init-value array */
498 /****************************************************************************
500 ****************************************************************************/
502 dma_addr_t page_mapping;
507 struct ilt_client_info {
513 #define ILT_CLIENT_SKIP_INIT 0x1
514 #define ILT_CLIENT_SKIP_MEM 0x2
519 struct ilt_line *lines;
520 struct ilt_client_info clients[4];
521 #define ILT_CLIENT_CDU 0
522 #define ILT_CLIENT_QM 1
523 #define ILT_CLIENT_SRC 2
524 #define ILT_CLIENT_TM 3
527 /****************************************************************************
529 ****************************************************************************/
535 /****************************************************************************
536 * Parity configuration
537 ****************************************************************************/
538 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
540 block##_REG_##block##_PRTY_MASK, \
541 block##_REG_##block##_PRTY_STS_CLR, \
542 en_mask, {m1, m1h, m2, m3}, #block \
545 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
547 block##_REG_##block##_PRTY_MASK_0, \
548 block##_REG_##block##_PRTY_STS_CLR_0, \
549 en_mask, {m1, m1h, m2, m3}, #block"_0" \
552 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
554 block##_REG_##block##_PRTY_MASK_1, \
555 block##_REG_##block##_PRTY_STS_CLR_1, \
556 en_mask, {m1, m1h, m2, m3}, #block"_1" \
559 static const struct {
562 u32 en_mask; /* Mask to enable parity attentions */
568 } reg_mask; /* Register mask (all valid bits) */
569 char name[8]; /* Block's longest name is 7 characters long
572 } bnx2x_blocks_parity_data[] = {
574 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
576 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
578 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
579 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
580 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
582 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
583 * want to handle "system kill" flow at the moment.
585 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
587 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
589 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
590 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
591 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
592 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
593 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
594 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
595 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
596 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
597 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
598 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
599 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
600 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
601 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
602 {0xf, 0xf, 0xf, 0xf}, "UPB"},
603 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
604 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
605 {0xf, 0xf, 0xf, 0xf}, "XPB"},
606 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
607 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
608 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
609 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
610 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
611 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
612 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
613 BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
614 BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
615 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
616 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
617 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
618 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
619 BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
620 BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
621 BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
622 BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
623 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
625 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
626 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
628 BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
629 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
631 BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
632 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
634 BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
638 /* [28] MCP Latched rom_parity
639 * [29] MCP Latched ump_rx_parity
640 * [30] MCP Latched ump_tx_parity
641 * [31] MCP Latched scpad_parity
643 #define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
644 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
645 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
646 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
648 #define MISC_AEU_ENABLE_MCP_PRTY_BITS \
649 (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
650 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
652 /* Below registers control the MCP parity attention output. When
653 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
654 * enabled, when cleared - disabled.
656 static const struct {
659 } mcp_attn_ctl_regs[] = {
660 { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
661 MISC_AEU_ENABLE_MCP_PRTY_BITS },
662 { MISC_REG_AEU_ENABLE4_NIG_0,
663 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
664 { MISC_REG_AEU_ENABLE4_PXP_0,
665 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
666 { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
667 MISC_AEU_ENABLE_MCP_PRTY_BITS },
668 { MISC_REG_AEU_ENABLE4_NIG_1,
669 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
670 { MISC_REG_AEU_ENABLE4_PXP_1,
671 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
674 static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
679 for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
680 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
683 reg_val |= mcp_attn_ctl_regs[i].bits;
685 reg_val &= ~mcp_attn_ctl_regs[i].bits;
687 REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
691 static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
694 return bnx2x_blocks_parity_data[idx].reg_mask.e1;
695 else if (CHIP_IS_E1H(bp))
696 return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
697 else if (CHIP_IS_E2(bp))
698 return bnx2x_blocks_parity_data[idx].reg_mask.e2;
699 else /* CHIP_IS_E3 */
700 return bnx2x_blocks_parity_data[idx].reg_mask.e3;
703 static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
707 for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
708 u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
711 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
713 DP(NETIF_MSG_HW, "Setting parity mask "
714 "for %s to\t\t0x%x\n",
715 bnx2x_blocks_parity_data[i].name, dis_mask);
719 /* Disable MCP parity attentions */
720 bnx2x_set_mcp_parity(bp, false);
723 /* Clear the parity error status registers. */
724 static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
727 u32 reg_val, mcp_aeu_bits =
728 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
729 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
730 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
731 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
733 /* Clear SEM_FAST parities */
734 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
735 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
736 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
737 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
739 for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
740 u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
743 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
745 if (reg_val & reg_mask)
747 "Parity errors in %s: 0x%x\n",
748 bnx2x_blocks_parity_data[i].name,
753 /* Check if there were parity attentions in MCP */
754 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
755 if (reg_val & mcp_aeu_bits)
756 DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
757 reg_val & mcp_aeu_bits);
759 /* Clear parity attentions in MCP:
760 * [7] clears Latched rom_parity
761 * [8] clears Latched ump_rx_parity
762 * [9] clears Latched ump_tx_parity
763 * [10] clears Latched scpad_parity (both ports)
765 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
768 static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
772 for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
773 u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
776 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
777 bnx2x_blocks_parity_data[i].en_mask & reg_mask);
780 /* Enable MCP parity attentions */
781 bnx2x_set_mcp_parity(bp, true);
785 #endif /* BNX2X_INIT_H */