drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 158         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 159         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 160
 161
 162 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 163         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 164         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 165         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 166
 167 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 168         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 169         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 170
 171 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 172         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 173 #define SFP_EEPROM_OPTIONS_SIZE                 2
 174
 175 #define EDC_MODE_LINEAR                         0x0022
 176 #define EDC_MODE_LIMITING                               0x0044
 177 #define EDC_MODE_PASSIVE_DAC                    0x0055
 178
 179 /* ETS defines*/
 180 #define DCBX_INVALID_COS                                        (0xFF)
 181
 182 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 183 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 184 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 185 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 186 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 187
 188 #define MAX_PACKET_SIZE                                 (9700)
 189 #define MAX_KR_LINK_RETRY                               4
 190
 191 /**********************************************************/
 192 /*                     INTERFACE                          */
 193 /**********************************************************/
 194
 195 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 196         bnx2x_cl45_write(_bp, _phy, \
 197                 (_phy)->def_md_devad, \
 198                 (_bank + (_addr & 0xf)), \
 199                 _val)
 200
 201 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 202         bnx2x_cl45_read(_bp, _phy, \
 203                 (_phy)->def_md_devad, \
 204                 (_bank + (_addr & 0xf)), \
 205                 _val)
 206
 207 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 208 {
 209         u32 val = REG_RD(bp, reg);
 210
 211         val |= bits;
 212         REG_WR(bp, reg, val);
 213         return val;
 214 }
 215
 216 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 217 {
 218         u32 val = REG_RD(bp, reg);
 219
 220         val &= ~bits;
 221         REG_WR(bp, reg, val);
 222         return val;
 223 }
 224
 225 /*
 226  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 227  *                   or link flap can be avoided.
 228  *
 229  * @params:     link parameters
 230  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 231  *         condition code.
 232  */
 233 static int bnx2x_check_lfa(struct link_params *params)
 234 {
 235         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 236         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 237         u32 saved_val, req_val, eee_status;
 238         struct bnx2x *bp = params->bp;
 239
 240         additional_config =
 241                 REG_RD(bp, params->lfa_base +
 242                            offsetof(struct shmem_lfa, additional_config));
 243
 244         /* NOTE: must be first condition checked -
 245         * to verify DCC bit is cleared in any case!
 246         */
 247         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 248                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 249                 REG_WR(bp, params->lfa_base +
 250                            offsetof(struct shmem_lfa, additional_config),
 251                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 252                 return LFA_DCC_LFA_DISABLED;
 253         }
 254
 255         /* Verify that link is up */
 256         link_status = REG_RD(bp, params->shmem_base +
 257                              offsetof(struct shmem_region,
 258                                       port_mb[params->port].link_status));
 259         if (!(link_status & LINK_STATUS_LINK_UP))
 260                 return LFA_LINK_DOWN;
 261
 262         /* if loaded after BOOT from SAN, don't flap the link in any case and
 263          * rely on link set by preboot driver
 264          */
 265         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 266                 return 0;
 267
 268         /* Verify that loopback mode is not set */
 269         if (params->loopback_mode)
 270                 return LFA_LOOPBACK_ENABLED;
 271
 272         /* Verify that MFW supports LFA */
 273         if (!params->lfa_base)
 274                 return LFA_MFW_IS_TOO_OLD;
 275
 276         if (params->num_phys == 3) {
 277                 cfg_size = 2;
 278                 lfa_mask = 0xffffffff;
 279         } else {
 280                 cfg_size = 1;
 281                 lfa_mask = 0xffff;
 282         }
 283
 284         /* Compare Duplex */
 285         saved_val = REG_RD(bp, params->lfa_base +
 286                            offsetof(struct shmem_lfa, req_duplex));
 287         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 288         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 289                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 290                                (saved_val & lfa_mask), (req_val & lfa_mask));
 291                 return LFA_DUPLEX_MISMATCH;
 292         }
 293         /* Compare Flow Control */
 294         saved_val = REG_RD(bp, params->lfa_base +
 295                            offsetof(struct shmem_lfa, req_flow_ctrl));
 296         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 297         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 298                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 299                                (saved_val & lfa_mask), (req_val & lfa_mask));
 300                 return LFA_FLOW_CTRL_MISMATCH;
 301         }
 302         /* Compare Link Speed */
 303         saved_val = REG_RD(bp, params->lfa_base +
 304                            offsetof(struct shmem_lfa, req_line_speed));
 305         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 306         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 307                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 308                                (saved_val & lfa_mask), (req_val & lfa_mask));
 309                 return LFA_LINK_SPEED_MISMATCH;
 310         }
 311
 312         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 313                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 314                                             offsetof(struct shmem_lfa,
 315                                                      speed_cap_mask[cfg_idx]));
 316
 317                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 318                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 319                                        cur_speed_cap_mask,
 320                                        params->speed_cap_mask[cfg_idx]);
 321                         return LFA_SPEED_CAP_MISMATCH;
 322                 }
 323         }
 324
 325         cur_req_fc_auto_adv =
 326                 REG_RD(bp, params->lfa_base +
 327                        offsetof(struct shmem_lfa, additional_config)) &
 328                 REQ_FC_AUTO_ADV_MASK;
 329
 330         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 331                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 332                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 333                 return LFA_FLOW_CTRL_MISMATCH;
 334         }
 335
 336         eee_status = REG_RD(bp, params->shmem2_base +
 337                             offsetof(struct shmem2_region,
 338                                      eee_status[params->port]));
 339
 340         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 341              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 342             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 343              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 344                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 345                                eee_status);
 346                 return LFA_EEE_MISMATCH;
 347         }
 348
 349         /* LFA conditions are met */
 350         return 0;
 351 }
 352 /******************************************************************/
 353 /*                      EPIO/GPIO section                         */
 354 /******************************************************************/
 355 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 356 {
 357         u32 epio_mask, gp_oenable;
 358         *en = 0;
 359         /* Sanity check */
 360         if (epio_pin > 31) {
 361                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 362                 return;
 363         }
 364
 365         epio_mask = 1 << epio_pin;
 366         /* Set this EPIO to output */
 367         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 368         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 369
 370         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 371 }
 372 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 373 {
 374         u32 epio_mask, gp_output, gp_oenable;
 375
 376         /* Sanity check */
 377         if (epio_pin > 31) {
 378                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 379                 return;
 380         }
 381         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 382         epio_mask = 1 << epio_pin;
 383         /* Set this EPIO to output */
 384         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 385         if (en)
 386                 gp_output |= epio_mask;
 387         else
 388                 gp_output &= ~epio_mask;
 389
 390         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 391
 392         /* Set the value for this EPIO */
 393         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 394         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 395 }
 396
 397 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 398 {
 399         if (pin_cfg == PIN_CFG_NA)
 400                 return;
 401         if (pin_cfg >= PIN_CFG_EPIO0) {
 402                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 403         } else {
 404                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 405                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 406                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 407         }
 408 }
 409
 410 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 411 {
 412         if (pin_cfg == PIN_CFG_NA)
 413                 return -EINVAL;
 414         if (pin_cfg >= PIN_CFG_EPIO0) {
 415                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 416         } else {
 417                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 418                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 419                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 420         }
 421         return 0;
 422
 423 }
 424 /******************************************************************/
 425 /*                              ETS section                       */
 426 /******************************************************************/
 427 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 428 {
 429         /* ETS disabled configuration*/
 430         struct bnx2x *bp = params->bp;
 431
 432         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 433
 434         /* mapping between entry  priority to client number (0,1,2 -debug and
 435          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 436          * 3bits client num.
 437          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 438          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 439          */
 440
 441         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 442         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 443          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 444          * COS0 entry, 4 - COS1 entry.
 445          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 446          * bit4   bit3    bit2   bit1     bit0
 447          * MCP and debug are strict
 448          */
 449
 450         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 451         /* defines which entries (clients) are subjected to WFQ arbitration */
 452         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 453         /* For strict priority entries defines the number of consecutive
 454          * slots for the highest priority.
 455          */
 456         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 457         /* mapping between the CREDIT_WEIGHT registers and actual client
 458          * numbers
 459          */
 460         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 461         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 462         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 463
 464         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 466         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 467         /* ETS mode disable */
 468         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 469         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 470          * weight for COS0/COS1.
 471          */
 472         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 473         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 474         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 475         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 476         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 477         /* Defines the number of consecutive slots for the strict priority */
 478         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 479 }
 480 /******************************************************************************
 481 * Description:
 482 *       Getting min_w_val will be set according to line speed .
 483 *.
 484 ******************************************************************************/
 485 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 486 {
 487         u32 min_w_val = 0;
 488         /* Calculate min_w_val.*/
 489         if (vars->link_up) {
 490                 if (vars->line_speed == SPEED_20000)
 491                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 492                 else
 493                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 494         } else
 495                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 496         /* If the link isn't up (static configuration for example ) The
 497          * link will be according to 20GBPS.
 498          */
 499         return min_w_val;
 500 }
 501 /******************************************************************************
 502 * Description:
 503 *       Getting credit upper bound form min_w_val.
 504 *.
 505 ******************************************************************************/
 506 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 507 {
 508         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 509                                                 MAX_PACKET_SIZE);
 510         return credit_upper_bound;
 511 }
 512 /******************************************************************************
 513 * Description:
 514 *       Set credit upper bound for NIG.
 515 *.
 516 ******************************************************************************/
 517 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 518         const struct link_params *params,
 519         const u32 min_w_val)
 520 {
 521         struct bnx2x *bp = params->bp;
 522         const u8 port = params->port;
 523         const u32 credit_upper_bound =
 524             bnx2x_ets_get_credit_upper_bound(min_w_val);
 525
 526         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 527                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 528         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 529                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 531                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 532         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 533                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 534         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 535                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 536         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 537                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 538
 539         if (!port) {
 540                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 541                         credit_upper_bound);
 542                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 543                         credit_upper_bound);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 545                         credit_upper_bound);
 546         }
 547 }
 548 /******************************************************************************
 549 * Description:
 550 *       Will return the NIG ETS registers to init values.Except
 551 *       credit_upper_bound.
 552 *       That isn't used in this configuration (No WFQ is enabled) and will be
 553 *       configured acording to spec
 554 *.
 555 ******************************************************************************/
 556 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 557                                         const struct link_vars *vars)
 558 {
 559         struct bnx2x *bp = params->bp;
 560         const u8 port = params->port;
 561         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 562         /* Mapping between entry  priority to client number (0,1,2 -debug and
 563          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 564          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 565          * reset value or init tool
 566          */
 567         if (port) {
 568                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 570         } else {
 571                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 573         }
 574         /* For strict priority entries defines the number of consecutive
 575          * slots for the highest priority.
 576          */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 578                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 579         /* Mapping between the CREDIT_WEIGHT registers and actual client
 580          * numbers
 581          */
 582         if (port) {
 583                 /*Port 1 has 6 COS*/
 584                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 586         } else {
 587                 /*Port 0 has 9 COS*/
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 589                        0x43210876);
 590                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 591         }
 592
 593         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 594          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 595          * COS0 entry, 4 - COS1 entry.
 596          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 597          * bit4   bit3    bit2   bit1     bit0
 598          * MCP and debug are strict
 599          */
 600         if (port)
 601                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 602         else
 603                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 604         /* defines which entries (clients) are subjected to WFQ arbitration */
 605         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 606                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 607
 608         /* Please notice the register address are note continuous and a
 609          * for here is note appropriate.In 2 port mode port0 only COS0-5
 610          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 611          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 612          * are never used for WFQ
 613          */
 614         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 615                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 616         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 617                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 618         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 619                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 620         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 621                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 622         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 623                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 624         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 625                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 626         if (!port) {
 627                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 628                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 629                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 630         }
 631
 632         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 633 }
 634 /******************************************************************************
 635 * Description:
 636 *       Set credit upper bound for PBF.
 637 *.
 638 ******************************************************************************/
 639 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 640         const struct link_params *params,
 641         const u32 min_w_val)
 642 {
 643         struct bnx2x *bp = params->bp;
 644         const u32 credit_upper_bound =
 645             bnx2x_ets_get_credit_upper_bound(min_w_val);
 646         const u8 port = params->port;
 647         u32 base_upper_bound = 0;
 648         u8 max_cos = 0;
 649         u8 i = 0;
 650         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 651          * port mode port1 has COS0-2 that can be used for WFQ.
 652          */
 653         if (!port) {
 654                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 655                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 656         } else {
 657                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 658                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 659         }
 660
 661         for (i = 0; i < max_cos; i++)
 662                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 663 }
 664
 665 /******************************************************************************
 666 * Description:
 667 *       Will return the PBF ETS registers to init values.Except
 668 *       credit_upper_bound.
 669 *       That isn't used in this configuration (No WFQ is enabled) and will be
 670 *       configured acording to spec
 671 *.
 672 ******************************************************************************/
 673 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 674 {
 675         struct bnx2x *bp = params->bp;
 676         const u8 port = params->port;
 677         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 678         u8 i = 0;
 679         u32 base_weight = 0;
 680         u8 max_cos = 0;
 681
 682         /* Mapping between entry  priority to client number 0 - COS0
 683          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 684          * TODO_ETS - Should be done by reset value or init tool
 685          */
 686         if (port)
 687                 /*  0x688 (|011|0 10|00 1|000) */
 688                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 689         else
 690                 /*  (10 1|100 |011|0 10|00 1|000) */
 691                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 692
 693         /* TODO_ETS - Should be done by reset value or init tool */
 694         if (port)
 695                 /* 0x688 (|011|0 10|00 1|000)*/
 696                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 697         else
 698         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 699         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 700
 701         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 702                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 703
 704
 705         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 706                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 707
 708         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 709                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 710         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 711          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 712          */
 713         if (!port) {
 714                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 715                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 716         } else {
 717                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 718                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 719         }
 720
 721         for (i = 0; i < max_cos; i++)
 722                 REG_WR(bp, base_weight + (0x4 * i), 0);
 723
 724         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 725 }
 726 /******************************************************************************
 727 * Description:
 728 *       E3B0 disable will return basicly the values to init values.
 729 *.
 730 ******************************************************************************/
 731 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 732                                    const struct link_vars *vars)
 733 {
 734         struct bnx2x *bp = params->bp;
 735
 736         if (!CHIP_IS_E3B0(bp)) {
 737                 DP(NETIF_MSG_LINK,
 738                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 739                 return -EINVAL;
 740         }
 741
 742         bnx2x_ets_e3b0_nig_disabled(params, vars);
 743
 744         bnx2x_ets_e3b0_pbf_disabled(params);
 745
 746         return 0;
 747 }
 748
 749 /******************************************************************************
 750 * Description:
 751 *       Disable will return basicly the values to init values.
 752 *
 753 ******************************************************************************/
 754 int bnx2x_ets_disabled(struct link_params *params,
 755                       struct link_vars *vars)
 756 {
 757         struct bnx2x *bp = params->bp;
 758         int bnx2x_status = 0;
 759
 760         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 761                 bnx2x_ets_e2e3a0_disabled(params);
 762         else if (CHIP_IS_E3B0(bp))
 763                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 764         else {
 765                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 766                 return -EINVAL;
 767         }
 768
 769         return bnx2x_status;
 770 }
 771
 772 /******************************************************************************
 773 * Description
 774 *       Set the COS mappimg to SP and BW until this point all the COS are not
 775 *       set as SP or BW.
 776 ******************************************************************************/
 777 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 778                                   const struct bnx2x_ets_params *ets_params,
 779                                   const u8 cos_sp_bitmap,
 780                                   const u8 cos_bw_bitmap)
 781 {
 782         struct bnx2x *bp = params->bp;
 783         const u8 port = params->port;
 784         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 785         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 786         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 787         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 788
 789         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 790                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 791
 792         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 793                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 794
 795         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 796                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 797                nig_cli_subject2wfq_bitmap);
 798
 799         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 800                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 801                pbf_cli_subject2wfq_bitmap);
 802
 803         return 0;
 804 }
 805
 806 /******************************************************************************
 807 * Description:
 808 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 809 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 810 ******************************************************************************/
 811 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 812                                      const u8 cos_entry,
 813                                      const u32 min_w_val_nig,
 814                                      const u32 min_w_val_pbf,
 815                                      const u16 total_bw,
 816                                      const u8 bw,
 817                                      const u8 port)
 818 {
 819         u32 nig_reg_adress_crd_weight = 0;
 820         u32 pbf_reg_adress_crd_weight = 0;
 821         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 822         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 823         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 824
 825         switch (cos_entry) {
 826         case 0:
 827             nig_reg_adress_crd_weight =
 828                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 829                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 830              pbf_reg_adress_crd_weight = (port) ?
 831                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 832              break;
 833         case 1:
 834              nig_reg_adress_crd_weight = (port) ?
 835                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 836                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 837              pbf_reg_adress_crd_weight = (port) ?
 838                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 839              break;
 840         case 2:
 841              nig_reg_adress_crd_weight = (port) ?
 842                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 843                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 844
 845                  pbf_reg_adress_crd_weight = (port) ?
 846                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 847              break;
 848         case 3:
 849             if (port)
 850                         return -EINVAL;
 851              nig_reg_adress_crd_weight =
 852                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 853              pbf_reg_adress_crd_weight =
 854                  PBF_REG_COS3_WEIGHT_P0;
 855              break;
 856         case 4:
 857             if (port)
 858                 return -EINVAL;
 859              nig_reg_adress_crd_weight =
 860                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 861              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 862              break;
 863         case 5:
 864             if (port)
 865                 return -EINVAL;
 866              nig_reg_adress_crd_weight =
 867                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 868              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 869              break;
 870         }
 871
 872         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 873
 874         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 875
 876         return 0;
 877 }
 878 /******************************************************************************
 879 * Description:
 880 *       Calculate the total BW.A value of 0 isn't legal.
 881 *
 882 ******************************************************************************/
 883 static int bnx2x_ets_e3b0_get_total_bw(
 884         const struct link_params *params,
 885         struct bnx2x_ets_params *ets_params,
 886         u16 *total_bw)
 887 {
 888         struct bnx2x *bp = params->bp;
 889         u8 cos_idx = 0;
 890         u8 is_bw_cos_exist = 0;
 891
 892         *total_bw = 0 ;
 893         /* Calculate total BW requested */
 894         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 895                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 896                         is_bw_cos_exist = 1;
 897                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 898                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 899                                                    "was set to 0\n");
 900                                 /* This is to prevent a state when ramrods
 901                                  * can't be sent
 902                                  */
 903                                 ets_params->cos[cos_idx].params.bw_params.bw
 904                                          = 1;
 905                         }
 906                         *total_bw +=
 907                                 ets_params->cos[cos_idx].params.bw_params.bw;
 908                 }
 909         }
 910
 911         /* Check total BW is valid */
 912         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 913                 if (*total_bw == 0) {
 914                         DP(NETIF_MSG_LINK,
 915                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 916                         return -EINVAL;
 917                 }
 918                 DP(NETIF_MSG_LINK,
 919                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 920                 /* We can handle a case whre the BW isn't 100 this can happen
 921                  * if the TC are joined.
 922                  */
 923         }
 924         return 0;
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Invalidate all the sp_pri_to_cos.
 930 *
 931 ******************************************************************************/
 932 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 933 {
 934         u8 pri = 0;
 935         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 936                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 937 }
 938 /******************************************************************************
 939 * Description:
 940 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 941 *       according to sp_pri_to_cos.
 942 *
 943 ******************************************************************************/
 944 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 945                                             u8 *sp_pri_to_cos, const u8 pri,
 946                                             const u8 cos_entry)
 947 {
 948         struct bnx2x *bp = params->bp;
 949         const u8 port = params->port;
 950         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 951                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 952
 953         if (pri >= max_num_of_cos) {
 954                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 955                    "parameter Illegal strict priority\n");
 956             return -EINVAL;
 957         }
 958
 959         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 960                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 961                                    "parameter There can't be two COS's with "
 962                                    "the same strict pri\n");
 963                 return -EINVAL;
 964         }
 965
 966         sp_pri_to_cos[pri] = cos_entry;
 967         return 0;
 968
 969 }
 970
 971 /******************************************************************************
 972 * Description:
 973 *       Returns the correct value according to COS and priority in
 974 *       the sp_pri_cli register.
 975 *
 976 ******************************************************************************/
 977 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 978                                          const u8 pri_set,
 979                                          const u8 pri_offset,
 980                                          const u8 entry_size)
 981 {
 982         u64 pri_cli_nig = 0;
 983         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 984                                                     (pri_set + pri_offset));
 985
 986         return pri_cli_nig;
 987 }
 988 /******************************************************************************
 989 * Description:
 990 *       Returns the correct value according to COS and priority in the
 991 *       sp_pri_cli register for NIG.
 992 *
 993 ******************************************************************************/
 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 995 {
 996         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 997         const u8 nig_cos_offset = 3;
 998         const u8 nig_pri_offset = 3;
 999
1000         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1001                 nig_pri_offset, 4);
1002
1003 }
1004 /******************************************************************************
1005 * Description:
1006 *       Returns the correct value according to COS and priority in the
1007 *       sp_pri_cli register for PBF.
1008 *
1009 ******************************************************************************/
1010 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1011 {
1012         const u8 pbf_cos_offset = 0;
1013         const u8 pbf_pri_offset = 0;
1014
1015         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1016                 pbf_pri_offset, 3);
1017
1018 }
1019
1020 /******************************************************************************
1021 * Description:
1022 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1023 *       according to sp_pri_to_cos.(which COS has higher priority)
1024 *
1025 ******************************************************************************/
1026 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1027                                              u8 *sp_pri_to_cos)
1028 {
1029         struct bnx2x *bp = params->bp;
1030         u8 i = 0;
1031         const u8 port = params->port;
1032         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1033         u64 pri_cli_nig = 0x210;
1034         u32 pri_cli_pbf = 0x0;
1035         u8 pri_set = 0;
1036         u8 pri_bitmask = 0;
1037         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1038                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1039
1040         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1041
1042         /* Set all the strict priority first */
1043         for (i = 0; i < max_num_of_cos; i++) {
1044                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1045                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1046                                 DP(NETIF_MSG_LINK,
1047                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1048                                            "invalid cos entry\n");
1049                                 return -EINVAL;
1050                         }
1051
1052                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1053                             sp_pri_to_cos[i], pri_set);
1054
1055                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1056                             sp_pri_to_cos[i], pri_set);
1057                         pri_bitmask = 1 << sp_pri_to_cos[i];
1058                         /* COS is used remove it from bitmap.*/
1059                         if (!(pri_bitmask & cos_bit_to_set)) {
1060                                 DP(NETIF_MSG_LINK,
1061                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1062                                         "invalid There can't be two COS's with"
1063                                         " the same strict pri\n");
1064                                 return -EINVAL;
1065                         }
1066                         cos_bit_to_set &= ~pri_bitmask;
1067                         pri_set++;
1068                 }
1069         }
1070
1071         /* Set all the Non strict priority i= COS*/
1072         for (i = 0; i < max_num_of_cos; i++) {
1073                 pri_bitmask = 1 << i;
1074                 /* Check if COS was already used for SP */
1075                 if (pri_bitmask & cos_bit_to_set) {
1076                         /* COS wasn't used for SP */
1077                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1078                             i, pri_set);
1079
1080                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1081                             i, pri_set);
1082                         /* COS is used remove it from bitmap.*/
1083                         cos_bit_to_set &= ~pri_bitmask;
1084                         pri_set++;
1085                 }
1086         }
1087
1088         if (pri_set != max_num_of_cos) {
1089                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1090                                    "entries were set\n");
1091                 return -EINVAL;
1092         }
1093
1094         if (port) {
1095                 /* Only 6 usable clients*/
1096                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1097                        (u32)pri_cli_nig);
1098
1099                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1100         } else {
1101                 /* Only 9 usable clients*/
1102                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1103                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1104
1105                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1106                        pri_cli_nig_lsb);
1107                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1108                        pri_cli_nig_msb);
1109
1110                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1111         }
1112         return 0;
1113 }
1114
1115 /******************************************************************************
1116 * Description:
1117 *       Configure the COS to ETS according to BW and SP settings.
1118 ******************************************************************************/
1119 int bnx2x_ets_e3b0_config(const struct link_params *params,
1120                          const struct link_vars *vars,
1121                          struct bnx2x_ets_params *ets_params)
1122 {
1123         struct bnx2x *bp = params->bp;
1124         int bnx2x_status = 0;
1125         const u8 port = params->port;
1126         u16 total_bw = 0;
1127         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1128         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1129         u8 cos_bw_bitmap = 0;
1130         u8 cos_sp_bitmap = 0;
1131         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1132         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1133                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1134         u8 cos_entry = 0;
1135
1136         if (!CHIP_IS_E3B0(bp)) {
1137                 DP(NETIF_MSG_LINK,
1138                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1139                 return -EINVAL;
1140         }
1141
1142         if ((ets_params->num_of_cos > max_num_of_cos)) {
1143                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1144                                    "isn't supported\n");
1145                 return -EINVAL;
1146         }
1147
1148         /* Prepare sp strict priority parameters*/
1149         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1150
1151         /* Prepare BW parameters*/
1152         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1153                                                    &total_bw);
1154         if (bnx2x_status) {
1155                 DP(NETIF_MSG_LINK,
1156                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1157                 return -EINVAL;
1158         }
1159
1160         /* Upper bound is set according to current link speed (min_w_val
1161          * should be the same for upper bound and COS credit val).
1162          */
1163         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1164         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1165
1166
1167         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1168                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1169                         cos_bw_bitmap |= (1 << cos_entry);
1170                         /* The function also sets the BW in HW(not the mappin
1171                          * yet)
1172                          */
1173                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1174                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1175                                 total_bw,
1176                                 ets_params->cos[cos_entry].params.bw_params.bw,
1177                                  port);
1178                 } else if (bnx2x_cos_state_strict ==
1179                         ets_params->cos[cos_entry].state){
1180                         cos_sp_bitmap |= (1 << cos_entry);
1181
1182                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1183                                 params,
1184                                 sp_pri_to_cos,
1185                                 ets_params->cos[cos_entry].params.sp_params.pri,
1186                                 cos_entry);
1187
1188                 } else {
1189                         DP(NETIF_MSG_LINK,
1190                            "bnx2x_ets_e3b0_config cos state not valid\n");
1191                         return -EINVAL;
1192                 }
1193                 if (bnx2x_status) {
1194                         DP(NETIF_MSG_LINK,
1195                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1196                         return bnx2x_status;
1197                 }
1198         }
1199
1200         /* Set SP register (which COS has higher priority) */
1201         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1202                                                          sp_pri_to_cos);
1203
1204         if (bnx2x_status) {
1205                 DP(NETIF_MSG_LINK,
1206                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1207                 return bnx2x_status;
1208         }
1209
1210         /* Set client mapping of BW and strict */
1211         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1212                                               cos_sp_bitmap,
1213                                               cos_bw_bitmap);
1214
1215         if (bnx2x_status) {
1216                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1217                 return bnx2x_status;
1218         }
1219         return 0;
1220 }
1221 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1222 {
1223         /* ETS disabled configuration */
1224         struct bnx2x *bp = params->bp;
1225         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1226         /* Defines which entries (clients) are subjected to WFQ arbitration
1227          * COS0 0x8
1228          * COS1 0x10
1229          */
1230         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1231         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1232          * client numbers (WEIGHT_0 does not actually have to represent
1233          * client 0)
1234          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1235          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1236          */
1237         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1238
1239         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1240                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1241         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1242                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1243
1244         /* ETS mode enabled*/
1245         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1246
1247         /* Defines the number of consecutive slots for the strict priority */
1248         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1249         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1250          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1251          * entry, 4 - COS1 entry.
1252          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1253          * bit4   bit3    bit2     bit1    bit0
1254          * MCP and debug are strict
1255          */
1256         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1257
1258         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1259         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1260                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1262                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1263 }
1264
1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1266                         const u32 cos1_bw)
1267 {
1268         /* ETS disabled configuration*/
1269         struct bnx2x *bp = params->bp;
1270         const u32 total_bw = cos0_bw + cos1_bw;
1271         u32 cos0_credit_weight = 0;
1272         u32 cos1_credit_weight = 0;
1273
1274         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1275
1276         if ((!total_bw) ||
1277             (!cos0_bw) ||
1278             (!cos1_bw)) {
1279                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1280                 return;
1281         }
1282
1283         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1284                 total_bw;
1285         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1286                 total_bw;
1287
1288         bnx2x_ets_bw_limit_common(params);
1289
1290         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1292
1293         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1294         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1295 }
1296
1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1298 {
1299         /* ETS disabled configuration*/
1300         struct bnx2x *bp = params->bp;
1301         u32 val = 0;
1302
1303         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1304         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1305          * as strict.  Bits 0,1,2 - debug and management entries,
1306          * 3 - COS0 entry, 4 - COS1 entry.
1307          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1308          *  bit4   bit3   bit2      bit1     bit0
1309          * MCP and debug are strict
1310          */
1311         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1312         /* For strict priority entries defines the number of consecutive slots
1313          * for the highest priority.
1314          */
1315         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1316         /* ETS mode disable */
1317         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1318         /* Defines the number of consecutive slots for the strict priority */
1319         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1320
1321         /* Defines the number of consecutive slots for the strict priority */
1322         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1323
1324         /* Mapping between entry  priority to client number (0,1,2 -debug and
1325          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326          * 3bits client num.
1327          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1328          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1329          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1330          */
1331         val = (!strict_cos) ? 0x2318 : 0x22E0;
1332         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1333
1334         return 0;
1335 }
1336
1337 /******************************************************************/
1338 /*                      PFC section                               */
1339 /******************************************************************/
1340 static void bnx2x_update_pfc_xmac(struct link_params *params,
1341                                   struct link_vars *vars,
1342                                   u8 is_lb)
1343 {
1344         struct bnx2x *bp = params->bp;
1345         u32 xmac_base;
1346         u32 pause_val, pfc0_val, pfc1_val;
1347
1348         /* XMAC base adrr */
1349         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1350
1351         /* Initialize pause and pfc registers */
1352         pause_val = 0x18000;
1353         pfc0_val = 0xFFFF8000;
1354         pfc1_val = 0x2;
1355
1356         /* No PFC support */
1357         if (!(params->feature_config_flags &
1358               FEATURE_CONFIG_PFC_ENABLED)) {
1359
1360                 /* RX flow control - Process pause frame in receive direction
1361                  */
1362                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364
1365                 /* TX flow control - Send pause packet when buffer is full */
1366                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1367                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1368         } else {/* PFC support */
1369                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1370                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1371                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1372                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1373                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374                 /* Write pause and PFC registers */
1375                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1376                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1377                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1378                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1379
1380         }
1381
1382         /* Write pause and PFC registers */
1383         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1384         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1385         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1386
1387
1388         /* Set MAC address for source TX Pause/PFC frames */
1389         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1390                ((params->mac_addr[2] << 24) |
1391                 (params->mac_addr[3] << 16) |
1392                 (params->mac_addr[4] << 8) |
1393                 (params->mac_addr[5])));
1394         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1395                ((params->mac_addr[0] << 8) |
1396                 (params->mac_addr[1])));
1397
1398         udelay(30);
1399 }
1400
1401
1402 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1403                                     u32 pfc_frames_sent[2],
1404                                     u32 pfc_frames_received[2])
1405 {
1406         /* Read pfc statistic */
1407         struct bnx2x *bp = params->bp;
1408         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1409         u32 val_xon = 0;
1410         u32 val_xoff = 0;
1411
1412         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1413
1414         /* PFC received frames */
1415         val_xoff = REG_RD(bp, emac_base +
1416                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1417         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1418         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1419         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1420
1421         pfc_frames_received[0] = val_xon + val_xoff;
1422
1423         /* PFC received sent */
1424         val_xoff = REG_RD(bp, emac_base +
1425                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1426         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1427         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1428         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1429
1430         pfc_frames_sent[0] = val_xon + val_xoff;
1431 }
1432
1433 /* Read pfc statistic*/
1434 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1435                          u32 pfc_frames_sent[2],
1436                          u32 pfc_frames_received[2])
1437 {
1438         /* Read pfc statistic */
1439         struct bnx2x *bp = params->bp;
1440
1441         DP(NETIF_MSG_LINK, "pfc statistic\n");
1442
1443         if (!vars->link_up)
1444                 return;
1445
1446         if (vars->mac_type == MAC_TYPE_EMAC) {
1447                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1448                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1449                                         pfc_frames_received);
1450         }
1451 }
1452 /******************************************************************/
1453 /*                      MAC/PBF section                           */
1454 /******************************************************************/
1455 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1456                                u32 emac_base)
1457 {
1458         u32 new_mode, cur_mode;
1459         u32 clc_cnt;
1460         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1461          * (a value of 49==0x31) and make sure that the AUTO poll is off
1462          */
1463         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1464
1465         if (USES_WARPCORE(bp))
1466                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1467         else
1468                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1469
1470         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1471             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1472                 return;
1473
1474         new_mode = cur_mode &
1475                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1476         new_mode |= clc_cnt;
1477         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1478
1479         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1480            cur_mode, new_mode);
1481         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1482         udelay(40);
1483 }
1484
1485 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1486                                         struct link_params *params)
1487 {
1488         u8 phy_index;
1489         /* Set mdio clock per phy */
1490         for (phy_index = INT_PHY; phy_index < params->num_phys;
1491               phy_index++)
1492                 bnx2x_set_mdio_clk(bp, params->chip_id,
1493                                    params->phy[phy_index].mdio_ctrl);
1494 }
1495
1496 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1497 {
1498         u32 port4mode_ovwr_val;
1499         /* Check 4-port override enabled */
1500         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1501         if (port4mode_ovwr_val & (1<<0)) {
1502                 /* Return 4-port mode override value */
1503                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1504         }
1505         /* Return 4-port mode from input pin */
1506         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1507 }
1508
1509 static void bnx2x_emac_init(struct link_params *params,
1510                             struct link_vars *vars)
1511 {
1512         /* reset and unreset the emac core */
1513         struct bnx2x *bp = params->bp;
1514         u8 port = params->port;
1515         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1516         u32 val;
1517         u16 timeout;
1518
1519         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1520                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1521         udelay(5);
1522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1524
1525         /* init emac - use read-modify-write */
1526         /* self clear reset */
1527         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1529
1530         timeout = 200;
1531         do {
1532                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1533                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1534                 if (!timeout) {
1535                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1536                         return;
1537                 }
1538                 timeout--;
1539         } while (val & EMAC_MODE_RESET);
1540
1541         bnx2x_set_mdio_emac_per_phy(bp, params);
1542         /* Set mac address */
1543         val = ((params->mac_addr[0] << 8) |
1544                 params->mac_addr[1]);
1545         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1546
1547         val = ((params->mac_addr[2] << 24) |
1548                (params->mac_addr[3] << 16) |
1549                (params->mac_addr[4] << 8) |
1550                 params->mac_addr[5]);
1551         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1552 }
1553
1554 static void bnx2x_set_xumac_nig(struct link_params *params,
1555                                 u16 tx_pause_en,
1556                                 u8 enable)
1557 {
1558         struct bnx2x *bp = params->bp;
1559
1560         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1561                enable);
1562         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1563                enable);
1564         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1565                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1566 }
1567
1568 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1569 {
1570         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1571         u32 val;
1572         struct bnx2x *bp = params->bp;
1573         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1574                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1575                 return;
1576         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1577         if (en)
1578                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1579                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1580         else
1581                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1582                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1583         /* Disable RX and TX */
1584         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1585 }
1586
1587 static void bnx2x_umac_enable(struct link_params *params,
1588                             struct link_vars *vars, u8 lb)
1589 {
1590         u32 val;
1591         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1592         struct bnx2x *bp = params->bp;
1593         /* Reset UMAC */
1594         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1595                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1596         usleep_range(1000, 2000);
1597
1598         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1599                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1600
1601         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1602
1603         /* This register opens the gate for the UMAC despite its name */
1604         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1605
1606         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1607                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1608                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1609                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1610         switch (vars->line_speed) {
1611         case SPEED_10:
1612                 val |= (0<<2);
1613                 break;
1614         case SPEED_100:
1615                 val |= (1<<2);
1616                 break;
1617         case SPEED_1000:
1618                 val |= (2<<2);
1619                 break;
1620         case SPEED_2500:
1621                 val |= (3<<2);
1622                 break;
1623         default:
1624                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1625                                vars->line_speed);
1626                 break;
1627         }
1628         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1629                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1630
1631         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1632                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1633
1634         if (vars->duplex == DUPLEX_HALF)
1635                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1636
1637         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1638         udelay(50);
1639
1640         /* Configure UMAC for EEE */
1641         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1642                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1643                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1644                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1645                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1646         } else {
1647                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1648         }
1649
1650         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1651         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1652                ((params->mac_addr[2] << 24) |
1653                 (params->mac_addr[3] << 16) |
1654                 (params->mac_addr[4] << 8) |
1655                 (params->mac_addr[5])));
1656         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1657                ((params->mac_addr[0] << 8) |
1658                 (params->mac_addr[1])));
1659
1660         /* Enable RX and TX */
1661         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1662         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1663                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1664         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1665         udelay(50);
1666
1667         /* Remove SW Reset */
1668         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1669
1670         /* Check loopback mode */
1671         if (lb)
1672                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1673         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1674
1675         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1676          * length used by the MAC receive logic to check frames.
1677          */
1678         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1679         bnx2x_set_xumac_nig(params,
1680                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1681         vars->mac_type = MAC_TYPE_UMAC;
1682
1683 }
1684
1685 /* Define the XMAC mode */
1686 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1687 {
1688         struct bnx2x *bp = params->bp;
1689         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1690
1691         /* In 4-port mode, need to set the mode only once, so if XMAC is
1692          * already out of reset, it means the mode has already been set,
1693          * and it must not* reset the XMAC again, since it controls both
1694          * ports of the path
1695          */
1696
1697         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1698              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1699              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1700             is_port4mode &&
1701             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1702              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1703                 DP(NETIF_MSG_LINK,
1704                    "XMAC already out of reset in 4-port mode\n");
1705                 return;
1706         }
1707
1708         /* Hard reset */
1709         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1710                MISC_REGISTERS_RESET_REG_2_XMAC);
1711         usleep_range(1000, 2000);
1712
1713         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1714                MISC_REGISTERS_RESET_REG_2_XMAC);
1715         if (is_port4mode) {
1716                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1717
1718                 /* Set the number of ports on the system side to up to 2 */
1719                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1720
1721                 /* Set the number of ports on the Warp Core to 10G */
1722                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1723         } else {
1724                 /* Set the number of ports on the system side to 1 */
1725                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1726                 if (max_speed == SPEED_10000) {
1727                         DP(NETIF_MSG_LINK,
1728                            "Init XMAC to 10G x 1 port per path\n");
1729                         /* Set the number of ports on the Warp Core to 10G */
1730                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1731                 } else {
1732                         DP(NETIF_MSG_LINK,
1733                            "Init XMAC to 20G x 2 ports per path\n");
1734                         /* Set the number of ports on the Warp Core to 20G */
1735                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1736                 }
1737         }
1738         /* Soft reset */
1739         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1740                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1741         usleep_range(1000, 2000);
1742
1743         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1744                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1745
1746 }
1747
1748 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1749 {
1750         u8 port = params->port;
1751         struct bnx2x *bp = params->bp;
1752         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1753         u32 val;
1754
1755         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1756             MISC_REGISTERS_RESET_REG_2_XMAC) {
1757                 /* Send an indication to change the state in the NIG back to XON
1758                  * Clearing this bit enables the next set of this bit to get
1759                  * rising edge
1760                  */
1761                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1762                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1763                        (pfc_ctrl & ~(1<<1)));
1764                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1765                        (pfc_ctrl | (1<<1)));
1766                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1767                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1768                 if (en)
1769                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1770                 else
1771                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1772                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1773         }
1774 }
1775
1776 static int bnx2x_xmac_enable(struct link_params *params,
1777                              struct link_vars *vars, u8 lb)
1778 {
1779         u32 val, xmac_base;
1780         struct bnx2x *bp = params->bp;
1781         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1782
1783         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1784
1785         bnx2x_xmac_init(params, vars->line_speed);
1786
1787         /* This register determines on which events the MAC will assert
1788          * error on the i/f to the NIG along w/ EOP.
1789          */
1790
1791         /* This register tells the NIG whether to send traffic to UMAC
1792          * or XMAC
1793          */
1794         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1795
1796         /* When XMAC is in XLGMII mode, disable sending idles for fault
1797          * detection.
1798          */
1799         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1800                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1801                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1802                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1803                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1804                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1805                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1806                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1807         }
1808         /* Set Max packet size */
1809         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1810
1811         /* CRC append for Tx packets */
1812         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1813
1814         /* update PFC */
1815         bnx2x_update_pfc_xmac(params, vars, 0);
1816
1817         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1818                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1819                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1820                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1821         } else {
1822                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1823         }
1824
1825         /* Enable TX and RX */
1826         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1827
1828         /* Set MAC in XLGMII mode for dual-mode */
1829         if ((vars->line_speed == SPEED_20000) &&
1830             (params->phy[INT_PHY].supported &
1831              SUPPORTED_20000baseKR2_Full))
1832                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1833
1834         /* Check loopback mode */
1835         if (lb)
1836                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1837         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1838         bnx2x_set_xumac_nig(params,
1839                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1840
1841         vars->mac_type = MAC_TYPE_XMAC;
1842
1843         return 0;
1844 }
1845
1846 static int bnx2x_emac_enable(struct link_params *params,
1847                              struct link_vars *vars, u8 lb)
1848 {
1849         struct bnx2x *bp = params->bp;
1850         u8 port = params->port;
1851         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1852         u32 val;
1853
1854         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1855
1856         /* Disable BMAC */
1857         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1858                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1859
1860         /* enable emac and not bmac */
1861         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1862
1863         /* ASIC */
1864         if (vars->phy_flags & PHY_XGXS_FLAG) {
1865                 u32 ser_lane = ((params->lane_config &
1866                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1867                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1868
1869                 DP(NETIF_MSG_LINK, "XGXS\n");
1870                 /* select the master lanes (out of 0-3) */
1871                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1872                 /* select XGXS */
1873                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1874
1875         } else { /* SerDes */
1876                 DP(NETIF_MSG_LINK, "SerDes\n");
1877                 /* select SerDes */
1878                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1879         }
1880
1881         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1882                       EMAC_RX_MODE_RESET);
1883         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1884                       EMAC_TX_MODE_RESET);
1885
1886                 /* pause enable/disable */
1887                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1888                                EMAC_RX_MODE_FLOW_EN);
1889
1890                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1891                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1892                                 EMAC_TX_MODE_FLOW_EN));
1893                 if (!(params->feature_config_flags &
1894                       FEATURE_CONFIG_PFC_ENABLED)) {
1895                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1896                                 bnx2x_bits_en(bp, emac_base +
1897                                               EMAC_REG_EMAC_RX_MODE,
1898                                               EMAC_RX_MODE_FLOW_EN);
1899
1900                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1901                                 bnx2x_bits_en(bp, emac_base +
1902                                               EMAC_REG_EMAC_TX_MODE,
1903                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1904                                                EMAC_TX_MODE_FLOW_EN));
1905                 } else
1906                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1907                                       EMAC_TX_MODE_FLOW_EN);
1908
1909         /* KEEP_VLAN_TAG, promiscuous */
1910         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1911         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1912
1913         /* Setting this bit causes MAC control frames (except for pause
1914          * frames) to be passed on for processing. This setting has no
1915          * affect on the operation of the pause frames. This bit effects
1916          * all packets regardless of RX Parser packet sorting logic.
1917          * Turn the PFC off to make sure we are in Xon state before
1918          * enabling it.
1919          */
1920         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1921         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923                 /* Enable PFC again */
1924                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1925                         EMAC_REG_RX_PFC_MODE_RX_EN |
1926                         EMAC_REG_RX_PFC_MODE_TX_EN |
1927                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1928
1929                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1930                         ((0x0101 <<
1931                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1932                          (0x00ff <<
1933                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1934                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1935         }
1936         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1937
1938         /* Set Loopback */
1939         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1940         if (lb)
1941                 val |= 0x810;
1942         else
1943                 val &= ~0x810;
1944         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1945
1946         /* Enable emac */
1947         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1948
1949         /* Enable emac for jumbo packets */
1950         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1951                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1952                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1953
1954         /* Strip CRC */
1955         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1956
1957         /* Disable the NIG in/out to the bmac */
1958         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1959         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1960         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1961
1962         /* Enable the NIG in/out to the emac */
1963         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1964         val = 0;
1965         if ((params->feature_config_flags &
1966               FEATURE_CONFIG_PFC_ENABLED) ||
1967             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1968                 val = 1;
1969
1970         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1971         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1972
1973         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1974
1975         vars->mac_type = MAC_TYPE_EMAC;
1976         return 0;
1977 }
1978
1979 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1980                                    struct link_vars *vars)
1981 {
1982         u32 wb_data[2];
1983         struct bnx2x *bp = params->bp;
1984         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1985                 NIG_REG_INGRESS_BMAC0_MEM;
1986
1987         u32 val = 0x14;
1988         if ((!(params->feature_config_flags &
1989               FEATURE_CONFIG_PFC_ENABLED)) &&
1990                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1991                 /* Enable BigMAC to react on received Pause packets */
1992                 val |= (1<<5);
1993         wb_data[0] = val;
1994         wb_data[1] = 0;
1995         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1996
1997         /* TX control */
1998         val = 0xc0;
1999         if (!(params->feature_config_flags &
2000               FEATURE_CONFIG_PFC_ENABLED) &&
2001                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2002                 val |= 0x800000;
2003         wb_data[0] = val;
2004         wb_data[1] = 0;
2005         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2006 }
2007
2008 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2009                                    struct link_vars *vars,
2010                                    u8 is_lb)
2011 {
2012         /* Set rx control: Strip CRC and enable BigMAC to relay
2013          * control packets to the system as well
2014          */
2015         u32 wb_data[2];
2016         struct bnx2x *bp = params->bp;
2017         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2018                 NIG_REG_INGRESS_BMAC0_MEM;
2019         u32 val = 0x14;
2020
2021         if ((!(params->feature_config_flags &
2022               FEATURE_CONFIG_PFC_ENABLED)) &&
2023                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2024                 /* Enable BigMAC to react on received Pause packets */
2025                 val |= (1<<5);
2026         wb_data[0] = val;
2027         wb_data[1] = 0;
2028         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2029         udelay(30);
2030
2031         /* Tx control */
2032         val = 0xc0;
2033         if (!(params->feature_config_flags &
2034                                 FEATURE_CONFIG_PFC_ENABLED) &&
2035             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2036                 val |= 0x800000;
2037         wb_data[0] = val;
2038         wb_data[1] = 0;
2039         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2040
2041         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2042                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2043                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2044                 wb_data[0] = 0x0;
2045                 wb_data[0] |= (1<<0);  /* RX */
2046                 wb_data[0] |= (1<<1);  /* TX */
2047                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2048                 wb_data[0] |= (1<<3);  /* 8 cos */
2049                 wb_data[0] |= (1<<5);  /* STATS */
2050                 wb_data[1] = 0;
2051                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2052                             wb_data, 2);
2053                 /* Clear the force Xon */
2054                 wb_data[0] &= ~(1<<2);
2055         } else {
2056                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2057                 /* Disable PFC RX & TX & STATS and set 8 COS */
2058                 wb_data[0] = 0x8;
2059                 wb_data[1] = 0;
2060         }
2061
2062         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2063
2064         /* Set Time (based unit is 512 bit time) between automatic
2065          * re-sending of PP packets amd enable automatic re-send of
2066          * Per-Priroity Packet as long as pp_gen is asserted and
2067          * pp_disable is low.
2068          */
2069         val = 0x8000;
2070         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2071                 val |= (1<<16); /* enable automatic re-send */
2072
2073         wb_data[0] = val;
2074         wb_data[1] = 0;
2075         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2076                     wb_data, 2);
2077
2078         /* mac control */
2079         val = 0x3; /* Enable RX and TX */
2080         if (is_lb) {
2081                 val |= 0x4; /* Local loopback */
2082                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2083         }
2084         /* When PFC enabled, Pass pause frames towards the NIG. */
2085         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2086                 val |= ((1<<6)|(1<<5));
2087
2088         wb_data[0] = val;
2089         wb_data[1] = 0;
2090         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2091 }
2092
2093 /******************************************************************************
2094 * Description:
2095 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2096 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2097 ******************************************************************************/
2098 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2099                                            u8 cos_entry,
2100                                            u32 priority_mask, u8 port)
2101 {
2102         u32 nig_reg_rx_priority_mask_add = 0;
2103
2104         switch (cos_entry) {
2105         case 0:
2106              nig_reg_rx_priority_mask_add = (port) ?
2107                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2108                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2109              break;
2110         case 1:
2111             nig_reg_rx_priority_mask_add = (port) ?
2112                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2113                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2114             break;
2115         case 2:
2116             nig_reg_rx_priority_mask_add = (port) ?
2117                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2118                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2119             break;
2120         case 3:
2121             if (port)
2122                 return -EINVAL;
2123             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2124             break;
2125         case 4:
2126             if (port)
2127                 return -EINVAL;
2128             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2129             break;
2130         case 5:
2131             if (port)
2132                 return -EINVAL;
2133             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2134             break;
2135         }
2136
2137         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2138
2139         return 0;
2140 }
2141 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2142 {
2143         struct bnx2x *bp = params->bp;
2144
2145         REG_WR(bp, params->shmem_base +
2146                offsetof(struct shmem_region,
2147                         port_mb[params->port].link_status), link_status);
2148 }
2149
2150 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2151 {
2152         struct bnx2x *bp = params->bp;
2153
2154         if (SHMEM2_HAS(bp, link_attr_sync))
2155                 REG_WR(bp, params->shmem2_base +
2156                        offsetof(struct shmem2_region,
2157                                 link_attr_sync[params->port]), link_attr);
2158 }
2159
2160 static void bnx2x_update_pfc_nig(struct link_params *params,
2161                 struct link_vars *vars,
2162                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2163 {
2164         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2165         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2166         u32 pkt_priority_to_cos = 0;
2167         struct bnx2x *bp = params->bp;
2168         u8 port = params->port;
2169
2170         int set_pfc = params->feature_config_flags &
2171                 FEATURE_CONFIG_PFC_ENABLED;
2172         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2173
2174         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2175          * MAC control frames (that are not pause packets)
2176          * will be forwarded to the XCM.
2177          */
2178         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2179                           NIG_REG_LLH0_XCM_MASK);
2180         /* NIG params will override non PFC params, since it's possible to
2181          * do transition from PFC to SAFC
2182          */
2183         if (set_pfc) {
2184                 pause_enable = 0;
2185                 llfc_out_en = 0;
2186                 llfc_enable = 0;
2187                 if (CHIP_IS_E3(bp))
2188                         ppp_enable = 0;
2189                 else
2190                         ppp_enable = 1;
2191                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2192                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2193                 xcm_out_en = 0;
2194                 hwpfc_enable = 1;
2195         } else  {
2196                 if (nig_params) {
2197                         llfc_out_en = nig_params->llfc_out_en;
2198                         llfc_enable = nig_params->llfc_enable;
2199                         pause_enable = nig_params->pause_enable;
2200                 } else  /* Default non PFC mode - PAUSE */
2201                         pause_enable = 1;
2202
2203                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2204                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2205                 xcm_out_en = 1;
2206         }
2207
2208         if (CHIP_IS_E3(bp))
2209                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2210                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2211         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2212                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2213         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2214                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2215         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2216                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2217
2218         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2219                NIG_REG_PPP_ENABLE_0, ppp_enable);
2220
2221         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2222                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2223
2224         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2225                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2226
2227         /* Output enable for RX_XCM # IF */
2228         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2229                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2230
2231         /* HW PFC TX enable */
2232         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2233                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2234
2235         if (nig_params) {
2236                 u8 i = 0;
2237                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2238
2239                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2240                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2241                 nig_params->rx_cos_priority_mask[i], port);
2242
2243                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2244                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2245                        nig_params->llfc_high_priority_classes);
2246
2247                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2248                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2249                        nig_params->llfc_low_priority_classes);
2250         }
2251         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2252                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2253                pkt_priority_to_cos);
2254 }
2255
2256 int bnx2x_update_pfc(struct link_params *params,
2257                       struct link_vars *vars,
2258                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2259 {
2260         /* The PFC and pause are orthogonal to one another, meaning when
2261          * PFC is enabled, the pause are disabled, and when PFC is
2262          * disabled, pause are set according to the pause result.
2263          */
2264         u32 val;
2265         struct bnx2x *bp = params->bp;
2266         int bnx2x_status = 0;
2267         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2268
2269         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2270                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2271         else
2272                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2273
2274         bnx2x_update_mng(params, vars->link_status);
2275
2276         /* Update NIG params */
2277         bnx2x_update_pfc_nig(params, vars, pfc_params);
2278
2279         if (!vars->link_up)
2280                 return bnx2x_status;
2281
2282         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2283
2284         if (CHIP_IS_E3(bp)) {
2285                 if (vars->mac_type == MAC_TYPE_XMAC)
2286                         bnx2x_update_pfc_xmac(params, vars, 0);
2287         } else {
2288                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2289                 if ((val &
2290                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2291                     == 0) {
2292                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2293                         bnx2x_emac_enable(params, vars, 0);
2294                         return bnx2x_status;
2295                 }
2296                 if (CHIP_IS_E2(bp))
2297                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2298                 else
2299                         bnx2x_update_pfc_bmac1(params, vars);
2300
2301                 val = 0;
2302                 if ((params->feature_config_flags &
2303                      FEATURE_CONFIG_PFC_ENABLED) ||
2304                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2305                         val = 1;
2306                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2307         }
2308         return bnx2x_status;
2309 }
2310
2311 static int bnx2x_bmac1_enable(struct link_params *params,
2312                               struct link_vars *vars,
2313                               u8 is_lb)
2314 {
2315         struct bnx2x *bp = params->bp;
2316         u8 port = params->port;
2317         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2318                                NIG_REG_INGRESS_BMAC0_MEM;
2319         u32 wb_data[2];
2320         u32 val;
2321
2322         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2323
2324         /* XGXS control */
2325         wb_data[0] = 0x3c;
2326         wb_data[1] = 0;
2327         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2328                     wb_data, 2);
2329
2330         /* TX MAC SA */
2331         wb_data[0] = ((params->mac_addr[2] << 24) |
2332                        (params->mac_addr[3] << 16) |
2333                        (params->mac_addr[4] << 8) |
2334                         params->mac_addr[5]);
2335         wb_data[1] = ((params->mac_addr[0] << 8) |
2336                         params->mac_addr[1]);
2337         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2338
2339         /* MAC control */
2340         val = 0x3;
2341         if (is_lb) {
2342                 val |= 0x4;
2343                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2344         }
2345         wb_data[0] = val;
2346         wb_data[1] = 0;
2347         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2348
2349         /* Set rx mtu */
2350         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2351         wb_data[1] = 0;
2352         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2353
2354         bnx2x_update_pfc_bmac1(params, vars);
2355
2356         /* Set tx mtu */
2357         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2358         wb_data[1] = 0;
2359         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2360
2361         /* Set cnt max size */
2362         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2363         wb_data[1] = 0;
2364         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2365
2366         /* Configure SAFC */
2367         wb_data[0] = 0x1000200;
2368         wb_data[1] = 0;
2369         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2370                     wb_data, 2);
2371
2372         return 0;
2373 }
2374
2375 static int bnx2x_bmac2_enable(struct link_params *params,
2376                               struct link_vars *vars,
2377                               u8 is_lb)
2378 {
2379         struct bnx2x *bp = params->bp;
2380         u8 port = params->port;
2381         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2382                                NIG_REG_INGRESS_BMAC0_MEM;
2383         u32 wb_data[2];
2384
2385         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2386
2387         wb_data[0] = 0;
2388         wb_data[1] = 0;
2389         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2390         udelay(30);
2391
2392         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2393         wb_data[0] = 0x3c;
2394         wb_data[1] = 0;
2395         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2396                     wb_data, 2);
2397
2398         udelay(30);
2399
2400         /* TX MAC SA */
2401         wb_data[0] = ((params->mac_addr[2] << 24) |
2402                        (params->mac_addr[3] << 16) |
2403                        (params->mac_addr[4] << 8) |
2404                         params->mac_addr[5]);
2405         wb_data[1] = ((params->mac_addr[0] << 8) |
2406                         params->mac_addr[1]);
2407         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2408                     wb_data, 2);
2409
2410         udelay(30);
2411
2412         /* Configure SAFC */
2413         wb_data[0] = 0x1000200;
2414         wb_data[1] = 0;
2415         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2416                     wb_data, 2);
2417         udelay(30);
2418
2419         /* Set RX MTU */
2420         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2421         wb_data[1] = 0;
2422         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2423         udelay(30);
2424
2425         /* Set TX MTU */
2426         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2427         wb_data[1] = 0;
2428         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2429         udelay(30);
2430         /* Set cnt max size */
2431         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2432         wb_data[1] = 0;
2433         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2434         udelay(30);
2435         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2436
2437         return 0;
2438 }
2439
2440 static int bnx2x_bmac_enable(struct link_params *params,
2441                              struct link_vars *vars,
2442                              u8 is_lb, u8 reset_bmac)
2443 {
2444         int rc = 0;
2445         u8 port = params->port;
2446         struct bnx2x *bp = params->bp;
2447         u32 val;
2448         /* Reset and unreset the BigMac */
2449         if (reset_bmac) {
2450                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2451                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2452                 usleep_range(1000, 2000);
2453         }
2454
2455         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2456                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2457
2458         /* Enable access for bmac registers */
2459         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2460
2461         /* Enable BMAC according to BMAC type*/
2462         if (CHIP_IS_E2(bp))
2463                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2464         else
2465                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2466         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2467         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2468         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2469         val = 0;
2470         if ((params->feature_config_flags &
2471               FEATURE_CONFIG_PFC_ENABLED) ||
2472             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2473                 val = 1;
2474         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2475         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2476         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2477         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2478         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2479         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2480
2481         vars->mac_type = MAC_TYPE_BMAC;
2482         return rc;
2483 }
2484
2485 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2486 {
2487         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2488                         NIG_REG_INGRESS_BMAC0_MEM;
2489         u32 wb_data[2];
2490         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2491
2492         if (CHIP_IS_E2(bp))
2493                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2494         else
2495                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2496         /* Only if the bmac is out of reset */
2497         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2498                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2499             nig_bmac_enable) {
2500                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2501                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2502                 if (en)
2503                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2504                 else
2505                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2506                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2507                 usleep_range(1000, 2000);
2508         }
2509 }
2510
2511 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2512                             u32 line_speed)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u8 port = params->port;
2516         u32 init_crd, crd;
2517         u32 count = 1000;
2518
2519         /* Disable port */
2520         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2521
2522         /* Wait for init credit */
2523         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2524         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2526
2527         while ((init_crd != crd) && count) {
2528                 usleep_range(5000, 10000);
2529                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2530                 count--;
2531         }
2532         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2533         if (init_crd != crd) {
2534                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2535                           init_crd, crd);
2536                 return -EINVAL;
2537         }
2538
2539         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2540             line_speed == SPEED_10 ||
2541             line_speed == SPEED_100 ||
2542             line_speed == SPEED_1000 ||
2543             line_speed == SPEED_2500) {
2544                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2545                 /* Update threshold */
2546                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2547                 /* Update init credit */
2548                 init_crd = 778;         /* (800-18-4) */
2549
2550         } else {
2551                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2552                               ETH_OVREHEAD)/16;
2553                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2554                 /* Update threshold */
2555                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2556                 /* Update init credit */
2557                 switch (line_speed) {
2558                 case SPEED_10000:
2559                         init_crd = thresh + 553 - 22;
2560                         break;
2561                 default:
2562                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2563                                   line_speed);
2564                         return -EINVAL;
2565                 }
2566         }
2567         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2568         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2569                  line_speed, init_crd);
2570
2571         /* Probe the credit changes */
2572         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2573         usleep_range(5000, 10000);
2574         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2575
2576         /* Enable port */
2577         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2578         return 0;
2579 }
2580
2581 /**
2582  * bnx2x_get_emac_base - retrive emac base address
2583  *
2584  * @bp:                 driver handle
2585  * @mdc_mdio_access:    access type
2586  * @port:               port id
2587  *
2588  * This function selects the MDC/MDIO access (through emac0 or
2589  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2590  * phy has a default access mode, which could also be overridden
2591  * by nvram configuration. This parameter, whether this is the
2592  * default phy configuration, or the nvram overrun
2593  * configuration, is passed here as mdc_mdio_access and selects
2594  * the emac_base for the CL45 read/writes operations
2595  */
2596 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2597                                u32 mdc_mdio_access, u8 port)
2598 {
2599         u32 emac_base = 0;
2600         switch (mdc_mdio_access) {
2601         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2602                 break;
2603         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2604                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2605                         emac_base = GRCBASE_EMAC1;
2606                 else
2607                         emac_base = GRCBASE_EMAC0;
2608                 break;
2609         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2610                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2611                         emac_base = GRCBASE_EMAC0;
2612                 else
2613                         emac_base = GRCBASE_EMAC1;
2614                 break;
2615         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2616                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2617                 break;
2618         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2619                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2620                 break;
2621         default:
2622                 break;
2623         }
2624         return emac_base;
2625
2626 }
2627
2628 /******************************************************************/
2629 /*                      CL22 access functions                     */
2630 /******************************************************************/
2631 static int bnx2x_cl22_write(struct bnx2x *bp,
2632                                        struct bnx2x_phy *phy,
2633                                        u16 reg, u16 val)
2634 {
2635         u32 tmp, mode;
2636         u8 i;
2637         int rc = 0;
2638         /* Switch to CL22 */
2639         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2640         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2641                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2642
2643         /* Address */
2644         tmp = ((phy->addr << 21) | (reg << 16) | val |
2645                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2646                EMAC_MDIO_COMM_START_BUSY);
2647         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2648
2649         for (i = 0; i < 50; i++) {
2650                 udelay(10);
2651
2652                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2653                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2654                         udelay(5);
2655                         break;
2656                 }
2657         }
2658         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2659                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2660                 rc = -EFAULT;
2661         }
2662         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2663         return rc;
2664 }
2665
2666 static int bnx2x_cl22_read(struct bnx2x *bp,
2667                                       struct bnx2x_phy *phy,
2668                                       u16 reg, u16 *ret_val)
2669 {
2670         u32 val, mode;
2671         u16 i;
2672         int rc = 0;
2673
2674         /* Switch to CL22 */
2675         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2676         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2677                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2678
2679         /* Address */
2680         val = ((phy->addr << 21) | (reg << 16) |
2681                EMAC_MDIO_COMM_COMMAND_READ_22 |
2682                EMAC_MDIO_COMM_START_BUSY);
2683         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2684
2685         for (i = 0; i < 50; i++) {
2686                 udelay(10);
2687
2688                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2689                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2690                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2691                         udelay(5);
2692                         break;
2693                 }
2694         }
2695         if (val & EMAC_MDIO_COMM_START_BUSY) {
2696                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2697
2698                 *ret_val = 0;
2699                 rc = -EFAULT;
2700         }
2701         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2702         return rc;
2703 }
2704
2705 /******************************************************************/
2706 /*                      CL45 access functions                     */
2707 /******************************************************************/
2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2709                            u8 devad, u16 reg, u16 *ret_val)
2710 {
2711         u32 val;
2712         u16 i;
2713         int rc = 0;
2714         u32 chip_id;
2715         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2716                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2717                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2718                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2719         }
2720
2721         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2722                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2723                               EMAC_MDIO_STATUS_10MB);
2724         /* Address */
2725         val = ((phy->addr << 21) | (devad << 16) | reg |
2726                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2727                EMAC_MDIO_COMM_START_BUSY);
2728         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2729
2730         for (i = 0; i < 50; i++) {
2731                 udelay(10);
2732
2733                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2734                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2735                         udelay(5);
2736                         break;
2737                 }
2738         }
2739         if (val & EMAC_MDIO_COMM_START_BUSY) {
2740                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2741                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2742                 *ret_val = 0;
2743                 rc = -EFAULT;
2744         } else {
2745                 /* Data */
2746                 val = ((phy->addr << 21) | (devad << 16) |
2747                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2748                        EMAC_MDIO_COMM_START_BUSY);
2749                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2750
2751                 for (i = 0; i < 50; i++) {
2752                         udelay(10);
2753
2754                         val = REG_RD(bp, phy->mdio_ctrl +
2755                                      EMAC_REG_EMAC_MDIO_COMM);
2756                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2757                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2758                                 break;
2759                         }
2760                 }
2761                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2762                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2763                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2764                         *ret_val = 0;
2765                         rc = -EFAULT;
2766                 }
2767         }
2768         /* Work around for E3 A0 */
2769         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2770                 phy->flags ^= FLAGS_DUMMY_READ;
2771                 if (phy->flags & FLAGS_DUMMY_READ) {
2772                         u16 temp_val;
2773                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2774                 }
2775         }
2776
2777         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2778                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2779                                EMAC_MDIO_STATUS_10MB);
2780         return rc;
2781 }
2782
2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2784                             u8 devad, u16 reg, u16 val)
2785 {
2786         u32 tmp;
2787         u8 i;
2788         int rc = 0;
2789         u32 chip_id;
2790         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2791                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2792                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2793                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2794         }
2795
2796         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2797                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2798                               EMAC_MDIO_STATUS_10MB);
2799
2800         /* Address */
2801         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2802                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2803                EMAC_MDIO_COMM_START_BUSY);
2804         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2805
2806         for (i = 0; i < 50; i++) {
2807                 udelay(10);
2808
2809                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2810                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2811                         udelay(5);
2812                         break;
2813                 }
2814         }
2815         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2816                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2817                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2818                 rc = -EFAULT;
2819         } else {
2820                 /* Data */
2821                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2822                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2823                        EMAC_MDIO_COMM_START_BUSY);
2824                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2825
2826                 for (i = 0; i < 50; i++) {
2827                         udelay(10);
2828
2829                         tmp = REG_RD(bp, phy->mdio_ctrl +
2830                                      EMAC_REG_EMAC_MDIO_COMM);
2831                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2832                                 udelay(5);
2833                                 break;
2834                         }
2835                 }
2836                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2837                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2838                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2839                         rc = -EFAULT;
2840                 }
2841         }
2842         /* Work around for E3 A0 */
2843         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2844                 phy->flags ^= FLAGS_DUMMY_READ;
2845                 if (phy->flags & FLAGS_DUMMY_READ) {
2846                         u16 temp_val;
2847                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2848                 }
2849         }
2850         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2851                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2852                                EMAC_MDIO_STATUS_10MB);
2853         return rc;
2854 }
2855
2856 /******************************************************************/
2857 /*                      EEE section                                */
2858 /******************************************************************/
2859 static u8 bnx2x_eee_has_cap(struct link_params *params)
2860 {
2861         struct bnx2x *bp = params->bp;
2862
2863         if (REG_RD(bp, params->shmem2_base) <=
2864                    offsetof(struct shmem2_region, eee_status[params->port]))
2865                 return 0;
2866
2867         return 1;
2868 }
2869
2870 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2871 {
2872         switch (nvram_mode) {
2873         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2874                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2875                 break;
2876         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2877                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2878                 break;
2879         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2880                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2881                 break;
2882         default:
2883                 *idle_timer = 0;
2884                 break;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2891 {
2892         switch (idle_timer) {
2893         case EEE_MODE_NVRAM_BALANCED_TIME:
2894                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2895                 break;
2896         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2897                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2898                 break;
2899         case EEE_MODE_NVRAM_LATENCY_TIME:
2900                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2901                 break;
2902         default:
2903                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2904                 break;
2905         }
2906
2907         return 0;
2908 }
2909
2910 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2911 {
2912         u32 eee_mode, eee_idle;
2913         struct bnx2x *bp = params->bp;
2914
2915         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2916                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2917                         /* time value in eee_mode --> used directly*/
2918                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2919                 } else {
2920                         /* hsi value in eee_mode --> time */
2921                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2922                                                     EEE_MODE_NVRAM_MASK,
2923                                                     &eee_idle))
2924                                 return 0;
2925                 }
2926         } else {
2927                 /* hsi values in nvram --> time*/
2928                 eee_mode = ((REG_RD(bp, params->shmem_base +
2929                                     offsetof(struct shmem_region, dev_info.
2930                                     port_feature_config[params->port].
2931                                     eee_power_mode)) &
2932                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2933                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2934
2935                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2936                         return 0;
2937         }
2938
2939         return eee_idle;
2940 }
2941
2942 static int bnx2x_eee_set_timers(struct link_params *params,
2943                                    struct link_vars *vars)
2944 {
2945         u32 eee_idle = 0, eee_mode;
2946         struct bnx2x *bp = params->bp;
2947
2948         eee_idle = bnx2x_eee_calc_timer(params);
2949
2950         if (eee_idle) {
2951                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2952                        eee_idle);
2953         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2954                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2955                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2956                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2957                 return -EINVAL;
2958         }
2959
2960         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2961         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2962                 /* eee_idle in 1u --> eee_status in 16u */
2963                 eee_idle >>= 4;
2964                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2965                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2966         } else {
2967                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2968                         return -EINVAL;
2969                 vars->eee_status |= eee_mode;
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int bnx2x_eee_initial_config(struct link_params *params,
2976                                      struct link_vars *vars, u8 mode)
2977 {
2978         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2979
2980         /* Propogate params' bits --> vars (for migration exposure) */
2981         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2982                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2983         else
2984                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2985
2986         if (params->eee_mode & EEE_MODE_ADV_LPI)
2987                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2988         else
2989                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2990
2991         return bnx2x_eee_set_timers(params, vars);
2992 }
2993
2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2995                                 struct link_params *params,
2996                                 struct link_vars *vars)
2997 {
2998         struct bnx2x *bp = params->bp;
2999
3000         /* Make Certain LPI is disabled */
3001         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3002
3003         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3004
3005         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3006
3007         return 0;
3008 }
3009
3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3011                                   struct link_params *params,
3012                                   struct link_vars *vars, u8 modes)
3013 {
3014         struct bnx2x *bp = params->bp;
3015         u16 val = 0;
3016
3017         /* Mask events preventing LPI generation */
3018         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3019
3020         if (modes & SHMEM_EEE_10G_ADV) {
3021                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3022                 val |= 0x8;
3023         }
3024         if (modes & SHMEM_EEE_1G_ADV) {
3025                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3026                 val |= 0x4;
3027         }
3028
3029         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3030
3031         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3032         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3033
3034         return 0;
3035 }
3036
3037 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3038 {
3039         struct bnx2x *bp = params->bp;
3040
3041         if (bnx2x_eee_has_cap(params))
3042                 REG_WR(bp, params->shmem2_base +
3043                        offsetof(struct shmem2_region,
3044                                 eee_status[params->port]), eee_status);
3045 }
3046
3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3048                                   struct link_params *params,
3049                                   struct link_vars *vars)
3050 {
3051         struct bnx2x *bp = params->bp;
3052         u16 adv = 0, lp = 0;
3053         u32 lp_adv = 0;
3054         u8 neg = 0;
3055
3056         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3057         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3058
3059         if (lp & 0x2) {
3060                 lp_adv |= SHMEM_EEE_100M_ADV;
3061                 if (adv & 0x2) {
3062                         if (vars->line_speed == SPEED_100)
3063                                 neg = 1;
3064                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3065                 }
3066         }
3067         if (lp & 0x14) {
3068                 lp_adv |= SHMEM_EEE_1G_ADV;
3069                 if (adv & 0x14) {
3070                         if (vars->line_speed == SPEED_1000)
3071                                 neg = 1;
3072                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3073                 }
3074         }
3075         if (lp & 0x68) {
3076                 lp_adv |= SHMEM_EEE_10G_ADV;
3077                 if (adv & 0x68) {
3078                         if (vars->line_speed == SPEED_10000)
3079                                 neg = 1;
3080                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3081                 }
3082         }
3083
3084         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3085         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3086
3087         if (neg) {
3088                 DP(NETIF_MSG_LINK, "EEE is active\n");
3089                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3090         }
3091
3092 }
3093
3094 /******************************************************************/
3095 /*                      BSC access functions from E3              */
3096 /******************************************************************/
3097 static void bnx2x_bsc_module_sel(struct link_params *params)
3098 {
3099         int idx;
3100         u32 board_cfg, sfp_ctrl;
3101         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3102         struct bnx2x *bp = params->bp;
3103         u8 port = params->port;
3104         /* Read I2C output PINs */
3105         board_cfg = REG_RD(bp, params->shmem_base +
3106                            offsetof(struct shmem_region,
3107                                     dev_info.shared_hw_config.board));
3108         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3109         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3110                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3111
3112         /* Read I2C output value */
3113         sfp_ctrl = REG_RD(bp, params->shmem_base +
3114                           offsetof(struct shmem_region,
3115                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3116         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3117         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3118         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3119         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3120                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3121 }
3122
3123 static int bnx2x_bsc_read(struct link_params *params,
3124                           struct bnx2x_phy *phy,
3125                           u8 sl_devid,
3126                           u16 sl_addr,
3127                           u8 lc_addr,
3128                           u8 xfer_cnt,
3129                           u32 *data_array)
3130 {
3131         u32 val, i;
3132         int rc = 0;
3133         struct bnx2x *bp = params->bp;
3134
3135         if (xfer_cnt > 16) {
3136                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137                                         xfer_cnt);
3138                 return -EINVAL;
3139         }
3140         bnx2x_bsc_module_sel(params);
3141
3142         xfer_cnt = 16 - lc_addr;
3143
3144         /* Enable the engine */
3145         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146         val |= MCPR_IMC_COMMAND_ENABLE;
3147         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
3149         /* Program slave device ID */
3150         val = (sl_devid << 16) | sl_addr;
3151         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
3153         /* Start xfer with 0 byte to update the address pointer ???*/
3154         val = (MCPR_IMC_COMMAND_ENABLE) |
3155               (MCPR_IMC_COMMAND_WRITE_OP <<
3156                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
3160         /* Poll for completion */
3161         i = 0;
3162         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164                 udelay(10);
3165                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166                 if (i++ > 1000) {
3167                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168                                                                 i);
3169                         rc = -EFAULT;
3170                         break;
3171                 }
3172         }
3173         if (rc == -EFAULT)
3174                 return rc;
3175
3176         /* Start xfer with read op */
3177         val = (MCPR_IMC_COMMAND_ENABLE) |
3178                 (MCPR_IMC_COMMAND_READ_OP <<
3179                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181                   (xfer_cnt);
3182         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
3184         /* Poll for completion */
3185         i = 0;
3186         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188                 udelay(10);
3189                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190                 if (i++ > 1000) {
3191                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192                         rc = -EFAULT;
3193                         break;
3194                 }
3195         }
3196         if (rc == -EFAULT)
3197                 return rc;
3198
3199         for (i = (lc_addr >> 2); i < 4; i++) {
3200                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201 #ifdef __BIG_ENDIAN
3202                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203                                 ((data_array[i] & 0x0000ff00) << 8) |
3204                                 ((data_array[i] & 0x00ff0000) >> 8) |
3205                                 ((data_array[i] & 0xff000000) >> 24);
3206 #endif
3207         }
3208         return rc;
3209 }
3210
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212                                      u8 devad, u16 reg, u16 or_val)
3213 {
3214         u16 val;
3215         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217 }
3218
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220                                       struct bnx2x_phy *phy,
3221                                       u8 devad, u16 reg, u16 and_val)
3222 {
3223         u16 val;
3224         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226 }
3227
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229                    u8 devad, u16 reg, u16 *ret_val)
3230 {
3231         u8 phy_index;
3232         /* Probe for the phy according to the given phy_addr, and execute
3233          * the read request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_read(params->bp,
3238                                                &params->phy[phy_index], devad,
3239                                                reg, ret_val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246                     u8 devad, u16 reg, u16 val)
3247 {
3248         u8 phy_index;
3249         /* Probe for the phy according to the given phy_addr, and execute
3250          * the write request on it
3251          */
3252         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253                 if (params->phy[phy_index].addr == phy_addr) {
3254                         return bnx2x_cl45_write(params->bp,
3255                                                 &params->phy[phy_index], devad,
3256                                                 reg, val);
3257                 }
3258         }
3259         return -EINVAL;
3260 }
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262                                   struct link_params *params)
3263 {
3264         u8 lane = 0;
3265         struct bnx2x *bp = params->bp;
3266         u32 path_swap, path_swap_ovr;
3267         u8 path, port;
3268
3269         path = BP_PATH(bp);
3270         port = params->port;
3271
3272         if (bnx2x_is_4_port_mode(bp)) {
3273                 u32 port_swap, port_swap_ovr;
3274
3275                 /* Figure out path swap value */
3276                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277                 if (path_swap_ovr & 0x1)
3278                         path_swap = (path_swap_ovr & 0x2);
3279                 else
3280                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282                 if (path_swap)
3283                         path = path ^ 1;
3284
3285                 /* Figure out port swap value */
3286                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287                 if (port_swap_ovr & 0x1)
3288                         port_swap = (port_swap_ovr & 0x2);
3289                 else
3290                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292                 if (port_swap)
3293                         port = port ^ 1;
3294
3295                 lane = (port<<1) + path;
3296         } else { /* Two port mode - no port swap */
3297
3298                 /* Figure out path swap value */
3299                 path_swap_ovr =
3300                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301                 if (path_swap_ovr & 0x1) {
3302                         path_swap = (path_swap_ovr & 0x2);
3303                 } else {
3304                         path_swap =
3305                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306                 }
3307                 if (path_swap)
3308                         path = path ^ 1;
3309
3310                 lane = path << 1 ;
3311         }
3312         return lane;
3313 }
3314
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316                               struct bnx2x_phy *phy)
3317 {
3318         u32 ser_lane;
3319         u16 offset, aer_val;
3320         struct bnx2x *bp = params->bp;
3321         ser_lane = ((params->lane_config &
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
3325         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326                 (phy->addr + ser_lane) : 0;
3327
3328         if (USES_WARPCORE(bp)) {
3329                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330                 /* In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386                                      struct link_params *params,
3387                                      u32 action)
3388 {
3389         struct bnx2x *bp = params->bp;
3390         switch (action) {
3391         case PHY_INIT:
3392                 /* Set correct devad */
3393                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395                        phy->def_md_devad);
3396                 break;
3397         }
3398 }
3399
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3401 {
3402         struct bnx2x *bp = params->bp;
3403         u8 port;
3404         u32 val;
3405         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406         port = params->port;
3407
3408         val = XGXS_RESET_BITS << (port*16);
3409
3410         /* Reset and unreset the SerDes/XGXS */
3411         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412         udelay(500);
3413         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415                                  PHY_INIT);
3416 }
3417
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419                                      struct link_params *params, u16 *ieee_fc)
3420 {
3421         struct bnx2x *bp = params->bp;
3422         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423         /* Resolve pause mode and advertisement Please refer to Table
3424          * 28B-3 of the 802.3ab-1999 spec
3425          */
3426
3427         switch (phy->req_flow_ctrl) {
3428         case BNX2X_FLOW_CTRL_AUTO:
3429                 switch (params->req_fc_auto_adv) {
3430                 case BNX2X_FLOW_CTRL_BOTH:
3431                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3432                         break;
3433                 case BNX2X_FLOW_CTRL_RX:
3434                 case BNX2X_FLOW_CTRL_TX:
3435                         *ieee_fc |=
3436                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3437                         break;
3438                 default:
3439                         break;
3440                 }
3441                 break;
3442         case BNX2X_FLOW_CTRL_TX:
3443                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3444                 break;
3445
3446         case BNX2X_FLOW_CTRL_RX:
3447         case BNX2X_FLOW_CTRL_BOTH:
3448                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3449                 break;
3450
3451         case BNX2X_FLOW_CTRL_NONE:
3452         default:
3453                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3454                 break;
3455         }
3456         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3457 }
3458
3459 static void set_phy_vars(struct link_params *params,
3460                          struct link_vars *vars)
3461 {
3462         struct bnx2x *bp = params->bp;
3463         u8 actual_phy_idx, phy_index, link_cfg_idx;
3464         u8 phy_config_swapped = params->multi_phy_config &
3465                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3466         for (phy_index = INT_PHY; phy_index < params->num_phys;
3467               phy_index++) {
3468                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3469                 actual_phy_idx = phy_index;
3470                 if (phy_config_swapped) {
3471                         if (phy_index == EXT_PHY1)
3472                                 actual_phy_idx = EXT_PHY2;
3473                         else if (phy_index == EXT_PHY2)
3474                                 actual_phy_idx = EXT_PHY1;
3475                 }
3476                 params->phy[actual_phy_idx].req_flow_ctrl =
3477                         params->req_flow_ctrl[link_cfg_idx];
3478
3479                 params->phy[actual_phy_idx].req_line_speed =
3480                         params->req_line_speed[link_cfg_idx];
3481
3482                 params->phy[actual_phy_idx].speed_cap_mask =
3483                         params->speed_cap_mask[link_cfg_idx];
3484
3485                 params->phy[actual_phy_idx].req_duplex =
3486                         params->req_duplex[link_cfg_idx];
3487
3488                 if (params->req_line_speed[link_cfg_idx] ==
3489                     SPEED_AUTO_NEG)
3490                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3491
3492                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3493                            " speed_cap_mask %x\n",
3494                            params->phy[actual_phy_idx].req_flow_ctrl,
3495                            params->phy[actual_phy_idx].req_line_speed,
3496                            params->phy[actual_phy_idx].speed_cap_mask);
3497         }
3498 }
3499
3500 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3501                                     struct bnx2x_phy *phy,
3502                                     struct link_vars *vars)
3503 {
3504         u16 val;
3505         struct bnx2x *bp = params->bp;
3506         /* Read modify write pause advertizing */
3507         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3508
3509         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3510
3511         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3512         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3513         if ((vars->ieee_fc &
3514             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3515             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3516                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3517         }
3518         if ((vars->ieee_fc &
3519             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3520             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3521                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3522         }
3523         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3524         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3525 }
3526
3527 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3528 {                                               /*  LD      LP   */
3529         switch (pause_result) {                 /* ASYM P ASYM P */
3530         case 0xb:                               /*   1  0   1  1 */
3531                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3532                 break;
3533
3534         case 0xe:                               /*   1  1   1  0 */
3535                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3536                 break;
3537
3538         case 0x5:                               /*   0  1   0  1 */
3539         case 0x7:                               /*   0  1   1  1 */
3540         case 0xd:                               /*   1  1   0  1 */
3541         case 0xf:                               /*   1  1   1  1 */
3542                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3543                 break;
3544
3545         default:
3546                 break;
3547         }
3548         if (pause_result & (1<<0))
3549                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3550         if (pause_result & (1<<1))
3551                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3552
3553 }
3554
3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3556                                         struct link_params *params,
3557                                         struct link_vars *vars)
3558 {
3559         u16 ld_pause;           /* local */
3560         u16 lp_pause;           /* link partner */
3561         u16 pause_result;
3562         struct bnx2x *bp = params->bp;
3563         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3564                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3565                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3566         } else if (CHIP_IS_E3(bp) &&
3567                 SINGLE_MEDIA_DIRECT(params)) {
3568                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3569                 u16 gp_status, gp_mask;
3570                 bnx2x_cl45_read(bp, phy,
3571                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3572                                 &gp_status);
3573                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3574                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3575                         lane;
3576                 if ((gp_status & gp_mask) == gp_mask) {
3577                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3578                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3579                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3580                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3581                 } else {
3582                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3583                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3584                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3585                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3586                         ld_pause = ((ld_pause &
3587                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3588                                     << 3);
3589                         lp_pause = ((lp_pause &
3590                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3591                                     << 3);
3592                 }
3593         } else {
3594                 bnx2x_cl45_read(bp, phy,
3595                                 MDIO_AN_DEVAD,
3596                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3597                 bnx2x_cl45_read(bp, phy,
3598                                 MDIO_AN_DEVAD,
3599                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3600         }
3601         pause_result = (ld_pause &
3602                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3603         pause_result |= (lp_pause &
3604                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3605         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3606         bnx2x_pause_resolve(vars, pause_result);
3607
3608 }
3609
3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3611                                    struct link_params *params,
3612                                    struct link_vars *vars)
3613 {
3614         u8 ret = 0;
3615         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3616         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3617                 /* Update the advertised flow-controled of LD/LP in AN */
3618                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3619                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3620                 /* But set the flow-control result as the requested one */
3621                 vars->flow_ctrl = phy->req_flow_ctrl;
3622         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3623                 vars->flow_ctrl = params->req_fc_auto_adv;
3624         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3625                 ret = 1;
3626                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3627         }
3628         return ret;
3629 }
3630 /******************************************************************/
3631 /*                      Warpcore section                          */
3632 /******************************************************************/
3633 /* The init_internal_warpcore should mirror the xgxs,
3634  * i.e. reset the lane (if needed), set aer for the
3635  * init configuration, and set/clear SGMII flag. Internal
3636  * phy init is done purely in phy_init stage.
3637  */
3638 #define WC_TX_DRIVER(post2, idriver, ipre) \
3639         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3640          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3641          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3642
3643 #define WC_TX_FIR(post, main, pre) \
3644         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3645          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3646          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3647
3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3649                                          struct link_params *params,
3650                                          struct link_vars *vars)
3651 {
3652         struct bnx2x *bp = params->bp;
3653         u16 i;
3654         static struct bnx2x_reg_set reg_set[] = {
3655                 /* Step 1 - Program the TX/RX alignment markers */
3656                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3658                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3659                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3662                 /* Step 2 - Configure the NP registers */
3663                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3666                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3667                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3668                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3669                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3670                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3671                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3672         };
3673         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3674
3675         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3676                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3677
3678         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3679                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3680                                  reg_set[i].val);
3681
3682         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3683         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3684         bnx2x_update_link_attr(params, vars->link_attr_sync);
3685 }
3686
3687 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3688                                                struct link_params *params)
3689 {
3690         struct bnx2x *bp = params->bp;
3691
3692         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3693         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3695         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3696                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3697 }
3698
3699 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3700                                          struct link_params *params)
3701 {
3702         /* Restart autoneg on the leading lane only */
3703         struct bnx2x *bp = params->bp;
3704         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3705         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3706                           MDIO_AER_BLOCK_AER_REG, lane);
3707         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3708                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3709
3710         /* Restore AER */
3711         bnx2x_set_aer_mmd(params, phy);
3712 }
3713
3714 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3715                                         struct link_params *params,
3716                                         struct link_vars *vars) {
3717         u16 lane, i, cl72_ctrl, an_adv = 0;
3718         struct bnx2x *bp = params->bp;
3719         static struct bnx2x_reg_set reg_set[] = {
3720                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3721                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3722                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3723                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3724                 /* Disable Autoneg: re-enable it after adv is done. */
3725                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3726                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3727                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3728         };
3729         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3730         /* Set to default registers that may be overriden by 10G force */
3731         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3732                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3733                                  reg_set[i].val);
3734
3735         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3736                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3737         cl72_ctrl &= 0x08ff;
3738         cl72_ctrl |= 0x3800;
3739         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3740                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3741
3742         /* Check adding advertisement for 1G KX */
3743         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3744              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3745             (vars->line_speed == SPEED_1000)) {
3746                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3747                 an_adv |= (1<<5);
3748
3749                 /* Enable CL37 1G Parallel Detect */
3750                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3751                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3752         }
3753         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3754              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3755             (vars->line_speed ==  SPEED_10000)) {
3756                 /* Check adding advertisement for 10G KR */
3757                 an_adv |= (1<<7);
3758                 /* Enable 10G Parallel Detect */
3759                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3760                                   MDIO_AER_BLOCK_AER_REG, 0);
3761
3762                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3763                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3764                 bnx2x_set_aer_mmd(params, phy);
3765                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3766         }
3767
3768         /* Set Transmit PMD settings */
3769         lane = bnx2x_get_warpcore_lane(phy, params);
3770         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3772                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3773         /* Configure the next lane if dual mode */
3774         if (phy->flags & FLAGS_WC_DUAL_MODE)
3775                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3776                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3777                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3778         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3779                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3780                          0x03f0);
3781         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3782                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3783                          0x03f0);
3784
3785         /* Advertised speeds */
3786         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3787                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3788
3789         /* Advertised and set FEC (Forward Error Correction) */
3790         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3791                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3792                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3793                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3794
3795         /* Enable CL37 BAM */
3796         if (REG_RD(bp, params->shmem_base +
3797                    offsetof(struct shmem_region, dev_info.
3798                             port_hw_config[params->port].default_cfg)) &
3799             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3800                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3801                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3802                                          1);
3803                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3804         }
3805
3806         /* Advertise pause */
3807         bnx2x_ext_phy_set_pause(params, phy, vars);
3808         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3809         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3810                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3811
3812         /* Over 1G - AN local device user page 1 */
3813         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3815
3816         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3817              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3818             (phy->req_line_speed == SPEED_20000)) {
3819
3820                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3821                                   MDIO_AER_BLOCK_AER_REG, lane);
3822
3823                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3824                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3825                                          (1<<11));
3826
3827                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3829                 bnx2x_set_aer_mmd(params, phy);
3830
3831                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3832         }
3833
3834         /* Enable Autoneg: only on the main lane */
3835         bnx2x_warpcore_restart_AN_KR(phy, params);
3836 }
3837
3838 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3839                                       struct link_params *params,
3840                                       struct link_vars *vars)
3841 {
3842         struct bnx2x *bp = params->bp;
3843         u16 val16, i, lane;
3844         static struct bnx2x_reg_set reg_set[] = {
3845                 /* Disable Autoneg */
3846                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3847                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3848                         0x3f00},
3849                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3850                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3851                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3852                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3853                 /* Leave cl72 training enable, needed for KR */
3854                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3855         };
3856
3857         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3858                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3859                                  reg_set[i].val);
3860
3861         lane = bnx2x_get_warpcore_lane(phy, params);
3862         /* Global registers */
3863         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3864                           MDIO_AER_BLOCK_AER_REG, 0);
3865         /* Disable CL36 PCS Tx */
3866         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3867                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3868         val16 &= ~(0x0011 << lane);
3869         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3870                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3871
3872         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3873                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3874         val16 |= (0x0303 << (lane << 1));
3875         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3877         /* Restore AER */
3878         bnx2x_set_aer_mmd(params, phy);
3879         /* Set speed via PMA/PMD register */
3880         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3881                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3882
3883         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3884                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3885
3886         /* Enable encoded forced speed */
3887         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3889
3890         /* Turn TX scramble payload only the 64/66 scrambler */
3891         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3892                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3893
3894         /* Turn RX scramble payload only the 64/66 scrambler */
3895         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3896                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3897
3898         /* Set and clear loopback to cause a reset to 64/66 decoder */
3899         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3901         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3902                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3903
3904 }
3905
3906 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3907                                        struct link_params *params,
3908                                        u8 is_xfi)
3909 {
3910         struct bnx2x *bp = params->bp;
3911         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3912         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3913
3914         /* Hold rxSeqStart */
3915         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3916                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3917
3918         /* Hold tx_fifo_reset */
3919         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3920                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3921
3922         /* Disable CL73 AN */
3923         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3924
3925         /* Disable 100FX Enable and Auto-Detect */
3926         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3927                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3928
3929         /* Disable 100FX Idle detect */
3930         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3931                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3932
3933         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3934         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3935                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3936
3937         /* Turn off auto-detect & fiber mode */
3938         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3939                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3940                                   0xFFEE);
3941
3942         /* Set filter_force_link, disable_false_link and parallel_detect */
3943         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3944                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3945         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3946                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3947                          ((val | 0x0006) & 0xFFFE));
3948
3949         /* Set XFI / SFI */
3950         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3951                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3952
3953         misc1_val &= ~(0x1f);
3954
3955         if (is_xfi) {
3956                 misc1_val |= 0x5;
3957                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3958                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3959         } else {
3960                 cfg_tap_val = REG_RD(bp, params->shmem_base +
3961                                      offsetof(struct shmem_region, dev_info.
3962                                               port_hw_config[params->port].
3963                                               sfi_tap_values));
3964
3965                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3966
3967                 tx_drv_brdct = (cfg_tap_val &
3968                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3969                                PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3970
3971                 misc1_val |= 0x9;
3972
3973                 /* TAP values are controlled by nvram, if value there isn't 0 */
3974                 if (tx_equal)
3975                         tap_val = (u16)tx_equal;
3976                 else
3977                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3978
3979                 if (tx_drv_brdct)
3980                         tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
3981                                                      0x06);
3982                 else
3983                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3984         }
3985         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3986                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3987
3988         /* Set Transmit PMD settings */
3989         lane = bnx2x_get_warpcore_lane(phy, params);
3990         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3991                          MDIO_WC_REG_TX_FIR_TAP,
3992                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3993         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3994                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3995                          tx_driver_val);
3996
3997         /* Enable fiber mode, enable and invert sig_det */
3998         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3999                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4000
4001         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4002         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4003                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4004
4005         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4006
4007         /* 10G XFI Full Duplex */
4008         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4009                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4010
4011         /* Release tx_fifo_reset */
4012         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4013                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4014                                   0xFFFE);
4015         /* Release rxSeqStart */
4016         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4017                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4018 }
4019
4020 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4021                                              struct link_params *params)
4022 {
4023         u16 val;
4024         struct bnx2x *bp = params->bp;
4025         /* Set global registers, so set AER lane to 0 */
4026         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4027                           MDIO_AER_BLOCK_AER_REG, 0);
4028
4029         /* Disable sequencer */
4030         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4031                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4032
4033         bnx2x_set_aer_mmd(params, phy);
4034
4035         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4036                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4037         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4038                          MDIO_AN_REG_CTRL, 0);
4039         /* Turn off CL73 */
4040         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4041                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4042         val &= ~(1<<5);
4043         val |= (1<<6);
4044         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4045                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4046
4047         /* Set 20G KR2 force speed */
4048         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4049                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4050
4051         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4052                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4053
4054         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4055                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4056         val &= ~(3<<14);
4057         val |= (1<<15);
4058         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4060         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4061                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4062
4063         /* Enable sequencer (over lane 0) */
4064         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4065                           MDIO_AER_BLOCK_AER_REG, 0);
4066
4067         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4068                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4069
4070         bnx2x_set_aer_mmd(params, phy);
4071 }
4072
4073 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4074                                          struct bnx2x_phy *phy,
4075                                          u16 lane)
4076 {
4077         /* Rx0 anaRxControl1G */
4078         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4079                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4080
4081         /* Rx2 anaRxControl1G */
4082         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4083                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4084
4085         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4087
4088         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4089                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4090
4091         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4093
4094         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4096
4097         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4099
4100         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4101                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4102
4103         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4105
4106         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4108
4109         /* Serdes Digital Misc1 */
4110         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4111                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4112
4113         /* Serdes Digital4 Misc3 */
4114         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4115                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4116
4117         /* Set Transmit PMD settings */
4118         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4119                          MDIO_WC_REG_TX_FIR_TAP,
4120                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4121                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4122         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4123                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4124                          WC_TX_DRIVER(0x02, 0x02, 0x02));
4125 }
4126
4127 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4128                                            struct link_params *params,
4129                                            u8 fiber_mode,
4130                                            u8 always_autoneg)
4131 {
4132         struct bnx2x *bp = params->bp;
4133         u16 val16, digctrl_kx1, digctrl_kx2;
4134
4135         /* Clear XFI clock comp in non-10G single lane mode. */
4136         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4137                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4138
4139         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4140
4141         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4142                 /* SGMII Autoneg */
4143                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4144                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4145                                          0x1000);
4146                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4147         } else {
4148                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4149                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4150                 val16 &= 0xcebf;
4151                 switch (phy->req_line_speed) {
4152                 case SPEED_10:
4153                         break;
4154                 case SPEED_100:
4155                         val16 |= 0x2000;
4156                         break;
4157                 case SPEED_1000:
4158                         val16 |= 0x0040;
4159                         break;
4160                 default:
4161                         DP(NETIF_MSG_LINK,
4162                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4163                         return;
4164                 }
4165
4166                 if (phy->req_duplex == DUPLEX_FULL)
4167                         val16 |= 0x0100;
4168
4169                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4170                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4171
4172                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4173                                phy->req_line_speed);
4174                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4175                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4176                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4177         }
4178
4179         /* SGMII Slave mode and disable signal detect */
4180         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4181                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4182         if (fiber_mode)
4183                 digctrl_kx1 = 1;
4184         else
4185                 digctrl_kx1 &= 0xff4a;
4186
4187         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4188                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4189                         digctrl_kx1);
4190
4191         /* Turn off parallel detect */
4192         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4193                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4194         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4195                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4196                         (digctrl_kx2 & ~(1<<2)));
4197
4198         /* Re-enable parallel detect */
4199         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4200                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4201                         (digctrl_kx2 | (1<<2)));
4202
4203         /* Enable autodet */
4204         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4205                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4206                         (digctrl_kx1 | 0x10));
4207 }
4208
4209 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4210                                       struct bnx2x_phy *phy,
4211                                       u8 reset)
4212 {
4213         u16 val;
4214         /* Take lane out of reset after configuration is finished */
4215         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4216                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4217         if (reset)
4218                 val |= 0xC000;
4219         else
4220                 val &= 0x3FFF;
4221         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4222                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4223         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4224                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4225 }
4226 /* Clear SFI/XFI link settings registers */
4227 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4228                                       struct link_params *params,
4229                                       u16 lane)
4230 {
4231         struct bnx2x *bp = params->bp;
4232         u16 i;
4233         static struct bnx2x_reg_set wc_regs[] = {
4234                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4235                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4236                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4237                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4238                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4239                         0x0195},
4240                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4241                         0x0007},
4242                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4243                         0x0002},
4244                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4245                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4246                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4247                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4248         };
4249         /* Set XFI clock comp as default. */
4250         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4251                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4252
4253         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4254                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4255                                  wc_regs[i].val);
4256
4257         lane = bnx2x_get_warpcore_lane(phy, params);
4258         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4260
4261 }
4262
4263 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4264                                                 u32 chip_id,
4265                                                 u32 shmem_base, u8 port,
4266                                                 u8 *gpio_num, u8 *gpio_port)
4267 {
4268         u32 cfg_pin;
4269         *gpio_num = 0;
4270         *gpio_port = 0;
4271         if (CHIP_IS_E3(bp)) {
4272                 cfg_pin = (REG_RD(bp, shmem_base +
4273                                 offsetof(struct shmem_region,
4274                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4275                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4276                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4277
4278                 /* Should not happen. This function called upon interrupt
4279                  * triggered by GPIO ( since EPIO can only generate interrupts
4280                  * to MCP).
4281                  * So if this function was called and none of the GPIOs was set,
4282                  * it means the shit hit the fan.
4283                  */
4284                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4285                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4286                         DP(NETIF_MSG_LINK,
4287                            "No cfg pin %x for module detect indication\n",
4288                            cfg_pin);
4289                         return -EINVAL;
4290                 }
4291
4292                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4293                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4294         } else {
4295                 *gpio_num = MISC_REGISTERS_GPIO_3;
4296                 *gpio_port = port;
4297         }
4298
4299         return 0;
4300 }
4301
4302 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4303                                        struct link_params *params)
4304 {
4305         struct bnx2x *bp = params->bp;
4306         u8 gpio_num, gpio_port;
4307         u32 gpio_val;
4308         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4309                                       params->shmem_base, params->port,
4310                                       &gpio_num, &gpio_port) != 0)
4311                 return 0;
4312         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4313
4314         /* Call the handling function in case module is detected */
4315         if (gpio_val == 0)
4316                 return 1;
4317         else
4318                 return 0;
4319 }
4320 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4321                                      struct link_params *params)
4322 {
4323         u16 gp2_status_reg0, lane;
4324         struct bnx2x *bp = params->bp;
4325
4326         lane = bnx2x_get_warpcore_lane(phy, params);
4327
4328         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4329                                  &gp2_status_reg0);
4330
4331         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4332 }
4333
4334 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4335                                           struct link_params *params,
4336                                           struct link_vars *vars)
4337 {
4338         struct bnx2x *bp = params->bp;
4339         u32 serdes_net_if;
4340         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4341
4342         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4343
4344         if (!vars->turn_to_run_wc_rt)
4345                 return;
4346
4347         if (vars->rx_tx_asic_rst) {
4348                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4349                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4350                                 offsetof(struct shmem_region, dev_info.
4351                                 port_hw_config[params->port].default_cfg)) &
4352                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4353
4354                 switch (serdes_net_if) {
4355                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4356                         /* Do we get link yet? */
4357                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4358                                         &gp_status1);
4359                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4360                                 /*10G KR*/
4361                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4362
4363                         if (lnkup_kr || lnkup) {
4364                                 vars->rx_tx_asic_rst = 0;
4365                         } else {
4366                                 /* Reset the lane to see if link comes up.*/
4367                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4368                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4369
4370                                 /* Restart Autoneg */
4371                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4372                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4373
4374                                 vars->rx_tx_asic_rst--;
4375                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4376                                 vars->rx_tx_asic_rst);
4377                         }
4378                         break;
4379
4380                 default:
4381                         break;
4382                 }
4383
4384         } /*params->rx_tx_asic_rst*/
4385
4386 }
4387 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4388                                       struct link_params *params)
4389 {
4390         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4391         struct bnx2x *bp = params->bp;
4392         bnx2x_warpcore_clear_regs(phy, params, lane);
4393         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4394              SPEED_10000) &&
4395             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4396                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4397                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4398         } else {
4399                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4400                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4401         }
4402 }
4403
4404 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4405                                          struct bnx2x_phy *phy,
4406                                          u8 tx_en)
4407 {
4408         struct bnx2x *bp = params->bp;
4409         u32 cfg_pin;
4410         u8 port = params->port;
4411
4412         cfg_pin = REG_RD(bp, params->shmem_base +
4413                          offsetof(struct shmem_region,
4414                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4415                 PORT_HW_CFG_E3_TX_LASER_MASK;
4416         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4417         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4418
4419         /* For 20G, the expected pin to be used is 3 pins after the current */
4420         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4421         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4422                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4423 }
4424
4425 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4426                                        struct link_params *params,
4427                                        struct link_vars *vars)
4428 {
4429         struct bnx2x *bp = params->bp;
4430         u32 serdes_net_if;
4431         u8 fiber_mode;
4432         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4433         serdes_net_if = (REG_RD(bp, params->shmem_base +
4434                          offsetof(struct shmem_region, dev_info.
4435                                   port_hw_config[params->port].default_cfg)) &
4436                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4437         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4438                            "serdes_net_if = 0x%x\n",
4439                        vars->line_speed, serdes_net_if);
4440         bnx2x_set_aer_mmd(params, phy);
4441         bnx2x_warpcore_reset_lane(bp, phy, 1);
4442         vars->phy_flags |= PHY_XGXS_FLAG;
4443         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4444             (phy->req_line_speed &&
4445              ((phy->req_line_speed == SPEED_100) ||
4446               (phy->req_line_speed == SPEED_10)))) {
4447                 vars->phy_flags |= PHY_SGMII_FLAG;
4448                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4449                 bnx2x_warpcore_clear_regs(phy, params, lane);
4450                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4451         } else {
4452                 switch (serdes_net_if) {
4453                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4454                         /* Enable KR Auto Neg */
4455                         if (params->loopback_mode != LOOPBACK_EXT)
4456                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4457                         else {
4458                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4459                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4460                         }
4461                         break;
4462
4463                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4464                         bnx2x_warpcore_clear_regs(phy, params, lane);
4465                         if (vars->line_speed == SPEED_10000) {
4466                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4467                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4468                         } else {
4469                                 if (SINGLE_MEDIA_DIRECT(params)) {
4470                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4471                                         fiber_mode = 1;
4472                                 } else {
4473                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4474                                         fiber_mode = 0;
4475                                 }
4476                                 bnx2x_warpcore_set_sgmii_speed(phy,
4477                                                                 params,
4478                                                                 fiber_mode,
4479                                                                 0);
4480                         }
4481
4482                         break;
4483
4484                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4485                         /* Issue Module detection if module is plugged, or
4486                          * enabled transmitter to avoid current leakage in case
4487                          * no module is connected
4488                          */
4489                         if (bnx2x_is_sfp_module_plugged(phy, params))
4490                                 bnx2x_sfp_module_detection(phy, params);
4491                         else
4492                                 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
4493
4494                         bnx2x_warpcore_config_sfi(phy, params);
4495                         break;
4496
4497                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4498                         if (vars->line_speed != SPEED_20000) {
4499                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4500                                 return;
4501                         }
4502                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4503                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4504                         /* Issue Module detection */
4505
4506                         bnx2x_sfp_module_detection(phy, params);
4507                         break;
4508                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4509                         if (!params->loopback_mode) {
4510                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4511                         } else {
4512                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4513                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4514                         }
4515                         break;
4516                 default:
4517                         DP(NETIF_MSG_LINK,
4518                            "Unsupported Serdes Net Interface 0x%x\n",
4519                            serdes_net_if);
4520                         return;
4521                 }
4522         }
4523
4524         /* Take lane out of reset after configuration is finished */
4525         bnx2x_warpcore_reset_lane(bp, phy, 0);
4526         DP(NETIF_MSG_LINK, "Exit config init\n");
4527 }
4528
4529 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4530                                       struct link_params *params)
4531 {
4532         struct bnx2x *bp = params->bp;
4533         u16 val16, lane;
4534         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4535         bnx2x_set_mdio_emac_per_phy(bp, params);
4536         bnx2x_set_aer_mmd(params, phy);
4537         /* Global register */
4538         bnx2x_warpcore_reset_lane(bp, phy, 1);
4539
4540         /* Clear loopback settings (if any) */
4541         /* 10G & 20G */
4542         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4543                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4544
4545         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4546                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4547
4548         /* Update those 1-copy registers */
4549         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4550                           MDIO_AER_BLOCK_AER_REG, 0);
4551         /* Enable 1G MDIO (1-copy) */
4552         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4553                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4554                                   ~0x10);
4555
4556         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4557                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4558         lane = bnx2x_get_warpcore_lane(phy, params);
4559         /* Disable CL36 PCS Tx */
4560         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4561                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4562         val16 |= (0x11 << lane);
4563         if (phy->flags & FLAGS_WC_DUAL_MODE)
4564                 val16 |= (0x22 << lane);
4565         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4566                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4567
4568         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4569                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4570         val16 &= ~(0x0303 << (lane << 1));
4571         val16 |= (0x0101 << (lane << 1));
4572         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4573                 val16 &= ~(0x0c0c << (lane << 1));
4574                 val16 |= (0x0404 << (lane << 1));
4575         }
4576
4577         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4578                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4579         /* Restore AER */
4580         bnx2x_set_aer_mmd(params, phy);
4581
4582 }
4583
4584 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4585                                         struct link_params *params)
4586 {
4587         struct bnx2x *bp = params->bp;
4588         u16 val16;
4589         u32 lane;
4590         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4591                        params->loopback_mode, phy->req_line_speed);
4592
4593         if (phy->req_line_speed < SPEED_10000 ||
4594             phy->supported & SUPPORTED_20000baseKR2_Full) {
4595                 /* 10/100/1000/20G-KR2 */
4596
4597                 /* Update those 1-copy registers */
4598                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4599                                   MDIO_AER_BLOCK_AER_REG, 0);
4600                 /* Enable 1G MDIO (1-copy) */
4601                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4602                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4603                                          0x10);
4604                 /* Set 1G loopback based on lane (1-copy) */
4605                 lane = bnx2x_get_warpcore_lane(phy, params);
4606                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4607                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4608                 val16 |= (1<<lane);
4609                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4610                         val16 |= (2<<lane);
4611                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4612                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4613                                  val16);
4614
4615                 /* Switch back to 4-copy registers */
4616                 bnx2x_set_aer_mmd(params, phy);
4617         } else {
4618                 /* 10G / 20G-DXGXS */
4619                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4620                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4621                                          0x4000);
4622                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4623                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4624         }
4625 }
4626
4627
4628
4629 static void bnx2x_sync_link(struct link_params *params,
4630                              struct link_vars *vars)
4631 {
4632         struct bnx2x *bp = params->bp;
4633         u8 link_10g_plus;
4634         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4635                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4636         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4637         if (vars->link_up) {
4638                 DP(NETIF_MSG_LINK, "phy link up\n");
4639
4640                 vars->phy_link_up = 1;
4641                 vars->duplex = DUPLEX_FULL;
4642                 switch (vars->link_status &
4643                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4644                 case LINK_10THD:
4645                         vars->duplex = DUPLEX_HALF;
4646                         /* Fall thru */
4647                 case LINK_10TFD:
4648                         vars->line_speed = SPEED_10;
4649                         break;
4650
4651                 case LINK_100TXHD:
4652                         vars->duplex = DUPLEX_HALF;
4653                         /* Fall thru */
4654                 case LINK_100T4:
4655                 case LINK_100TXFD:
4656                         vars->line_speed = SPEED_100;
4657                         break;
4658
4659                 case LINK_1000THD:
4660                         vars->duplex = DUPLEX_HALF;
4661                         /* Fall thru */
4662                 case LINK_1000TFD:
4663                         vars->line_speed = SPEED_1000;
4664                         break;
4665
4666                 case LINK_2500THD:
4667                         vars->duplex = DUPLEX_HALF;
4668                         /* Fall thru */
4669                 case LINK_2500TFD:
4670                         vars->line_speed = SPEED_2500;
4671                         break;
4672
4673                 case LINK_10GTFD:
4674                         vars->line_speed = SPEED_10000;
4675                         break;
4676                 case LINK_20GTFD:
4677                         vars->line_speed = SPEED_20000;
4678                         break;
4679                 default:
4680                         break;
4681                 }
4682                 vars->flow_ctrl = 0;
4683                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4684                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4685
4686                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4687                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4688
4689                 if (!vars->flow_ctrl)
4690                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4691
4692                 if (vars->line_speed &&
4693                     ((vars->line_speed == SPEED_10) ||
4694                      (vars->line_speed == SPEED_100))) {
4695                         vars->phy_flags |= PHY_SGMII_FLAG;
4696                 } else {
4697                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4698                 }
4699                 if (vars->line_speed &&
4700                     USES_WARPCORE(bp) &&
4701                     (vars->line_speed == SPEED_1000))
4702                         vars->phy_flags |= PHY_SGMII_FLAG;
4703                 /* Anything 10 and over uses the bmac */
4704                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4705
4706                 if (link_10g_plus) {
4707                         if (USES_WARPCORE(bp))
4708                                 vars->mac_type = MAC_TYPE_XMAC;
4709                         else
4710                                 vars->mac_type = MAC_TYPE_BMAC;
4711                 } else {
4712                         if (USES_WARPCORE(bp))
4713                                 vars->mac_type = MAC_TYPE_UMAC;
4714                         else
4715                                 vars->mac_type = MAC_TYPE_EMAC;
4716                 }
4717         } else { /* Link down */
4718                 DP(NETIF_MSG_LINK, "phy link down\n");
4719
4720                 vars->phy_link_up = 0;
4721
4722                 vars->line_speed = 0;
4723                 vars->duplex = DUPLEX_FULL;
4724                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4725
4726                 /* Indicate no mac active */
4727                 vars->mac_type = MAC_TYPE_NONE;
4728                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4729                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4730                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4731                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4732         }
4733 }
4734
4735 void bnx2x_link_status_update(struct link_params *params,
4736                               struct link_vars *vars)
4737 {
4738         struct bnx2x *bp = params->bp;
4739         u8 port = params->port;
4740         u32 sync_offset, media_types;
4741         /* Update PHY configuration */
4742         set_phy_vars(params, vars);
4743
4744         vars->link_status = REG_RD(bp, params->shmem_base +
4745                                    offsetof(struct shmem_region,
4746                                             port_mb[port].link_status));
4747
4748         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4749         if (params->loopback_mode != LOOPBACK_NONE &&
4750             params->loopback_mode != LOOPBACK_EXT)
4751                 vars->link_status |= LINK_STATUS_LINK_UP;
4752
4753         if (bnx2x_eee_has_cap(params))
4754                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4755                                           offsetof(struct shmem2_region,
4756                                                    eee_status[params->port]));
4757
4758         vars->phy_flags = PHY_XGXS_FLAG;
4759         bnx2x_sync_link(params, vars);
4760         /* Sync media type */
4761         sync_offset = params->shmem_base +
4762                         offsetof(struct shmem_region,
4763                                  dev_info.port_hw_config[port].media_type);
4764         media_types = REG_RD(bp, sync_offset);
4765
4766         params->phy[INT_PHY].media_type =
4767                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4768                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4769         params->phy[EXT_PHY1].media_type =
4770                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4771                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4772         params->phy[EXT_PHY2].media_type =
4773                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4774                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4775         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4776
4777         /* Sync AEU offset */
4778         sync_offset = params->shmem_base +
4779                         offsetof(struct shmem_region,
4780                                  dev_info.port_hw_config[port].aeu_int_mask);
4781
4782         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4783
4784         /* Sync PFC status */
4785         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4786                 params->feature_config_flags |=
4787                                         FEATURE_CONFIG_PFC_ENABLED;
4788         else
4789                 params->feature_config_flags &=
4790                                         ~FEATURE_CONFIG_PFC_ENABLED;
4791
4792         if (SHMEM2_HAS(bp, link_attr_sync))
4793                 vars->link_attr_sync = SHMEM2_RD(bp,
4794                                                  link_attr_sync[params->port]);
4795
4796         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4797                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4798         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4799                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4800 }
4801
4802 static void bnx2x_set_master_ln(struct link_params *params,
4803                                 struct bnx2x_phy *phy)
4804 {
4805         struct bnx2x *bp = params->bp;
4806         u16 new_master_ln, ser_lane;
4807         ser_lane = ((params->lane_config &
4808                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4809                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4810
4811         /* Set the master_ln for AN */
4812         CL22_RD_OVER_CL45(bp, phy,
4813                           MDIO_REG_BANK_XGXS_BLOCK2,
4814                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4815                           &new_master_ln);
4816
4817         CL22_WR_OVER_CL45(bp, phy,
4818                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4819                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4820                           (new_master_ln | ser_lane));
4821 }
4822
4823 static int bnx2x_reset_unicore(struct link_params *params,
4824                                struct bnx2x_phy *phy,
4825                                u8 set_serdes)
4826 {
4827         struct bnx2x *bp = params->bp;
4828         u16 mii_control;
4829         u16 i;
4830         CL22_RD_OVER_CL45(bp, phy,
4831                           MDIO_REG_BANK_COMBO_IEEE0,
4832                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4833
4834         /* Reset the unicore */
4835         CL22_WR_OVER_CL45(bp, phy,
4836                           MDIO_REG_BANK_COMBO_IEEE0,
4837                           MDIO_COMBO_IEEE0_MII_CONTROL,
4838                           (mii_control |
4839                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4840         if (set_serdes)
4841                 bnx2x_set_serdes_access(bp, params->port);
4842
4843         /* Wait for the reset to self clear */
4844         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4845                 udelay(5);
4846
4847                 /* The reset erased the previous bank value */
4848                 CL22_RD_OVER_CL45(bp, phy,
4849                                   MDIO_REG_BANK_COMBO_IEEE0,
4850                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4851                                   &mii_control);
4852
4853                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4854                         udelay(5);
4855                         return 0;
4856                 }
4857         }
4858
4859         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4860                               " Port %d\n",
4861                          params->port);
4862         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4863         return -EINVAL;
4864
4865 }
4866
4867 static void bnx2x_set_swap_lanes(struct link_params *params,
4868                                  struct bnx2x_phy *phy)
4869 {
4870         struct bnx2x *bp = params->bp;
4871         /* Each two bits represents a lane number:
4872          * No swap is 0123 => 0x1b no need to enable the swap
4873          */
4874         u16 rx_lane_swap, tx_lane_swap;
4875
4876         rx_lane_swap = ((params->lane_config &
4877                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4878                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4879         tx_lane_swap = ((params->lane_config &
4880                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4881                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4882
4883         if (rx_lane_swap != 0x1b) {
4884                 CL22_WR_OVER_CL45(bp, phy,
4885                                   MDIO_REG_BANK_XGXS_BLOCK2,
4886                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4887                                   (rx_lane_swap |
4888                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4889                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4890         } else {
4891                 CL22_WR_OVER_CL45(bp, phy,
4892                                   MDIO_REG_BANK_XGXS_BLOCK2,
4893                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4894         }
4895
4896         if (tx_lane_swap != 0x1b) {
4897                 CL22_WR_OVER_CL45(bp, phy,
4898                                   MDIO_REG_BANK_XGXS_BLOCK2,
4899                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4900                                   (tx_lane_swap |
4901                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4902         } else {
4903                 CL22_WR_OVER_CL45(bp, phy,
4904                                   MDIO_REG_BANK_XGXS_BLOCK2,
4905                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4906         }
4907 }
4908
4909 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4910                                          struct link_params *params)
4911 {
4912         struct bnx2x *bp = params->bp;
4913         u16 control2;
4914         CL22_RD_OVER_CL45(bp, phy,
4915                           MDIO_REG_BANK_SERDES_DIGITAL,
4916                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4917                           &control2);
4918         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4919                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4920         else
4921                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4922         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4923                 phy->speed_cap_mask, control2);
4924         CL22_WR_OVER_CL45(bp, phy,
4925                           MDIO_REG_BANK_SERDES_DIGITAL,
4926                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4927                           control2);
4928
4929         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4930              (phy->speed_cap_mask &
4931                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4932                 DP(NETIF_MSG_LINK, "XGXS\n");
4933
4934                 CL22_WR_OVER_CL45(bp, phy,
4935                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4936                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4937                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4938
4939                 CL22_RD_OVER_CL45(bp, phy,
4940                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4941                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4942                                   &control2);
4943
4944
4945                 control2 |=
4946                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4947
4948                 CL22_WR_OVER_CL45(bp, phy,
4949                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4950                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4951                                   control2);
4952
4953                 /* Disable parallel detection of HiG */
4954                 CL22_WR_OVER_CL45(bp, phy,
4955                                   MDIO_REG_BANK_XGXS_BLOCK2,
4956                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4957                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4958                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4959         }
4960 }
4961
4962 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4963                               struct link_params *params,
4964                               struct link_vars *vars,
4965                               u8 enable_cl73)
4966 {
4967         struct bnx2x *bp = params->bp;
4968         u16 reg_val;
4969
4970         /* CL37 Autoneg */
4971         CL22_RD_OVER_CL45(bp, phy,
4972                           MDIO_REG_BANK_COMBO_IEEE0,
4973                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4974
4975         /* CL37 Autoneg Enabled */
4976         if (vars->line_speed == SPEED_AUTO_NEG)
4977                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4978         else /* CL37 Autoneg Disabled */
4979                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4980                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4981
4982         CL22_WR_OVER_CL45(bp, phy,
4983                           MDIO_REG_BANK_COMBO_IEEE0,
4984                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4985
4986         /* Enable/Disable Autodetection */
4987
4988         CL22_RD_OVER_CL45(bp, phy,
4989                           MDIO_REG_BANK_SERDES_DIGITAL,
4990                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4991         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4992                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4993         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4994         if (vars->line_speed == SPEED_AUTO_NEG)
4995                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4996         else
4997                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4998
4999         CL22_WR_OVER_CL45(bp, phy,
5000                           MDIO_REG_BANK_SERDES_DIGITAL,
5001                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5002
5003         /* Enable TetonII and BAM autoneg */
5004         CL22_RD_OVER_CL45(bp, phy,
5005                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5006                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5007                           &reg_val);
5008         if (vars->line_speed == SPEED_AUTO_NEG) {
5009                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5010                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5011                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5012         } else {
5013                 /* TetonII and BAM Autoneg Disabled */
5014                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5015                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5016         }
5017         CL22_WR_OVER_CL45(bp, phy,
5018                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5019                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5020                           reg_val);
5021
5022         if (enable_cl73) {
5023                 /* Enable Cl73 FSM status bits */
5024                 CL22_WR_OVER_CL45(bp, phy,
5025                                   MDIO_REG_BANK_CL73_USERB0,
5026                                   MDIO_CL73_USERB0_CL73_UCTRL,
5027                                   0xe);
5028
5029                 /* Enable BAM Station Manager*/
5030                 CL22_WR_OVER_CL45(bp, phy,
5031                         MDIO_REG_BANK_CL73_USERB0,
5032                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5033                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5034                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5035                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5036
5037                 /* Advertise CL73 link speeds */
5038                 CL22_RD_OVER_CL45(bp, phy,
5039                                   MDIO_REG_BANK_CL73_IEEEB1,
5040                                   MDIO_CL73_IEEEB1_AN_ADV2,
5041                                   &reg_val);
5042                 if (phy->speed_cap_mask &
5043                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5044                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5045                 if (phy->speed_cap_mask &
5046                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5047                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5048
5049                 CL22_WR_OVER_CL45(bp, phy,
5050                                   MDIO_REG_BANK_CL73_IEEEB1,
5051                                   MDIO_CL73_IEEEB1_AN_ADV2,
5052                                   reg_val);
5053
5054                 /* CL73 Autoneg Enabled */
5055                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5056
5057         } else /* CL73 Autoneg Disabled */
5058                 reg_val = 0;
5059
5060         CL22_WR_OVER_CL45(bp, phy,
5061                           MDIO_REG_BANK_CL73_IEEEB0,
5062                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5063 }
5064
5065 /* Program SerDes, forced speed */
5066 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5067                                  struct link_params *params,
5068                                  struct link_vars *vars)
5069 {
5070         struct bnx2x *bp = params->bp;
5071         u16 reg_val;
5072
5073         /* Program duplex, disable autoneg and sgmii*/
5074         CL22_RD_OVER_CL45(bp, phy,
5075                           MDIO_REG_BANK_COMBO_IEEE0,
5076                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5077         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5078                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5079                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5080         if (phy->req_duplex == DUPLEX_FULL)
5081                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5082         CL22_WR_OVER_CL45(bp, phy,
5083                           MDIO_REG_BANK_COMBO_IEEE0,
5084                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5085
5086         /* Program speed
5087          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5088          */
5089         CL22_RD_OVER_CL45(bp, phy,
5090                           MDIO_REG_BANK_SERDES_DIGITAL,
5091                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5092         /* Clearing the speed value before setting the right speed */
5093         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5094
5095         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5096                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5097
5098         if (!((vars->line_speed == SPEED_1000) ||
5099               (vars->line_speed == SPEED_100) ||
5100               (vars->line_speed == SPEED_10))) {
5101
5102                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5103                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5104                 if (vars->line_speed == SPEED_10000)
5105                         reg_val |=
5106                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5107         }
5108
5109         CL22_WR_OVER_CL45(bp, phy,
5110                           MDIO_REG_BANK_SERDES_DIGITAL,
5111                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5112
5113 }
5114
5115 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5116                                               struct link_params *params)
5117 {
5118         struct bnx2x *bp = params->bp;
5119         u16 val = 0;
5120
5121         /* Set extended capabilities */
5122         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5123                 val |= MDIO_OVER_1G_UP1_2_5G;
5124         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5125                 val |= MDIO_OVER_1G_UP1_10G;
5126         CL22_WR_OVER_CL45(bp, phy,
5127                           MDIO_REG_BANK_OVER_1G,
5128                           MDIO_OVER_1G_UP1, val);
5129
5130         CL22_WR_OVER_CL45(bp, phy,
5131                           MDIO_REG_BANK_OVER_1G,
5132                           MDIO_OVER_1G_UP3, 0x400);
5133 }
5134
5135 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5136                                               struct link_params *params,
5137                                               u16 ieee_fc)
5138 {
5139         struct bnx2x *bp = params->bp;
5140         u16 val;
5141         /* For AN, we are always publishing full duplex */
5142
5143         CL22_WR_OVER_CL45(bp, phy,
5144                           MDIO_REG_BANK_COMBO_IEEE0,
5145                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5146         CL22_RD_OVER_CL45(bp, phy,
5147                           MDIO_REG_BANK_CL73_IEEEB1,
5148                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5149         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5150         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5151         CL22_WR_OVER_CL45(bp, phy,
5152                           MDIO_REG_BANK_CL73_IEEEB1,
5153                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5154 }
5155
5156 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5157                                   struct link_params *params,
5158                                   u8 enable_cl73)
5159 {
5160         struct bnx2x *bp = params->bp;
5161         u16 mii_control;
5162
5163         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5164         /* Enable and restart BAM/CL37 aneg */
5165
5166         if (enable_cl73) {
5167                 CL22_RD_OVER_CL45(bp, phy,
5168                                   MDIO_REG_BANK_CL73_IEEEB0,
5169                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5170                                   &mii_control);
5171
5172                 CL22_WR_OVER_CL45(bp, phy,
5173                                   MDIO_REG_BANK_CL73_IEEEB0,
5174                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5175                                   (mii_control |
5176                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5177                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5178         } else {
5179
5180                 CL22_RD_OVER_CL45(bp, phy,
5181                                   MDIO_REG_BANK_COMBO_IEEE0,
5182                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5183                                   &mii_control);
5184                 DP(NETIF_MSG_LINK,
5185                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5186                          mii_control);
5187                 CL22_WR_OVER_CL45(bp, phy,
5188                                   MDIO_REG_BANK_COMBO_IEEE0,
5189                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5190                                   (mii_control |
5191                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5192                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5193         }
5194 }
5195
5196 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5197                                            struct link_params *params,
5198                                            struct link_vars *vars)
5199 {
5200         struct bnx2x *bp = params->bp;
5201         u16 control1;
5202
5203         /* In SGMII mode, the unicore is always slave */
5204
5205         CL22_RD_OVER_CL45(bp, phy,
5206                           MDIO_REG_BANK_SERDES_DIGITAL,
5207                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5208                           &control1);
5209         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5210         /* Set sgmii mode (and not fiber) */
5211         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5212                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5213                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5214         CL22_WR_OVER_CL45(bp, phy,
5215                           MDIO_REG_BANK_SERDES_DIGITAL,
5216                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5217                           control1);
5218
5219         /* If forced speed */
5220         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5221                 /* Set speed, disable autoneg */
5222                 u16 mii_control;
5223
5224                 CL22_RD_OVER_CL45(bp, phy,
5225                                   MDIO_REG_BANK_COMBO_IEEE0,
5226                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5227                                   &mii_control);
5228                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5229                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5230                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5231
5232                 switch (vars->line_speed) {
5233                 case SPEED_100:
5234                         mii_control |=
5235                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5236                         break;
5237                 case SPEED_1000:
5238                         mii_control |=
5239                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5240                         break;
5241                 case SPEED_10:
5242                         /* There is nothing to set for 10M */
5243                         break;
5244                 default:
5245                         /* Invalid speed for SGMII */
5246                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5247                                   vars->line_speed);
5248                         break;
5249                 }
5250
5251                 /* Setting the full duplex */
5252                 if (phy->req_duplex == DUPLEX_FULL)
5253                         mii_control |=
5254                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5255                 CL22_WR_OVER_CL45(bp, phy,
5256                                   MDIO_REG_BANK_COMBO_IEEE0,
5257                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5258                                   mii_control);
5259
5260         } else { /* AN mode */
5261                 /* Enable and restart AN */
5262                 bnx2x_restart_autoneg(phy, params, 0);
5263         }
5264 }
5265
5266 /* Link management
5267  */
5268 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5269                                              struct link_params *params)
5270 {
5271         struct bnx2x *bp = params->bp;
5272         u16 pd_10g, status2_1000x;
5273         if (phy->req_line_speed != SPEED_AUTO_NEG)
5274                 return 0;
5275         CL22_RD_OVER_CL45(bp, phy,
5276                           MDIO_REG_BANK_SERDES_DIGITAL,
5277                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5278                           &status2_1000x);
5279         CL22_RD_OVER_CL45(bp, phy,
5280                           MDIO_REG_BANK_SERDES_DIGITAL,
5281                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5282                           &status2_1000x);
5283         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5284                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5285                          params->port);
5286                 return 1;
5287         }
5288
5289         CL22_RD_OVER_CL45(bp, phy,
5290                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5291                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5292                           &pd_10g);
5293
5294         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5295                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5296                          params->port);
5297                 return 1;
5298         }
5299         return 0;
5300 }
5301
5302 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5303                                 struct link_params *params,
5304                                 struct link_vars *vars,
5305                                 u32 gp_status)
5306 {
5307         u16 ld_pause;   /* local driver */
5308         u16 lp_pause;   /* link partner */
5309         u16 pause_result;
5310         struct bnx2x *bp = params->bp;
5311         if ((gp_status &
5312              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5313               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5314             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5315              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5316
5317                 CL22_RD_OVER_CL45(bp, phy,
5318                                   MDIO_REG_BANK_CL73_IEEEB1,
5319                                   MDIO_CL73_IEEEB1_AN_ADV1,
5320                                   &ld_pause);
5321                 CL22_RD_OVER_CL45(bp, phy,
5322                                   MDIO_REG_BANK_CL73_IEEEB1,
5323                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5324                                   &lp_pause);
5325                 pause_result = (ld_pause &
5326                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5327                 pause_result |= (lp_pause &
5328                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5329                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5330         } else {
5331                 CL22_RD_OVER_CL45(bp, phy,
5332                                   MDIO_REG_BANK_COMBO_IEEE0,
5333                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5334                                   &ld_pause);
5335                 CL22_RD_OVER_CL45(bp, phy,
5336                         MDIO_REG_BANK_COMBO_IEEE0,
5337                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5338                         &lp_pause);
5339                 pause_result = (ld_pause &
5340                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5341                 pause_result |= (lp_pause &
5342                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5343                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5344         }
5345         bnx2x_pause_resolve(vars, pause_result);
5346
5347 }
5348
5349 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5350                                     struct link_params *params,
5351                                     struct link_vars *vars,
5352                                     u32 gp_status)
5353 {
5354         struct bnx2x *bp = params->bp;
5355         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5356
5357         /* Resolve from gp_status in case of AN complete and not sgmii */
5358         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5359                 /* Update the advertised flow-controled of LD/LP in AN */
5360                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5361                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5362                 /* But set the flow-control result as the requested one */
5363                 vars->flow_ctrl = phy->req_flow_ctrl;
5364         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5365                 vars->flow_ctrl = params->req_fc_auto_adv;
5366         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5367                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5368                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5369                         vars->flow_ctrl = params->req_fc_auto_adv;
5370                         return;
5371                 }
5372                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5373         }
5374         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5375 }
5376
5377 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5378                                          struct link_params *params)
5379 {
5380         struct bnx2x *bp = params->bp;
5381         u16 rx_status, ustat_val, cl37_fsm_received;
5382         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5383         /* Step 1: Make sure signal is detected */
5384         CL22_RD_OVER_CL45(bp, phy,
5385                           MDIO_REG_BANK_RX0,
5386                           MDIO_RX0_RX_STATUS,
5387                           &rx_status);
5388         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5389             (MDIO_RX0_RX_STATUS_SIGDET)) {
5390                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5391                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5392                 CL22_WR_OVER_CL45(bp, phy,
5393                                   MDIO_REG_BANK_CL73_IEEEB0,
5394                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5395                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5396                 return;
5397         }
5398         /* Step 2: Check CL73 state machine */
5399         CL22_RD_OVER_CL45(bp, phy,
5400                           MDIO_REG_BANK_CL73_USERB0,
5401                           MDIO_CL73_USERB0_CL73_USTAT1,
5402                           &ustat_val);
5403         if ((ustat_val &
5404              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5405               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5406             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5407               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5408                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5409                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5410                 return;
5411         }
5412         /* Step 3: Check CL37 Message Pages received to indicate LP
5413          * supports only CL37
5414          */
5415         CL22_RD_OVER_CL45(bp, phy,
5416                           MDIO_REG_BANK_REMOTE_PHY,
5417                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5418                           &cl37_fsm_received);
5419         if ((cl37_fsm_received &
5420              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5421              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5422             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5423               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5424                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5425                              "misc_rx_status(0x8330) = 0x%x\n",
5426                          cl37_fsm_received);
5427                 return;
5428         }
5429         /* The combined cl37/cl73 fsm state information indicating that
5430          * we are connected to a device which does not support cl73, but
5431          * does support cl37 BAM. In this case we disable cl73 and
5432          * restart cl37 auto-neg
5433          */
5434
5435         /* Disable CL73 */
5436         CL22_WR_OVER_CL45(bp, phy,
5437                           MDIO_REG_BANK_CL73_IEEEB0,
5438                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5439                           0);
5440         /* Restart CL37 autoneg */
5441         bnx2x_restart_autoneg(phy, params, 0);
5442         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5443 }
5444
5445 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5446                                   struct link_params *params,
5447                                   struct link_vars *vars,
5448                                   u32 gp_status)
5449 {
5450         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5451                 vars->link_status |=
5452                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5453
5454         if (bnx2x_direct_parallel_detect_used(phy, params))
5455                 vars->link_status |=
5456                         LINK_STATUS_PARALLEL_DETECTION_USED;
5457 }
5458 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5459                                      struct link_params *params,
5460                                       struct link_vars *vars,
5461                                       u16 is_link_up,
5462                                       u16 speed_mask,
5463                                       u16 is_duplex)
5464 {
5465         struct bnx2x *bp = params->bp;
5466         if (phy->req_line_speed == SPEED_AUTO_NEG)
5467                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5468         if (is_link_up) {
5469                 DP(NETIF_MSG_LINK, "phy link up\n");
5470
5471                 vars->phy_link_up = 1;
5472                 vars->link_status |= LINK_STATUS_LINK_UP;
5473
5474                 switch (speed_mask) {
5475                 case GP_STATUS_10M:
5476                         vars->line_speed = SPEED_10;
5477                         if (is_duplex == DUPLEX_FULL)
5478                                 vars->link_status |= LINK_10TFD;
5479                         else
5480                                 vars->link_status |= LINK_10THD;
5481                         break;
5482
5483                 case GP_STATUS_100M:
5484                         vars->line_speed = SPEED_100;
5485                         if (is_duplex == DUPLEX_FULL)
5486                                 vars->link_status |= LINK_100TXFD;
5487                         else
5488                                 vars->link_status |= LINK_100TXHD;
5489                         break;
5490
5491                 case GP_STATUS_1G:
5492                 case GP_STATUS_1G_KX:
5493                         vars->line_speed = SPEED_1000;
5494                         if (is_duplex == DUPLEX_FULL)
5495                                 vars->link_status |= LINK_1000TFD;
5496                         else
5497                                 vars->link_status |= LINK_1000THD;
5498                         break;
5499
5500                 case GP_STATUS_2_5G:
5501                         vars->line_speed = SPEED_2500;
5502                         if (is_duplex == DUPLEX_FULL)
5503                                 vars->link_status |= LINK_2500TFD;
5504                         else
5505                                 vars->link_status |= LINK_2500THD;
5506                         break;
5507
5508                 case GP_STATUS_5G:
5509                 case GP_STATUS_6G:
5510                         DP(NETIF_MSG_LINK,
5511                                  "link speed unsupported  gp_status 0x%x\n",
5512                                   speed_mask);
5513                         return -EINVAL;
5514
5515                 case GP_STATUS_10G_KX4:
5516                 case GP_STATUS_10G_HIG:
5517                 case GP_STATUS_10G_CX4:
5518                 case GP_STATUS_10G_KR:
5519                 case GP_STATUS_10G_SFI:
5520                 case GP_STATUS_10G_XFI:
5521                         vars->line_speed = SPEED_10000;
5522                         vars->link_status |= LINK_10GTFD;
5523                         break;
5524                 case GP_STATUS_20G_DXGXS:
5525                 case GP_STATUS_20G_KR2:
5526                         vars->line_speed = SPEED_20000;
5527                         vars->link_status |= LINK_20GTFD;
5528                         break;
5529                 default:
5530                         DP(NETIF_MSG_LINK,
5531                                   "link speed unsupported gp_status 0x%x\n",
5532                                   speed_mask);
5533                         return -EINVAL;
5534                 }
5535         } else { /* link_down */
5536                 DP(NETIF_MSG_LINK, "phy link down\n");
5537
5538                 vars->phy_link_up = 0;
5539
5540                 vars->duplex = DUPLEX_FULL;
5541                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5542                 vars->mac_type = MAC_TYPE_NONE;
5543         }
5544         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5545                     vars->phy_link_up, vars->line_speed);
5546         return 0;
5547 }
5548
5549 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5550                                       struct link_params *params,
5551                                       struct link_vars *vars)
5552 {
5553         struct bnx2x *bp = params->bp;
5554
5555         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5556         int rc = 0;
5557
5558         /* Read gp_status */
5559         CL22_RD_OVER_CL45(bp, phy,
5560                           MDIO_REG_BANK_GP_STATUS,
5561                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5562                           &gp_status);
5563         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5564                 duplex = DUPLEX_FULL;
5565         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5566                 link_up = 1;
5567         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5568         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5569                        gp_status, link_up, speed_mask);
5570         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5571                                          duplex);
5572         if (rc == -EINVAL)
5573                 return rc;
5574
5575         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5576                 if (SINGLE_MEDIA_DIRECT(params)) {
5577                         vars->duplex = duplex;
5578                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5579                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5580                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5581                                                       gp_status);
5582                 }
5583         } else { /* Link_down */
5584                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5585                     SINGLE_MEDIA_DIRECT(params)) {
5586                         /* Check signal is detected */
5587                         bnx2x_check_fallback_to_cl37(phy, params);
5588                 }
5589         }
5590
5591         /* Read LP advertised speeds*/
5592         if (SINGLE_MEDIA_DIRECT(params) &&
5593             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5594                 u16 val;
5595
5596                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5597                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5598
5599                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5600                         vars->link_status |=
5601                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5602                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5603                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5604                         vars->link_status |=
5605                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5606
5607                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5608                                   MDIO_OVER_1G_LP_UP1, &val);
5609
5610                 if (val & MDIO_OVER_1G_UP1_2_5G)
5611                         vars->link_status |=
5612                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5613                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5614                         vars->link_status |=
5615                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5616         }
5617
5618         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5619                    vars->duplex, vars->flow_ctrl, vars->link_status);
5620         return rc;
5621 }
5622
5623 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5624                                      struct link_params *params,
5625                                      struct link_vars *vars)
5626 {
5627         struct bnx2x *bp = params->bp;
5628         u8 lane;
5629         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5630         int rc = 0;
5631         lane = bnx2x_get_warpcore_lane(phy, params);
5632         /* Read gp_status */
5633         if ((params->loopback_mode) &&
5634             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5635                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5636                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5637                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5638                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5639                 link_up &= 0x1;
5640         } else if ((phy->req_line_speed > SPEED_10000) &&
5641                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5642                 u16 temp_link_up;
5643                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5644                                 1, &temp_link_up);
5645                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5646                                 1, &link_up);
5647                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5648                                temp_link_up, link_up);
5649                 link_up &= (1<<2);
5650                 if (link_up)
5651                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5652         } else {
5653                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5654                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5655                                 &gp_status1);
5656                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5657                 /* Check for either KR, 1G, or AN up. */
5658                 link_up = ((gp_status1 >> 8) |
5659                            (gp_status1 >> 12) |
5660                            (gp_status1)) &
5661                         (1 << lane);
5662                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5663                         u16 an_link;
5664                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5665                                         MDIO_AN_REG_STATUS, &an_link);
5666                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5667                                         MDIO_AN_REG_STATUS, &an_link);
5668                         link_up |= (an_link & (1<<2));
5669                 }
5670                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5671                         u16 pd, gp_status4;
5672                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5673                                 /* Check Autoneg complete */
5674                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5675                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5676                                                 &gp_status4);
5677                                 if (gp_status4 & ((1<<12)<<lane))
5678                                         vars->link_status |=
5679                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5680
5681                                 /* Check parallel detect used */
5682                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5683                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5684                                                 &pd);
5685                                 if (pd & (1<<15))
5686                                         vars->link_status |=
5687                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5688                         }
5689                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5690                         vars->duplex = duplex;
5691                 }
5692         }
5693
5694         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5695             SINGLE_MEDIA_DIRECT(params)) {
5696                 u16 val;
5697
5698                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5699                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5700
5701                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5702                         vars->link_status |=
5703                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5704                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5705                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5706                         vars->link_status |=
5707                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5708
5709                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5710                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5711
5712                 if (val & MDIO_OVER_1G_UP1_2_5G)
5713                         vars->link_status |=
5714                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5715                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5716                         vars->link_status |=
5717                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5718
5719         }
5720
5721
5722         if (lane < 2) {
5723                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5724                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5725         } else {
5726                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5727                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5728         }
5729         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5730
5731         if ((lane & 1) == 0)
5732                 gp_speed <<= 8;
5733         gp_speed &= 0x3f00;
5734         link_up = !!link_up;
5735
5736         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5737                                          duplex);
5738
5739         /* In case of KR link down, start up the recovering procedure */
5740         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5741             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5742                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5743
5744         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5745                    vars->duplex, vars->flow_ctrl, vars->link_status);
5746         return rc;
5747 }
5748 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5749 {
5750         struct bnx2x *bp = params->bp;
5751         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5752         u16 lp_up2;
5753         u16 tx_driver;
5754         u16 bank;
5755
5756         /* Read precomp */
5757         CL22_RD_OVER_CL45(bp, phy,
5758                           MDIO_REG_BANK_OVER_1G,
5759                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5760
5761         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5762         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5763                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5764                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5765
5766         if (lp_up2 == 0)
5767                 return;
5768
5769         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5770               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5771                 CL22_RD_OVER_CL45(bp, phy,
5772                                   bank,
5773                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5774
5775                 /* Replace tx_driver bits [15:12] */
5776                 if (lp_up2 !=
5777                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5778                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5779                         tx_driver |= lp_up2;
5780                         CL22_WR_OVER_CL45(bp, phy,
5781                                           bank,
5782                                           MDIO_TX0_TX_DRIVER, tx_driver);
5783                 }
5784         }
5785 }
5786
5787 static int bnx2x_emac_program(struct link_params *params,
5788                               struct link_vars *vars)
5789 {
5790         struct bnx2x *bp = params->bp;
5791         u8 port = params->port;
5792         u16 mode = 0;
5793
5794         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5795         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5796                        EMAC_REG_EMAC_MODE,
5797                        (EMAC_MODE_25G_MODE |
5798                         EMAC_MODE_PORT_MII_10M |
5799                         EMAC_MODE_HALF_DUPLEX));
5800         switch (vars->line_speed) {
5801         case SPEED_10:
5802                 mode |= EMAC_MODE_PORT_MII_10M;
5803                 break;
5804
5805         case SPEED_100:
5806                 mode |= EMAC_MODE_PORT_MII;
5807                 break;
5808
5809         case SPEED_1000:
5810                 mode |= EMAC_MODE_PORT_GMII;
5811                 break;
5812
5813         case SPEED_2500:
5814                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5815                 break;
5816
5817         default:
5818                 /* 10G not valid for EMAC */
5819                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5820                            vars->line_speed);
5821                 return -EINVAL;
5822         }
5823
5824         if (vars->duplex == DUPLEX_HALF)
5825                 mode |= EMAC_MODE_HALF_DUPLEX;
5826         bnx2x_bits_en(bp,
5827                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5828                       mode);
5829
5830         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5831         return 0;
5832 }
5833
5834 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5835                                   struct link_params *params)
5836 {
5837
5838         u16 bank, i = 0;
5839         struct bnx2x *bp = params->bp;
5840
5841         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5842               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5843                         CL22_WR_OVER_CL45(bp, phy,
5844                                           bank,
5845                                           MDIO_RX0_RX_EQ_BOOST,
5846                                           phy->rx_preemphasis[i]);
5847         }
5848
5849         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5850                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5851                         CL22_WR_OVER_CL45(bp, phy,
5852                                           bank,
5853                                           MDIO_TX0_TX_DRIVER,
5854                                           phy->tx_preemphasis[i]);
5855         }
5856 }
5857
5858 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5859                                    struct link_params *params,
5860                                    struct link_vars *vars)
5861 {
5862         struct bnx2x *bp = params->bp;
5863         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5864                           (params->loopback_mode == LOOPBACK_XGXS));
5865         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5866                 if (SINGLE_MEDIA_DIRECT(params) &&
5867                     (params->feature_config_flags &
5868                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5869                         bnx2x_set_preemphasis(phy, params);
5870
5871                 /* Forced speed requested? */
5872                 if (vars->line_speed != SPEED_AUTO_NEG ||
5873                     (SINGLE_MEDIA_DIRECT(params) &&
5874                      params->loopback_mode == LOOPBACK_EXT)) {
5875                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5876
5877                         /* Disable autoneg */
5878                         bnx2x_set_autoneg(phy, params, vars, 0);
5879
5880                         /* Program speed and duplex */
5881                         bnx2x_program_serdes(phy, params, vars);
5882
5883                 } else { /* AN_mode */
5884                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5885
5886                         /* AN enabled */
5887                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5888
5889                         /* Program duplex & pause advertisement (for aneg) */
5890                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5891                                                           vars->ieee_fc);
5892
5893                         /* Enable autoneg */
5894                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5895
5896                         /* Enable and restart AN */
5897                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5898                 }
5899
5900         } else { /* SGMII mode */
5901                 DP(NETIF_MSG_LINK, "SGMII\n");
5902
5903                 bnx2x_initialize_sgmii_process(phy, params, vars);
5904         }
5905 }
5906
5907 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5908                           struct link_params *params,
5909                           struct link_vars *vars)
5910 {
5911         int rc;
5912         vars->phy_flags |= PHY_XGXS_FLAG;
5913         if ((phy->req_line_speed &&
5914              ((phy->req_line_speed == SPEED_100) ||
5915               (phy->req_line_speed == SPEED_10))) ||
5916             (!phy->req_line_speed &&
5917              (phy->speed_cap_mask >=
5918               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5919              (phy->speed_cap_mask <
5920               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5921             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5922                 vars->phy_flags |= PHY_SGMII_FLAG;
5923         else
5924                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5925
5926         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5927         bnx2x_set_aer_mmd(params, phy);
5928         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5929                 bnx2x_set_master_ln(params, phy);
5930
5931         rc = bnx2x_reset_unicore(params, phy, 0);
5932         /* Reset the SerDes and wait for reset bit return low */
5933         if (rc)
5934                 return rc;
5935
5936         bnx2x_set_aer_mmd(params, phy);
5937         /* Setting the masterLn_def again after the reset */
5938         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5939                 bnx2x_set_master_ln(params, phy);
5940                 bnx2x_set_swap_lanes(params, phy);
5941         }
5942
5943         return rc;
5944 }
5945
5946 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5947                                      struct bnx2x_phy *phy,
5948                                      struct link_params *params)
5949 {
5950         u16 cnt, ctrl;
5951         /* Wait for soft reset to get cleared up to 1 sec */
5952         for (cnt = 0; cnt < 1000; cnt++) {
5953                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5954                         bnx2x_cl22_read(bp, phy,
5955                                 MDIO_PMA_REG_CTRL, &ctrl);
5956                 else
5957                         bnx2x_cl45_read(bp, phy,
5958                                 MDIO_PMA_DEVAD,
5959                                 MDIO_PMA_REG_CTRL, &ctrl);
5960                 if (!(ctrl & (1<<15)))
5961                         break;
5962                 usleep_range(1000, 2000);
5963         }
5964
5965         if (cnt == 1000)
5966                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5967                                       " Port %d\n",
5968                          params->port);
5969         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5970         return cnt;
5971 }
5972
5973 static void bnx2x_link_int_enable(struct link_params *params)
5974 {
5975         u8 port = params->port;
5976         u32 mask;
5977         struct bnx2x *bp = params->bp;
5978
5979         /* Setting the status to report on link up for either XGXS or SerDes */
5980         if (CHIP_IS_E3(bp)) {
5981                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5982                 if (!(SINGLE_MEDIA_DIRECT(params)))
5983                         mask |= NIG_MASK_MI_INT;
5984         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5985                 mask = (NIG_MASK_XGXS0_LINK10G |
5986                         NIG_MASK_XGXS0_LINK_STATUS);
5987                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5988                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5989                         params->phy[INT_PHY].type !=
5990                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5991                         mask |= NIG_MASK_MI_INT;
5992                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5993                 }
5994
5995         } else { /* SerDes */
5996                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5997                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5998                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5999                         params->phy[INT_PHY].type !=
6000                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6001                         mask |= NIG_MASK_MI_INT;
6002                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6003                 }
6004         }
6005         bnx2x_bits_en(bp,
6006                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6007                       mask);
6008
6009         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6010                  (params->switch_cfg == SWITCH_CFG_10G),
6011                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6012         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6013                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6014                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6015                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6016         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6017            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6018            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6019 }
6020
6021 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6022                                      u8 exp_mi_int)
6023 {
6024         u32 latch_status = 0;
6025
6026         /* Disable the MI INT ( external phy int ) by writing 1 to the
6027          * status register. Link down indication is high-active-signal,
6028          * so in this case we need to write the status to clear the XOR
6029          */
6030         /* Read Latched signals */
6031         latch_status = REG_RD(bp,
6032                                     NIG_REG_LATCH_STATUS_0 + port*8);
6033         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6034         /* Handle only those with latched-signal=up.*/
6035         if (exp_mi_int)
6036                 bnx2x_bits_en(bp,
6037                               NIG_REG_STATUS_INTERRUPT_PORT0
6038                               + port*4,
6039                               NIG_STATUS_EMAC0_MI_INT);
6040         else
6041                 bnx2x_bits_dis(bp,
6042                                NIG_REG_STATUS_INTERRUPT_PORT0
6043                                + port*4,
6044                                NIG_STATUS_EMAC0_MI_INT);
6045
6046         if (latch_status & 1) {
6047
6048                 /* For all latched-signal=up : Re-Arm Latch signals */
6049                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6050                        (latch_status & 0xfffe) | (latch_status & 1));
6051         }
6052         /* For all latched-signal=up,Write original_signal to status */
6053 }
6054
6055 static void bnx2x_link_int_ack(struct link_params *params,
6056                                struct link_vars *vars, u8 is_10g_plus)
6057 {
6058         struct bnx2x *bp = params->bp;
6059         u8 port = params->port;
6060         u32 mask;
6061         /* First reset all status we assume only one line will be
6062          * change at a time
6063          */
6064         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6065                        (NIG_STATUS_XGXS0_LINK10G |
6066                         NIG_STATUS_XGXS0_LINK_STATUS |
6067                         NIG_STATUS_SERDES0_LINK_STATUS));
6068         if (vars->phy_link_up) {
6069                 if (USES_WARPCORE(bp))
6070                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6071                 else {
6072                         if (is_10g_plus)
6073                                 mask = NIG_STATUS_XGXS0_LINK10G;
6074                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6075                                 /* Disable the link interrupt by writing 1 to
6076                                  * the relevant lane in the status register
6077                                  */
6078                                 u32 ser_lane =
6079                                         ((params->lane_config &
6080                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6081                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6082                                 mask = ((1 << ser_lane) <<
6083                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6084                         } else
6085                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6086                 }
6087                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6088                                mask);
6089                 bnx2x_bits_en(bp,
6090                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6091                               mask);
6092         }
6093 }
6094
6095 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6096 {
6097         u8 *str_ptr = str;
6098         u32 mask = 0xf0000000;
6099         u8 shift = 8*4;
6100         u8 digit;
6101         u8 remove_leading_zeros = 1;
6102         if (*len < 10) {
6103                 /* Need more than 10chars for this format */
6104                 *str_ptr = '\0';
6105                 (*len)--;
6106                 return -EINVAL;
6107         }
6108         while (shift > 0) {
6109
6110                 shift -= 4;
6111                 digit = ((num & mask) >> shift);
6112                 if (digit == 0 && remove_leading_zeros) {
6113                         mask = mask >> 4;
6114                         continue;
6115                 } else if (digit < 0xa)
6116                         *str_ptr = digit + '0';
6117                 else
6118                         *str_ptr = digit - 0xa + 'a';
6119                 remove_leading_zeros = 0;
6120                 str_ptr++;
6121                 (*len)--;
6122                 mask = mask >> 4;
6123                 if (shift == 4*4) {
6124                         *str_ptr = '.';
6125                         str_ptr++;
6126                         (*len)--;
6127                         remove_leading_zeros = 1;
6128                 }
6129         }
6130         return 0;
6131 }
6132
6133
6134 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6135 {
6136         str[0] = '\0';
6137         (*len)--;
6138         return 0;
6139 }
6140
6141 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6142                                  u16 len)
6143 {
6144         struct bnx2x *bp;
6145         u32 spirom_ver = 0;
6146         int status = 0;
6147         u8 *ver_p = version;
6148         u16 remain_len = len;
6149         if (version == NULL || params == NULL)
6150                 return -EINVAL;
6151         bp = params->bp;
6152
6153         /* Extract first external phy*/
6154         version[0] = '\0';
6155         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6156
6157         if (params->phy[EXT_PHY1].format_fw_ver) {
6158                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6159                                                               ver_p,
6160                                                               &remain_len);
6161                 ver_p += (len - remain_len);
6162         }
6163         if ((params->num_phys == MAX_PHYS) &&
6164             (params->phy[EXT_PHY2].ver_addr != 0)) {
6165                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6166                 if (params->phy[EXT_PHY2].format_fw_ver) {
6167                         *ver_p = '/';
6168                         ver_p++;
6169                         remain_len--;
6170                         status |= params->phy[EXT_PHY2].format_fw_ver(
6171                                 spirom_ver,
6172                                 ver_p,
6173                                 &remain_len);
6174                         ver_p = version + (len - remain_len);
6175                 }
6176         }
6177         *ver_p = '\0';
6178         return status;
6179 }
6180
6181 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6182                                     struct link_params *params)
6183 {
6184         u8 port = params->port;
6185         struct bnx2x *bp = params->bp;
6186
6187         if (phy->req_line_speed != SPEED_1000) {
6188                 u32 md_devad = 0;
6189
6190                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6191
6192                 if (!CHIP_IS_E3(bp)) {
6193                         /* Change the uni_phy_addr in the nig */
6194                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6195                                                port*0x18));
6196
6197                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6198                                0x5);
6199                 }
6200
6201                 bnx2x_cl45_write(bp, phy,
6202                                  5,
6203                                  (MDIO_REG_BANK_AER_BLOCK +
6204                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6205                                  0x2800);
6206
6207                 bnx2x_cl45_write(bp, phy,
6208                                  5,
6209                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6210                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6211                                  0x6041);
6212                 msleep(200);
6213                 /* Set aer mmd back */
6214                 bnx2x_set_aer_mmd(params, phy);
6215
6216                 if (!CHIP_IS_E3(bp)) {
6217                         /* And md_devad */
6218                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6219                                md_devad);
6220                 }
6221         } else {
6222                 u16 mii_ctrl;
6223                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6224                 bnx2x_cl45_read(bp, phy, 5,
6225                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6226                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6227                                 &mii_ctrl);
6228                 bnx2x_cl45_write(bp, phy, 5,
6229                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6230                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6231                                  mii_ctrl |
6232                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6233         }
6234 }
6235
6236 int bnx2x_set_led(struct link_params *params,
6237                   struct link_vars *vars, u8 mode, u32 speed)
6238 {
6239         u8 port = params->port;
6240         u16 hw_led_mode = params->hw_led_mode;
6241         int rc = 0;
6242         u8 phy_idx;
6243         u32 tmp;
6244         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6245         struct bnx2x *bp = params->bp;
6246         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6247         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6248                  speed, hw_led_mode);
6249         /* In case */
6250         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6251                 if (params->phy[phy_idx].set_link_led) {
6252                         params->phy[phy_idx].set_link_led(
6253                                 &params->phy[phy_idx], params, mode);
6254                 }
6255         }
6256
6257         switch (mode) {
6258         case LED_MODE_FRONT_PANEL_OFF:
6259         case LED_MODE_OFF:
6260                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6261                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6262                        SHARED_HW_CFG_LED_MAC1);
6263
6264                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6265                 if (params->phy[EXT_PHY1].type ==
6266                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6267                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6268                                 EMAC_LED_100MB_OVERRIDE |
6269                                 EMAC_LED_10MB_OVERRIDE);
6270                 else
6271                         tmp |= EMAC_LED_OVERRIDE;
6272
6273                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6274                 break;
6275
6276         case LED_MODE_OPER:
6277                 /* For all other phys, OPER mode is same as ON, so in case
6278                  * link is down, do nothing
6279                  */
6280                 if (!vars->link_up)
6281                         break;
6282         case LED_MODE_ON:
6283                 if (((params->phy[EXT_PHY1].type ==
6284                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6285                          (params->phy[EXT_PHY1].type ==
6286                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6287                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6288                         /* This is a work-around for E2+8727 Configurations */
6289                         if (mode == LED_MODE_ON ||
6290                                 speed == SPEED_10000){
6291                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6292                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6293
6294                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6295                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6296                                         (tmp | EMAC_LED_OVERRIDE));
6297                                 /* Return here without enabling traffic
6298                                  * LED blink and setting rate in ON mode.
6299                                  * In oper mode, enabling LED blink
6300                                  * and setting rate is needed.
6301                                  */
6302                                 if (mode == LED_MODE_ON)
6303                                         return rc;
6304                         }
6305                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6306                         /* This is a work-around for HW issue found when link
6307                          * is up in CL73
6308                          */
6309                         if ((!CHIP_IS_E3(bp)) ||
6310                             (CHIP_IS_E3(bp) &&
6311                              mode == LED_MODE_ON))
6312                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6313
6314                         if (CHIP_IS_E1x(bp) ||
6315                             CHIP_IS_E2(bp) ||
6316                             (mode == LED_MODE_ON))
6317                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6318                         else
6319                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6320                                        hw_led_mode);
6321                 } else if ((params->phy[EXT_PHY1].type ==
6322                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6323                            (mode == LED_MODE_ON)) {
6324                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6325                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6326                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6327                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6328                         /* Break here; otherwise, it'll disable the
6329                          * intended override.
6330                          */
6331                         break;
6332                 } else
6333                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6334                                hw_led_mode);
6335
6336                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6337                 /* Set blinking rate to ~15.9Hz */
6338                 if (CHIP_IS_E3(bp))
6339                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6340                                LED_BLINK_RATE_VAL_E3);
6341                 else
6342                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6343                                LED_BLINK_RATE_VAL_E1X_E2);
6344                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6345                        port*4, 1);
6346                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6347                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6348                         (tmp & (~EMAC_LED_OVERRIDE)));
6349
6350                 if (CHIP_IS_E1(bp) &&
6351                     ((speed == SPEED_2500) ||
6352                      (speed == SPEED_1000) ||
6353                      (speed == SPEED_100) ||
6354                      (speed == SPEED_10))) {
6355                         /* For speeds less than 10G LED scheme is different */
6356                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6357                                + port*4, 1);
6358                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6359                                port*4, 0);
6360                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6361                                port*4, 1);
6362                 }
6363                 break;
6364
6365         default:
6366                 rc = -EINVAL;
6367                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6368                          mode);
6369                 break;
6370         }
6371         return rc;
6372
6373 }
6374
6375 /* This function comes to reflect the actual link state read DIRECTLY from the
6376  * HW
6377  */
6378 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6379                     u8 is_serdes)
6380 {
6381         struct bnx2x *bp = params->bp;
6382         u16 gp_status = 0, phy_index = 0;
6383         u8 ext_phy_link_up = 0, serdes_phy_type;
6384         struct link_vars temp_vars;
6385         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6386
6387         if (CHIP_IS_E3(bp)) {
6388                 u16 link_up;
6389                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6390                     > SPEED_10000) {
6391                         /* Check 20G link */
6392                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6393                                         1, &link_up);
6394                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6395                                         1, &link_up);
6396                         link_up &= (1<<2);
6397                 } else {
6398                         /* Check 10G link and below*/
6399                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6400                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6401                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6402                                         &gp_status);
6403                         gp_status = ((gp_status >> 8) & 0xf) |
6404                                 ((gp_status >> 12) & 0xf);
6405                         link_up = gp_status & (1 << lane);
6406                 }
6407                 if (!link_up)
6408                         return -ESRCH;
6409         } else {
6410                 CL22_RD_OVER_CL45(bp, int_phy,
6411                           MDIO_REG_BANK_GP_STATUS,
6412                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6413                           &gp_status);
6414         /* Link is up only if both local phy and external phy are up */
6415         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6416                 return -ESRCH;
6417         }
6418         /* In XGXS loopback mode, do not check external PHY */
6419         if (params->loopback_mode == LOOPBACK_XGXS)
6420                 return 0;
6421
6422         switch (params->num_phys) {
6423         case 1:
6424                 /* No external PHY */
6425                 return 0;
6426         case 2:
6427                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6428                         &params->phy[EXT_PHY1],
6429                         params, &temp_vars);
6430                 break;
6431         case 3: /* Dual Media */
6432                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6433                       phy_index++) {
6434                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6435                                             ETH_PHY_SFPP_10G_FIBER) ||
6436                                            (params->phy[phy_index].media_type ==
6437                                             ETH_PHY_SFP_1G_FIBER) ||
6438                                            (params->phy[phy_index].media_type ==
6439                                             ETH_PHY_XFP_FIBER) ||
6440                                            (params->phy[phy_index].media_type ==
6441                                             ETH_PHY_DA_TWINAX));
6442
6443                         if (is_serdes != serdes_phy_type)
6444                                 continue;
6445                         if (params->phy[phy_index].read_status) {
6446                                 ext_phy_link_up |=
6447                                         params->phy[phy_index].read_status(
6448                                                 &params->phy[phy_index],
6449                                                 params, &temp_vars);
6450                         }
6451                 }
6452                 break;
6453         }
6454         if (ext_phy_link_up)
6455                 return 0;
6456         return -ESRCH;
6457 }
6458
6459 static int bnx2x_link_initialize(struct link_params *params,
6460                                  struct link_vars *vars)
6461 {
6462         int rc = 0;
6463         u8 phy_index, non_ext_phy;
6464         struct bnx2x *bp = params->bp;
6465         /* In case of external phy existence, the line speed would be the
6466          * line speed linked up by the external phy. In case it is direct
6467          * only, then the line_speed during initialization will be
6468          * equal to the req_line_speed
6469          */
6470         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6471
6472         /* Initialize the internal phy in case this is a direct board
6473          * (no external phys), or this board has external phy which requires
6474          * to first.
6475          */
6476         if (!USES_WARPCORE(bp))
6477                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6478         /* init ext phy and enable link state int */
6479         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6480                        (params->loopback_mode == LOOPBACK_XGXS));
6481
6482         if (non_ext_phy ||
6483             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6484             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6485                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6486                 if (vars->line_speed == SPEED_AUTO_NEG &&
6487                     (CHIP_IS_E1x(bp) ||
6488                      CHIP_IS_E2(bp)))
6489                         bnx2x_set_parallel_detection(phy, params);
6490                 if (params->phy[INT_PHY].config_init)
6491                         params->phy[INT_PHY].config_init(phy, params, vars);
6492         }
6493
6494         /* Init external phy*/
6495         if (non_ext_phy) {
6496                 if (params->phy[INT_PHY].supported &
6497                     SUPPORTED_FIBRE)
6498                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6499         } else {
6500                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6501                       phy_index++) {
6502                         /* No need to initialize second phy in case of first
6503                          * phy only selection. In case of second phy, we do
6504                          * need to initialize the first phy, since they are
6505                          * connected.
6506                          */
6507                         if (params->phy[phy_index].supported &
6508                             SUPPORTED_FIBRE)
6509                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6510
6511                         if (phy_index == EXT_PHY2 &&
6512                             (bnx2x_phy_selection(params) ==
6513                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6514                                 DP(NETIF_MSG_LINK,
6515                                    "Not initializing second phy\n");
6516                                 continue;
6517                         }
6518                         params->phy[phy_index].config_init(
6519                                 &params->phy[phy_index],
6520                                 params, vars);
6521                 }
6522         }
6523         /* Reset the interrupt indication after phy was initialized */
6524         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6525                        params->port*4,
6526                        (NIG_STATUS_XGXS0_LINK10G |
6527                         NIG_STATUS_XGXS0_LINK_STATUS |
6528                         NIG_STATUS_SERDES0_LINK_STATUS |
6529                         NIG_MASK_MI_INT));
6530         return rc;
6531 }
6532
6533 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6534                                  struct link_params *params)
6535 {
6536         /* Reset the SerDes/XGXS */
6537         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6538                (0x1ff << (params->port*16)));
6539 }
6540
6541 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6542                                         struct link_params *params)
6543 {
6544         struct bnx2x *bp = params->bp;
6545         u8 gpio_port;
6546         /* HW reset */
6547         if (CHIP_IS_E2(bp))
6548                 gpio_port = BP_PATH(bp);
6549         else
6550                 gpio_port = params->port;
6551         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6552                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6553                        gpio_port);
6554         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6555                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6556                        gpio_port);
6557         DP(NETIF_MSG_LINK, "reset external PHY\n");
6558 }
6559
6560 static int bnx2x_update_link_down(struct link_params *params,
6561                                   struct link_vars *vars)
6562 {
6563         struct bnx2x *bp = params->bp;
6564         u8 port = params->port;
6565
6566         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6567         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6568         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6569         /* Indicate no mac active */
6570         vars->mac_type = MAC_TYPE_NONE;
6571
6572         /* Update shared memory */
6573         vars->link_status &= ~LINK_UPDATE_MASK;
6574         vars->line_speed = 0;
6575         bnx2x_update_mng(params, vars->link_status);
6576
6577         /* Activate nig drain */
6578         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6579
6580         /* Disable emac */
6581         if (!CHIP_IS_E3(bp))
6582                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6583
6584         usleep_range(10000, 20000);
6585         /* Reset BigMac/Xmac */
6586         if (CHIP_IS_E1x(bp) ||
6587             CHIP_IS_E2(bp))
6588                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6589
6590         if (CHIP_IS_E3(bp)) {
6591                 /* Prevent LPI Generation by chip */
6592                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6593                        0);
6594                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6595                        0);
6596                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6597                                       SHMEM_EEE_ACTIVE_BIT);
6598
6599                 bnx2x_update_mng_eee(params, vars->eee_status);
6600                 bnx2x_set_xmac_rxtx(params, 0);
6601                 bnx2x_set_umac_rxtx(params, 0);
6602         }
6603
6604         return 0;
6605 }
6606
6607 static int bnx2x_update_link_up(struct link_params *params,
6608                                 struct link_vars *vars,
6609                                 u8 link_10g)
6610 {
6611         struct bnx2x *bp = params->bp;
6612         u8 phy_idx, port = params->port;
6613         int rc = 0;
6614
6615         vars->link_status |= (LINK_STATUS_LINK_UP |
6616                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6617         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6618
6619         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6620                 vars->link_status |=
6621                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6622
6623         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6624                 vars->link_status |=
6625                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6626         if (USES_WARPCORE(bp)) {
6627                 if (link_10g) {
6628                         if (bnx2x_xmac_enable(params, vars, 0) ==
6629                             -ESRCH) {
6630                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6631                                 vars->link_up = 0;
6632                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6633                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6634                         }
6635                 } else
6636                         bnx2x_umac_enable(params, vars, 0);
6637                 bnx2x_set_led(params, vars,
6638                               LED_MODE_OPER, vars->line_speed);
6639
6640                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6641                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6642                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6643                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6644                                (params->port << 2), 1);
6645                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6646                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6647                                (params->port << 2), 0xfc20);
6648                 }
6649         }
6650         if ((CHIP_IS_E1x(bp) ||
6651              CHIP_IS_E2(bp))) {
6652                 if (link_10g) {
6653                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6654                             -ESRCH) {
6655                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6656                                 vars->link_up = 0;
6657                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6658                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6659                         }
6660
6661                         bnx2x_set_led(params, vars,
6662                                       LED_MODE_OPER, SPEED_10000);
6663                 } else {
6664                         rc = bnx2x_emac_program(params, vars);
6665                         bnx2x_emac_enable(params, vars, 0);
6666
6667                         /* AN complete? */
6668                         if ((vars->link_status &
6669                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6670                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6671                             SINGLE_MEDIA_DIRECT(params))
6672                                 bnx2x_set_gmii_tx_driver(params);
6673                 }
6674         }
6675
6676         /* PBF - link up */
6677         if (CHIP_IS_E1x(bp))
6678                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6679                                        vars->line_speed);
6680
6681         /* Disable drain */
6682         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6683
6684         /* Update shared memory */
6685         bnx2x_update_mng(params, vars->link_status);
6686         bnx2x_update_mng_eee(params, vars->eee_status);
6687         /* Check remote fault */
6688         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6689                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6690                         bnx2x_check_half_open_conn(params, vars, 0);
6691                         break;
6692                 }
6693         }
6694         msleep(20);
6695         return rc;
6696 }
6697 /* The bnx2x_link_update function should be called upon link
6698  * interrupt.
6699  * Link is considered up as follows:
6700  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6701  *   to be up
6702  * - SINGLE_MEDIA - The link between the 577xx and the external
6703  *   phy (XGXS) need to up as well as the external link of the
6704  *   phy (PHY_EXT1)
6705  * - DUAL_MEDIA - The link between the 577xx and the first
6706  *   external phy needs to be up, and at least one of the 2
6707  *   external phy link must be up.
6708  */
6709 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6710 {
6711         struct bnx2x *bp = params->bp;
6712         struct link_vars phy_vars[MAX_PHYS];
6713         u8 port = params->port;
6714         u8 link_10g_plus, phy_index;
6715         u8 ext_phy_link_up = 0, cur_link_up;
6716         int rc = 0;
6717         u8 is_mi_int = 0;
6718         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6719         u8 active_external_phy = INT_PHY;
6720         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6721         vars->link_status &= ~LINK_UPDATE_MASK;
6722         for (phy_index = INT_PHY; phy_index < params->num_phys;
6723               phy_index++) {
6724                 phy_vars[phy_index].flow_ctrl = 0;
6725                 phy_vars[phy_index].link_status = 0;
6726                 phy_vars[phy_index].line_speed = 0;
6727                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6728                 phy_vars[phy_index].phy_link_up = 0;
6729                 phy_vars[phy_index].link_up = 0;
6730                 phy_vars[phy_index].fault_detected = 0;
6731                 /* different consideration, since vars holds inner state */
6732                 phy_vars[phy_index].eee_status = vars->eee_status;
6733         }
6734
6735         if (USES_WARPCORE(bp))
6736                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6737
6738         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6739                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6740                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6741
6742         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6743                                 port*0x18) > 0);
6744         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6745                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6746                  is_mi_int,
6747                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6748
6749         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6750           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6751           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6752
6753         /* Disable emac */
6754         if (!CHIP_IS_E3(bp))
6755                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6756
6757         /* Step 1:
6758          * Check external link change only for external phys, and apply
6759          * priority selection between them in case the link on both phys
6760          * is up. Note that instead of the common vars, a temporary
6761          * vars argument is used since each phy may have different link/
6762          * speed/duplex result
6763          */
6764         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6765               phy_index++) {
6766                 struct bnx2x_phy *phy = &params->phy[phy_index];
6767                 if (!phy->read_status)
6768                         continue;
6769                 /* Read link status and params of this ext phy */
6770                 cur_link_up = phy->read_status(phy, params,
6771                                                &phy_vars[phy_index]);
6772                 if (cur_link_up) {
6773                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6774                                    phy_index);
6775                 } else {
6776                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6777                                    phy_index);
6778                         continue;
6779                 }
6780
6781                 if (!ext_phy_link_up) {
6782                         ext_phy_link_up = 1;
6783                         active_external_phy = phy_index;
6784                 } else {
6785                         switch (bnx2x_phy_selection(params)) {
6786                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6787                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6788                         /* In this option, the first PHY makes sure to pass the
6789                          * traffic through itself only.
6790                          * Its not clear how to reset the link on the second phy
6791                          */
6792                                 active_external_phy = EXT_PHY1;
6793                                 break;
6794                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6795                         /* In this option, the first PHY makes sure to pass the
6796                          * traffic through the second PHY.
6797                          */
6798                                 active_external_phy = EXT_PHY2;
6799                                 break;
6800                         default:
6801                         /* Link indication on both PHYs with the following cases
6802                          * is invalid:
6803                          * - FIRST_PHY means that second phy wasn't initialized,
6804                          * hence its link is expected to be down
6805                          * - SECOND_PHY means that first phy should not be able
6806                          * to link up by itself (using configuration)
6807                          * - DEFAULT should be overriden during initialiazation
6808                          */
6809                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6810                                            "mpc=0x%x. DISABLING LINK !!!\n",
6811                                            params->multi_phy_config);
6812                                 ext_phy_link_up = 0;
6813                                 break;
6814                         }
6815                 }
6816         }
6817         prev_line_speed = vars->line_speed;
6818         /* Step 2:
6819          * Read the status of the internal phy. In case of
6820          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6821          * otherwise this is the link between the 577xx and the first
6822          * external phy
6823          */
6824         if (params->phy[INT_PHY].read_status)
6825                 params->phy[INT_PHY].read_status(
6826                         &params->phy[INT_PHY],
6827                         params, vars);
6828         /* The INT_PHY flow control reside in the vars. This include the
6829          * case where the speed or flow control are not set to AUTO.
6830          * Otherwise, the active external phy flow control result is set
6831          * to the vars. The ext_phy_line_speed is needed to check if the
6832          * speed is different between the internal phy and external phy.
6833          * This case may be result of intermediate link speed change.
6834          */
6835         if (active_external_phy > INT_PHY) {
6836                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6837                 /* Link speed is taken from the XGXS. AN and FC result from
6838                  * the external phy.
6839                  */
6840                 vars->link_status |= phy_vars[active_external_phy].link_status;
6841
6842                 /* if active_external_phy is first PHY and link is up - disable
6843                  * disable TX on second external PHY
6844                  */
6845                 if (active_external_phy == EXT_PHY1) {
6846                         if (params->phy[EXT_PHY2].phy_specific_func) {
6847                                 DP(NETIF_MSG_LINK,
6848                                    "Disabling TX on EXT_PHY2\n");
6849                                 params->phy[EXT_PHY2].phy_specific_func(
6850                                         &params->phy[EXT_PHY2],
6851                                         params, DISABLE_TX);
6852                         }
6853                 }
6854
6855                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6856                 vars->duplex = phy_vars[active_external_phy].duplex;
6857                 if (params->phy[active_external_phy].supported &
6858                     SUPPORTED_FIBRE)
6859                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6860                 else
6861                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6862
6863                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6864
6865                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6866                            active_external_phy);
6867         }
6868
6869         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6870               phy_index++) {
6871                 if (params->phy[phy_index].flags &
6872                     FLAGS_REARM_LATCH_SIGNAL) {
6873                         bnx2x_rearm_latch_signal(bp, port,
6874                                                  phy_index ==
6875                                                  active_external_phy);
6876                         break;
6877                 }
6878         }
6879         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6880                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6881                    vars->link_status, ext_phy_line_speed);
6882         /* Upon link speed change set the NIG into drain mode. Comes to
6883          * deals with possible FIFO glitch due to clk change when speed
6884          * is decreased without link down indicator
6885          */
6886
6887         if (vars->phy_link_up) {
6888                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6889                     (ext_phy_line_speed != vars->line_speed)) {
6890                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6891                                    " different than the external"
6892                                    " link speed %d\n", vars->line_speed,
6893                                    ext_phy_line_speed);
6894                         vars->phy_link_up = 0;
6895                 } else if (prev_line_speed != vars->line_speed) {
6896                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6897                                0);
6898                         usleep_range(1000, 2000);
6899                 }
6900         }
6901
6902         /* Anything 10 and over uses the bmac */
6903         link_10g_plus = (vars->line_speed >= SPEED_10000);
6904
6905         bnx2x_link_int_ack(params, vars, link_10g_plus);
6906
6907         /* In case external phy link is up, and internal link is down
6908          * (not initialized yet probably after link initialization, it
6909          * needs to be initialized.
6910          * Note that after link down-up as result of cable plug, the xgxs
6911          * link would probably become up again without the need
6912          * initialize it
6913          */
6914         if (!(SINGLE_MEDIA_DIRECT(params))) {
6915                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6916                            " init_preceding = %d\n", ext_phy_link_up,
6917                            vars->phy_link_up,
6918                            params->phy[EXT_PHY1].flags &
6919                            FLAGS_INIT_XGXS_FIRST);
6920                 if (!(params->phy[EXT_PHY1].flags &
6921                       FLAGS_INIT_XGXS_FIRST)
6922                     && ext_phy_link_up && !vars->phy_link_up) {
6923                         vars->line_speed = ext_phy_line_speed;
6924                         if (vars->line_speed < SPEED_1000)
6925                                 vars->phy_flags |= PHY_SGMII_FLAG;
6926                         else
6927                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6928
6929                         if (params->phy[INT_PHY].config_init)
6930                                 params->phy[INT_PHY].config_init(
6931                                         &params->phy[INT_PHY], params,
6932                                                 vars);
6933                 }
6934         }
6935         /* Link is up only if both local phy and external phy (in case of
6936          * non-direct board) are up and no fault detected on active PHY.
6937          */
6938         vars->link_up = (vars->phy_link_up &&
6939                          (ext_phy_link_up ||
6940                           SINGLE_MEDIA_DIRECT(params)) &&
6941                          (phy_vars[active_external_phy].fault_detected == 0));
6942
6943         /* Update the PFC configuration in case it was changed */
6944         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6945                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6946         else
6947                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6948
6949         if (vars->link_up)
6950                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6951         else
6952                 rc = bnx2x_update_link_down(params, vars);
6953
6954         /* Update MCP link status was changed */
6955         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6956                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6957
6958         return rc;
6959 }
6960
6961 /*****************************************************************************/
6962 /*                          External Phy section                             */
6963 /*****************************************************************************/
6964 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6965 {
6966         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6967                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6968         usleep_range(1000, 2000);
6969         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6970                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6971 }
6972
6973 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6974                                       u32 spirom_ver, u32 ver_addr)
6975 {
6976         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6977                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6978
6979         if (ver_addr)
6980                 REG_WR(bp, ver_addr, spirom_ver);
6981 }
6982
6983 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6984                                       struct bnx2x_phy *phy,
6985                                       u8 port)
6986 {
6987         u16 fw_ver1, fw_ver2;
6988
6989         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6990                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6991         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6992                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6993         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6994                                   phy->ver_addr);
6995 }
6996
6997 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6998                                        struct bnx2x_phy *phy,
6999                                        struct link_vars *vars)
7000 {
7001         u16 val;
7002         bnx2x_cl45_read(bp, phy,
7003                         MDIO_AN_DEVAD,
7004                         MDIO_AN_REG_STATUS, &val);
7005         bnx2x_cl45_read(bp, phy,
7006                         MDIO_AN_DEVAD,
7007                         MDIO_AN_REG_STATUS, &val);
7008         if (val & (1<<5))
7009                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7010         if ((val & (1<<0)) == 0)
7011                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7012 }
7013
7014 /******************************************************************/
7015 /*              common BCM8073/BCM8727 PHY SECTION                */
7016 /******************************************************************/
7017 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7018                                   struct link_params *params,
7019                                   struct link_vars *vars)
7020 {
7021         struct bnx2x *bp = params->bp;
7022         if (phy->req_line_speed == SPEED_10 ||
7023             phy->req_line_speed == SPEED_100) {
7024                 vars->flow_ctrl = phy->req_flow_ctrl;
7025                 return;
7026         }
7027
7028         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7029             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7030                 u16 pause_result;
7031                 u16 ld_pause;           /* local */
7032                 u16 lp_pause;           /* link partner */
7033                 bnx2x_cl45_read(bp, phy,
7034                                 MDIO_AN_DEVAD,
7035                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7036
7037                 bnx2x_cl45_read(bp, phy,
7038                                 MDIO_AN_DEVAD,
7039                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7040                 pause_result = (ld_pause &
7041                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7042                 pause_result |= (lp_pause &
7043                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7044
7045                 bnx2x_pause_resolve(vars, pause_result);
7046                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7047                            pause_result);
7048         }
7049 }
7050 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7051                                              struct bnx2x_phy *phy,
7052                                              u8 port)
7053 {
7054         u32 count = 0;
7055         u16 fw_ver1, fw_msgout;
7056         int rc = 0;
7057
7058         /* Boot port from external ROM  */
7059         /* EDC grst */
7060         bnx2x_cl45_write(bp, phy,
7061                          MDIO_PMA_DEVAD,
7062                          MDIO_PMA_REG_GEN_CTRL,
7063                          0x0001);
7064
7065         /* Ucode reboot and rst */
7066         bnx2x_cl45_write(bp, phy,
7067                          MDIO_PMA_DEVAD,
7068                          MDIO_PMA_REG_GEN_CTRL,
7069                          0x008c);
7070
7071         bnx2x_cl45_write(bp, phy,
7072                          MDIO_PMA_DEVAD,
7073                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7074
7075         /* Reset internal microprocessor */
7076         bnx2x_cl45_write(bp, phy,
7077                          MDIO_PMA_DEVAD,
7078                          MDIO_PMA_REG_GEN_CTRL,
7079                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7080
7081         /* Release srst bit */
7082         bnx2x_cl45_write(bp, phy,
7083                          MDIO_PMA_DEVAD,
7084                          MDIO_PMA_REG_GEN_CTRL,
7085                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7086
7087         /* Delay 100ms per the PHY specifications */
7088         msleep(100);
7089
7090         /* 8073 sometimes taking longer to download */
7091         do {
7092                 count++;
7093                 if (count > 300) {
7094                         DP(NETIF_MSG_LINK,
7095                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7096                                  "Download failed. fw version = 0x%x\n",
7097                                  port, fw_ver1);
7098                         rc = -EINVAL;
7099                         break;
7100                 }
7101
7102                 bnx2x_cl45_read(bp, phy,
7103                                 MDIO_PMA_DEVAD,
7104                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7105                 bnx2x_cl45_read(bp, phy,
7106                                 MDIO_PMA_DEVAD,
7107                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7108
7109                 usleep_range(1000, 2000);
7110         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7111                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7112                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7113
7114         /* Clear ser_boot_ctl bit */
7115         bnx2x_cl45_write(bp, phy,
7116                          MDIO_PMA_DEVAD,
7117                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7118         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7119
7120         DP(NETIF_MSG_LINK,
7121                  "bnx2x_8073_8727_external_rom_boot port %x:"
7122                  "Download complete. fw version = 0x%x\n",
7123                  port, fw_ver1);
7124
7125         return rc;
7126 }
7127
7128 /******************************************************************/
7129 /*                      BCM8073 PHY SECTION                       */
7130 /******************************************************************/
7131 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7132 {
7133         /* This is only required for 8073A1, version 102 only */
7134         u16 val;
7135
7136         /* Read 8073 HW revision*/
7137         bnx2x_cl45_read(bp, phy,
7138                         MDIO_PMA_DEVAD,
7139                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7140
7141         if (val != 1) {
7142                 /* No need to workaround in 8073 A1 */
7143                 return 0;
7144         }
7145
7146         bnx2x_cl45_read(bp, phy,
7147                         MDIO_PMA_DEVAD,
7148                         MDIO_PMA_REG_ROM_VER2, &val);
7149
7150         /* SNR should be applied only for version 0x102 */
7151         if (val != 0x102)
7152                 return 0;
7153
7154         return 1;
7155 }
7156
7157 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7158 {
7159         u16 val, cnt, cnt1 ;
7160
7161         bnx2x_cl45_read(bp, phy,
7162                         MDIO_PMA_DEVAD,
7163                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7164
7165         if (val > 0) {
7166                 /* No need to workaround in 8073 A1 */
7167                 return 0;
7168         }
7169         /* XAUI workaround in 8073 A0: */
7170
7171         /* After loading the boot ROM and restarting Autoneg, poll
7172          * Dev1, Reg $C820:
7173          */
7174
7175         for (cnt = 0; cnt < 1000; cnt++) {
7176                 bnx2x_cl45_read(bp, phy,
7177                                 MDIO_PMA_DEVAD,
7178                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7179                                 &val);
7180                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7181                    * system initialization (XAUI work-around not required, as
7182                    * these bits indicate 2.5G or 1G link up).
7183                    */
7184                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7185                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7186                         return 0;
7187                 } else if (!(val & (1<<15))) {
7188                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7189                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7190                          * MSB (bit15) goes to 1 (indicating that the XAUI
7191                          * workaround has completed), then continue on with
7192                          * system initialization.
7193                          */
7194                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7195                                 bnx2x_cl45_read(bp, phy,
7196                                         MDIO_PMA_DEVAD,
7197                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7198                                 if (val & (1<<15)) {
7199                                         DP(NETIF_MSG_LINK,
7200                                           "XAUI workaround has completed\n");
7201                                         return 0;
7202                                  }
7203                                  usleep_range(3000, 6000);
7204                         }
7205                         break;
7206                 }
7207                 usleep_range(3000, 6000);
7208         }
7209         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7210         return -EINVAL;
7211 }
7212
7213 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7214 {
7215         /* Force KR or KX */
7216         bnx2x_cl45_write(bp, phy,
7217                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7218         bnx2x_cl45_write(bp, phy,
7219                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7220         bnx2x_cl45_write(bp, phy,
7221                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7222         bnx2x_cl45_write(bp, phy,
7223                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7224 }
7225
7226 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7227                                       struct bnx2x_phy *phy,
7228                                       struct link_vars *vars)
7229 {
7230         u16 cl37_val;
7231         struct bnx2x *bp = params->bp;
7232         bnx2x_cl45_read(bp, phy,
7233                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7234
7235         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7236         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7237         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7238         if ((vars->ieee_fc &
7239             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7240             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7241                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7242         }
7243         if ((vars->ieee_fc &
7244             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7245             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7246                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7247         }
7248         if ((vars->ieee_fc &
7249             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7250             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7251                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7252         }
7253         DP(NETIF_MSG_LINK,
7254                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7255
7256         bnx2x_cl45_write(bp, phy,
7257                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7258         msleep(500);
7259 }
7260
7261 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7262                                      struct link_params *params,
7263                                      u32 action)
7264 {
7265         struct bnx2x *bp = params->bp;
7266         switch (action) {
7267         case PHY_INIT:
7268                 /* Enable LASI */
7269                 bnx2x_cl45_write(bp, phy,
7270                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7271                 bnx2x_cl45_write(bp, phy,
7272                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7273                 break;
7274         }
7275 }
7276
7277 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7278                                   struct link_params *params,
7279                                   struct link_vars *vars)
7280 {
7281         struct bnx2x *bp = params->bp;
7282         u16 val = 0, tmp1;
7283         u8 gpio_port;
7284         DP(NETIF_MSG_LINK, "Init 8073\n");
7285
7286         if (CHIP_IS_E2(bp))
7287                 gpio_port = BP_PATH(bp);
7288         else
7289                 gpio_port = params->port;
7290         /* Restore normal power mode*/
7291         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7292                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7293
7294         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7295                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7296
7297         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7298         bnx2x_8073_set_pause_cl37(params, phy, vars);
7299
7300         bnx2x_cl45_read(bp, phy,
7301                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7302
7303         bnx2x_cl45_read(bp, phy,
7304                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7305
7306         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7307
7308         /* Swap polarity if required - Must be done only in non-1G mode */
7309         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7310                 /* Configure the 8073 to swap _P and _N of the KR lines */
7311                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7312                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7313                 bnx2x_cl45_read(bp, phy,
7314                                 MDIO_PMA_DEVAD,
7315                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7316                 bnx2x_cl45_write(bp, phy,
7317                                  MDIO_PMA_DEVAD,
7318                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7319                                  (val | (3<<9)));
7320         }
7321
7322
7323         /* Enable CL37 BAM */
7324         if (REG_RD(bp, params->shmem_base +
7325                          offsetof(struct shmem_region, dev_info.
7326                                   port_hw_config[params->port].default_cfg)) &
7327             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7328
7329                 bnx2x_cl45_read(bp, phy,
7330                                 MDIO_AN_DEVAD,
7331                                 MDIO_AN_REG_8073_BAM, &val);
7332                 bnx2x_cl45_write(bp, phy,
7333                                  MDIO_AN_DEVAD,
7334                                  MDIO_AN_REG_8073_BAM, val | 1);
7335                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7336         }
7337         if (params->loopback_mode == LOOPBACK_EXT) {
7338                 bnx2x_807x_force_10G(bp, phy);
7339                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7340                 return 0;
7341         } else {
7342                 bnx2x_cl45_write(bp, phy,
7343                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7344         }
7345         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7346                 if (phy->req_line_speed == SPEED_10000) {
7347                         val = (1<<7);
7348                 } else if (phy->req_line_speed ==  SPEED_2500) {
7349                         val = (1<<5);
7350                         /* Note that 2.5G works only when used with 1G
7351                          * advertisement
7352                          */
7353                 } else
7354                         val = (1<<5);
7355         } else {
7356                 val = 0;
7357                 if (phy->speed_cap_mask &
7358                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7359                         val |= (1<<7);
7360
7361                 /* Note that 2.5G works only when used with 1G advertisement */
7362                 if (phy->speed_cap_mask &
7363                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7364                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7365                         val |= (1<<5);
7366                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7367         }
7368
7369         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7370         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7371
7372         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7373              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7374             (phy->req_line_speed == SPEED_2500)) {
7375                 u16 phy_ver;
7376                 /* Allow 2.5G for A1 and above */
7377                 bnx2x_cl45_read(bp, phy,
7378                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7379                                 &phy_ver);
7380                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7381                 if (phy_ver > 0)
7382                         tmp1 |= 1;
7383                 else
7384                         tmp1 &= 0xfffe;
7385         } else {
7386                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7387                 tmp1 &= 0xfffe;
7388         }
7389
7390         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7391         /* Add support for CL37 (passive mode) II */
7392
7393         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7394         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7395                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7396                                   0x20 : 0x40)));
7397
7398         /* Add support for CL37 (passive mode) III */
7399         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7400
7401         /* The SNR will improve about 2db by changing BW and FEE main
7402          * tap. Rest commands are executed after link is up
7403          * Change FFE main cursor to 5 in EDC register
7404          */
7405         if (bnx2x_8073_is_snr_needed(bp, phy))
7406                 bnx2x_cl45_write(bp, phy,
7407                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7408                                  0xFB0C);
7409
7410         /* Enable FEC (Forware Error Correction) Request in the AN */
7411         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7412         tmp1 |= (1<<15);
7413         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7414
7415         bnx2x_ext_phy_set_pause(params, phy, vars);
7416
7417         /* Restart autoneg */
7418         msleep(500);
7419         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7420         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7421                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7422         return 0;
7423 }
7424
7425 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7426                                  struct link_params *params,
7427                                  struct link_vars *vars)
7428 {
7429         struct bnx2x *bp = params->bp;
7430         u8 link_up = 0;
7431         u16 val1, val2;
7432         u16 link_status = 0;
7433         u16 an1000_status = 0;
7434
7435         bnx2x_cl45_read(bp, phy,
7436                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7437
7438         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7439
7440         /* Clear the interrupt LASI status register */
7441         bnx2x_cl45_read(bp, phy,
7442                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7443         bnx2x_cl45_read(bp, phy,
7444                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7445         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7446         /* Clear MSG-OUT */
7447         bnx2x_cl45_read(bp, phy,
7448                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7449
7450         /* Check the LASI */
7451         bnx2x_cl45_read(bp, phy,
7452                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7453
7454         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7455
7456         /* Check the link status */
7457         bnx2x_cl45_read(bp, phy,
7458                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7459         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7460
7461         bnx2x_cl45_read(bp, phy,
7462                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7463         bnx2x_cl45_read(bp, phy,
7464                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7465         link_up = ((val1 & 4) == 4);
7466         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7467
7468         if (link_up &&
7469              ((phy->req_line_speed != SPEED_10000))) {
7470                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7471                         return 0;
7472         }
7473         bnx2x_cl45_read(bp, phy,
7474                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7475         bnx2x_cl45_read(bp, phy,
7476                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7477
7478         /* Check the link status on 1.1.2 */
7479         bnx2x_cl45_read(bp, phy,
7480                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7481         bnx2x_cl45_read(bp, phy,
7482                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7483         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7484                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7485
7486         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7487         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7488                 /* The SNR will improve about 2dbby changing the BW and FEE main
7489                  * tap. The 1st write to change FFE main tap is set before
7490                  * restart AN. Change PLL Bandwidth in EDC register
7491                  */
7492                 bnx2x_cl45_write(bp, phy,
7493                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7494                                  0x26BC);
7495
7496                 /* Change CDR Bandwidth in EDC register */
7497                 bnx2x_cl45_write(bp, phy,
7498                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7499                                  0x0333);
7500         }
7501         bnx2x_cl45_read(bp, phy,
7502                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7503                         &link_status);
7504
7505         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7506         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7507                 link_up = 1;
7508                 vars->line_speed = SPEED_10000;
7509                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7510                            params->port);
7511         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7512                 link_up = 1;
7513                 vars->line_speed = SPEED_2500;
7514                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7515                            params->port);
7516         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7517                 link_up = 1;
7518                 vars->line_speed = SPEED_1000;
7519                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7520                            params->port);
7521         } else {
7522                 link_up = 0;
7523                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7524                            params->port);
7525         }
7526
7527         if (link_up) {
7528                 /* Swap polarity if required */
7529                 if (params->lane_config &
7530                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7531                         /* Configure the 8073 to swap P and N of the KR lines */
7532                         bnx2x_cl45_read(bp, phy,
7533                                         MDIO_XS_DEVAD,
7534                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7535                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7536                          * when it`s in 10G mode.
7537                          */
7538                         if (vars->line_speed == SPEED_1000) {
7539                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7540                                               "the 8073\n");
7541                                 val1 |= (1<<3);
7542                         } else
7543                                 val1 &= ~(1<<3);
7544
7545                         bnx2x_cl45_write(bp, phy,
7546                                          MDIO_XS_DEVAD,
7547                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7548                                          val1);
7549                 }
7550                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7551                 bnx2x_8073_resolve_fc(phy, params, vars);
7552                 vars->duplex = DUPLEX_FULL;
7553         }
7554
7555         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7556                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7557                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7558
7559                 if (val1 & (1<<5))
7560                         vars->link_status |=
7561                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7562                 if (val1 & (1<<7))
7563                         vars->link_status |=
7564                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7565         }
7566
7567         return link_up;
7568 }
7569
7570 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7571                                   struct link_params *params)
7572 {
7573         struct bnx2x *bp = params->bp;
7574         u8 gpio_port;
7575         if (CHIP_IS_E2(bp))
7576                 gpio_port = BP_PATH(bp);
7577         else
7578                 gpio_port = params->port;
7579         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7580            gpio_port);
7581         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7582                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7583                        gpio_port);
7584 }
7585
7586 /******************************************************************/
7587 /*                      BCM8705 PHY SECTION                       */
7588 /******************************************************************/
7589 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7590                                   struct link_params *params,
7591                                   struct link_vars *vars)
7592 {
7593         struct bnx2x *bp = params->bp;
7594         DP(NETIF_MSG_LINK, "init 8705\n");
7595         /* Restore normal power mode*/
7596         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7597                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7598         /* HW reset */
7599         bnx2x_ext_phy_hw_reset(bp, params->port);
7600         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7601         bnx2x_wait_reset_complete(bp, phy, params);
7602
7603         bnx2x_cl45_write(bp, phy,
7604                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7605         bnx2x_cl45_write(bp, phy,
7606                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7607         bnx2x_cl45_write(bp, phy,
7608                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7609         bnx2x_cl45_write(bp, phy,
7610                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7611         /* BCM8705 doesn't have microcode, hence the 0 */
7612         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7613         return 0;
7614 }
7615
7616 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7617                                  struct link_params *params,
7618                                  struct link_vars *vars)
7619 {
7620         u8 link_up = 0;
7621         u16 val1, rx_sd;
7622         struct bnx2x *bp = params->bp;
7623         DP(NETIF_MSG_LINK, "read status 8705\n");
7624         bnx2x_cl45_read(bp, phy,
7625                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7626         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7627
7628         bnx2x_cl45_read(bp, phy,
7629                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7630         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7631
7632         bnx2x_cl45_read(bp, phy,
7633                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7634
7635         bnx2x_cl45_read(bp, phy,
7636                       MDIO_PMA_DEVAD, 0xc809, &val1);
7637         bnx2x_cl45_read(bp, phy,
7638                       MDIO_PMA_DEVAD, 0xc809, &val1);
7639
7640         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7641         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7642         if (link_up) {
7643                 vars->line_speed = SPEED_10000;
7644                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7645         }
7646         return link_up;
7647 }
7648
7649 /******************************************************************/
7650 /*                      SFP+ module Section                       */
7651 /******************************************************************/
7652 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7653                                            struct bnx2x_phy *phy,
7654                                            u8 pmd_dis)
7655 {
7656         struct bnx2x *bp = params->bp;
7657         /* Disable transmitter only for bootcodes which can enable it afterwards
7658          * (for D3 link)
7659          */
7660         if (pmd_dis) {
7661                 if (params->feature_config_flags &
7662                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7663                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7664                 else {
7665                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7666                         return;
7667                 }
7668         } else
7669                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7670         bnx2x_cl45_write(bp, phy,
7671                          MDIO_PMA_DEVAD,
7672                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7673 }
7674
7675 static u8 bnx2x_get_gpio_port(struct link_params *params)
7676 {
7677         u8 gpio_port;
7678         u32 swap_val, swap_override;
7679         struct bnx2x *bp = params->bp;
7680         if (CHIP_IS_E2(bp))
7681                 gpio_port = BP_PATH(bp);
7682         else
7683                 gpio_port = params->port;
7684         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7685         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7686         return gpio_port ^ (swap_val && swap_override);
7687 }
7688
7689 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7690                                            struct bnx2x_phy *phy,
7691                                            u8 tx_en)
7692 {
7693         u16 val;
7694         u8 port = params->port;
7695         struct bnx2x *bp = params->bp;
7696         u32 tx_en_mode;
7697
7698         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7699         tx_en_mode = REG_RD(bp, params->shmem_base +
7700                             offsetof(struct shmem_region,
7701                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7702                 PORT_HW_CFG_TX_LASER_MASK;
7703         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7704                            "mode = %x\n", tx_en, port, tx_en_mode);
7705         switch (tx_en_mode) {
7706         case PORT_HW_CFG_TX_LASER_MDIO:
7707
7708                 bnx2x_cl45_read(bp, phy,
7709                                 MDIO_PMA_DEVAD,
7710                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7711                                 &val);
7712
7713                 if (tx_en)
7714                         val &= ~(1<<15);
7715                 else
7716                         val |= (1<<15);
7717
7718                 bnx2x_cl45_write(bp, phy,
7719                                  MDIO_PMA_DEVAD,
7720                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7721                                  val);
7722         break;
7723         case PORT_HW_CFG_TX_LASER_GPIO0:
7724         case PORT_HW_CFG_TX_LASER_GPIO1:
7725         case PORT_HW_CFG_TX_LASER_GPIO2:
7726         case PORT_HW_CFG_TX_LASER_GPIO3:
7727         {
7728                 u16 gpio_pin;
7729                 u8 gpio_port, gpio_mode;
7730                 if (tx_en)
7731                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7732                 else
7733                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7734
7735                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7736                 gpio_port = bnx2x_get_gpio_port(params);
7737                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7738                 break;
7739         }
7740         default:
7741                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7742                 break;
7743         }
7744 }
7745
7746 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7747                                       struct bnx2x_phy *phy,
7748                                       u8 tx_en)
7749 {
7750         struct bnx2x *bp = params->bp;
7751         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7752         if (CHIP_IS_E3(bp))
7753                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7754         else
7755                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7756 }
7757
7758 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7759                                              struct link_params *params,
7760                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7761                                              u8 *o_buf, u8 is_init)
7762 {
7763         struct bnx2x *bp = params->bp;
7764         u16 val = 0;
7765         u16 i;
7766         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7767                 DP(NETIF_MSG_LINK,
7768                    "Reading from eeprom is limited to 0xf\n");
7769                 return -EINVAL;
7770         }
7771         /* Set the read command byte count */
7772         bnx2x_cl45_write(bp, phy,
7773                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7774                          (byte_cnt | (dev_addr << 8)));
7775
7776         /* Set the read command address */
7777         bnx2x_cl45_write(bp, phy,
7778                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7779                          addr);
7780
7781         /* Activate read command */
7782         bnx2x_cl45_write(bp, phy,
7783                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7784                          0x2c0f);
7785
7786         /* Wait up to 500us for command complete status */
7787         for (i = 0; i < 100; i++) {
7788                 bnx2x_cl45_read(bp, phy,
7789                                 MDIO_PMA_DEVAD,
7790                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7791                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7792                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7793                         break;
7794                 udelay(5);
7795         }
7796
7797         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7798                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7799                 DP(NETIF_MSG_LINK,
7800                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7801                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7802                 return -EINVAL;
7803         }
7804
7805         /* Read the buffer */
7806         for (i = 0; i < byte_cnt; i++) {
7807                 bnx2x_cl45_read(bp, phy,
7808                                 MDIO_PMA_DEVAD,
7809                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7810                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7811         }
7812
7813         for (i = 0; i < 100; i++) {
7814                 bnx2x_cl45_read(bp, phy,
7815                                 MDIO_PMA_DEVAD,
7816                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7817                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7818                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7819                         return 0;
7820                 usleep_range(1000, 2000);
7821         }
7822         return -EINVAL;
7823 }
7824
7825 static void bnx2x_warpcore_power_module(struct link_params *params,
7826                                         u8 power)
7827 {
7828         u32 pin_cfg;
7829         struct bnx2x *bp = params->bp;
7830
7831         pin_cfg = (REG_RD(bp, params->shmem_base +
7832                           offsetof(struct shmem_region,
7833                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7834                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7835                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7836
7837         if (pin_cfg == PIN_CFG_NA)
7838                 return;
7839         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7840                        power, pin_cfg);
7841         /* Low ==> corresponding SFP+ module is powered
7842          * high ==> the SFP+ module is powered down
7843          */
7844         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7845 }
7846 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7847                                                  struct link_params *params,
7848                                                  u8 dev_addr,
7849                                                  u16 addr, u8 byte_cnt,
7850                                                  u8 *o_buf, u8 is_init)
7851 {
7852         int rc = 0;
7853         u8 i, j = 0, cnt = 0;
7854         u32 data_array[4];
7855         u16 addr32;
7856         struct bnx2x *bp = params->bp;
7857
7858         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7859                 DP(NETIF_MSG_LINK,
7860                    "Reading from eeprom is limited to 16 bytes\n");
7861                 return -EINVAL;
7862         }
7863
7864         /* 4 byte aligned address */
7865         addr32 = addr & (~0x3);
7866         do {
7867                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7868                         bnx2x_warpcore_power_module(params, 0);
7869                         /* Note that 100us are not enough here */
7870                         usleep_range(1000, 2000);
7871                         bnx2x_warpcore_power_module(params, 1);
7872                 }
7873                 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt,
7874                                     data_array);
7875         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7876
7877         if (rc == 0) {
7878                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7879                         o_buf[j] = *((u8 *)data_array + i);
7880                         j++;
7881                 }
7882         }
7883
7884         return rc;
7885 }
7886
7887 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7888                                              struct link_params *params,
7889                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7890                                              u8 *o_buf, u8 is_init)
7891 {
7892         struct bnx2x *bp = params->bp;
7893         u16 val, i;
7894
7895         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7896                 DP(NETIF_MSG_LINK,
7897                    "Reading from eeprom is limited to 0xf\n");
7898                 return -EINVAL;
7899         }
7900
7901         /* Set 2-wire transfer rate of SFP+ module EEPROM
7902          * to 100Khz since some DACs(direct attached cables) do
7903          * not work at 400Khz.
7904          */
7905         bnx2x_cl45_write(bp, phy,
7906                          MDIO_PMA_DEVAD,
7907                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7908                          ((dev_addr << 8) | 1));
7909
7910         /* Need to read from 1.8000 to clear it */
7911         bnx2x_cl45_read(bp, phy,
7912                         MDIO_PMA_DEVAD,
7913                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7914                         &val);
7915
7916         /* Set the read command byte count */
7917         bnx2x_cl45_write(bp, phy,
7918                          MDIO_PMA_DEVAD,
7919                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7920                          ((byte_cnt < 2) ? 2 : byte_cnt));
7921
7922         /* Set the read command address */
7923         bnx2x_cl45_write(bp, phy,
7924                          MDIO_PMA_DEVAD,
7925                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7926                          addr);
7927         /* Set the destination address */
7928         bnx2x_cl45_write(bp, phy,
7929                          MDIO_PMA_DEVAD,
7930                          0x8004,
7931                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7932
7933         /* Activate read command */
7934         bnx2x_cl45_write(bp, phy,
7935                          MDIO_PMA_DEVAD,
7936                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7937                          0x8002);
7938         /* Wait appropriate time for two-wire command to finish before
7939          * polling the status register
7940          */
7941         usleep_range(1000, 2000);
7942
7943         /* Wait up to 500us for command complete status */
7944         for (i = 0; i < 100; i++) {
7945                 bnx2x_cl45_read(bp, phy,
7946                                 MDIO_PMA_DEVAD,
7947                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7948                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7949                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7950                         break;
7951                 udelay(5);
7952         }
7953
7954         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7955                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7956                 DP(NETIF_MSG_LINK,
7957                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7958                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7959                 return -EFAULT;
7960         }
7961
7962         /* Read the buffer */
7963         for (i = 0; i < byte_cnt; i++) {
7964                 bnx2x_cl45_read(bp, phy,
7965                                 MDIO_PMA_DEVAD,
7966                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7967                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7968         }
7969
7970         for (i = 0; i < 100; i++) {
7971                 bnx2x_cl45_read(bp, phy,
7972                                 MDIO_PMA_DEVAD,
7973                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7974                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7975                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7976                         return 0;
7977                 usleep_range(1000, 2000);
7978         }
7979
7980         return -EINVAL;
7981 }
7982 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7983                                  struct link_params *params, u8 dev_addr,
7984                                  u16 addr, u16 byte_cnt, u8 *o_buf)
7985 {
7986         int rc = 0;
7987         struct bnx2x *bp = params->bp;
7988         u8 xfer_size;
7989         u8 *user_data = o_buf;
7990         read_sfp_module_eeprom_func_p read_func;
7991
7992         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
7993                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
7994                 return -EINVAL;
7995         }
7996
7997         switch (phy->type) {
7998         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7999                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8000                 break;
8001         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8002         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8003                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8004                 break;
8005         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8006                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8007                 break;
8008         default:
8009                 return -EOPNOTSUPP;
8010         }
8011
8012         while (!rc && (byte_cnt > 0)) {
8013                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8014                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8015                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8016                                user_data, 0);
8017                 byte_cnt -= xfer_size;
8018                 user_data += xfer_size;
8019                 addr += xfer_size;
8020         }
8021         return rc;
8022 }
8023
8024 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8025                               struct link_params *params,
8026                               u16 *edc_mode)
8027 {
8028         struct bnx2x *bp = params->bp;
8029         u32 sync_offset = 0, phy_idx, media_types;
8030         u8 gport, val[2], check_limiting_mode = 0;
8031         *edc_mode = EDC_MODE_LIMITING;
8032         phy->media_type = ETH_PHY_UNSPECIFIED;
8033         /* First check for copper cable */
8034         if (bnx2x_read_sfp_module_eeprom(phy,
8035                                          params,
8036                                          I2C_DEV_ADDR_A0,
8037                                          SFP_EEPROM_CON_TYPE_ADDR,
8038                                          2,
8039                                          (u8 *)val) != 0) {
8040                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8041                 return -EINVAL;
8042         }
8043
8044         switch (val[0]) {
8045         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8046         {
8047                 u8 copper_module_type;
8048                 phy->media_type = ETH_PHY_DA_TWINAX;
8049                 /* Check if its active cable (includes SFP+ module)
8050                  * of passive cable
8051                  */
8052                 if (bnx2x_read_sfp_module_eeprom(phy,
8053                                                params,
8054                                                I2C_DEV_ADDR_A0,
8055                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8056                                                1,
8057                                                &copper_module_type) != 0) {
8058                         DP(NETIF_MSG_LINK,
8059                                 "Failed to read copper-cable-type"
8060                                 " from SFP+ EEPROM\n");
8061                         return -EINVAL;
8062                 }
8063
8064                 if (copper_module_type &
8065                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8066                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8067                         check_limiting_mode = 1;
8068                 } else if (copper_module_type &
8069                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8070                                 DP(NETIF_MSG_LINK,
8071                                    "Passive Copper cable detected\n");
8072                                 *edc_mode =
8073                                       EDC_MODE_PASSIVE_DAC;
8074                 } else {
8075                         DP(NETIF_MSG_LINK,
8076                            "Unknown copper-cable-type 0x%x !!!\n",
8077                            copper_module_type);
8078                         return -EINVAL;
8079                 }
8080                 break;
8081         }
8082         case SFP_EEPROM_CON_TYPE_VAL_LC:
8083         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8084                 check_limiting_mode = 1;
8085                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8086                                SFP_EEPROM_COMP_CODE_LR_MASK |
8087                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8088                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8089                         gport = params->port;
8090                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8091                         if (phy->req_line_speed != SPEED_1000) {
8092                                 phy->req_line_speed = SPEED_1000;
8093                                 if (!CHIP_IS_E1x(bp)) {
8094                                         gport = BP_PATH(bp) +
8095                                         (params->port << 1);
8096                                 }
8097                                 netdev_err(bp->dev,
8098                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8099                                            gport);
8100                         }
8101                 } else {
8102                         int idx, cfg_idx = 0;
8103                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8104                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8105                                 if (params->phy[idx].type == phy->type) {
8106                                         cfg_idx = LINK_CONFIG_IDX(idx);
8107                                         break;
8108                                 }
8109                         }
8110                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8111                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8112                 }
8113                 break;
8114         default:
8115                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8116                          val[0]);
8117                 return -EINVAL;
8118         }
8119         sync_offset = params->shmem_base +
8120                 offsetof(struct shmem_region,
8121                          dev_info.port_hw_config[params->port].media_type);
8122         media_types = REG_RD(bp, sync_offset);
8123         /* Update media type for non-PMF sync */
8124         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8125                 if (&(params->phy[phy_idx]) == phy) {
8126                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8127                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8128                         media_types |= ((phy->media_type &
8129                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8130                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8131                         break;
8132                 }
8133         }
8134         REG_WR(bp, sync_offset, media_types);
8135         if (check_limiting_mode) {
8136                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8137                 if (bnx2x_read_sfp_module_eeprom(phy,
8138                                                  params,
8139                                                  I2C_DEV_ADDR_A0,
8140                                                  SFP_EEPROM_OPTIONS_ADDR,
8141                                                  SFP_EEPROM_OPTIONS_SIZE,
8142                                                  options) != 0) {
8143                         DP(NETIF_MSG_LINK,
8144                            "Failed to read Option field from module EEPROM\n");
8145                         return -EINVAL;
8146                 }
8147                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8148                         *edc_mode = EDC_MODE_LINEAR;
8149                 else
8150                         *edc_mode = EDC_MODE_LIMITING;
8151         }
8152         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8153         return 0;
8154 }
8155 /* This function read the relevant field from the module (SFP+), and verify it
8156  * is compliant with this board
8157  */
8158 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8159                                    struct link_params *params)
8160 {
8161         struct bnx2x *bp = params->bp;
8162         u32 val, cmd;
8163         u32 fw_resp, fw_cmd_param;
8164         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8165         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8166         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8167         val = REG_RD(bp, params->shmem_base +
8168                          offsetof(struct shmem_region, dev_info.
8169                                   port_feature_config[params->port].config));
8170         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8171             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8172                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8173                 return 0;
8174         }
8175
8176         if (params->feature_config_flags &
8177             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8178                 /* Use specific phy request */
8179                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8180         } else if (params->feature_config_flags &
8181                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8182                 /* Use first phy request only in case of non-dual media*/
8183                 if (DUAL_MEDIA(params)) {
8184                         DP(NETIF_MSG_LINK,
8185                            "FW does not support OPT MDL verification\n");
8186                         return -EINVAL;
8187                 }
8188                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8189         } else {
8190                 /* No support in OPT MDL detection */
8191                 DP(NETIF_MSG_LINK,
8192                    "FW does not support OPT MDL verification\n");
8193                 return -EINVAL;
8194         }
8195
8196         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8197         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8198         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8199                 DP(NETIF_MSG_LINK, "Approved module\n");
8200                 return 0;
8201         }
8202
8203         /* Format the warning message */
8204         if (bnx2x_read_sfp_module_eeprom(phy,
8205                                          params,
8206                                          I2C_DEV_ADDR_A0,
8207                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8208                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8209                                          (u8 *)vendor_name))
8210                 vendor_name[0] = '\0';
8211         else
8212                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8213         if (bnx2x_read_sfp_module_eeprom(phy,
8214                                          params,
8215                                          I2C_DEV_ADDR_A0,
8216                                          SFP_EEPROM_PART_NO_ADDR,
8217                                          SFP_EEPROM_PART_NO_SIZE,
8218                                          (u8 *)vendor_pn))
8219                 vendor_pn[0] = '\0';
8220         else
8221                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8222
8223         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8224                               " Port %d from %s part number %s\n",
8225                          params->port, vendor_name, vendor_pn);
8226         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8227             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8228                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8229         return -EINVAL;
8230 }
8231
8232 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8233                                                  struct link_params *params)
8234
8235 {
8236         u8 val;
8237         int rc;
8238         struct bnx2x *bp = params->bp;
8239         u16 timeout;
8240         /* Initialization time after hot-plug may take up to 300ms for
8241          * some phys type ( e.g. JDSU )
8242          */
8243
8244         for (timeout = 0; timeout < 60; timeout++) {
8245                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8246                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8247                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8248                                 1);
8249                 else
8250                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8251                                                           I2C_DEV_ADDR_A0,
8252                                                           1, 1, &val);
8253                 if (rc == 0) {
8254                         DP(NETIF_MSG_LINK,
8255                            "SFP+ module initialization took %d ms\n",
8256                            timeout * 5);
8257                         return 0;
8258                 }
8259                 usleep_range(5000, 10000);
8260         }
8261         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8262                                           1, 1, &val);
8263         return rc;
8264 }
8265
8266 static void bnx2x_8727_power_module(struct bnx2x *bp,
8267                                     struct bnx2x_phy *phy,
8268                                     u8 is_power_up) {
8269         /* Make sure GPIOs are not using for LED mode */
8270         u16 val;
8271         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8272          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8273          * output
8274          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8275          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8276          * where the 1st bit is the over-current(only input), and 2nd bit is
8277          * for power( only output )
8278          *
8279          * In case of NOC feature is disabled and power is up, set GPIO control
8280          *  as input to enable listening of over-current indication
8281          */
8282         if (phy->flags & FLAGS_NOC)
8283                 return;
8284         if (is_power_up)
8285                 val = (1<<4);
8286         else
8287                 /* Set GPIO control to OUTPUT, and set the power bit
8288                  * to according to the is_power_up
8289                  */
8290                 val = (1<<1);
8291
8292         bnx2x_cl45_write(bp, phy,
8293                          MDIO_PMA_DEVAD,
8294                          MDIO_PMA_REG_8727_GPIO_CTRL,
8295                          val);
8296 }
8297
8298 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8299                                         struct bnx2x_phy *phy,
8300                                         u16 edc_mode)
8301 {
8302         u16 cur_limiting_mode;
8303
8304         bnx2x_cl45_read(bp, phy,
8305                         MDIO_PMA_DEVAD,
8306                         MDIO_PMA_REG_ROM_VER2,
8307                         &cur_limiting_mode);
8308         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8309                  cur_limiting_mode);
8310
8311         if (edc_mode == EDC_MODE_LIMITING) {
8312                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8313                 bnx2x_cl45_write(bp, phy,
8314                                  MDIO_PMA_DEVAD,
8315                                  MDIO_PMA_REG_ROM_VER2,
8316                                  EDC_MODE_LIMITING);
8317         } else { /* LRM mode ( default )*/
8318
8319                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8320
8321                 /* Changing to LRM mode takes quite few seconds. So do it only
8322                  * if current mode is limiting (default is LRM)
8323                  */
8324                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8325                         return 0;
8326
8327                 bnx2x_cl45_write(bp, phy,
8328                                  MDIO_PMA_DEVAD,
8329                                  MDIO_PMA_REG_LRM_MODE,
8330                                  0);
8331                 bnx2x_cl45_write(bp, phy,
8332                                  MDIO_PMA_DEVAD,
8333                                  MDIO_PMA_REG_ROM_VER2,
8334                                  0x128);
8335                 bnx2x_cl45_write(bp, phy,
8336                                  MDIO_PMA_DEVAD,
8337                                  MDIO_PMA_REG_MISC_CTRL0,
8338                                  0x4008);
8339                 bnx2x_cl45_write(bp, phy,
8340                                  MDIO_PMA_DEVAD,
8341                                  MDIO_PMA_REG_LRM_MODE,
8342                                  0xaaaa);
8343         }
8344         return 0;
8345 }
8346
8347 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8348                                         struct bnx2x_phy *phy,
8349                                         u16 edc_mode)
8350 {
8351         u16 phy_identifier;
8352         u16 rom_ver2_val;
8353         bnx2x_cl45_read(bp, phy,
8354                         MDIO_PMA_DEVAD,
8355                         MDIO_PMA_REG_PHY_IDENTIFIER,
8356                         &phy_identifier);
8357
8358         bnx2x_cl45_write(bp, phy,
8359                          MDIO_PMA_DEVAD,
8360                          MDIO_PMA_REG_PHY_IDENTIFIER,
8361                          (phy_identifier & ~(1<<9)));
8362
8363         bnx2x_cl45_read(bp, phy,
8364                         MDIO_PMA_DEVAD,
8365                         MDIO_PMA_REG_ROM_VER2,
8366                         &rom_ver2_val);
8367         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8368         bnx2x_cl45_write(bp, phy,
8369                          MDIO_PMA_DEVAD,
8370                          MDIO_PMA_REG_ROM_VER2,
8371                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8372
8373         bnx2x_cl45_write(bp, phy,
8374                          MDIO_PMA_DEVAD,
8375                          MDIO_PMA_REG_PHY_IDENTIFIER,
8376                          (phy_identifier | (1<<9)));
8377
8378         return 0;
8379 }
8380
8381 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8382                                      struct link_params *params,
8383                                      u32 action)
8384 {
8385         struct bnx2x *bp = params->bp;
8386         u16 val;
8387         switch (action) {
8388         case DISABLE_TX:
8389                 bnx2x_sfp_set_transmitter(params, phy, 0);
8390                 break;
8391         case ENABLE_TX:
8392                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8393                         bnx2x_sfp_set_transmitter(params, phy, 1);
8394                 break;
8395         case PHY_INIT:
8396                 bnx2x_cl45_write(bp, phy,
8397                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8398                                  (1<<2) | (1<<5));
8399                 bnx2x_cl45_write(bp, phy,
8400                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8401                                  0);
8402                 bnx2x_cl45_write(bp, phy,
8403                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8404                 /* Make MOD_ABS give interrupt on change */
8405                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8406                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8407                                 &val);
8408                 val |= (1<<12);
8409                 if (phy->flags & FLAGS_NOC)
8410                         val |= (3<<5);
8411                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8412                  * status which reflect SFP+ module over-current
8413                  */
8414                 if (!(phy->flags & FLAGS_NOC))
8415                         val &= 0xff8f; /* Reset bits 4-6 */
8416                 bnx2x_cl45_write(bp, phy,
8417                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8418                                  val);
8419                 break;
8420         default:
8421                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8422                    action);
8423                 return;
8424         }
8425 }
8426
8427 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8428                                            u8 gpio_mode)
8429 {
8430         struct bnx2x *bp = params->bp;
8431
8432         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8433                             offsetof(struct shmem_region,
8434                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8435                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8436         switch (fault_led_gpio) {
8437         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8438                 return;
8439         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8440         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8441         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8442         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8443         {
8444                 u8 gpio_port = bnx2x_get_gpio_port(params);
8445                 u16 gpio_pin = fault_led_gpio -
8446                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8447                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8448                                    "pin %x port %x mode %x\n",
8449                                gpio_pin, gpio_port, gpio_mode);
8450                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8451         }
8452         break;
8453         default:
8454                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8455                                fault_led_gpio);
8456         }
8457 }
8458
8459 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8460                                           u8 gpio_mode)
8461 {
8462         u32 pin_cfg;
8463         u8 port = params->port;
8464         struct bnx2x *bp = params->bp;
8465         pin_cfg = (REG_RD(bp, params->shmem_base +
8466                          offsetof(struct shmem_region,
8467                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8468                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8469                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8470         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8471                        gpio_mode, pin_cfg);
8472         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8473 }
8474
8475 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8476                                            u8 gpio_mode)
8477 {
8478         struct bnx2x *bp = params->bp;
8479         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8480         if (CHIP_IS_E3(bp)) {
8481                 /* Low ==> if SFP+ module is supported otherwise
8482                  * High ==> if SFP+ module is not on the approved vendor list
8483                  */
8484                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8485         } else
8486                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8487 }
8488
8489 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8490                                     struct link_params *params)
8491 {
8492         struct bnx2x *bp = params->bp;
8493         bnx2x_warpcore_power_module(params, 0);
8494         /* Put Warpcore in low power mode */
8495         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8496
8497         /* Put LCPLL in low power mode */
8498         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8499         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8500         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8501 }
8502
8503 static void bnx2x_power_sfp_module(struct link_params *params,
8504                                    struct bnx2x_phy *phy,
8505                                    u8 power)
8506 {
8507         struct bnx2x *bp = params->bp;
8508         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8509
8510         switch (phy->type) {
8511         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8512         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8513                 bnx2x_8727_power_module(params->bp, phy, power);
8514                 break;
8515         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8516                 bnx2x_warpcore_power_module(params, power);
8517                 break;
8518         default:
8519                 break;
8520         }
8521 }
8522 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8523                                              struct bnx2x_phy *phy,
8524                                              u16 edc_mode)
8525 {
8526         u16 val = 0;
8527         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8528         struct bnx2x *bp = params->bp;
8529
8530         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8531         /* This is a global register which controls all lanes */
8532         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8533                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8534         val &= ~(0xf << (lane << 2));
8535
8536         switch (edc_mode) {
8537         case EDC_MODE_LINEAR:
8538         case EDC_MODE_LIMITING:
8539                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8540                 break;
8541         case EDC_MODE_PASSIVE_DAC:
8542                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8543                 break;
8544         default:
8545                 break;
8546         }
8547
8548         val |= (mode << (lane << 2));
8549         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8550                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8551         /* A must read */
8552         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8553                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8554
8555         /* Restart microcode to re-read the new mode */
8556         bnx2x_warpcore_reset_lane(bp, phy, 1);
8557         bnx2x_warpcore_reset_lane(bp, phy, 0);
8558
8559 }
8560
8561 static void bnx2x_set_limiting_mode(struct link_params *params,
8562                                     struct bnx2x_phy *phy,
8563                                     u16 edc_mode)
8564 {
8565         switch (phy->type) {
8566         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8567                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8568                 break;
8569         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8570         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8571                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8572                 break;
8573         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8574                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8575                 break;
8576         }
8577 }
8578
8579 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8580                                struct link_params *params)
8581 {
8582         struct bnx2x *bp = params->bp;
8583         u16 edc_mode;
8584         int rc = 0;
8585
8586         u32 val = REG_RD(bp, params->shmem_base +
8587                              offsetof(struct shmem_region, dev_info.
8588                                      port_feature_config[params->port].config));
8589         /* Enabled transmitter by default */
8590         bnx2x_sfp_set_transmitter(params, phy, 1);
8591         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8592                  params->port);
8593         /* Power up module */
8594         bnx2x_power_sfp_module(params, phy, 1);
8595         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8596                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8597                 return -EINVAL;
8598         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8599                 /* Check SFP+ module compatibility */
8600                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8601                 rc = -EINVAL;
8602                 /* Turn on fault module-detected led */
8603                 bnx2x_set_sfp_module_fault_led(params,
8604                                                MISC_REGISTERS_GPIO_HIGH);
8605
8606                 /* Check if need to power down the SFP+ module */
8607                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8608                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8609                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8610                         bnx2x_power_sfp_module(params, phy, 0);
8611                         return rc;
8612                 }
8613         } else {
8614                 /* Turn off fault module-detected led */
8615                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8616         }
8617
8618         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8619          * is done automatically
8620          */
8621         bnx2x_set_limiting_mode(params, phy, edc_mode);
8622
8623         /* Disable transmit for this module if the module is not approved, and
8624          * laser needs to be disabled.
8625          */
8626         if ((rc) &&
8627             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8628              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8629                 bnx2x_sfp_set_transmitter(params, phy, 0);
8630
8631         return rc;
8632 }
8633
8634 void bnx2x_handle_module_detect_int(struct link_params *params)
8635 {
8636         struct bnx2x *bp = params->bp;
8637         struct bnx2x_phy *phy;
8638         u32 gpio_val;
8639         u8 gpio_num, gpio_port;
8640         if (CHIP_IS_E3(bp)) {
8641                 phy = &params->phy[INT_PHY];
8642                 /* Always enable TX laser,will be disabled in case of fault */
8643                 bnx2x_sfp_set_transmitter(params, phy, 1);
8644         } else {
8645                 phy = &params->phy[EXT_PHY1];
8646         }
8647         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8648                                       params->port, &gpio_num, &gpio_port) ==
8649             -EINVAL) {
8650                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8651                 return;
8652         }
8653
8654         /* Set valid module led off */
8655         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8656
8657         /* Get current gpio val reflecting module plugged in / out*/
8658         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8659
8660         /* Call the handling function in case module is detected */
8661         if (gpio_val == 0) {
8662                 bnx2x_set_mdio_emac_per_phy(bp, params);
8663                 bnx2x_set_aer_mmd(params, phy);
8664
8665                 bnx2x_power_sfp_module(params, phy, 1);
8666                 bnx2x_set_gpio_int(bp, gpio_num,
8667                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8668                                    gpio_port);
8669                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8670                         bnx2x_sfp_module_detection(phy, params);
8671                         if (CHIP_IS_E3(bp)) {
8672                                 u16 rx_tx_in_reset;
8673                                 /* In case WC is out of reset, reconfigure the
8674                                  * link speed while taking into account 1G
8675                                  * module limitation.
8676                                  */
8677                                 bnx2x_cl45_read(bp, phy,
8678                                                 MDIO_WC_DEVAD,
8679                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8680                                                 &rx_tx_in_reset);
8681                                 if ((!rx_tx_in_reset) &&
8682                                     (params->link_flags &
8683                                      PHY_INITIALIZED)) {
8684                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8685                                         bnx2x_warpcore_config_sfi(phy, params);
8686                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8687                                 }
8688                         }
8689                 } else {
8690                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8691                 }
8692         } else {
8693                 bnx2x_set_gpio_int(bp, gpio_num,
8694                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8695                                    gpio_port);
8696                 /* Module was plugged out.
8697                  * Disable transmit for this module
8698                  */
8699                 phy->media_type = ETH_PHY_NOT_PRESENT;
8700         }
8701 }
8702
8703 /******************************************************************/
8704 /*              Used by 8706 and 8727                             */
8705 /******************************************************************/
8706 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8707                                  struct bnx2x_phy *phy,
8708                                  u16 alarm_status_offset,
8709                                  u16 alarm_ctrl_offset)
8710 {
8711         u16 alarm_status, val;
8712         bnx2x_cl45_read(bp, phy,
8713                         MDIO_PMA_DEVAD, alarm_status_offset,
8714                         &alarm_status);
8715         bnx2x_cl45_read(bp, phy,
8716                         MDIO_PMA_DEVAD, alarm_status_offset,
8717                         &alarm_status);
8718         /* Mask or enable the fault event. */
8719         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8720         if (alarm_status & (1<<0))
8721                 val &= ~(1<<0);
8722         else
8723                 val |= (1<<0);
8724         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8725 }
8726 /******************************************************************/
8727 /*              common BCM8706/BCM8726 PHY SECTION                */
8728 /******************************************************************/
8729 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8730                                       struct link_params *params,
8731                                       struct link_vars *vars)
8732 {
8733         u8 link_up = 0;
8734         u16 val1, val2, rx_sd, pcs_status;
8735         struct bnx2x *bp = params->bp;
8736         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8737         /* Clear RX Alarm*/
8738         bnx2x_cl45_read(bp, phy,
8739                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8740
8741         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8742                              MDIO_PMA_LASI_TXCTRL);
8743
8744         /* Clear LASI indication*/
8745         bnx2x_cl45_read(bp, phy,
8746                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8747         bnx2x_cl45_read(bp, phy,
8748                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8749         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8750
8751         bnx2x_cl45_read(bp, phy,
8752                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8753         bnx2x_cl45_read(bp, phy,
8754                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8755         bnx2x_cl45_read(bp, phy,
8756                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8757         bnx2x_cl45_read(bp, phy,
8758                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8759
8760         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8761                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8762         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8763          * are set, or if the autoneg bit 1 is set
8764          */
8765         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8766         if (link_up) {
8767                 if (val2 & (1<<1))
8768                         vars->line_speed = SPEED_1000;
8769                 else
8770                         vars->line_speed = SPEED_10000;
8771                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8772                 vars->duplex = DUPLEX_FULL;
8773         }
8774
8775         /* Capture 10G link fault. Read twice to clear stale value. */
8776         if (vars->line_speed == SPEED_10000) {
8777                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8778                             MDIO_PMA_LASI_TXSTAT, &val1);
8779                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8780                             MDIO_PMA_LASI_TXSTAT, &val1);
8781                 if (val1 & (1<<0))
8782                         vars->fault_detected = 1;
8783         }
8784
8785         return link_up;
8786 }
8787
8788 /******************************************************************/
8789 /*                      BCM8706 PHY SECTION                       */
8790 /******************************************************************/
8791 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8792                                  struct link_params *params,
8793                                  struct link_vars *vars)
8794 {
8795         u32 tx_en_mode;
8796         u16 cnt, val, tmp1;
8797         struct bnx2x *bp = params->bp;
8798
8799         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8800                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8801         /* HW reset */
8802         bnx2x_ext_phy_hw_reset(bp, params->port);
8803         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8804         bnx2x_wait_reset_complete(bp, phy, params);
8805
8806         /* Wait until fw is loaded */
8807         for (cnt = 0; cnt < 100; cnt++) {
8808                 bnx2x_cl45_read(bp, phy,
8809                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8810                 if (val)
8811                         break;
8812                 usleep_range(10000, 20000);
8813         }
8814         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8815         if ((params->feature_config_flags &
8816              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8817                 u8 i;
8818                 u16 reg;
8819                 for (i = 0; i < 4; i++) {
8820                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8821                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8822                                    MDIO_XS_8706_REG_BANK_RX0);
8823                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8824                         /* Clear first 3 bits of the control */
8825                         val &= ~0x7;
8826                         /* Set control bits according to configuration */
8827                         val |= (phy->rx_preemphasis[i] & 0x7);
8828                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8829                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8830                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8831                 }
8832         }
8833         /* Force speed */
8834         if (phy->req_line_speed == SPEED_10000) {
8835                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8836
8837                 bnx2x_cl45_write(bp, phy,
8838                                  MDIO_PMA_DEVAD,
8839                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8840                 bnx2x_cl45_write(bp, phy,
8841                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8842                                  0);
8843                 /* Arm LASI for link and Tx fault. */
8844                 bnx2x_cl45_write(bp, phy,
8845                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8846         } else {
8847                 /* Force 1Gbps using autoneg with 1G advertisement */
8848
8849                 /* Allow CL37 through CL73 */
8850                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8851                 bnx2x_cl45_write(bp, phy,
8852                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8853
8854                 /* Enable Full-Duplex advertisement on CL37 */
8855                 bnx2x_cl45_write(bp, phy,
8856                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8857                 /* Enable CL37 AN */
8858                 bnx2x_cl45_write(bp, phy,
8859                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8860                 /* 1G support */
8861                 bnx2x_cl45_write(bp, phy,
8862                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8863
8864                 /* Enable clause 73 AN */
8865                 bnx2x_cl45_write(bp, phy,
8866                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8867                 bnx2x_cl45_write(bp, phy,
8868                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8869                                  0x0400);
8870                 bnx2x_cl45_write(bp, phy,
8871                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8872                                  0x0004);
8873         }
8874         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8875
8876         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8877          * power mode, if TX Laser is disabled
8878          */
8879
8880         tx_en_mode = REG_RD(bp, params->shmem_base +
8881                             offsetof(struct shmem_region,
8882                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8883                         & PORT_HW_CFG_TX_LASER_MASK;
8884
8885         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8886                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8887                 bnx2x_cl45_read(bp, phy,
8888                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8889                 tmp1 |= 0x1;
8890                 bnx2x_cl45_write(bp, phy,
8891                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8892         }
8893
8894         return 0;
8895 }
8896
8897 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8898                                   struct link_params *params,
8899                                   struct link_vars *vars)
8900 {
8901         return bnx2x_8706_8726_read_status(phy, params, vars);
8902 }
8903
8904 /******************************************************************/
8905 /*                      BCM8726 PHY SECTION                       */
8906 /******************************************************************/
8907 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8908                                        struct link_params *params)
8909 {
8910         struct bnx2x *bp = params->bp;
8911         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8912         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8913 }
8914
8915 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8916                                          struct link_params *params)
8917 {
8918         struct bnx2x *bp = params->bp;
8919         /* Need to wait 100ms after reset */
8920         msleep(100);
8921
8922         /* Micro controller re-boot */
8923         bnx2x_cl45_write(bp, phy,
8924                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8925
8926         /* Set soft reset */
8927         bnx2x_cl45_write(bp, phy,
8928                          MDIO_PMA_DEVAD,
8929                          MDIO_PMA_REG_GEN_CTRL,
8930                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8931
8932         bnx2x_cl45_write(bp, phy,
8933                          MDIO_PMA_DEVAD,
8934                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8935
8936         bnx2x_cl45_write(bp, phy,
8937                          MDIO_PMA_DEVAD,
8938                          MDIO_PMA_REG_GEN_CTRL,
8939                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8940
8941         /* Wait for 150ms for microcode load */
8942         msleep(150);
8943
8944         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8945         bnx2x_cl45_write(bp, phy,
8946                          MDIO_PMA_DEVAD,
8947                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8948
8949         msleep(200);
8950         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8951 }
8952
8953 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8954                                  struct link_params *params,
8955                                  struct link_vars *vars)
8956 {
8957         struct bnx2x *bp = params->bp;
8958         u16 val1;
8959         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8960         if (link_up) {
8961                 bnx2x_cl45_read(bp, phy,
8962                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8963                                 &val1);
8964                 if (val1 & (1<<15)) {
8965                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8966                         link_up = 0;
8967                         vars->line_speed = 0;
8968                 }
8969         }
8970         return link_up;
8971 }
8972
8973
8974 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8975                                   struct link_params *params,
8976                                   struct link_vars *vars)
8977 {
8978         struct bnx2x *bp = params->bp;
8979         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8980
8981         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8982         bnx2x_wait_reset_complete(bp, phy, params);
8983
8984         bnx2x_8726_external_rom_boot(phy, params);
8985
8986         /* Need to call module detected on initialization since the module
8987          * detection triggered by actual module insertion might occur before
8988          * driver is loaded, and when driver is loaded, it reset all
8989          * registers, including the transmitter
8990          */
8991         bnx2x_sfp_module_detection(phy, params);
8992
8993         if (phy->req_line_speed == SPEED_1000) {
8994                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8995                 bnx2x_cl45_write(bp, phy,
8996                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8997                 bnx2x_cl45_write(bp, phy,
8998                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8999                 bnx2x_cl45_write(bp, phy,
9000                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9001                 bnx2x_cl45_write(bp, phy,
9002                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9003                                  0x400);
9004         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9005                    (phy->speed_cap_mask &
9006                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9007                    ((phy->speed_cap_mask &
9008                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9009                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9010                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9011                 /* Set Flow control */
9012                 bnx2x_ext_phy_set_pause(params, phy, vars);
9013                 bnx2x_cl45_write(bp, phy,
9014                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9015                 bnx2x_cl45_write(bp, phy,
9016                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9017                 bnx2x_cl45_write(bp, phy,
9018                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9019                 bnx2x_cl45_write(bp, phy,
9020                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9021                 bnx2x_cl45_write(bp, phy,
9022                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9023                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9024                  * change
9025                  */
9026                 bnx2x_cl45_write(bp, phy,
9027                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9028                 bnx2x_cl45_write(bp, phy,
9029                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9030                                  0x400);
9031
9032         } else { /* Default 10G. Set only LASI control */
9033                 bnx2x_cl45_write(bp, phy,
9034                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9035         }
9036
9037         /* Set TX PreEmphasis if needed */
9038         if ((params->feature_config_flags &
9039              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9040                 DP(NETIF_MSG_LINK,
9041                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9042                          phy->tx_preemphasis[0],
9043                          phy->tx_preemphasis[1]);
9044                 bnx2x_cl45_write(bp, phy,
9045                                  MDIO_PMA_DEVAD,
9046                                  MDIO_PMA_REG_8726_TX_CTRL1,
9047                                  phy->tx_preemphasis[0]);
9048
9049                 bnx2x_cl45_write(bp, phy,
9050                                  MDIO_PMA_DEVAD,
9051                                  MDIO_PMA_REG_8726_TX_CTRL2,
9052                                  phy->tx_preemphasis[1]);
9053         }
9054
9055         return 0;
9056
9057 }
9058
9059 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9060                                   struct link_params *params)
9061 {
9062         struct bnx2x *bp = params->bp;
9063         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9064         /* Set serial boot control for external load */
9065         bnx2x_cl45_write(bp, phy,
9066                          MDIO_PMA_DEVAD,
9067                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9068 }
9069
9070 /******************************************************************/
9071 /*                      BCM8727 PHY SECTION                       */
9072 /******************************************************************/
9073
9074 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9075                                     struct link_params *params, u8 mode)
9076 {
9077         struct bnx2x *bp = params->bp;
9078         u16 led_mode_bitmask = 0;
9079         u16 gpio_pins_bitmask = 0;
9080         u16 val;
9081         /* Only NOC flavor requires to set the LED specifically */
9082         if (!(phy->flags & FLAGS_NOC))
9083                 return;
9084         switch (mode) {
9085         case LED_MODE_FRONT_PANEL_OFF:
9086         case LED_MODE_OFF:
9087                 led_mode_bitmask = 0;
9088                 gpio_pins_bitmask = 0x03;
9089                 break;
9090         case LED_MODE_ON:
9091                 led_mode_bitmask = 0;
9092                 gpio_pins_bitmask = 0x02;
9093                 break;
9094         case LED_MODE_OPER:
9095                 led_mode_bitmask = 0x60;
9096                 gpio_pins_bitmask = 0x11;
9097                 break;
9098         }
9099         bnx2x_cl45_read(bp, phy,
9100                         MDIO_PMA_DEVAD,
9101                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9102                         &val);
9103         val &= 0xff8f;
9104         val |= led_mode_bitmask;
9105         bnx2x_cl45_write(bp, phy,
9106                          MDIO_PMA_DEVAD,
9107                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9108                          val);
9109         bnx2x_cl45_read(bp, phy,
9110                         MDIO_PMA_DEVAD,
9111                         MDIO_PMA_REG_8727_GPIO_CTRL,
9112                         &val);
9113         val &= 0xffe0;
9114         val |= gpio_pins_bitmask;
9115         bnx2x_cl45_write(bp, phy,
9116                          MDIO_PMA_DEVAD,
9117                          MDIO_PMA_REG_8727_GPIO_CTRL,
9118                          val);
9119 }
9120 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9121                                 struct link_params *params) {
9122         u32 swap_val, swap_override;
9123         u8 port;
9124         /* The PHY reset is controlled by GPIO 1. Fake the port number
9125          * to cancel the swap done in set_gpio()
9126          */
9127         struct bnx2x *bp = params->bp;
9128         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9129         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9130         port = (swap_val && swap_override) ^ 1;
9131         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9132                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9133 }
9134
9135 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9136                                     struct link_params *params)
9137 {
9138         struct bnx2x *bp = params->bp;
9139         u16 tmp1, val;
9140         /* Set option 1G speed */
9141         if ((phy->req_line_speed == SPEED_1000) ||
9142             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9143                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9144                 bnx2x_cl45_write(bp, phy,
9145                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9146                 bnx2x_cl45_write(bp, phy,
9147                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9148                 bnx2x_cl45_read(bp, phy,
9149                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9150                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9151                 /* Power down the XAUI until link is up in case of dual-media
9152                  * and 1G
9153                  */
9154                 if (DUAL_MEDIA(params)) {
9155                         bnx2x_cl45_read(bp, phy,
9156                                         MDIO_PMA_DEVAD,
9157                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9158                         val |= (3<<10);
9159                         bnx2x_cl45_write(bp, phy,
9160                                          MDIO_PMA_DEVAD,
9161                                          MDIO_PMA_REG_8727_PCS_GP, val);
9162                 }
9163         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9164                    ((phy->speed_cap_mask &
9165                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9166                    ((phy->speed_cap_mask &
9167                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9168                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9169
9170                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9171                 bnx2x_cl45_write(bp, phy,
9172                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9173                 bnx2x_cl45_write(bp, phy,
9174                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9175         } else {
9176                 /* Since the 8727 has only single reset pin, need to set the 10G
9177                  * registers although it is default
9178                  */
9179                 bnx2x_cl45_write(bp, phy,
9180                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9181                                  0x0020);
9182                 bnx2x_cl45_write(bp, phy,
9183                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9184                 bnx2x_cl45_write(bp, phy,
9185                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9186                 bnx2x_cl45_write(bp, phy,
9187                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9188                                  0x0008);
9189         }
9190 }
9191
9192 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9193                                   struct link_params *params,
9194                                   struct link_vars *vars)
9195 {
9196         u32 tx_en_mode;
9197         u16 tmp1, mod_abs, tmp2;
9198         struct bnx2x *bp = params->bp;
9199         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9200
9201         bnx2x_wait_reset_complete(bp, phy, params);
9202
9203         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9204
9205         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9206         /* Initially configure MOD_ABS to interrupt when module is
9207          * presence( bit 8)
9208          */
9209         bnx2x_cl45_read(bp, phy,
9210                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9211         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9212          * When the EDC is off it locks onto a reference clock and avoids
9213          * becoming 'lost'
9214          */
9215         mod_abs &= ~(1<<8);
9216         if (!(phy->flags & FLAGS_NOC))
9217                 mod_abs &= ~(1<<9);
9218         bnx2x_cl45_write(bp, phy,
9219                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9220
9221         /* Enable/Disable PHY transmitter output */
9222         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9223
9224         bnx2x_8727_power_module(bp, phy, 1);
9225
9226         bnx2x_cl45_read(bp, phy,
9227                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9228
9229         bnx2x_cl45_read(bp, phy,
9230                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9231
9232         bnx2x_8727_config_speed(phy, params);
9233
9234
9235         /* Set TX PreEmphasis if needed */
9236         if ((params->feature_config_flags &
9237              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9238                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9239                            phy->tx_preemphasis[0],
9240                            phy->tx_preemphasis[1]);
9241                 bnx2x_cl45_write(bp, phy,
9242                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9243                                  phy->tx_preemphasis[0]);
9244
9245                 bnx2x_cl45_write(bp, phy,
9246                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9247                                  phy->tx_preemphasis[1]);
9248         }
9249
9250         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9251          * power mode, if TX Laser is disabled
9252          */
9253         tx_en_mode = REG_RD(bp, params->shmem_base +
9254                             offsetof(struct shmem_region,
9255                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9256                         & PORT_HW_CFG_TX_LASER_MASK;
9257
9258         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9259
9260                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9261                 bnx2x_cl45_read(bp, phy,
9262                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9263                 tmp2 |= 0x1000;
9264                 tmp2 &= 0xFFEF;
9265                 bnx2x_cl45_write(bp, phy,
9266                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9267                 bnx2x_cl45_read(bp, phy,
9268                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9269                                 &tmp2);
9270                 bnx2x_cl45_write(bp, phy,
9271                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9272                                  (tmp2 & 0x7fff));
9273         }
9274
9275         return 0;
9276 }
9277
9278 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9279                                       struct link_params *params)
9280 {
9281         struct bnx2x *bp = params->bp;
9282         u16 mod_abs, rx_alarm_status;
9283         u32 val = REG_RD(bp, params->shmem_base +
9284                              offsetof(struct shmem_region, dev_info.
9285                                       port_feature_config[params->port].
9286                                       config));
9287         bnx2x_cl45_read(bp, phy,
9288                         MDIO_PMA_DEVAD,
9289                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9290         if (mod_abs & (1<<8)) {
9291
9292                 /* Module is absent */
9293                 DP(NETIF_MSG_LINK,
9294                    "MOD_ABS indication show module is absent\n");
9295                 phy->media_type = ETH_PHY_NOT_PRESENT;
9296                 /* 1. Set mod_abs to detect next module
9297                  *    presence event
9298                  * 2. Set EDC off by setting OPTXLOS signal input to low
9299                  *    (bit 9).
9300                  *    When the EDC is off it locks onto a reference clock and
9301                  *    avoids becoming 'lost'.
9302                  */
9303                 mod_abs &= ~(1<<8);
9304                 if (!(phy->flags & FLAGS_NOC))
9305                         mod_abs &= ~(1<<9);
9306                 bnx2x_cl45_write(bp, phy,
9307                                  MDIO_PMA_DEVAD,
9308                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9309
9310                 /* Clear RX alarm since it stays up as long as
9311                  * the mod_abs wasn't changed
9312                  */
9313                 bnx2x_cl45_read(bp, phy,
9314                                 MDIO_PMA_DEVAD,
9315                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9316
9317         } else {
9318                 /* Module is present */
9319                 DP(NETIF_MSG_LINK,
9320                    "MOD_ABS indication show module is present\n");
9321                 /* First disable transmitter, and if the module is ok, the
9322                  * module_detection will enable it
9323                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9324                  * 2. Restore the default polarity of the OPRXLOS signal and
9325                  * this signal will then correctly indicate the presence or
9326                  * absence of the Rx signal. (bit 9)
9327                  */
9328                 mod_abs |= (1<<8);
9329                 if (!(phy->flags & FLAGS_NOC))
9330                         mod_abs |= (1<<9);
9331                 bnx2x_cl45_write(bp, phy,
9332                                  MDIO_PMA_DEVAD,
9333                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9334
9335                 /* Clear RX alarm since it stays up as long as the mod_abs
9336                  * wasn't changed. This is need to be done before calling the
9337                  * module detection, otherwise it will clear* the link update
9338                  * alarm
9339                  */
9340                 bnx2x_cl45_read(bp, phy,
9341                                 MDIO_PMA_DEVAD,
9342                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9343
9344
9345                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9346                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9347                         bnx2x_sfp_set_transmitter(params, phy, 0);
9348
9349                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9350                         bnx2x_sfp_module_detection(phy, params);
9351                 else
9352                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9353
9354                 /* Reconfigure link speed based on module type limitations */
9355                 bnx2x_8727_config_speed(phy, params);
9356         }
9357
9358         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9359                    rx_alarm_status);
9360         /* No need to check link status in case of module plugged in/out */
9361 }
9362
9363 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9364                                  struct link_params *params,
9365                                  struct link_vars *vars)
9366
9367 {
9368         struct bnx2x *bp = params->bp;
9369         u8 link_up = 0, oc_port = params->port;
9370         u16 link_status = 0;
9371         u16 rx_alarm_status, lasi_ctrl, val1;
9372
9373         /* If PHY is not initialized, do not check link status */
9374         bnx2x_cl45_read(bp, phy,
9375                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9376                         &lasi_ctrl);
9377         if (!lasi_ctrl)
9378                 return 0;
9379
9380         /* Check the LASI on Rx */
9381         bnx2x_cl45_read(bp, phy,
9382                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9383                         &rx_alarm_status);
9384         vars->line_speed = 0;
9385         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9386
9387         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9388                              MDIO_PMA_LASI_TXCTRL);
9389
9390         bnx2x_cl45_read(bp, phy,
9391                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9392
9393         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9394
9395         /* Clear MSG-OUT */
9396         bnx2x_cl45_read(bp, phy,
9397                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9398
9399         /* If a module is present and there is need to check
9400          * for over current
9401          */
9402         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9403                 /* Check over-current using 8727 GPIO0 input*/
9404                 bnx2x_cl45_read(bp, phy,
9405                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9406                                 &val1);
9407
9408                 if ((val1 & (1<<8)) == 0) {
9409                         if (!CHIP_IS_E1x(bp))
9410                                 oc_port = BP_PATH(bp) + (params->port << 1);
9411                         DP(NETIF_MSG_LINK,
9412                            "8727 Power fault has been detected on port %d\n",
9413                            oc_port);
9414                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9415                                             "been detected and the power to "
9416                                             "that SFP+ module has been removed "
9417                                             "to prevent failure of the card. "
9418                                             "Please remove the SFP+ module and "
9419                                             "restart the system to clear this "
9420                                             "error.\n",
9421                          oc_port);
9422                         /* Disable all RX_ALARMs except for mod_abs */
9423                         bnx2x_cl45_write(bp, phy,
9424                                          MDIO_PMA_DEVAD,
9425                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9426
9427                         bnx2x_cl45_read(bp, phy,
9428                                         MDIO_PMA_DEVAD,
9429                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9430                         /* Wait for module_absent_event */
9431                         val1 |= (1<<8);
9432                         bnx2x_cl45_write(bp, phy,
9433                                          MDIO_PMA_DEVAD,
9434                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9435                         /* Clear RX alarm */
9436                         bnx2x_cl45_read(bp, phy,
9437                                 MDIO_PMA_DEVAD,
9438                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9439                         bnx2x_8727_power_module(params->bp, phy, 0);
9440                         return 0;
9441                 }
9442         } /* Over current check */
9443
9444         /* When module absent bit is set, check module */
9445         if (rx_alarm_status & (1<<5)) {
9446                 bnx2x_8727_handle_mod_abs(phy, params);
9447                 /* Enable all mod_abs and link detection bits */
9448                 bnx2x_cl45_write(bp, phy,
9449                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9450                                  ((1<<5) | (1<<2)));
9451         }
9452
9453         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9454                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9455                 bnx2x_sfp_set_transmitter(params, phy, 1);
9456         } else {
9457                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9458                 return 0;
9459         }
9460
9461         bnx2x_cl45_read(bp, phy,
9462                         MDIO_PMA_DEVAD,
9463                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9464
9465         /* Bits 0..2 --> speed detected,
9466          * Bits 13..15--> link is down
9467          */
9468         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9469                 link_up = 1;
9470                 vars->line_speed = SPEED_10000;
9471                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9472                            params->port);
9473         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9474                 link_up = 1;
9475                 vars->line_speed = SPEED_1000;
9476                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9477                            params->port);
9478         } else {
9479                 link_up = 0;
9480                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9481                            params->port);
9482         }
9483
9484         /* Capture 10G link fault. */
9485         if (vars->line_speed == SPEED_10000) {
9486                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9487                             MDIO_PMA_LASI_TXSTAT, &val1);
9488
9489                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9490                             MDIO_PMA_LASI_TXSTAT, &val1);
9491
9492                 if (val1 & (1<<0)) {
9493                         vars->fault_detected = 1;
9494                 }
9495         }
9496
9497         if (link_up) {
9498                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9499                 vars->duplex = DUPLEX_FULL;
9500                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9501         }
9502
9503         if ((DUAL_MEDIA(params)) &&
9504             (phy->req_line_speed == SPEED_1000)) {
9505                 bnx2x_cl45_read(bp, phy,
9506                                 MDIO_PMA_DEVAD,
9507                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9508                 /* In case of dual-media board and 1G, power up the XAUI side,
9509                  * otherwise power it down. For 10G it is done automatically
9510                  */
9511                 if (link_up)
9512                         val1 &= ~(3<<10);
9513                 else
9514                         val1 |= (3<<10);
9515                 bnx2x_cl45_write(bp, phy,
9516                                  MDIO_PMA_DEVAD,
9517                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9518         }
9519         return link_up;
9520 }
9521
9522 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9523                                   struct link_params *params)
9524 {
9525         struct bnx2x *bp = params->bp;
9526
9527         /* Enable/Disable PHY transmitter output */
9528         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9529
9530         /* Disable Transmitter */
9531         bnx2x_sfp_set_transmitter(params, phy, 0);
9532         /* Clear LASI */
9533         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9534
9535 }
9536
9537 /******************************************************************/
9538 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9539 /******************************************************************/
9540 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9541                                             struct bnx2x *bp,
9542                                             u8 port)
9543 {
9544         u16 val, fw_ver2, cnt, i;
9545         static struct bnx2x_reg_set reg_set[] = {
9546                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9547                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9548                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9549                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9550                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9551         };
9552         u16 fw_ver1;
9553
9554         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9555             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9556                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9557                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9558                                 phy->ver_addr);
9559         } else {
9560                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9561                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9562                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9563                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9564                                          reg_set[i].reg, reg_set[i].val);
9565
9566                 for (cnt = 0; cnt < 100; cnt++) {
9567                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9568                         if (val & 1)
9569                                 break;
9570                         udelay(5);
9571                 }
9572                 if (cnt == 100) {
9573                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9574                                         "phy fw version(1)\n");
9575                         bnx2x_save_spirom_version(bp, port, 0,
9576                                                   phy->ver_addr);
9577                         return;
9578                 }
9579
9580
9581                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9582                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9583                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9584                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9585                 for (cnt = 0; cnt < 100; cnt++) {
9586                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9587                         if (val & 1)
9588                                 break;
9589                         udelay(5);
9590                 }
9591                 if (cnt == 100) {
9592                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9593                                         "version(2)\n");
9594                         bnx2x_save_spirom_version(bp, port, 0,
9595                                                   phy->ver_addr);
9596                         return;
9597                 }
9598
9599                 /* lower 16 bits of the register SPI_FW_STATUS */
9600                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9601                 /* upper 16 bits of register SPI_FW_STATUS */
9602                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9603
9604                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9605                                           phy->ver_addr);
9606         }
9607
9608 }
9609 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9610                                 struct bnx2x_phy *phy)
9611 {
9612         u16 val, offset, i;
9613         static struct bnx2x_reg_set reg_set[] = {
9614                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9615                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9616                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9617                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9618                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9619                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9620                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9621         };
9622         /* PHYC_CTL_LED_CTL */
9623         bnx2x_cl45_read(bp, phy,
9624                         MDIO_PMA_DEVAD,
9625                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9626         val &= 0xFE00;
9627         val |= 0x0092;
9628
9629         bnx2x_cl45_write(bp, phy,
9630                          MDIO_PMA_DEVAD,
9631                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9632
9633         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9634                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9635                                  reg_set[i].val);
9636
9637         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9638             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9639                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9640         else
9641                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9642
9643         /* stretch_en for LED3*/
9644         bnx2x_cl45_read_or_write(bp, phy,
9645                                  MDIO_PMA_DEVAD, offset,
9646                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9647 }
9648
9649 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9650                                       struct link_params *params,
9651                                       u32 action)
9652 {
9653         struct bnx2x *bp = params->bp;
9654         switch (action) {
9655         case PHY_INIT:
9656                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9657                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9658                         /* Save spirom version */
9659                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9660                 }
9661                 /* This phy uses the NIG latch mechanism since link indication
9662                  * arrives through its LED4 and not via its LASI signal, so we
9663                  * get steady signal instead of clear on read
9664                  */
9665                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9666                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9667
9668                 bnx2x_848xx_set_led(bp, phy);
9669                 break;
9670         }
9671 }
9672
9673 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9674                                        struct link_params *params,
9675                                        struct link_vars *vars)
9676 {
9677         struct bnx2x *bp = params->bp;
9678         u16 autoneg_val, an_1000_val, an_10_100_val;
9679
9680         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9681         bnx2x_cl45_write(bp, phy,
9682                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9683
9684         /* set 1000 speed advertisement */
9685         bnx2x_cl45_read(bp, phy,
9686                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9687                         &an_1000_val);
9688
9689         bnx2x_ext_phy_set_pause(params, phy, vars);
9690         bnx2x_cl45_read(bp, phy,
9691                         MDIO_AN_DEVAD,
9692                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9693                         &an_10_100_val);
9694         bnx2x_cl45_read(bp, phy,
9695                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9696                         &autoneg_val);
9697         /* Disable forced speed */
9698         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9699         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9700
9701         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9702              (phy->speed_cap_mask &
9703              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9704             (phy->req_line_speed == SPEED_1000)) {
9705                 an_1000_val |= (1<<8);
9706                 autoneg_val |= (1<<9 | 1<<12);
9707                 if (phy->req_duplex == DUPLEX_FULL)
9708                         an_1000_val |= (1<<9);
9709                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9710         } else
9711                 an_1000_val &= ~((1<<8) | (1<<9));
9712
9713         bnx2x_cl45_write(bp, phy,
9714                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9715                          an_1000_val);
9716
9717         /* set 100 speed advertisement */
9718         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9719              (phy->speed_cap_mask &
9720               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9721                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9722                 an_10_100_val |= (1<<7);
9723                 /* Enable autoneg and restart autoneg for legacy speeds */
9724                 autoneg_val |= (1<<9 | 1<<12);
9725
9726                 if (phy->req_duplex == DUPLEX_FULL)
9727                         an_10_100_val |= (1<<8);
9728                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9729         }
9730         /* set 10 speed advertisement */
9731         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9732              (phy->speed_cap_mask &
9733               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9734                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9735              (phy->supported &
9736               (SUPPORTED_10baseT_Half |
9737                SUPPORTED_10baseT_Full)))) {
9738                 an_10_100_val |= (1<<5);
9739                 autoneg_val |= (1<<9 | 1<<12);
9740                 if (phy->req_duplex == DUPLEX_FULL)
9741                         an_10_100_val |= (1<<6);
9742                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9743         }
9744
9745         /* Only 10/100 are allowed to work in FORCE mode */
9746         if ((phy->req_line_speed == SPEED_100) &&
9747             (phy->supported &
9748              (SUPPORTED_100baseT_Half |
9749               SUPPORTED_100baseT_Full))) {
9750                 autoneg_val |= (1<<13);
9751                 /* Enabled AUTO-MDIX when autoneg is disabled */
9752                 bnx2x_cl45_write(bp, phy,
9753                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9754                                  (1<<15 | 1<<9 | 7<<0));
9755                 /* The PHY needs this set even for forced link. */
9756                 an_10_100_val |= (1<<8) | (1<<7);
9757                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9758         }
9759         if ((phy->req_line_speed == SPEED_10) &&
9760             (phy->supported &
9761              (SUPPORTED_10baseT_Half |
9762               SUPPORTED_10baseT_Full))) {
9763                 /* Enabled AUTO-MDIX when autoneg is disabled */
9764                 bnx2x_cl45_write(bp, phy,
9765                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9766                                  (1<<15 | 1<<9 | 7<<0));
9767                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9768         }
9769
9770         bnx2x_cl45_write(bp, phy,
9771                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9772                          an_10_100_val);
9773
9774         if (phy->req_duplex == DUPLEX_FULL)
9775                 autoneg_val |= (1<<8);
9776
9777         /* Always write this if this is not 84833/4.
9778          * For 84833/4, write it only when it's a forced speed.
9779          */
9780         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9781              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9782             ((autoneg_val & (1<<12)) == 0))
9783                 bnx2x_cl45_write(bp, phy,
9784                          MDIO_AN_DEVAD,
9785                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9786
9787         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9788             (phy->speed_cap_mask &
9789              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9790                 (phy->req_line_speed == SPEED_10000)) {
9791                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9792                         /* Restart autoneg for 10G*/
9793
9794                         bnx2x_cl45_read_or_write(
9795                                 bp, phy,
9796                                 MDIO_AN_DEVAD,
9797                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9798                                 0x1000);
9799                         bnx2x_cl45_write(bp, phy,
9800                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9801                                          0x3200);
9802         } else
9803                 bnx2x_cl45_write(bp, phy,
9804                                  MDIO_AN_DEVAD,
9805                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9806                                  1);
9807
9808         return 0;
9809 }
9810
9811 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9812                                   struct link_params *params,
9813                                   struct link_vars *vars)
9814 {
9815         struct bnx2x *bp = params->bp;
9816         /* Restore normal power mode*/
9817         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9818                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9819
9820         /* HW reset */
9821         bnx2x_ext_phy_hw_reset(bp, params->port);
9822         bnx2x_wait_reset_complete(bp, phy, params);
9823
9824         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9825         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9826 }
9827
9828 #define PHY84833_CMDHDLR_WAIT 300
9829 #define PHY84833_CMDHDLR_MAX_ARGS 5
9830 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9831                                 struct link_params *params, u16 fw_cmd,
9832                                 u16 cmd_args[], int argc)
9833 {
9834         int idx;
9835         u16 val;
9836         struct bnx2x *bp = params->bp;
9837         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9838         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9839                         MDIO_84833_CMD_HDLR_STATUS,
9840                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9841         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9842                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9843                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9844                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9845                         break;
9846                 usleep_range(1000, 2000);
9847         }
9848         if (idx >= PHY84833_CMDHDLR_WAIT) {
9849                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9850                 return -EINVAL;
9851         }
9852
9853         /* Prepare argument(s) and issue command */
9854         for (idx = 0; idx < argc; idx++) {
9855                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9856                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9857                                 cmd_args[idx]);
9858         }
9859         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9860                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9861         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9862                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9863                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9864                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9865                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9866                         break;
9867                 usleep_range(1000, 2000);
9868         }
9869         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9870                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9871                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9872                 return -EINVAL;
9873         }
9874         /* Gather returning data */
9875         for (idx = 0; idx < argc; idx++) {
9876                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9877                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9878                                 &cmd_args[idx]);
9879         }
9880         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9881                         MDIO_84833_CMD_HDLR_STATUS,
9882                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9883         return 0;
9884 }
9885
9886 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9887                                    struct link_params *params,
9888                                    struct link_vars *vars)
9889 {
9890         u32 pair_swap;
9891         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9892         int status;
9893         struct bnx2x *bp = params->bp;
9894
9895         /* Check for configuration. */
9896         pair_swap = REG_RD(bp, params->shmem_base +
9897                            offsetof(struct shmem_region,
9898                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9899                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9900
9901         if (pair_swap == 0)
9902                 return 0;
9903
9904         /* Only the second argument is used for this command */
9905         data[1] = (u16)pair_swap;
9906
9907         status = bnx2x_84833_cmd_hdlr(phy, params,
9908                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9909         if (status == 0)
9910                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9911
9912         return status;
9913 }
9914
9915 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9916                                       u32 shmem_base_path[],
9917                                       u32 chip_id)
9918 {
9919         u32 reset_pin[2];
9920         u32 idx;
9921         u8 reset_gpios;
9922         if (CHIP_IS_E3(bp)) {
9923                 /* Assume that these will be GPIOs, not EPIOs. */
9924                 for (idx = 0; idx < 2; idx++) {
9925                         /* Map config param to register bit. */
9926                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9927                                 offsetof(struct shmem_region,
9928                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9929                         reset_pin[idx] = (reset_pin[idx] &
9930                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9931                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9932                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9933                         reset_pin[idx] = (1 << reset_pin[idx]);
9934                 }
9935                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9936         } else {
9937                 /* E2, look from diff place of shmem. */
9938                 for (idx = 0; idx < 2; idx++) {
9939                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9940                                 offsetof(struct shmem_region,
9941                                 dev_info.port_hw_config[0].default_cfg));
9942                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9943                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9944                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9945                         reset_pin[idx] = (1 << reset_pin[idx]);
9946                 }
9947                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9948         }
9949
9950         return reset_gpios;
9951 }
9952
9953 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9954                                 struct link_params *params)
9955 {
9956         struct bnx2x *bp = params->bp;
9957         u8 reset_gpios;
9958         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9959                                 offsetof(struct shmem2_region,
9960                                 other_shmem_base_addr));
9961
9962         u32 shmem_base_path[2];
9963
9964         /* Work around for 84833 LED failure inside RESET status */
9965         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9966                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9967                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9968         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9969                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9970                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9971
9972         shmem_base_path[0] = params->shmem_base;
9973         shmem_base_path[1] = other_shmem_base_addr;
9974
9975         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9976                                                   params->chip_id);
9977
9978         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9979         udelay(10);
9980         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9981                 reset_gpios);
9982
9983         return 0;
9984 }
9985
9986 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9987                                    struct link_params *params,
9988                                    struct link_vars *vars)
9989 {
9990         int rc;
9991         struct bnx2x *bp = params->bp;
9992         u16 cmd_args = 0;
9993
9994         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
9995
9996         /* Prevent Phy from working in EEE and advertising it */
9997         rc = bnx2x_84833_cmd_hdlr(phy, params,
9998                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9999         if (rc) {
10000                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10001                 return rc;
10002         }
10003
10004         return bnx2x_eee_disable(phy, params, vars);
10005 }
10006
10007 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10008                                    struct link_params *params,
10009                                    struct link_vars *vars)
10010 {
10011         int rc;
10012         struct bnx2x *bp = params->bp;
10013         u16 cmd_args = 1;
10014
10015         rc = bnx2x_84833_cmd_hdlr(phy, params,
10016                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10017         if (rc) {
10018                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10019                 return rc;
10020         }
10021
10022         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10023 }
10024
10025 #define PHY84833_CONSTANT_LATENCY 1193
10026 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10027                                    struct link_params *params,
10028                                    struct link_vars *vars)
10029 {
10030         struct bnx2x *bp = params->bp;
10031         u8 port, initialize = 1;
10032         u16 val;
10033         u32 actual_phy_selection;
10034         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10035         int rc = 0;
10036
10037         usleep_range(1000, 2000);
10038
10039         if (!(CHIP_IS_E1x(bp)))
10040                 port = BP_PATH(bp);
10041         else
10042                 port = params->port;
10043
10044         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10045                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10046                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10047                                port);
10048         } else {
10049                 /* MDIO reset */
10050                 bnx2x_cl45_write(bp, phy,
10051                                 MDIO_PMA_DEVAD,
10052                                 MDIO_PMA_REG_CTRL, 0x8000);
10053         }
10054
10055         bnx2x_wait_reset_complete(bp, phy, params);
10056
10057         /* Wait for GPHY to come out of reset */
10058         msleep(50);
10059         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10060             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10061                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10062                  * behavior.
10063                  */
10064                 u16 temp;
10065                 temp = vars->line_speed;
10066                 vars->line_speed = SPEED_10000;
10067                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10068                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10069                 vars->line_speed = temp;
10070         }
10071
10072         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10073                         MDIO_CTL_REG_84823_MEDIA, &val);
10074         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10075                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10076                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10077                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10078                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10079
10080         if (CHIP_IS_E3(bp)) {
10081                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10082                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10083         } else {
10084                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10085                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10086         }
10087
10088         actual_phy_selection = bnx2x_phy_selection(params);
10089
10090         switch (actual_phy_selection) {
10091         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10092                 /* Do nothing. Essentially this is like the priority copper */
10093                 break;
10094         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10095                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10096                 break;
10097         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10098                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10099                 break;
10100         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10101                 /* Do nothing here. The first PHY won't be initialized at all */
10102                 break;
10103         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10104                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10105                 initialize = 0;
10106                 break;
10107         }
10108         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10109                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10110
10111         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10112                          MDIO_CTL_REG_84823_MEDIA, val);
10113         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10114                    params->multi_phy_config, val);
10115
10116         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10117             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10118                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10119
10120                 /* Keep AutogrEEEn disabled. */
10121                 cmd_args[0] = 0x0;
10122                 cmd_args[1] = 0x0;
10123                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10124                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10125                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10126                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10127                         PHY84833_CMDHDLR_MAX_ARGS);
10128                 if (rc)
10129                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10130         }
10131         if (initialize)
10132                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10133         else
10134                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10135         /* 84833 PHY has a better feature and doesn't need to support this. */
10136         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10137                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10138                         offsetof(struct shmem_region,
10139                         dev_info.port_hw_config[params->port].default_cfg)) &
10140                         PORT_HW_CFG_ENABLE_CMS_MASK;
10141
10142                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10143                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10144                 if (cms_enable)
10145                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10146                 else
10147                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10148                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10149                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10150         }
10151
10152         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10153                         MDIO_84833_TOP_CFG_FW_REV, &val);
10154
10155         /* Configure EEE support */
10156         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10157             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10158             bnx2x_eee_has_cap(params)) {
10159                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10160                 if (rc) {
10161                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10162                         bnx2x_8483x_disable_eee(phy, params, vars);
10163                         return rc;
10164                 }
10165
10166                 if ((phy->req_duplex == DUPLEX_FULL) &&
10167                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10168                     (bnx2x_eee_calc_timer(params) ||
10169                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10170                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10171                 else
10172                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10173                 if (rc) {
10174                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10175                         return rc;
10176                 }
10177         } else {
10178                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10179         }
10180
10181         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10182             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10183                 /* Bring PHY out of super isolate mode as the final step. */
10184                 bnx2x_cl45_read_and_write(bp, phy,
10185                                           MDIO_CTL_DEVAD,
10186                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10187                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10188         }
10189         return rc;
10190 }
10191
10192 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10193                                   struct link_params *params,
10194                                   struct link_vars *vars)
10195 {
10196         struct bnx2x *bp = params->bp;
10197         u16 val, val1, val2;
10198         u8 link_up = 0;
10199
10200
10201         /* Check 10G-BaseT link status */
10202         /* Check PMD signal ok */
10203         bnx2x_cl45_read(bp, phy,
10204                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10205         bnx2x_cl45_read(bp, phy,
10206                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10207                         &val2);
10208         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10209
10210         /* Check link 10G */
10211         if (val2 & (1<<11)) {
10212                 vars->line_speed = SPEED_10000;
10213                 vars->duplex = DUPLEX_FULL;
10214                 link_up = 1;
10215                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10216         } else { /* Check Legacy speed link */
10217                 u16 legacy_status, legacy_speed;
10218
10219                 /* Enable expansion register 0x42 (Operation mode status) */
10220                 bnx2x_cl45_write(bp, phy,
10221                                  MDIO_AN_DEVAD,
10222                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10223
10224                 /* Get legacy speed operation status */
10225                 bnx2x_cl45_read(bp, phy,
10226                                 MDIO_AN_DEVAD,
10227                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10228                                 &legacy_status);
10229
10230                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10231                    legacy_status);
10232                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10233                 legacy_speed = (legacy_status & (3<<9));
10234                 if (legacy_speed == (0<<9))
10235                         vars->line_speed = SPEED_10;
10236                 else if (legacy_speed == (1<<9))
10237                         vars->line_speed = SPEED_100;
10238                 else if (legacy_speed == (2<<9))
10239                         vars->line_speed = SPEED_1000;
10240                 else { /* Should not happen: Treat as link down */
10241                         vars->line_speed = 0;
10242                         link_up = 0;
10243                 }
10244
10245                 if (link_up) {
10246                         if (legacy_status & (1<<8))
10247                                 vars->duplex = DUPLEX_FULL;
10248                         else
10249                                 vars->duplex = DUPLEX_HALF;
10250
10251                         DP(NETIF_MSG_LINK,
10252                            "Link is up in %dMbps, is_duplex_full= %d\n",
10253                            vars->line_speed,
10254                            (vars->duplex == DUPLEX_FULL));
10255                         /* Check legacy speed AN resolution */
10256                         bnx2x_cl45_read(bp, phy,
10257                                         MDIO_AN_DEVAD,
10258                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10259                                         &val);
10260                         if (val & (1<<5))
10261                                 vars->link_status |=
10262                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10263                         bnx2x_cl45_read(bp, phy,
10264                                         MDIO_AN_DEVAD,
10265                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10266                                         &val);
10267                         if ((val & (1<<0)) == 0)
10268                                 vars->link_status |=
10269                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10270                 }
10271         }
10272         if (link_up) {
10273                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10274                            vars->line_speed);
10275                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10276
10277                 /* Read LP advertised speeds */
10278                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10279                                 MDIO_AN_REG_CL37_FC_LP, &val);
10280                 if (val & (1<<5))
10281                         vars->link_status |=
10282                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10283                 if (val & (1<<6))
10284                         vars->link_status |=
10285                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10286                 if (val & (1<<7))
10287                         vars->link_status |=
10288                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10289                 if (val & (1<<8))
10290                         vars->link_status |=
10291                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10292                 if (val & (1<<9))
10293                         vars->link_status |=
10294                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10295
10296                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10297                                 MDIO_AN_REG_1000T_STATUS, &val);
10298
10299                 if (val & (1<<10))
10300                         vars->link_status |=
10301                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10302                 if (val & (1<<11))
10303                         vars->link_status |=
10304                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10305
10306                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10307                                 MDIO_AN_REG_MASTER_STATUS, &val);
10308
10309                 if (val & (1<<11))
10310                         vars->link_status |=
10311                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10312
10313                 /* Determine if EEE was negotiated */
10314                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10315                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10316                         bnx2x_eee_an_resolve(phy, params, vars);
10317         }
10318
10319         return link_up;
10320 }
10321
10322 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10323 {
10324         int status = 0;
10325         u32 spirom_ver;
10326         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10327         status = bnx2x_format_ver(spirom_ver, str, len);
10328         return status;
10329 }
10330
10331 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10332                                 struct link_params *params)
10333 {
10334         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10335                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10336         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10337                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10338 }
10339
10340 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10341                                         struct link_params *params)
10342 {
10343         bnx2x_cl45_write(params->bp, phy,
10344                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10345         bnx2x_cl45_write(params->bp, phy,
10346                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10347 }
10348
10349 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10350                                    struct link_params *params)
10351 {
10352         struct bnx2x *bp = params->bp;
10353         u8 port;
10354         u16 val16;
10355
10356         if (!(CHIP_IS_E1x(bp)))
10357                 port = BP_PATH(bp);
10358         else
10359                 port = params->port;
10360
10361         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10362                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10363                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10364                                port);
10365         } else {
10366                 bnx2x_cl45_read(bp, phy,
10367                                 MDIO_CTL_DEVAD,
10368                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10369                 val16 |= MDIO_84833_SUPER_ISOLATE;
10370                 bnx2x_cl45_write(bp, phy,
10371                                  MDIO_CTL_DEVAD,
10372                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10373         }
10374 }
10375
10376 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10377                                      struct link_params *params, u8 mode)
10378 {
10379         struct bnx2x *bp = params->bp;
10380         u16 val;
10381         u8 port;
10382
10383         if (!(CHIP_IS_E1x(bp)))
10384                 port = BP_PATH(bp);
10385         else
10386                 port = params->port;
10387
10388         switch (mode) {
10389         case LED_MODE_OFF:
10390
10391                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10392
10393                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10394                     SHARED_HW_CFG_LED_EXTPHY1) {
10395
10396                         /* Set LED masks */
10397                         bnx2x_cl45_write(bp, phy,
10398                                         MDIO_PMA_DEVAD,
10399                                         MDIO_PMA_REG_8481_LED1_MASK,
10400                                         0x0);
10401
10402                         bnx2x_cl45_write(bp, phy,
10403                                         MDIO_PMA_DEVAD,
10404                                         MDIO_PMA_REG_8481_LED2_MASK,
10405                                         0x0);
10406
10407                         bnx2x_cl45_write(bp, phy,
10408                                         MDIO_PMA_DEVAD,
10409                                         MDIO_PMA_REG_8481_LED3_MASK,
10410                                         0x0);
10411
10412                         bnx2x_cl45_write(bp, phy,
10413                                         MDIO_PMA_DEVAD,
10414                                         MDIO_PMA_REG_8481_LED5_MASK,
10415                                         0x0);
10416
10417                 } else {
10418                         bnx2x_cl45_write(bp, phy,
10419                                          MDIO_PMA_DEVAD,
10420                                          MDIO_PMA_REG_8481_LED1_MASK,
10421                                          0x0);
10422                 }
10423                 break;
10424         case LED_MODE_FRONT_PANEL_OFF:
10425
10426                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10427                    port);
10428
10429                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10430                     SHARED_HW_CFG_LED_EXTPHY1) {
10431
10432                         /* Set LED masks */
10433                         bnx2x_cl45_write(bp, phy,
10434                                          MDIO_PMA_DEVAD,
10435                                          MDIO_PMA_REG_8481_LED1_MASK,
10436                                          0x0);
10437
10438                         bnx2x_cl45_write(bp, phy,
10439                                          MDIO_PMA_DEVAD,
10440                                          MDIO_PMA_REG_8481_LED2_MASK,
10441                                          0x0);
10442
10443                         bnx2x_cl45_write(bp, phy,
10444                                          MDIO_PMA_DEVAD,
10445                                          MDIO_PMA_REG_8481_LED3_MASK,
10446                                          0x0);
10447
10448                         bnx2x_cl45_write(bp, phy,
10449                                          MDIO_PMA_DEVAD,
10450                                          MDIO_PMA_REG_8481_LED5_MASK,
10451                                          0x20);
10452
10453                 } else {
10454                         bnx2x_cl45_write(bp, phy,
10455                                          MDIO_PMA_DEVAD,
10456                                          MDIO_PMA_REG_8481_LED1_MASK,
10457                                          0x0);
10458                         if (phy->type ==
10459                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10460                                 /* Disable MI_INT interrupt before setting LED4
10461                                  * source to constant off.
10462                                  */
10463                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10464                                            params->port*4) &
10465                                     NIG_MASK_MI_INT) {
10466                                         params->link_flags |=
10467                                         LINK_FLAGS_INT_DISABLED;
10468
10469                                         bnx2x_bits_dis(
10470                                                 bp,
10471                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10472                                                 params->port*4,
10473                                                 NIG_MASK_MI_INT);
10474                                 }
10475                                 bnx2x_cl45_write(bp, phy,
10476                                                  MDIO_PMA_DEVAD,
10477                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10478                                                  0x0);
10479                         }
10480                 }
10481                 break;
10482         case LED_MODE_ON:
10483
10484                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10485
10486                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10487                     SHARED_HW_CFG_LED_EXTPHY1) {
10488                         /* Set control reg */
10489                         bnx2x_cl45_read(bp, phy,
10490                                         MDIO_PMA_DEVAD,
10491                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10492                                         &val);
10493                         val &= 0x8000;
10494                         val |= 0x2492;
10495
10496                         bnx2x_cl45_write(bp, phy,
10497                                          MDIO_PMA_DEVAD,
10498                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10499                                          val);
10500
10501                         /* Set LED masks */
10502                         bnx2x_cl45_write(bp, phy,
10503                                          MDIO_PMA_DEVAD,
10504                                          MDIO_PMA_REG_8481_LED1_MASK,
10505                                          0x0);
10506
10507                         bnx2x_cl45_write(bp, phy,
10508                                          MDIO_PMA_DEVAD,
10509                                          MDIO_PMA_REG_8481_LED2_MASK,
10510                                          0x20);
10511
10512                         bnx2x_cl45_write(bp, phy,
10513                                          MDIO_PMA_DEVAD,
10514                                          MDIO_PMA_REG_8481_LED3_MASK,
10515                                          0x20);
10516
10517                         bnx2x_cl45_write(bp, phy,
10518                                          MDIO_PMA_DEVAD,
10519                                          MDIO_PMA_REG_8481_LED5_MASK,
10520                                          0x0);
10521                 } else {
10522                         bnx2x_cl45_write(bp, phy,
10523                                          MDIO_PMA_DEVAD,
10524                                          MDIO_PMA_REG_8481_LED1_MASK,
10525                                          0x20);
10526                         if (phy->type ==
10527                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10528                                 /* Disable MI_INT interrupt before setting LED4
10529                                  * source to constant on.
10530                                  */
10531                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10532                                            params->port*4) &
10533                                     NIG_MASK_MI_INT) {
10534                                         params->link_flags |=
10535                                         LINK_FLAGS_INT_DISABLED;
10536
10537                                         bnx2x_bits_dis(
10538                                                 bp,
10539                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10540                                                 params->port*4,
10541                                                 NIG_MASK_MI_INT);
10542                                 }
10543                                 bnx2x_cl45_write(bp, phy,
10544                                                  MDIO_PMA_DEVAD,
10545                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10546                                                  0x20);
10547                         }
10548                 }
10549                 break;
10550
10551         case LED_MODE_OPER:
10552
10553                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10554
10555                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10556                     SHARED_HW_CFG_LED_EXTPHY1) {
10557
10558                         /* Set control reg */
10559                         bnx2x_cl45_read(bp, phy,
10560                                         MDIO_PMA_DEVAD,
10561                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10562                                         &val);
10563
10564                         if (!((val &
10565                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10566                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10567                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10568                                 bnx2x_cl45_write(bp, phy,
10569                                                  MDIO_PMA_DEVAD,
10570                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10571                                                  0xa492);
10572                         }
10573
10574                         /* Set LED masks */
10575                         bnx2x_cl45_write(bp, phy,
10576                                          MDIO_PMA_DEVAD,
10577                                          MDIO_PMA_REG_8481_LED1_MASK,
10578                                          0x10);
10579
10580                         bnx2x_cl45_write(bp, phy,
10581                                          MDIO_PMA_DEVAD,
10582                                          MDIO_PMA_REG_8481_LED2_MASK,
10583                                          0x80);
10584
10585                         bnx2x_cl45_write(bp, phy,
10586                                          MDIO_PMA_DEVAD,
10587                                          MDIO_PMA_REG_8481_LED3_MASK,
10588                                          0x98);
10589
10590                         bnx2x_cl45_write(bp, phy,
10591                                          MDIO_PMA_DEVAD,
10592                                          MDIO_PMA_REG_8481_LED5_MASK,
10593                                          0x40);
10594
10595                 } else {
10596                         bnx2x_cl45_write(bp, phy,
10597                                          MDIO_PMA_DEVAD,
10598                                          MDIO_PMA_REG_8481_LED1_MASK,
10599                                          0x80);
10600
10601                         /* Tell LED3 to blink on source */
10602                         bnx2x_cl45_read(bp, phy,
10603                                         MDIO_PMA_DEVAD,
10604                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10605                                         &val);
10606                         val &= ~(7<<6);
10607                         val |= (1<<6); /* A83B[8:6]= 1 */
10608                         bnx2x_cl45_write(bp, phy,
10609                                          MDIO_PMA_DEVAD,
10610                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10611                                          val);
10612                         if (phy->type ==
10613                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10614                                 /* Restore LED4 source to external link,
10615                                  * and re-enable interrupts.
10616                                  */
10617                                 bnx2x_cl45_write(bp, phy,
10618                                                  MDIO_PMA_DEVAD,
10619                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10620                                                  0x40);
10621                                 if (params->link_flags &
10622                                     LINK_FLAGS_INT_DISABLED) {
10623                                         bnx2x_link_int_enable(params);
10624                                         params->link_flags &=
10625                                                 ~LINK_FLAGS_INT_DISABLED;
10626                                 }
10627                         }
10628                 }
10629                 break;
10630         }
10631
10632         /* This is a workaround for E3+84833 until autoneg
10633          * restart is fixed in f/w
10634          */
10635         if (CHIP_IS_E3(bp)) {
10636                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10637                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10638         }
10639 }
10640
10641 /******************************************************************/
10642 /*                      54618SE PHY SECTION                       */
10643 /******************************************************************/
10644 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10645                                         struct link_params *params,
10646                                         u32 action)
10647 {
10648         struct bnx2x *bp = params->bp;
10649         u16 temp;
10650         switch (action) {
10651         case PHY_INIT:
10652                 /* Configure LED4: set to INTR (0x6). */
10653                 /* Accessing shadow register 0xe. */
10654                 bnx2x_cl22_write(bp, phy,
10655                                  MDIO_REG_GPHY_SHADOW,
10656                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10657                 bnx2x_cl22_read(bp, phy,
10658                                 MDIO_REG_GPHY_SHADOW,
10659                                 &temp);
10660                 temp &= ~(0xf << 4);
10661                 temp |= (0x6 << 4);
10662                 bnx2x_cl22_write(bp, phy,
10663                                  MDIO_REG_GPHY_SHADOW,
10664                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10665                 /* Configure INTR based on link status change. */
10666                 bnx2x_cl22_write(bp, phy,
10667                                  MDIO_REG_INTR_MASK,
10668                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10669                 break;
10670         }
10671 }
10672
10673 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10674                                                struct link_params *params,
10675                                                struct link_vars *vars)
10676 {
10677         struct bnx2x *bp = params->bp;
10678         u8 port;
10679         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10680         u32 cfg_pin;
10681
10682         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10683         usleep_range(1000, 2000);
10684
10685         /* This works with E3 only, no need to check the chip
10686          * before determining the port.
10687          */
10688         port = params->port;
10689
10690         cfg_pin = (REG_RD(bp, params->shmem_base +
10691                         offsetof(struct shmem_region,
10692                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10693                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10694                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10695
10696         /* Drive pin high to bring the GPHY out of reset. */
10697         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10698
10699         /* wait for GPHY to reset */
10700         msleep(50);
10701
10702         /* reset phy */
10703         bnx2x_cl22_write(bp, phy,
10704                          MDIO_PMA_REG_CTRL, 0x8000);
10705         bnx2x_wait_reset_complete(bp, phy, params);
10706
10707         /* Wait for GPHY to reset */
10708         msleep(50);
10709
10710
10711         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10712         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10713         bnx2x_cl22_write(bp, phy,
10714                         MDIO_REG_GPHY_SHADOW,
10715                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10716         bnx2x_cl22_read(bp, phy,
10717                         MDIO_REG_GPHY_SHADOW,
10718                         &temp);
10719         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10720         bnx2x_cl22_write(bp, phy,
10721                         MDIO_REG_GPHY_SHADOW,
10722                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10723
10724         /* Set up fc */
10725         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10726         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10727         fc_val = 0;
10728         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10729                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10730                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10731
10732         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10733                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10734                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10735
10736         /* Read all advertisement */
10737         bnx2x_cl22_read(bp, phy,
10738                         0x09,
10739                         &an_1000_val);
10740
10741         bnx2x_cl22_read(bp, phy,
10742                         0x04,
10743                         &an_10_100_val);
10744
10745         bnx2x_cl22_read(bp, phy,
10746                         MDIO_PMA_REG_CTRL,
10747                         &autoneg_val);
10748
10749         /* Disable forced speed */
10750         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10751         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10752                            (1<<11));
10753
10754         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10755                         (phy->speed_cap_mask &
10756                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10757                         (phy->req_line_speed == SPEED_1000)) {
10758                 an_1000_val |= (1<<8);
10759                 autoneg_val |= (1<<9 | 1<<12);
10760                 if (phy->req_duplex == DUPLEX_FULL)
10761                         an_1000_val |= (1<<9);
10762                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10763         } else
10764                 an_1000_val &= ~((1<<8) | (1<<9));
10765
10766         bnx2x_cl22_write(bp, phy,
10767                         0x09,
10768                         an_1000_val);
10769         bnx2x_cl22_read(bp, phy,
10770                         0x09,
10771                         &an_1000_val);
10772
10773         /* Set 100 speed advertisement */
10774         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10775                         (phy->speed_cap_mask &
10776                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10777                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10778                 an_10_100_val |= (1<<7);
10779                 /* Enable autoneg and restart autoneg for legacy speeds */
10780                 autoneg_val |= (1<<9 | 1<<12);
10781
10782                 if (phy->req_duplex == DUPLEX_FULL)
10783                         an_10_100_val |= (1<<8);
10784                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10785         }
10786
10787         /* Set 10 speed advertisement */
10788         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10789                         (phy->speed_cap_mask &
10790                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10791                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10792                 an_10_100_val |= (1<<5);
10793                 autoneg_val |= (1<<9 | 1<<12);
10794                 if (phy->req_duplex == DUPLEX_FULL)
10795                         an_10_100_val |= (1<<6);
10796                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10797         }
10798
10799         /* Only 10/100 are allowed to work in FORCE mode */
10800         if (phy->req_line_speed == SPEED_100) {
10801                 autoneg_val |= (1<<13);
10802                 /* Enabled AUTO-MDIX when autoneg is disabled */
10803                 bnx2x_cl22_write(bp, phy,
10804                                 0x18,
10805                                 (1<<15 | 1<<9 | 7<<0));
10806                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10807         }
10808         if (phy->req_line_speed == SPEED_10) {
10809                 /* Enabled AUTO-MDIX when autoneg is disabled */
10810                 bnx2x_cl22_write(bp, phy,
10811                                 0x18,
10812                                 (1<<15 | 1<<9 | 7<<0));
10813                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10814         }
10815
10816         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10817                 int rc;
10818
10819                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10820                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10821                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10822                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10823                 temp &= 0xfffe;
10824                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10825
10826                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10827                 if (rc) {
10828                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10829                         bnx2x_eee_disable(phy, params, vars);
10830                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10831                            (phy->req_duplex == DUPLEX_FULL) &&
10832                            (bnx2x_eee_calc_timer(params) ||
10833                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10834                         /* Need to advertise EEE only when requested,
10835                          * and either no LPI assertion was requested,
10836                          * or it was requested and a valid timer was set.
10837                          * Also notice full duplex is required for EEE.
10838                          */
10839                         bnx2x_eee_advertise(phy, params, vars,
10840                                             SHMEM_EEE_1G_ADV);
10841                 } else {
10842                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10843                         bnx2x_eee_disable(phy, params, vars);
10844                 }
10845         } else {
10846                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10847                                     SHMEM_EEE_SUPPORTED_SHIFT;
10848
10849                 if (phy->flags & FLAGS_EEE) {
10850                         /* Handle legacy auto-grEEEn */
10851                         if (params->feature_config_flags &
10852                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10853                                 temp = 6;
10854                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10855                         } else {
10856                                 temp = 0;
10857                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10858                         }
10859                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10860                                          MDIO_AN_REG_EEE_ADV, temp);
10861                 }
10862         }
10863
10864         bnx2x_cl22_write(bp, phy,
10865                         0x04,
10866                         an_10_100_val | fc_val);
10867
10868         if (phy->req_duplex == DUPLEX_FULL)
10869                 autoneg_val |= (1<<8);
10870
10871         bnx2x_cl22_write(bp, phy,
10872                         MDIO_PMA_REG_CTRL, autoneg_val);
10873
10874         return 0;
10875 }
10876
10877
10878 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10879                                        struct link_params *params, u8 mode)
10880 {
10881         struct bnx2x *bp = params->bp;
10882         u16 temp;
10883
10884         bnx2x_cl22_write(bp, phy,
10885                 MDIO_REG_GPHY_SHADOW,
10886                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10887         bnx2x_cl22_read(bp, phy,
10888                 MDIO_REG_GPHY_SHADOW,
10889                 &temp);
10890         temp &= 0xff00;
10891
10892         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10893         switch (mode) {
10894         case LED_MODE_FRONT_PANEL_OFF:
10895         case LED_MODE_OFF:
10896                 temp |= 0x00ee;
10897                 break;
10898         case LED_MODE_OPER:
10899                 temp |= 0x0001;
10900                 break;
10901         case LED_MODE_ON:
10902                 temp |= 0x00ff;
10903                 break;
10904         default:
10905                 break;
10906         }
10907         bnx2x_cl22_write(bp, phy,
10908                 MDIO_REG_GPHY_SHADOW,
10909                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10910         return;
10911 }
10912
10913
10914 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10915                                      struct link_params *params)
10916 {
10917         struct bnx2x *bp = params->bp;
10918         u32 cfg_pin;
10919         u8 port;
10920
10921         /* In case of no EPIO routed to reset the GPHY, put it
10922          * in low power mode.
10923          */
10924         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10925         /* This works with E3 only, no need to check the chip
10926          * before determining the port.
10927          */
10928         port = params->port;
10929         cfg_pin = (REG_RD(bp, params->shmem_base +
10930                         offsetof(struct shmem_region,
10931                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10932                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10933                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10934
10935         /* Drive pin low to put GPHY in reset. */
10936         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10937 }
10938
10939 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10940                                     struct link_params *params,
10941                                     struct link_vars *vars)
10942 {
10943         struct bnx2x *bp = params->bp;
10944         u16 val;
10945         u8 link_up = 0;
10946         u16 legacy_status, legacy_speed;
10947
10948         /* Get speed operation status */
10949         bnx2x_cl22_read(bp, phy,
10950                         MDIO_REG_GPHY_AUX_STATUS,
10951                         &legacy_status);
10952         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10953
10954         /* Read status to clear the PHY interrupt. */
10955         bnx2x_cl22_read(bp, phy,
10956                         MDIO_REG_INTR_STATUS,
10957                         &val);
10958
10959         link_up = ((legacy_status & (1<<2)) == (1<<2));
10960
10961         if (link_up) {
10962                 legacy_speed = (legacy_status & (7<<8));
10963                 if (legacy_speed == (7<<8)) {
10964                         vars->line_speed = SPEED_1000;
10965                         vars->duplex = DUPLEX_FULL;
10966                 } else if (legacy_speed == (6<<8)) {
10967                         vars->line_speed = SPEED_1000;
10968                         vars->duplex = DUPLEX_HALF;
10969                 } else if (legacy_speed == (5<<8)) {
10970                         vars->line_speed = SPEED_100;
10971                         vars->duplex = DUPLEX_FULL;
10972                 }
10973                 /* Omitting 100Base-T4 for now */
10974                 else if (legacy_speed == (3<<8)) {
10975                         vars->line_speed = SPEED_100;
10976                         vars->duplex = DUPLEX_HALF;
10977                 } else if (legacy_speed == (2<<8)) {
10978                         vars->line_speed = SPEED_10;
10979                         vars->duplex = DUPLEX_FULL;
10980                 } else if (legacy_speed == (1<<8)) {
10981                         vars->line_speed = SPEED_10;
10982                         vars->duplex = DUPLEX_HALF;
10983                 } else /* Should not happen */
10984                         vars->line_speed = 0;
10985
10986                 DP(NETIF_MSG_LINK,
10987                    "Link is up in %dMbps, is_duplex_full= %d\n",
10988                    vars->line_speed,
10989                    (vars->duplex == DUPLEX_FULL));
10990
10991                 /* Check legacy speed AN resolution */
10992                 bnx2x_cl22_read(bp, phy,
10993                                 0x01,
10994                                 &val);
10995                 if (val & (1<<5))
10996                         vars->link_status |=
10997                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10998                 bnx2x_cl22_read(bp, phy,
10999                                 0x06,
11000                                 &val);
11001                 if ((val & (1<<0)) == 0)
11002                         vars->link_status |=
11003                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11004
11005                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11006                            vars->line_speed);
11007
11008                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11009
11010                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11011                         /* Report LP advertised speeds */
11012                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11013
11014                         if (val & (1<<5))
11015                                 vars->link_status |=
11016                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11017                         if (val & (1<<6))
11018                                 vars->link_status |=
11019                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11020                         if (val & (1<<7))
11021                                 vars->link_status |=
11022                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11023                         if (val & (1<<8))
11024                                 vars->link_status |=
11025                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11026                         if (val & (1<<9))
11027                                 vars->link_status |=
11028                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11029
11030                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11031                         if (val & (1<<10))
11032                                 vars->link_status |=
11033                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11034                         if (val & (1<<11))
11035                                 vars->link_status |=
11036                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11037
11038                         if ((phy->flags & FLAGS_EEE) &&
11039                             bnx2x_eee_has_cap(params))
11040                                 bnx2x_eee_an_resolve(phy, params, vars);
11041                 }
11042         }
11043         return link_up;
11044 }
11045
11046 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11047                                           struct link_params *params)
11048 {
11049         struct bnx2x *bp = params->bp;
11050         u16 val;
11051         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11052
11053         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11054
11055         /* Enable master/slave manual mmode and set to master */
11056         /* mii write 9 [bits set 11 12] */
11057         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11058
11059         /* forced 1G and disable autoneg */
11060         /* set val [mii read 0] */
11061         /* set val [expr $val & [bits clear 6 12 13]] */
11062         /* set val [expr $val | [bits set 6 8]] */
11063         /* mii write 0 $val */
11064         bnx2x_cl22_read(bp, phy, 0x00, &val);
11065         val &= ~((1<<6) | (1<<12) | (1<<13));
11066         val |= (1<<6) | (1<<8);
11067         bnx2x_cl22_write(bp, phy, 0x00, val);
11068
11069         /* Set external loopback and Tx using 6dB coding */
11070         /* mii write 0x18 7 */
11071         /* set val [mii read 0x18] */
11072         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11073         bnx2x_cl22_write(bp, phy, 0x18, 7);
11074         bnx2x_cl22_read(bp, phy, 0x18, &val);
11075         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11076
11077         /* This register opens the gate for the UMAC despite its name */
11078         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11079
11080         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11081          * length used by the MAC receive logic to check frames.
11082          */
11083         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11084 }
11085
11086 /******************************************************************/
11087 /*                      SFX7101 PHY SECTION                       */
11088 /******************************************************************/
11089 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11090                                        struct link_params *params)
11091 {
11092         struct bnx2x *bp = params->bp;
11093         /* SFX7101_XGXS_TEST1 */
11094         bnx2x_cl45_write(bp, phy,
11095                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11096 }
11097
11098 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11099                                   struct link_params *params,
11100                                   struct link_vars *vars)
11101 {
11102         u16 fw_ver1, fw_ver2, val;
11103         struct bnx2x *bp = params->bp;
11104         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11105
11106         /* Restore normal power mode*/
11107         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11108                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11109         /* HW reset */
11110         bnx2x_ext_phy_hw_reset(bp, params->port);
11111         bnx2x_wait_reset_complete(bp, phy, params);
11112
11113         bnx2x_cl45_write(bp, phy,
11114                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11115         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11116         bnx2x_cl45_write(bp, phy,
11117                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11118
11119         bnx2x_ext_phy_set_pause(params, phy, vars);
11120         /* Restart autoneg */
11121         bnx2x_cl45_read(bp, phy,
11122                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11123         val |= 0x200;
11124         bnx2x_cl45_write(bp, phy,
11125                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11126
11127         /* Save spirom version */
11128         bnx2x_cl45_read(bp, phy,
11129                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11130
11131         bnx2x_cl45_read(bp, phy,
11132                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11133         bnx2x_save_spirom_version(bp, params->port,
11134                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11135         return 0;
11136 }
11137
11138 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11139                                  struct link_params *params,
11140                                  struct link_vars *vars)
11141 {
11142         struct bnx2x *bp = params->bp;
11143         u8 link_up;
11144         u16 val1, val2;
11145         bnx2x_cl45_read(bp, phy,
11146                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11147         bnx2x_cl45_read(bp, phy,
11148                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11149         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11150                    val2, val1);
11151         bnx2x_cl45_read(bp, phy,
11152                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11153         bnx2x_cl45_read(bp, phy,
11154                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11155         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11156                    val2, val1);
11157         link_up = ((val1 & 4) == 4);
11158         /* If link is up print the AN outcome of the SFX7101 PHY */
11159         if (link_up) {
11160                 bnx2x_cl45_read(bp, phy,
11161                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11162                                 &val2);
11163                 vars->line_speed = SPEED_10000;
11164                 vars->duplex = DUPLEX_FULL;
11165                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11166                            val2, (val2 & (1<<14)));
11167                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11168                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11169
11170                 /* Read LP advertised speeds */
11171                 if (val2 & (1<<11))
11172                         vars->link_status |=
11173                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11174         }
11175         return link_up;
11176 }
11177
11178 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11179 {
11180         if (*len < 5)
11181                 return -EINVAL;
11182         str[0] = (spirom_ver & 0xFF);
11183         str[1] = (spirom_ver & 0xFF00) >> 8;
11184         str[2] = (spirom_ver & 0xFF0000) >> 16;
11185         str[3] = (spirom_ver & 0xFF000000) >> 24;
11186         str[4] = '\0';
11187         *len -= 5;
11188         return 0;
11189 }
11190
11191 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11192 {
11193         u16 val, cnt;
11194
11195         bnx2x_cl45_read(bp, phy,
11196                         MDIO_PMA_DEVAD,
11197                         MDIO_PMA_REG_7101_RESET, &val);
11198
11199         for (cnt = 0; cnt < 10; cnt++) {
11200                 msleep(50);
11201                 /* Writes a self-clearing reset */
11202                 bnx2x_cl45_write(bp, phy,
11203                                  MDIO_PMA_DEVAD,
11204                                  MDIO_PMA_REG_7101_RESET,
11205                                  (val | (1<<15)));
11206                 /* Wait for clear */
11207                 bnx2x_cl45_read(bp, phy,
11208                                 MDIO_PMA_DEVAD,
11209                                 MDIO_PMA_REG_7101_RESET, &val);
11210
11211                 if ((val & (1<<15)) == 0)
11212                         break;
11213         }
11214 }
11215
11216 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11217                                 struct link_params *params) {
11218         /* Low power mode is controlled by GPIO 2 */
11219         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11220                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11221         /* The PHY reset is controlled by GPIO 1 */
11222         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11223                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11224 }
11225
11226 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11227                                     struct link_params *params, u8 mode)
11228 {
11229         u16 val = 0;
11230         struct bnx2x *bp = params->bp;
11231         switch (mode) {
11232         case LED_MODE_FRONT_PANEL_OFF:
11233         case LED_MODE_OFF:
11234                 val = 2;
11235                 break;
11236         case LED_MODE_ON:
11237                 val = 1;
11238                 break;
11239         case LED_MODE_OPER:
11240                 val = 0;
11241                 break;
11242         }
11243         bnx2x_cl45_write(bp, phy,
11244                          MDIO_PMA_DEVAD,
11245                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11246                          val);
11247 }
11248
11249 /******************************************************************/
11250 /*                      STATIC PHY DECLARATION                    */
11251 /******************************************************************/
11252
11253 static const struct bnx2x_phy phy_null = {
11254         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11255         .addr           = 0,
11256         .def_md_devad   = 0,
11257         .flags          = FLAGS_INIT_XGXS_FIRST,
11258         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11259         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11260         .mdio_ctrl      = 0,
11261         .supported      = 0,
11262         .media_type     = ETH_PHY_NOT_PRESENT,
11263         .ver_addr       = 0,
11264         .req_flow_ctrl  = 0,
11265         .req_line_speed = 0,
11266         .speed_cap_mask = 0,
11267         .req_duplex     = 0,
11268         .rsrv           = 0,
11269         .config_init    = (config_init_t)NULL,
11270         .read_status    = (read_status_t)NULL,
11271         .link_reset     = (link_reset_t)NULL,
11272         .config_loopback = (config_loopback_t)NULL,
11273         .format_fw_ver  = (format_fw_ver_t)NULL,
11274         .hw_reset       = (hw_reset_t)NULL,
11275         .set_link_led   = (set_link_led_t)NULL,
11276         .phy_specific_func = (phy_specific_func_t)NULL
11277 };
11278
11279 static const struct bnx2x_phy phy_serdes = {
11280         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11281         .addr           = 0xff,
11282         .def_md_devad   = 0,
11283         .flags          = 0,
11284         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11285         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11286         .mdio_ctrl      = 0,
11287         .supported      = (SUPPORTED_10baseT_Half |
11288                            SUPPORTED_10baseT_Full |
11289                            SUPPORTED_100baseT_Half |
11290                            SUPPORTED_100baseT_Full |
11291                            SUPPORTED_1000baseT_Full |
11292                            SUPPORTED_2500baseX_Full |
11293                            SUPPORTED_TP |
11294                            SUPPORTED_Autoneg |
11295                            SUPPORTED_Pause |
11296                            SUPPORTED_Asym_Pause),
11297         .media_type     = ETH_PHY_BASE_T,
11298         .ver_addr       = 0,
11299         .req_flow_ctrl  = 0,
11300         .req_line_speed = 0,
11301         .speed_cap_mask = 0,
11302         .req_duplex     = 0,
11303         .rsrv           = 0,
11304         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11305         .read_status    = (read_status_t)bnx2x_link_settings_status,
11306         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11307         .config_loopback = (config_loopback_t)NULL,
11308         .format_fw_ver  = (format_fw_ver_t)NULL,
11309         .hw_reset       = (hw_reset_t)NULL,
11310         .set_link_led   = (set_link_led_t)NULL,
11311         .phy_specific_func = (phy_specific_func_t)NULL
11312 };
11313
11314 static const struct bnx2x_phy phy_xgxs = {
11315         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11316         .addr           = 0xff,
11317         .def_md_devad   = 0,
11318         .flags          = 0,
11319         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11320         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11321         .mdio_ctrl      = 0,
11322         .supported      = (SUPPORTED_10baseT_Half |
11323                            SUPPORTED_10baseT_Full |
11324                            SUPPORTED_100baseT_Half |
11325                            SUPPORTED_100baseT_Full |
11326                            SUPPORTED_1000baseT_Full |
11327                            SUPPORTED_2500baseX_Full |
11328                            SUPPORTED_10000baseT_Full |
11329                            SUPPORTED_FIBRE |
11330                            SUPPORTED_Autoneg |
11331                            SUPPORTED_Pause |
11332                            SUPPORTED_Asym_Pause),
11333         .media_type     = ETH_PHY_CX4,
11334         .ver_addr       = 0,
11335         .req_flow_ctrl  = 0,
11336         .req_line_speed = 0,
11337         .speed_cap_mask = 0,
11338         .req_duplex     = 0,
11339         .rsrv           = 0,
11340         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11341         .read_status    = (read_status_t)bnx2x_link_settings_status,
11342         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11343         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11344         .format_fw_ver  = (format_fw_ver_t)NULL,
11345         .hw_reset       = (hw_reset_t)NULL,
11346         .set_link_led   = (set_link_led_t)NULL,
11347         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11348 };
11349 static const struct bnx2x_phy phy_warpcore = {
11350         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11351         .addr           = 0xff,
11352         .def_md_devad   = 0,
11353         .flags          = FLAGS_TX_ERROR_CHECK,
11354         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11355         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11356         .mdio_ctrl      = 0,
11357         .supported      = (SUPPORTED_10baseT_Half |
11358                            SUPPORTED_10baseT_Full |
11359                            SUPPORTED_100baseT_Half |
11360                            SUPPORTED_100baseT_Full |
11361                            SUPPORTED_1000baseT_Full |
11362                            SUPPORTED_10000baseT_Full |
11363                            SUPPORTED_20000baseKR2_Full |
11364                            SUPPORTED_20000baseMLD2_Full |
11365                            SUPPORTED_FIBRE |
11366                            SUPPORTED_Autoneg |
11367                            SUPPORTED_Pause |
11368                            SUPPORTED_Asym_Pause),
11369         .media_type     = ETH_PHY_UNSPECIFIED,
11370         .ver_addr       = 0,
11371         .req_flow_ctrl  = 0,
11372         .req_line_speed = 0,
11373         .speed_cap_mask = 0,
11374         /* req_duplex = */0,
11375         /* rsrv = */0,
11376         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11377         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11378         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11379         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11380         .format_fw_ver  = (format_fw_ver_t)NULL,
11381         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11382         .set_link_led   = (set_link_led_t)NULL,
11383         .phy_specific_func = (phy_specific_func_t)NULL
11384 };
11385
11386
11387 static const struct bnx2x_phy phy_7101 = {
11388         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11389         .addr           = 0xff,
11390         .def_md_devad   = 0,
11391         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11392         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11393         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11394         .mdio_ctrl      = 0,
11395         .supported      = (SUPPORTED_10000baseT_Full |
11396                            SUPPORTED_TP |
11397                            SUPPORTED_Autoneg |
11398                            SUPPORTED_Pause |
11399                            SUPPORTED_Asym_Pause),
11400         .media_type     = ETH_PHY_BASE_T,
11401         .ver_addr       = 0,
11402         .req_flow_ctrl  = 0,
11403         .req_line_speed = 0,
11404         .speed_cap_mask = 0,
11405         .req_duplex     = 0,
11406         .rsrv           = 0,
11407         .config_init    = (config_init_t)bnx2x_7101_config_init,
11408         .read_status    = (read_status_t)bnx2x_7101_read_status,
11409         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11410         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11411         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11412         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11413         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11414         .phy_specific_func = (phy_specific_func_t)NULL
11415 };
11416 static const struct bnx2x_phy phy_8073 = {
11417         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11418         .addr           = 0xff,
11419         .def_md_devad   = 0,
11420         .flags          = 0,
11421         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11422         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11423         .mdio_ctrl      = 0,
11424         .supported      = (SUPPORTED_10000baseT_Full |
11425                            SUPPORTED_2500baseX_Full |
11426                            SUPPORTED_1000baseT_Full |
11427                            SUPPORTED_FIBRE |
11428                            SUPPORTED_Autoneg |
11429                            SUPPORTED_Pause |
11430                            SUPPORTED_Asym_Pause),
11431         .media_type     = ETH_PHY_KR,
11432         .ver_addr       = 0,
11433         .req_flow_ctrl  = 0,
11434         .req_line_speed = 0,
11435         .speed_cap_mask = 0,
11436         .req_duplex     = 0,
11437         .rsrv           = 0,
11438         .config_init    = (config_init_t)bnx2x_8073_config_init,
11439         .read_status    = (read_status_t)bnx2x_8073_read_status,
11440         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11441         .config_loopback = (config_loopback_t)NULL,
11442         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11443         .hw_reset       = (hw_reset_t)NULL,
11444         .set_link_led   = (set_link_led_t)NULL,
11445         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11446 };
11447 static const struct bnx2x_phy phy_8705 = {
11448         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11449         .addr           = 0xff,
11450         .def_md_devad   = 0,
11451         .flags          = FLAGS_INIT_XGXS_FIRST,
11452         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11453         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11454         .mdio_ctrl      = 0,
11455         .supported      = (SUPPORTED_10000baseT_Full |
11456                            SUPPORTED_FIBRE |
11457                            SUPPORTED_Pause |
11458                            SUPPORTED_Asym_Pause),
11459         .media_type     = ETH_PHY_XFP_FIBER,
11460         .ver_addr       = 0,
11461         .req_flow_ctrl  = 0,
11462         .req_line_speed = 0,
11463         .speed_cap_mask = 0,
11464         .req_duplex     = 0,
11465         .rsrv           = 0,
11466         .config_init    = (config_init_t)bnx2x_8705_config_init,
11467         .read_status    = (read_status_t)bnx2x_8705_read_status,
11468         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11469         .config_loopback = (config_loopback_t)NULL,
11470         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11471         .hw_reset       = (hw_reset_t)NULL,
11472         .set_link_led   = (set_link_led_t)NULL,
11473         .phy_specific_func = (phy_specific_func_t)NULL
11474 };
11475 static const struct bnx2x_phy phy_8706 = {
11476         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11477         .addr           = 0xff,
11478         .def_md_devad   = 0,
11479         .flags          = FLAGS_INIT_XGXS_FIRST,
11480         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11481         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11482         .mdio_ctrl      = 0,
11483         .supported      = (SUPPORTED_10000baseT_Full |
11484                            SUPPORTED_1000baseT_Full |
11485                            SUPPORTED_FIBRE |
11486                            SUPPORTED_Pause |
11487                            SUPPORTED_Asym_Pause),
11488         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11489         .ver_addr       = 0,
11490         .req_flow_ctrl  = 0,
11491         .req_line_speed = 0,
11492         .speed_cap_mask = 0,
11493         .req_duplex     = 0,
11494         .rsrv           = 0,
11495         .config_init    = (config_init_t)bnx2x_8706_config_init,
11496         .read_status    = (read_status_t)bnx2x_8706_read_status,
11497         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11498         .config_loopback = (config_loopback_t)NULL,
11499         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11500         .hw_reset       = (hw_reset_t)NULL,
11501         .set_link_led   = (set_link_led_t)NULL,
11502         .phy_specific_func = (phy_specific_func_t)NULL
11503 };
11504
11505 static const struct bnx2x_phy phy_8726 = {
11506         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11507         .addr           = 0xff,
11508         .def_md_devad   = 0,
11509         .flags          = (FLAGS_INIT_XGXS_FIRST |
11510                            FLAGS_TX_ERROR_CHECK),
11511         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11512         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11513         .mdio_ctrl      = 0,
11514         .supported      = (SUPPORTED_10000baseT_Full |
11515                            SUPPORTED_1000baseT_Full |
11516                            SUPPORTED_Autoneg |
11517                            SUPPORTED_FIBRE |
11518                            SUPPORTED_Pause |
11519                            SUPPORTED_Asym_Pause),
11520         .media_type     = ETH_PHY_NOT_PRESENT,
11521         .ver_addr       = 0,
11522         .req_flow_ctrl  = 0,
11523         .req_line_speed = 0,
11524         .speed_cap_mask = 0,
11525         .req_duplex     = 0,
11526         .rsrv           = 0,
11527         .config_init    = (config_init_t)bnx2x_8726_config_init,
11528         .read_status    = (read_status_t)bnx2x_8726_read_status,
11529         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11530         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11531         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11532         .hw_reset       = (hw_reset_t)NULL,
11533         .set_link_led   = (set_link_led_t)NULL,
11534         .phy_specific_func = (phy_specific_func_t)NULL
11535 };
11536
11537 static const struct bnx2x_phy phy_8727 = {
11538         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11539         .addr           = 0xff,
11540         .def_md_devad   = 0,
11541         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11542                            FLAGS_TX_ERROR_CHECK),
11543         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11544         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11545         .mdio_ctrl      = 0,
11546         .supported      = (SUPPORTED_10000baseT_Full |
11547                            SUPPORTED_1000baseT_Full |
11548                            SUPPORTED_FIBRE |
11549                            SUPPORTED_Pause |
11550                            SUPPORTED_Asym_Pause),
11551         .media_type     = ETH_PHY_NOT_PRESENT,
11552         .ver_addr       = 0,
11553         .req_flow_ctrl  = 0,
11554         .req_line_speed = 0,
11555         .speed_cap_mask = 0,
11556         .req_duplex     = 0,
11557         .rsrv           = 0,
11558         .config_init    = (config_init_t)bnx2x_8727_config_init,
11559         .read_status    = (read_status_t)bnx2x_8727_read_status,
11560         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11561         .config_loopback = (config_loopback_t)NULL,
11562         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11563         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11564         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11565         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11566 };
11567 static const struct bnx2x_phy phy_8481 = {
11568         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11569         .addr           = 0xff,
11570         .def_md_devad   = 0,
11571         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11572                           FLAGS_REARM_LATCH_SIGNAL,
11573         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11574         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11575         .mdio_ctrl      = 0,
11576         .supported      = (SUPPORTED_10baseT_Half |
11577                            SUPPORTED_10baseT_Full |
11578                            SUPPORTED_100baseT_Half |
11579                            SUPPORTED_100baseT_Full |
11580                            SUPPORTED_1000baseT_Full |
11581                            SUPPORTED_10000baseT_Full |
11582                            SUPPORTED_TP |
11583                            SUPPORTED_Autoneg |
11584                            SUPPORTED_Pause |
11585                            SUPPORTED_Asym_Pause),
11586         .media_type     = ETH_PHY_BASE_T,
11587         .ver_addr       = 0,
11588         .req_flow_ctrl  = 0,
11589         .req_line_speed = 0,
11590         .speed_cap_mask = 0,
11591         .req_duplex     = 0,
11592         .rsrv           = 0,
11593         .config_init    = (config_init_t)bnx2x_8481_config_init,
11594         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11595         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11596         .config_loopback = (config_loopback_t)NULL,
11597         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11598         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11599         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11600         .phy_specific_func = (phy_specific_func_t)NULL
11601 };
11602
11603 static const struct bnx2x_phy phy_84823 = {
11604         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11605         .addr           = 0xff,
11606         .def_md_devad   = 0,
11607         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11608                            FLAGS_REARM_LATCH_SIGNAL |
11609                            FLAGS_TX_ERROR_CHECK),
11610         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11611         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11612         .mdio_ctrl      = 0,
11613         .supported      = (SUPPORTED_10baseT_Half |
11614                            SUPPORTED_10baseT_Full |
11615                            SUPPORTED_100baseT_Half |
11616                            SUPPORTED_100baseT_Full |
11617                            SUPPORTED_1000baseT_Full |
11618                            SUPPORTED_10000baseT_Full |
11619                            SUPPORTED_TP |
11620                            SUPPORTED_Autoneg |
11621                            SUPPORTED_Pause |
11622                            SUPPORTED_Asym_Pause),
11623         .media_type     = ETH_PHY_BASE_T,
11624         .ver_addr       = 0,
11625         .req_flow_ctrl  = 0,
11626         .req_line_speed = 0,
11627         .speed_cap_mask = 0,
11628         .req_duplex     = 0,
11629         .rsrv           = 0,
11630         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11631         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11632         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11633         .config_loopback = (config_loopback_t)NULL,
11634         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11635         .hw_reset       = (hw_reset_t)NULL,
11636         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11637         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11638 };
11639
11640 static const struct bnx2x_phy phy_84833 = {
11641         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11642         .addr           = 0xff,
11643         .def_md_devad   = 0,
11644         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11645                            FLAGS_REARM_LATCH_SIGNAL |
11646                            FLAGS_TX_ERROR_CHECK),
11647         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11648         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11649         .mdio_ctrl      = 0,
11650         .supported      = (SUPPORTED_100baseT_Half |
11651                            SUPPORTED_100baseT_Full |
11652                            SUPPORTED_1000baseT_Full |
11653                            SUPPORTED_10000baseT_Full |
11654                            SUPPORTED_TP |
11655                            SUPPORTED_Autoneg |
11656                            SUPPORTED_Pause |
11657                            SUPPORTED_Asym_Pause),
11658         .media_type     = ETH_PHY_BASE_T,
11659         .ver_addr       = 0,
11660         .req_flow_ctrl  = 0,
11661         .req_line_speed = 0,
11662         .speed_cap_mask = 0,
11663         .req_duplex     = 0,
11664         .rsrv           = 0,
11665         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11666         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11667         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11668         .config_loopback = (config_loopback_t)NULL,
11669         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11670         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11671         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11672         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11673 };
11674
11675 static const struct bnx2x_phy phy_84834 = {
11676         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11677         .addr           = 0xff,
11678         .def_md_devad   = 0,
11679         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11680                             FLAGS_REARM_LATCH_SIGNAL,
11681         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11682         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11683         .mdio_ctrl      = 0,
11684         .supported      = (SUPPORTED_100baseT_Half |
11685                            SUPPORTED_100baseT_Full |
11686                            SUPPORTED_1000baseT_Full |
11687                            SUPPORTED_10000baseT_Full |
11688                            SUPPORTED_TP |
11689                            SUPPORTED_Autoneg |
11690                            SUPPORTED_Pause |
11691                            SUPPORTED_Asym_Pause),
11692         .media_type     = ETH_PHY_BASE_T,
11693         .ver_addr       = 0,
11694         .req_flow_ctrl  = 0,
11695         .req_line_speed = 0,
11696         .speed_cap_mask = 0,
11697         .req_duplex     = 0,
11698         .rsrv           = 0,
11699         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11700         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11701         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11702         .config_loopback = (config_loopback_t)NULL,
11703         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11704         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11705         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11706         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11707 };
11708
11709 static const struct bnx2x_phy phy_54618se = {
11710         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11711         .addr           = 0xff,
11712         .def_md_devad   = 0,
11713         .flags          = FLAGS_INIT_XGXS_FIRST,
11714         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11715         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11716         .mdio_ctrl      = 0,
11717         .supported      = (SUPPORTED_10baseT_Half |
11718                            SUPPORTED_10baseT_Full |
11719                            SUPPORTED_100baseT_Half |
11720                            SUPPORTED_100baseT_Full |
11721                            SUPPORTED_1000baseT_Full |
11722                            SUPPORTED_TP |
11723                            SUPPORTED_Autoneg |
11724                            SUPPORTED_Pause |
11725                            SUPPORTED_Asym_Pause),
11726         .media_type     = ETH_PHY_BASE_T,
11727         .ver_addr       = 0,
11728         .req_flow_ctrl  = 0,
11729         .req_line_speed = 0,
11730         .speed_cap_mask = 0,
11731         /* req_duplex = */0,
11732         /* rsrv = */0,
11733         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11734         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11735         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11736         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11737         .format_fw_ver  = (format_fw_ver_t)NULL,
11738         .hw_reset       = (hw_reset_t)NULL,
11739         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11740         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11741 };
11742 /*****************************************************************/
11743 /*                                                               */
11744 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11745 /*                                                               */
11746 /*****************************************************************/
11747
11748 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11749                                      struct bnx2x_phy *phy, u8 port,
11750                                      u8 phy_index)
11751 {
11752         /* Get the 4 lanes xgxs config rx and tx */
11753         u32 rx = 0, tx = 0, i;
11754         for (i = 0; i < 2; i++) {
11755                 /* INT_PHY and EXT_PHY1 share the same value location in
11756                  * the shmem. When num_phys is greater than 1, than this value
11757                  * applies only to EXT_PHY1
11758                  */
11759                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11760                         rx = REG_RD(bp, shmem_base +
11761                                     offsetof(struct shmem_region,
11762                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11763
11764                         tx = REG_RD(bp, shmem_base +
11765                                     offsetof(struct shmem_region,
11766                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11767                 } else {
11768                         rx = REG_RD(bp, shmem_base +
11769                                     offsetof(struct shmem_region,
11770                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11771
11772                         tx = REG_RD(bp, shmem_base +
11773                                     offsetof(struct shmem_region,
11774                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11775                 }
11776
11777                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11778                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11779
11780                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11781                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11782         }
11783 }
11784
11785 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11786                                     u8 phy_index, u8 port)
11787 {
11788         u32 ext_phy_config = 0;
11789         switch (phy_index) {
11790         case EXT_PHY1:
11791                 ext_phy_config = REG_RD(bp, shmem_base +
11792                                               offsetof(struct shmem_region,
11793                         dev_info.port_hw_config[port].external_phy_config));
11794                 break;
11795         case EXT_PHY2:
11796                 ext_phy_config = REG_RD(bp, shmem_base +
11797                                               offsetof(struct shmem_region,
11798                         dev_info.port_hw_config[port].external_phy_config2));
11799                 break;
11800         default:
11801                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11802                 return -EINVAL;
11803         }
11804
11805         return ext_phy_config;
11806 }
11807 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11808                                   struct bnx2x_phy *phy)
11809 {
11810         u32 phy_addr;
11811         u32 chip_id;
11812         u32 switch_cfg = (REG_RD(bp, shmem_base +
11813                                        offsetof(struct shmem_region,
11814                         dev_info.port_feature_config[port].link_config)) &
11815                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11816         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11817                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11818
11819         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11820         if (USES_WARPCORE(bp)) {
11821                 u32 serdes_net_if;
11822                 phy_addr = REG_RD(bp,
11823                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11824                 *phy = phy_warpcore;
11825                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11826                         phy->flags |= FLAGS_4_PORT_MODE;
11827                 else
11828                         phy->flags &= ~FLAGS_4_PORT_MODE;
11829                         /* Check Dual mode */
11830                 serdes_net_if = (REG_RD(bp, shmem_base +
11831                                         offsetof(struct shmem_region, dev_info.
11832                                         port_hw_config[port].default_cfg)) &
11833                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11834                 /* Set the appropriate supported and flags indications per
11835                  * interface type of the chip
11836                  */
11837                 switch (serdes_net_if) {
11838                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11839                         phy->supported &= (SUPPORTED_10baseT_Half |
11840                                            SUPPORTED_10baseT_Full |
11841                                            SUPPORTED_100baseT_Half |
11842                                            SUPPORTED_100baseT_Full |
11843                                            SUPPORTED_1000baseT_Full |
11844                                            SUPPORTED_FIBRE |
11845                                            SUPPORTED_Autoneg |
11846                                            SUPPORTED_Pause |
11847                                            SUPPORTED_Asym_Pause);
11848                         phy->media_type = ETH_PHY_BASE_T;
11849                         break;
11850                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11851                         phy->supported &= (SUPPORTED_1000baseT_Full |
11852                                            SUPPORTED_10000baseT_Full |
11853                                            SUPPORTED_FIBRE |
11854                                            SUPPORTED_Pause |
11855                                            SUPPORTED_Asym_Pause);
11856                         phy->media_type = ETH_PHY_XFP_FIBER;
11857                         break;
11858                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11859                         phy->supported &= (SUPPORTED_1000baseT_Full |
11860                                            SUPPORTED_10000baseT_Full |
11861                                            SUPPORTED_FIBRE |
11862                                            SUPPORTED_Pause |
11863                                            SUPPORTED_Asym_Pause);
11864                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11865                         break;
11866                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11867                         phy->media_type = ETH_PHY_KR;
11868                         phy->supported &= (SUPPORTED_1000baseT_Full |
11869                                            SUPPORTED_10000baseT_Full |
11870                                            SUPPORTED_FIBRE |
11871                                            SUPPORTED_Autoneg |
11872                                            SUPPORTED_Pause |
11873                                            SUPPORTED_Asym_Pause);
11874                         break;
11875                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11876                         phy->media_type = ETH_PHY_KR;
11877                         phy->flags |= FLAGS_WC_DUAL_MODE;
11878                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11879                                            SUPPORTED_FIBRE |
11880                                            SUPPORTED_Pause |
11881                                            SUPPORTED_Asym_Pause);
11882                         break;
11883                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11884                         phy->media_type = ETH_PHY_KR;
11885                         phy->flags |= FLAGS_WC_DUAL_MODE;
11886                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11887                                            SUPPORTED_10000baseT_Full |
11888                                            SUPPORTED_1000baseT_Full |
11889                                            SUPPORTED_Autoneg |
11890                                            SUPPORTED_FIBRE |
11891                                            SUPPORTED_Pause |
11892                                            SUPPORTED_Asym_Pause);
11893                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11894                         break;
11895                 default:
11896                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11897                                        serdes_net_if);
11898                         break;
11899                 }
11900
11901                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11902                  * was not set as expected. For B0, ECO will be enabled so there
11903                  * won't be an issue there
11904                  */
11905                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11906                         phy->flags |= FLAGS_MDC_MDIO_WA;
11907                 else
11908                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11909         } else {
11910                 switch (switch_cfg) {
11911                 case SWITCH_CFG_1G:
11912                         phy_addr = REG_RD(bp,
11913                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11914                                           port * 0x10);
11915                         *phy = phy_serdes;
11916                         break;
11917                 case SWITCH_CFG_10G:
11918                         phy_addr = REG_RD(bp,
11919                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11920                                           port * 0x18);
11921                         *phy = phy_xgxs;
11922                         break;
11923                 default:
11924                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11925                         return -EINVAL;
11926                 }
11927         }
11928         phy->addr = (u8)phy_addr;
11929         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11930                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11931                                             port);
11932         if (CHIP_IS_E2(bp))
11933                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11934         else
11935                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11936
11937         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11938                    port, phy->addr, phy->mdio_ctrl);
11939
11940         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11941         return 0;
11942 }
11943
11944 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11945                                   u8 phy_index,
11946                                   u32 shmem_base,
11947                                   u32 shmem2_base,
11948                                   u8 port,
11949                                   struct bnx2x_phy *phy)
11950 {
11951         u32 ext_phy_config, phy_type, config2;
11952         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11953         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11954                                                   phy_index, port);
11955         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11956         /* Select the phy type */
11957         switch (phy_type) {
11958         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11959                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11960                 *phy = phy_8073;
11961                 break;
11962         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11963                 *phy = phy_8705;
11964                 break;
11965         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11966                 *phy = phy_8706;
11967                 break;
11968         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11969                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11970                 *phy = phy_8726;
11971                 break;
11972         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11973                 /* BCM8727_NOC => BCM8727 no over current */
11974                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11975                 *phy = phy_8727;
11976                 phy->flags |= FLAGS_NOC;
11977                 break;
11978         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11979         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11980                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11981                 *phy = phy_8727;
11982                 break;
11983         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11984                 *phy = phy_8481;
11985                 break;
11986         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11987                 *phy = phy_84823;
11988                 break;
11989         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11990                 *phy = phy_84833;
11991                 break;
11992         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
11993                 *phy = phy_84834;
11994                 break;
11995         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11996         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11997                 *phy = phy_54618se;
11998                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
11999                         phy->flags |= FLAGS_EEE;
12000                 break;
12001         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12002                 *phy = phy_7101;
12003                 break;
12004         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12005                 *phy = phy_null;
12006                 return -EINVAL;
12007         default:
12008                 *phy = phy_null;
12009                 /* In case external PHY wasn't found */
12010                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12011                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12012                         return -EINVAL;
12013                 return 0;
12014         }
12015
12016         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12017         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12018
12019         /* The shmem address of the phy version is located on different
12020          * structures. In case this structure is too old, do not set
12021          * the address
12022          */
12023         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12024                                         dev_info.shared_hw_config.config2));
12025         if (phy_index == EXT_PHY1) {
12026                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12027                                 port_mb[port].ext_phy_fw_version);
12028
12029                 /* Check specific mdc mdio settings */
12030                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12031                         mdc_mdio_access = config2 &
12032                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12033         } else {
12034                 u32 size = REG_RD(bp, shmem2_base);
12035
12036                 if (size >
12037                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12038                         phy->ver_addr = shmem2_base +
12039                             offsetof(struct shmem2_region,
12040                                      ext_phy_fw_version2[port]);
12041                 }
12042                 /* Check specific mdc mdio settings */
12043                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12044                         mdc_mdio_access = (config2 &
12045                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12046                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12047                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12048         }
12049         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12050
12051         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12052              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12053             (phy->ver_addr)) {
12054                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12055                  * version lower than or equal to 1.39
12056                  */
12057                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12058                 if (((raw_ver & 0x7F) <= 39) &&
12059                     (((raw_ver & 0xF80) >> 7) <= 1))
12060                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12061                                             SUPPORTED_100baseT_Full);
12062         }
12063
12064         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12065                    phy_type, port, phy_index);
12066         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12067                    phy->addr, phy->mdio_ctrl);
12068         return 0;
12069 }
12070
12071 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12072                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12073 {
12074         int status = 0;
12075         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12076         if (phy_index == INT_PHY)
12077                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12078         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12079                                         port, phy);
12080         return status;
12081 }
12082
12083 static void bnx2x_phy_def_cfg(struct link_params *params,
12084                               struct bnx2x_phy *phy,
12085                               u8 phy_index)
12086 {
12087         struct bnx2x *bp = params->bp;
12088         u32 link_config;
12089         /* Populate the default phy configuration for MF mode */
12090         if (phy_index == EXT_PHY2) {
12091                 link_config = REG_RD(bp, params->shmem_base +
12092                                      offsetof(struct shmem_region, dev_info.
12093                         port_feature_config[params->port].link_config2));
12094                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12095                                              offsetof(struct shmem_region,
12096                                                       dev_info.
12097                         port_hw_config[params->port].speed_capability_mask2));
12098         } else {
12099                 link_config = REG_RD(bp, params->shmem_base +
12100                                      offsetof(struct shmem_region, dev_info.
12101                                 port_feature_config[params->port].link_config));
12102                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12103                                              offsetof(struct shmem_region,
12104                                                       dev_info.
12105                         port_hw_config[params->port].speed_capability_mask));
12106         }
12107         DP(NETIF_MSG_LINK,
12108            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12109            phy_index, link_config, phy->speed_cap_mask);
12110
12111         phy->req_duplex = DUPLEX_FULL;
12112         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12113         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12114                 phy->req_duplex = DUPLEX_HALF;
12115         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12116                 phy->req_line_speed = SPEED_10;
12117                 break;
12118         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12119                 phy->req_duplex = DUPLEX_HALF;
12120         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12121                 phy->req_line_speed = SPEED_100;
12122                 break;
12123         case PORT_FEATURE_LINK_SPEED_1G:
12124                 phy->req_line_speed = SPEED_1000;
12125                 break;
12126         case PORT_FEATURE_LINK_SPEED_2_5G:
12127                 phy->req_line_speed = SPEED_2500;
12128                 break;
12129         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12130                 phy->req_line_speed = SPEED_10000;
12131                 break;
12132         default:
12133                 phy->req_line_speed = SPEED_AUTO_NEG;
12134                 break;
12135         }
12136
12137         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12138         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12139                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12140                 break;
12141         case PORT_FEATURE_FLOW_CONTROL_TX:
12142                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12143                 break;
12144         case PORT_FEATURE_FLOW_CONTROL_RX:
12145                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12146                 break;
12147         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12148                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12149                 break;
12150         default:
12151                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12152                 break;
12153         }
12154 }
12155
12156 u32 bnx2x_phy_selection(struct link_params *params)
12157 {
12158         u32 phy_config_swapped, prio_cfg;
12159         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12160
12161         phy_config_swapped = params->multi_phy_config &
12162                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12163
12164         prio_cfg = params->multi_phy_config &
12165                         PORT_HW_CFG_PHY_SELECTION_MASK;
12166
12167         if (phy_config_swapped) {
12168                 switch (prio_cfg) {
12169                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12170                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12171                      break;
12172                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12173                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12174                      break;
12175                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12176                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12177                      break;
12178                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12179                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12180                      break;
12181                 }
12182         } else
12183                 return_cfg = prio_cfg;
12184
12185         return return_cfg;
12186 }
12187
12188 int bnx2x_phy_probe(struct link_params *params)
12189 {
12190         u8 phy_index, actual_phy_idx;
12191         u32 phy_config_swapped, sync_offset, media_types;
12192         struct bnx2x *bp = params->bp;
12193         struct bnx2x_phy *phy;
12194         params->num_phys = 0;
12195         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12196         phy_config_swapped = params->multi_phy_config &
12197                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12198
12199         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12200               phy_index++) {
12201                 actual_phy_idx = phy_index;
12202                 if (phy_config_swapped) {
12203                         if (phy_index == EXT_PHY1)
12204                                 actual_phy_idx = EXT_PHY2;
12205                         else if (phy_index == EXT_PHY2)
12206                                 actual_phy_idx = EXT_PHY1;
12207                 }
12208                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12209                                " actual_phy_idx %x\n", phy_config_swapped,
12210                            phy_index, actual_phy_idx);
12211                 phy = &params->phy[actual_phy_idx];
12212                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12213                                        params->shmem2_base, params->port,
12214                                        phy) != 0) {
12215                         params->num_phys = 0;
12216                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12217                                    phy_index);
12218                         for (phy_index = INT_PHY;
12219                               phy_index < MAX_PHYS;
12220                               phy_index++)
12221                                 *phy = phy_null;
12222                         return -EINVAL;
12223                 }
12224                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12225                         break;
12226
12227                 if (params->feature_config_flags &
12228                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12229                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12230
12231                 if (!(params->feature_config_flags &
12232                       FEATURE_CONFIG_MT_SUPPORT))
12233                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12234
12235                 sync_offset = params->shmem_base +
12236                         offsetof(struct shmem_region,
12237                         dev_info.port_hw_config[params->port].media_type);
12238                 media_types = REG_RD(bp, sync_offset);
12239
12240                 /* Update media type for non-PMF sync only for the first time
12241                  * In case the media type changes afterwards, it will be updated
12242                  * using the update_status function
12243                  */
12244                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12245                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12246                                      actual_phy_idx))) == 0) {
12247                         media_types |= ((phy->media_type &
12248                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12249                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12250                                  actual_phy_idx));
12251                 }
12252                 REG_WR(bp, sync_offset, media_types);
12253
12254                 bnx2x_phy_def_cfg(params, phy, phy_index);
12255                 params->num_phys++;
12256         }
12257
12258         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12259         return 0;
12260 }
12261
12262 static void bnx2x_init_bmac_loopback(struct link_params *params,
12263                                      struct link_vars *vars)
12264 {
12265         struct bnx2x *bp = params->bp;
12266                 vars->link_up = 1;
12267                 vars->line_speed = SPEED_10000;
12268                 vars->duplex = DUPLEX_FULL;
12269                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12270                 vars->mac_type = MAC_TYPE_BMAC;
12271
12272                 vars->phy_flags = PHY_XGXS_FLAG;
12273
12274                 bnx2x_xgxs_deassert(params);
12275
12276                 /* Set bmac loopback */
12277                 bnx2x_bmac_enable(params, vars, 1, 1);
12278
12279                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12280 }
12281
12282 static void bnx2x_init_emac_loopback(struct link_params *params,
12283                                      struct link_vars *vars)
12284 {
12285         struct bnx2x *bp = params->bp;
12286                 vars->link_up = 1;
12287                 vars->line_speed = SPEED_1000;
12288                 vars->duplex = DUPLEX_FULL;
12289                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12290                 vars->mac_type = MAC_TYPE_EMAC;
12291
12292                 vars->phy_flags = PHY_XGXS_FLAG;
12293
12294                 bnx2x_xgxs_deassert(params);
12295                 /* Set bmac loopback */
12296                 bnx2x_emac_enable(params, vars, 1);
12297                 bnx2x_emac_program(params, vars);
12298                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12299 }
12300
12301 static void bnx2x_init_xmac_loopback(struct link_params *params,
12302                                      struct link_vars *vars)
12303 {
12304         struct bnx2x *bp = params->bp;
12305         vars->link_up = 1;
12306         if (!params->req_line_speed[0])
12307                 vars->line_speed = SPEED_10000;
12308         else
12309                 vars->line_speed = params->req_line_speed[0];
12310         vars->duplex = DUPLEX_FULL;
12311         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12312         vars->mac_type = MAC_TYPE_XMAC;
12313         vars->phy_flags = PHY_XGXS_FLAG;
12314         /* Set WC to loopback mode since link is required to provide clock
12315          * to the XMAC in 20G mode
12316          */
12317         bnx2x_set_aer_mmd(params, &params->phy[0]);
12318         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12319         params->phy[INT_PHY].config_loopback(
12320                         &params->phy[INT_PHY],
12321                         params);
12322
12323         bnx2x_xmac_enable(params, vars, 1);
12324         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12325 }
12326
12327 static void bnx2x_init_umac_loopback(struct link_params *params,
12328                                      struct link_vars *vars)
12329 {
12330         struct bnx2x *bp = params->bp;
12331         vars->link_up = 1;
12332         vars->line_speed = SPEED_1000;
12333         vars->duplex = DUPLEX_FULL;
12334         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12335         vars->mac_type = MAC_TYPE_UMAC;
12336         vars->phy_flags = PHY_XGXS_FLAG;
12337         bnx2x_umac_enable(params, vars, 1);
12338
12339         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12340 }
12341
12342 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12343                                      struct link_vars *vars)
12344 {
12345         struct bnx2x *bp = params->bp;
12346         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12347         vars->link_up = 1;
12348         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12349         vars->duplex = DUPLEX_FULL;
12350         if (params->req_line_speed[0] == SPEED_1000)
12351                 vars->line_speed = SPEED_1000;
12352         else if ((params->req_line_speed[0] == SPEED_20000) ||
12353                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12354                 vars->line_speed = SPEED_20000;
12355         else
12356                 vars->line_speed = SPEED_10000;
12357
12358         if (!USES_WARPCORE(bp))
12359                 bnx2x_xgxs_deassert(params);
12360         bnx2x_link_initialize(params, vars);
12361
12362         if (params->req_line_speed[0] == SPEED_1000) {
12363                 if (USES_WARPCORE(bp))
12364                         bnx2x_umac_enable(params, vars, 0);
12365                 else {
12366                         bnx2x_emac_program(params, vars);
12367                         bnx2x_emac_enable(params, vars, 0);
12368                 }
12369         } else {
12370                 if (USES_WARPCORE(bp))
12371                         bnx2x_xmac_enable(params, vars, 0);
12372                 else
12373                         bnx2x_bmac_enable(params, vars, 0, 1);
12374         }
12375
12376         if (params->loopback_mode == LOOPBACK_XGXS) {
12377                 /* Set 10G XGXS loopback */
12378                 int_phy->config_loopback(int_phy, params);
12379         } else {
12380                 /* Set external phy loopback */
12381                 u8 phy_index;
12382                 for (phy_index = EXT_PHY1;
12383                       phy_index < params->num_phys; phy_index++)
12384                         if (params->phy[phy_index].config_loopback)
12385                                 params->phy[phy_index].config_loopback(
12386                                         &params->phy[phy_index],
12387                                         params);
12388         }
12389         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12390
12391         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12392 }
12393
12394 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12395 {
12396         struct bnx2x *bp = params->bp;
12397         u8 val = en * 0x1F;
12398
12399         /* Open / close the gate between the NIG and the BRB */
12400         if (!CHIP_IS_E1x(bp))
12401                 val |= en * 0x20;
12402         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12403
12404         if (!CHIP_IS_E1(bp)) {
12405                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12406                        en*0x3);
12407         }
12408
12409         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12410                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12411 }
12412 static int bnx2x_avoid_link_flap(struct link_params *params,
12413                                             struct link_vars *vars)
12414 {
12415         u32 phy_idx;
12416         u32 dont_clear_stat, lfa_sts;
12417         struct bnx2x *bp = params->bp;
12418
12419         /* Sync the link parameters */
12420         bnx2x_link_status_update(params, vars);
12421
12422         /*
12423          * The module verification was already done by previous link owner,
12424          * so this call is meant only to get warning message
12425          */
12426
12427         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12428                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12429                 if (phy->phy_specific_func) {
12430                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12431                         phy->phy_specific_func(phy, params, PHY_INIT);
12432                 }
12433                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12434                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12435                     (phy->media_type == ETH_PHY_DA_TWINAX))
12436                         bnx2x_verify_sfp_module(phy, params);
12437         }
12438         lfa_sts = REG_RD(bp, params->lfa_base +
12439                          offsetof(struct shmem_lfa,
12440                                   lfa_sts));
12441
12442         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12443
12444         /* Re-enable the NIG/MAC */
12445         if (CHIP_IS_E3(bp)) {
12446                 if (!dont_clear_stat) {
12447                         REG_WR(bp, GRCBASE_MISC +
12448                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12449                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12450                                 params->port));
12451                         REG_WR(bp, GRCBASE_MISC +
12452                                MISC_REGISTERS_RESET_REG_2_SET,
12453                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12454                                 params->port));
12455                 }
12456                 if (vars->line_speed < SPEED_10000)
12457                         bnx2x_umac_enable(params, vars, 0);
12458                 else
12459                         bnx2x_xmac_enable(params, vars, 0);
12460         } else {
12461                 if (vars->line_speed < SPEED_10000)
12462                         bnx2x_emac_enable(params, vars, 0);
12463                 else
12464                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12465         }
12466
12467         /* Increment LFA count */
12468         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12469                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12470                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12471                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12472         /* Clear link flap reason */
12473         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12474
12475         REG_WR(bp, params->lfa_base +
12476                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12477
12478         /* Disable NIG DRAIN */
12479         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12480
12481         /* Enable interrupts */
12482         bnx2x_link_int_enable(params);
12483         return 0;
12484 }
12485
12486 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12487                                          struct link_vars *vars,
12488                                          int lfa_status)
12489 {
12490         u32 lfa_sts, cfg_idx, tmp_val;
12491         struct bnx2x *bp = params->bp;
12492
12493         bnx2x_link_reset(params, vars, 1);
12494
12495         if (!params->lfa_base)
12496                 return;
12497         /* Store the new link parameters */
12498         REG_WR(bp, params->lfa_base +
12499                offsetof(struct shmem_lfa, req_duplex),
12500                params->req_duplex[0] | (params->req_duplex[1] << 16));
12501
12502         REG_WR(bp, params->lfa_base +
12503                offsetof(struct shmem_lfa, req_flow_ctrl),
12504                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12505
12506         REG_WR(bp, params->lfa_base +
12507                offsetof(struct shmem_lfa, req_line_speed),
12508                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12509
12510         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12511                 REG_WR(bp, params->lfa_base +
12512                        offsetof(struct shmem_lfa,
12513                                 speed_cap_mask[cfg_idx]),
12514                        params->speed_cap_mask[cfg_idx]);
12515         }
12516
12517         tmp_val = REG_RD(bp, params->lfa_base +
12518                          offsetof(struct shmem_lfa, additional_config));
12519         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12520         tmp_val |= params->req_fc_auto_adv;
12521
12522         REG_WR(bp, params->lfa_base +
12523                offsetof(struct shmem_lfa, additional_config), tmp_val);
12524
12525         lfa_sts = REG_RD(bp, params->lfa_base +
12526                          offsetof(struct shmem_lfa, lfa_sts));
12527
12528         /* Clear the "Don't Clear Statistics" bit, and set reason */
12529         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12530
12531         /* Set link flap reason */
12532         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12533         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12534                     LFA_LINK_FLAP_REASON_OFFSET);
12535
12536         /* Increment link flap counter */
12537         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12538                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12539                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12540                     << LINK_FLAP_COUNT_OFFSET));
12541         REG_WR(bp, params->lfa_base +
12542                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12543         /* Proceed with regular link initialization */
12544 }
12545
12546 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12547 {
12548         int lfa_status;
12549         struct bnx2x *bp = params->bp;
12550         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12551         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12552                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12553         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12554                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12555         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12556         vars->link_status = 0;
12557         vars->phy_link_up = 0;
12558         vars->link_up = 0;
12559         vars->line_speed = 0;
12560         vars->duplex = DUPLEX_FULL;
12561         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12562         vars->mac_type = MAC_TYPE_NONE;
12563         vars->phy_flags = 0;
12564         vars->check_kr2_recovery_cnt = 0;
12565         params->link_flags = PHY_INITIALIZED;
12566         /* Driver opens NIG-BRB filters */
12567         bnx2x_set_rx_filter(params, 1);
12568         /* Check if link flap can be avoided */
12569         lfa_status = bnx2x_check_lfa(params);
12570
12571         if (lfa_status == 0) {
12572                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12573                 return bnx2x_avoid_link_flap(params, vars);
12574         }
12575
12576         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12577                        lfa_status);
12578         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12579
12580         /* Disable attentions */
12581         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12582                        (NIG_MASK_XGXS0_LINK_STATUS |
12583                         NIG_MASK_XGXS0_LINK10G |
12584                         NIG_MASK_SERDES0_LINK_STATUS |
12585                         NIG_MASK_MI_INT));
12586
12587         bnx2x_emac_init(params, vars);
12588
12589         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12590                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12591
12592         if (params->num_phys == 0) {
12593                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12594                 return -EINVAL;
12595         }
12596         set_phy_vars(params, vars);
12597
12598         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12599         switch (params->loopback_mode) {
12600         case LOOPBACK_BMAC:
12601                 bnx2x_init_bmac_loopback(params, vars);
12602                 break;
12603         case LOOPBACK_EMAC:
12604                 bnx2x_init_emac_loopback(params, vars);
12605                 break;
12606         case LOOPBACK_XMAC:
12607                 bnx2x_init_xmac_loopback(params, vars);
12608                 break;
12609         case LOOPBACK_UMAC:
12610                 bnx2x_init_umac_loopback(params, vars);
12611                 break;
12612         case LOOPBACK_XGXS:
12613         case LOOPBACK_EXT_PHY:
12614                 bnx2x_init_xgxs_loopback(params, vars);
12615                 break;
12616         default:
12617                 if (!CHIP_IS_E3(bp)) {
12618                         if (params->switch_cfg == SWITCH_CFG_10G)
12619                                 bnx2x_xgxs_deassert(params);
12620                         else
12621                                 bnx2x_serdes_deassert(bp, params->port);
12622                 }
12623                 bnx2x_link_initialize(params, vars);
12624                 msleep(30);
12625                 bnx2x_link_int_enable(params);
12626                 break;
12627         }
12628         bnx2x_update_mng(params, vars->link_status);
12629
12630         bnx2x_update_mng_eee(params, vars->eee_status);
12631         return 0;
12632 }
12633
12634 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12635                      u8 reset_ext_phy)
12636 {
12637         struct bnx2x *bp = params->bp;
12638         u8 phy_index, port = params->port, clear_latch_ind = 0;
12639         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12640         /* Disable attentions */
12641         vars->link_status = 0;
12642         bnx2x_update_mng(params, vars->link_status);
12643         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12644                               SHMEM_EEE_ACTIVE_BIT);
12645         bnx2x_update_mng_eee(params, vars->eee_status);
12646         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12647                        (NIG_MASK_XGXS0_LINK_STATUS |
12648                         NIG_MASK_XGXS0_LINK10G |
12649                         NIG_MASK_SERDES0_LINK_STATUS |
12650                         NIG_MASK_MI_INT));
12651
12652         /* Activate nig drain */
12653         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12654
12655         /* Disable nig egress interface */
12656         if (!CHIP_IS_E3(bp)) {
12657                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12658                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12659         }
12660
12661                 if (!CHIP_IS_E3(bp)) {
12662                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12663                 } else {
12664                         bnx2x_set_xmac_rxtx(params, 0);
12665                         bnx2x_set_umac_rxtx(params, 0);
12666                 }
12667         /* Disable emac */
12668         if (!CHIP_IS_E3(bp))
12669                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12670
12671         usleep_range(10000, 20000);
12672         /* The PHY reset is controlled by GPIO 1
12673          * Hold it as vars low
12674          */
12675          /* Clear link led */
12676         bnx2x_set_mdio_emac_per_phy(bp, params);
12677         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12678
12679         if (reset_ext_phy) {
12680                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12681                       phy_index++) {
12682                         if (params->phy[phy_index].link_reset) {
12683                                 bnx2x_set_aer_mmd(params,
12684                                                   &params->phy[phy_index]);
12685                                 params->phy[phy_index].link_reset(
12686                                         &params->phy[phy_index],
12687                                         params);
12688                         }
12689                         if (params->phy[phy_index].flags &
12690                             FLAGS_REARM_LATCH_SIGNAL)
12691                                 clear_latch_ind = 1;
12692                 }
12693         }
12694
12695         if (clear_latch_ind) {
12696                 /* Clear latching indication */
12697                 bnx2x_rearm_latch_signal(bp, port, 0);
12698                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12699                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12700         }
12701         if (params->phy[INT_PHY].link_reset)
12702                 params->phy[INT_PHY].link_reset(
12703                         &params->phy[INT_PHY], params);
12704
12705         /* Disable nig ingress interface */
12706         if (!CHIP_IS_E3(bp)) {
12707                 /* Reset BigMac */
12708                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12709                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12710                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12711                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12712         } else {
12713                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12714                 bnx2x_set_xumac_nig(params, 0, 0);
12715                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12716                     MISC_REGISTERS_RESET_REG_2_XMAC)
12717                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12718                                XMAC_CTRL_REG_SOFT_RESET);
12719         }
12720         vars->link_up = 0;
12721         vars->phy_flags = 0;
12722         return 0;
12723 }
12724 int bnx2x_lfa_reset(struct link_params *params,
12725                                struct link_vars *vars)
12726 {
12727         struct bnx2x *bp = params->bp;
12728         vars->link_up = 0;
12729         vars->phy_flags = 0;
12730         params->link_flags &= ~PHY_INITIALIZED;
12731         if (!params->lfa_base)
12732                 return bnx2x_link_reset(params, vars, 1);
12733         /*
12734          * Activate NIG drain so that during this time the device won't send
12735          * anything while it is unable to response.
12736          */
12737         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12738
12739         /*
12740          * Close gracefully the gate from BMAC to NIG such that no half packets
12741          * are passed.
12742          */
12743         if (!CHIP_IS_E3(bp))
12744                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12745
12746         if (CHIP_IS_E3(bp)) {
12747                 bnx2x_set_xmac_rxtx(params, 0);
12748                 bnx2x_set_umac_rxtx(params, 0);
12749         }
12750         /* Wait 10ms for the pipe to clean up*/
12751         usleep_range(10000, 20000);
12752
12753         /* Clean the NIG-BRB using the network filters in a way that will
12754          * not cut a packet in the middle.
12755          */
12756         bnx2x_set_rx_filter(params, 0);
12757
12758         /*
12759          * Re-open the gate between the BMAC and the NIG, after verifying the
12760          * gate to the BRB is closed, otherwise packets may arrive to the
12761          * firmware before driver had initialized it. The target is to achieve
12762          * minimum management protocol down time.
12763          */
12764         if (!CHIP_IS_E3(bp))
12765                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12766
12767         if (CHIP_IS_E3(bp)) {
12768                 bnx2x_set_xmac_rxtx(params, 1);
12769                 bnx2x_set_umac_rxtx(params, 1);
12770         }
12771         /* Disable NIG drain */
12772         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12773         return 0;
12774 }
12775
12776 /****************************************************************************/
12777 /*                              Common function                             */
12778 /****************************************************************************/
12779 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12780                                       u32 shmem_base_path[],
12781                                       u32 shmem2_base_path[], u8 phy_index,
12782                                       u32 chip_id)
12783 {
12784         struct bnx2x_phy phy[PORT_MAX];
12785         struct bnx2x_phy *phy_blk[PORT_MAX];
12786         u16 val;
12787         s8 port = 0;
12788         s8 port_of_path = 0;
12789         u32 swap_val, swap_override;
12790         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12791         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12792         port ^= (swap_val && swap_override);
12793         bnx2x_ext_phy_hw_reset(bp, port);
12794         /* PART1 - Reset both phys */
12795         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12796                 u32 shmem_base, shmem2_base;
12797                 /* In E2, same phy is using for port0 of the two paths */
12798                 if (CHIP_IS_E1x(bp)) {
12799                         shmem_base = shmem_base_path[0];
12800                         shmem2_base = shmem2_base_path[0];
12801                         port_of_path = port;
12802                 } else {
12803                         shmem_base = shmem_base_path[port];
12804                         shmem2_base = shmem2_base_path[port];
12805                         port_of_path = 0;
12806                 }
12807
12808                 /* Extract the ext phy address for the port */
12809                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12810                                        port_of_path, &phy[port]) !=
12811                     0) {
12812                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12813                         return -EINVAL;
12814                 }
12815                 /* Disable attentions */
12816                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12817                                port_of_path*4,
12818                                (NIG_MASK_XGXS0_LINK_STATUS |
12819                                 NIG_MASK_XGXS0_LINK10G |
12820                                 NIG_MASK_SERDES0_LINK_STATUS |
12821                                 NIG_MASK_MI_INT));
12822
12823                 /* Need to take the phy out of low power mode in order
12824                  * to write to access its registers
12825                  */
12826                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12827                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12828                                port);
12829
12830                 /* Reset the phy */
12831                 bnx2x_cl45_write(bp, &phy[port],
12832                                  MDIO_PMA_DEVAD,
12833                                  MDIO_PMA_REG_CTRL,
12834                                  1<<15);
12835         }
12836
12837         /* Add delay of 150ms after reset */
12838         msleep(150);
12839
12840         if (phy[PORT_0].addr & 0x1) {
12841                 phy_blk[PORT_0] = &(phy[PORT_1]);
12842                 phy_blk[PORT_1] = &(phy[PORT_0]);
12843         } else {
12844                 phy_blk[PORT_0] = &(phy[PORT_0]);
12845                 phy_blk[PORT_1] = &(phy[PORT_1]);
12846         }
12847
12848         /* PART2 - Download firmware to both phys */
12849         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12850                 if (CHIP_IS_E1x(bp))
12851                         port_of_path = port;
12852                 else
12853                         port_of_path = 0;
12854
12855                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12856                            phy_blk[port]->addr);
12857                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12858                                                       port_of_path))
12859                         return -EINVAL;
12860
12861                 /* Only set bit 10 = 1 (Tx power down) */
12862                 bnx2x_cl45_read(bp, phy_blk[port],
12863                                 MDIO_PMA_DEVAD,
12864                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12865
12866                 /* Phase1 of TX_POWER_DOWN reset */
12867                 bnx2x_cl45_write(bp, phy_blk[port],
12868                                  MDIO_PMA_DEVAD,
12869                                  MDIO_PMA_REG_TX_POWER_DOWN,
12870                                  (val | 1<<10));
12871         }
12872
12873         /* Toggle Transmitter: Power down and then up with 600ms delay
12874          * between
12875          */
12876         msleep(600);
12877
12878         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12879         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12880                 /* Phase2 of POWER_DOWN_RESET */
12881                 /* Release bit 10 (Release Tx power down) */
12882                 bnx2x_cl45_read(bp, phy_blk[port],
12883                                 MDIO_PMA_DEVAD,
12884                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12885
12886                 bnx2x_cl45_write(bp, phy_blk[port],
12887                                 MDIO_PMA_DEVAD,
12888                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12889                 usleep_range(15000, 30000);
12890
12891                 /* Read modify write the SPI-ROM version select register */
12892                 bnx2x_cl45_read(bp, phy_blk[port],
12893                                 MDIO_PMA_DEVAD,
12894                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12895                 bnx2x_cl45_write(bp, phy_blk[port],
12896                                  MDIO_PMA_DEVAD,
12897                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12898
12899                 /* set GPIO2 back to LOW */
12900                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12901                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12902         }
12903         return 0;
12904 }
12905 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12906                                       u32 shmem_base_path[],
12907                                       u32 shmem2_base_path[], u8 phy_index,
12908                                       u32 chip_id)
12909 {
12910         u32 val;
12911         s8 port;
12912         struct bnx2x_phy phy;
12913         /* Use port1 because of the static port-swap */
12914         /* Enable the module detection interrupt */
12915         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12916         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12917                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12918         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12919
12920         bnx2x_ext_phy_hw_reset(bp, 0);
12921         usleep_range(5000, 10000);
12922         for (port = 0; port < PORT_MAX; port++) {
12923                 u32 shmem_base, shmem2_base;
12924
12925                 /* In E2, same phy is using for port0 of the two paths */
12926                 if (CHIP_IS_E1x(bp)) {
12927                         shmem_base = shmem_base_path[0];
12928                         shmem2_base = shmem2_base_path[0];
12929                 } else {
12930                         shmem_base = shmem_base_path[port];
12931                         shmem2_base = shmem2_base_path[port];
12932                 }
12933                 /* Extract the ext phy address for the port */
12934                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12935                                        port, &phy) !=
12936                     0) {
12937                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12938                         return -EINVAL;
12939                 }
12940
12941                 /* Reset phy*/
12942                 bnx2x_cl45_write(bp, &phy,
12943                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12944
12945
12946                 /* Set fault module detected LED on */
12947                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12948                                MISC_REGISTERS_GPIO_HIGH,
12949                                port);
12950         }
12951
12952         return 0;
12953 }
12954 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12955                                          u8 *io_gpio, u8 *io_port)
12956 {
12957
12958         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12959                                           offsetof(struct shmem_region,
12960                                 dev_info.port_hw_config[PORT_0].default_cfg));
12961         switch (phy_gpio_reset) {
12962         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12963                 *io_gpio = 0;
12964                 *io_port = 0;
12965                 break;
12966         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12967                 *io_gpio = 1;
12968                 *io_port = 0;
12969                 break;
12970         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12971                 *io_gpio = 2;
12972                 *io_port = 0;
12973                 break;
12974         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12975                 *io_gpio = 3;
12976                 *io_port = 0;
12977                 break;
12978         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12979                 *io_gpio = 0;
12980                 *io_port = 1;
12981                 break;
12982         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12983                 *io_gpio = 1;
12984                 *io_port = 1;
12985                 break;
12986         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12987                 *io_gpio = 2;
12988                 *io_port = 1;
12989                 break;
12990         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12991                 *io_gpio = 3;
12992                 *io_port = 1;
12993                 break;
12994         default:
12995                 /* Don't override the io_gpio and io_port */
12996                 break;
12997         }
12998 }
12999
13000 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13001                                       u32 shmem_base_path[],
13002                                       u32 shmem2_base_path[], u8 phy_index,
13003                                       u32 chip_id)
13004 {
13005         s8 port, reset_gpio;
13006         u32 swap_val, swap_override;
13007         struct bnx2x_phy phy[PORT_MAX];
13008         struct bnx2x_phy *phy_blk[PORT_MAX];
13009         s8 port_of_path;
13010         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13011         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13012
13013         reset_gpio = MISC_REGISTERS_GPIO_1;
13014         port = 1;
13015
13016         /* Retrieve the reset gpio/port which control the reset.
13017          * Default is GPIO1, PORT1
13018          */
13019         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13020                                      (u8 *)&reset_gpio, (u8 *)&port);
13021
13022         /* Calculate the port based on port swap */
13023         port ^= (swap_val && swap_override);
13024
13025         /* Initiate PHY reset*/
13026         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13027                        port);
13028         usleep_range(1000, 2000);
13029         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13030                        port);
13031
13032         usleep_range(5000, 10000);
13033
13034         /* PART1 - Reset both phys */
13035         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13036                 u32 shmem_base, shmem2_base;
13037
13038                 /* In E2, same phy is using for port0 of the two paths */
13039                 if (CHIP_IS_E1x(bp)) {
13040                         shmem_base = shmem_base_path[0];
13041                         shmem2_base = shmem2_base_path[0];
13042                         port_of_path = port;
13043                 } else {
13044                         shmem_base = shmem_base_path[port];
13045                         shmem2_base = shmem2_base_path[port];
13046                         port_of_path = 0;
13047                 }
13048
13049                 /* Extract the ext phy address for the port */
13050                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13051                                        port_of_path, &phy[port]) !=
13052                                        0) {
13053                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13054                         return -EINVAL;
13055                 }
13056                 /* disable attentions */
13057                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13058                                port_of_path*4,
13059                                (NIG_MASK_XGXS0_LINK_STATUS |
13060                                 NIG_MASK_XGXS0_LINK10G |
13061                                 NIG_MASK_SERDES0_LINK_STATUS |
13062                                 NIG_MASK_MI_INT));
13063
13064
13065                 /* Reset the phy */
13066                 bnx2x_cl45_write(bp, &phy[port],
13067                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13068         }
13069
13070         /* Add delay of 150ms after reset */
13071         msleep(150);
13072         if (phy[PORT_0].addr & 0x1) {
13073                 phy_blk[PORT_0] = &(phy[PORT_1]);
13074                 phy_blk[PORT_1] = &(phy[PORT_0]);
13075         } else {
13076                 phy_blk[PORT_0] = &(phy[PORT_0]);
13077                 phy_blk[PORT_1] = &(phy[PORT_1]);
13078         }
13079         /* PART2 - Download firmware to both phys */
13080         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13081                 if (CHIP_IS_E1x(bp))
13082                         port_of_path = port;
13083                 else
13084                         port_of_path = 0;
13085                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13086                            phy_blk[port]->addr);
13087                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13088                                                       port_of_path))
13089                         return -EINVAL;
13090                 /* Disable PHY transmitter output */
13091                 bnx2x_cl45_write(bp, phy_blk[port],
13092                                  MDIO_PMA_DEVAD,
13093                                  MDIO_PMA_REG_TX_DISABLE, 1);
13094
13095         }
13096         return 0;
13097 }
13098
13099 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13100                                                 u32 shmem_base_path[],
13101                                                 u32 shmem2_base_path[],
13102                                                 u8 phy_index,
13103                                                 u32 chip_id)
13104 {
13105         u8 reset_gpios;
13106         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13107         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13108         udelay(10);
13109         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13110         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13111                 reset_gpios);
13112         return 0;
13113 }
13114
13115 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13116                                      u32 shmem2_base_path[], u8 phy_index,
13117                                      u32 ext_phy_type, u32 chip_id)
13118 {
13119         int rc = 0;
13120
13121         switch (ext_phy_type) {
13122         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13123                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13124                                                 shmem2_base_path,
13125                                                 phy_index, chip_id);
13126                 break;
13127         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13128         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13129         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13130                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13131                                                 shmem2_base_path,
13132                                                 phy_index, chip_id);
13133                 break;
13134
13135         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13136                 /* GPIO1 affects both ports, so there's need to pull
13137                  * it for single port alone
13138                  */
13139                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13140                                                 shmem2_base_path,
13141                                                 phy_index, chip_id);
13142                 break;
13143         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13144         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13145                 /* GPIO3's are linked, and so both need to be toggled
13146                  * to obtain required 2us pulse.
13147                  */
13148                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13149                                                 shmem2_base_path,
13150                                                 phy_index, chip_id);
13151                 break;
13152         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13153                 rc = -EINVAL;
13154                 break;
13155         default:
13156                 DP(NETIF_MSG_LINK,
13157                            "ext_phy 0x%x common init not required\n",
13158                            ext_phy_type);
13159                 break;
13160         }
13161
13162         if (rc)
13163                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13164                                       " Port %d\n",
13165                          0);
13166         return rc;
13167 }
13168
13169 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13170                           u32 shmem2_base_path[], u32 chip_id)
13171 {
13172         int rc = 0;
13173         u32 phy_ver, val;
13174         u8 phy_index = 0;
13175         u32 ext_phy_type, ext_phy_config;
13176
13177         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13178         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13179         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13180         if (CHIP_IS_E3(bp)) {
13181                 /* Enable EPIO */
13182                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13183                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13184         }
13185         /* Check if common init was already done */
13186         phy_ver = REG_RD(bp, shmem_base_path[0] +
13187                          offsetof(struct shmem_region,
13188                                   port_mb[PORT_0].ext_phy_fw_version));
13189         if (phy_ver) {
13190                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13191                                phy_ver);
13192                 return 0;
13193         }
13194
13195         /* Read the ext_phy_type for arbitrary port(0) */
13196         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13197               phy_index++) {
13198                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13199                                                           shmem_base_path[0],
13200                                                           phy_index, 0);
13201                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13202                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13203                                                 shmem2_base_path,
13204                                                 phy_index, ext_phy_type,
13205                                                 chip_id);
13206         }
13207         return rc;
13208 }
13209
13210 static void bnx2x_check_over_curr(struct link_params *params,
13211                                   struct link_vars *vars)
13212 {
13213         struct bnx2x *bp = params->bp;
13214         u32 cfg_pin;
13215         u8 port = params->port;
13216         u32 pin_val;
13217
13218         cfg_pin = (REG_RD(bp, params->shmem_base +
13219                           offsetof(struct shmem_region,
13220                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13221                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13222                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13223
13224         /* Ignore check if no external input PIN available */
13225         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13226                 return;
13227
13228         if (!pin_val) {
13229                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13230                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13231                                             " been detected and the power to "
13232                                             "that SFP+ module has been removed"
13233                                             " to prevent failure of the card."
13234                                             " Please remove the SFP+ module and"
13235                                             " restart the system to clear this"
13236                                             " error.\n",
13237                          params->port);
13238                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13239                         bnx2x_warpcore_power_module(params, 0);
13240                 }
13241         } else
13242                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13243 }
13244
13245 /* Returns 0 if no change occured since last check; 1 otherwise. */
13246 static u8 bnx2x_analyze_link_error(struct link_params *params,
13247                                     struct link_vars *vars, u32 status,
13248                                     u32 phy_flag, u32 link_flag, u8 notify)
13249 {
13250         struct bnx2x *bp = params->bp;
13251         /* Compare new value with previous value */
13252         u8 led_mode;
13253         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13254
13255         if ((status ^ old_status) == 0)
13256                 return 0;
13257
13258         /* If values differ */
13259         switch (phy_flag) {
13260         case PHY_HALF_OPEN_CONN_FLAG:
13261                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13262                 break;
13263         case PHY_SFP_TX_FAULT_FLAG:
13264                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13265                 break;
13266         default:
13267                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13268         }
13269         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13270            old_status, status);
13271
13272         /* a. Update shmem->link_status accordingly
13273          * b. Update link_vars->link_up
13274          */
13275         if (status) {
13276                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13277                 vars->link_status |= link_flag;
13278                 vars->link_up = 0;
13279                 vars->phy_flags |= phy_flag;
13280
13281                 /* activate nig drain */
13282                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13283                 /* Set LED mode to off since the PHY doesn't know about these
13284                  * errors
13285                  */
13286                 led_mode = LED_MODE_OFF;
13287         } else {
13288                 vars->link_status |= LINK_STATUS_LINK_UP;
13289                 vars->link_status &= ~link_flag;
13290                 vars->link_up = 1;
13291                 vars->phy_flags &= ~phy_flag;
13292                 led_mode = LED_MODE_OPER;
13293
13294                 /* Clear nig drain */
13295                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13296         }
13297         bnx2x_sync_link(params, vars);
13298         /* Update the LED according to the link state */
13299         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13300
13301         /* Update link status in the shared memory */
13302         bnx2x_update_mng(params, vars->link_status);
13303
13304         /* C. Trigger General Attention */
13305         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13306         if (notify)
13307                 bnx2x_notify_link_changed(bp);
13308
13309         return 1;
13310 }
13311
13312 /******************************************************************************
13313 * Description:
13314 *       This function checks for half opened connection change indication.
13315 *       When such change occurs, it calls the bnx2x_analyze_link_error
13316 *       to check if Remote Fault is set or cleared. Reception of remote fault
13317 *       status message in the MAC indicates that the peer's MAC has detected
13318 *       a fault, for example, due to break in the TX side of fiber.
13319 *
13320 ******************************************************************************/
13321 int bnx2x_check_half_open_conn(struct link_params *params,
13322                                 struct link_vars *vars,
13323                                 u8 notify)
13324 {
13325         struct bnx2x *bp = params->bp;
13326         u32 lss_status = 0;
13327         u32 mac_base;
13328         /* In case link status is physically up @ 10G do */
13329         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13330             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13331                 return 0;
13332
13333         if (CHIP_IS_E3(bp) &&
13334             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13335               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13336                 /* Check E3 XMAC */
13337                 /* Note that link speed cannot be queried here, since it may be
13338                  * zero while link is down. In case UMAC is active, LSS will
13339                  * simply not be set
13340                  */
13341                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13342
13343                 /* Clear stick bits (Requires rising edge) */
13344                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13345                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13346                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13347                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13348                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13349                         lss_status = 1;
13350
13351                 bnx2x_analyze_link_error(params, vars, lss_status,
13352                                          PHY_HALF_OPEN_CONN_FLAG,
13353                                          LINK_STATUS_NONE, notify);
13354         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13355                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13356                 /* Check E1X / E2 BMAC */
13357                 u32 lss_status_reg;
13358                 u32 wb_data[2];
13359                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13360                         NIG_REG_INGRESS_BMAC0_MEM;
13361                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13362                 if (CHIP_IS_E2(bp))
13363                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13364                 else
13365                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13366
13367                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13368                 lss_status = (wb_data[0] > 0);
13369
13370                 bnx2x_analyze_link_error(params, vars, lss_status,
13371                                          PHY_HALF_OPEN_CONN_FLAG,
13372                                          LINK_STATUS_NONE, notify);
13373         }
13374         return 0;
13375 }
13376 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13377                                          struct link_params *params,
13378                                          struct link_vars *vars)
13379 {
13380         struct bnx2x *bp = params->bp;
13381         u32 cfg_pin, value = 0;
13382         u8 led_change, port = params->port;
13383
13384         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13385         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13386                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13387                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13388                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13389
13390         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13391                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13392                 return;
13393         }
13394
13395         led_change = bnx2x_analyze_link_error(params, vars, value,
13396                                               PHY_SFP_TX_FAULT_FLAG,
13397                                               LINK_STATUS_SFP_TX_FAULT, 1);
13398
13399         if (led_change) {
13400                 /* Change TX_Fault led, set link status for further syncs */
13401                 u8 led_mode;
13402
13403                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13404                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13405                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13406                 } else {
13407                         led_mode = MISC_REGISTERS_GPIO_LOW;
13408                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13409                 }
13410
13411                 /* If module is unapproved, led should be on regardless */
13412                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13413                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13414                            led_mode);
13415                         bnx2x_set_e3_module_fault_led(params, led_mode);
13416                 }
13417         }
13418 }
13419 static void bnx2x_disable_kr2(struct link_params *params,
13420                               struct link_vars *vars,
13421                               struct bnx2x_phy *phy)
13422 {
13423         struct bnx2x *bp = params->bp;
13424         int i;
13425         static struct bnx2x_reg_set reg_set[] = {
13426                 /* Step 1 - Program the TX/RX alignment markers */
13427                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13428                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13429                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13430                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13431                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13432                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13433                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13434                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13435                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13436                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13437                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13438                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13439                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13440                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13441                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13442         };
13443         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13444
13445         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
13446                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13447                                  reg_set[i].val);
13448         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13449         bnx2x_update_link_attr(params, vars->link_attr_sync);
13450
13451         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
13452         /* Restart AN on leading lane */
13453         bnx2x_warpcore_restart_AN_KR(phy, params);
13454 }
13455
13456 static void bnx2x_kr2_recovery(struct link_params *params,
13457                                struct link_vars *vars,
13458                                struct bnx2x_phy *phy)
13459 {
13460         struct bnx2x *bp = params->bp;
13461         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13462         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13463         bnx2x_warpcore_restart_AN_KR(phy, params);
13464 }
13465
13466 static void bnx2x_check_kr2_wa(struct link_params *params,
13467                                struct link_vars *vars,
13468                                struct bnx2x_phy *phy)
13469 {
13470         struct bnx2x *bp = params->bp;
13471         u16 base_page, next_page, not_kr2_device, lane;
13472         int sigdet;
13473
13474         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13475          * Since some switches tend to reinit the AN process and clear the
13476          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13477          * and recovered many times
13478          */
13479         if (vars->check_kr2_recovery_cnt > 0) {
13480                 vars->check_kr2_recovery_cnt--;
13481                 return;
13482         }
13483
13484         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13485         if (!sigdet) {
13486                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13487                         bnx2x_kr2_recovery(params, vars, phy);
13488                         DP(NETIF_MSG_LINK, "No sigdet\n");
13489                 }
13490                 return;
13491         }
13492
13493         lane = bnx2x_get_warpcore_lane(phy, params);
13494         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13495                           MDIO_AER_BLOCK_AER_REG, lane);
13496         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13497                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13498         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13499                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13500         bnx2x_set_aer_mmd(params, phy);
13501
13502         /* CL73 has not begun yet */
13503         if (base_page == 0) {
13504                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13505                         bnx2x_kr2_recovery(params, vars, phy);
13506                         DP(NETIF_MSG_LINK, "No BP\n");
13507                 }
13508                 return;
13509         }
13510
13511         /* In case NP bit is not set in the BasePage, or it is set,
13512          * but only KX is advertised, declare this link partner as non-KR2
13513          * device.
13514          */
13515         not_kr2_device = (((base_page & 0x8000) == 0) ||
13516                           (((base_page & 0x8000) &&
13517                             ((next_page & 0xe0) == 0x2))));
13518
13519         /* In case KR2 is already disabled, check if we need to re-enable it */
13520         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13521                 if (!not_kr2_device) {
13522                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13523                            next_page);
13524                         bnx2x_kr2_recovery(params, vars, phy);
13525                 }
13526                 return;
13527         }
13528         /* KR2 is enabled, but not KR2 device */
13529         if (not_kr2_device) {
13530                 /* Disable KR2 on both lanes */
13531                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13532                 bnx2x_disable_kr2(params, vars, phy);
13533                 return;
13534         }
13535 }
13536
13537 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13538 {
13539         u16 phy_idx;
13540         struct bnx2x *bp = params->bp;
13541         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13542                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13543                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13544                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13545                             0)
13546                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13547                         break;
13548                 }
13549         }
13550
13551         if (CHIP_IS_E3(bp)) {
13552                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13553                 bnx2x_set_aer_mmd(params, phy);
13554                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13555                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13556                         bnx2x_check_kr2_wa(params, vars, phy);
13557                 bnx2x_check_over_curr(params, vars);
13558                 if (vars->rx_tx_asic_rst)
13559                         bnx2x_warpcore_config_runtime(phy, params, vars);
13560
13561                 if ((REG_RD(bp, params->shmem_base +
13562                             offsetof(struct shmem_region, dev_info.
13563                                 port_hw_config[params->port].default_cfg))
13564                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13565                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13566                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13567                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13568                         } else if (vars->link_status &
13569                                 LINK_STATUS_SFP_TX_FAULT) {
13570                                 /* Clean trail, interrupt corrects the leds */
13571                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13572                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13573                                 /* Update link status in the shared memory */
13574                                 bnx2x_update_mng(params, vars->link_status);
13575                         }
13576                 }
13577         }
13578 }
13579
13580 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13581                              u32 shmem_base,
13582                              u32 shmem2_base,
13583                              u8 port)
13584 {
13585         u8 phy_index, fan_failure_det_req = 0;
13586         struct bnx2x_phy phy;
13587         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13588               phy_index++) {
13589                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13590                                        port, &phy)
13591                     != 0) {
13592                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13593                         return 0;
13594                 }
13595                 fan_failure_det_req |= (phy.flags &
13596                                         FLAGS_FAN_FAILURE_DET_REQ);
13597         }
13598         return fan_failure_det_req;
13599 }
13600
13601 void bnx2x_hw_reset_phy(struct link_params *params)
13602 {
13603         u8 phy_index;
13604         struct bnx2x *bp = params->bp;
13605         bnx2x_update_mng(params, 0);
13606         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13607                        (NIG_MASK_XGXS0_LINK_STATUS |
13608                         NIG_MASK_XGXS0_LINK10G |
13609                         NIG_MASK_SERDES0_LINK_STATUS |
13610                         NIG_MASK_MI_INT));
13611
13612         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13613               phy_index++) {
13614                 if (params->phy[phy_index].hw_reset) {
13615                         params->phy[phy_index].hw_reset(
13616                                 &params->phy[phy_index],
13617                                 params);
13618                         params->phy[phy_index] = phy_null;
13619                 }
13620         }
13621 }
13622
13623 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13624                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13625                             u8 port)
13626 {
13627         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13628         u32 val;
13629         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13630         if (CHIP_IS_E3(bp)) {
13631                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13632                                               shmem_base,
13633                                               port,
13634                                               &gpio_num,
13635                                               &gpio_port) != 0)
13636                         return;
13637         } else {
13638                 struct bnx2x_phy phy;
13639                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13640                       phy_index++) {
13641                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13642                                                shmem2_base, port, &phy)
13643                             != 0) {
13644                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13645                                 return;
13646                         }
13647                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13648                                 gpio_num = MISC_REGISTERS_GPIO_3;
13649                                 gpio_port = port;
13650                                 break;
13651                         }
13652                 }
13653         }
13654
13655         if (gpio_num == 0xff)
13656                 return;
13657
13658         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13659         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13660
13661         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13662         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13663         gpio_port ^= (swap_val && swap_override);
13664
13665         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13666                 (gpio_num + (gpio_port << 2));
13667
13668         sync_offset = shmem_base +
13669                 offsetof(struct shmem_region,
13670                          dev_info.port_hw_config[port].aeu_int_mask);
13671         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13672
13673         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13674                        gpio_num, gpio_port, vars->aeu_int_mask);
13675
13676         if (port == 0)
13677                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13678         else
13679                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13680
13681         /* Open appropriate AEU for interrupts */
13682         aeu_mask = REG_RD(bp, offset);
13683         aeu_mask |= vars->aeu_int_mask;
13684         REG_WR(bp, offset, aeu_mask);
13685
13686         /* Enable the GPIO to trigger interrupt */
13687         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13688         val |= 1 << (gpio_num + (gpio_port << 2));
13689         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13690 }