drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 /********************************************************/
  31 #define ETH_HLEN                        14
  32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  33 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  34 #define ETH_MIN_PACKET_SIZE             60
  35 #define ETH_MAX_PACKET_SIZE             1500
  36 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  44 #define MCPR_IMC_COMMAND_READ_OP        1
  45 #define MCPR_IMC_COMMAND_WRITE_OP       2
  46
  47 /* LED Blink rate that will achieve ~15.9Hz */
  48 #define LED_BLINK_RATE_VAL_E3           354
  49 #define LED_BLINK_RATE_VAL_E1X_E2       480
  50 /***********************************************************/
  51 /*                      Shortcut definitions               */
  52 /***********************************************************/
  53
  54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  55
  56 #define NIG_STATUS_EMAC0_MI_INT \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  58 #define NIG_STATUS_XGXS0_LINK10G \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  60 #define NIG_STATUS_XGXS0_LINK_STATUS \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  64 #define NIG_STATUS_SERDES0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  66 #define NIG_MASK_MI_INT \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  68 #define NIG_MASK_XGXS0_LINK10G \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  70 #define NIG_MASK_XGXS0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  72 #define NIG_MASK_SERDES0_LINK_STATUS \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  74
  75 #define MDIO_AN_CL73_OR_37_COMPLETE \
  76                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  77                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  78
  79 #define XGXS_RESET_BITS \
  80         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  84          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  85
  86 #define SERDES_RESET_BITS \
  87         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  90          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  91
  92 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  93 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  94 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  95 #define AUTONEG_PARALLEL \
  96                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  97 #define AUTONEG_SGMII_FIBER_AUTODET \
  98                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  99 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 100
 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 105 #define GP_STATUS_SPEED_MASK \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 107 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 108 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 109 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 110 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 111 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 112 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 113 #define GP_STATUS_10G_HIG \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 115 #define GP_STATUS_10G_CX4 \
 116                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 118 #define GP_STATUS_10G_KX4 \
 119                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 121 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 123 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 124 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 125 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 126 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 127 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 128 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 129 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 130 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 131 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 132 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 133 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 134 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 135 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 136 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 137 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 138 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 139 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 140
 141 #define LINK_UPDATE_MASK \
 142                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 143                          LINK_STATUS_LINK_UP | \
 144                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 145                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 146                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 147                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 148                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 149                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 150                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 151
 152 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 153         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 154         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 155
 156
 157 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 158         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 159         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 160         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 161
 162 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 163         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 164         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 165
 166 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 167         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 168 #define SFP_EEPROM_OPTIONS_SIZE                 2
 169
 170 #define EDC_MODE_LINEAR                         0x0022
 171 #define EDC_MODE_LIMITING                               0x0044
 172 #define EDC_MODE_PASSIVE_DAC                    0x0055
 173
 174 /* ETS defines*/
 175 #define DCBX_INVALID_COS                                        (0xFF)
 176
 177 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 178 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 179 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 180 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 181 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 182
 183 #define MAX_PACKET_SIZE                                 (9700)
 184 #define MAX_KR_LINK_RETRY                               4
 185
 186 /**********************************************************/
 187 /*                     INTERFACE                          */
 188 /**********************************************************/
 189
 190 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 191         bnx2x_cl45_write(_bp, _phy, \
 192                 (_phy)->def_md_devad, \
 193                 (_bank + (_addr & 0xf)), \
 194                 _val)
 195
 196 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 197         bnx2x_cl45_read(_bp, _phy, \
 198                 (_phy)->def_md_devad, \
 199                 (_bank + (_addr & 0xf)), \
 200                 _val)
 201
 202 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 203 {
 204         u32 val = REG_RD(bp, reg);
 205
 206         val |= bits;
 207         REG_WR(bp, reg, val);
 208         return val;
 209 }
 210
 211 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 212 {
 213         u32 val = REG_RD(bp, reg);
 214
 215         val &= ~bits;
 216         REG_WR(bp, reg, val);
 217         return val;
 218 }
 219
 220 /*
 221  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 222  *                   or link flap can be avoided.
 223  *
 224  * @params:     link parameters
 225  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 226  *         condition code.
 227  */
 228 static int bnx2x_check_lfa(struct link_params *params)
 229 {
 230         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 231         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 232         u32 saved_val, req_val, eee_status;
 233         struct bnx2x *bp = params->bp;
 234
 235         additional_config =
 236                 REG_RD(bp, params->lfa_base +
 237                            offsetof(struct shmem_lfa, additional_config));
 238
 239         /* NOTE: must be first condition checked -
 240         * to verify DCC bit is cleared in any case!
 241         */
 242         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 243                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 244                 REG_WR(bp, params->lfa_base +
 245                            offsetof(struct shmem_lfa, additional_config),
 246                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 247                 return LFA_DCC_LFA_DISABLED;
 248         }
 249
 250         /* Verify that link is up */
 251         link_status = REG_RD(bp, params->shmem_base +
 252                              offsetof(struct shmem_region,
 253                                       port_mb[params->port].link_status));
 254         if (!(link_status & LINK_STATUS_LINK_UP))
 255                 return LFA_LINK_DOWN;
 256
 257         /* if loaded after BOOT from SAN, don't flap the link in any case and
 258          * rely on link set by preboot driver
 259          */
 260         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 261                 return 0;
 262
 263         /* Verify that loopback mode is not set */
 264         if (params->loopback_mode)
 265                 return LFA_LOOPBACK_ENABLED;
 266
 267         /* Verify that MFW supports LFA */
 268         if (!params->lfa_base)
 269                 return LFA_MFW_IS_TOO_OLD;
 270
 271         if (params->num_phys == 3) {
 272                 cfg_size = 2;
 273                 lfa_mask = 0xffffffff;
 274         } else {
 275                 cfg_size = 1;
 276                 lfa_mask = 0xffff;
 277         }
 278
 279         /* Compare Duplex */
 280         saved_val = REG_RD(bp, params->lfa_base +
 281                            offsetof(struct shmem_lfa, req_duplex));
 282         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 283         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 284                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 285                                (saved_val & lfa_mask), (req_val & lfa_mask));
 286                 return LFA_DUPLEX_MISMATCH;
 287         }
 288         /* Compare Flow Control */
 289         saved_val = REG_RD(bp, params->lfa_base +
 290                            offsetof(struct shmem_lfa, req_flow_ctrl));
 291         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 292         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 293                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 294                                (saved_val & lfa_mask), (req_val & lfa_mask));
 295                 return LFA_FLOW_CTRL_MISMATCH;
 296         }
 297         /* Compare Link Speed */
 298         saved_val = REG_RD(bp, params->lfa_base +
 299                            offsetof(struct shmem_lfa, req_line_speed));
 300         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 301         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 302                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 303                                (saved_val & lfa_mask), (req_val & lfa_mask));
 304                 return LFA_LINK_SPEED_MISMATCH;
 305         }
 306
 307         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 308                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 309                                             offsetof(struct shmem_lfa,
 310                                                      speed_cap_mask[cfg_idx]));
 311
 312                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 313                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 314                                        cur_speed_cap_mask,
 315                                        params->speed_cap_mask[cfg_idx]);
 316                         return LFA_SPEED_CAP_MISMATCH;
 317                 }
 318         }
 319
 320         cur_req_fc_auto_adv =
 321                 REG_RD(bp, params->lfa_base +
 322                        offsetof(struct shmem_lfa, additional_config)) &
 323                 REQ_FC_AUTO_ADV_MASK;
 324
 325         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 326                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 327                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 328                 return LFA_FLOW_CTRL_MISMATCH;
 329         }
 330
 331         eee_status = REG_RD(bp, params->shmem2_base +
 332                             offsetof(struct shmem2_region,
 333                                      eee_status[params->port]));
 334
 335         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 336              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 337             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 338              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 339                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 340                                eee_status);
 341                 return LFA_EEE_MISMATCH;
 342         }
 343
 344         /* LFA conditions are met */
 345         return 0;
 346 }
 347 /******************************************************************/
 348 /*                      EPIO/GPIO section                         */
 349 /******************************************************************/
 350 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 351 {
 352         u32 epio_mask, gp_oenable;
 353         *en = 0;
 354         /* Sanity check */
 355         if (epio_pin > 31) {
 356                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 357                 return;
 358         }
 359
 360         epio_mask = 1 << epio_pin;
 361         /* Set this EPIO to output */
 362         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 363         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 364
 365         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 366 }
 367 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 368 {
 369         u32 epio_mask, gp_output, gp_oenable;
 370
 371         /* Sanity check */
 372         if (epio_pin > 31) {
 373                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 374                 return;
 375         }
 376         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 377         epio_mask = 1 << epio_pin;
 378         /* Set this EPIO to output */
 379         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 380         if (en)
 381                 gp_output |= epio_mask;
 382         else
 383                 gp_output &= ~epio_mask;
 384
 385         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 386
 387         /* Set the value for this EPIO */
 388         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 389         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 390 }
 391
 392 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 393 {
 394         if (pin_cfg == PIN_CFG_NA)
 395                 return;
 396         if (pin_cfg >= PIN_CFG_EPIO0) {
 397                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 398         } else {
 399                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 400                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 401                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 402         }
 403 }
 404
 405 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 406 {
 407         if (pin_cfg == PIN_CFG_NA)
 408                 return -EINVAL;
 409         if (pin_cfg >= PIN_CFG_EPIO0) {
 410                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 411         } else {
 412                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 413                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 414                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 415         }
 416         return 0;
 417
 418 }
 419 /******************************************************************/
 420 /*                              ETS section                       */
 421 /******************************************************************/
 422 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 423 {
 424         /* ETS disabled configuration*/
 425         struct bnx2x *bp = params->bp;
 426
 427         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 428
 429         /* mapping between entry  priority to client number (0,1,2 -debug and
 430          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 431          * 3bits client num.
 432          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 433          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 434          */
 435
 436         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 437         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 438          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 439          * COS0 entry, 4 - COS1 entry.
 440          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 441          * bit4   bit3    bit2   bit1     bit0
 442          * MCP and debug are strict
 443          */
 444
 445         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 446         /* defines which entries (clients) are subjected to WFQ arbitration */
 447         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 448         /* For strict priority entries defines the number of consecutive
 449          * slots for the highest priority.
 450          */
 451         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 452         /* mapping between the CREDIT_WEIGHT registers and actual client
 453          * numbers
 454          */
 455         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 456         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 457         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 458
 459         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 460         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 461         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 462         /* ETS mode disable */
 463         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 464         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 465          * weight for COS0/COS1.
 466          */
 467         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 468         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 469         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 470         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 471         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 472         /* Defines the number of consecutive slots for the strict priority */
 473         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 474 }
 475 /******************************************************************************
 476 * Description:
 477 *       Getting min_w_val will be set according to line speed .
 478 *.
 479 ******************************************************************************/
 480 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 481 {
 482         u32 min_w_val = 0;
 483         /* Calculate min_w_val.*/
 484         if (vars->link_up) {
 485                 if (vars->line_speed == SPEED_20000)
 486                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 487                 else
 488                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 489         } else
 490                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 491         /* If the link isn't up (static configuration for example ) The
 492          * link will be according to 20GBPS.
 493          */
 494         return min_w_val;
 495 }
 496 /******************************************************************************
 497 * Description:
 498 *       Getting credit upper bound form min_w_val.
 499 *.
 500 ******************************************************************************/
 501 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 502 {
 503         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 504                                                 MAX_PACKET_SIZE);
 505         return credit_upper_bound;
 506 }
 507 /******************************************************************************
 508 * Description:
 509 *       Set credit upper bound for NIG.
 510 *.
 511 ******************************************************************************/
 512 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 513         const struct link_params *params,
 514         const u32 min_w_val)
 515 {
 516         struct bnx2x *bp = params->bp;
 517         const u8 port = params->port;
 518         const u32 credit_upper_bound =
 519             bnx2x_ets_get_credit_upper_bound(min_w_val);
 520
 521         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 522                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 523         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 524                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 525         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 526                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 527         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 528                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 529         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 530                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 531         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 532                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 533
 534         if (!port) {
 535                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 536                         credit_upper_bound);
 537                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 538                         credit_upper_bound);
 539                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 540                         credit_upper_bound);
 541         }
 542 }
 543 /******************************************************************************
 544 * Description:
 545 *       Will return the NIG ETS registers to init values.Except
 546 *       credit_upper_bound.
 547 *       That isn't used in this configuration (No WFQ is enabled) and will be
 548 *       configured acording to spec
 549 *.
 550 ******************************************************************************/
 551 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 552                                         const struct link_vars *vars)
 553 {
 554         struct bnx2x *bp = params->bp;
 555         const u8 port = params->port;
 556         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 557         /* Mapping between entry  priority to client number (0,1,2 -debug and
 558          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 559          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 560          * reset value or init tool
 561          */
 562         if (port) {
 563                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 564                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 565         } else {
 566                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 567                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 568         }
 569         /* For strict priority entries defines the number of consecutive
 570          * slots for the highest priority.
 571          */
 572         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 573                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 574         /* Mapping between the CREDIT_WEIGHT registers and actual client
 575          * numbers
 576          */
 577         if (port) {
 578                 /*Port 1 has 6 COS*/
 579                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 580                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 581         } else {
 582                 /*Port 0 has 9 COS*/
 583                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 584                        0x43210876);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 586         }
 587
 588         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 589          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 590          * COS0 entry, 4 - COS1 entry.
 591          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 592          * bit4   bit3    bit2   bit1     bit0
 593          * MCP and debug are strict
 594          */
 595         if (port)
 596                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 597         else
 598                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 599         /* defines which entries (clients) are subjected to WFQ arbitration */
 600         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 601                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 602
 603         /* Please notice the register address are note continuous and a
 604          * for here is note appropriate.In 2 port mode port0 only COS0-5
 605          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 606          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 607          * are never used for WFQ
 608          */
 609         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 610                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 611         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 612                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 613         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 614                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 615         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 616                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 617         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 618                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 619         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 620                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 621         if (!port) {
 622                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 623                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 624                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 625         }
 626
 627         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 628 }
 629 /******************************************************************************
 630 * Description:
 631 *       Set credit upper bound for PBF.
 632 *.
 633 ******************************************************************************/
 634 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 635         const struct link_params *params,
 636         const u32 min_w_val)
 637 {
 638         struct bnx2x *bp = params->bp;
 639         const u32 credit_upper_bound =
 640             bnx2x_ets_get_credit_upper_bound(min_w_val);
 641         const u8 port = params->port;
 642         u32 base_upper_bound = 0;
 643         u8 max_cos = 0;
 644         u8 i = 0;
 645         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 646          * port mode port1 has COS0-2 that can be used for WFQ.
 647          */
 648         if (!port) {
 649                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 650                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 651         } else {
 652                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 653                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 654         }
 655
 656         for (i = 0; i < max_cos; i++)
 657                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 658 }
 659
 660 /******************************************************************************
 661 * Description:
 662 *       Will return the PBF ETS registers to init values.Except
 663 *       credit_upper_bound.
 664 *       That isn't used in this configuration (No WFQ is enabled) and will be
 665 *       configured acording to spec
 666 *.
 667 ******************************************************************************/
 668 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 669 {
 670         struct bnx2x *bp = params->bp;
 671         const u8 port = params->port;
 672         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 673         u8 i = 0;
 674         u32 base_weight = 0;
 675         u8 max_cos = 0;
 676
 677         /* Mapping between entry  priority to client number 0 - COS0
 678          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 679          * TODO_ETS - Should be done by reset value or init tool
 680          */
 681         if (port)
 682                 /*  0x688 (|011|0 10|00 1|000) */
 683                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 684         else
 685                 /*  (10 1|100 |011|0 10|00 1|000) */
 686                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 687
 688         /* TODO_ETS - Should be done by reset value or init tool */
 689         if (port)
 690                 /* 0x688 (|011|0 10|00 1|000)*/
 691                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 692         else
 693         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 694         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 695
 696         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 697                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 698
 699
 700         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 701                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 702
 703         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 704                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 705         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 706          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 707          */
 708         if (!port) {
 709                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 710                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 711         } else {
 712                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 713                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 714         }
 715
 716         for (i = 0; i < max_cos; i++)
 717                 REG_WR(bp, base_weight + (0x4 * i), 0);
 718
 719         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 720 }
 721 /******************************************************************************
 722 * Description:
 723 *       E3B0 disable will return basicly the values to init values.
 724 *.
 725 ******************************************************************************/
 726 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 727                                    const struct link_vars *vars)
 728 {
 729         struct bnx2x *bp = params->bp;
 730
 731         if (!CHIP_IS_E3B0(bp)) {
 732                 DP(NETIF_MSG_LINK,
 733                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 734                 return -EINVAL;
 735         }
 736
 737         bnx2x_ets_e3b0_nig_disabled(params, vars);
 738
 739         bnx2x_ets_e3b0_pbf_disabled(params);
 740
 741         return 0;
 742 }
 743
 744 /******************************************************************************
 745 * Description:
 746 *       Disable will return basicly the values to init values.
 747 *
 748 ******************************************************************************/
 749 int bnx2x_ets_disabled(struct link_params *params,
 750                       struct link_vars *vars)
 751 {
 752         struct bnx2x *bp = params->bp;
 753         int bnx2x_status = 0;
 754
 755         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 756                 bnx2x_ets_e2e3a0_disabled(params);
 757         else if (CHIP_IS_E3B0(bp))
 758                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 759         else {
 760                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 761                 return -EINVAL;
 762         }
 763
 764         return bnx2x_status;
 765 }
 766
 767 /******************************************************************************
 768 * Description
 769 *       Set the COS mappimg to SP and BW until this point all the COS are not
 770 *       set as SP or BW.
 771 ******************************************************************************/
 772 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 773                                   const struct bnx2x_ets_params *ets_params,
 774                                   const u8 cos_sp_bitmap,
 775                                   const u8 cos_bw_bitmap)
 776 {
 777         struct bnx2x *bp = params->bp;
 778         const u8 port = params->port;
 779         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 780         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 781         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 782         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 783
 784         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 785                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 786
 787         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 788                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 789
 790         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 791                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 792                nig_cli_subject2wfq_bitmap);
 793
 794         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 795                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 796                pbf_cli_subject2wfq_bitmap);
 797
 798         return 0;
 799 }
 800
 801 /******************************************************************************
 802 * Description:
 803 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 804 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 805 ******************************************************************************/
 806 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 807                                      const u8 cos_entry,
 808                                      const u32 min_w_val_nig,
 809                                      const u32 min_w_val_pbf,
 810                                      const u16 total_bw,
 811                                      const u8 bw,
 812                                      const u8 port)
 813 {
 814         u32 nig_reg_adress_crd_weight = 0;
 815         u32 pbf_reg_adress_crd_weight = 0;
 816         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 817         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 818         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 819
 820         switch (cos_entry) {
 821         case 0:
 822             nig_reg_adress_crd_weight =
 823                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 824                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 825              pbf_reg_adress_crd_weight = (port) ?
 826                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 827              break;
 828         case 1:
 829              nig_reg_adress_crd_weight = (port) ?
 830                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 831                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 832              pbf_reg_adress_crd_weight = (port) ?
 833                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 834              break;
 835         case 2:
 836              nig_reg_adress_crd_weight = (port) ?
 837                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 838                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 839
 840                  pbf_reg_adress_crd_weight = (port) ?
 841                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 842              break;
 843         case 3:
 844             if (port)
 845                         return -EINVAL;
 846              nig_reg_adress_crd_weight =
 847                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 848              pbf_reg_adress_crd_weight =
 849                  PBF_REG_COS3_WEIGHT_P0;
 850              break;
 851         case 4:
 852             if (port)
 853                 return -EINVAL;
 854              nig_reg_adress_crd_weight =
 855                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 856              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 857              break;
 858         case 5:
 859             if (port)
 860                 return -EINVAL;
 861              nig_reg_adress_crd_weight =
 862                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 863              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 864              break;
 865         }
 866
 867         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 868
 869         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 870
 871         return 0;
 872 }
 873 /******************************************************************************
 874 * Description:
 875 *       Calculate the total BW.A value of 0 isn't legal.
 876 *
 877 ******************************************************************************/
 878 static int bnx2x_ets_e3b0_get_total_bw(
 879         const struct link_params *params,
 880         struct bnx2x_ets_params *ets_params,
 881         u16 *total_bw)
 882 {
 883         struct bnx2x *bp = params->bp;
 884         u8 cos_idx = 0;
 885         u8 is_bw_cos_exist = 0;
 886
 887         *total_bw = 0 ;
 888         /* Calculate total BW requested */
 889         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 890                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 891                         is_bw_cos_exist = 1;
 892                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 893                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 894                                                    "was set to 0\n");
 895                                 /* This is to prevent a state when ramrods
 896                                  * can't be sent
 897                                  */
 898                                 ets_params->cos[cos_idx].params.bw_params.bw
 899                                          = 1;
 900                         }
 901                         *total_bw +=
 902                                 ets_params->cos[cos_idx].params.bw_params.bw;
 903                 }
 904         }
 905
 906         /* Check total BW is valid */
 907         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 908                 if (*total_bw == 0) {
 909                         DP(NETIF_MSG_LINK,
 910                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 911                         return -EINVAL;
 912                 }
 913                 DP(NETIF_MSG_LINK,
 914                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 915                 /* We can handle a case whre the BW isn't 100 this can happen
 916                  * if the TC are joined.
 917                  */
 918         }
 919         return 0;
 920 }
 921
 922 /******************************************************************************
 923 * Description:
 924 *       Invalidate all the sp_pri_to_cos.
 925 *
 926 ******************************************************************************/
 927 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 928 {
 929         u8 pri = 0;
 930         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 931                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 932 }
 933 /******************************************************************************
 934 * Description:
 935 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 936 *       according to sp_pri_to_cos.
 937 *
 938 ******************************************************************************/
 939 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 940                                             u8 *sp_pri_to_cos, const u8 pri,
 941                                             const u8 cos_entry)
 942 {
 943         struct bnx2x *bp = params->bp;
 944         const u8 port = params->port;
 945         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 946                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 947
 948         if (pri >= max_num_of_cos) {
 949                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 950                    "parameter Illegal strict priority\n");
 951             return -EINVAL;
 952         }
 953
 954         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 955                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 956                                    "parameter There can't be two COS's with "
 957                                    "the same strict pri\n");
 958                 return -EINVAL;
 959         }
 960
 961         sp_pri_to_cos[pri] = cos_entry;
 962         return 0;
 963
 964 }
 965
 966 /******************************************************************************
 967 * Description:
 968 *       Returns the correct value according to COS and priority in
 969 *       the sp_pri_cli register.
 970 *
 971 ******************************************************************************/
 972 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 973                                          const u8 pri_set,
 974                                          const u8 pri_offset,
 975                                          const u8 entry_size)
 976 {
 977         u64 pri_cli_nig = 0;
 978         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 979                                                     (pri_set + pri_offset));
 980
 981         return pri_cli_nig;
 982 }
 983 /******************************************************************************
 984 * Description:
 985 *       Returns the correct value according to COS and priority in the
 986 *       sp_pri_cli register for NIG.
 987 *
 988 ******************************************************************************/
 989 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 990 {
 991         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 992         const u8 nig_cos_offset = 3;
 993         const u8 nig_pri_offset = 3;
 994
 995         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 996                 nig_pri_offset, 4);
 997
 998 }
 999 /******************************************************************************
1000 * Description:
1001 *       Returns the correct value according to COS and priority in the
1002 *       sp_pri_cli register for PBF.
1003 *
1004 ******************************************************************************/
1005 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1006 {
1007         const u8 pbf_cos_offset = 0;
1008         const u8 pbf_pri_offset = 0;
1009
1010         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1011                 pbf_pri_offset, 3);
1012
1013 }
1014
1015 /******************************************************************************
1016 * Description:
1017 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1018 *       according to sp_pri_to_cos.(which COS has higher priority)
1019 *
1020 ******************************************************************************/
1021 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1022                                              u8 *sp_pri_to_cos)
1023 {
1024         struct bnx2x *bp = params->bp;
1025         u8 i = 0;
1026         const u8 port = params->port;
1027         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1028         u64 pri_cli_nig = 0x210;
1029         u32 pri_cli_pbf = 0x0;
1030         u8 pri_set = 0;
1031         u8 pri_bitmask = 0;
1032         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1033                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1034
1035         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1036
1037         /* Set all the strict priority first */
1038         for (i = 0; i < max_num_of_cos; i++) {
1039                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1040                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1041                                 DP(NETIF_MSG_LINK,
1042                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1043                                            "invalid cos entry\n");
1044                                 return -EINVAL;
1045                         }
1046
1047                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1048                             sp_pri_to_cos[i], pri_set);
1049
1050                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1051                             sp_pri_to_cos[i], pri_set);
1052                         pri_bitmask = 1 << sp_pri_to_cos[i];
1053                         /* COS is used remove it from bitmap.*/
1054                         if (!(pri_bitmask & cos_bit_to_set)) {
1055                                 DP(NETIF_MSG_LINK,
1056                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1057                                         "invalid There can't be two COS's with"
1058                                         " the same strict pri\n");
1059                                 return -EINVAL;
1060                         }
1061                         cos_bit_to_set &= ~pri_bitmask;
1062                         pri_set++;
1063                 }
1064         }
1065
1066         /* Set all the Non strict priority i= COS*/
1067         for (i = 0; i < max_num_of_cos; i++) {
1068                 pri_bitmask = 1 << i;
1069                 /* Check if COS was already used for SP */
1070                 if (pri_bitmask & cos_bit_to_set) {
1071                         /* COS wasn't used for SP */
1072                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1073                             i, pri_set);
1074
1075                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1076                             i, pri_set);
1077                         /* COS is used remove it from bitmap.*/
1078                         cos_bit_to_set &= ~pri_bitmask;
1079                         pri_set++;
1080                 }
1081         }
1082
1083         if (pri_set != max_num_of_cos) {
1084                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1085                                    "entries were set\n");
1086                 return -EINVAL;
1087         }
1088
1089         if (port) {
1090                 /* Only 6 usable clients*/
1091                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1092                        (u32)pri_cli_nig);
1093
1094                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1095         } else {
1096                 /* Only 9 usable clients*/
1097                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1098                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1099
1100                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1101                        pri_cli_nig_lsb);
1102                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1103                        pri_cli_nig_msb);
1104
1105                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1106         }
1107         return 0;
1108 }
1109
1110 /******************************************************************************
1111 * Description:
1112 *       Configure the COS to ETS according to BW and SP settings.
1113 ******************************************************************************/
1114 int bnx2x_ets_e3b0_config(const struct link_params *params,
1115                          const struct link_vars *vars,
1116                          struct bnx2x_ets_params *ets_params)
1117 {
1118         struct bnx2x *bp = params->bp;
1119         int bnx2x_status = 0;
1120         const u8 port = params->port;
1121         u16 total_bw = 0;
1122         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1123         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1124         u8 cos_bw_bitmap = 0;
1125         u8 cos_sp_bitmap = 0;
1126         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1127         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1128                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1129         u8 cos_entry = 0;
1130
1131         if (!CHIP_IS_E3B0(bp)) {
1132                 DP(NETIF_MSG_LINK,
1133                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1134                 return -EINVAL;
1135         }
1136
1137         if ((ets_params->num_of_cos > max_num_of_cos)) {
1138                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1139                                    "isn't supported\n");
1140                 return -EINVAL;
1141         }
1142
1143         /* Prepare sp strict priority parameters*/
1144         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1145
1146         /* Prepare BW parameters*/
1147         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1148                                                    &total_bw);
1149         if (bnx2x_status) {
1150                 DP(NETIF_MSG_LINK,
1151                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1152                 return -EINVAL;
1153         }
1154
1155         /* Upper bound is set according to current link speed (min_w_val
1156          * should be the same for upper bound and COS credit val).
1157          */
1158         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1159         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1160
1161
1162         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1163                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1164                         cos_bw_bitmap |= (1 << cos_entry);
1165                         /* The function also sets the BW in HW(not the mappin
1166                          * yet)
1167                          */
1168                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1169                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1170                                 total_bw,
1171                                 ets_params->cos[cos_entry].params.bw_params.bw,
1172                                  port);
1173                 } else if (bnx2x_cos_state_strict ==
1174                         ets_params->cos[cos_entry].state){
1175                         cos_sp_bitmap |= (1 << cos_entry);
1176
1177                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1178                                 params,
1179                                 sp_pri_to_cos,
1180                                 ets_params->cos[cos_entry].params.sp_params.pri,
1181                                 cos_entry);
1182
1183                 } else {
1184                         DP(NETIF_MSG_LINK,
1185                            "bnx2x_ets_e3b0_config cos state not valid\n");
1186                         return -EINVAL;
1187                 }
1188                 if (bnx2x_status) {
1189                         DP(NETIF_MSG_LINK,
1190                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1191                         return bnx2x_status;
1192                 }
1193         }
1194
1195         /* Set SP register (which COS has higher priority) */
1196         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1197                                                          sp_pri_to_cos);
1198
1199         if (bnx2x_status) {
1200                 DP(NETIF_MSG_LINK,
1201                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1202                 return bnx2x_status;
1203         }
1204
1205         /* Set client mapping of BW and strict */
1206         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1207                                               cos_sp_bitmap,
1208                                               cos_bw_bitmap);
1209
1210         if (bnx2x_status) {
1211                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1212                 return bnx2x_status;
1213         }
1214         return 0;
1215 }
1216 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1217 {
1218         /* ETS disabled configuration */
1219         struct bnx2x *bp = params->bp;
1220         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1221         /* Defines which entries (clients) are subjected to WFQ arbitration
1222          * COS0 0x8
1223          * COS1 0x10
1224          */
1225         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1226         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1227          * client numbers (WEIGHT_0 does not actually have to represent
1228          * client 0)
1229          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1230          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1231          */
1232         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1233
1234         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1235                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1236         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1237                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1238
1239         /* ETS mode enabled*/
1240         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1241
1242         /* Defines the number of consecutive slots for the strict priority */
1243         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1244         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1245          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1246          * entry, 4 - COS1 entry.
1247          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1248          * bit4   bit3    bit2     bit1    bit0
1249          * MCP and debug are strict
1250          */
1251         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1252
1253         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1254         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1255                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1256         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1257                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1258 }
1259
1260 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1261                         const u32 cos1_bw)
1262 {
1263         /* ETS disabled configuration*/
1264         struct bnx2x *bp = params->bp;
1265         const u32 total_bw = cos0_bw + cos1_bw;
1266         u32 cos0_credit_weight = 0;
1267         u32 cos1_credit_weight = 0;
1268
1269         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1270
1271         if ((!total_bw) ||
1272             (!cos0_bw) ||
1273             (!cos1_bw)) {
1274                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1275                 return;
1276         }
1277
1278         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1279                 total_bw;
1280         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1281                 total_bw;
1282
1283         bnx2x_ets_bw_limit_common(params);
1284
1285         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1286         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1287
1288         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1289         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1290 }
1291
1292 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1293 {
1294         /* ETS disabled configuration*/
1295         struct bnx2x *bp = params->bp;
1296         u32 val = 0;
1297
1298         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1299         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1300          * as strict.  Bits 0,1,2 - debug and management entries,
1301          * 3 - COS0 entry, 4 - COS1 entry.
1302          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1303          *  bit4   bit3   bit2      bit1     bit0
1304          * MCP and debug are strict
1305          */
1306         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1307         /* For strict priority entries defines the number of consecutive slots
1308          * for the highest priority.
1309          */
1310         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1311         /* ETS mode disable */
1312         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1313         /* Defines the number of consecutive slots for the strict priority */
1314         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1315
1316         /* Defines the number of consecutive slots for the strict priority */
1317         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1318
1319         /* Mapping between entry  priority to client number (0,1,2 -debug and
1320          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1321          * 3bits client num.
1322          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1323          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1324          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1325          */
1326         val = (!strict_cos) ? 0x2318 : 0x22E0;
1327         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1328
1329         return 0;
1330 }
1331
1332 /******************************************************************/
1333 /*                      PFC section                               */
1334 /******************************************************************/
1335 static void bnx2x_update_pfc_xmac(struct link_params *params,
1336                                   struct link_vars *vars,
1337                                   u8 is_lb)
1338 {
1339         struct bnx2x *bp = params->bp;
1340         u32 xmac_base;
1341         u32 pause_val, pfc0_val, pfc1_val;
1342
1343         /* XMAC base adrr */
1344         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1345
1346         /* Initialize pause and pfc registers */
1347         pause_val = 0x18000;
1348         pfc0_val = 0xFFFF8000;
1349         pfc1_val = 0x2;
1350
1351         /* No PFC support */
1352         if (!(params->feature_config_flags &
1353               FEATURE_CONFIG_PFC_ENABLED)) {
1354
1355                 /* RX flow control - Process pause frame in receive direction
1356                  */
1357                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1358                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1359
1360                 /* TX flow control - Send pause packet when buffer is full */
1361                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1362                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1363         } else {/* PFC support */
1364                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1365                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1366                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1367                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1368                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1369                 /* Write pause and PFC registers */
1370                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1371                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1372                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1373                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374
1375         }
1376
1377         /* Write pause and PFC registers */
1378         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1379         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1380         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1381
1382
1383         /* Set MAC address for source TX Pause/PFC frames */
1384         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1385                ((params->mac_addr[2] << 24) |
1386                 (params->mac_addr[3] << 16) |
1387                 (params->mac_addr[4] << 8) |
1388                 (params->mac_addr[5])));
1389         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1390                ((params->mac_addr[0] << 8) |
1391                 (params->mac_addr[1])));
1392
1393         udelay(30);
1394 }
1395
1396
1397 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1398                                     u32 pfc_frames_sent[2],
1399                                     u32 pfc_frames_received[2])
1400 {
1401         /* Read pfc statistic */
1402         struct bnx2x *bp = params->bp;
1403         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1404         u32 val_xon = 0;
1405         u32 val_xoff = 0;
1406
1407         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1408
1409         /* PFC received frames */
1410         val_xoff = REG_RD(bp, emac_base +
1411                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1412         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1413         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1414         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1415
1416         pfc_frames_received[0] = val_xon + val_xoff;
1417
1418         /* PFC received sent */
1419         val_xoff = REG_RD(bp, emac_base +
1420                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1421         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1422         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1423         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1424
1425         pfc_frames_sent[0] = val_xon + val_xoff;
1426 }
1427
1428 /* Read pfc statistic*/
1429 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1430                          u32 pfc_frames_sent[2],
1431                          u32 pfc_frames_received[2])
1432 {
1433         /* Read pfc statistic */
1434         struct bnx2x *bp = params->bp;
1435
1436         DP(NETIF_MSG_LINK, "pfc statistic\n");
1437
1438         if (!vars->link_up)
1439                 return;
1440
1441         if (vars->mac_type == MAC_TYPE_EMAC) {
1442                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1443                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1444                                         pfc_frames_received);
1445         }
1446 }
1447 /******************************************************************/
1448 /*                      MAC/PBF section                           */
1449 /******************************************************************/
1450 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1451                                u32 emac_base)
1452 {
1453         u32 new_mode, cur_mode;
1454         u32 clc_cnt;
1455         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1456          * (a value of 49==0x31) and make sure that the AUTO poll is off
1457          */
1458         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1459
1460         if (USES_WARPCORE(bp))
1461                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1462         else
1463                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1464
1465         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1466             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1467                 return;
1468
1469         new_mode = cur_mode &
1470                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1471         new_mode |= clc_cnt;
1472         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1473
1474         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1475            cur_mode, new_mode);
1476         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1477         udelay(40);
1478 }
1479
1480 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1481                                         struct link_params *params)
1482 {
1483         u8 phy_index;
1484         /* Set mdio clock per phy */
1485         for (phy_index = INT_PHY; phy_index < params->num_phys;
1486               phy_index++)
1487                 bnx2x_set_mdio_clk(bp, params->chip_id,
1488                                    params->phy[phy_index].mdio_ctrl);
1489 }
1490
1491 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1492 {
1493         u32 port4mode_ovwr_val;
1494         /* Check 4-port override enabled */
1495         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1496         if (port4mode_ovwr_val & (1<<0)) {
1497                 /* Return 4-port mode override value */
1498                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1499         }
1500         /* Return 4-port mode from input pin */
1501         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1502 }
1503
1504 static void bnx2x_emac_init(struct link_params *params,
1505                             struct link_vars *vars)
1506 {
1507         /* reset and unreset the emac core */
1508         struct bnx2x *bp = params->bp;
1509         u8 port = params->port;
1510         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1511         u32 val;
1512         u16 timeout;
1513
1514         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1515                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1516         udelay(5);
1517         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1518                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1519
1520         /* init emac - use read-modify-write */
1521         /* self clear reset */
1522         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1523         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1524
1525         timeout = 200;
1526         do {
1527                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1529                 if (!timeout) {
1530                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1531                         return;
1532                 }
1533                 timeout--;
1534         } while (val & EMAC_MODE_RESET);
1535
1536         bnx2x_set_mdio_emac_per_phy(bp, params);
1537         /* Set mac address */
1538         val = ((params->mac_addr[0] << 8) |
1539                 params->mac_addr[1]);
1540         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1541
1542         val = ((params->mac_addr[2] << 24) |
1543                (params->mac_addr[3] << 16) |
1544                (params->mac_addr[4] << 8) |
1545                 params->mac_addr[5]);
1546         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1547 }
1548
1549 static void bnx2x_set_xumac_nig(struct link_params *params,
1550                                 u16 tx_pause_en,
1551                                 u8 enable)
1552 {
1553         struct bnx2x *bp = params->bp;
1554
1555         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1556                enable);
1557         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1558                enable);
1559         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1560                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1561 }
1562
1563 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1564 {
1565         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1566         u32 val;
1567         struct bnx2x *bp = params->bp;
1568         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1569                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1570                 return;
1571         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1572         if (en)
1573                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1574                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1575         else
1576                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1577                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1578         /* Disable RX and TX */
1579         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1580 }
1581
1582 static void bnx2x_umac_enable(struct link_params *params,
1583                             struct link_vars *vars, u8 lb)
1584 {
1585         u32 val;
1586         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1587         struct bnx2x *bp = params->bp;
1588         /* Reset UMAC */
1589         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1590                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1591         usleep_range(1000, 2000);
1592
1593         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1594                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1595
1596         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1597
1598         /* This register opens the gate for the UMAC despite its name */
1599         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1600
1601         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1602                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1603                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1604                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1605         switch (vars->line_speed) {
1606         case SPEED_10:
1607                 val |= (0<<2);
1608                 break;
1609         case SPEED_100:
1610                 val |= (1<<2);
1611                 break;
1612         case SPEED_1000:
1613                 val |= (2<<2);
1614                 break;
1615         case SPEED_2500:
1616                 val |= (3<<2);
1617                 break;
1618         default:
1619                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1620                                vars->line_speed);
1621                 break;
1622         }
1623         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1624                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1625
1626         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1627                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1628
1629         if (vars->duplex == DUPLEX_HALF)
1630                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1631
1632         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1633         udelay(50);
1634
1635         /* Configure UMAC for EEE */
1636         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1637                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1638                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1639                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1640                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1641         } else {
1642                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1643         }
1644
1645         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1646         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1647                ((params->mac_addr[2] << 24) |
1648                 (params->mac_addr[3] << 16) |
1649                 (params->mac_addr[4] << 8) |
1650                 (params->mac_addr[5])));
1651         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1652                ((params->mac_addr[0] << 8) |
1653                 (params->mac_addr[1])));
1654
1655         /* Enable RX and TX */
1656         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1657         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1658                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1659         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1660         udelay(50);
1661
1662         /* Remove SW Reset */
1663         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1664
1665         /* Check loopback mode */
1666         if (lb)
1667                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1668         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1669
1670         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1671          * length used by the MAC receive logic to check frames.
1672          */
1673         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1674         bnx2x_set_xumac_nig(params,
1675                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1676         vars->mac_type = MAC_TYPE_UMAC;
1677
1678 }
1679
1680 /* Define the XMAC mode */
1681 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1682 {
1683         struct bnx2x *bp = params->bp;
1684         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1685
1686         /* In 4-port mode, need to set the mode only once, so if XMAC is
1687          * already out of reset, it means the mode has already been set,
1688          * and it must not* reset the XMAC again, since it controls both
1689          * ports of the path
1690          */
1691
1692         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1693              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1694              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1695             is_port4mode &&
1696             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1697              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1698                 DP(NETIF_MSG_LINK,
1699                    "XMAC already out of reset in 4-port mode\n");
1700                 return;
1701         }
1702
1703         /* Hard reset */
1704         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1705                MISC_REGISTERS_RESET_REG_2_XMAC);
1706         usleep_range(1000, 2000);
1707
1708         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1709                MISC_REGISTERS_RESET_REG_2_XMAC);
1710         if (is_port4mode) {
1711                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1712
1713                 /* Set the number of ports on the system side to up to 2 */
1714                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1715
1716                 /* Set the number of ports on the Warp Core to 10G */
1717                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1718         } else {
1719                 /* Set the number of ports on the system side to 1 */
1720                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1721                 if (max_speed == SPEED_10000) {
1722                         DP(NETIF_MSG_LINK,
1723                            "Init XMAC to 10G x 1 port per path\n");
1724                         /* Set the number of ports on the Warp Core to 10G */
1725                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1726                 } else {
1727                         DP(NETIF_MSG_LINK,
1728                            "Init XMAC to 20G x 2 ports per path\n");
1729                         /* Set the number of ports on the Warp Core to 20G */
1730                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1731                 }
1732         }
1733         /* Soft reset */
1734         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1735                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1736         usleep_range(1000, 2000);
1737
1738         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1739                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1740
1741 }
1742
1743 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1744 {
1745         u8 port = params->port;
1746         struct bnx2x *bp = params->bp;
1747         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1748         u32 val;
1749
1750         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1751             MISC_REGISTERS_RESET_REG_2_XMAC) {
1752                 /* Send an indication to change the state in the NIG back to XON
1753                  * Clearing this bit enables the next set of this bit to get
1754                  * rising edge
1755                  */
1756                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1757                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1758                        (pfc_ctrl & ~(1<<1)));
1759                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1760                        (pfc_ctrl | (1<<1)));
1761                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1762                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1763                 if (en)
1764                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1765                 else
1766                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1767                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1768         }
1769 }
1770
1771 static int bnx2x_xmac_enable(struct link_params *params,
1772                              struct link_vars *vars, u8 lb)
1773 {
1774         u32 val, xmac_base;
1775         struct bnx2x *bp = params->bp;
1776         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1777
1778         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1779
1780         bnx2x_xmac_init(params, vars->line_speed);
1781
1782         /* This register determines on which events the MAC will assert
1783          * error on the i/f to the NIG along w/ EOP.
1784          */
1785
1786         /* This register tells the NIG whether to send traffic to UMAC
1787          * or XMAC
1788          */
1789         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1790
1791         /* When XMAC is in XLGMII mode, disable sending idles for fault
1792          * detection.
1793          */
1794         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1795                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1796                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1797                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1798                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1799                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1800                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1801                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1802         }
1803         /* Set Max packet size */
1804         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1805
1806         /* CRC append for Tx packets */
1807         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1808
1809         /* update PFC */
1810         bnx2x_update_pfc_xmac(params, vars, 0);
1811
1812         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1813                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1814                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1815                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1816         } else {
1817                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1818         }
1819
1820         /* Enable TX and RX */
1821         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1822
1823         /* Set MAC in XLGMII mode for dual-mode */
1824         if ((vars->line_speed == SPEED_20000) &&
1825             (params->phy[INT_PHY].supported &
1826              SUPPORTED_20000baseKR2_Full))
1827                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1828
1829         /* Check loopback mode */
1830         if (lb)
1831                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1832         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1833         bnx2x_set_xumac_nig(params,
1834                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1835
1836         vars->mac_type = MAC_TYPE_XMAC;
1837
1838         return 0;
1839 }
1840
1841 static int bnx2x_emac_enable(struct link_params *params,
1842                              struct link_vars *vars, u8 lb)
1843 {
1844         struct bnx2x *bp = params->bp;
1845         u8 port = params->port;
1846         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1847         u32 val;
1848
1849         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1850
1851         /* Disable BMAC */
1852         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1853                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1854
1855         /* enable emac and not bmac */
1856         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1857
1858         /* ASIC */
1859         if (vars->phy_flags & PHY_XGXS_FLAG) {
1860                 u32 ser_lane = ((params->lane_config &
1861                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1862                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1863
1864                 DP(NETIF_MSG_LINK, "XGXS\n");
1865                 /* select the master lanes (out of 0-3) */
1866                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1867                 /* select XGXS */
1868                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1869
1870         } else { /* SerDes */
1871                 DP(NETIF_MSG_LINK, "SerDes\n");
1872                 /* select SerDes */
1873                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1874         }
1875
1876         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1877                       EMAC_RX_MODE_RESET);
1878         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1879                       EMAC_TX_MODE_RESET);
1880
1881                 /* pause enable/disable */
1882                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1883                                EMAC_RX_MODE_FLOW_EN);
1884
1885                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1886                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1887                                 EMAC_TX_MODE_FLOW_EN));
1888                 if (!(params->feature_config_flags &
1889                       FEATURE_CONFIG_PFC_ENABLED)) {
1890                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1891                                 bnx2x_bits_en(bp, emac_base +
1892                                               EMAC_REG_EMAC_RX_MODE,
1893                                               EMAC_RX_MODE_FLOW_EN);
1894
1895                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1896                                 bnx2x_bits_en(bp, emac_base +
1897                                               EMAC_REG_EMAC_TX_MODE,
1898                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1899                                                EMAC_TX_MODE_FLOW_EN));
1900                 } else
1901                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1902                                       EMAC_TX_MODE_FLOW_EN);
1903
1904         /* KEEP_VLAN_TAG, promiscuous */
1905         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1906         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1907
1908         /* Setting this bit causes MAC control frames (except for pause
1909          * frames) to be passed on for processing. This setting has no
1910          * affect on the operation of the pause frames. This bit effects
1911          * all packets regardless of RX Parser packet sorting logic.
1912          * Turn the PFC off to make sure we are in Xon state before
1913          * enabling it.
1914          */
1915         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1916         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1917                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1918                 /* Enable PFC again */
1919                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1920                         EMAC_REG_RX_PFC_MODE_RX_EN |
1921                         EMAC_REG_RX_PFC_MODE_TX_EN |
1922                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1923
1924                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1925                         ((0x0101 <<
1926                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1927                          (0x00ff <<
1928                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1929                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1930         }
1931         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1932
1933         /* Set Loopback */
1934         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1935         if (lb)
1936                 val |= 0x810;
1937         else
1938                 val &= ~0x810;
1939         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1940
1941         /* Enable emac */
1942         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1943
1944         /* Enable emac for jumbo packets */
1945         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1946                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1947                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1948
1949         /* Strip CRC */
1950         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1951
1952         /* Disable the NIG in/out to the bmac */
1953         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1954         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1955         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1956
1957         /* Enable the NIG in/out to the emac */
1958         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1959         val = 0;
1960         if ((params->feature_config_flags &
1961               FEATURE_CONFIG_PFC_ENABLED) ||
1962             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1963                 val = 1;
1964
1965         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1966         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1967
1968         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1969
1970         vars->mac_type = MAC_TYPE_EMAC;
1971         return 0;
1972 }
1973
1974 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1975                                    struct link_vars *vars)
1976 {
1977         u32 wb_data[2];
1978         struct bnx2x *bp = params->bp;
1979         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1980                 NIG_REG_INGRESS_BMAC0_MEM;
1981
1982         u32 val = 0x14;
1983         if ((!(params->feature_config_flags &
1984               FEATURE_CONFIG_PFC_ENABLED)) &&
1985                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1986                 /* Enable BigMAC to react on received Pause packets */
1987                 val |= (1<<5);
1988         wb_data[0] = val;
1989         wb_data[1] = 0;
1990         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1991
1992         /* TX control */
1993         val = 0xc0;
1994         if (!(params->feature_config_flags &
1995               FEATURE_CONFIG_PFC_ENABLED) &&
1996                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1997                 val |= 0x800000;
1998         wb_data[0] = val;
1999         wb_data[1] = 0;
2000         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2001 }
2002
2003 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2004                                    struct link_vars *vars,
2005                                    u8 is_lb)
2006 {
2007         /* Set rx control: Strip CRC and enable BigMAC to relay
2008          * control packets to the system as well
2009          */
2010         u32 wb_data[2];
2011         struct bnx2x *bp = params->bp;
2012         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2013                 NIG_REG_INGRESS_BMAC0_MEM;
2014         u32 val = 0x14;
2015
2016         if ((!(params->feature_config_flags &
2017               FEATURE_CONFIG_PFC_ENABLED)) &&
2018                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2019                 /* Enable BigMAC to react on received Pause packets */
2020                 val |= (1<<5);
2021         wb_data[0] = val;
2022         wb_data[1] = 0;
2023         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2024         udelay(30);
2025
2026         /* Tx control */
2027         val = 0xc0;
2028         if (!(params->feature_config_flags &
2029                                 FEATURE_CONFIG_PFC_ENABLED) &&
2030             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2031                 val |= 0x800000;
2032         wb_data[0] = val;
2033         wb_data[1] = 0;
2034         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2035
2036         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2037                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2038                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2039                 wb_data[0] = 0x0;
2040                 wb_data[0] |= (1<<0);  /* RX */
2041                 wb_data[0] |= (1<<1);  /* TX */
2042                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2043                 wb_data[0] |= (1<<3);  /* 8 cos */
2044                 wb_data[0] |= (1<<5);  /* STATS */
2045                 wb_data[1] = 0;
2046                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2047                             wb_data, 2);
2048                 /* Clear the force Xon */
2049                 wb_data[0] &= ~(1<<2);
2050         } else {
2051                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2052                 /* Disable PFC RX & TX & STATS and set 8 COS */
2053                 wb_data[0] = 0x8;
2054                 wb_data[1] = 0;
2055         }
2056
2057         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2058
2059         /* Set Time (based unit is 512 bit time) between automatic
2060          * re-sending of PP packets amd enable automatic re-send of
2061          * Per-Priroity Packet as long as pp_gen is asserted and
2062          * pp_disable is low.
2063          */
2064         val = 0x8000;
2065         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2066                 val |= (1<<16); /* enable automatic re-send */
2067
2068         wb_data[0] = val;
2069         wb_data[1] = 0;
2070         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2071                     wb_data, 2);
2072
2073         /* mac control */
2074         val = 0x3; /* Enable RX and TX */
2075         if (is_lb) {
2076                 val |= 0x4; /* Local loopback */
2077                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2078         }
2079         /* When PFC enabled, Pass pause frames towards the NIG. */
2080         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2081                 val |= ((1<<6)|(1<<5));
2082
2083         wb_data[0] = val;
2084         wb_data[1] = 0;
2085         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2086 }
2087
2088 /******************************************************************************
2089 * Description:
2090 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2091 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2092 ******************************************************************************/
2093 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2094                                            u8 cos_entry,
2095                                            u32 priority_mask, u8 port)
2096 {
2097         u32 nig_reg_rx_priority_mask_add = 0;
2098
2099         switch (cos_entry) {
2100         case 0:
2101              nig_reg_rx_priority_mask_add = (port) ?
2102                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2103                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2104              break;
2105         case 1:
2106             nig_reg_rx_priority_mask_add = (port) ?
2107                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2108                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2109             break;
2110         case 2:
2111             nig_reg_rx_priority_mask_add = (port) ?
2112                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2113                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2114             break;
2115         case 3:
2116             if (port)
2117                 return -EINVAL;
2118             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2119             break;
2120         case 4:
2121             if (port)
2122                 return -EINVAL;
2123             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2124             break;
2125         case 5:
2126             if (port)
2127                 return -EINVAL;
2128             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2129             break;
2130         }
2131
2132         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2133
2134         return 0;
2135 }
2136 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2137 {
2138         struct bnx2x *bp = params->bp;
2139
2140         REG_WR(bp, params->shmem_base +
2141                offsetof(struct shmem_region,
2142                         port_mb[params->port].link_status), link_status);
2143 }
2144
2145 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2146 {
2147         struct bnx2x *bp = params->bp;
2148
2149         if (SHMEM2_HAS(bp, link_attr_sync))
2150                 REG_WR(bp, params->shmem2_base +
2151                        offsetof(struct shmem2_region,
2152                                 link_attr_sync[params->port]), link_attr);
2153 }
2154
2155 static void bnx2x_update_pfc_nig(struct link_params *params,
2156                 struct link_vars *vars,
2157                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2158 {
2159         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2160         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2161         u32 pkt_priority_to_cos = 0;
2162         struct bnx2x *bp = params->bp;
2163         u8 port = params->port;
2164
2165         int set_pfc = params->feature_config_flags &
2166                 FEATURE_CONFIG_PFC_ENABLED;
2167         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2168
2169         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2170          * MAC control frames (that are not pause packets)
2171          * will be forwarded to the XCM.
2172          */
2173         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2174                           NIG_REG_LLH0_XCM_MASK);
2175         /* NIG params will override non PFC params, since it's possible to
2176          * do transition from PFC to SAFC
2177          */
2178         if (set_pfc) {
2179                 pause_enable = 0;
2180                 llfc_out_en = 0;
2181                 llfc_enable = 0;
2182                 if (CHIP_IS_E3(bp))
2183                         ppp_enable = 0;
2184                 else
2185                         ppp_enable = 1;
2186                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2187                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2188                 xcm_out_en = 0;
2189                 hwpfc_enable = 1;
2190         } else  {
2191                 if (nig_params) {
2192                         llfc_out_en = nig_params->llfc_out_en;
2193                         llfc_enable = nig_params->llfc_enable;
2194                         pause_enable = nig_params->pause_enable;
2195                 } else  /* Default non PFC mode - PAUSE */
2196                         pause_enable = 1;
2197
2198                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2199                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2200                 xcm_out_en = 1;
2201         }
2202
2203         if (CHIP_IS_E3(bp))
2204                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2205                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2206         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2207                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2208         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2209                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2210         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2211                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2212
2213         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2214                NIG_REG_PPP_ENABLE_0, ppp_enable);
2215
2216         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2217                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2218
2219         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2220                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2221
2222         /* Output enable for RX_XCM # IF */
2223         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2224                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2225
2226         /* HW PFC TX enable */
2227         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2228                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2229
2230         if (nig_params) {
2231                 u8 i = 0;
2232                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2233
2234                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2235                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2236                 nig_params->rx_cos_priority_mask[i], port);
2237
2238                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2239                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2240                        nig_params->llfc_high_priority_classes);
2241
2242                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2243                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2244                        nig_params->llfc_low_priority_classes);
2245         }
2246         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2247                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2248                pkt_priority_to_cos);
2249 }
2250
2251 int bnx2x_update_pfc(struct link_params *params,
2252                       struct link_vars *vars,
2253                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2254 {
2255         /* The PFC and pause are orthogonal to one another, meaning when
2256          * PFC is enabled, the pause are disabled, and when PFC is
2257          * disabled, pause are set according to the pause result.
2258          */
2259         u32 val;
2260         struct bnx2x *bp = params->bp;
2261         int bnx2x_status = 0;
2262         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2263
2264         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2265                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2266         else
2267                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2268
2269         bnx2x_update_mng(params, vars->link_status);
2270
2271         /* Update NIG params */
2272         bnx2x_update_pfc_nig(params, vars, pfc_params);
2273
2274         if (!vars->link_up)
2275                 return bnx2x_status;
2276
2277         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2278
2279         if (CHIP_IS_E3(bp)) {
2280                 if (vars->mac_type == MAC_TYPE_XMAC)
2281                         bnx2x_update_pfc_xmac(params, vars, 0);
2282         } else {
2283                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2284                 if ((val &
2285                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2286                     == 0) {
2287                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2288                         bnx2x_emac_enable(params, vars, 0);
2289                         return bnx2x_status;
2290                 }
2291                 if (CHIP_IS_E2(bp))
2292                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2293                 else
2294                         bnx2x_update_pfc_bmac1(params, vars);
2295
2296                 val = 0;
2297                 if ((params->feature_config_flags &
2298                      FEATURE_CONFIG_PFC_ENABLED) ||
2299                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2300                         val = 1;
2301                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2302         }
2303         return bnx2x_status;
2304 }
2305
2306 static int bnx2x_bmac1_enable(struct link_params *params,
2307                               struct link_vars *vars,
2308                               u8 is_lb)
2309 {
2310         struct bnx2x *bp = params->bp;
2311         u8 port = params->port;
2312         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2313                                NIG_REG_INGRESS_BMAC0_MEM;
2314         u32 wb_data[2];
2315         u32 val;
2316
2317         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2318
2319         /* XGXS control */
2320         wb_data[0] = 0x3c;
2321         wb_data[1] = 0;
2322         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2323                     wb_data, 2);
2324
2325         /* TX MAC SA */
2326         wb_data[0] = ((params->mac_addr[2] << 24) |
2327                        (params->mac_addr[3] << 16) |
2328                        (params->mac_addr[4] << 8) |
2329                         params->mac_addr[5]);
2330         wb_data[1] = ((params->mac_addr[0] << 8) |
2331                         params->mac_addr[1]);
2332         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2333
2334         /* MAC control */
2335         val = 0x3;
2336         if (is_lb) {
2337                 val |= 0x4;
2338                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2339         }
2340         wb_data[0] = val;
2341         wb_data[1] = 0;
2342         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2343
2344         /* Set rx mtu */
2345         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2346         wb_data[1] = 0;
2347         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2348
2349         bnx2x_update_pfc_bmac1(params, vars);
2350
2351         /* Set tx mtu */
2352         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2353         wb_data[1] = 0;
2354         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2355
2356         /* Set cnt max size */
2357         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2358         wb_data[1] = 0;
2359         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2360
2361         /* Configure SAFC */
2362         wb_data[0] = 0x1000200;
2363         wb_data[1] = 0;
2364         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2365                     wb_data, 2);
2366
2367         return 0;
2368 }
2369
2370 static int bnx2x_bmac2_enable(struct link_params *params,
2371                               struct link_vars *vars,
2372                               u8 is_lb)
2373 {
2374         struct bnx2x *bp = params->bp;
2375         u8 port = params->port;
2376         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2377                                NIG_REG_INGRESS_BMAC0_MEM;
2378         u32 wb_data[2];
2379
2380         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2381
2382         wb_data[0] = 0;
2383         wb_data[1] = 0;
2384         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2385         udelay(30);
2386
2387         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2388         wb_data[0] = 0x3c;
2389         wb_data[1] = 0;
2390         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2391                     wb_data, 2);
2392
2393         udelay(30);
2394
2395         /* TX MAC SA */
2396         wb_data[0] = ((params->mac_addr[2] << 24) |
2397                        (params->mac_addr[3] << 16) |
2398                        (params->mac_addr[4] << 8) |
2399                         params->mac_addr[5]);
2400         wb_data[1] = ((params->mac_addr[0] << 8) |
2401                         params->mac_addr[1]);
2402         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2403                     wb_data, 2);
2404
2405         udelay(30);
2406
2407         /* Configure SAFC */
2408         wb_data[0] = 0x1000200;
2409         wb_data[1] = 0;
2410         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2411                     wb_data, 2);
2412         udelay(30);
2413
2414         /* Set RX MTU */
2415         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2416         wb_data[1] = 0;
2417         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2418         udelay(30);
2419
2420         /* Set TX MTU */
2421         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2422         wb_data[1] = 0;
2423         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2424         udelay(30);
2425         /* Set cnt max size */
2426         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2427         wb_data[1] = 0;
2428         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2429         udelay(30);
2430         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2431
2432         return 0;
2433 }
2434
2435 static int bnx2x_bmac_enable(struct link_params *params,
2436                              struct link_vars *vars,
2437                              u8 is_lb, u8 reset_bmac)
2438 {
2439         int rc = 0;
2440         u8 port = params->port;
2441         struct bnx2x *bp = params->bp;
2442         u32 val;
2443         /* Reset and unreset the BigMac */
2444         if (reset_bmac) {
2445                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2446                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2447                 usleep_range(1000, 2000);
2448         }
2449
2450         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2451                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2452
2453         /* Enable access for bmac registers */
2454         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2455
2456         /* Enable BMAC according to BMAC type*/
2457         if (CHIP_IS_E2(bp))
2458                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2459         else
2460                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2461         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2462         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2463         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2464         val = 0;
2465         if ((params->feature_config_flags &
2466               FEATURE_CONFIG_PFC_ENABLED) ||
2467             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2468                 val = 1;
2469         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2470         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2471         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2472         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2473         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2474         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2475
2476         vars->mac_type = MAC_TYPE_BMAC;
2477         return rc;
2478 }
2479
2480 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2481 {
2482         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2483                         NIG_REG_INGRESS_BMAC0_MEM;
2484         u32 wb_data[2];
2485         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2486
2487         if (CHIP_IS_E2(bp))
2488                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2489         else
2490                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2491         /* Only if the bmac is out of reset */
2492         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2493                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2494             nig_bmac_enable) {
2495                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2496                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2497                 if (en)
2498                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2499                 else
2500                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2501                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2502                 usleep_range(1000, 2000);
2503         }
2504 }
2505
2506 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2507                             u32 line_speed)
2508 {
2509         struct bnx2x *bp = params->bp;
2510         u8 port = params->port;
2511         u32 init_crd, crd;
2512         u32 count = 1000;
2513
2514         /* Disable port */
2515         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2516
2517         /* Wait for init credit */
2518         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2519         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2520         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2521
2522         while ((init_crd != crd) && count) {
2523                 usleep_range(5000, 10000);
2524                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525                 count--;
2526         }
2527         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2528         if (init_crd != crd) {
2529                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2530                           init_crd, crd);
2531                 return -EINVAL;
2532         }
2533
2534         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2535             line_speed == SPEED_10 ||
2536             line_speed == SPEED_100 ||
2537             line_speed == SPEED_1000 ||
2538             line_speed == SPEED_2500) {
2539                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2540                 /* Update threshold */
2541                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2542                 /* Update init credit */
2543                 init_crd = 778;         /* (800-18-4) */
2544
2545         } else {
2546                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2547                               ETH_OVREHEAD)/16;
2548                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2549                 /* Update threshold */
2550                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2551                 /* Update init credit */
2552                 switch (line_speed) {
2553                 case SPEED_10000:
2554                         init_crd = thresh + 553 - 22;
2555                         break;
2556                 default:
2557                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2558                                   line_speed);
2559                         return -EINVAL;
2560                 }
2561         }
2562         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2563         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2564                  line_speed, init_crd);
2565
2566         /* Probe the credit changes */
2567         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2568         usleep_range(5000, 10000);
2569         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2570
2571         /* Enable port */
2572         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2573         return 0;
2574 }
2575
2576 /**
2577  * bnx2x_get_emac_base - retrive emac base address
2578  *
2579  * @bp:                 driver handle
2580  * @mdc_mdio_access:    access type
2581  * @port:               port id
2582  *
2583  * This function selects the MDC/MDIO access (through emac0 or
2584  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2585  * phy has a default access mode, which could also be overridden
2586  * by nvram configuration. This parameter, whether this is the
2587  * default phy configuration, or the nvram overrun
2588  * configuration, is passed here as mdc_mdio_access and selects
2589  * the emac_base for the CL45 read/writes operations
2590  */
2591 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2592                                u32 mdc_mdio_access, u8 port)
2593 {
2594         u32 emac_base = 0;
2595         switch (mdc_mdio_access) {
2596         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2597                 break;
2598         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2599                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2600                         emac_base = GRCBASE_EMAC1;
2601                 else
2602                         emac_base = GRCBASE_EMAC0;
2603                 break;
2604         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2605                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2606                         emac_base = GRCBASE_EMAC0;
2607                 else
2608                         emac_base = GRCBASE_EMAC1;
2609                 break;
2610         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2611                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2612                 break;
2613         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2614                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2615                 break;
2616         default:
2617                 break;
2618         }
2619         return emac_base;
2620
2621 }
2622
2623 /******************************************************************/
2624 /*                      CL22 access functions                     */
2625 /******************************************************************/
2626 static int bnx2x_cl22_write(struct bnx2x *bp,
2627                                        struct bnx2x_phy *phy,
2628                                        u16 reg, u16 val)
2629 {
2630         u32 tmp, mode;
2631         u8 i;
2632         int rc = 0;
2633         /* Switch to CL22 */
2634         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2635         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2636                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2637
2638         /* Address */
2639         tmp = ((phy->addr << 21) | (reg << 16) | val |
2640                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2641                EMAC_MDIO_COMM_START_BUSY);
2642         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2643
2644         for (i = 0; i < 50; i++) {
2645                 udelay(10);
2646
2647                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2648                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2649                         udelay(5);
2650                         break;
2651                 }
2652         }
2653         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2654                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2655                 rc = -EFAULT;
2656         }
2657         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2658         return rc;
2659 }
2660
2661 static int bnx2x_cl22_read(struct bnx2x *bp,
2662                                       struct bnx2x_phy *phy,
2663                                       u16 reg, u16 *ret_val)
2664 {
2665         u32 val, mode;
2666         u16 i;
2667         int rc = 0;
2668
2669         /* Switch to CL22 */
2670         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2671         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2672                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2673
2674         /* Address */
2675         val = ((phy->addr << 21) | (reg << 16) |
2676                EMAC_MDIO_COMM_COMMAND_READ_22 |
2677                EMAC_MDIO_COMM_START_BUSY);
2678         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2679
2680         for (i = 0; i < 50; i++) {
2681                 udelay(10);
2682
2683                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2684                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2685                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2686                         udelay(5);
2687                         break;
2688                 }
2689         }
2690         if (val & EMAC_MDIO_COMM_START_BUSY) {
2691                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2692
2693                 *ret_val = 0;
2694                 rc = -EFAULT;
2695         }
2696         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2697         return rc;
2698 }
2699
2700 /******************************************************************/
2701 /*                      CL45 access functions                     */
2702 /******************************************************************/
2703 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2704                            u8 devad, u16 reg, u16 *ret_val)
2705 {
2706         u32 val;
2707         u16 i;
2708         int rc = 0;
2709         u32 chip_id;
2710         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2711                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2712                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2713                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2714         }
2715
2716         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2717                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2718                               EMAC_MDIO_STATUS_10MB);
2719         /* Address */
2720         val = ((phy->addr << 21) | (devad << 16) | reg |
2721                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2722                EMAC_MDIO_COMM_START_BUSY);
2723         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2724
2725         for (i = 0; i < 50; i++) {
2726                 udelay(10);
2727
2728                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2729                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2730                         udelay(5);
2731                         break;
2732                 }
2733         }
2734         if (val & EMAC_MDIO_COMM_START_BUSY) {
2735                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2736                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2737                 *ret_val = 0;
2738                 rc = -EFAULT;
2739         } else {
2740                 /* Data */
2741                 val = ((phy->addr << 21) | (devad << 16) |
2742                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2743                        EMAC_MDIO_COMM_START_BUSY);
2744                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2745
2746                 for (i = 0; i < 50; i++) {
2747                         udelay(10);
2748
2749                         val = REG_RD(bp, phy->mdio_ctrl +
2750                                      EMAC_REG_EMAC_MDIO_COMM);
2751                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2752                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2753                                 break;
2754                         }
2755                 }
2756                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2757                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2758                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2759                         *ret_val = 0;
2760                         rc = -EFAULT;
2761                 }
2762         }
2763         /* Work around for E3 A0 */
2764         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2765                 phy->flags ^= FLAGS_DUMMY_READ;
2766                 if (phy->flags & FLAGS_DUMMY_READ) {
2767                         u16 temp_val;
2768                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2769                 }
2770         }
2771
2772         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2773                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2774                                EMAC_MDIO_STATUS_10MB);
2775         return rc;
2776 }
2777
2778 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2779                             u8 devad, u16 reg, u16 val)
2780 {
2781         u32 tmp;
2782         u8 i;
2783         int rc = 0;
2784         u32 chip_id;
2785         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2786                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2787                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2788                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2789         }
2790
2791         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2792                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2793                               EMAC_MDIO_STATUS_10MB);
2794
2795         /* Address */
2796         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2797                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2798                EMAC_MDIO_COMM_START_BUSY);
2799         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2800
2801         for (i = 0; i < 50; i++) {
2802                 udelay(10);
2803
2804                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2805                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2806                         udelay(5);
2807                         break;
2808                 }
2809         }
2810         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2811                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2812                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2813                 rc = -EFAULT;
2814         } else {
2815                 /* Data */
2816                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2817                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2818                        EMAC_MDIO_COMM_START_BUSY);
2819                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2820
2821                 for (i = 0; i < 50; i++) {
2822                         udelay(10);
2823
2824                         tmp = REG_RD(bp, phy->mdio_ctrl +
2825                                      EMAC_REG_EMAC_MDIO_COMM);
2826                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2827                                 udelay(5);
2828                                 break;
2829                         }
2830                 }
2831                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2832                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2833                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2834                         rc = -EFAULT;
2835                 }
2836         }
2837         /* Work around for E3 A0 */
2838         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2839                 phy->flags ^= FLAGS_DUMMY_READ;
2840                 if (phy->flags & FLAGS_DUMMY_READ) {
2841                         u16 temp_val;
2842                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2843                 }
2844         }
2845         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2846                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2847                                EMAC_MDIO_STATUS_10MB);
2848         return rc;
2849 }
2850
2851 /******************************************************************/
2852 /*                      EEE section                                */
2853 /******************************************************************/
2854 static u8 bnx2x_eee_has_cap(struct link_params *params)
2855 {
2856         struct bnx2x *bp = params->bp;
2857
2858         if (REG_RD(bp, params->shmem2_base) <=
2859                    offsetof(struct shmem2_region, eee_status[params->port]))
2860                 return 0;
2861
2862         return 1;
2863 }
2864
2865 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2866 {
2867         switch (nvram_mode) {
2868         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2869                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2870                 break;
2871         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2872                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2873                 break;
2874         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2875                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2876                 break;
2877         default:
2878                 *idle_timer = 0;
2879                 break;
2880         }
2881
2882         return 0;
2883 }
2884
2885 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2886 {
2887         switch (idle_timer) {
2888         case EEE_MODE_NVRAM_BALANCED_TIME:
2889                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2890                 break;
2891         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2892                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2893                 break;
2894         case EEE_MODE_NVRAM_LATENCY_TIME:
2895                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2896                 break;
2897         default:
2898                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2899                 break;
2900         }
2901
2902         return 0;
2903 }
2904
2905 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2906 {
2907         u32 eee_mode, eee_idle;
2908         struct bnx2x *bp = params->bp;
2909
2910         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2911                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2912                         /* time value in eee_mode --> used directly*/
2913                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2914                 } else {
2915                         /* hsi value in eee_mode --> time */
2916                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2917                                                     EEE_MODE_NVRAM_MASK,
2918                                                     &eee_idle))
2919                                 return 0;
2920                 }
2921         } else {
2922                 /* hsi values in nvram --> time*/
2923                 eee_mode = ((REG_RD(bp, params->shmem_base +
2924                                     offsetof(struct shmem_region, dev_info.
2925                                     port_feature_config[params->port].
2926                                     eee_power_mode)) &
2927                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2928                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2929
2930                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2931                         return 0;
2932         }
2933
2934         return eee_idle;
2935 }
2936
2937 static int bnx2x_eee_set_timers(struct link_params *params,
2938                                    struct link_vars *vars)
2939 {
2940         u32 eee_idle = 0, eee_mode;
2941         struct bnx2x *bp = params->bp;
2942
2943         eee_idle = bnx2x_eee_calc_timer(params);
2944
2945         if (eee_idle) {
2946                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2947                        eee_idle);
2948         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2949                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2950                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2951                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2952                 return -EINVAL;
2953         }
2954
2955         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2956         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2957                 /* eee_idle in 1u --> eee_status in 16u */
2958                 eee_idle >>= 4;
2959                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2960                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2961         } else {
2962                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2963                         return -EINVAL;
2964                 vars->eee_status |= eee_mode;
2965         }
2966
2967         return 0;
2968 }
2969
2970 static int bnx2x_eee_initial_config(struct link_params *params,
2971                                      struct link_vars *vars, u8 mode)
2972 {
2973         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2974
2975         /* Propogate params' bits --> vars (for migration exposure) */
2976         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2977                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2978         else
2979                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2980
2981         if (params->eee_mode & EEE_MODE_ADV_LPI)
2982                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2983         else
2984                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2985
2986         return bnx2x_eee_set_timers(params, vars);
2987 }
2988
2989 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2990                                 struct link_params *params,
2991                                 struct link_vars *vars)
2992 {
2993         struct bnx2x *bp = params->bp;
2994
2995         /* Make Certain LPI is disabled */
2996         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2997
2998         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2999
3000         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3001
3002         return 0;
3003 }
3004
3005 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3006                                   struct link_params *params,
3007                                   struct link_vars *vars, u8 modes)
3008 {
3009         struct bnx2x *bp = params->bp;
3010         u16 val = 0;
3011
3012         /* Mask events preventing LPI generation */
3013         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3014
3015         if (modes & SHMEM_EEE_10G_ADV) {
3016                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3017                 val |= 0x8;
3018         }
3019         if (modes & SHMEM_EEE_1G_ADV) {
3020                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3021                 val |= 0x4;
3022         }
3023
3024         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3025
3026         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3027         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3028
3029         return 0;
3030 }
3031
3032 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3033 {
3034         struct bnx2x *bp = params->bp;
3035
3036         if (bnx2x_eee_has_cap(params))
3037                 REG_WR(bp, params->shmem2_base +
3038                        offsetof(struct shmem2_region,
3039                                 eee_status[params->port]), eee_status);
3040 }
3041
3042 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3043                                   struct link_params *params,
3044                                   struct link_vars *vars)
3045 {
3046         struct bnx2x *bp = params->bp;
3047         u16 adv = 0, lp = 0;
3048         u32 lp_adv = 0;
3049         u8 neg = 0;
3050
3051         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3052         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3053
3054         if (lp & 0x2) {
3055                 lp_adv |= SHMEM_EEE_100M_ADV;
3056                 if (adv & 0x2) {
3057                         if (vars->line_speed == SPEED_100)
3058                                 neg = 1;
3059                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3060                 }
3061         }
3062         if (lp & 0x14) {
3063                 lp_adv |= SHMEM_EEE_1G_ADV;
3064                 if (adv & 0x14) {
3065                         if (vars->line_speed == SPEED_1000)
3066                                 neg = 1;
3067                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3068                 }
3069         }
3070         if (lp & 0x68) {
3071                 lp_adv |= SHMEM_EEE_10G_ADV;
3072                 if (adv & 0x68) {
3073                         if (vars->line_speed == SPEED_10000)
3074                                 neg = 1;
3075                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3076                 }
3077         }
3078
3079         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3080         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3081
3082         if (neg) {
3083                 DP(NETIF_MSG_LINK, "EEE is active\n");
3084                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3085         }
3086
3087 }
3088
3089 /******************************************************************/
3090 /*                      BSC access functions from E3              */
3091 /******************************************************************/
3092 static void bnx2x_bsc_module_sel(struct link_params *params)
3093 {
3094         int idx;
3095         u32 board_cfg, sfp_ctrl;
3096         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3097         struct bnx2x *bp = params->bp;
3098         u8 port = params->port;
3099         /* Read I2C output PINs */
3100         board_cfg = REG_RD(bp, params->shmem_base +
3101                            offsetof(struct shmem_region,
3102                                     dev_info.shared_hw_config.board));
3103         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3104         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3105                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3106
3107         /* Read I2C output value */
3108         sfp_ctrl = REG_RD(bp, params->shmem_base +
3109                           offsetof(struct shmem_region,
3110                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3111         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3112         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3113         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3114         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3115                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3116 }
3117
3118 static int bnx2x_bsc_read(struct link_params *params,
3119                           struct bnx2x_phy *phy,
3120                           u8 sl_devid,
3121                           u16 sl_addr,
3122                           u8 lc_addr,
3123                           u8 xfer_cnt,
3124                           u32 *data_array)
3125 {
3126         u32 val, i;
3127         int rc = 0;
3128         struct bnx2x *bp = params->bp;
3129
3130         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3131                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3132                 return -EINVAL;
3133         }
3134
3135         if (xfer_cnt > 16) {
3136                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137                                         xfer_cnt);
3138                 return -EINVAL;
3139         }
3140         bnx2x_bsc_module_sel(params);
3141
3142         xfer_cnt = 16 - lc_addr;
3143
3144         /* Enable the engine */
3145         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146         val |= MCPR_IMC_COMMAND_ENABLE;
3147         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
3149         /* Program slave device ID */
3150         val = (sl_devid << 16) | sl_addr;
3151         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
3153         /* Start xfer with 0 byte to update the address pointer ???*/
3154         val = (MCPR_IMC_COMMAND_ENABLE) |
3155               (MCPR_IMC_COMMAND_WRITE_OP <<
3156                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
3160         /* Poll for completion */
3161         i = 0;
3162         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164                 udelay(10);
3165                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166                 if (i++ > 1000) {
3167                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168                                                                 i);
3169                         rc = -EFAULT;
3170                         break;
3171                 }
3172         }
3173         if (rc == -EFAULT)
3174                 return rc;
3175
3176         /* Start xfer with read op */
3177         val = (MCPR_IMC_COMMAND_ENABLE) |
3178                 (MCPR_IMC_COMMAND_READ_OP <<
3179                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181                   (xfer_cnt);
3182         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
3184         /* Poll for completion */
3185         i = 0;
3186         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188                 udelay(10);
3189                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190                 if (i++ > 1000) {
3191                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192                         rc = -EFAULT;
3193                         break;
3194                 }
3195         }
3196         if (rc == -EFAULT)
3197                 return rc;
3198
3199         for (i = (lc_addr >> 2); i < 4; i++) {
3200                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201 #ifdef __BIG_ENDIAN
3202                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203                                 ((data_array[i] & 0x0000ff00) << 8) |
3204                                 ((data_array[i] & 0x00ff0000) >> 8) |
3205                                 ((data_array[i] & 0xff000000) >> 24);
3206 #endif
3207         }
3208         return rc;
3209 }
3210
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212                                      u8 devad, u16 reg, u16 or_val)
3213 {
3214         u16 val;
3215         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217 }
3218
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220                                       struct bnx2x_phy *phy,
3221                                       u8 devad, u16 reg, u16 and_val)
3222 {
3223         u16 val;
3224         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226 }
3227
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229                    u8 devad, u16 reg, u16 *ret_val)
3230 {
3231         u8 phy_index;
3232         /* Probe for the phy according to the given phy_addr, and execute
3233          * the read request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_read(params->bp,
3238                                                &params->phy[phy_index], devad,
3239                                                reg, ret_val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246                     u8 devad, u16 reg, u16 val)
3247 {
3248         u8 phy_index;
3249         /* Probe for the phy according to the given phy_addr, and execute
3250          * the write request on it
3251          */
3252         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253                 if (params->phy[phy_index].addr == phy_addr) {
3254                         return bnx2x_cl45_write(params->bp,
3255                                                 &params->phy[phy_index], devad,
3256                                                 reg, val);
3257                 }
3258         }
3259         return -EINVAL;
3260 }
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262                                   struct link_params *params)
3263 {
3264         u8 lane = 0;
3265         struct bnx2x *bp = params->bp;
3266         u32 path_swap, path_swap_ovr;
3267         u8 path, port;
3268
3269         path = BP_PATH(bp);
3270         port = params->port;
3271
3272         if (bnx2x_is_4_port_mode(bp)) {
3273                 u32 port_swap, port_swap_ovr;
3274
3275                 /* Figure out path swap value */
3276                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277                 if (path_swap_ovr & 0x1)
3278                         path_swap = (path_swap_ovr & 0x2);
3279                 else
3280                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282                 if (path_swap)
3283                         path = path ^ 1;
3284
3285                 /* Figure out port swap value */
3286                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287                 if (port_swap_ovr & 0x1)
3288                         port_swap = (port_swap_ovr & 0x2);
3289                 else
3290                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292                 if (port_swap)
3293                         port = port ^ 1;
3294
3295                 lane = (port<<1) + path;
3296         } else { /* Two port mode - no port swap */
3297
3298                 /* Figure out path swap value */
3299                 path_swap_ovr =
3300                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301                 if (path_swap_ovr & 0x1) {
3302                         path_swap = (path_swap_ovr & 0x2);
3303                 } else {
3304                         path_swap =
3305                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306                 }
3307                 if (path_swap)
3308                         path = path ^ 1;
3309
3310                 lane = path << 1 ;
3311         }
3312         return lane;
3313 }
3314
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316                               struct bnx2x_phy *phy)
3317 {
3318         u32 ser_lane;
3319         u16 offset, aer_val;
3320         struct bnx2x *bp = params->bp;
3321         ser_lane = ((params->lane_config &
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
3325         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326                 (phy->addr + ser_lane) : 0;
3327
3328         if (USES_WARPCORE(bp)) {
3329                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330                 /* In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386                                      struct link_params *params,
3387                                      u32 action)
3388 {
3389         struct bnx2x *bp = params->bp;
3390         switch (action) {
3391         case PHY_INIT:
3392                 /* Set correct devad */
3393                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395                        phy->def_md_devad);
3396                 break;
3397         }
3398 }
3399
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3401 {
3402         struct bnx2x *bp = params->bp;
3403         u8 port;
3404         u32 val;
3405         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406         port = params->port;
3407
3408         val = XGXS_RESET_BITS << (port*16);
3409
3410         /* Reset and unreset the SerDes/XGXS */
3411         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412         udelay(500);
3413         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415                                  PHY_INIT);
3416 }
3417
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419                                      struct link_params *params, u16 *ieee_fc)
3420 {
3421         struct bnx2x *bp = params->bp;
3422         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423         /* Resolve pause mode and advertisement Please refer to Table
3424          * 28B-3 of the 802.3ab-1999 spec
3425          */
3426
3427         switch (phy->req_flow_ctrl) {
3428         case BNX2X_FLOW_CTRL_AUTO:
3429                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3430                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3431                 else
3432                         *ieee_fc |=
3433                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3434                 break;
3435
3436         case BNX2X_FLOW_CTRL_TX:
3437                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3438                 break;
3439
3440         case BNX2X_FLOW_CTRL_RX:
3441         case BNX2X_FLOW_CTRL_BOTH:
3442                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3443                 break;
3444
3445         case BNX2X_FLOW_CTRL_NONE:
3446         default:
3447                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3448                 break;
3449         }
3450         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3451 }
3452
3453 static void set_phy_vars(struct link_params *params,
3454                          struct link_vars *vars)
3455 {
3456         struct bnx2x *bp = params->bp;
3457         u8 actual_phy_idx, phy_index, link_cfg_idx;
3458         u8 phy_config_swapped = params->multi_phy_config &
3459                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3460         for (phy_index = INT_PHY; phy_index < params->num_phys;
3461               phy_index++) {
3462                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3463                 actual_phy_idx = phy_index;
3464                 if (phy_config_swapped) {
3465                         if (phy_index == EXT_PHY1)
3466                                 actual_phy_idx = EXT_PHY2;
3467                         else if (phy_index == EXT_PHY2)
3468                                 actual_phy_idx = EXT_PHY1;
3469                 }
3470                 params->phy[actual_phy_idx].req_flow_ctrl =
3471                         params->req_flow_ctrl[link_cfg_idx];
3472
3473                 params->phy[actual_phy_idx].req_line_speed =
3474                         params->req_line_speed[link_cfg_idx];
3475
3476                 params->phy[actual_phy_idx].speed_cap_mask =
3477                         params->speed_cap_mask[link_cfg_idx];
3478
3479                 params->phy[actual_phy_idx].req_duplex =
3480                         params->req_duplex[link_cfg_idx];
3481
3482                 if (params->req_line_speed[link_cfg_idx] ==
3483                     SPEED_AUTO_NEG)
3484                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3485
3486                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3487                            " speed_cap_mask %x\n",
3488                            params->phy[actual_phy_idx].req_flow_ctrl,
3489                            params->phy[actual_phy_idx].req_line_speed,
3490                            params->phy[actual_phy_idx].speed_cap_mask);
3491         }
3492 }
3493
3494 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3495                                     struct bnx2x_phy *phy,
3496                                     struct link_vars *vars)
3497 {
3498         u16 val;
3499         struct bnx2x *bp = params->bp;
3500         /* Read modify write pause advertizing */
3501         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3502
3503         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3504
3505         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3506         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3507         if ((vars->ieee_fc &
3508             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3509             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3510                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3511         }
3512         if ((vars->ieee_fc &
3513             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3514             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3515                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3516         }
3517         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3518         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3519 }
3520
3521 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3522 {                                               /*  LD      LP   */
3523         switch (pause_result) {                 /* ASYM P ASYM P */
3524         case 0xb:                               /*   1  0   1  1 */
3525                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3526                 break;
3527
3528         case 0xe:                               /*   1  1   1  0 */
3529                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3530                 break;
3531
3532         case 0x5:                               /*   0  1   0  1 */
3533         case 0x7:                               /*   0  1   1  1 */
3534         case 0xd:                               /*   1  1   0  1 */
3535         case 0xf:                               /*   1  1   1  1 */
3536                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3537                 break;
3538
3539         default:
3540                 break;
3541         }
3542         if (pause_result & (1<<0))
3543                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3544         if (pause_result & (1<<1))
3545                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3546
3547 }
3548
3549 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3550                                         struct link_params *params,
3551                                         struct link_vars *vars)
3552 {
3553         u16 ld_pause;           /* local */
3554         u16 lp_pause;           /* link partner */
3555         u16 pause_result;
3556         struct bnx2x *bp = params->bp;
3557         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3558                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3559                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3560         } else if (CHIP_IS_E3(bp) &&
3561                 SINGLE_MEDIA_DIRECT(params)) {
3562                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3563                 u16 gp_status, gp_mask;
3564                 bnx2x_cl45_read(bp, phy,
3565                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3566                                 &gp_status);
3567                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3568                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3569                         lane;
3570                 if ((gp_status & gp_mask) == gp_mask) {
3571                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3572                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3573                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3574                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3575                 } else {
3576                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3577                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3578                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3579                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3580                         ld_pause = ((ld_pause &
3581                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3582                                     << 3);
3583                         lp_pause = ((lp_pause &
3584                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3585                                     << 3);
3586                 }
3587         } else {
3588                 bnx2x_cl45_read(bp, phy,
3589                                 MDIO_AN_DEVAD,
3590                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3591                 bnx2x_cl45_read(bp, phy,
3592                                 MDIO_AN_DEVAD,
3593                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3594         }
3595         pause_result = (ld_pause &
3596                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3597         pause_result |= (lp_pause &
3598                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3599         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3600         bnx2x_pause_resolve(vars, pause_result);
3601
3602 }
3603
3604 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3605                                    struct link_params *params,
3606                                    struct link_vars *vars)
3607 {
3608         u8 ret = 0;
3609         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3610         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3611                 /* Update the advertised flow-controled of LD/LP in AN */
3612                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3613                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3614                 /* But set the flow-control result as the requested one */
3615                 vars->flow_ctrl = phy->req_flow_ctrl;
3616         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3617                 vars->flow_ctrl = params->req_fc_auto_adv;
3618         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3619                 ret = 1;
3620                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3621         }
3622         return ret;
3623 }
3624 /******************************************************************/
3625 /*                      Warpcore section                          */
3626 /******************************************************************/
3627 /* The init_internal_warpcore should mirror the xgxs,
3628  * i.e. reset the lane (if needed), set aer for the
3629  * init configuration, and set/clear SGMII flag. Internal
3630  * phy init is done purely in phy_init stage.
3631  */
3632 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3633                                          struct link_params *params,
3634                                          struct link_vars *vars)
3635 {
3636         struct bnx2x *bp = params->bp;
3637         u16 i;
3638         static struct bnx2x_reg_set reg_set[] = {
3639                 /* Step 1 - Program the TX/RX alignment markers */
3640                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3641                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3642                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3643                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3644                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3645                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3646                 /* Step 2 - Configure the NP registers */
3647                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3648                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3649                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3650                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3651                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3652                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3653                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3654                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3655                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3656         };
3657         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3658
3659         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3660                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3661
3662         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3663                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3664                                  reg_set[i].val);
3665
3666         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3667         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3668         bnx2x_update_link_attr(params, vars->link_attr_sync);
3669 }
3670
3671 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3672                                                struct link_params *params)
3673 {
3674         struct bnx2x *bp = params->bp;
3675
3676         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3677         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3679         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3680                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3681 }
3682
3683 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3684                                          struct link_params *params)
3685 {
3686         /* Restart autoneg on the leading lane only */
3687         struct bnx2x *bp = params->bp;
3688         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3689         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3690                           MDIO_AER_BLOCK_AER_REG, lane);
3691         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3692                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3693
3694         /* Restore AER */
3695         bnx2x_set_aer_mmd(params, phy);
3696 }
3697
3698 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3699                                         struct link_params *params,
3700                                         struct link_vars *vars) {
3701         u16 lane, i, cl72_ctrl, an_adv = 0;
3702         u16 ucode_ver;
3703         struct bnx2x *bp = params->bp;
3704         static struct bnx2x_reg_set reg_set[] = {
3705                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3706                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3707                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3708                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3709                 /* Disable Autoneg: re-enable it after adv is done. */
3710                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3711                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3712                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3713         };
3714         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3715         /* Set to default registers that may be overriden by 10G force */
3716         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3717                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3718                                  reg_set[i].val);
3719
3720         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3721                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3722         cl72_ctrl &= 0x08ff;
3723         cl72_ctrl |= 0x3800;
3724         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3725                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3726
3727         /* Check adding advertisement for 1G KX */
3728         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3729              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3730             (vars->line_speed == SPEED_1000)) {
3731                 u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3732                 an_adv |= (1<<5);
3733
3734                 /* Enable CL37 1G Parallel Detect */
3735                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3736                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3737         }
3738         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3739              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3740             (vars->line_speed ==  SPEED_10000)) {
3741                 /* Check adding advertisement for 10G KR */
3742                 an_adv |= (1<<7);
3743                 /* Enable 10G Parallel Detect */
3744                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3745                                   MDIO_AER_BLOCK_AER_REG, 0);
3746
3747                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3748                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3749                 bnx2x_set_aer_mmd(params, phy);
3750                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3751         }
3752
3753         /* Set Transmit PMD settings */
3754         lane = bnx2x_get_warpcore_lane(phy, params);
3755         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3757                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3758                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3759                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3760         /* Configure the next lane if dual mode */
3761         if (phy->flags & FLAGS_WC_DUAL_MODE)
3762                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3763                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3764                                  ((0x02 <<
3765                                  MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3766                                   (0x06 <<
3767                                    MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3768                                   (0x09 <<
3769                                 MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3770         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3772                          0x03f0);
3773         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3774                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3775                          0x03f0);
3776
3777         /* Advertised speeds */
3778         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3779                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3780
3781         /* Advertised and set FEC (Forward Error Correction) */
3782         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3783                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3784                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3785                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3786
3787         /* Enable CL37 BAM */
3788         if (REG_RD(bp, params->shmem_base +
3789                    offsetof(struct shmem_region, dev_info.
3790                             port_hw_config[params->port].default_cfg)) &
3791             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3792                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3793                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3794                                          1);
3795                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3796         }
3797
3798         /* Advertise pause */
3799         bnx2x_ext_phy_set_pause(params, phy, vars);
3800         /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3801          */
3802         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3803                         MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver);
3804         if (ucode_ver < 0xd108) {
3805                 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n",
3806                                ucode_ver);
3807                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3808         }
3809         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3810                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3811
3812         /* Over 1G - AN local device user page 1 */
3813         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3815
3816         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3817              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3818             (phy->req_line_speed == SPEED_20000)) {
3819
3820                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3821                                   MDIO_AER_BLOCK_AER_REG, lane);
3822
3823                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3824                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3825                                          (1<<11));
3826
3827                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3829                 bnx2x_set_aer_mmd(params, phy);
3830
3831                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3832         }
3833
3834         /* Enable Autoneg: only on the main lane */
3835         bnx2x_warpcore_restart_AN_KR(phy, params);
3836 }
3837
3838 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3839                                       struct link_params *params,
3840                                       struct link_vars *vars)
3841 {
3842         struct bnx2x *bp = params->bp;
3843         u16 val16, i, lane;
3844         static struct bnx2x_reg_set reg_set[] = {
3845                 /* Disable Autoneg */
3846                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3847                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3848                         0x3f00},
3849                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3850                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3851                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3852                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3853                 /* Leave cl72 training enable, needed for KR */
3854                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3855         };
3856
3857         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3858                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3859                                  reg_set[i].val);
3860
3861         lane = bnx2x_get_warpcore_lane(phy, params);
3862         /* Global registers */
3863         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3864                           MDIO_AER_BLOCK_AER_REG, 0);
3865         /* Disable CL36 PCS Tx */
3866         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3867                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3868         val16 &= ~(0x0011 << lane);
3869         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3870                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3871
3872         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3873                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3874         val16 |= (0x0303 << (lane << 1));
3875         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3877         /* Restore AER */
3878         bnx2x_set_aer_mmd(params, phy);
3879         /* Set speed via PMA/PMD register */
3880         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3881                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3882
3883         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3884                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3885
3886         /* Enable encoded forced speed */
3887         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3889
3890         /* Turn TX scramble payload only the 64/66 scrambler */
3891         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3892                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3893
3894         /* Turn RX scramble payload only the 64/66 scrambler */
3895         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3896                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3897
3898         /* Set and clear loopback to cause a reset to 64/66 decoder */
3899         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3901         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3902                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3903
3904 }
3905
3906 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3907                                        struct link_params *params,
3908                                        u8 is_xfi)
3909 {
3910         struct bnx2x *bp = params->bp;
3911         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3912         /* Hold rxSeqStart */
3913         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3914                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3915
3916         /* Hold tx_fifo_reset */
3917         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3918                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3919
3920         /* Disable CL73 AN */
3921         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3922
3923         /* Disable 100FX Enable and Auto-Detect */
3924         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3925                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3926
3927         /* Disable 100FX Idle detect */
3928         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3929                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3930
3931         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3932         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3933                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3934
3935         /* Turn off auto-detect & fiber mode */
3936         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3937                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3938                                   0xFFEE);
3939
3940         /* Set filter_force_link, disable_false_link and parallel_detect */
3941         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3942                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3943         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3944                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3945                          ((val | 0x0006) & 0xFFFE));
3946
3947         /* Set XFI / SFI */
3948         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3949                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3950
3951         misc1_val &= ~(0x1f);
3952
3953         if (is_xfi) {
3954                 misc1_val |= 0x5;
3955                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3956                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3957                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3958                 tx_driver_val =
3959                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3960                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3961                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3962
3963         } else {
3964                 misc1_val |= 0x9;
3965                 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3966                            (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3967                            (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3968                 tx_driver_val =
3969                       ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3970                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3971                        (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3972         }
3973         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3974                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3975
3976         /* Set Transmit PMD settings */
3977         lane = bnx2x_get_warpcore_lane(phy, params);
3978         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3979                          MDIO_WC_REG_TX_FIR_TAP,
3980                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3981         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3982                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3983                          tx_driver_val);
3984
3985         /* Enable fiber mode, enable and invert sig_det */
3986         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3987                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3988
3989         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3990         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3991                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3992
3993         bnx2x_warpcore_set_lpi_passthrough(phy, params);
3994
3995         /* 10G XFI Full Duplex */
3996         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3997                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3998
3999         /* Release tx_fifo_reset */
4000         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4001                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4002                                   0xFFFE);
4003         /* Release rxSeqStart */
4004         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4005                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4006 }
4007
4008 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4009                                              struct link_params *params)
4010 {
4011         u16 val;
4012         struct bnx2x *bp = params->bp;
4013         /* Set global registers, so set AER lane to 0 */
4014         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4015                           MDIO_AER_BLOCK_AER_REG, 0);
4016
4017         /* Disable sequencer */
4018         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4019                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4020
4021         bnx2x_set_aer_mmd(params, phy);
4022
4023         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4024                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4025         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4026                          MDIO_AN_REG_CTRL, 0);
4027         /* Turn off CL73 */
4028         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4029                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4030         val &= ~(1<<5);
4031         val |= (1<<6);
4032         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4033                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4034
4035         /* Set 20G KR2 force speed */
4036         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4037                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4038
4039         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4040                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4041
4042         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4043                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4044         val &= ~(3<<14);
4045         val |= (1<<15);
4046         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4048         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4049                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4050
4051         /* Enable sequencer (over lane 0) */
4052         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4053                           MDIO_AER_BLOCK_AER_REG, 0);
4054
4055         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4056                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4057
4058         bnx2x_set_aer_mmd(params, phy);
4059 }
4060
4061 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4062                                          struct bnx2x_phy *phy,
4063                                          u16 lane)
4064 {
4065         /* Rx0 anaRxControl1G */
4066         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4068
4069         /* Rx2 anaRxControl1G */
4070         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4071                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4072
4073         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4074                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4075
4076         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4077                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4078
4079         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4080                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4081
4082         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4083                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4084
4085         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4087
4088         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4089                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4090
4091         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4093
4094         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4096
4097         /* Serdes Digital Misc1 */
4098         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4099                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4100
4101         /* Serdes Digital4 Misc3 */
4102         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4103                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4104
4105         /* Set Transmit PMD settings */
4106         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107                          MDIO_WC_REG_TX_FIR_TAP,
4108                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4109                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4110                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4111                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4112         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4113                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4114                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4115                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4116                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4117 }
4118
4119 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4120                                            struct link_params *params,
4121                                            u8 fiber_mode,
4122                                            u8 always_autoneg)
4123 {
4124         struct bnx2x *bp = params->bp;
4125         u16 val16, digctrl_kx1, digctrl_kx2;
4126
4127         /* Clear XFI clock comp in non-10G single lane mode. */
4128         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4129                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4130
4131         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4132
4133         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4134                 /* SGMII Autoneg */
4135                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4136                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4137                                          0x1000);
4138                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4139         } else {
4140                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4141                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4142                 val16 &= 0xcebf;
4143                 switch (phy->req_line_speed) {
4144                 case SPEED_10:
4145                         break;
4146                 case SPEED_100:
4147                         val16 |= 0x2000;
4148                         break;
4149                 case SPEED_1000:
4150                         val16 |= 0x0040;
4151                         break;
4152                 default:
4153                         DP(NETIF_MSG_LINK,
4154                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4155                         return;
4156                 }
4157
4158                 if (phy->req_duplex == DUPLEX_FULL)
4159                         val16 |= 0x0100;
4160
4161                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4162                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4163
4164                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4165                                phy->req_line_speed);
4166                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4167                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4168                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4169         }
4170
4171         /* SGMII Slave mode and disable signal detect */
4172         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4173                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4174         if (fiber_mode)
4175                 digctrl_kx1 = 1;
4176         else
4177                 digctrl_kx1 &= 0xff4a;
4178
4179         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4181                         digctrl_kx1);
4182
4183         /* Turn off parallel detect */
4184         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4185                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4186         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4187                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4188                         (digctrl_kx2 & ~(1<<2)));
4189
4190         /* Re-enable parallel detect */
4191         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4192                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4193                         (digctrl_kx2 | (1<<2)));
4194
4195         /* Enable autodet */
4196         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4197                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4198                         (digctrl_kx1 | 0x10));
4199 }
4200
4201 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4202                                       struct bnx2x_phy *phy,
4203                                       u8 reset)
4204 {
4205         u16 val;
4206         /* Take lane out of reset after configuration is finished */
4207         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4208                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4209         if (reset)
4210                 val |= 0xC000;
4211         else
4212                 val &= 0x3FFF;
4213         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4214                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4215         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4216                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4217 }
4218 /* Clear SFI/XFI link settings registers */
4219 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4220                                       struct link_params *params,
4221                                       u16 lane)
4222 {
4223         struct bnx2x *bp = params->bp;
4224         u16 i;
4225         static struct bnx2x_reg_set wc_regs[] = {
4226                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4227                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4228                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4229                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4230                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4231                         0x0195},
4232                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4233                         0x0007},
4234                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4235                         0x0002},
4236                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4237                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4238                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4239                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4240         };
4241         /* Set XFI clock comp as default. */
4242         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4243                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4244
4245         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4246                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4247                                  wc_regs[i].val);
4248
4249         lane = bnx2x_get_warpcore_lane(phy, params);
4250         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4251                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4252
4253 }
4254
4255 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4256                                                 u32 chip_id,
4257                                                 u32 shmem_base, u8 port,
4258                                                 u8 *gpio_num, u8 *gpio_port)
4259 {
4260         u32 cfg_pin;
4261         *gpio_num = 0;
4262         *gpio_port = 0;
4263         if (CHIP_IS_E3(bp)) {
4264                 cfg_pin = (REG_RD(bp, shmem_base +
4265                                 offsetof(struct shmem_region,
4266                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4267                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4268                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4269
4270                 /* Should not happen. This function called upon interrupt
4271                  * triggered by GPIO ( since EPIO can only generate interrupts
4272                  * to MCP).
4273                  * So if this function was called and none of the GPIOs was set,
4274                  * it means the shit hit the fan.
4275                  */
4276                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4277                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4278                         DP(NETIF_MSG_LINK,
4279                            "No cfg pin %x for module detect indication\n",
4280                            cfg_pin);
4281                         return -EINVAL;
4282                 }
4283
4284                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4285                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4286         } else {
4287                 *gpio_num = MISC_REGISTERS_GPIO_3;
4288                 *gpio_port = port;
4289         }
4290
4291         return 0;
4292 }
4293
4294 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4295                                        struct link_params *params)
4296 {
4297         struct bnx2x *bp = params->bp;
4298         u8 gpio_num, gpio_port;
4299         u32 gpio_val;
4300         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4301                                       params->shmem_base, params->port,
4302                                       &gpio_num, &gpio_port) != 0)
4303                 return 0;
4304         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4305
4306         /* Call the handling function in case module is detected */
4307         if (gpio_val == 0)
4308                 return 1;
4309         else
4310                 return 0;
4311 }
4312 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4313                                      struct link_params *params)
4314 {
4315         u16 gp2_status_reg0, lane;
4316         struct bnx2x *bp = params->bp;
4317
4318         lane = bnx2x_get_warpcore_lane(phy, params);
4319
4320         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4321                                  &gp2_status_reg0);
4322
4323         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4324 }
4325
4326 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4327                                           struct link_params *params,
4328                                           struct link_vars *vars)
4329 {
4330         struct bnx2x *bp = params->bp;
4331         u32 serdes_net_if;
4332         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4333         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4334
4335         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4336
4337         if (!vars->turn_to_run_wc_rt)
4338                 return;
4339
4340         /* Return if there is no link partner */
4341         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4342                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4343                 return;
4344         }
4345
4346         if (vars->rx_tx_asic_rst) {
4347                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4348                                 offsetof(struct shmem_region, dev_info.
4349                                 port_hw_config[params->port].default_cfg)) &
4350                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4351
4352                 switch (serdes_net_if) {
4353                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4354                         /* Do we get link yet? */
4355                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4356                                         &gp_status1);
4357                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4358                                 /*10G KR*/
4359                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4360
4361                         DP(NETIF_MSG_LINK,
4362                                 "gp_status1 0x%x\n", gp_status1);
4363
4364                         if (lnkup_kr || lnkup) {
4365                                         vars->rx_tx_asic_rst = 0;
4366                                         DP(NETIF_MSG_LINK,
4367                                         "link up, rx_tx_asic_rst 0x%x\n",
4368                                         vars->rx_tx_asic_rst);
4369                         } else {
4370                                 /* Reset the lane to see if link comes up.*/
4371                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4372                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4373
4374                                 /* Restart Autoneg */
4375                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4376                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4377
4378                                 vars->rx_tx_asic_rst--;
4379                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4380                                 vars->rx_tx_asic_rst);
4381                         }
4382                         break;
4383
4384                 default:
4385                         break;
4386                 }
4387
4388         } /*params->rx_tx_asic_rst*/
4389
4390 }
4391 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4392                                       struct link_params *params)
4393 {
4394         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4395         struct bnx2x *bp = params->bp;
4396         bnx2x_warpcore_clear_regs(phy, params, lane);
4397         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4398              SPEED_10000) &&
4399             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4400                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4401                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4402         } else {
4403                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4404                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4405         }
4406 }
4407
4408 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4409                                          struct bnx2x_phy *phy,
4410                                          u8 tx_en)
4411 {
4412         struct bnx2x *bp = params->bp;
4413         u32 cfg_pin;
4414         u8 port = params->port;
4415
4416         cfg_pin = REG_RD(bp, params->shmem_base +
4417                          offsetof(struct shmem_region,
4418                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4419                 PORT_HW_CFG_E3_TX_LASER_MASK;
4420         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4421         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4422
4423         /* For 20G, the expected pin to be used is 3 pins after the current */
4424         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4425         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4426                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4427 }
4428
4429 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4430                                        struct link_params *params,
4431                                        struct link_vars *vars)
4432 {
4433         struct bnx2x *bp = params->bp;
4434         u32 serdes_net_if;
4435         u8 fiber_mode;
4436         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4437         serdes_net_if = (REG_RD(bp, params->shmem_base +
4438                          offsetof(struct shmem_region, dev_info.
4439                                   port_hw_config[params->port].default_cfg)) &
4440                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4441         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4442                            "serdes_net_if = 0x%x\n",
4443                        vars->line_speed, serdes_net_if);
4444         bnx2x_set_aer_mmd(params, phy);
4445         bnx2x_warpcore_reset_lane(bp, phy, 1);
4446         vars->phy_flags |= PHY_XGXS_FLAG;
4447         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4448             (phy->req_line_speed &&
4449              ((phy->req_line_speed == SPEED_100) ||
4450               (phy->req_line_speed == SPEED_10)))) {
4451                 vars->phy_flags |= PHY_SGMII_FLAG;
4452                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4453                 bnx2x_warpcore_clear_regs(phy, params, lane);
4454                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4455         } else {
4456                 switch (serdes_net_if) {
4457                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4458                         /* Enable KR Auto Neg */
4459                         if (params->loopback_mode != LOOPBACK_EXT)
4460                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4461                         else {
4462                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4463                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4464                         }
4465                         break;
4466
4467                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4468                         bnx2x_warpcore_clear_regs(phy, params, lane);
4469                         if (vars->line_speed == SPEED_10000) {
4470                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4471                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4472                         } else {
4473                                 if (SINGLE_MEDIA_DIRECT(params)) {
4474                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4475                                         fiber_mode = 1;
4476                                 } else {
4477                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4478                                         fiber_mode = 0;
4479                                 }
4480                                 bnx2x_warpcore_set_sgmii_speed(phy,
4481                                                                 params,
4482                                                                 fiber_mode,
4483                                                                 0);
4484                         }
4485
4486                         break;
4487
4488                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4489                         /* Issue Module detection if module is plugged, or
4490                          * enabled transmitter to avoid current leakage in case
4491                          * no module is connected
4492                          */
4493                         if (bnx2x_is_sfp_module_plugged(phy, params))
4494                                 bnx2x_sfp_module_detection(phy, params);
4495                         else
4496                                 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
4497
4498                         bnx2x_warpcore_config_sfi(phy, params);
4499                         break;
4500
4501                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4502                         if (vars->line_speed != SPEED_20000) {
4503                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4504                                 return;
4505                         }
4506                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4507                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4508                         /* Issue Module detection */
4509
4510                         bnx2x_sfp_module_detection(phy, params);
4511                         break;
4512                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4513                         if (!params->loopback_mode) {
4514                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4515                         } else {
4516                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4517                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4518                         }
4519                         break;
4520                 default:
4521                         DP(NETIF_MSG_LINK,
4522                            "Unsupported Serdes Net Interface 0x%x\n",
4523                            serdes_net_if);
4524                         return;
4525                 }
4526         }
4527
4528         /* Take lane out of reset after configuration is finished */
4529         bnx2x_warpcore_reset_lane(bp, phy, 0);
4530         DP(NETIF_MSG_LINK, "Exit config init\n");
4531 }
4532
4533 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4534                                       struct link_params *params)
4535 {
4536         struct bnx2x *bp = params->bp;
4537         u16 val16, lane;
4538         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4539         bnx2x_set_mdio_emac_per_phy(bp, params);
4540         bnx2x_set_aer_mmd(params, phy);
4541         /* Global register */
4542         bnx2x_warpcore_reset_lane(bp, phy, 1);
4543
4544         /* Clear loopback settings (if any) */
4545         /* 10G & 20G */
4546         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4547                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4548
4549         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4550                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4551
4552         /* Update those 1-copy registers */
4553         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4554                           MDIO_AER_BLOCK_AER_REG, 0);
4555         /* Enable 1G MDIO (1-copy) */
4556         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4557                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4558                                   ~0x10);
4559
4560         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4561                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4562         lane = bnx2x_get_warpcore_lane(phy, params);
4563         /* Disable CL36 PCS Tx */
4564         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4565                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4566         val16 |= (0x11 << lane);
4567         if (phy->flags & FLAGS_WC_DUAL_MODE)
4568                 val16 |= (0x22 << lane);
4569         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4570                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4571
4572         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4573                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4574         val16 &= ~(0x0303 << (lane << 1));
4575         val16 |= (0x0101 << (lane << 1));
4576         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4577                 val16 &= ~(0x0c0c << (lane << 1));
4578                 val16 |= (0x0404 << (lane << 1));
4579         }
4580
4581         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4582                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4583         /* Restore AER */
4584         bnx2x_set_aer_mmd(params, phy);
4585
4586 }
4587
4588 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4589                                         struct link_params *params)
4590 {
4591         struct bnx2x *bp = params->bp;
4592         u16 val16;
4593         u32 lane;
4594         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4595                        params->loopback_mode, phy->req_line_speed);
4596
4597         if (phy->req_line_speed < SPEED_10000 ||
4598             phy->supported & SUPPORTED_20000baseKR2_Full) {
4599                 /* 10/100/1000/20G-KR2 */
4600
4601                 /* Update those 1-copy registers */
4602                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4603                                   MDIO_AER_BLOCK_AER_REG, 0);
4604                 /* Enable 1G MDIO (1-copy) */
4605                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4606                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4607                                          0x10);
4608                 /* Set 1G loopback based on lane (1-copy) */
4609                 lane = bnx2x_get_warpcore_lane(phy, params);
4610                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4611                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4612                 val16 |= (1<<lane);
4613                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4614                         val16 |= (2<<lane);
4615                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4616                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4617                                  val16);
4618
4619                 /* Switch back to 4-copy registers */
4620                 bnx2x_set_aer_mmd(params, phy);
4621         } else {
4622                 /* 10G / 20G-DXGXS */
4623                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4624                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4625                                          0x4000);
4626                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4627                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4628         }
4629 }
4630
4631
4632
4633 static void bnx2x_sync_link(struct link_params *params,
4634                              struct link_vars *vars)
4635 {
4636         struct bnx2x *bp = params->bp;
4637         u8 link_10g_plus;
4638         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4639                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4640         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4641         if (vars->link_up) {
4642                 DP(NETIF_MSG_LINK, "phy link up\n");
4643
4644                 vars->phy_link_up = 1;
4645                 vars->duplex = DUPLEX_FULL;
4646                 switch (vars->link_status &
4647                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4648                 case LINK_10THD:
4649                         vars->duplex = DUPLEX_HALF;
4650                         /* Fall thru */
4651                 case LINK_10TFD:
4652                         vars->line_speed = SPEED_10;
4653                         break;
4654
4655                 case LINK_100TXHD:
4656                         vars->duplex = DUPLEX_HALF;
4657                         /* Fall thru */
4658                 case LINK_100T4:
4659                 case LINK_100TXFD:
4660                         vars->line_speed = SPEED_100;
4661                         break;
4662
4663                 case LINK_1000THD:
4664                         vars->duplex = DUPLEX_HALF;
4665                         /* Fall thru */
4666                 case LINK_1000TFD:
4667                         vars->line_speed = SPEED_1000;
4668                         break;
4669
4670                 case LINK_2500THD:
4671                         vars->duplex = DUPLEX_HALF;
4672                         /* Fall thru */
4673                 case LINK_2500TFD:
4674                         vars->line_speed = SPEED_2500;
4675                         break;
4676
4677                 case LINK_10GTFD:
4678                         vars->line_speed = SPEED_10000;
4679                         break;
4680                 case LINK_20GTFD:
4681                         vars->line_speed = SPEED_20000;
4682                         break;
4683                 default:
4684                         break;
4685                 }
4686                 vars->flow_ctrl = 0;
4687                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4688                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4689
4690                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4691                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4692
4693                 if (!vars->flow_ctrl)
4694                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4695
4696                 if (vars->line_speed &&
4697                     ((vars->line_speed == SPEED_10) ||
4698                      (vars->line_speed == SPEED_100))) {
4699                         vars->phy_flags |= PHY_SGMII_FLAG;
4700                 } else {
4701                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4702                 }
4703                 if (vars->line_speed &&
4704                     USES_WARPCORE(bp) &&
4705                     (vars->line_speed == SPEED_1000))
4706                         vars->phy_flags |= PHY_SGMII_FLAG;
4707                 /* Anything 10 and over uses the bmac */
4708                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4709
4710                 if (link_10g_plus) {
4711                         if (USES_WARPCORE(bp))
4712                                 vars->mac_type = MAC_TYPE_XMAC;
4713                         else
4714                                 vars->mac_type = MAC_TYPE_BMAC;
4715                 } else {
4716                         if (USES_WARPCORE(bp))
4717                                 vars->mac_type = MAC_TYPE_UMAC;
4718                         else
4719                                 vars->mac_type = MAC_TYPE_EMAC;
4720                 }
4721         } else { /* Link down */
4722                 DP(NETIF_MSG_LINK, "phy link down\n");
4723
4724                 vars->phy_link_up = 0;
4725
4726                 vars->line_speed = 0;
4727                 vars->duplex = DUPLEX_FULL;
4728                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4729
4730                 /* Indicate no mac active */
4731                 vars->mac_type = MAC_TYPE_NONE;
4732                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4733                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4734                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4735                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4736         }
4737 }
4738
4739 void bnx2x_link_status_update(struct link_params *params,
4740                               struct link_vars *vars)
4741 {
4742         struct bnx2x *bp = params->bp;
4743         u8 port = params->port;
4744         u32 sync_offset, media_types;
4745         /* Update PHY configuration */
4746         set_phy_vars(params, vars);
4747
4748         vars->link_status = REG_RD(bp, params->shmem_base +
4749                                    offsetof(struct shmem_region,
4750                                             port_mb[port].link_status));
4751
4752         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4753         if (bp->link_params.loopback_mode != LOOPBACK_NONE &&
4754             bp->link_params.loopback_mode != LOOPBACK_EXT)
4755                 vars->link_status |= LINK_STATUS_LINK_UP;
4756
4757         if (bnx2x_eee_has_cap(params))
4758                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4759                                           offsetof(struct shmem2_region,
4760                                                    eee_status[params->port]));
4761
4762         vars->phy_flags = PHY_XGXS_FLAG;
4763         bnx2x_sync_link(params, vars);
4764         /* Sync media type */
4765         sync_offset = params->shmem_base +
4766                         offsetof(struct shmem_region,
4767                                  dev_info.port_hw_config[port].media_type);
4768         media_types = REG_RD(bp, sync_offset);
4769
4770         params->phy[INT_PHY].media_type =
4771                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4772                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4773         params->phy[EXT_PHY1].media_type =
4774                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4775                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4776         params->phy[EXT_PHY2].media_type =
4777                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4778                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4779         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4780
4781         /* Sync AEU offset */
4782         sync_offset = params->shmem_base +
4783                         offsetof(struct shmem_region,
4784                                  dev_info.port_hw_config[port].aeu_int_mask);
4785
4786         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4787
4788         /* Sync PFC status */
4789         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4790                 params->feature_config_flags |=
4791                                         FEATURE_CONFIG_PFC_ENABLED;
4792         else
4793                 params->feature_config_flags &=
4794                                         ~FEATURE_CONFIG_PFC_ENABLED;
4795
4796         if (SHMEM2_HAS(bp, link_attr_sync))
4797                 vars->link_attr_sync = SHMEM2_RD(bp,
4798                                                  link_attr_sync[params->port]);
4799
4800         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4801                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4802         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4803                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4804 }
4805
4806 static void bnx2x_set_master_ln(struct link_params *params,
4807                                 struct bnx2x_phy *phy)
4808 {
4809         struct bnx2x *bp = params->bp;
4810         u16 new_master_ln, ser_lane;
4811         ser_lane = ((params->lane_config &
4812                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4813                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4814
4815         /* Set the master_ln for AN */
4816         CL22_RD_OVER_CL45(bp, phy,
4817                           MDIO_REG_BANK_XGXS_BLOCK2,
4818                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4819                           &new_master_ln);
4820
4821         CL22_WR_OVER_CL45(bp, phy,
4822                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4823                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4824                           (new_master_ln | ser_lane));
4825 }
4826
4827 static int bnx2x_reset_unicore(struct link_params *params,
4828                                struct bnx2x_phy *phy,
4829                                u8 set_serdes)
4830 {
4831         struct bnx2x *bp = params->bp;
4832         u16 mii_control;
4833         u16 i;
4834         CL22_RD_OVER_CL45(bp, phy,
4835                           MDIO_REG_BANK_COMBO_IEEE0,
4836                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4837
4838         /* Reset the unicore */
4839         CL22_WR_OVER_CL45(bp, phy,
4840                           MDIO_REG_BANK_COMBO_IEEE0,
4841                           MDIO_COMBO_IEEE0_MII_CONTROL,
4842                           (mii_control |
4843                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4844         if (set_serdes)
4845                 bnx2x_set_serdes_access(bp, params->port);
4846
4847         /* Wait for the reset to self clear */
4848         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4849                 udelay(5);
4850
4851                 /* The reset erased the previous bank value */
4852                 CL22_RD_OVER_CL45(bp, phy,
4853                                   MDIO_REG_BANK_COMBO_IEEE0,
4854                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4855                                   &mii_control);
4856
4857                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4858                         udelay(5);
4859                         return 0;
4860                 }
4861         }
4862
4863         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4864                               " Port %d\n",
4865                          params->port);
4866         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4867         return -EINVAL;
4868
4869 }
4870
4871 static void bnx2x_set_swap_lanes(struct link_params *params,
4872                                  struct bnx2x_phy *phy)
4873 {
4874         struct bnx2x *bp = params->bp;
4875         /* Each two bits represents a lane number:
4876          * No swap is 0123 => 0x1b no need to enable the swap
4877          */
4878         u16 rx_lane_swap, tx_lane_swap;
4879
4880         rx_lane_swap = ((params->lane_config &
4881                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4882                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4883         tx_lane_swap = ((params->lane_config &
4884                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4885                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4886
4887         if (rx_lane_swap != 0x1b) {
4888                 CL22_WR_OVER_CL45(bp, phy,
4889                                   MDIO_REG_BANK_XGXS_BLOCK2,
4890                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4891                                   (rx_lane_swap |
4892                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4893                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4894         } else {
4895                 CL22_WR_OVER_CL45(bp, phy,
4896                                   MDIO_REG_BANK_XGXS_BLOCK2,
4897                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4898         }
4899
4900         if (tx_lane_swap != 0x1b) {
4901                 CL22_WR_OVER_CL45(bp, phy,
4902                                   MDIO_REG_BANK_XGXS_BLOCK2,
4903                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4904                                   (tx_lane_swap |
4905                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4906         } else {
4907                 CL22_WR_OVER_CL45(bp, phy,
4908                                   MDIO_REG_BANK_XGXS_BLOCK2,
4909                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4910         }
4911 }
4912
4913 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4914                                          struct link_params *params)
4915 {
4916         struct bnx2x *bp = params->bp;
4917         u16 control2;
4918         CL22_RD_OVER_CL45(bp, phy,
4919                           MDIO_REG_BANK_SERDES_DIGITAL,
4920                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4921                           &control2);
4922         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4923                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4924         else
4925                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4926         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4927                 phy->speed_cap_mask, control2);
4928         CL22_WR_OVER_CL45(bp, phy,
4929                           MDIO_REG_BANK_SERDES_DIGITAL,
4930                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4931                           control2);
4932
4933         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4934              (phy->speed_cap_mask &
4935                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4936                 DP(NETIF_MSG_LINK, "XGXS\n");
4937
4938                 CL22_WR_OVER_CL45(bp, phy,
4939                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4940                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4941                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4942
4943                 CL22_RD_OVER_CL45(bp, phy,
4944                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4945                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4946                                   &control2);
4947
4948
4949                 control2 |=
4950                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4951
4952                 CL22_WR_OVER_CL45(bp, phy,
4953                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4954                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4955                                   control2);
4956
4957                 /* Disable parallel detection of HiG */
4958                 CL22_WR_OVER_CL45(bp, phy,
4959                                   MDIO_REG_BANK_XGXS_BLOCK2,
4960                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4961                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4962                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4963         }
4964 }
4965
4966 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4967                               struct link_params *params,
4968                               struct link_vars *vars,
4969                               u8 enable_cl73)
4970 {
4971         struct bnx2x *bp = params->bp;
4972         u16 reg_val;
4973
4974         /* CL37 Autoneg */
4975         CL22_RD_OVER_CL45(bp, phy,
4976                           MDIO_REG_BANK_COMBO_IEEE0,
4977                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4978
4979         /* CL37 Autoneg Enabled */
4980         if (vars->line_speed == SPEED_AUTO_NEG)
4981                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4982         else /* CL37 Autoneg Disabled */
4983                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4984                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4985
4986         CL22_WR_OVER_CL45(bp, phy,
4987                           MDIO_REG_BANK_COMBO_IEEE0,
4988                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4989
4990         /* Enable/Disable Autodetection */
4991
4992         CL22_RD_OVER_CL45(bp, phy,
4993                           MDIO_REG_BANK_SERDES_DIGITAL,
4994                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4995         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4996                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4997         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4998         if (vars->line_speed == SPEED_AUTO_NEG)
4999                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5000         else
5001                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5002
5003         CL22_WR_OVER_CL45(bp, phy,
5004                           MDIO_REG_BANK_SERDES_DIGITAL,
5005                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5006
5007         /* Enable TetonII and BAM autoneg */
5008         CL22_RD_OVER_CL45(bp, phy,
5009                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5010                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5011                           &reg_val);
5012         if (vars->line_speed == SPEED_AUTO_NEG) {
5013                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5014                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5015                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5016         } else {
5017                 /* TetonII and BAM Autoneg Disabled */
5018                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5019                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5020         }
5021         CL22_WR_OVER_CL45(bp, phy,
5022                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5023                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5024                           reg_val);
5025
5026         if (enable_cl73) {
5027                 /* Enable Cl73 FSM status bits */
5028                 CL22_WR_OVER_CL45(bp, phy,
5029                                   MDIO_REG_BANK_CL73_USERB0,
5030                                   MDIO_CL73_USERB0_CL73_UCTRL,
5031                                   0xe);
5032
5033                 /* Enable BAM Station Manager*/
5034                 CL22_WR_OVER_CL45(bp, phy,
5035                         MDIO_REG_BANK_CL73_USERB0,
5036                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5037                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5038                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5039                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5040
5041                 /* Advertise CL73 link speeds */
5042                 CL22_RD_OVER_CL45(bp, phy,
5043                                   MDIO_REG_BANK_CL73_IEEEB1,
5044                                   MDIO_CL73_IEEEB1_AN_ADV2,
5045                                   &reg_val);
5046                 if (phy->speed_cap_mask &
5047                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5048                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5049                 if (phy->speed_cap_mask &
5050                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5051                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5052
5053                 CL22_WR_OVER_CL45(bp, phy,
5054                                   MDIO_REG_BANK_CL73_IEEEB1,
5055                                   MDIO_CL73_IEEEB1_AN_ADV2,
5056                                   reg_val);
5057
5058                 /* CL73 Autoneg Enabled */
5059                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5060
5061         } else /* CL73 Autoneg Disabled */
5062                 reg_val = 0;
5063
5064         CL22_WR_OVER_CL45(bp, phy,
5065                           MDIO_REG_BANK_CL73_IEEEB0,
5066                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5067 }
5068
5069 /* Program SerDes, forced speed */
5070 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5071                                  struct link_params *params,
5072                                  struct link_vars *vars)
5073 {
5074         struct bnx2x *bp = params->bp;
5075         u16 reg_val;
5076
5077         /* Program duplex, disable autoneg and sgmii*/
5078         CL22_RD_OVER_CL45(bp, phy,
5079                           MDIO_REG_BANK_COMBO_IEEE0,
5080                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5081         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5082                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5083                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5084         if (phy->req_duplex == DUPLEX_FULL)
5085                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5086         CL22_WR_OVER_CL45(bp, phy,
5087                           MDIO_REG_BANK_COMBO_IEEE0,
5088                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5089
5090         /* Program speed
5091          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5092          */
5093         CL22_RD_OVER_CL45(bp, phy,
5094                           MDIO_REG_BANK_SERDES_DIGITAL,
5095                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5096         /* Clearing the speed value before setting the right speed */
5097         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5098
5099         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5100                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5101
5102         if (!((vars->line_speed == SPEED_1000) ||
5103               (vars->line_speed == SPEED_100) ||
5104               (vars->line_speed == SPEED_10))) {
5105
5106                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5107                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5108                 if (vars->line_speed == SPEED_10000)
5109                         reg_val |=
5110                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5111         }
5112
5113         CL22_WR_OVER_CL45(bp, phy,
5114                           MDIO_REG_BANK_SERDES_DIGITAL,
5115                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5116
5117 }
5118
5119 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5120                                               struct link_params *params)
5121 {
5122         struct bnx2x *bp = params->bp;
5123         u16 val = 0;
5124
5125         /* Set extended capabilities */
5126         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5127                 val |= MDIO_OVER_1G_UP1_2_5G;
5128         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5129                 val |= MDIO_OVER_1G_UP1_10G;
5130         CL22_WR_OVER_CL45(bp, phy,
5131                           MDIO_REG_BANK_OVER_1G,
5132                           MDIO_OVER_1G_UP1, val);
5133
5134         CL22_WR_OVER_CL45(bp, phy,
5135                           MDIO_REG_BANK_OVER_1G,
5136                           MDIO_OVER_1G_UP3, 0x400);
5137 }
5138
5139 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5140                                               struct link_params *params,
5141                                               u16 ieee_fc)
5142 {
5143         struct bnx2x *bp = params->bp;
5144         u16 val;
5145         /* For AN, we are always publishing full duplex */
5146
5147         CL22_WR_OVER_CL45(bp, phy,
5148                           MDIO_REG_BANK_COMBO_IEEE0,
5149                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5150         CL22_RD_OVER_CL45(bp, phy,
5151                           MDIO_REG_BANK_CL73_IEEEB1,
5152                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5153         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5154         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5155         CL22_WR_OVER_CL45(bp, phy,
5156                           MDIO_REG_BANK_CL73_IEEEB1,
5157                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5158 }
5159
5160 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5161                                   struct link_params *params,
5162                                   u8 enable_cl73)
5163 {
5164         struct bnx2x *bp = params->bp;
5165         u16 mii_control;
5166
5167         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5168         /* Enable and restart BAM/CL37 aneg */
5169
5170         if (enable_cl73) {
5171                 CL22_RD_OVER_CL45(bp, phy,
5172                                   MDIO_REG_BANK_CL73_IEEEB0,
5173                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5174                                   &mii_control);
5175
5176                 CL22_WR_OVER_CL45(bp, phy,
5177                                   MDIO_REG_BANK_CL73_IEEEB0,
5178                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5179                                   (mii_control |
5180                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5181                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5182         } else {
5183
5184                 CL22_RD_OVER_CL45(bp, phy,
5185                                   MDIO_REG_BANK_COMBO_IEEE0,
5186                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5187                                   &mii_control);
5188                 DP(NETIF_MSG_LINK,
5189                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5190                          mii_control);
5191                 CL22_WR_OVER_CL45(bp, phy,
5192                                   MDIO_REG_BANK_COMBO_IEEE0,
5193                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5194                                   (mii_control |
5195                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5196                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5197         }
5198 }
5199
5200 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5201                                            struct link_params *params,
5202                                            struct link_vars *vars)
5203 {
5204         struct bnx2x *bp = params->bp;
5205         u16 control1;
5206
5207         /* In SGMII mode, the unicore is always slave */
5208
5209         CL22_RD_OVER_CL45(bp, phy,
5210                           MDIO_REG_BANK_SERDES_DIGITAL,
5211                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5212                           &control1);
5213         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5214         /* Set sgmii mode (and not fiber) */
5215         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5216                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5217                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5218         CL22_WR_OVER_CL45(bp, phy,
5219                           MDIO_REG_BANK_SERDES_DIGITAL,
5220                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5221                           control1);
5222
5223         /* If forced speed */
5224         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5225                 /* Set speed, disable autoneg */
5226                 u16 mii_control;
5227
5228                 CL22_RD_OVER_CL45(bp, phy,
5229                                   MDIO_REG_BANK_COMBO_IEEE0,
5230                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5231                                   &mii_control);
5232                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5233                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5234                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5235
5236                 switch (vars->line_speed) {
5237                 case SPEED_100:
5238                         mii_control |=
5239                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5240                         break;
5241                 case SPEED_1000:
5242                         mii_control |=
5243                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5244                         break;
5245                 case SPEED_10:
5246                         /* There is nothing to set for 10M */
5247                         break;
5248                 default:
5249                         /* Invalid speed for SGMII */
5250                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5251                                   vars->line_speed);
5252                         break;
5253                 }
5254
5255                 /* Setting the full duplex */
5256                 if (phy->req_duplex == DUPLEX_FULL)
5257                         mii_control |=
5258                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5259                 CL22_WR_OVER_CL45(bp, phy,
5260                                   MDIO_REG_BANK_COMBO_IEEE0,
5261                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5262                                   mii_control);
5263
5264         } else { /* AN mode */
5265                 /* Enable and restart AN */
5266                 bnx2x_restart_autoneg(phy, params, 0);
5267         }
5268 }
5269
5270 /* Link management
5271  */
5272 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5273                                              struct link_params *params)
5274 {
5275         struct bnx2x *bp = params->bp;
5276         u16 pd_10g, status2_1000x;
5277         if (phy->req_line_speed != SPEED_AUTO_NEG)
5278                 return 0;
5279         CL22_RD_OVER_CL45(bp, phy,
5280                           MDIO_REG_BANK_SERDES_DIGITAL,
5281                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5282                           &status2_1000x);
5283         CL22_RD_OVER_CL45(bp, phy,
5284                           MDIO_REG_BANK_SERDES_DIGITAL,
5285                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5286                           &status2_1000x);
5287         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5288                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5289                          params->port);
5290                 return 1;
5291         }
5292
5293         CL22_RD_OVER_CL45(bp, phy,
5294                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5295                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5296                           &pd_10g);
5297
5298         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5299                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5300                          params->port);
5301                 return 1;
5302         }
5303         return 0;
5304 }
5305
5306 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5307                                 struct link_params *params,
5308                                 struct link_vars *vars,
5309                                 u32 gp_status)
5310 {
5311         u16 ld_pause;   /* local driver */
5312         u16 lp_pause;   /* link partner */
5313         u16 pause_result;
5314         struct bnx2x *bp = params->bp;
5315         if ((gp_status &
5316              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5317               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5318             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5319              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5320
5321                 CL22_RD_OVER_CL45(bp, phy,
5322                                   MDIO_REG_BANK_CL73_IEEEB1,
5323                                   MDIO_CL73_IEEEB1_AN_ADV1,
5324                                   &ld_pause);
5325                 CL22_RD_OVER_CL45(bp, phy,
5326                                   MDIO_REG_BANK_CL73_IEEEB1,
5327                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5328                                   &lp_pause);
5329                 pause_result = (ld_pause &
5330                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5331                 pause_result |= (lp_pause &
5332                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5333                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5334         } else {
5335                 CL22_RD_OVER_CL45(bp, phy,
5336                                   MDIO_REG_BANK_COMBO_IEEE0,
5337                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5338                                   &ld_pause);
5339                 CL22_RD_OVER_CL45(bp, phy,
5340                         MDIO_REG_BANK_COMBO_IEEE0,
5341                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5342                         &lp_pause);
5343                 pause_result = (ld_pause &
5344                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5345                 pause_result |= (lp_pause &
5346                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5347                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5348         }
5349         bnx2x_pause_resolve(vars, pause_result);
5350
5351 }
5352
5353 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5354                                     struct link_params *params,
5355                                     struct link_vars *vars,
5356                                     u32 gp_status)
5357 {
5358         struct bnx2x *bp = params->bp;
5359         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5360
5361         /* Resolve from gp_status in case of AN complete and not sgmii */
5362         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5363                 /* Update the advertised flow-controled of LD/LP in AN */
5364                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5365                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5366                 /* But set the flow-control result as the requested one */
5367                 vars->flow_ctrl = phy->req_flow_ctrl;
5368         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5369                 vars->flow_ctrl = params->req_fc_auto_adv;
5370         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5371                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5372                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5373                         vars->flow_ctrl = params->req_fc_auto_adv;
5374                         return;
5375                 }
5376                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5377         }
5378         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5379 }
5380
5381 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5382                                          struct link_params *params)
5383 {
5384         struct bnx2x *bp = params->bp;
5385         u16 rx_status, ustat_val, cl37_fsm_received;
5386         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5387         /* Step 1: Make sure signal is detected */
5388         CL22_RD_OVER_CL45(bp, phy,
5389                           MDIO_REG_BANK_RX0,
5390                           MDIO_RX0_RX_STATUS,
5391                           &rx_status);
5392         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5393             (MDIO_RX0_RX_STATUS_SIGDET)) {
5394                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5395                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5396                 CL22_WR_OVER_CL45(bp, phy,
5397                                   MDIO_REG_BANK_CL73_IEEEB0,
5398                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5399                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5400                 return;
5401         }
5402         /* Step 2: Check CL73 state machine */
5403         CL22_RD_OVER_CL45(bp, phy,
5404                           MDIO_REG_BANK_CL73_USERB0,
5405                           MDIO_CL73_USERB0_CL73_USTAT1,
5406                           &ustat_val);
5407         if ((ustat_val &
5408              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5409               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5410             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5411               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5412                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5413                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5414                 return;
5415         }
5416         /* Step 3: Check CL37 Message Pages received to indicate LP
5417          * supports only CL37
5418          */
5419         CL22_RD_OVER_CL45(bp, phy,
5420                           MDIO_REG_BANK_REMOTE_PHY,
5421                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5422                           &cl37_fsm_received);
5423         if ((cl37_fsm_received &
5424              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5425              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5426             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5427               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5428                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5429                              "misc_rx_status(0x8330) = 0x%x\n",
5430                          cl37_fsm_received);
5431                 return;
5432         }
5433         /* The combined cl37/cl73 fsm state information indicating that
5434          * we are connected to a device which does not support cl73, but
5435          * does support cl37 BAM. In this case we disable cl73 and
5436          * restart cl37 auto-neg
5437          */
5438
5439         /* Disable CL73 */
5440         CL22_WR_OVER_CL45(bp, phy,
5441                           MDIO_REG_BANK_CL73_IEEEB0,
5442                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5443                           0);
5444         /* Restart CL37 autoneg */
5445         bnx2x_restart_autoneg(phy, params, 0);
5446         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5447 }
5448
5449 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5450                                   struct link_params *params,
5451                                   struct link_vars *vars,
5452                                   u32 gp_status)
5453 {
5454         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5455                 vars->link_status |=
5456                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5457
5458         if (bnx2x_direct_parallel_detect_used(phy, params))
5459                 vars->link_status |=
5460                         LINK_STATUS_PARALLEL_DETECTION_USED;
5461 }
5462 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5463                                      struct link_params *params,
5464                                       struct link_vars *vars,
5465                                       u16 is_link_up,
5466                                       u16 speed_mask,
5467                                       u16 is_duplex)
5468 {
5469         struct bnx2x *bp = params->bp;
5470         if (phy->req_line_speed == SPEED_AUTO_NEG)
5471                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5472         if (is_link_up) {
5473                 DP(NETIF_MSG_LINK, "phy link up\n");
5474
5475                 vars->phy_link_up = 1;
5476                 vars->link_status |= LINK_STATUS_LINK_UP;
5477
5478                 switch (speed_mask) {
5479                 case GP_STATUS_10M:
5480                         vars->line_speed = SPEED_10;
5481                         if (is_duplex == DUPLEX_FULL)
5482                                 vars->link_status |= LINK_10TFD;
5483                         else
5484                                 vars->link_status |= LINK_10THD;
5485                         break;
5486
5487                 case GP_STATUS_100M:
5488                         vars->line_speed = SPEED_100;
5489                         if (is_duplex == DUPLEX_FULL)
5490                                 vars->link_status |= LINK_100TXFD;
5491                         else
5492                                 vars->link_status |= LINK_100TXHD;
5493                         break;
5494
5495                 case GP_STATUS_1G:
5496                 case GP_STATUS_1G_KX:
5497                         vars->line_speed = SPEED_1000;
5498                         if (is_duplex == DUPLEX_FULL)
5499                                 vars->link_status |= LINK_1000TFD;
5500                         else
5501                                 vars->link_status |= LINK_1000THD;
5502                         break;
5503
5504                 case GP_STATUS_2_5G:
5505                         vars->line_speed = SPEED_2500;
5506                         if (is_duplex == DUPLEX_FULL)
5507                                 vars->link_status |= LINK_2500TFD;
5508                         else
5509                                 vars->link_status |= LINK_2500THD;
5510                         break;
5511
5512                 case GP_STATUS_5G:
5513                 case GP_STATUS_6G:
5514                         DP(NETIF_MSG_LINK,
5515                                  "link speed unsupported  gp_status 0x%x\n",
5516                                   speed_mask);
5517                         return -EINVAL;
5518
5519                 case GP_STATUS_10G_KX4:
5520                 case GP_STATUS_10G_HIG:
5521                 case GP_STATUS_10G_CX4:
5522                 case GP_STATUS_10G_KR:
5523                 case GP_STATUS_10G_SFI:
5524                 case GP_STATUS_10G_XFI:
5525                         vars->line_speed = SPEED_10000;
5526                         vars->link_status |= LINK_10GTFD;
5527                         break;
5528                 case GP_STATUS_20G_DXGXS:
5529                 case GP_STATUS_20G_KR2:
5530                         vars->line_speed = SPEED_20000;
5531                         vars->link_status |= LINK_20GTFD;
5532                         break;
5533                 default:
5534                         DP(NETIF_MSG_LINK,
5535                                   "link speed unsupported gp_status 0x%x\n",
5536                                   speed_mask);
5537                         return -EINVAL;
5538                 }
5539         } else { /* link_down */
5540                 DP(NETIF_MSG_LINK, "phy link down\n");
5541
5542                 vars->phy_link_up = 0;
5543
5544                 vars->duplex = DUPLEX_FULL;
5545                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5546                 vars->mac_type = MAC_TYPE_NONE;
5547         }
5548         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5549                     vars->phy_link_up, vars->line_speed);
5550         return 0;
5551 }
5552
5553 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5554                                       struct link_params *params,
5555                                       struct link_vars *vars)
5556 {
5557         struct bnx2x *bp = params->bp;
5558
5559         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5560         int rc = 0;
5561
5562         /* Read gp_status */
5563         CL22_RD_OVER_CL45(bp, phy,
5564                           MDIO_REG_BANK_GP_STATUS,
5565                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5566                           &gp_status);
5567         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5568                 duplex = DUPLEX_FULL;
5569         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5570                 link_up = 1;
5571         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5572         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5573                        gp_status, link_up, speed_mask);
5574         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5575                                          duplex);
5576         if (rc == -EINVAL)
5577                 return rc;
5578
5579         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5580                 if (SINGLE_MEDIA_DIRECT(params)) {
5581                         vars->duplex = duplex;
5582                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5583                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5584                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5585                                                       gp_status);
5586                 }
5587         } else { /* Link_down */
5588                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5589                     SINGLE_MEDIA_DIRECT(params)) {
5590                         /* Check signal is detected */
5591                         bnx2x_check_fallback_to_cl37(phy, params);
5592                 }
5593         }
5594
5595         /* Read LP advertised speeds*/
5596         if (SINGLE_MEDIA_DIRECT(params) &&
5597             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5598                 u16 val;
5599
5600                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5601                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5602
5603                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5604                         vars->link_status |=
5605                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5606                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5607                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5608                         vars->link_status |=
5609                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5610
5611                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5612                                   MDIO_OVER_1G_LP_UP1, &val);
5613
5614                 if (val & MDIO_OVER_1G_UP1_2_5G)
5615                         vars->link_status |=
5616                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5617                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5618                         vars->link_status |=
5619                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5620         }
5621
5622         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5623                    vars->duplex, vars->flow_ctrl, vars->link_status);
5624         return rc;
5625 }
5626
5627 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5628                                      struct link_params *params,
5629                                      struct link_vars *vars)
5630 {
5631         struct bnx2x *bp = params->bp;
5632         u8 lane;
5633         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5634         int rc = 0;
5635         lane = bnx2x_get_warpcore_lane(phy, params);
5636         /* Read gp_status */
5637         if ((params->loopback_mode) &&
5638             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5639                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5640                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5641                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5642                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5643                 link_up &= 0x1;
5644         } else if ((phy->req_line_speed > SPEED_10000) &&
5645                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5646                 u16 temp_link_up;
5647                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5648                                 1, &temp_link_up);
5649                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5650                                 1, &link_up);
5651                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5652                                temp_link_up, link_up);
5653                 link_up &= (1<<2);
5654                 if (link_up)
5655                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5656         } else {
5657                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5658                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5659                                 &gp_status1);
5660                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5661                 /* Check for either KR, 1G, or AN up. */
5662                 link_up = ((gp_status1 >> 8) |
5663                            (gp_status1 >> 12) |
5664                            (gp_status1)) &
5665                         (1 << lane);
5666                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5667                         u16 an_link;
5668                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5669                                         MDIO_AN_REG_STATUS, &an_link);
5670                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5671                                         MDIO_AN_REG_STATUS, &an_link);
5672                         link_up |= (an_link & (1<<2));
5673                 }
5674                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5675                         u16 pd, gp_status4;
5676                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5677                                 /* Check Autoneg complete */
5678                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5679                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5680                                                 &gp_status4);
5681                                 if (gp_status4 & ((1<<12)<<lane))
5682                                         vars->link_status |=
5683                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5684
5685                                 /* Check parallel detect used */
5686                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5687                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5688                                                 &pd);
5689                                 if (pd & (1<<15))
5690                                         vars->link_status |=
5691                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5692                         }
5693                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5694                         vars->duplex = duplex;
5695                 }
5696         }
5697
5698         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5699             SINGLE_MEDIA_DIRECT(params)) {
5700                 u16 val;
5701
5702                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5703                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5704
5705                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5706                         vars->link_status |=
5707                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5708                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5709                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5710                         vars->link_status |=
5711                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5712
5713                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5714                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5715
5716                 if (val & MDIO_OVER_1G_UP1_2_5G)
5717                         vars->link_status |=
5718                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5719                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5720                         vars->link_status |=
5721                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5722
5723         }
5724
5725
5726         if (lane < 2) {
5727                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5728                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5729         } else {
5730                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5731                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5732         }
5733         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5734
5735         if ((lane & 1) == 0)
5736                 gp_speed <<= 8;
5737         gp_speed &= 0x3f00;
5738         link_up = !!link_up;
5739
5740         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5741                                          duplex);
5742
5743         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5744                    vars->duplex, vars->flow_ctrl, vars->link_status);
5745         return rc;
5746 }
5747 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5748 {
5749         struct bnx2x *bp = params->bp;
5750         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5751         u16 lp_up2;
5752         u16 tx_driver;
5753         u16 bank;
5754
5755         /* Read precomp */
5756         CL22_RD_OVER_CL45(bp, phy,
5757                           MDIO_REG_BANK_OVER_1G,
5758                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5759
5760         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5761         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5762                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5763                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5764
5765         if (lp_up2 == 0)
5766                 return;
5767
5768         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5769               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5770                 CL22_RD_OVER_CL45(bp, phy,
5771                                   bank,
5772                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5773
5774                 /* Replace tx_driver bits [15:12] */
5775                 if (lp_up2 !=
5776                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5777                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5778                         tx_driver |= lp_up2;
5779                         CL22_WR_OVER_CL45(bp, phy,
5780                                           bank,
5781                                           MDIO_TX0_TX_DRIVER, tx_driver);
5782                 }
5783         }
5784 }
5785
5786 static int bnx2x_emac_program(struct link_params *params,
5787                               struct link_vars *vars)
5788 {
5789         struct bnx2x *bp = params->bp;
5790         u8 port = params->port;
5791         u16 mode = 0;
5792
5793         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5794         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5795                        EMAC_REG_EMAC_MODE,
5796                        (EMAC_MODE_25G_MODE |
5797                         EMAC_MODE_PORT_MII_10M |
5798                         EMAC_MODE_HALF_DUPLEX));
5799         switch (vars->line_speed) {
5800         case SPEED_10:
5801                 mode |= EMAC_MODE_PORT_MII_10M;
5802                 break;
5803
5804         case SPEED_100:
5805                 mode |= EMAC_MODE_PORT_MII;
5806                 break;
5807
5808         case SPEED_1000:
5809                 mode |= EMAC_MODE_PORT_GMII;
5810                 break;
5811
5812         case SPEED_2500:
5813                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5814                 break;
5815
5816         default:
5817                 /* 10G not valid for EMAC */
5818                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5819                            vars->line_speed);
5820                 return -EINVAL;
5821         }
5822
5823         if (vars->duplex == DUPLEX_HALF)
5824                 mode |= EMAC_MODE_HALF_DUPLEX;
5825         bnx2x_bits_en(bp,
5826                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5827                       mode);
5828
5829         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5830         return 0;
5831 }
5832
5833 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5834                                   struct link_params *params)
5835 {
5836
5837         u16 bank, i = 0;
5838         struct bnx2x *bp = params->bp;
5839
5840         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5841               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5842                         CL22_WR_OVER_CL45(bp, phy,
5843                                           bank,
5844                                           MDIO_RX0_RX_EQ_BOOST,
5845                                           phy->rx_preemphasis[i]);
5846         }
5847
5848         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5849                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5850                         CL22_WR_OVER_CL45(bp, phy,
5851                                           bank,
5852                                           MDIO_TX0_TX_DRIVER,
5853                                           phy->tx_preemphasis[i]);
5854         }
5855 }
5856
5857 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5858                                    struct link_params *params,
5859                                    struct link_vars *vars)
5860 {
5861         struct bnx2x *bp = params->bp;
5862         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5863                           (params->loopback_mode == LOOPBACK_XGXS));
5864         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5865                 if (SINGLE_MEDIA_DIRECT(params) &&
5866                     (params->feature_config_flags &
5867                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5868                         bnx2x_set_preemphasis(phy, params);
5869
5870                 /* Forced speed requested? */
5871                 if (vars->line_speed != SPEED_AUTO_NEG ||
5872                     (SINGLE_MEDIA_DIRECT(params) &&
5873                      params->loopback_mode == LOOPBACK_EXT)) {
5874                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5875
5876                         /* Disable autoneg */
5877                         bnx2x_set_autoneg(phy, params, vars, 0);
5878
5879                         /* Program speed and duplex */
5880                         bnx2x_program_serdes(phy, params, vars);
5881
5882                 } else { /* AN_mode */
5883                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5884
5885                         /* AN enabled */
5886                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5887
5888                         /* Program duplex & pause advertisement (for aneg) */
5889                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5890                                                           vars->ieee_fc);
5891
5892                         /* Enable autoneg */
5893                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5894
5895                         /* Enable and restart AN */
5896                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5897                 }
5898
5899         } else { /* SGMII mode */
5900                 DP(NETIF_MSG_LINK, "SGMII\n");
5901
5902                 bnx2x_initialize_sgmii_process(phy, params, vars);
5903         }
5904 }
5905
5906 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5907                           struct link_params *params,
5908                           struct link_vars *vars)
5909 {
5910         int rc;
5911         vars->phy_flags |= PHY_XGXS_FLAG;
5912         if ((phy->req_line_speed &&
5913              ((phy->req_line_speed == SPEED_100) ||
5914               (phy->req_line_speed == SPEED_10))) ||
5915             (!phy->req_line_speed &&
5916              (phy->speed_cap_mask >=
5917               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5918              (phy->speed_cap_mask <
5919               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5920             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5921                 vars->phy_flags |= PHY_SGMII_FLAG;
5922         else
5923                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5924
5925         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5926         bnx2x_set_aer_mmd(params, phy);
5927         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5928                 bnx2x_set_master_ln(params, phy);
5929
5930         rc = bnx2x_reset_unicore(params, phy, 0);
5931         /* Reset the SerDes and wait for reset bit return low */
5932         if (rc)
5933                 return rc;
5934
5935         bnx2x_set_aer_mmd(params, phy);
5936         /* Setting the masterLn_def again after the reset */
5937         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5938                 bnx2x_set_master_ln(params, phy);
5939                 bnx2x_set_swap_lanes(params, phy);
5940         }
5941
5942         return rc;
5943 }
5944
5945 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5946                                      struct bnx2x_phy *phy,
5947                                      struct link_params *params)
5948 {
5949         u16 cnt, ctrl;
5950         /* Wait for soft reset to get cleared up to 1 sec */
5951         for (cnt = 0; cnt < 1000; cnt++) {
5952                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5953                         bnx2x_cl22_read(bp, phy,
5954                                 MDIO_PMA_REG_CTRL, &ctrl);
5955                 else
5956                         bnx2x_cl45_read(bp, phy,
5957                                 MDIO_PMA_DEVAD,
5958                                 MDIO_PMA_REG_CTRL, &ctrl);
5959                 if (!(ctrl & (1<<15)))
5960                         break;
5961                 usleep_range(1000, 2000);
5962         }
5963
5964         if (cnt == 1000)
5965                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5966                                       " Port %d\n",
5967                          params->port);
5968         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5969         return cnt;
5970 }
5971
5972 static void bnx2x_link_int_enable(struct link_params *params)
5973 {
5974         u8 port = params->port;
5975         u32 mask;
5976         struct bnx2x *bp = params->bp;
5977
5978         /* Setting the status to report on link up for either XGXS or SerDes */
5979         if (CHIP_IS_E3(bp)) {
5980                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5981                 if (!(SINGLE_MEDIA_DIRECT(params)))
5982                         mask |= NIG_MASK_MI_INT;
5983         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5984                 mask = (NIG_MASK_XGXS0_LINK10G |
5985                         NIG_MASK_XGXS0_LINK_STATUS);
5986                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5987                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5988                         params->phy[INT_PHY].type !=
5989                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5990                         mask |= NIG_MASK_MI_INT;
5991                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5992                 }
5993
5994         } else { /* SerDes */
5995                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5996                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5997                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5998                         params->phy[INT_PHY].type !=
5999                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6000                         mask |= NIG_MASK_MI_INT;
6001                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6002                 }
6003         }
6004         bnx2x_bits_en(bp,
6005                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6006                       mask);
6007
6008         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6009                  (params->switch_cfg == SWITCH_CFG_10G),
6010                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6011         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6012                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6013                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6014                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6015         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6016            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6017            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6018 }
6019
6020 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6021                                      u8 exp_mi_int)
6022 {
6023         u32 latch_status = 0;
6024
6025         /* Disable the MI INT ( external phy int ) by writing 1 to the
6026          * status register. Link down indication is high-active-signal,
6027          * so in this case we need to write the status to clear the XOR
6028          */
6029         /* Read Latched signals */
6030         latch_status = REG_RD(bp,
6031                                     NIG_REG_LATCH_STATUS_0 + port*8);
6032         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6033         /* Handle only those with latched-signal=up.*/
6034         if (exp_mi_int)
6035                 bnx2x_bits_en(bp,
6036                               NIG_REG_STATUS_INTERRUPT_PORT0
6037                               + port*4,
6038                               NIG_STATUS_EMAC0_MI_INT);
6039         else
6040                 bnx2x_bits_dis(bp,
6041                                NIG_REG_STATUS_INTERRUPT_PORT0
6042                                + port*4,
6043                                NIG_STATUS_EMAC0_MI_INT);
6044
6045         if (latch_status & 1) {
6046
6047                 /* For all latched-signal=up : Re-Arm Latch signals */
6048                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6049                        (latch_status & 0xfffe) | (latch_status & 1));
6050         }
6051         /* For all latched-signal=up,Write original_signal to status */
6052 }
6053
6054 static void bnx2x_link_int_ack(struct link_params *params,
6055                                struct link_vars *vars, u8 is_10g_plus)
6056 {
6057         struct bnx2x *bp = params->bp;
6058         u8 port = params->port;
6059         u32 mask;
6060         /* First reset all status we assume only one line will be
6061          * change at a time
6062          */
6063         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6064                        (NIG_STATUS_XGXS0_LINK10G |
6065                         NIG_STATUS_XGXS0_LINK_STATUS |
6066                         NIG_STATUS_SERDES0_LINK_STATUS));
6067         if (vars->phy_link_up) {
6068                 if (USES_WARPCORE(bp))
6069                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6070                 else {
6071                         if (is_10g_plus)
6072                                 mask = NIG_STATUS_XGXS0_LINK10G;
6073                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6074                                 /* Disable the link interrupt by writing 1 to
6075                                  * the relevant lane in the status register
6076                                  */
6077                                 u32 ser_lane =
6078                                         ((params->lane_config &
6079                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6080                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6081                                 mask = ((1 << ser_lane) <<
6082                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6083                         } else
6084                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6085                 }
6086                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6087                                mask);
6088                 bnx2x_bits_en(bp,
6089                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6090                               mask);
6091         }
6092 }
6093
6094 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6095 {
6096         u8 *str_ptr = str;
6097         u32 mask = 0xf0000000;
6098         u8 shift = 8*4;
6099         u8 digit;
6100         u8 remove_leading_zeros = 1;
6101         if (*len < 10) {
6102                 /* Need more than 10chars for this format */
6103                 *str_ptr = '\0';
6104                 (*len)--;
6105                 return -EINVAL;
6106         }
6107         while (shift > 0) {
6108
6109                 shift -= 4;
6110                 digit = ((num & mask) >> shift);
6111                 if (digit == 0 && remove_leading_zeros) {
6112                         mask = mask >> 4;
6113                         continue;
6114                 } else if (digit < 0xa)
6115                         *str_ptr = digit + '0';
6116                 else
6117                         *str_ptr = digit - 0xa + 'a';
6118                 remove_leading_zeros = 0;
6119                 str_ptr++;
6120                 (*len)--;
6121                 mask = mask >> 4;
6122                 if (shift == 4*4) {
6123                         *str_ptr = '.';
6124                         str_ptr++;
6125                         (*len)--;
6126                         remove_leading_zeros = 1;
6127                 }
6128         }
6129         return 0;
6130 }
6131
6132
6133 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6134 {
6135         str[0] = '\0';
6136         (*len)--;
6137         return 0;
6138 }
6139
6140 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6141                                  u16 len)
6142 {
6143         struct bnx2x *bp;
6144         u32 spirom_ver = 0;
6145         int status = 0;
6146         u8 *ver_p = version;
6147         u16 remain_len = len;
6148         if (version == NULL || params == NULL)
6149                 return -EINVAL;
6150         bp = params->bp;
6151
6152         /* Extract first external phy*/
6153         version[0] = '\0';
6154         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6155
6156         if (params->phy[EXT_PHY1].format_fw_ver) {
6157                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6158                                                               ver_p,
6159                                                               &remain_len);
6160                 ver_p += (len - remain_len);
6161         }
6162         if ((params->num_phys == MAX_PHYS) &&
6163             (params->phy[EXT_PHY2].ver_addr != 0)) {
6164                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6165                 if (params->phy[EXT_PHY2].format_fw_ver) {
6166                         *ver_p = '/';
6167                         ver_p++;
6168                         remain_len--;
6169                         status |= params->phy[EXT_PHY2].format_fw_ver(
6170                                 spirom_ver,
6171                                 ver_p,
6172                                 &remain_len);
6173                         ver_p = version + (len - remain_len);
6174                 }
6175         }
6176         *ver_p = '\0';
6177         return status;
6178 }
6179
6180 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6181                                     struct link_params *params)
6182 {
6183         u8 port = params->port;
6184         struct bnx2x *bp = params->bp;
6185
6186         if (phy->req_line_speed != SPEED_1000) {
6187                 u32 md_devad = 0;
6188
6189                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6190
6191                 if (!CHIP_IS_E3(bp)) {
6192                         /* Change the uni_phy_addr in the nig */
6193                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6194                                                port*0x18));
6195
6196                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6197                                0x5);
6198                 }
6199
6200                 bnx2x_cl45_write(bp, phy,
6201                                  5,
6202                                  (MDIO_REG_BANK_AER_BLOCK +
6203                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6204                                  0x2800);
6205
6206                 bnx2x_cl45_write(bp, phy,
6207                                  5,
6208                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6209                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6210                                  0x6041);
6211                 msleep(200);
6212                 /* Set aer mmd back */
6213                 bnx2x_set_aer_mmd(params, phy);
6214
6215                 if (!CHIP_IS_E3(bp)) {
6216                         /* And md_devad */
6217                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6218                                md_devad);
6219                 }
6220         } else {
6221                 u16 mii_ctrl;
6222                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6223                 bnx2x_cl45_read(bp, phy, 5,
6224                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6225                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6226                                 &mii_ctrl);
6227                 bnx2x_cl45_write(bp, phy, 5,
6228                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6229                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6230                                  mii_ctrl |
6231                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6232         }
6233 }
6234
6235 int bnx2x_set_led(struct link_params *params,
6236                   struct link_vars *vars, u8 mode, u32 speed)
6237 {
6238         u8 port = params->port;
6239         u16 hw_led_mode = params->hw_led_mode;
6240         int rc = 0;
6241         u8 phy_idx;
6242         u32 tmp;
6243         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6244         struct bnx2x *bp = params->bp;
6245         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6246         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6247                  speed, hw_led_mode);
6248         /* In case */
6249         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6250                 if (params->phy[phy_idx].set_link_led) {
6251                         params->phy[phy_idx].set_link_led(
6252                                 &params->phy[phy_idx], params, mode);
6253                 }
6254         }
6255
6256         switch (mode) {
6257         case LED_MODE_FRONT_PANEL_OFF:
6258         case LED_MODE_OFF:
6259                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6260                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6261                        SHARED_HW_CFG_LED_MAC1);
6262
6263                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6264                 if (params->phy[EXT_PHY1].type ==
6265                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6266                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6267                                 EMAC_LED_100MB_OVERRIDE |
6268                                 EMAC_LED_10MB_OVERRIDE);
6269                 else
6270                         tmp |= EMAC_LED_OVERRIDE;
6271
6272                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6273                 break;
6274
6275         case LED_MODE_OPER:
6276                 /* For all other phys, OPER mode is same as ON, so in case
6277                  * link is down, do nothing
6278                  */
6279                 if (!vars->link_up)
6280                         break;
6281         case LED_MODE_ON:
6282                 if (((params->phy[EXT_PHY1].type ==
6283                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6284                          (params->phy[EXT_PHY1].type ==
6285                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6286                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6287                         /* This is a work-around for E2+8727 Configurations */
6288                         if (mode == LED_MODE_ON ||
6289                                 speed == SPEED_10000){
6290                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6291                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6292
6293                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6294                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6295                                         (tmp | EMAC_LED_OVERRIDE));
6296                                 /* Return here without enabling traffic
6297                                  * LED blink and setting rate in ON mode.
6298                                  * In oper mode, enabling LED blink
6299                                  * and setting rate is needed.
6300                                  */
6301                                 if (mode == LED_MODE_ON)
6302                                         return rc;
6303                         }
6304                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6305                         /* This is a work-around for HW issue found when link
6306                          * is up in CL73
6307                          */
6308                         if ((!CHIP_IS_E3(bp)) ||
6309                             (CHIP_IS_E3(bp) &&
6310                              mode == LED_MODE_ON))
6311                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6312
6313                         if (CHIP_IS_E1x(bp) ||
6314                             CHIP_IS_E2(bp) ||
6315                             (mode == LED_MODE_ON))
6316                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6317                         else
6318                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6319                                        hw_led_mode);
6320                 } else if ((params->phy[EXT_PHY1].type ==
6321                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6322                            (mode == LED_MODE_ON)) {
6323                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6324                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6325                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6326                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6327                         /* Break here; otherwise, it'll disable the
6328                          * intended override.
6329                          */
6330                         break;
6331                 } else
6332                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6333                                hw_led_mode);
6334
6335                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6336                 /* Set blinking rate to ~15.9Hz */
6337                 if (CHIP_IS_E3(bp))
6338                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6339                                LED_BLINK_RATE_VAL_E3);
6340                 else
6341                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6342                                LED_BLINK_RATE_VAL_E1X_E2);
6343                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6344                        port*4, 1);
6345                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6346                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6347                         (tmp & (~EMAC_LED_OVERRIDE)));
6348
6349                 if (CHIP_IS_E1(bp) &&
6350                     ((speed == SPEED_2500) ||
6351                      (speed == SPEED_1000) ||
6352                      (speed == SPEED_100) ||
6353                      (speed == SPEED_10))) {
6354                         /* For speeds less than 10G LED scheme is different */
6355                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6356                                + port*4, 1);
6357                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6358                                port*4, 0);
6359                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6360                                port*4, 1);
6361                 }
6362                 break;
6363
6364         default:
6365                 rc = -EINVAL;
6366                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6367                          mode);
6368                 break;
6369         }
6370         return rc;
6371
6372 }
6373
6374 /* This function comes to reflect the actual link state read DIRECTLY from the
6375  * HW
6376  */
6377 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6378                     u8 is_serdes)
6379 {
6380         struct bnx2x *bp = params->bp;
6381         u16 gp_status = 0, phy_index = 0;
6382         u8 ext_phy_link_up = 0, serdes_phy_type;
6383         struct link_vars temp_vars;
6384         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6385
6386         if (CHIP_IS_E3(bp)) {
6387                 u16 link_up;
6388                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6389                     > SPEED_10000) {
6390                         /* Check 20G link */
6391                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6392                                         1, &link_up);
6393                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6394                                         1, &link_up);
6395                         link_up &= (1<<2);
6396                 } else {
6397                         /* Check 10G link and below*/
6398                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6399                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6400                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6401                                         &gp_status);
6402                         gp_status = ((gp_status >> 8) & 0xf) |
6403                                 ((gp_status >> 12) & 0xf);
6404                         link_up = gp_status & (1 << lane);
6405                 }
6406                 if (!link_up)
6407                         return -ESRCH;
6408         } else {
6409                 CL22_RD_OVER_CL45(bp, int_phy,
6410                           MDIO_REG_BANK_GP_STATUS,
6411                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6412                           &gp_status);
6413         /* Link is up only if both local phy and external phy are up */
6414         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6415                 return -ESRCH;
6416         }
6417         /* In XGXS loopback mode, do not check external PHY */
6418         if (params->loopback_mode == LOOPBACK_XGXS)
6419                 return 0;
6420
6421         switch (params->num_phys) {
6422         case 1:
6423                 /* No external PHY */
6424                 return 0;
6425         case 2:
6426                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6427                         &params->phy[EXT_PHY1],
6428                         params, &temp_vars);
6429                 break;
6430         case 3: /* Dual Media */
6431                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6432                       phy_index++) {
6433                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6434                                             ETH_PHY_SFPP_10G_FIBER) ||
6435                                            (params->phy[phy_index].media_type ==
6436                                             ETH_PHY_SFP_1G_FIBER) ||
6437                                            (params->phy[phy_index].media_type ==
6438                                             ETH_PHY_XFP_FIBER) ||
6439                                            (params->phy[phy_index].media_type ==
6440                                             ETH_PHY_DA_TWINAX));
6441
6442                         if (is_serdes != serdes_phy_type)
6443                                 continue;
6444                         if (params->phy[phy_index].read_status) {
6445                                 ext_phy_link_up |=
6446                                         params->phy[phy_index].read_status(
6447                                                 &params->phy[phy_index],
6448                                                 params, &temp_vars);
6449                         }
6450                 }
6451                 break;
6452         }
6453         if (ext_phy_link_up)
6454                 return 0;
6455         return -ESRCH;
6456 }
6457
6458 static int bnx2x_link_initialize(struct link_params *params,
6459                                  struct link_vars *vars)
6460 {
6461         int rc = 0;
6462         u8 phy_index, non_ext_phy;
6463         struct bnx2x *bp = params->bp;
6464         /* In case of external phy existence, the line speed would be the
6465          * line speed linked up by the external phy. In case it is direct
6466          * only, then the line_speed during initialization will be
6467          * equal to the req_line_speed
6468          */
6469         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6470
6471         /* Initialize the internal phy in case this is a direct board
6472          * (no external phys), or this board has external phy which requires
6473          * to first.
6474          */
6475         if (!USES_WARPCORE(bp))
6476                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6477         /* init ext phy and enable link state int */
6478         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6479                        (params->loopback_mode == LOOPBACK_XGXS));
6480
6481         if (non_ext_phy ||
6482             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6483             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6484                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6485                 if (vars->line_speed == SPEED_AUTO_NEG &&
6486                     (CHIP_IS_E1x(bp) ||
6487                      CHIP_IS_E2(bp)))
6488                         bnx2x_set_parallel_detection(phy, params);
6489                         if (params->phy[INT_PHY].config_init)
6490                                 params->phy[INT_PHY].config_init(phy,
6491                                                                  params,
6492                                                                  vars);
6493         }
6494
6495         /* Init external phy*/
6496         if (non_ext_phy) {
6497                 if (params->phy[INT_PHY].supported &
6498                     SUPPORTED_FIBRE)
6499                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6500         } else {
6501                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6502                       phy_index++) {
6503                         /* No need to initialize second phy in case of first
6504                          * phy only selection. In case of second phy, we do
6505                          * need to initialize the first phy, since they are
6506                          * connected.
6507                          */
6508                         if (params->phy[phy_index].supported &
6509                             SUPPORTED_FIBRE)
6510                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6511
6512                         if (phy_index == EXT_PHY2 &&
6513                             (bnx2x_phy_selection(params) ==
6514                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6515                                 DP(NETIF_MSG_LINK,
6516                                    "Not initializing second phy\n");
6517                                 continue;
6518                         }
6519                         params->phy[phy_index].config_init(
6520                                 &params->phy[phy_index],
6521                                 params, vars);
6522                 }
6523         }
6524         /* Reset the interrupt indication after phy was initialized */
6525         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6526                        params->port*4,
6527                        (NIG_STATUS_XGXS0_LINK10G |
6528                         NIG_STATUS_XGXS0_LINK_STATUS |
6529                         NIG_STATUS_SERDES0_LINK_STATUS |
6530                         NIG_MASK_MI_INT));
6531         return rc;
6532 }
6533
6534 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6535                                  struct link_params *params)
6536 {
6537         /* Reset the SerDes/XGXS */
6538         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6539                (0x1ff << (params->port*16)));
6540 }
6541
6542 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6543                                         struct link_params *params)
6544 {
6545         struct bnx2x *bp = params->bp;
6546         u8 gpio_port;
6547         /* HW reset */
6548         if (CHIP_IS_E2(bp))
6549                 gpio_port = BP_PATH(bp);
6550         else
6551                 gpio_port = params->port;
6552         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6553                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6554                        gpio_port);
6555         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6556                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6557                        gpio_port);
6558         DP(NETIF_MSG_LINK, "reset external PHY\n");
6559 }
6560
6561 static int bnx2x_update_link_down(struct link_params *params,
6562                                   struct link_vars *vars)
6563 {
6564         struct bnx2x *bp = params->bp;
6565         u8 port = params->port;
6566
6567         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6568         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6569         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6570         /* Indicate no mac active */
6571         vars->mac_type = MAC_TYPE_NONE;
6572
6573         /* Update shared memory */
6574         vars->link_status &= ~LINK_UPDATE_MASK;
6575         vars->line_speed = 0;
6576         bnx2x_update_mng(params, vars->link_status);
6577
6578         /* Activate nig drain */
6579         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6580
6581         /* Disable emac */
6582         if (!CHIP_IS_E3(bp))
6583                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6584
6585         usleep_range(10000, 20000);
6586         /* Reset BigMac/Xmac */
6587         if (CHIP_IS_E1x(bp) ||
6588             CHIP_IS_E2(bp))
6589                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6590
6591         if (CHIP_IS_E3(bp)) {
6592                 /* Prevent LPI Generation by chip */
6593                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6594                        0);
6595                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6596                        0);
6597                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6598                                       SHMEM_EEE_ACTIVE_BIT);
6599
6600                 bnx2x_update_mng_eee(params, vars->eee_status);
6601                 bnx2x_set_xmac_rxtx(params, 0);
6602                 bnx2x_set_umac_rxtx(params, 0);
6603         }
6604
6605         return 0;
6606 }
6607
6608 static int bnx2x_update_link_up(struct link_params *params,
6609                                 struct link_vars *vars,
6610                                 u8 link_10g)
6611 {
6612         struct bnx2x *bp = params->bp;
6613         u8 phy_idx, port = params->port;
6614         int rc = 0;
6615
6616         vars->link_status |= (LINK_STATUS_LINK_UP |
6617                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6618         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6619
6620         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6621                 vars->link_status |=
6622                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6623
6624         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6625                 vars->link_status |=
6626                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6627         if (USES_WARPCORE(bp)) {
6628                 if (link_10g) {
6629                         if (bnx2x_xmac_enable(params, vars, 0) ==
6630                             -ESRCH) {
6631                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6632                                 vars->link_up = 0;
6633                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6634                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6635                         }
6636                 } else
6637                         bnx2x_umac_enable(params, vars, 0);
6638                 bnx2x_set_led(params, vars,
6639                               LED_MODE_OPER, vars->line_speed);
6640
6641                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6642                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6643                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6644                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6645                                (params->port << 2), 1);
6646                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6647                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6648                                (params->port << 2), 0xfc20);
6649                 }
6650         }
6651         if ((CHIP_IS_E1x(bp) ||
6652              CHIP_IS_E2(bp))) {
6653                 if (link_10g) {
6654                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6655                             -ESRCH) {
6656                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6657                                 vars->link_up = 0;
6658                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6659                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6660                         }
6661
6662                         bnx2x_set_led(params, vars,
6663                                       LED_MODE_OPER, SPEED_10000);
6664                 } else {
6665                         rc = bnx2x_emac_program(params, vars);
6666                         bnx2x_emac_enable(params, vars, 0);
6667
6668                         /* AN complete? */
6669                         if ((vars->link_status &
6670                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6671                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6672                             SINGLE_MEDIA_DIRECT(params))
6673                                 bnx2x_set_gmii_tx_driver(params);
6674                 }
6675         }
6676
6677         /* PBF - link up */
6678         if (CHIP_IS_E1x(bp))
6679                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6680                                        vars->line_speed);
6681
6682         /* Disable drain */
6683         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6684
6685         /* Update shared memory */
6686         bnx2x_update_mng(params, vars->link_status);
6687         bnx2x_update_mng_eee(params, vars->eee_status);
6688         /* Check remote fault */
6689         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6690                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6691                         bnx2x_check_half_open_conn(params, vars, 0);
6692                         break;
6693                 }
6694         }
6695         msleep(20);
6696         return rc;
6697 }
6698 /* The bnx2x_link_update function should be called upon link
6699  * interrupt.
6700  * Link is considered up as follows:
6701  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6702  *   to be up
6703  * - SINGLE_MEDIA - The link between the 577xx and the external
6704  *   phy (XGXS) need to up as well as the external link of the
6705  *   phy (PHY_EXT1)
6706  * - DUAL_MEDIA - The link between the 577xx and the first
6707  *   external phy needs to be up, and at least one of the 2
6708  *   external phy link must be up.
6709  */
6710 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6711 {
6712         struct bnx2x *bp = params->bp;
6713         struct link_vars phy_vars[MAX_PHYS];
6714         u8 port = params->port;
6715         u8 link_10g_plus, phy_index;
6716         u8 ext_phy_link_up = 0, cur_link_up;
6717         int rc = 0;
6718         u8 is_mi_int = 0;
6719         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6720         u8 active_external_phy = INT_PHY;
6721         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6722         vars->link_status &= ~LINK_UPDATE_MASK;
6723         for (phy_index = INT_PHY; phy_index < params->num_phys;
6724               phy_index++) {
6725                 phy_vars[phy_index].flow_ctrl = 0;
6726                 phy_vars[phy_index].link_status = 0;
6727                 phy_vars[phy_index].line_speed = 0;
6728                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6729                 phy_vars[phy_index].phy_link_up = 0;
6730                 phy_vars[phy_index].link_up = 0;
6731                 phy_vars[phy_index].fault_detected = 0;
6732                 /* different consideration, since vars holds inner state */
6733                 phy_vars[phy_index].eee_status = vars->eee_status;
6734         }
6735
6736         if (USES_WARPCORE(bp))
6737                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6738
6739         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6740                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6741                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6742
6743         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6744                                 port*0x18) > 0);
6745         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6746                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6747                  is_mi_int,
6748                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6749
6750         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6751           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6752           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6753
6754         /* Disable emac */
6755         if (!CHIP_IS_E3(bp))
6756                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6757
6758         /* Step 1:
6759          * Check external link change only for external phys, and apply
6760          * priority selection between them in case the link on both phys
6761          * is up. Note that instead of the common vars, a temporary
6762          * vars argument is used since each phy may have different link/
6763          * speed/duplex result
6764          */
6765         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6766               phy_index++) {
6767                 struct bnx2x_phy *phy = &params->phy[phy_index];
6768                 if (!phy->read_status)
6769                         continue;
6770                 /* Read link status and params of this ext phy */
6771                 cur_link_up = phy->read_status(phy, params,
6772                                                &phy_vars[phy_index]);
6773                 if (cur_link_up) {
6774                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6775                                    phy_index);
6776                 } else {
6777                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6778                                    phy_index);
6779                         continue;
6780                 }
6781
6782                 if (!ext_phy_link_up) {
6783                         ext_phy_link_up = 1;
6784                         active_external_phy = phy_index;
6785                 } else {
6786                         switch (bnx2x_phy_selection(params)) {
6787                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6788                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6789                         /* In this option, the first PHY makes sure to pass the
6790                          * traffic through itself only.
6791                          * Its not clear how to reset the link on the second phy
6792                          */
6793                                 active_external_phy = EXT_PHY1;
6794                                 break;
6795                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6796                         /* In this option, the first PHY makes sure to pass the
6797                          * traffic through the second PHY.
6798                          */
6799                                 active_external_phy = EXT_PHY2;
6800                                 break;
6801                         default:
6802                         /* Link indication on both PHYs with the following cases
6803                          * is invalid:
6804                          * - FIRST_PHY means that second phy wasn't initialized,
6805                          * hence its link is expected to be down
6806                          * - SECOND_PHY means that first phy should not be able
6807                          * to link up by itself (using configuration)
6808                          * - DEFAULT should be overriden during initialiazation
6809                          */
6810                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6811                                            "mpc=0x%x. DISABLING LINK !!!\n",
6812                                            params->multi_phy_config);
6813                                 ext_phy_link_up = 0;
6814                                 break;
6815                         }
6816                 }
6817         }
6818         prev_line_speed = vars->line_speed;
6819         /* Step 2:
6820          * Read the status of the internal phy. In case of
6821          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6822          * otherwise this is the link between the 577xx and the first
6823          * external phy
6824          */
6825         if (params->phy[INT_PHY].read_status)
6826                 params->phy[INT_PHY].read_status(
6827                         &params->phy[INT_PHY],
6828                         params, vars);
6829         /* The INT_PHY flow control reside in the vars. This include the
6830          * case where the speed or flow control are not set to AUTO.
6831          * Otherwise, the active external phy flow control result is set
6832          * to the vars. The ext_phy_line_speed is needed to check if the
6833          * speed is different between the internal phy and external phy.
6834          * This case may be result of intermediate link speed change.
6835          */
6836         if (active_external_phy > INT_PHY) {
6837                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6838                 /* Link speed is taken from the XGXS. AN and FC result from
6839                  * the external phy.
6840                  */
6841                 vars->link_status |= phy_vars[active_external_phy].link_status;
6842
6843                 /* if active_external_phy is first PHY and link is up - disable
6844                  * disable TX on second external PHY
6845                  */
6846                 if (active_external_phy == EXT_PHY1) {
6847                         if (params->phy[EXT_PHY2].phy_specific_func) {
6848                                 DP(NETIF_MSG_LINK,
6849                                    "Disabling TX on EXT_PHY2\n");
6850                                 params->phy[EXT_PHY2].phy_specific_func(
6851                                         &params->phy[EXT_PHY2],
6852                                         params, DISABLE_TX);
6853                         }
6854                 }
6855
6856                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6857                 vars->duplex = phy_vars[active_external_phy].duplex;
6858                 if (params->phy[active_external_phy].supported &
6859                     SUPPORTED_FIBRE)
6860                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6861                 else
6862                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6863
6864                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6865
6866                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6867                            active_external_phy);
6868         }
6869
6870         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6871               phy_index++) {
6872                 if (params->phy[phy_index].flags &
6873                     FLAGS_REARM_LATCH_SIGNAL) {
6874                         bnx2x_rearm_latch_signal(bp, port,
6875                                                  phy_index ==
6876                                                  active_external_phy);
6877                         break;
6878                 }
6879         }
6880         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6881                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6882                    vars->link_status, ext_phy_line_speed);
6883         /* Upon link speed change set the NIG into drain mode. Comes to
6884          * deals with possible FIFO glitch due to clk change when speed
6885          * is decreased without link down indicator
6886          */
6887
6888         if (vars->phy_link_up) {
6889                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6890                     (ext_phy_line_speed != vars->line_speed)) {
6891                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6892                                    " different than the external"
6893                                    " link speed %d\n", vars->line_speed,
6894                                    ext_phy_line_speed);
6895                         vars->phy_link_up = 0;
6896                 } else if (prev_line_speed != vars->line_speed) {
6897                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6898                                0);
6899                         usleep_range(1000, 2000);
6900                 }
6901         }
6902
6903         /* Anything 10 and over uses the bmac */
6904         link_10g_plus = (vars->line_speed >= SPEED_10000);
6905
6906         bnx2x_link_int_ack(params, vars, link_10g_plus);
6907
6908         /* In case external phy link is up, and internal link is down
6909          * (not initialized yet probably after link initialization, it
6910          * needs to be initialized.
6911          * Note that after link down-up as result of cable plug, the xgxs
6912          * link would probably become up again without the need
6913          * initialize it
6914          */
6915         if (!(SINGLE_MEDIA_DIRECT(params))) {
6916                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6917                            " init_preceding = %d\n", ext_phy_link_up,
6918                            vars->phy_link_up,
6919                            params->phy[EXT_PHY1].flags &
6920                            FLAGS_INIT_XGXS_FIRST);
6921                 if (!(params->phy[EXT_PHY1].flags &
6922                       FLAGS_INIT_XGXS_FIRST)
6923                     && ext_phy_link_up && !vars->phy_link_up) {
6924                         vars->line_speed = ext_phy_line_speed;
6925                         if (vars->line_speed < SPEED_1000)
6926                                 vars->phy_flags |= PHY_SGMII_FLAG;
6927                         else
6928                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6929
6930                         if (params->phy[INT_PHY].config_init)
6931                                 params->phy[INT_PHY].config_init(
6932                                         &params->phy[INT_PHY], params,
6933                                                 vars);
6934                 }
6935         }
6936         /* Link is up only if both local phy and external phy (in case of
6937          * non-direct board) are up and no fault detected on active PHY.
6938          */
6939         vars->link_up = (vars->phy_link_up &&
6940                          (ext_phy_link_up ||
6941                           SINGLE_MEDIA_DIRECT(params)) &&
6942                          (phy_vars[active_external_phy].fault_detected == 0));
6943
6944         /* Update the PFC configuration in case it was changed */
6945         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6946                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6947         else
6948                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6949
6950         if (vars->link_up)
6951                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6952         else
6953                 rc = bnx2x_update_link_down(params, vars);
6954
6955         /* Update MCP link status was changed */
6956         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6957                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6958
6959         return rc;
6960 }
6961
6962 /*****************************************************************************/
6963 /*                          External Phy section                             */
6964 /*****************************************************************************/
6965 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6966 {
6967         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6968                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6969         usleep_range(1000, 2000);
6970         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6971                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6972 }
6973
6974 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6975                                       u32 spirom_ver, u32 ver_addr)
6976 {
6977         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6978                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6979
6980         if (ver_addr)
6981                 REG_WR(bp, ver_addr, spirom_ver);
6982 }
6983
6984 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6985                                       struct bnx2x_phy *phy,
6986                                       u8 port)
6987 {
6988         u16 fw_ver1, fw_ver2;
6989
6990         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6991                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6992         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6993                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6994         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6995                                   phy->ver_addr);
6996 }
6997
6998 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6999                                        struct bnx2x_phy *phy,
7000                                        struct link_vars *vars)
7001 {
7002         u16 val;
7003         bnx2x_cl45_read(bp, phy,
7004                         MDIO_AN_DEVAD,
7005                         MDIO_AN_REG_STATUS, &val);
7006         bnx2x_cl45_read(bp, phy,
7007                         MDIO_AN_DEVAD,
7008                         MDIO_AN_REG_STATUS, &val);
7009         if (val & (1<<5))
7010                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7011         if ((val & (1<<0)) == 0)
7012                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7013 }
7014
7015 /******************************************************************/
7016 /*              common BCM8073/BCM8727 PHY SECTION                */
7017 /******************************************************************/
7018 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7019                                   struct link_params *params,
7020                                   struct link_vars *vars)
7021 {
7022         struct bnx2x *bp = params->bp;
7023         if (phy->req_line_speed == SPEED_10 ||
7024             phy->req_line_speed == SPEED_100) {
7025                 vars->flow_ctrl = phy->req_flow_ctrl;
7026                 return;
7027         }
7028
7029         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7030             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7031                 u16 pause_result;
7032                 u16 ld_pause;           /* local */
7033                 u16 lp_pause;           /* link partner */
7034                 bnx2x_cl45_read(bp, phy,
7035                                 MDIO_AN_DEVAD,
7036                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7037
7038                 bnx2x_cl45_read(bp, phy,
7039                                 MDIO_AN_DEVAD,
7040                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7041                 pause_result = (ld_pause &
7042                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7043                 pause_result |= (lp_pause &
7044                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7045
7046                 bnx2x_pause_resolve(vars, pause_result);
7047                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7048                            pause_result);
7049         }
7050 }
7051 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7052                                              struct bnx2x_phy *phy,
7053                                              u8 port)
7054 {
7055         u32 count = 0;
7056         u16 fw_ver1, fw_msgout;
7057         int rc = 0;
7058
7059         /* Boot port from external ROM  */
7060         /* EDC grst */
7061         bnx2x_cl45_write(bp, phy,
7062                          MDIO_PMA_DEVAD,
7063                          MDIO_PMA_REG_GEN_CTRL,
7064                          0x0001);
7065
7066         /* Ucode reboot and rst */
7067         bnx2x_cl45_write(bp, phy,
7068                          MDIO_PMA_DEVAD,
7069                          MDIO_PMA_REG_GEN_CTRL,
7070                          0x008c);
7071
7072         bnx2x_cl45_write(bp, phy,
7073                          MDIO_PMA_DEVAD,
7074                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7075
7076         /* Reset internal microprocessor */
7077         bnx2x_cl45_write(bp, phy,
7078                          MDIO_PMA_DEVAD,
7079                          MDIO_PMA_REG_GEN_CTRL,
7080                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7081
7082         /* Release srst bit */
7083         bnx2x_cl45_write(bp, phy,
7084                          MDIO_PMA_DEVAD,
7085                          MDIO_PMA_REG_GEN_CTRL,
7086                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7087
7088         /* Delay 100ms per the PHY specifications */
7089         msleep(100);
7090
7091         /* 8073 sometimes taking longer to download */
7092         do {
7093                 count++;
7094                 if (count > 300) {
7095                         DP(NETIF_MSG_LINK,
7096                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7097                                  "Download failed. fw version = 0x%x\n",
7098                                  port, fw_ver1);
7099                         rc = -EINVAL;
7100                         break;
7101                 }
7102
7103                 bnx2x_cl45_read(bp, phy,
7104                                 MDIO_PMA_DEVAD,
7105                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7106                 bnx2x_cl45_read(bp, phy,
7107                                 MDIO_PMA_DEVAD,
7108                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7109
7110                 usleep_range(1000, 2000);
7111         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7112                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7113                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7114
7115         /* Clear ser_boot_ctl bit */
7116         bnx2x_cl45_write(bp, phy,
7117                          MDIO_PMA_DEVAD,
7118                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7119         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7120
7121         DP(NETIF_MSG_LINK,
7122                  "bnx2x_8073_8727_external_rom_boot port %x:"
7123                  "Download complete. fw version = 0x%x\n",
7124                  port, fw_ver1);
7125
7126         return rc;
7127 }
7128
7129 /******************************************************************/
7130 /*                      BCM8073 PHY SECTION                       */
7131 /******************************************************************/
7132 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7133 {
7134         /* This is only required for 8073A1, version 102 only */
7135         u16 val;
7136
7137         /* Read 8073 HW revision*/
7138         bnx2x_cl45_read(bp, phy,
7139                         MDIO_PMA_DEVAD,
7140                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7141
7142         if (val != 1) {
7143                 /* No need to workaround in 8073 A1 */
7144                 return 0;
7145         }
7146
7147         bnx2x_cl45_read(bp, phy,
7148                         MDIO_PMA_DEVAD,
7149                         MDIO_PMA_REG_ROM_VER2, &val);
7150
7151         /* SNR should be applied only for version 0x102 */
7152         if (val != 0x102)
7153                 return 0;
7154
7155         return 1;
7156 }
7157
7158 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7159 {
7160         u16 val, cnt, cnt1 ;
7161
7162         bnx2x_cl45_read(bp, phy,
7163                         MDIO_PMA_DEVAD,
7164                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7165
7166         if (val > 0) {
7167                 /* No need to workaround in 8073 A1 */
7168                 return 0;
7169         }
7170         /* XAUI workaround in 8073 A0: */
7171
7172         /* After loading the boot ROM and restarting Autoneg, poll
7173          * Dev1, Reg $C820:
7174          */
7175
7176         for (cnt = 0; cnt < 1000; cnt++) {
7177                 bnx2x_cl45_read(bp, phy,
7178                                 MDIO_PMA_DEVAD,
7179                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7180                                 &val);
7181                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7182                    * system initialization (XAUI work-around not required, as
7183                    * these bits indicate 2.5G or 1G link up).
7184                    */
7185                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7186                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7187                         return 0;
7188                 } else if (!(val & (1<<15))) {
7189                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7190                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7191                          * MSB (bit15) goes to 1 (indicating that the XAUI
7192                          * workaround has completed), then continue on with
7193                          * system initialization.
7194                          */
7195                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7196                                 bnx2x_cl45_read(bp, phy,
7197                                         MDIO_PMA_DEVAD,
7198                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7199                                 if (val & (1<<15)) {
7200                                         DP(NETIF_MSG_LINK,
7201                                           "XAUI workaround has completed\n");
7202                                         return 0;
7203                                  }
7204                                  usleep_range(3000, 6000);
7205                         }
7206                         break;
7207                 }
7208                 usleep_range(3000, 6000);
7209         }
7210         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7211         return -EINVAL;
7212 }
7213
7214 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7215 {
7216         /* Force KR or KX */
7217         bnx2x_cl45_write(bp, phy,
7218                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7219         bnx2x_cl45_write(bp, phy,
7220                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7221         bnx2x_cl45_write(bp, phy,
7222                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7223         bnx2x_cl45_write(bp, phy,
7224                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7225 }
7226
7227 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7228                                       struct bnx2x_phy *phy,
7229                                       struct link_vars *vars)
7230 {
7231         u16 cl37_val;
7232         struct bnx2x *bp = params->bp;
7233         bnx2x_cl45_read(bp, phy,
7234                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7235
7236         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7237         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7238         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7239         if ((vars->ieee_fc &
7240             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7241             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7242                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7243         }
7244         if ((vars->ieee_fc &
7245             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7246             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7247                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7248         }
7249         if ((vars->ieee_fc &
7250             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7251             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7252                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7253         }
7254         DP(NETIF_MSG_LINK,
7255                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7256
7257         bnx2x_cl45_write(bp, phy,
7258                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7259         msleep(500);
7260 }
7261
7262 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7263                                      struct link_params *params,
7264                                      u32 action)
7265 {
7266         struct bnx2x *bp = params->bp;
7267         switch (action) {
7268         case PHY_INIT:
7269                 /* Enable LASI */
7270                 bnx2x_cl45_write(bp, phy,
7271                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7272                 bnx2x_cl45_write(bp, phy,
7273                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7274                 break;
7275         }
7276 }
7277
7278 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7279                                   struct link_params *params,
7280                                   struct link_vars *vars)
7281 {
7282         struct bnx2x *bp = params->bp;
7283         u16 val = 0, tmp1;
7284         u8 gpio_port;
7285         DP(NETIF_MSG_LINK, "Init 8073\n");
7286
7287         if (CHIP_IS_E2(bp))
7288                 gpio_port = BP_PATH(bp);
7289         else
7290                 gpio_port = params->port;
7291         /* Restore normal power mode*/
7292         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7293                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7294
7295         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7296                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7297
7298         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7299         bnx2x_8073_set_pause_cl37(params, phy, vars);
7300
7301         bnx2x_cl45_read(bp, phy,
7302                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7303
7304         bnx2x_cl45_read(bp, phy,
7305                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7306
7307         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7308
7309         /* Swap polarity if required - Must be done only in non-1G mode */
7310         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7311                 /* Configure the 8073 to swap _P and _N of the KR lines */
7312                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7313                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7314                 bnx2x_cl45_read(bp, phy,
7315                                 MDIO_PMA_DEVAD,
7316                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7317                 bnx2x_cl45_write(bp, phy,
7318                                  MDIO_PMA_DEVAD,
7319                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7320                                  (val | (3<<9)));
7321         }
7322
7323
7324         /* Enable CL37 BAM */
7325         if (REG_RD(bp, params->shmem_base +
7326                          offsetof(struct shmem_region, dev_info.
7327                                   port_hw_config[params->port].default_cfg)) &
7328             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7329
7330                 bnx2x_cl45_read(bp, phy,
7331                                 MDIO_AN_DEVAD,
7332                                 MDIO_AN_REG_8073_BAM, &val);
7333                 bnx2x_cl45_write(bp, phy,
7334                                  MDIO_AN_DEVAD,
7335                                  MDIO_AN_REG_8073_BAM, val | 1);
7336                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7337         }
7338         if (params->loopback_mode == LOOPBACK_EXT) {
7339                 bnx2x_807x_force_10G(bp, phy);
7340                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7341                 return 0;
7342         } else {
7343                 bnx2x_cl45_write(bp, phy,
7344                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7345         }
7346         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7347                 if (phy->req_line_speed == SPEED_10000) {
7348                         val = (1<<7);
7349                 } else if (phy->req_line_speed ==  SPEED_2500) {
7350                         val = (1<<5);
7351                         /* Note that 2.5G works only when used with 1G
7352                          * advertisement
7353                          */
7354                 } else
7355                         val = (1<<5);
7356         } else {
7357                 val = 0;
7358                 if (phy->speed_cap_mask &
7359                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7360                         val |= (1<<7);
7361
7362                 /* Note that 2.5G works only when used with 1G advertisement */
7363                 if (phy->speed_cap_mask &
7364                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7365                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7366                         val |= (1<<5);
7367                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7368         }
7369
7370         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7371         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7372
7373         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7374              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7375             (phy->req_line_speed == SPEED_2500)) {
7376                 u16 phy_ver;
7377                 /* Allow 2.5G for A1 and above */
7378                 bnx2x_cl45_read(bp, phy,
7379                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7380                                 &phy_ver);
7381                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7382                 if (phy_ver > 0)
7383                         tmp1 |= 1;
7384                 else
7385                         tmp1 &= 0xfffe;
7386         } else {
7387                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7388                 tmp1 &= 0xfffe;
7389         }
7390
7391         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7392         /* Add support for CL37 (passive mode) II */
7393
7394         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7395         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7396                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7397                                   0x20 : 0x40)));
7398
7399         /* Add support for CL37 (passive mode) III */
7400         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7401
7402         /* The SNR will improve about 2db by changing BW and FEE main
7403          * tap. Rest commands are executed after link is up
7404          * Change FFE main cursor to 5 in EDC register
7405          */
7406         if (bnx2x_8073_is_snr_needed(bp, phy))
7407                 bnx2x_cl45_write(bp, phy,
7408                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7409                                  0xFB0C);
7410
7411         /* Enable FEC (Forware Error Correction) Request in the AN */
7412         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7413         tmp1 |= (1<<15);
7414         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7415
7416         bnx2x_ext_phy_set_pause(params, phy, vars);
7417
7418         /* Restart autoneg */
7419         msleep(500);
7420         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7421         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7422                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7423         return 0;
7424 }
7425
7426 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7427                                  struct link_params *params,
7428                                  struct link_vars *vars)
7429 {
7430         struct bnx2x *bp = params->bp;
7431         u8 link_up = 0;
7432         u16 val1, val2;
7433         u16 link_status = 0;
7434         u16 an1000_status = 0;
7435
7436         bnx2x_cl45_read(bp, phy,
7437                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7438
7439         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7440
7441         /* Clear the interrupt LASI status register */
7442         bnx2x_cl45_read(bp, phy,
7443                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7444         bnx2x_cl45_read(bp, phy,
7445                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7446         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7447         /* Clear MSG-OUT */
7448         bnx2x_cl45_read(bp, phy,
7449                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7450
7451         /* Check the LASI */
7452         bnx2x_cl45_read(bp, phy,
7453                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7454
7455         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7456
7457         /* Check the link status */
7458         bnx2x_cl45_read(bp, phy,
7459                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7460         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7461
7462         bnx2x_cl45_read(bp, phy,
7463                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7464         bnx2x_cl45_read(bp, phy,
7465                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7466         link_up = ((val1 & 4) == 4);
7467         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7468
7469         if (link_up &&
7470              ((phy->req_line_speed != SPEED_10000))) {
7471                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7472                         return 0;
7473         }
7474         bnx2x_cl45_read(bp, phy,
7475                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7476         bnx2x_cl45_read(bp, phy,
7477                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7478
7479         /* Check the link status on 1.1.2 */
7480         bnx2x_cl45_read(bp, phy,
7481                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7482         bnx2x_cl45_read(bp, phy,
7483                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7484         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7485                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7486
7487         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7488         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7489                 /* The SNR will improve about 2dbby changing the BW and FEE main
7490                  * tap. The 1st write to change FFE main tap is set before
7491                  * restart AN. Change PLL Bandwidth in EDC register
7492                  */
7493                 bnx2x_cl45_write(bp, phy,
7494                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7495                                  0x26BC);
7496
7497                 /* Change CDR Bandwidth in EDC register */
7498                 bnx2x_cl45_write(bp, phy,
7499                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7500                                  0x0333);
7501         }
7502         bnx2x_cl45_read(bp, phy,
7503                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7504                         &link_status);
7505
7506         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7507         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7508                 link_up = 1;
7509                 vars->line_speed = SPEED_10000;
7510                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7511                            params->port);
7512         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7513                 link_up = 1;
7514                 vars->line_speed = SPEED_2500;
7515                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7516                            params->port);
7517         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7518                 link_up = 1;
7519                 vars->line_speed = SPEED_1000;
7520                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7521                            params->port);
7522         } else {
7523                 link_up = 0;
7524                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7525                            params->port);
7526         }
7527
7528         if (link_up) {
7529                 /* Swap polarity if required */
7530                 if (params->lane_config &
7531                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7532                         /* Configure the 8073 to swap P and N of the KR lines */
7533                         bnx2x_cl45_read(bp, phy,
7534                                         MDIO_XS_DEVAD,
7535                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7536                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7537                          * when it`s in 10G mode.
7538                          */
7539                         if (vars->line_speed == SPEED_1000) {
7540                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7541                                               "the 8073\n");
7542                                 val1 |= (1<<3);
7543                         } else
7544                                 val1 &= ~(1<<3);
7545
7546                         bnx2x_cl45_write(bp, phy,
7547                                          MDIO_XS_DEVAD,
7548                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7549                                          val1);
7550                 }
7551                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7552                 bnx2x_8073_resolve_fc(phy, params, vars);
7553                 vars->duplex = DUPLEX_FULL;
7554         }
7555
7556         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7557                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7558                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7559
7560                 if (val1 & (1<<5))
7561                         vars->link_status |=
7562                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7563                 if (val1 & (1<<7))
7564                         vars->link_status |=
7565                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7566         }
7567
7568         return link_up;
7569 }
7570
7571 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7572                                   struct link_params *params)
7573 {
7574         struct bnx2x *bp = params->bp;
7575         u8 gpio_port;
7576         if (CHIP_IS_E2(bp))
7577                 gpio_port = BP_PATH(bp);
7578         else
7579                 gpio_port = params->port;
7580         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7581            gpio_port);
7582         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7583                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7584                        gpio_port);
7585 }
7586
7587 /******************************************************************/
7588 /*                      BCM8705 PHY SECTION                       */
7589 /******************************************************************/
7590 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7591                                   struct link_params *params,
7592                                   struct link_vars *vars)
7593 {
7594         struct bnx2x *bp = params->bp;
7595         DP(NETIF_MSG_LINK, "init 8705\n");
7596         /* Restore normal power mode*/
7597         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7598                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7599         /* HW reset */
7600         bnx2x_ext_phy_hw_reset(bp, params->port);
7601         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7602         bnx2x_wait_reset_complete(bp, phy, params);
7603
7604         bnx2x_cl45_write(bp, phy,
7605                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7606         bnx2x_cl45_write(bp, phy,
7607                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7608         bnx2x_cl45_write(bp, phy,
7609                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7610         bnx2x_cl45_write(bp, phy,
7611                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7612         /* BCM8705 doesn't have microcode, hence the 0 */
7613         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7614         return 0;
7615 }
7616
7617 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7618                                  struct link_params *params,
7619                                  struct link_vars *vars)
7620 {
7621         u8 link_up = 0;
7622         u16 val1, rx_sd;
7623         struct bnx2x *bp = params->bp;
7624         DP(NETIF_MSG_LINK, "read status 8705\n");
7625         bnx2x_cl45_read(bp, phy,
7626                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7627         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7628
7629         bnx2x_cl45_read(bp, phy,
7630                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7631         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7632
7633         bnx2x_cl45_read(bp, phy,
7634                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7635
7636         bnx2x_cl45_read(bp, phy,
7637                       MDIO_PMA_DEVAD, 0xc809, &val1);
7638         bnx2x_cl45_read(bp, phy,
7639                       MDIO_PMA_DEVAD, 0xc809, &val1);
7640
7641         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7642         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7643         if (link_up) {
7644                 vars->line_speed = SPEED_10000;
7645                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7646         }
7647         return link_up;
7648 }
7649
7650 /******************************************************************/
7651 /*                      SFP+ module Section                       */
7652 /******************************************************************/
7653 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7654                                            struct bnx2x_phy *phy,
7655                                            u8 pmd_dis)
7656 {
7657         struct bnx2x *bp = params->bp;
7658         /* Disable transmitter only for bootcodes which can enable it afterwards
7659          * (for D3 link)
7660          */
7661         if (pmd_dis) {
7662                 if (params->feature_config_flags &
7663                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7664                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7665                 else {
7666                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7667                         return;
7668                 }
7669         } else
7670                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7671         bnx2x_cl45_write(bp, phy,
7672                          MDIO_PMA_DEVAD,
7673                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7674 }
7675
7676 static u8 bnx2x_get_gpio_port(struct link_params *params)
7677 {
7678         u8 gpio_port;
7679         u32 swap_val, swap_override;
7680         struct bnx2x *bp = params->bp;
7681         if (CHIP_IS_E2(bp))
7682                 gpio_port = BP_PATH(bp);
7683         else
7684                 gpio_port = params->port;
7685         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7686         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7687         return gpio_port ^ (swap_val && swap_override);
7688 }
7689
7690 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7691                                            struct bnx2x_phy *phy,
7692                                            u8 tx_en)
7693 {
7694         u16 val;
7695         u8 port = params->port;
7696         struct bnx2x *bp = params->bp;
7697         u32 tx_en_mode;
7698
7699         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7700         tx_en_mode = REG_RD(bp, params->shmem_base +
7701                             offsetof(struct shmem_region,
7702                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7703                 PORT_HW_CFG_TX_LASER_MASK;
7704         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7705                            "mode = %x\n", tx_en, port, tx_en_mode);
7706         switch (tx_en_mode) {
7707         case PORT_HW_CFG_TX_LASER_MDIO:
7708
7709                 bnx2x_cl45_read(bp, phy,
7710                                 MDIO_PMA_DEVAD,
7711                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7712                                 &val);
7713
7714                 if (tx_en)
7715                         val &= ~(1<<15);
7716                 else
7717                         val |= (1<<15);
7718
7719                 bnx2x_cl45_write(bp, phy,
7720                                  MDIO_PMA_DEVAD,
7721                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7722                                  val);
7723         break;
7724         case PORT_HW_CFG_TX_LASER_GPIO0:
7725         case PORT_HW_CFG_TX_LASER_GPIO1:
7726         case PORT_HW_CFG_TX_LASER_GPIO2:
7727         case PORT_HW_CFG_TX_LASER_GPIO3:
7728         {
7729                 u16 gpio_pin;
7730                 u8 gpio_port, gpio_mode;
7731                 if (tx_en)
7732                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7733                 else
7734                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7735
7736                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7737                 gpio_port = bnx2x_get_gpio_port(params);
7738                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7739                 break;
7740         }
7741         default:
7742                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7743                 break;
7744         }
7745 }
7746
7747 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7748                                       struct bnx2x_phy *phy,
7749                                       u8 tx_en)
7750 {
7751         struct bnx2x *bp = params->bp;
7752         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7753         if (CHIP_IS_E3(bp))
7754                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7755         else
7756                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7757 }
7758
7759 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7760                                              struct link_params *params,
7761                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7762 {
7763         struct bnx2x *bp = params->bp;
7764         u16 val = 0;
7765         u16 i;
7766         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7767                 DP(NETIF_MSG_LINK,
7768                    "Reading from eeprom is limited to 0xf\n");
7769                 return -EINVAL;
7770         }
7771         /* Set the read command byte count */
7772         bnx2x_cl45_write(bp, phy,
7773                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7774                          (byte_cnt | 0xa000));
7775
7776         /* Set the read command address */
7777         bnx2x_cl45_write(bp, phy,
7778                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7779                          addr);
7780
7781         /* Activate read command */
7782         bnx2x_cl45_write(bp, phy,
7783                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7784                          0x2c0f);
7785
7786         /* Wait up to 500us for command complete status */
7787         for (i = 0; i < 100; i++) {
7788                 bnx2x_cl45_read(bp, phy,
7789                                 MDIO_PMA_DEVAD,
7790                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7791                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7792                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7793                         break;
7794                 udelay(5);
7795         }
7796
7797         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7798                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7799                 DP(NETIF_MSG_LINK,
7800                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7801                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7802                 return -EINVAL;
7803         }
7804
7805         /* Read the buffer */
7806         for (i = 0; i < byte_cnt; i++) {
7807                 bnx2x_cl45_read(bp, phy,
7808                                 MDIO_PMA_DEVAD,
7809                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7810                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7811         }
7812
7813         for (i = 0; i < 100; i++) {
7814                 bnx2x_cl45_read(bp, phy,
7815                                 MDIO_PMA_DEVAD,
7816                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7817                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7818                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7819                         return 0;
7820                 usleep_range(1000, 2000);
7821         }
7822         return -EINVAL;
7823 }
7824
7825 static void bnx2x_warpcore_power_module(struct link_params *params,
7826                                         u8 power)
7827 {
7828         u32 pin_cfg;
7829         struct bnx2x *bp = params->bp;
7830
7831         pin_cfg = (REG_RD(bp, params->shmem_base +
7832                           offsetof(struct shmem_region,
7833                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7834                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7835                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7836
7837         if (pin_cfg == PIN_CFG_NA)
7838                 return;
7839         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7840                        power, pin_cfg);
7841         /* Low ==> corresponding SFP+ module is powered
7842          * high ==> the SFP+ module is powered down
7843          */
7844         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7845 }
7846 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7847                                                  struct link_params *params,
7848                                                  u16 addr, u8 byte_cnt,
7849                                                  u8 *o_buf, u8 is_init)
7850 {
7851         int rc = 0;
7852         u8 i, j = 0, cnt = 0;
7853         u32 data_array[4];
7854         u16 addr32;
7855         struct bnx2x *bp = params->bp;
7856
7857         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7858                 DP(NETIF_MSG_LINK,
7859                    "Reading from eeprom is limited to 16 bytes\n");
7860                 return -EINVAL;
7861         }
7862
7863         /* 4 byte aligned address */
7864         addr32 = addr & (~0x3);
7865         do {
7866                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7867                         bnx2x_warpcore_power_module(params, 0);
7868                         /* Note that 100us are not enough here */
7869                         usleep_range(1000, 2000);
7870                         bnx2x_warpcore_power_module(params, 1);
7871                 }
7872                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7873                                     data_array);
7874         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7875
7876         if (rc == 0) {
7877                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7878                         o_buf[j] = *((u8 *)data_array + i);
7879                         j++;
7880                 }
7881         }
7882
7883         return rc;
7884 }
7885
7886 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7887                                              struct link_params *params,
7888                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7889 {
7890         struct bnx2x *bp = params->bp;
7891         u16 val, i;
7892
7893         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7894                 DP(NETIF_MSG_LINK,
7895                    "Reading from eeprom is limited to 0xf\n");
7896                 return -EINVAL;
7897         }
7898
7899         /* Need to read from 1.8000 to clear it */
7900         bnx2x_cl45_read(bp, phy,
7901                         MDIO_PMA_DEVAD,
7902                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7903                         &val);
7904
7905         /* Set the read command byte count */
7906         bnx2x_cl45_write(bp, phy,
7907                          MDIO_PMA_DEVAD,
7908                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7909                          ((byte_cnt < 2) ? 2 : byte_cnt));
7910
7911         /* Set the read command address */
7912         bnx2x_cl45_write(bp, phy,
7913                          MDIO_PMA_DEVAD,
7914                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7915                          addr);
7916         /* Set the destination address */
7917         bnx2x_cl45_write(bp, phy,
7918                          MDIO_PMA_DEVAD,
7919                          0x8004,
7920                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7921
7922         /* Activate read command */
7923         bnx2x_cl45_write(bp, phy,
7924                          MDIO_PMA_DEVAD,
7925                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7926                          0x8002);
7927         /* Wait appropriate time for two-wire command to finish before
7928          * polling the status register
7929          */
7930         usleep_range(1000, 2000);
7931
7932         /* Wait up to 500us for command complete status */
7933         for (i = 0; i < 100; i++) {
7934                 bnx2x_cl45_read(bp, phy,
7935                                 MDIO_PMA_DEVAD,
7936                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7937                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7938                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7939                         break;
7940                 udelay(5);
7941         }
7942
7943         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7944                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7945                 DP(NETIF_MSG_LINK,
7946                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7947                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7948                 return -EFAULT;
7949         }
7950
7951         /* Read the buffer */
7952         for (i = 0; i < byte_cnt; i++) {
7953                 bnx2x_cl45_read(bp, phy,
7954                                 MDIO_PMA_DEVAD,
7955                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7956                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7957         }
7958
7959         for (i = 0; i < 100; i++) {
7960                 bnx2x_cl45_read(bp, phy,
7961                                 MDIO_PMA_DEVAD,
7962                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7963                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7964                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7965                         return 0;
7966                 usleep_range(1000, 2000);
7967         }
7968
7969         return -EINVAL;
7970 }
7971
7972 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7973                                  struct link_params *params, u16 addr,
7974                                  u8 byte_cnt, u8 *o_buf)
7975 {
7976         int rc = -EOPNOTSUPP;
7977         switch (phy->type) {
7978         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7979                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7980                                                        byte_cnt, o_buf);
7981         break;
7982         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7983         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7984                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7985                                                        byte_cnt, o_buf);
7986         break;
7987         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7988                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7989                                                            byte_cnt, o_buf, 0);
7990         break;
7991         }
7992         return rc;
7993 }
7994
7995 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7996                               struct link_params *params,
7997                               u16 *edc_mode)
7998 {
7999         struct bnx2x *bp = params->bp;
8000         u32 sync_offset = 0, phy_idx, media_types;
8001         u8 gport, val[2], check_limiting_mode = 0;
8002         *edc_mode = EDC_MODE_LIMITING;
8003         phy->media_type = ETH_PHY_UNSPECIFIED;
8004         /* First check for copper cable */
8005         if (bnx2x_read_sfp_module_eeprom(phy,
8006                                          params,
8007                                          SFP_EEPROM_CON_TYPE_ADDR,
8008                                          2,
8009                                          (u8 *)val) != 0) {
8010                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8011                 return -EINVAL;
8012         }
8013
8014         switch (val[0]) {
8015         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8016         {
8017                 u8 copper_module_type;
8018                 phy->media_type = ETH_PHY_DA_TWINAX;
8019                 /* Check if its active cable (includes SFP+ module)
8020                  * of passive cable
8021                  */
8022                 if (bnx2x_read_sfp_module_eeprom(phy,
8023                                                params,
8024                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8025                                                1,
8026                                                &copper_module_type) != 0) {
8027                         DP(NETIF_MSG_LINK,
8028                                 "Failed to read copper-cable-type"
8029                                 " from SFP+ EEPROM\n");
8030                         return -EINVAL;
8031                 }
8032
8033                 if (copper_module_type &
8034                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8035                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8036                         check_limiting_mode = 1;
8037                 } else if (copper_module_type &
8038                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8039                                 DP(NETIF_MSG_LINK,
8040                                    "Passive Copper cable detected\n");
8041                                 *edc_mode =
8042                                       EDC_MODE_PASSIVE_DAC;
8043                 } else {
8044                         DP(NETIF_MSG_LINK,
8045                            "Unknown copper-cable-type 0x%x !!!\n",
8046                            copper_module_type);
8047                         return -EINVAL;
8048                 }
8049                 break;
8050         }
8051         case SFP_EEPROM_CON_TYPE_VAL_LC:
8052                 check_limiting_mode = 1;
8053                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8054                                SFP_EEPROM_COMP_CODE_LR_MASK |
8055                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8056                         DP(NETIF_MSG_LINK, "1G Optic module detected\n");
8057                         gport = params->port;
8058                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8059                         phy->req_line_speed = SPEED_1000;
8060                         if (!CHIP_IS_E1x(bp))
8061                                 gport = BP_PATH(bp) + (params->port << 1);
8062                         netdev_err(bp->dev, "Warning: Link speed was forced to 1000Mbps."
8063                               " Current SFP module in port %d is not"
8064                               " compliant with 10G Ethernet\n",
8065                          gport);
8066                 } else {
8067                         int idx, cfg_idx = 0;
8068                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8069                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8070                                 if (params->phy[idx].type == phy->type) {
8071                                         cfg_idx = LINK_CONFIG_IDX(idx);
8072                                         break;
8073                                 }
8074                         }
8075                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8076                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8077                 }
8078                 break;
8079         default:
8080                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8081                          val[0]);
8082                 return -EINVAL;
8083         }
8084         sync_offset = params->shmem_base +
8085                 offsetof(struct shmem_region,
8086                          dev_info.port_hw_config[params->port].media_type);
8087         media_types = REG_RD(bp, sync_offset);
8088         /* Update media type for non-PMF sync */
8089         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8090                 if (&(params->phy[phy_idx]) == phy) {
8091                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8092                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8093                         media_types |= ((phy->media_type &
8094                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8095                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8096                         break;
8097                 }
8098         }
8099         REG_WR(bp, sync_offset, media_types);
8100         if (check_limiting_mode) {
8101                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8102                 if (bnx2x_read_sfp_module_eeprom(phy,
8103                                                  params,
8104                                                  SFP_EEPROM_OPTIONS_ADDR,
8105                                                  SFP_EEPROM_OPTIONS_SIZE,
8106                                                  options) != 0) {
8107                         DP(NETIF_MSG_LINK,
8108                            "Failed to read Option field from module EEPROM\n");
8109                         return -EINVAL;
8110                 }
8111                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8112                         *edc_mode = EDC_MODE_LINEAR;
8113                 else
8114                         *edc_mode = EDC_MODE_LIMITING;
8115         }
8116         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8117         return 0;
8118 }
8119 /* This function read the relevant field from the module (SFP+), and verify it
8120  * is compliant with this board
8121  */
8122 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8123                                    struct link_params *params)
8124 {
8125         struct bnx2x *bp = params->bp;
8126         u32 val, cmd;
8127         u32 fw_resp, fw_cmd_param;
8128         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8129         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8130         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8131         val = REG_RD(bp, params->shmem_base +
8132                          offsetof(struct shmem_region, dev_info.
8133                                   port_feature_config[params->port].config));
8134         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8135             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8136                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8137                 return 0;
8138         }
8139
8140         if (params->feature_config_flags &
8141             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8142                 /* Use specific phy request */
8143                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8144         } else if (params->feature_config_flags &
8145                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8146                 /* Use first phy request only in case of non-dual media*/
8147                 if (DUAL_MEDIA(params)) {
8148                         DP(NETIF_MSG_LINK,
8149                            "FW does not support OPT MDL verification\n");
8150                         return -EINVAL;
8151                 }
8152                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8153         } else {
8154                 /* No support in OPT MDL detection */
8155                 DP(NETIF_MSG_LINK,
8156                    "FW does not support OPT MDL verification\n");
8157                 return -EINVAL;
8158         }
8159
8160         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8161         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8162         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8163                 DP(NETIF_MSG_LINK, "Approved module\n");
8164                 return 0;
8165         }
8166
8167         /* Format the warning message */
8168         if (bnx2x_read_sfp_module_eeprom(phy,
8169                                          params,
8170                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8171                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8172                                          (u8 *)vendor_name))
8173                 vendor_name[0] = '\0';
8174         else
8175                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8176         if (bnx2x_read_sfp_module_eeprom(phy,
8177                                          params,
8178                                          SFP_EEPROM_PART_NO_ADDR,
8179                                          SFP_EEPROM_PART_NO_SIZE,
8180                                          (u8 *)vendor_pn))
8181                 vendor_pn[0] = '\0';
8182         else
8183                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8184
8185         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8186                               " Port %d from %s part number %s\n",
8187                          params->port, vendor_name, vendor_pn);
8188         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8189             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8190                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8191         return -EINVAL;
8192 }
8193
8194 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8195                                                  struct link_params *params)
8196
8197 {
8198         u8 val;
8199         int rc;
8200         struct bnx2x *bp = params->bp;
8201         u16 timeout;
8202         /* Initialization time after hot-plug may take up to 300ms for
8203          * some phys type ( e.g. JDSU )
8204          */
8205
8206         for (timeout = 0; timeout < 60; timeout++) {
8207                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8208                         rc = bnx2x_warpcore_read_sfp_module_eeprom(phy,
8209                                                                    params, 1,
8210                                                                    1, &val, 1);
8211                 else
8212                         rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1,
8213                                                           &val);
8214                 if (rc == 0) {
8215                         DP(NETIF_MSG_LINK,
8216                            "SFP+ module initialization took %d ms\n",
8217                            timeout * 5);
8218                         return 0;
8219                 }
8220                 usleep_range(5000, 10000);
8221         }
8222         rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val);
8223         return rc;
8224 }
8225
8226 static void bnx2x_8727_power_module(struct bnx2x *bp,
8227                                     struct bnx2x_phy *phy,
8228                                     u8 is_power_up) {
8229         /* Make sure GPIOs are not using for LED mode */
8230         u16 val;
8231         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8232          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8233          * output
8234          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8235          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8236          * where the 1st bit is the over-current(only input), and 2nd bit is
8237          * for power( only output )
8238          *
8239          * In case of NOC feature is disabled and power is up, set GPIO control
8240          *  as input to enable listening of over-current indication
8241          */
8242         if (phy->flags & FLAGS_NOC)
8243                 return;
8244         if (is_power_up)
8245                 val = (1<<4);
8246         else
8247                 /* Set GPIO control to OUTPUT, and set the power bit
8248                  * to according to the is_power_up
8249                  */
8250                 val = (1<<1);
8251
8252         bnx2x_cl45_write(bp, phy,
8253                          MDIO_PMA_DEVAD,
8254                          MDIO_PMA_REG_8727_GPIO_CTRL,
8255                          val);
8256 }
8257
8258 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8259                                         struct bnx2x_phy *phy,
8260                                         u16 edc_mode)
8261 {
8262         u16 cur_limiting_mode;
8263
8264         bnx2x_cl45_read(bp, phy,
8265                         MDIO_PMA_DEVAD,
8266                         MDIO_PMA_REG_ROM_VER2,
8267                         &cur_limiting_mode);
8268         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8269                  cur_limiting_mode);
8270
8271         if (edc_mode == EDC_MODE_LIMITING) {
8272                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8273                 bnx2x_cl45_write(bp, phy,
8274                                  MDIO_PMA_DEVAD,
8275                                  MDIO_PMA_REG_ROM_VER2,
8276                                  EDC_MODE_LIMITING);
8277         } else { /* LRM mode ( default )*/
8278
8279                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8280
8281                 /* Changing to LRM mode takes quite few seconds. So do it only
8282                  * if current mode is limiting (default is LRM)
8283                  */
8284                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8285                         return 0;
8286
8287                 bnx2x_cl45_write(bp, phy,
8288                                  MDIO_PMA_DEVAD,
8289                                  MDIO_PMA_REG_LRM_MODE,
8290                                  0);
8291                 bnx2x_cl45_write(bp, phy,
8292                                  MDIO_PMA_DEVAD,
8293                                  MDIO_PMA_REG_ROM_VER2,
8294                                  0x128);
8295                 bnx2x_cl45_write(bp, phy,
8296                                  MDIO_PMA_DEVAD,
8297                                  MDIO_PMA_REG_MISC_CTRL0,
8298                                  0x4008);
8299                 bnx2x_cl45_write(bp, phy,
8300                                  MDIO_PMA_DEVAD,
8301                                  MDIO_PMA_REG_LRM_MODE,
8302                                  0xaaaa);
8303         }
8304         return 0;
8305 }
8306
8307 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8308                                         struct bnx2x_phy *phy,
8309                                         u16 edc_mode)
8310 {
8311         u16 phy_identifier;
8312         u16 rom_ver2_val;
8313         bnx2x_cl45_read(bp, phy,
8314                         MDIO_PMA_DEVAD,
8315                         MDIO_PMA_REG_PHY_IDENTIFIER,
8316                         &phy_identifier);
8317
8318         bnx2x_cl45_write(bp, phy,
8319                          MDIO_PMA_DEVAD,
8320                          MDIO_PMA_REG_PHY_IDENTIFIER,
8321                          (phy_identifier & ~(1<<9)));
8322
8323         bnx2x_cl45_read(bp, phy,
8324                         MDIO_PMA_DEVAD,
8325                         MDIO_PMA_REG_ROM_VER2,
8326                         &rom_ver2_val);
8327         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8328         bnx2x_cl45_write(bp, phy,
8329                          MDIO_PMA_DEVAD,
8330                          MDIO_PMA_REG_ROM_VER2,
8331                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8332
8333         bnx2x_cl45_write(bp, phy,
8334                          MDIO_PMA_DEVAD,
8335                          MDIO_PMA_REG_PHY_IDENTIFIER,
8336                          (phy_identifier | (1<<9)));
8337
8338         return 0;
8339 }
8340
8341 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8342                                      struct link_params *params,
8343                                      u32 action)
8344 {
8345         struct bnx2x *bp = params->bp;
8346         u16 val;
8347         switch (action) {
8348         case DISABLE_TX:
8349                 bnx2x_sfp_set_transmitter(params, phy, 0);
8350                 break;
8351         case ENABLE_TX:
8352                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8353                         bnx2x_sfp_set_transmitter(params, phy, 1);
8354                 break;
8355         case PHY_INIT:
8356                 bnx2x_cl45_write(bp, phy,
8357                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8358                                  (1<<2) | (1<<5));
8359                 bnx2x_cl45_write(bp, phy,
8360                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8361                                  0);
8362                 bnx2x_cl45_write(bp, phy,
8363                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8364                 /* Make MOD_ABS give interrupt on change */
8365                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8366                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8367                                 &val);
8368                 val |= (1<<12);
8369                 if (phy->flags & FLAGS_NOC)
8370                         val |= (3<<5);
8371                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8372                  * status which reflect SFP+ module over-current
8373                  */
8374                 if (!(phy->flags & FLAGS_NOC))
8375                         val &= 0xff8f; /* Reset bits 4-6 */
8376                 bnx2x_cl45_write(bp, phy,
8377                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8378                                  val);
8379
8380                 /* Set 2-wire transfer rate of SFP+ module EEPROM
8381                  * to 100Khz since some DACs(direct attached cables) do
8382                  * not work at 400Khz.
8383                  */
8384                 bnx2x_cl45_write(bp, phy,
8385                                  MDIO_PMA_DEVAD,
8386                                  MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8387                                  0xa001);
8388                 break;
8389         default:
8390                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8391                    action);
8392                 return;
8393         }
8394 }
8395
8396 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8397                                            u8 gpio_mode)
8398 {
8399         struct bnx2x *bp = params->bp;
8400
8401         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8402                             offsetof(struct shmem_region,
8403                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8404                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8405         switch (fault_led_gpio) {
8406         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8407                 return;
8408         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8409         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8410         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8411         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8412         {
8413                 u8 gpio_port = bnx2x_get_gpio_port(params);
8414                 u16 gpio_pin = fault_led_gpio -
8415                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8416                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8417                                    "pin %x port %x mode %x\n",
8418                                gpio_pin, gpio_port, gpio_mode);
8419                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8420         }
8421         break;
8422         default:
8423                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8424                                fault_led_gpio);
8425         }
8426 }
8427
8428 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8429                                           u8 gpio_mode)
8430 {
8431         u32 pin_cfg;
8432         u8 port = params->port;
8433         struct bnx2x *bp = params->bp;
8434         pin_cfg = (REG_RD(bp, params->shmem_base +
8435                          offsetof(struct shmem_region,
8436                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8437                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8438                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8439         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8440                        gpio_mode, pin_cfg);
8441         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8442 }
8443
8444 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8445                                            u8 gpio_mode)
8446 {
8447         struct bnx2x *bp = params->bp;
8448         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8449         if (CHIP_IS_E3(bp)) {
8450                 /* Low ==> if SFP+ module is supported otherwise
8451                  * High ==> if SFP+ module is not on the approved vendor list
8452                  */
8453                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8454         } else
8455                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8456 }
8457
8458 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8459                                     struct link_params *params)
8460 {
8461         struct bnx2x *bp = params->bp;
8462         bnx2x_warpcore_power_module(params, 0);
8463         /* Put Warpcore in low power mode */
8464         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8465
8466         /* Put LCPLL in low power mode */
8467         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8468         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8469         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8470 }
8471
8472 static void bnx2x_power_sfp_module(struct link_params *params,
8473                                    struct bnx2x_phy *phy,
8474                                    u8 power)
8475 {
8476         struct bnx2x *bp = params->bp;
8477         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8478
8479         switch (phy->type) {
8480         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8481         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8482                 bnx2x_8727_power_module(params->bp, phy, power);
8483                 break;
8484         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8485                 bnx2x_warpcore_power_module(params, power);
8486                 break;
8487         default:
8488                 break;
8489         }
8490 }
8491 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8492                                              struct bnx2x_phy *phy,
8493                                              u16 edc_mode)
8494 {
8495         u16 val = 0;
8496         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8497         struct bnx2x *bp = params->bp;
8498
8499         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8500         /* This is a global register which controls all lanes */
8501         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8502                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8503         val &= ~(0xf << (lane << 2));
8504
8505         switch (edc_mode) {
8506         case EDC_MODE_LINEAR:
8507         case EDC_MODE_LIMITING:
8508                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8509                 break;
8510         case EDC_MODE_PASSIVE_DAC:
8511                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8512                 break;
8513         default:
8514                 break;
8515         }
8516
8517         val |= (mode << (lane << 2));
8518         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8519                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8520         /* A must read */
8521         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8522                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8523
8524         /* Restart microcode to re-read the new mode */
8525         bnx2x_warpcore_reset_lane(bp, phy, 1);
8526         bnx2x_warpcore_reset_lane(bp, phy, 0);
8527
8528 }
8529
8530 static void bnx2x_set_limiting_mode(struct link_params *params,
8531                                     struct bnx2x_phy *phy,
8532                                     u16 edc_mode)
8533 {
8534         switch (phy->type) {
8535         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8536                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8537                 break;
8538         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8539         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8540                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8541                 break;
8542         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8543                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8544                 break;
8545         }
8546 }
8547
8548 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8549                                struct link_params *params)
8550 {
8551         struct bnx2x *bp = params->bp;
8552         u16 edc_mode;
8553         int rc = 0;
8554
8555         u32 val = REG_RD(bp, params->shmem_base +
8556                              offsetof(struct shmem_region, dev_info.
8557                                      port_feature_config[params->port].config));
8558         /* Enabled transmitter by default */
8559         bnx2x_sfp_set_transmitter(params, phy, 1);
8560         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8561                  params->port);
8562         /* Power up module */
8563         bnx2x_power_sfp_module(params, phy, 1);
8564         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8565                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8566                 return -EINVAL;
8567         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8568                 /* Check SFP+ module compatibility */
8569                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8570                 rc = -EINVAL;
8571                 /* Turn on fault module-detected led */
8572                 bnx2x_set_sfp_module_fault_led(params,
8573                                                MISC_REGISTERS_GPIO_HIGH);
8574
8575                 /* Check if need to power down the SFP+ module */
8576                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8577                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8578                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8579                         bnx2x_power_sfp_module(params, phy, 0);
8580                         return rc;
8581                 }
8582         } else {
8583                 /* Turn off fault module-detected led */
8584                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8585         }
8586
8587         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8588          * is done automatically
8589          */
8590         bnx2x_set_limiting_mode(params, phy, edc_mode);
8591
8592         /* Disable transmit for this module if the module is not approved, and
8593          * laser needs to be disabled.
8594          */
8595         if ((rc) &&
8596             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8597              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8598                 bnx2x_sfp_set_transmitter(params, phy, 0);
8599
8600         return rc;
8601 }
8602
8603 void bnx2x_handle_module_detect_int(struct link_params *params)
8604 {
8605         struct bnx2x *bp = params->bp;
8606         struct bnx2x_phy *phy;
8607         u32 gpio_val;
8608         u8 gpio_num, gpio_port;
8609         if (CHIP_IS_E3(bp)) {
8610                 phy = &params->phy[INT_PHY];
8611                 /* Always enable TX laser,will be disabled in case of fault */
8612                 bnx2x_sfp_set_transmitter(params, phy, 1);
8613         } else {
8614                 phy = &params->phy[EXT_PHY1];
8615         }
8616         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8617                                       params->port, &gpio_num, &gpio_port) ==
8618             -EINVAL) {
8619                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8620                 return;
8621         }
8622
8623         /* Set valid module led off */
8624         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8625
8626         /* Get current gpio val reflecting module plugged in / out*/
8627         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8628
8629         /* Call the handling function in case module is detected */
8630         if (gpio_val == 0) {
8631                 bnx2x_set_mdio_emac_per_phy(bp, params);
8632                 bnx2x_set_aer_mmd(params, phy);
8633
8634                 bnx2x_power_sfp_module(params, phy, 1);
8635                 bnx2x_set_gpio_int(bp, gpio_num,
8636                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8637                                    gpio_port);
8638                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8639                         bnx2x_sfp_module_detection(phy, params);
8640                         if (CHIP_IS_E3(bp)) {
8641                                 u16 rx_tx_in_reset;
8642                                 /* In case WC is out of reset, reconfigure the
8643                                  * link speed while taking into account 1G
8644                                  * module limitation.
8645                                  */
8646                                 bnx2x_cl45_read(bp, phy,
8647                                                 MDIO_WC_DEVAD,
8648                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8649                                                 &rx_tx_in_reset);
8650                                 if ((!rx_tx_in_reset) &&
8651                                     (params->link_flags &
8652                                      PHY_INITIALIZED)) {
8653                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8654                                         bnx2x_warpcore_config_sfi(phy, params);
8655                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8656                                 }
8657                         }
8658                 } else {
8659                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8660                 }
8661         } else {
8662                 bnx2x_set_gpio_int(bp, gpio_num,
8663                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8664                                    gpio_port);
8665                 /* Module was plugged out.
8666                  * Disable transmit for this module
8667                  */
8668                 phy->media_type = ETH_PHY_NOT_PRESENT;
8669         }
8670 }
8671
8672 /******************************************************************/
8673 /*              Used by 8706 and 8727                             */
8674 /******************************************************************/
8675 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8676                                  struct bnx2x_phy *phy,
8677                                  u16 alarm_status_offset,
8678                                  u16 alarm_ctrl_offset)
8679 {
8680         u16 alarm_status, val;
8681         bnx2x_cl45_read(bp, phy,
8682                         MDIO_PMA_DEVAD, alarm_status_offset,
8683                         &alarm_status);
8684         bnx2x_cl45_read(bp, phy,
8685                         MDIO_PMA_DEVAD, alarm_status_offset,
8686                         &alarm_status);
8687         /* Mask or enable the fault event. */
8688         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8689         if (alarm_status & (1<<0))
8690                 val &= ~(1<<0);
8691         else
8692                 val |= (1<<0);
8693         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8694 }
8695 /******************************************************************/
8696 /*              common BCM8706/BCM8726 PHY SECTION                */
8697 /******************************************************************/
8698 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8699                                       struct link_params *params,
8700                                       struct link_vars *vars)
8701 {
8702         u8 link_up = 0;
8703         u16 val1, val2, rx_sd, pcs_status;
8704         struct bnx2x *bp = params->bp;
8705         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8706         /* Clear RX Alarm*/
8707         bnx2x_cl45_read(bp, phy,
8708                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8709
8710         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8711                              MDIO_PMA_LASI_TXCTRL);
8712
8713         /* Clear LASI indication*/
8714         bnx2x_cl45_read(bp, phy,
8715                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8716         bnx2x_cl45_read(bp, phy,
8717                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8718         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8719
8720         bnx2x_cl45_read(bp, phy,
8721                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8722         bnx2x_cl45_read(bp, phy,
8723                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8724         bnx2x_cl45_read(bp, phy,
8725                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8726         bnx2x_cl45_read(bp, phy,
8727                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8728
8729         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8730                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8731         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8732          * are set, or if the autoneg bit 1 is set
8733          */
8734         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8735         if (link_up) {
8736                 if (val2 & (1<<1))
8737                         vars->line_speed = SPEED_1000;
8738                 else
8739                         vars->line_speed = SPEED_10000;
8740                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8741                 vars->duplex = DUPLEX_FULL;
8742         }
8743
8744         /* Capture 10G link fault. Read twice to clear stale value. */
8745         if (vars->line_speed == SPEED_10000) {
8746                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8747                             MDIO_PMA_LASI_TXSTAT, &val1);
8748                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8749                             MDIO_PMA_LASI_TXSTAT, &val1);
8750                 if (val1 & (1<<0))
8751                         vars->fault_detected = 1;
8752         }
8753
8754         return link_up;
8755 }
8756
8757 /******************************************************************/
8758 /*                      BCM8706 PHY SECTION                       */
8759 /******************************************************************/
8760 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8761                                  struct link_params *params,
8762                                  struct link_vars *vars)
8763 {
8764         u32 tx_en_mode;
8765         u16 cnt, val, tmp1;
8766         struct bnx2x *bp = params->bp;
8767
8768         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8769                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8770         /* HW reset */
8771         bnx2x_ext_phy_hw_reset(bp, params->port);
8772         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8773         bnx2x_wait_reset_complete(bp, phy, params);
8774
8775         /* Wait until fw is loaded */
8776         for (cnt = 0; cnt < 100; cnt++) {
8777                 bnx2x_cl45_read(bp, phy,
8778                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8779                 if (val)
8780                         break;
8781                 usleep_range(10000, 20000);
8782         }
8783         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8784         if ((params->feature_config_flags &
8785              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8786                 u8 i;
8787                 u16 reg;
8788                 for (i = 0; i < 4; i++) {
8789                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8790                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8791                                    MDIO_XS_8706_REG_BANK_RX0);
8792                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8793                         /* Clear first 3 bits of the control */
8794                         val &= ~0x7;
8795                         /* Set control bits according to configuration */
8796                         val |= (phy->rx_preemphasis[i] & 0x7);
8797                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8798                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8799                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8800                 }
8801         }
8802         /* Force speed */
8803         if (phy->req_line_speed == SPEED_10000) {
8804                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8805
8806                 bnx2x_cl45_write(bp, phy,
8807                                  MDIO_PMA_DEVAD,
8808                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8809                 bnx2x_cl45_write(bp, phy,
8810                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8811                                  0);
8812                 /* Arm LASI for link and Tx fault. */
8813                 bnx2x_cl45_write(bp, phy,
8814                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8815         } else {
8816                 /* Force 1Gbps using autoneg with 1G advertisement */
8817
8818                 /* Allow CL37 through CL73 */
8819                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8820                 bnx2x_cl45_write(bp, phy,
8821                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8822
8823                 /* Enable Full-Duplex advertisement on CL37 */
8824                 bnx2x_cl45_write(bp, phy,
8825                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8826                 /* Enable CL37 AN */
8827                 bnx2x_cl45_write(bp, phy,
8828                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8829                 /* 1G support */
8830                 bnx2x_cl45_write(bp, phy,
8831                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8832
8833                 /* Enable clause 73 AN */
8834                 bnx2x_cl45_write(bp, phy,
8835                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8836                 bnx2x_cl45_write(bp, phy,
8837                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8838                                  0x0400);
8839                 bnx2x_cl45_write(bp, phy,
8840                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8841                                  0x0004);
8842         }
8843         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8844
8845         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8846          * power mode, if TX Laser is disabled
8847          */
8848
8849         tx_en_mode = REG_RD(bp, params->shmem_base +
8850                             offsetof(struct shmem_region,
8851                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8852                         & PORT_HW_CFG_TX_LASER_MASK;
8853
8854         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8855                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8856                 bnx2x_cl45_read(bp, phy,
8857                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8858                 tmp1 |= 0x1;
8859                 bnx2x_cl45_write(bp, phy,
8860                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8861         }
8862
8863         return 0;
8864 }
8865
8866 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8867                                   struct link_params *params,
8868                                   struct link_vars *vars)
8869 {
8870         return bnx2x_8706_8726_read_status(phy, params, vars);
8871 }
8872
8873 /******************************************************************/
8874 /*                      BCM8726 PHY SECTION                       */
8875 /******************************************************************/
8876 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8877                                        struct link_params *params)
8878 {
8879         struct bnx2x *bp = params->bp;
8880         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8881         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8882 }
8883
8884 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8885                                          struct link_params *params)
8886 {
8887         struct bnx2x *bp = params->bp;
8888         /* Need to wait 100ms after reset */
8889         msleep(100);
8890
8891         /* Micro controller re-boot */
8892         bnx2x_cl45_write(bp, phy,
8893                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8894
8895         /* Set soft reset */
8896         bnx2x_cl45_write(bp, phy,
8897                          MDIO_PMA_DEVAD,
8898                          MDIO_PMA_REG_GEN_CTRL,
8899                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8900
8901         bnx2x_cl45_write(bp, phy,
8902                          MDIO_PMA_DEVAD,
8903                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8904
8905         bnx2x_cl45_write(bp, phy,
8906                          MDIO_PMA_DEVAD,
8907                          MDIO_PMA_REG_GEN_CTRL,
8908                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8909
8910         /* Wait for 150ms for microcode load */
8911         msleep(150);
8912
8913         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8914         bnx2x_cl45_write(bp, phy,
8915                          MDIO_PMA_DEVAD,
8916                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8917
8918         msleep(200);
8919         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8920 }
8921
8922 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8923                                  struct link_params *params,
8924                                  struct link_vars *vars)
8925 {
8926         struct bnx2x *bp = params->bp;
8927         u16 val1;
8928         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8929         if (link_up) {
8930                 bnx2x_cl45_read(bp, phy,
8931                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8932                                 &val1);
8933                 if (val1 & (1<<15)) {
8934                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8935                         link_up = 0;
8936                         vars->line_speed = 0;
8937                 }
8938         }
8939         return link_up;
8940 }
8941
8942
8943 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8944                                   struct link_params *params,
8945                                   struct link_vars *vars)
8946 {
8947         struct bnx2x *bp = params->bp;
8948         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8949
8950         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8951         bnx2x_wait_reset_complete(bp, phy, params);
8952
8953         bnx2x_8726_external_rom_boot(phy, params);
8954
8955         /* Need to call module detected on initialization since the module
8956          * detection triggered by actual module insertion might occur before
8957          * driver is loaded, and when driver is loaded, it reset all
8958          * registers, including the transmitter
8959          */
8960         bnx2x_sfp_module_detection(phy, params);
8961
8962         if (phy->req_line_speed == SPEED_1000) {
8963                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8964                 bnx2x_cl45_write(bp, phy,
8965                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8966                 bnx2x_cl45_write(bp, phy,
8967                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8968                 bnx2x_cl45_write(bp, phy,
8969                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8970                 bnx2x_cl45_write(bp, phy,
8971                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8972                                  0x400);
8973         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8974                    (phy->speed_cap_mask &
8975                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8976                    ((phy->speed_cap_mask &
8977                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8978                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8979                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8980                 /* Set Flow control */
8981                 bnx2x_ext_phy_set_pause(params, phy, vars);
8982                 bnx2x_cl45_write(bp, phy,
8983                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8984                 bnx2x_cl45_write(bp, phy,
8985                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8986                 bnx2x_cl45_write(bp, phy,
8987                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8988                 bnx2x_cl45_write(bp, phy,
8989                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8990                 bnx2x_cl45_write(bp, phy,
8991                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8992                 /* Enable RX-ALARM control to receive interrupt for 1G speed
8993                  * change
8994                  */
8995                 bnx2x_cl45_write(bp, phy,
8996                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8997                 bnx2x_cl45_write(bp, phy,
8998                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8999                                  0x400);
9000
9001         } else { /* Default 10G. Set only LASI control */
9002                 bnx2x_cl45_write(bp, phy,
9003                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9004         }
9005
9006         /* Set TX PreEmphasis if needed */
9007         if ((params->feature_config_flags &
9008              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9009                 DP(NETIF_MSG_LINK,
9010                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9011                          phy->tx_preemphasis[0],
9012                          phy->tx_preemphasis[1]);
9013                 bnx2x_cl45_write(bp, phy,
9014                                  MDIO_PMA_DEVAD,
9015                                  MDIO_PMA_REG_8726_TX_CTRL1,
9016                                  phy->tx_preemphasis[0]);
9017
9018                 bnx2x_cl45_write(bp, phy,
9019                                  MDIO_PMA_DEVAD,
9020                                  MDIO_PMA_REG_8726_TX_CTRL2,
9021                                  phy->tx_preemphasis[1]);
9022         }
9023
9024         return 0;
9025
9026 }
9027
9028 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9029                                   struct link_params *params)
9030 {
9031         struct bnx2x *bp = params->bp;
9032         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9033         /* Set serial boot control for external load */
9034         bnx2x_cl45_write(bp, phy,
9035                          MDIO_PMA_DEVAD,
9036                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9037 }
9038
9039 /******************************************************************/
9040 /*                      BCM8727 PHY SECTION                       */
9041 /******************************************************************/
9042
9043 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9044                                     struct link_params *params, u8 mode)
9045 {
9046         struct bnx2x *bp = params->bp;
9047         u16 led_mode_bitmask = 0;
9048         u16 gpio_pins_bitmask = 0;
9049         u16 val;
9050         /* Only NOC flavor requires to set the LED specifically */
9051         if (!(phy->flags & FLAGS_NOC))
9052                 return;
9053         switch (mode) {
9054         case LED_MODE_FRONT_PANEL_OFF:
9055         case LED_MODE_OFF:
9056                 led_mode_bitmask = 0;
9057                 gpio_pins_bitmask = 0x03;
9058                 break;
9059         case LED_MODE_ON:
9060                 led_mode_bitmask = 0;
9061                 gpio_pins_bitmask = 0x02;
9062                 break;
9063         case LED_MODE_OPER:
9064                 led_mode_bitmask = 0x60;
9065                 gpio_pins_bitmask = 0x11;
9066                 break;
9067         }
9068         bnx2x_cl45_read(bp, phy,
9069                         MDIO_PMA_DEVAD,
9070                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9071                         &val);
9072         val &= 0xff8f;
9073         val |= led_mode_bitmask;
9074         bnx2x_cl45_write(bp, phy,
9075                          MDIO_PMA_DEVAD,
9076                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9077                          val);
9078         bnx2x_cl45_read(bp, phy,
9079                         MDIO_PMA_DEVAD,
9080                         MDIO_PMA_REG_8727_GPIO_CTRL,
9081                         &val);
9082         val &= 0xffe0;
9083         val |= gpio_pins_bitmask;
9084         bnx2x_cl45_write(bp, phy,
9085                          MDIO_PMA_DEVAD,
9086                          MDIO_PMA_REG_8727_GPIO_CTRL,
9087                          val);
9088 }
9089 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9090                                 struct link_params *params) {
9091         u32 swap_val, swap_override;
9092         u8 port;
9093         /* The PHY reset is controlled by GPIO 1. Fake the port number
9094          * to cancel the swap done in set_gpio()
9095          */
9096         struct bnx2x *bp = params->bp;
9097         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9098         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9099         port = (swap_val && swap_override) ^ 1;
9100         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9101                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9102 }
9103
9104 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9105                                     struct link_params *params)
9106 {
9107         struct bnx2x *bp = params->bp;
9108         u16 tmp1, val;
9109         /* Set option 1G speed */
9110         if ((phy->req_line_speed == SPEED_1000) ||
9111             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9112                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9113                 bnx2x_cl45_write(bp, phy,
9114                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9115                 bnx2x_cl45_write(bp, phy,
9116                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9117                 bnx2x_cl45_read(bp, phy,
9118                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9119                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9120                 /* Power down the XAUI until link is up in case of dual-media
9121                  * and 1G
9122                  */
9123                 if (DUAL_MEDIA(params)) {
9124                         bnx2x_cl45_read(bp, phy,
9125                                         MDIO_PMA_DEVAD,
9126                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9127                         val |= (3<<10);
9128                         bnx2x_cl45_write(bp, phy,
9129                                          MDIO_PMA_DEVAD,
9130                                          MDIO_PMA_REG_8727_PCS_GP, val);
9131                 }
9132         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9133                    ((phy->speed_cap_mask &
9134                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9135                    ((phy->speed_cap_mask &
9136                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9137                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9138
9139                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9140                 bnx2x_cl45_write(bp, phy,
9141                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9142                 bnx2x_cl45_write(bp, phy,
9143                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9144         } else {
9145                 /* Since the 8727 has only single reset pin, need to set the 10G
9146                  * registers although it is default
9147                  */
9148                 bnx2x_cl45_write(bp, phy,
9149                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9150                                  0x0020);
9151                 bnx2x_cl45_write(bp, phy,
9152                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9153                 bnx2x_cl45_write(bp, phy,
9154                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9155                 bnx2x_cl45_write(bp, phy,
9156                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9157                                  0x0008);
9158         }
9159 }
9160
9161 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9162                                   struct link_params *params,
9163                                   struct link_vars *vars)
9164 {
9165         u32 tx_en_mode;
9166         u16 tmp1, mod_abs, tmp2;
9167         struct bnx2x *bp = params->bp;
9168         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9169
9170         bnx2x_wait_reset_complete(bp, phy, params);
9171
9172         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9173
9174         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9175         /* Initially configure MOD_ABS to interrupt when module is
9176          * presence( bit 8)
9177          */
9178         bnx2x_cl45_read(bp, phy,
9179                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9180         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9181          * When the EDC is off it locks onto a reference clock and avoids
9182          * becoming 'lost'
9183          */
9184         mod_abs &= ~(1<<8);
9185         if (!(phy->flags & FLAGS_NOC))
9186                 mod_abs &= ~(1<<9);
9187         bnx2x_cl45_write(bp, phy,
9188                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9189
9190         /* Enable/Disable PHY transmitter output */
9191         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9192
9193         bnx2x_8727_power_module(bp, phy, 1);
9194
9195         bnx2x_cl45_read(bp, phy,
9196                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9197
9198         bnx2x_cl45_read(bp, phy,
9199                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9200
9201         bnx2x_8727_config_speed(phy, params);
9202
9203
9204         /* Set TX PreEmphasis if needed */
9205         if ((params->feature_config_flags &
9206              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9207                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9208                            phy->tx_preemphasis[0],
9209                            phy->tx_preemphasis[1]);
9210                 bnx2x_cl45_write(bp, phy,
9211                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9212                                  phy->tx_preemphasis[0]);
9213
9214                 bnx2x_cl45_write(bp, phy,
9215                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9216                                  phy->tx_preemphasis[1]);
9217         }
9218
9219         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9220          * power mode, if TX Laser is disabled
9221          */
9222         tx_en_mode = REG_RD(bp, params->shmem_base +
9223                             offsetof(struct shmem_region,
9224                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9225                         & PORT_HW_CFG_TX_LASER_MASK;
9226
9227         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9228
9229                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9230                 bnx2x_cl45_read(bp, phy,
9231                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9232                 tmp2 |= 0x1000;
9233                 tmp2 &= 0xFFEF;
9234                 bnx2x_cl45_write(bp, phy,
9235                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9236                 bnx2x_cl45_read(bp, phy,
9237                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9238                                 &tmp2);
9239                 bnx2x_cl45_write(bp, phy,
9240                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9241                                  (tmp2 & 0x7fff));
9242         }
9243
9244         return 0;
9245 }
9246
9247 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9248                                       struct link_params *params)
9249 {
9250         struct bnx2x *bp = params->bp;
9251         u16 mod_abs, rx_alarm_status;
9252         u32 val = REG_RD(bp, params->shmem_base +
9253                              offsetof(struct shmem_region, dev_info.
9254                                       port_feature_config[params->port].
9255                                       config));
9256         bnx2x_cl45_read(bp, phy,
9257                         MDIO_PMA_DEVAD,
9258                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9259         if (mod_abs & (1<<8)) {
9260
9261                 /* Module is absent */
9262                 DP(NETIF_MSG_LINK,
9263                    "MOD_ABS indication show module is absent\n");
9264                 phy->media_type = ETH_PHY_NOT_PRESENT;
9265                 /* 1. Set mod_abs to detect next module
9266                  *    presence event
9267                  * 2. Set EDC off by setting OPTXLOS signal input to low
9268                  *    (bit 9).
9269                  *    When the EDC is off it locks onto a reference clock and
9270                  *    avoids becoming 'lost'.
9271                  */
9272                 mod_abs &= ~(1<<8);
9273                 if (!(phy->flags & FLAGS_NOC))
9274                         mod_abs &= ~(1<<9);
9275                 bnx2x_cl45_write(bp, phy,
9276                                  MDIO_PMA_DEVAD,
9277                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9278
9279                 /* Clear RX alarm since it stays up as long as
9280                  * the mod_abs wasn't changed
9281                  */
9282                 bnx2x_cl45_read(bp, phy,
9283                                 MDIO_PMA_DEVAD,
9284                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9285
9286         } else {
9287                 /* Module is present */
9288                 DP(NETIF_MSG_LINK,
9289                    "MOD_ABS indication show module is present\n");
9290                 /* First disable transmitter, and if the module is ok, the
9291                  * module_detection will enable it
9292                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9293                  * 2. Restore the default polarity of the OPRXLOS signal and
9294                  * this signal will then correctly indicate the presence or
9295                  * absence of the Rx signal. (bit 9)
9296                  */
9297                 mod_abs |= (1<<8);
9298                 if (!(phy->flags & FLAGS_NOC))
9299                         mod_abs |= (1<<9);
9300                 bnx2x_cl45_write(bp, phy,
9301                                  MDIO_PMA_DEVAD,
9302                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9303
9304                 /* Clear RX alarm since it stays up as long as the mod_abs
9305                  * wasn't changed. This is need to be done before calling the
9306                  * module detection, otherwise it will clear* the link update
9307                  * alarm
9308                  */
9309                 bnx2x_cl45_read(bp, phy,
9310                                 MDIO_PMA_DEVAD,
9311                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9312
9313
9314                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9315                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9316                         bnx2x_sfp_set_transmitter(params, phy, 0);
9317
9318                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9319                         bnx2x_sfp_module_detection(phy, params);
9320                 else
9321                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9322
9323                 /* Reconfigure link speed based on module type limitations */
9324                 bnx2x_8727_config_speed(phy, params);
9325         }
9326
9327         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9328                    rx_alarm_status);
9329         /* No need to check link status in case of module plugged in/out */
9330 }
9331
9332 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9333                                  struct link_params *params,
9334                                  struct link_vars *vars)
9335
9336 {
9337         struct bnx2x *bp = params->bp;
9338         u8 link_up = 0, oc_port = params->port;
9339         u16 link_status = 0;
9340         u16 rx_alarm_status, lasi_ctrl, val1;
9341
9342         /* If PHY is not initialized, do not check link status */
9343         bnx2x_cl45_read(bp, phy,
9344                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9345                         &lasi_ctrl);
9346         if (!lasi_ctrl)
9347                 return 0;
9348
9349         /* Check the LASI on Rx */
9350         bnx2x_cl45_read(bp, phy,
9351                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9352                         &rx_alarm_status);
9353         vars->line_speed = 0;
9354         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9355
9356         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9357                              MDIO_PMA_LASI_TXCTRL);
9358
9359         bnx2x_cl45_read(bp, phy,
9360                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9361
9362         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9363
9364         /* Clear MSG-OUT */
9365         bnx2x_cl45_read(bp, phy,
9366                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9367
9368         /* If a module is present and there is need to check
9369          * for over current
9370          */
9371         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9372                 /* Check over-current using 8727 GPIO0 input*/
9373                 bnx2x_cl45_read(bp, phy,
9374                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9375                                 &val1);
9376
9377                 if ((val1 & (1<<8)) == 0) {
9378                         if (!CHIP_IS_E1x(bp))
9379                                 oc_port = BP_PATH(bp) + (params->port << 1);
9380                         DP(NETIF_MSG_LINK,
9381                            "8727 Power fault has been detected on port %d\n",
9382                            oc_port);
9383                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9384                                             "been detected and the power to "
9385                                             "that SFP+ module has been removed "
9386                                             "to prevent failure of the card. "
9387                                             "Please remove the SFP+ module and "
9388                                             "restart the system to clear this "
9389                                             "error.\n",
9390                          oc_port);
9391                         /* Disable all RX_ALARMs except for mod_abs */
9392                         bnx2x_cl45_write(bp, phy,
9393                                          MDIO_PMA_DEVAD,
9394                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9395
9396                         bnx2x_cl45_read(bp, phy,
9397                                         MDIO_PMA_DEVAD,
9398                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9399                         /* Wait for module_absent_event */
9400                         val1 |= (1<<8);
9401                         bnx2x_cl45_write(bp, phy,
9402                                          MDIO_PMA_DEVAD,
9403                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9404                         /* Clear RX alarm */
9405                         bnx2x_cl45_read(bp, phy,
9406                                 MDIO_PMA_DEVAD,
9407                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9408                         bnx2x_8727_power_module(params->bp, phy, 0);
9409                         return 0;
9410                 }
9411         } /* Over current check */
9412
9413         /* When module absent bit is set, check module */
9414         if (rx_alarm_status & (1<<5)) {
9415                 bnx2x_8727_handle_mod_abs(phy, params);
9416                 /* Enable all mod_abs and link detection bits */
9417                 bnx2x_cl45_write(bp, phy,
9418                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9419                                  ((1<<5) | (1<<2)));
9420         }
9421
9422         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9423                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9424                 bnx2x_sfp_set_transmitter(params, phy, 1);
9425         } else {
9426                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9427                 return 0;
9428         }
9429
9430         bnx2x_cl45_read(bp, phy,
9431                         MDIO_PMA_DEVAD,
9432                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9433
9434         /* Bits 0..2 --> speed detected,
9435          * Bits 13..15--> link is down
9436          */
9437         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9438                 link_up = 1;
9439                 vars->line_speed = SPEED_10000;
9440                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9441                            params->port);
9442         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9443                 link_up = 1;
9444                 vars->line_speed = SPEED_1000;
9445                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9446                            params->port);
9447         } else {
9448                 link_up = 0;
9449                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9450                            params->port);
9451         }
9452
9453         /* Capture 10G link fault. */
9454         if (vars->line_speed == SPEED_10000) {
9455                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9456                             MDIO_PMA_LASI_TXSTAT, &val1);
9457
9458                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9459                             MDIO_PMA_LASI_TXSTAT, &val1);
9460
9461                 if (val1 & (1<<0)) {
9462                         vars->fault_detected = 1;
9463                 }
9464         }
9465
9466         if (link_up) {
9467                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9468                 vars->duplex = DUPLEX_FULL;
9469                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9470         }
9471
9472         if ((DUAL_MEDIA(params)) &&
9473             (phy->req_line_speed == SPEED_1000)) {
9474                 bnx2x_cl45_read(bp, phy,
9475                                 MDIO_PMA_DEVAD,
9476                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9477                 /* In case of dual-media board and 1G, power up the XAUI side,
9478                  * otherwise power it down. For 10G it is done automatically
9479                  */
9480                 if (link_up)
9481                         val1 &= ~(3<<10);
9482                 else
9483                         val1 |= (3<<10);
9484                 bnx2x_cl45_write(bp, phy,
9485                                  MDIO_PMA_DEVAD,
9486                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9487         }
9488         return link_up;
9489 }
9490
9491 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9492                                   struct link_params *params)
9493 {
9494         struct bnx2x *bp = params->bp;
9495
9496         /* Enable/Disable PHY transmitter output */
9497         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9498
9499         /* Disable Transmitter */
9500         bnx2x_sfp_set_transmitter(params, phy, 0);
9501         /* Clear LASI */
9502         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9503
9504 }
9505
9506 /******************************************************************/
9507 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9508 /******************************************************************/
9509 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9510                                             struct bnx2x *bp,
9511                                             u8 port)
9512 {
9513         u16 val, fw_ver2, cnt, i;
9514         static struct bnx2x_reg_set reg_set[] = {
9515                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9516                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9517                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9518                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9519                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9520         };
9521         u16 fw_ver1;
9522
9523         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9524             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9525                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9526                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9527                                 phy->ver_addr);
9528         } else {
9529                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9530                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9531                 for (i = 0; i < ARRAY_SIZE(reg_set);
9532                       i++)
9533                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9534                                          reg_set[i].reg, reg_set[i].val);
9535
9536                 for (cnt = 0; cnt < 100; cnt++) {
9537                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9538                         if (val & 1)
9539                                 break;
9540                         udelay(5);
9541                 }
9542                 if (cnt == 100) {
9543                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9544                                         "phy fw version(1)\n");
9545                         bnx2x_save_spirom_version(bp, port, 0,
9546                                                   phy->ver_addr);
9547                         return;
9548                 }
9549
9550
9551                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9552                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9553                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9554                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9555                 for (cnt = 0; cnt < 100; cnt++) {
9556                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9557                         if (val & 1)
9558                                 break;
9559                         udelay(5);
9560                 }
9561                 if (cnt == 100) {
9562                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9563                                         "version(2)\n");
9564                         bnx2x_save_spirom_version(bp, port, 0,
9565                                                   phy->ver_addr);
9566                         return;
9567                 }
9568
9569                 /* lower 16 bits of the register SPI_FW_STATUS */
9570                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9571                 /* upper 16 bits of register SPI_FW_STATUS */
9572                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9573
9574                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9575                                           phy->ver_addr);
9576         }
9577
9578 }
9579 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9580                                 struct bnx2x_phy *phy)
9581 {
9582         u16 val, offset, i;
9583         static struct bnx2x_reg_set reg_set[] = {
9584                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9585                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9586                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9587                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9588                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9589                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9590                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9591         };
9592         /* PHYC_CTL_LED_CTL */
9593         bnx2x_cl45_read(bp, phy,
9594                         MDIO_PMA_DEVAD,
9595                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9596         val &= 0xFE00;
9597         val |= 0x0092;
9598
9599         bnx2x_cl45_write(bp, phy,
9600                          MDIO_PMA_DEVAD,
9601                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9602
9603         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9604                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9605                                  reg_set[i].val);
9606
9607         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9608             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9609                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9610         else
9611                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9612
9613         /* stretch_en for LED3*/
9614         bnx2x_cl45_read_or_write(bp, phy,
9615                                  MDIO_PMA_DEVAD, offset,
9616                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9617 }
9618
9619 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9620                                       struct link_params *params,
9621                                       u32 action)
9622 {
9623         struct bnx2x *bp = params->bp;
9624         switch (action) {
9625         case PHY_INIT:
9626                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9627                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9628                         /* Save spirom version */
9629                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9630                 }
9631                 /* This phy uses the NIG latch mechanism since link indication
9632                  * arrives through its LED4 and not via its LASI signal, so we
9633                  * get steady signal instead of clear on read
9634                  */
9635                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9636                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9637
9638                 bnx2x_848xx_set_led(bp, phy);
9639                 break;
9640         }
9641 }
9642
9643 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9644                                        struct link_params *params,
9645                                        struct link_vars *vars)
9646 {
9647         struct bnx2x *bp = params->bp;
9648         u16 autoneg_val, an_1000_val, an_10_100_val;
9649
9650         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9651         bnx2x_cl45_write(bp, phy,
9652                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9653
9654         /* set 1000 speed advertisement */
9655         bnx2x_cl45_read(bp, phy,
9656                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9657                         &an_1000_val);
9658
9659         bnx2x_ext_phy_set_pause(params, phy, vars);
9660         bnx2x_cl45_read(bp, phy,
9661                         MDIO_AN_DEVAD,
9662                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9663                         &an_10_100_val);
9664         bnx2x_cl45_read(bp, phy,
9665                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9666                         &autoneg_val);
9667         /* Disable forced speed */
9668         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9669         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9670
9671         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9672              (phy->speed_cap_mask &
9673              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9674             (phy->req_line_speed == SPEED_1000)) {
9675                 an_1000_val |= (1<<8);
9676                 autoneg_val |= (1<<9 | 1<<12);
9677                 if (phy->req_duplex == DUPLEX_FULL)
9678                         an_1000_val |= (1<<9);
9679                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9680         } else
9681                 an_1000_val &= ~((1<<8) | (1<<9));
9682
9683         bnx2x_cl45_write(bp, phy,
9684                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9685                          an_1000_val);
9686
9687         /* set 100 speed advertisement */
9688         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9689              (phy->speed_cap_mask &
9690               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9691                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9692                 an_10_100_val |= (1<<7);
9693                 /* Enable autoneg and restart autoneg for legacy speeds */
9694                 autoneg_val |= (1<<9 | 1<<12);
9695
9696                 if (phy->req_duplex == DUPLEX_FULL)
9697                         an_10_100_val |= (1<<8);
9698                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9699         }
9700         /* set 10 speed advertisement */
9701         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9702              (phy->speed_cap_mask &
9703               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9704                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9705              (phy->supported &
9706               (SUPPORTED_10baseT_Half |
9707                SUPPORTED_10baseT_Full)))) {
9708                 an_10_100_val |= (1<<5);
9709                 autoneg_val |= (1<<9 | 1<<12);
9710                 if (phy->req_duplex == DUPLEX_FULL)
9711                         an_10_100_val |= (1<<6);
9712                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9713         }
9714
9715         /* Only 10/100 are allowed to work in FORCE mode */
9716         if ((phy->req_line_speed == SPEED_100) &&
9717             (phy->supported &
9718              (SUPPORTED_100baseT_Half |
9719               SUPPORTED_100baseT_Full))) {
9720                 autoneg_val |= (1<<13);
9721                 /* Enabled AUTO-MDIX when autoneg is disabled */
9722                 bnx2x_cl45_write(bp, phy,
9723                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9724                                  (1<<15 | 1<<9 | 7<<0));
9725                 /* The PHY needs this set even for forced link. */
9726                 an_10_100_val |= (1<<8) | (1<<7);
9727                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9728         }
9729         if ((phy->req_line_speed == SPEED_10) &&
9730             (phy->supported &
9731              (SUPPORTED_10baseT_Half |
9732               SUPPORTED_10baseT_Full))) {
9733                 /* Enabled AUTO-MDIX when autoneg is disabled */
9734                 bnx2x_cl45_write(bp, phy,
9735                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9736                                  (1<<15 | 1<<9 | 7<<0));
9737                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9738         }
9739
9740         bnx2x_cl45_write(bp, phy,
9741                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9742                          an_10_100_val);
9743
9744         if (phy->req_duplex == DUPLEX_FULL)
9745                 autoneg_val |= (1<<8);
9746
9747         /* Always write this if this is not 84833/4.
9748          * For 84833/4, write it only when it's a forced speed.
9749          */
9750         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9751              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9752             ((autoneg_val & (1<<12)) == 0))
9753                 bnx2x_cl45_write(bp, phy,
9754                          MDIO_AN_DEVAD,
9755                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9756
9757         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9758             (phy->speed_cap_mask &
9759              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9760                 (phy->req_line_speed == SPEED_10000)) {
9761                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9762                         /* Restart autoneg for 10G*/
9763
9764                         bnx2x_cl45_read_or_write(
9765                                 bp, phy,
9766                                 MDIO_AN_DEVAD,
9767                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9768                                 0x1000);
9769                         bnx2x_cl45_write(bp, phy,
9770                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9771                                          0x3200);
9772         } else
9773                 bnx2x_cl45_write(bp, phy,
9774                                  MDIO_AN_DEVAD,
9775                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9776                                  1);
9777
9778         return 0;
9779 }
9780
9781 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9782                                   struct link_params *params,
9783                                   struct link_vars *vars)
9784 {
9785         struct bnx2x *bp = params->bp;
9786         /* Restore normal power mode*/
9787         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9788                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9789
9790         /* HW reset */
9791         bnx2x_ext_phy_hw_reset(bp, params->port);
9792         bnx2x_wait_reset_complete(bp, phy, params);
9793
9794         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9795         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9796 }
9797
9798 #define PHY84833_CMDHDLR_WAIT 300
9799 #define PHY84833_CMDHDLR_MAX_ARGS 5
9800 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9801                                 struct link_params *params, u16 fw_cmd,
9802                                 u16 cmd_args[], int argc)
9803 {
9804         int idx;
9805         u16 val;
9806         struct bnx2x *bp = params->bp;
9807         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9808         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9809                         MDIO_84833_CMD_HDLR_STATUS,
9810                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9811         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9812                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9813                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9814                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9815                         break;
9816                 usleep_range(1000, 2000);
9817         }
9818         if (idx >= PHY84833_CMDHDLR_WAIT) {
9819                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9820                 return -EINVAL;
9821         }
9822
9823         /* Prepare argument(s) and issue command */
9824         for (idx = 0; idx < argc; idx++) {
9825                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9826                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9827                                 cmd_args[idx]);
9828         }
9829         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9830                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9831         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9832                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9833                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9834                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9835                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9836                         break;
9837                 usleep_range(1000, 2000);
9838         }
9839         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9840                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9841                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9842                 return -EINVAL;
9843         }
9844         /* Gather returning data */
9845         for (idx = 0; idx < argc; idx++) {
9846                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9847                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9848                                 &cmd_args[idx]);
9849         }
9850         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9851                         MDIO_84833_CMD_HDLR_STATUS,
9852                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9853         return 0;
9854 }
9855
9856 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9857                                    struct link_params *params,
9858                                    struct link_vars *vars)
9859 {
9860         u32 pair_swap;
9861         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9862         int status;
9863         struct bnx2x *bp = params->bp;
9864
9865         /* Check for configuration. */
9866         pair_swap = REG_RD(bp, params->shmem_base +
9867                            offsetof(struct shmem_region,
9868                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9869                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9870
9871         if (pair_swap == 0)
9872                 return 0;
9873
9874         /* Only the second argument is used for this command */
9875         data[1] = (u16)pair_swap;
9876
9877         status = bnx2x_84833_cmd_hdlr(phy, params,
9878                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9879         if (status == 0)
9880                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9881
9882         return status;
9883 }
9884
9885 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9886                                       u32 shmem_base_path[],
9887                                       u32 chip_id)
9888 {
9889         u32 reset_pin[2];
9890         u32 idx;
9891         u8 reset_gpios;
9892         if (CHIP_IS_E3(bp)) {
9893                 /* Assume that these will be GPIOs, not EPIOs. */
9894                 for (idx = 0; idx < 2; idx++) {
9895                         /* Map config param to register bit. */
9896                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9897                                 offsetof(struct shmem_region,
9898                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9899                         reset_pin[idx] = (reset_pin[idx] &
9900                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9901                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9902                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9903                         reset_pin[idx] = (1 << reset_pin[idx]);
9904                 }
9905                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9906         } else {
9907                 /* E2, look from diff place of shmem. */
9908                 for (idx = 0; idx < 2; idx++) {
9909                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9910                                 offsetof(struct shmem_region,
9911                                 dev_info.port_hw_config[0].default_cfg));
9912                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9913                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9914                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9915                         reset_pin[idx] = (1 << reset_pin[idx]);
9916                 }
9917                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9918         }
9919
9920         return reset_gpios;
9921 }
9922
9923 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9924                                 struct link_params *params)
9925 {
9926         struct bnx2x *bp = params->bp;
9927         u8 reset_gpios;
9928         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9929                                 offsetof(struct shmem2_region,
9930                                 other_shmem_base_addr));
9931
9932         u32 shmem_base_path[2];
9933
9934         /* Work around for 84833 LED failure inside RESET status */
9935         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9936                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9937                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9938         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9939                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9940                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9941
9942         shmem_base_path[0] = params->shmem_base;
9943         shmem_base_path[1] = other_shmem_base_addr;
9944
9945         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9946                                                   params->chip_id);
9947
9948         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9949         udelay(10);
9950         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9951                 reset_gpios);
9952
9953         return 0;
9954 }
9955
9956 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9957                                    struct link_params *params,
9958                                    struct link_vars *vars)
9959 {
9960         int rc;
9961         struct bnx2x *bp = params->bp;
9962         u16 cmd_args = 0;
9963
9964         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
9965
9966         /* Prevent Phy from working in EEE and advertising it */
9967         rc = bnx2x_84833_cmd_hdlr(phy, params,
9968                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9969         if (rc) {
9970                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
9971                 return rc;
9972         }
9973
9974         return bnx2x_eee_disable(phy, params, vars);
9975 }
9976
9977 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
9978                                    struct link_params *params,
9979                                    struct link_vars *vars)
9980 {
9981         int rc;
9982         struct bnx2x *bp = params->bp;
9983         u16 cmd_args = 1;
9984
9985         rc = bnx2x_84833_cmd_hdlr(phy, params,
9986                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9987         if (rc) {
9988                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
9989                 return rc;
9990         }
9991
9992         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
9993 }
9994
9995 #define PHY84833_CONSTANT_LATENCY 1193
9996 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9997                                    struct link_params *params,
9998                                    struct link_vars *vars)
9999 {
10000         struct bnx2x *bp = params->bp;
10001         u8 port, initialize = 1;
10002         u16 val;
10003         u32 actual_phy_selection;
10004         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10005         int rc = 0;
10006
10007         usleep_range(1000, 2000);
10008
10009         if (!(CHIP_IS_E1x(bp)))
10010                 port = BP_PATH(bp);
10011         else
10012                 port = params->port;
10013
10014         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10015                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10016                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10017                                port);
10018         } else {
10019                 /* MDIO reset */
10020                 bnx2x_cl45_write(bp, phy,
10021                                 MDIO_PMA_DEVAD,
10022                                 MDIO_PMA_REG_CTRL, 0x8000);
10023         }
10024
10025         bnx2x_wait_reset_complete(bp, phy, params);
10026
10027         /* Wait for GPHY to come out of reset */
10028         msleep(50);
10029         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10030             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10031                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10032                  * behavior.
10033                  */
10034                 u16 temp;
10035                 temp = vars->line_speed;
10036                 vars->line_speed = SPEED_10000;
10037                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10038                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10039                 vars->line_speed = temp;
10040         }
10041
10042         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10043                         MDIO_CTL_REG_84823_MEDIA, &val);
10044         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10045                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10046                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10047                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10048                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10049
10050         if (CHIP_IS_E3(bp)) {
10051                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10052                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10053         } else {
10054                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10055                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10056         }
10057
10058         actual_phy_selection = bnx2x_phy_selection(params);
10059
10060         switch (actual_phy_selection) {
10061         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10062                 /* Do nothing. Essentially this is like the priority copper */
10063                 break;
10064         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10065                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10066                 break;
10067         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10068                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10069                 break;
10070         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10071                 /* Do nothing here. The first PHY won't be initialized at all */
10072                 break;
10073         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10074                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10075                 initialize = 0;
10076                 break;
10077         }
10078         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10079                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10080
10081         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10082                          MDIO_CTL_REG_84823_MEDIA, val);
10083         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10084                    params->multi_phy_config, val);
10085
10086         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10087             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10088                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10089
10090                 /* Keep AutogrEEEn disabled. */
10091                 cmd_args[0] = 0x0;
10092                 cmd_args[1] = 0x0;
10093                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10094                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10095                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10096                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10097                         PHY84833_CMDHDLR_MAX_ARGS);
10098                 if (rc)
10099                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10100         }
10101         if (initialize)
10102                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10103         else
10104                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10105         /* 84833 PHY has a better feature and doesn't need to support this. */
10106         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10107                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10108                         offsetof(struct shmem_region,
10109                         dev_info.port_hw_config[params->port].default_cfg)) &
10110                         PORT_HW_CFG_ENABLE_CMS_MASK;
10111
10112                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10113                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10114                 if (cms_enable)
10115                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10116                 else
10117                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10118                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10119                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10120         }
10121
10122         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10123                         MDIO_84833_TOP_CFG_FW_REV, &val);
10124
10125         /* Configure EEE support */
10126         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10127             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10128             bnx2x_eee_has_cap(params)) {
10129                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10130                 if (rc) {
10131                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10132                         bnx2x_8483x_disable_eee(phy, params, vars);
10133                         return rc;
10134                 }
10135
10136                 if ((phy->req_duplex == DUPLEX_FULL) &&
10137                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10138                     (bnx2x_eee_calc_timer(params) ||
10139                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10140                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10141                 else
10142                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10143                 if (rc) {
10144                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10145                         return rc;
10146                 }
10147         } else {
10148                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10149         }
10150
10151         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10152             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10153                 /* Bring PHY out of super isolate mode as the final step. */
10154                 bnx2x_cl45_read_and_write(bp, phy,
10155                                           MDIO_CTL_DEVAD,
10156                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10157                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10158         }
10159         return rc;
10160 }
10161
10162 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10163                                   struct link_params *params,
10164                                   struct link_vars *vars)
10165 {
10166         struct bnx2x *bp = params->bp;
10167         u16 val, val1, val2;
10168         u8 link_up = 0;
10169
10170
10171         /* Check 10G-BaseT link status */
10172         /* Check PMD signal ok */
10173         bnx2x_cl45_read(bp, phy,
10174                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10175         bnx2x_cl45_read(bp, phy,
10176                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10177                         &val2);
10178         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10179
10180         /* Check link 10G */
10181         if (val2 & (1<<11)) {
10182                 vars->line_speed = SPEED_10000;
10183                 vars->duplex = DUPLEX_FULL;
10184                 link_up = 1;
10185                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10186         } else { /* Check Legacy speed link */
10187                 u16 legacy_status, legacy_speed;
10188
10189                 /* Enable expansion register 0x42 (Operation mode status) */
10190                 bnx2x_cl45_write(bp, phy,
10191                                  MDIO_AN_DEVAD,
10192                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10193
10194                 /* Get legacy speed operation status */
10195                 bnx2x_cl45_read(bp, phy,
10196                                 MDIO_AN_DEVAD,
10197                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10198                                 &legacy_status);
10199
10200                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10201                    legacy_status);
10202                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10203                 legacy_speed = (legacy_status & (3<<9));
10204                 if (legacy_speed == (0<<9))
10205                         vars->line_speed = SPEED_10;
10206                 else if (legacy_speed == (1<<9))
10207                         vars->line_speed = SPEED_100;
10208                 else if (legacy_speed == (2<<9))
10209                         vars->line_speed = SPEED_1000;
10210                 else { /* Should not happen: Treat as link down */
10211                         vars->line_speed = 0;
10212                         link_up = 0;
10213                 }
10214
10215                 if (link_up) {
10216                         if (legacy_status & (1<<8))
10217                                 vars->duplex = DUPLEX_FULL;
10218                         else
10219                                 vars->duplex = DUPLEX_HALF;
10220
10221                         DP(NETIF_MSG_LINK,
10222                            "Link is up in %dMbps, is_duplex_full= %d\n",
10223                            vars->line_speed,
10224                            (vars->duplex == DUPLEX_FULL));
10225                         /* Check legacy speed AN resolution */
10226                         bnx2x_cl45_read(bp, phy,
10227                                         MDIO_AN_DEVAD,
10228                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10229                                         &val);
10230                         if (val & (1<<5))
10231                                 vars->link_status |=
10232                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10233                         bnx2x_cl45_read(bp, phy,
10234                                         MDIO_AN_DEVAD,
10235                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10236                                         &val);
10237                         if ((val & (1<<0)) == 0)
10238                                 vars->link_status |=
10239                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10240                 }
10241         }
10242         if (link_up) {
10243                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10244                            vars->line_speed);
10245                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10246
10247                 /* Read LP advertised speeds */
10248                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10249                                 MDIO_AN_REG_CL37_FC_LP, &val);
10250                 if (val & (1<<5))
10251                         vars->link_status |=
10252                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10253                 if (val & (1<<6))
10254                         vars->link_status |=
10255                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10256                 if (val & (1<<7))
10257                         vars->link_status |=
10258                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10259                 if (val & (1<<8))
10260                         vars->link_status |=
10261                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10262                 if (val & (1<<9))
10263                         vars->link_status |=
10264                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10265
10266                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10267                                 MDIO_AN_REG_1000T_STATUS, &val);
10268
10269                 if (val & (1<<10))
10270                         vars->link_status |=
10271                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10272                 if (val & (1<<11))
10273                         vars->link_status |=
10274                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10275
10276                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10277                                 MDIO_AN_REG_MASTER_STATUS, &val);
10278
10279                 if (val & (1<<11))
10280                         vars->link_status |=
10281                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10282
10283                 /* Determine if EEE was negotiated */
10284                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10285                         bnx2x_eee_an_resolve(phy, params, vars);
10286         }
10287
10288         return link_up;
10289 }
10290
10291 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10292 {
10293         int status = 0;
10294         u32 spirom_ver;
10295         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10296         status = bnx2x_format_ver(spirom_ver, str, len);
10297         return status;
10298 }
10299
10300 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10301                                 struct link_params *params)
10302 {
10303         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10304                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10305         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10306                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10307 }
10308
10309 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10310                                         struct link_params *params)
10311 {
10312         bnx2x_cl45_write(params->bp, phy,
10313                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10314         bnx2x_cl45_write(params->bp, phy,
10315                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10316 }
10317
10318 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10319                                    struct link_params *params)
10320 {
10321         struct bnx2x *bp = params->bp;
10322         u8 port;
10323         u16 val16;
10324
10325         if (!(CHIP_IS_E1x(bp)))
10326                 port = BP_PATH(bp);
10327         else
10328                 port = params->port;
10329
10330         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10331                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10332                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10333                                port);
10334         } else {
10335                 bnx2x_cl45_read(bp, phy,
10336                                 MDIO_CTL_DEVAD,
10337                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10338                 val16 |= MDIO_84833_SUPER_ISOLATE;
10339                 bnx2x_cl45_write(bp, phy,
10340                                  MDIO_CTL_DEVAD,
10341                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10342         }
10343 }
10344
10345 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10346                                      struct link_params *params, u8 mode)
10347 {
10348         struct bnx2x *bp = params->bp;
10349         u16 val;
10350         u8 port;
10351
10352         if (!(CHIP_IS_E1x(bp)))
10353                 port = BP_PATH(bp);
10354         else
10355                 port = params->port;
10356
10357         switch (mode) {
10358         case LED_MODE_OFF:
10359
10360                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10361
10362                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10363                     SHARED_HW_CFG_LED_EXTPHY1) {
10364
10365                         /* Set LED masks */
10366                         bnx2x_cl45_write(bp, phy,
10367                                         MDIO_PMA_DEVAD,
10368                                         MDIO_PMA_REG_8481_LED1_MASK,
10369                                         0x0);
10370
10371                         bnx2x_cl45_write(bp, phy,
10372                                         MDIO_PMA_DEVAD,
10373                                         MDIO_PMA_REG_8481_LED2_MASK,
10374                                         0x0);
10375
10376                         bnx2x_cl45_write(bp, phy,
10377                                         MDIO_PMA_DEVAD,
10378                                         MDIO_PMA_REG_8481_LED3_MASK,
10379                                         0x0);
10380
10381                         bnx2x_cl45_write(bp, phy,
10382                                         MDIO_PMA_DEVAD,
10383                                         MDIO_PMA_REG_8481_LED5_MASK,
10384                                         0x0);
10385
10386                 } else {
10387                         bnx2x_cl45_write(bp, phy,
10388                                          MDIO_PMA_DEVAD,
10389                                          MDIO_PMA_REG_8481_LED1_MASK,
10390                                          0x0);
10391                 }
10392                 break;
10393         case LED_MODE_FRONT_PANEL_OFF:
10394
10395                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10396                    port);
10397
10398                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10399                     SHARED_HW_CFG_LED_EXTPHY1) {
10400
10401                         /* Set LED masks */
10402                         bnx2x_cl45_write(bp, phy,
10403                                          MDIO_PMA_DEVAD,
10404                                          MDIO_PMA_REG_8481_LED1_MASK,
10405                                          0x0);
10406
10407                         bnx2x_cl45_write(bp, phy,
10408                                          MDIO_PMA_DEVAD,
10409                                          MDIO_PMA_REG_8481_LED2_MASK,
10410                                          0x0);
10411
10412                         bnx2x_cl45_write(bp, phy,
10413                                          MDIO_PMA_DEVAD,
10414                                          MDIO_PMA_REG_8481_LED3_MASK,
10415                                          0x0);
10416
10417                         bnx2x_cl45_write(bp, phy,
10418                                          MDIO_PMA_DEVAD,
10419                                          MDIO_PMA_REG_8481_LED5_MASK,
10420                                          0x20);
10421
10422                 } else {
10423                         bnx2x_cl45_write(bp, phy,
10424                                          MDIO_PMA_DEVAD,
10425                                          MDIO_PMA_REG_8481_LED1_MASK,
10426                                          0x0);
10427                         if (phy->type ==
10428                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10429                                 /* Disable MI_INT interrupt before setting LED4
10430                                  * source to constant off.
10431                                  */
10432                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10433                                            params->port*4) &
10434                                     NIG_MASK_MI_INT) {
10435                                         params->link_flags |=
10436                                         LINK_FLAGS_INT_DISABLED;
10437
10438                                         bnx2x_bits_dis(
10439                                                 bp,
10440                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10441                                                 params->port*4,
10442                                                 NIG_MASK_MI_INT);
10443                                 }
10444                                 bnx2x_cl45_write(bp, phy,
10445                                                  MDIO_PMA_DEVAD,
10446                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10447                                                  0x0);
10448                         }
10449                 }
10450                 break;
10451         case LED_MODE_ON:
10452
10453                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10454
10455                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10456                     SHARED_HW_CFG_LED_EXTPHY1) {
10457                         /* Set control reg */
10458                         bnx2x_cl45_read(bp, phy,
10459                                         MDIO_PMA_DEVAD,
10460                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10461                                         &val);
10462                         val &= 0x8000;
10463                         val |= 0x2492;
10464
10465                         bnx2x_cl45_write(bp, phy,
10466                                          MDIO_PMA_DEVAD,
10467                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10468                                          val);
10469
10470                         /* Set LED masks */
10471                         bnx2x_cl45_write(bp, phy,
10472                                          MDIO_PMA_DEVAD,
10473                                          MDIO_PMA_REG_8481_LED1_MASK,
10474                                          0x0);
10475
10476                         bnx2x_cl45_write(bp, phy,
10477                                          MDIO_PMA_DEVAD,
10478                                          MDIO_PMA_REG_8481_LED2_MASK,
10479                                          0x20);
10480
10481                         bnx2x_cl45_write(bp, phy,
10482                                          MDIO_PMA_DEVAD,
10483                                          MDIO_PMA_REG_8481_LED3_MASK,
10484                                          0x20);
10485
10486                         bnx2x_cl45_write(bp, phy,
10487                                          MDIO_PMA_DEVAD,
10488                                          MDIO_PMA_REG_8481_LED5_MASK,
10489                                          0x0);
10490                 } else {
10491                         bnx2x_cl45_write(bp, phy,
10492                                          MDIO_PMA_DEVAD,
10493                                          MDIO_PMA_REG_8481_LED1_MASK,
10494                                          0x20);
10495                         if (phy->type ==
10496                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10497                                 /* Disable MI_INT interrupt before setting LED4
10498                                  * source to constant on.
10499                                  */
10500                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10501                                            params->port*4) &
10502                                     NIG_MASK_MI_INT) {
10503                                         params->link_flags |=
10504                                         LINK_FLAGS_INT_DISABLED;
10505
10506                                         bnx2x_bits_dis(
10507                                                 bp,
10508                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10509                                                 params->port*4,
10510                                                 NIG_MASK_MI_INT);
10511                                 }
10512                                 bnx2x_cl45_write(bp, phy,
10513                                                  MDIO_PMA_DEVAD,
10514                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10515                                                  0x20);
10516                         }
10517                 }
10518                 break;
10519
10520         case LED_MODE_OPER:
10521
10522                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10523
10524                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10525                     SHARED_HW_CFG_LED_EXTPHY1) {
10526
10527                         /* Set control reg */
10528                         bnx2x_cl45_read(bp, phy,
10529                                         MDIO_PMA_DEVAD,
10530                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10531                                         &val);
10532
10533                         if (!((val &
10534                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10535                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10536                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10537                                 bnx2x_cl45_write(bp, phy,
10538                                                  MDIO_PMA_DEVAD,
10539                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10540                                                  0xa492);
10541                         }
10542
10543                         /* Set LED masks */
10544                         bnx2x_cl45_write(bp, phy,
10545                                          MDIO_PMA_DEVAD,
10546                                          MDIO_PMA_REG_8481_LED1_MASK,
10547                                          0x10);
10548
10549                         bnx2x_cl45_write(bp, phy,
10550                                          MDIO_PMA_DEVAD,
10551                                          MDIO_PMA_REG_8481_LED2_MASK,
10552                                          0x80);
10553
10554                         bnx2x_cl45_write(bp, phy,
10555                                          MDIO_PMA_DEVAD,
10556                                          MDIO_PMA_REG_8481_LED3_MASK,
10557                                          0x98);
10558
10559                         bnx2x_cl45_write(bp, phy,
10560                                          MDIO_PMA_DEVAD,
10561                                          MDIO_PMA_REG_8481_LED5_MASK,
10562                                          0x40);
10563
10564                 } else {
10565                         bnx2x_cl45_write(bp, phy,
10566                                          MDIO_PMA_DEVAD,
10567                                          MDIO_PMA_REG_8481_LED1_MASK,
10568                                          0x80);
10569
10570                         /* Tell LED3 to blink on source */
10571                         bnx2x_cl45_read(bp, phy,
10572                                         MDIO_PMA_DEVAD,
10573                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10574                                         &val);
10575                         val &= ~(7<<6);
10576                         val |= (1<<6); /* A83B[8:6]= 1 */
10577                         bnx2x_cl45_write(bp, phy,
10578                                          MDIO_PMA_DEVAD,
10579                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10580                                          val);
10581                         if (phy->type ==
10582                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10583                                 /* Restore LED4 source to external link,
10584                                  * and re-enable interrupts.
10585                                  */
10586                                 bnx2x_cl45_write(bp, phy,
10587                                                  MDIO_PMA_DEVAD,
10588                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10589                                                  0x40);
10590                                 if (params->link_flags &
10591                                     LINK_FLAGS_INT_DISABLED) {
10592                                         bnx2x_link_int_enable(params);
10593                                         params->link_flags &=
10594                                                 ~LINK_FLAGS_INT_DISABLED;
10595                                 }
10596                         }
10597                 }
10598                 break;
10599         }
10600
10601         /* This is a workaround for E3+84833 until autoneg
10602          * restart is fixed in f/w
10603          */
10604         if (CHIP_IS_E3(bp)) {
10605                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10606                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10607         }
10608 }
10609
10610 /******************************************************************/
10611 /*                      54618SE PHY SECTION                       */
10612 /******************************************************************/
10613 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10614                                         struct link_params *params,
10615                                         u32 action)
10616 {
10617         struct bnx2x *bp = params->bp;
10618         u16 temp;
10619         switch (action) {
10620         case PHY_INIT:
10621                 /* Configure LED4: set to INTR (0x6). */
10622                 /* Accessing shadow register 0xe. */
10623                 bnx2x_cl22_write(bp, phy,
10624                                  MDIO_REG_GPHY_SHADOW,
10625                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10626                 bnx2x_cl22_read(bp, phy,
10627                                 MDIO_REG_GPHY_SHADOW,
10628                                 &temp);
10629                 temp &= ~(0xf << 4);
10630                 temp |= (0x6 << 4);
10631                 bnx2x_cl22_write(bp, phy,
10632                                  MDIO_REG_GPHY_SHADOW,
10633                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10634                 /* Configure INTR based on link status change. */
10635                 bnx2x_cl22_write(bp, phy,
10636                                  MDIO_REG_INTR_MASK,
10637                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10638                 break;
10639         }
10640 }
10641
10642 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10643                                                struct link_params *params,
10644                                                struct link_vars *vars)
10645 {
10646         struct bnx2x *bp = params->bp;
10647         u8 port;
10648         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10649         u32 cfg_pin;
10650
10651         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10652         usleep_range(1000, 2000);
10653
10654         /* This works with E3 only, no need to check the chip
10655          * before determining the port.
10656          */
10657         port = params->port;
10658
10659         cfg_pin = (REG_RD(bp, params->shmem_base +
10660                         offsetof(struct shmem_region,
10661                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10662                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10663                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10664
10665         /* Drive pin high to bring the GPHY out of reset. */
10666         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10667
10668         /* wait for GPHY to reset */
10669         msleep(50);
10670
10671         /* reset phy */
10672         bnx2x_cl22_write(bp, phy,
10673                          MDIO_PMA_REG_CTRL, 0x8000);
10674         bnx2x_wait_reset_complete(bp, phy, params);
10675
10676         /* Wait for GPHY to reset */
10677         msleep(50);
10678
10679
10680         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10681         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10682         bnx2x_cl22_write(bp, phy,
10683                         MDIO_REG_GPHY_SHADOW,
10684                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10685         bnx2x_cl22_read(bp, phy,
10686                         MDIO_REG_GPHY_SHADOW,
10687                         &temp);
10688         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10689         bnx2x_cl22_write(bp, phy,
10690                         MDIO_REG_GPHY_SHADOW,
10691                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10692
10693         /* Set up fc */
10694         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10695         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10696         fc_val = 0;
10697         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10698                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10699                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10700
10701         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10702                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10703                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10704
10705         /* Read all advertisement */
10706         bnx2x_cl22_read(bp, phy,
10707                         0x09,
10708                         &an_1000_val);
10709
10710         bnx2x_cl22_read(bp, phy,
10711                         0x04,
10712                         &an_10_100_val);
10713
10714         bnx2x_cl22_read(bp, phy,
10715                         MDIO_PMA_REG_CTRL,
10716                         &autoneg_val);
10717
10718         /* Disable forced speed */
10719         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10720         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10721                            (1<<11));
10722
10723         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10724                         (phy->speed_cap_mask &
10725                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10726                         (phy->req_line_speed == SPEED_1000)) {
10727                 an_1000_val |= (1<<8);
10728                 autoneg_val |= (1<<9 | 1<<12);
10729                 if (phy->req_duplex == DUPLEX_FULL)
10730                         an_1000_val |= (1<<9);
10731                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10732         } else
10733                 an_1000_val &= ~((1<<8) | (1<<9));
10734
10735         bnx2x_cl22_write(bp, phy,
10736                         0x09,
10737                         an_1000_val);
10738         bnx2x_cl22_read(bp, phy,
10739                         0x09,
10740                         &an_1000_val);
10741
10742         /* Set 100 speed advertisement */
10743         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10744                         (phy->speed_cap_mask &
10745                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10746                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10747                 an_10_100_val |= (1<<7);
10748                 /* Enable autoneg and restart autoneg for legacy speeds */
10749                 autoneg_val |= (1<<9 | 1<<12);
10750
10751                 if (phy->req_duplex == DUPLEX_FULL)
10752                         an_10_100_val |= (1<<8);
10753                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10754         }
10755
10756         /* Set 10 speed advertisement */
10757         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10758                         (phy->speed_cap_mask &
10759                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10760                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10761                 an_10_100_val |= (1<<5);
10762                 autoneg_val |= (1<<9 | 1<<12);
10763                 if (phy->req_duplex == DUPLEX_FULL)
10764                         an_10_100_val |= (1<<6);
10765                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10766         }
10767
10768         /* Only 10/100 are allowed to work in FORCE mode */
10769         if (phy->req_line_speed == SPEED_100) {
10770                 autoneg_val |= (1<<13);
10771                 /* Enabled AUTO-MDIX when autoneg is disabled */
10772                 bnx2x_cl22_write(bp, phy,
10773                                 0x18,
10774                                 (1<<15 | 1<<9 | 7<<0));
10775                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10776         }
10777         if (phy->req_line_speed == SPEED_10) {
10778                 /* Enabled AUTO-MDIX when autoneg is disabled */
10779                 bnx2x_cl22_write(bp, phy,
10780                                 0x18,
10781                                 (1<<15 | 1<<9 | 7<<0));
10782                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10783         }
10784
10785         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10786                 int rc;
10787
10788                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10789                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10790                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10791                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10792                 temp &= 0xfffe;
10793                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10794
10795                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10796                 if (rc) {
10797                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10798                         bnx2x_eee_disable(phy, params, vars);
10799                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10800                            (phy->req_duplex == DUPLEX_FULL) &&
10801                            (bnx2x_eee_calc_timer(params) ||
10802                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10803                         /* Need to advertise EEE only when requested,
10804                          * and either no LPI assertion was requested,
10805                          * or it was requested and a valid timer was set.
10806                          * Also notice full duplex is required for EEE.
10807                          */
10808                         bnx2x_eee_advertise(phy, params, vars,
10809                                             SHMEM_EEE_1G_ADV);
10810                 } else {
10811                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10812                         bnx2x_eee_disable(phy, params, vars);
10813                 }
10814         } else {
10815                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10816                                     SHMEM_EEE_SUPPORTED_SHIFT;
10817
10818                 if (phy->flags & FLAGS_EEE) {
10819                         /* Handle legacy auto-grEEEn */
10820                         if (params->feature_config_flags &
10821                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10822                                 temp = 6;
10823                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10824                         } else {
10825                                 temp = 0;
10826                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10827                         }
10828                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10829                                          MDIO_AN_REG_EEE_ADV, temp);
10830                 }
10831         }
10832
10833         bnx2x_cl22_write(bp, phy,
10834                         0x04,
10835                         an_10_100_val | fc_val);
10836
10837         if (phy->req_duplex == DUPLEX_FULL)
10838                 autoneg_val |= (1<<8);
10839
10840         bnx2x_cl22_write(bp, phy,
10841                         MDIO_PMA_REG_CTRL, autoneg_val);
10842
10843         return 0;
10844 }
10845
10846
10847 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10848                                        struct link_params *params, u8 mode)
10849 {
10850         struct bnx2x *bp = params->bp;
10851         u16 temp;
10852
10853         bnx2x_cl22_write(bp, phy,
10854                 MDIO_REG_GPHY_SHADOW,
10855                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10856         bnx2x_cl22_read(bp, phy,
10857                 MDIO_REG_GPHY_SHADOW,
10858                 &temp);
10859         temp &= 0xff00;
10860
10861         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10862         switch (mode) {
10863         case LED_MODE_FRONT_PANEL_OFF:
10864         case LED_MODE_OFF:
10865                 temp |= 0x00ee;
10866                 break;
10867         case LED_MODE_OPER:
10868                 temp |= 0x0001;
10869                 break;
10870         case LED_MODE_ON:
10871                 temp |= 0x00ff;
10872                 break;
10873         default:
10874                 break;
10875         }
10876         bnx2x_cl22_write(bp, phy,
10877                 MDIO_REG_GPHY_SHADOW,
10878                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10879         return;
10880 }
10881
10882
10883 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10884                                      struct link_params *params)
10885 {
10886         struct bnx2x *bp = params->bp;
10887         u32 cfg_pin;
10888         u8 port;
10889
10890         /* In case of no EPIO routed to reset the GPHY, put it
10891          * in low power mode.
10892          */
10893         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10894         /* This works with E3 only, no need to check the chip
10895          * before determining the port.
10896          */
10897         port = params->port;
10898         cfg_pin = (REG_RD(bp, params->shmem_base +
10899                         offsetof(struct shmem_region,
10900                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10901                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10902                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10903
10904         /* Drive pin low to put GPHY in reset. */
10905         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10906 }
10907
10908 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10909                                     struct link_params *params,
10910                                     struct link_vars *vars)
10911 {
10912         struct bnx2x *bp = params->bp;
10913         u16 val;
10914         u8 link_up = 0;
10915         u16 legacy_status, legacy_speed;
10916
10917         /* Get speed operation status */
10918         bnx2x_cl22_read(bp, phy,
10919                         MDIO_REG_GPHY_AUX_STATUS,
10920                         &legacy_status);
10921         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10922
10923         /* Read status to clear the PHY interrupt. */
10924         bnx2x_cl22_read(bp, phy,
10925                         MDIO_REG_INTR_STATUS,
10926                         &val);
10927
10928         link_up = ((legacy_status & (1<<2)) == (1<<2));
10929
10930         if (link_up) {
10931                 legacy_speed = (legacy_status & (7<<8));
10932                 if (legacy_speed == (7<<8)) {
10933                         vars->line_speed = SPEED_1000;
10934                         vars->duplex = DUPLEX_FULL;
10935                 } else if (legacy_speed == (6<<8)) {
10936                         vars->line_speed = SPEED_1000;
10937                         vars->duplex = DUPLEX_HALF;
10938                 } else if (legacy_speed == (5<<8)) {
10939                         vars->line_speed = SPEED_100;
10940                         vars->duplex = DUPLEX_FULL;
10941                 }
10942                 /* Omitting 100Base-T4 for now */
10943                 else if (legacy_speed == (3<<8)) {
10944                         vars->line_speed = SPEED_100;
10945                         vars->duplex = DUPLEX_HALF;
10946                 } else if (legacy_speed == (2<<8)) {
10947                         vars->line_speed = SPEED_10;
10948                         vars->duplex = DUPLEX_FULL;
10949                 } else if (legacy_speed == (1<<8)) {
10950                         vars->line_speed = SPEED_10;
10951                         vars->duplex = DUPLEX_HALF;
10952                 } else /* Should not happen */
10953                         vars->line_speed = 0;
10954
10955                 DP(NETIF_MSG_LINK,
10956                    "Link is up in %dMbps, is_duplex_full= %d\n",
10957                    vars->line_speed,
10958                    (vars->duplex == DUPLEX_FULL));
10959
10960                 /* Check legacy speed AN resolution */
10961                 bnx2x_cl22_read(bp, phy,
10962                                 0x01,
10963                                 &val);
10964                 if (val & (1<<5))
10965                         vars->link_status |=
10966                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10967                 bnx2x_cl22_read(bp, phy,
10968                                 0x06,
10969                                 &val);
10970                 if ((val & (1<<0)) == 0)
10971                         vars->link_status |=
10972                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10973
10974                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10975                            vars->line_speed);
10976
10977                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10978
10979                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10980                         /* Report LP advertised speeds */
10981                         bnx2x_cl22_read(bp, phy, 0x5, &val);
10982
10983                         if (val & (1<<5))
10984                                 vars->link_status |=
10985                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10986                         if (val & (1<<6))
10987                                 vars->link_status |=
10988                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10989                         if (val & (1<<7))
10990                                 vars->link_status |=
10991                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10992                         if (val & (1<<8))
10993                                 vars->link_status |=
10994                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10995                         if (val & (1<<9))
10996                                 vars->link_status |=
10997                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10998
10999                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11000                         if (val & (1<<10))
11001                                 vars->link_status |=
11002                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11003                         if (val & (1<<11))
11004                                 vars->link_status |=
11005                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11006
11007                         if ((phy->flags & FLAGS_EEE) &&
11008                             bnx2x_eee_has_cap(params))
11009                                 bnx2x_eee_an_resolve(phy, params, vars);
11010                 }
11011         }
11012         return link_up;
11013 }
11014
11015 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11016                                           struct link_params *params)
11017 {
11018         struct bnx2x *bp = params->bp;
11019         u16 val;
11020         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11021
11022         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11023
11024         /* Enable master/slave manual mmode and set to master */
11025         /* mii write 9 [bits set 11 12] */
11026         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11027
11028         /* forced 1G and disable autoneg */
11029         /* set val [mii read 0] */
11030         /* set val [expr $val & [bits clear 6 12 13]] */
11031         /* set val [expr $val | [bits set 6 8]] */
11032         /* mii write 0 $val */
11033         bnx2x_cl22_read(bp, phy, 0x00, &val);
11034         val &= ~((1<<6) | (1<<12) | (1<<13));
11035         val |= (1<<6) | (1<<8);
11036         bnx2x_cl22_write(bp, phy, 0x00, val);
11037
11038         /* Set external loopback and Tx using 6dB coding */
11039         /* mii write 0x18 7 */
11040         /* set val [mii read 0x18] */
11041         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11042         bnx2x_cl22_write(bp, phy, 0x18, 7);
11043         bnx2x_cl22_read(bp, phy, 0x18, &val);
11044         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11045
11046         /* This register opens the gate for the UMAC despite its name */
11047         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11048
11049         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11050          * length used by the MAC receive logic to check frames.
11051          */
11052         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11053 }
11054
11055 /******************************************************************/
11056 /*                      SFX7101 PHY SECTION                       */
11057 /******************************************************************/
11058 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11059                                        struct link_params *params)
11060 {
11061         struct bnx2x *bp = params->bp;
11062         /* SFX7101_XGXS_TEST1 */
11063         bnx2x_cl45_write(bp, phy,
11064                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11065 }
11066
11067 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11068                                   struct link_params *params,
11069                                   struct link_vars *vars)
11070 {
11071         u16 fw_ver1, fw_ver2, val;
11072         struct bnx2x *bp = params->bp;
11073         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11074
11075         /* Restore normal power mode*/
11076         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11077                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11078         /* HW reset */
11079         bnx2x_ext_phy_hw_reset(bp, params->port);
11080         bnx2x_wait_reset_complete(bp, phy, params);
11081
11082         bnx2x_cl45_write(bp, phy,
11083                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11084         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11085         bnx2x_cl45_write(bp, phy,
11086                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11087
11088         bnx2x_ext_phy_set_pause(params, phy, vars);
11089         /* Restart autoneg */
11090         bnx2x_cl45_read(bp, phy,
11091                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11092         val |= 0x200;
11093         bnx2x_cl45_write(bp, phy,
11094                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11095
11096         /* Save spirom version */
11097         bnx2x_cl45_read(bp, phy,
11098                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11099
11100         bnx2x_cl45_read(bp, phy,
11101                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11102         bnx2x_save_spirom_version(bp, params->port,
11103                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11104         return 0;
11105 }
11106
11107 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11108                                  struct link_params *params,
11109                                  struct link_vars *vars)
11110 {
11111         struct bnx2x *bp = params->bp;
11112         u8 link_up;
11113         u16 val1, val2;
11114         bnx2x_cl45_read(bp, phy,
11115                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11116         bnx2x_cl45_read(bp, phy,
11117                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11118         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11119                    val2, val1);
11120         bnx2x_cl45_read(bp, phy,
11121                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11122         bnx2x_cl45_read(bp, phy,
11123                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11124         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11125                    val2, val1);
11126         link_up = ((val1 & 4) == 4);
11127         /* If link is up print the AN outcome of the SFX7101 PHY */
11128         if (link_up) {
11129                 bnx2x_cl45_read(bp, phy,
11130                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11131                                 &val2);
11132                 vars->line_speed = SPEED_10000;
11133                 vars->duplex = DUPLEX_FULL;
11134                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11135                            val2, (val2 & (1<<14)));
11136                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11137                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11138
11139                 /* Read LP advertised speeds */
11140                 if (val2 & (1<<11))
11141                         vars->link_status |=
11142                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11143         }
11144         return link_up;
11145 }
11146
11147 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11148 {
11149         if (*len < 5)
11150                 return -EINVAL;
11151         str[0] = (spirom_ver & 0xFF);
11152         str[1] = (spirom_ver & 0xFF00) >> 8;
11153         str[2] = (spirom_ver & 0xFF0000) >> 16;
11154         str[3] = (spirom_ver & 0xFF000000) >> 24;
11155         str[4] = '\0';
11156         *len -= 5;
11157         return 0;
11158 }
11159
11160 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11161 {
11162         u16 val, cnt;
11163
11164         bnx2x_cl45_read(bp, phy,
11165                         MDIO_PMA_DEVAD,
11166                         MDIO_PMA_REG_7101_RESET, &val);
11167
11168         for (cnt = 0; cnt < 10; cnt++) {
11169                 msleep(50);
11170                 /* Writes a self-clearing reset */
11171                 bnx2x_cl45_write(bp, phy,
11172                                  MDIO_PMA_DEVAD,
11173                                  MDIO_PMA_REG_7101_RESET,
11174                                  (val | (1<<15)));
11175                 /* Wait for clear */
11176                 bnx2x_cl45_read(bp, phy,
11177                                 MDIO_PMA_DEVAD,
11178                                 MDIO_PMA_REG_7101_RESET, &val);
11179
11180                 if ((val & (1<<15)) == 0)
11181                         break;
11182         }
11183 }
11184
11185 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11186                                 struct link_params *params) {
11187         /* Low power mode is controlled by GPIO 2 */
11188         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11189                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11190         /* The PHY reset is controlled by GPIO 1 */
11191         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11192                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11193 }
11194
11195 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11196                                     struct link_params *params, u8 mode)
11197 {
11198         u16 val = 0;
11199         struct bnx2x *bp = params->bp;
11200         switch (mode) {
11201         case LED_MODE_FRONT_PANEL_OFF:
11202         case LED_MODE_OFF:
11203                 val = 2;
11204                 break;
11205         case LED_MODE_ON:
11206                 val = 1;
11207                 break;
11208         case LED_MODE_OPER:
11209                 val = 0;
11210                 break;
11211         }
11212         bnx2x_cl45_write(bp, phy,
11213                          MDIO_PMA_DEVAD,
11214                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11215                          val);
11216 }
11217
11218 /******************************************************************/
11219 /*                      STATIC PHY DECLARATION                    */
11220 /******************************************************************/
11221
11222 static const struct bnx2x_phy phy_null = {
11223         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11224         .addr           = 0,
11225         .def_md_devad   = 0,
11226         .flags          = FLAGS_INIT_XGXS_FIRST,
11227         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11228         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11229         .mdio_ctrl      = 0,
11230         .supported      = 0,
11231         .media_type     = ETH_PHY_NOT_PRESENT,
11232         .ver_addr       = 0,
11233         .req_flow_ctrl  = 0,
11234         .req_line_speed = 0,
11235         .speed_cap_mask = 0,
11236         .req_duplex     = 0,
11237         .rsrv           = 0,
11238         .config_init    = (config_init_t)NULL,
11239         .read_status    = (read_status_t)NULL,
11240         .link_reset     = (link_reset_t)NULL,
11241         .config_loopback = (config_loopback_t)NULL,
11242         .format_fw_ver  = (format_fw_ver_t)NULL,
11243         .hw_reset       = (hw_reset_t)NULL,
11244         .set_link_led   = (set_link_led_t)NULL,
11245         .phy_specific_func = (phy_specific_func_t)NULL
11246 };
11247
11248 static const struct bnx2x_phy phy_serdes = {
11249         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11250         .addr           = 0xff,
11251         .def_md_devad   = 0,
11252         .flags          = 0,
11253         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11254         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11255         .mdio_ctrl      = 0,
11256         .supported      = (SUPPORTED_10baseT_Half |
11257                            SUPPORTED_10baseT_Full |
11258                            SUPPORTED_100baseT_Half |
11259                            SUPPORTED_100baseT_Full |
11260                            SUPPORTED_1000baseT_Full |
11261                            SUPPORTED_2500baseX_Full |
11262                            SUPPORTED_TP |
11263                            SUPPORTED_Autoneg |
11264                            SUPPORTED_Pause |
11265                            SUPPORTED_Asym_Pause),
11266         .media_type     = ETH_PHY_BASE_T,
11267         .ver_addr       = 0,
11268         .req_flow_ctrl  = 0,
11269         .req_line_speed = 0,
11270         .speed_cap_mask = 0,
11271         .req_duplex     = 0,
11272         .rsrv           = 0,
11273         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11274         .read_status    = (read_status_t)bnx2x_link_settings_status,
11275         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11276         .config_loopback = (config_loopback_t)NULL,
11277         .format_fw_ver  = (format_fw_ver_t)NULL,
11278         .hw_reset       = (hw_reset_t)NULL,
11279         .set_link_led   = (set_link_led_t)NULL,
11280         .phy_specific_func = (phy_specific_func_t)NULL
11281 };
11282
11283 static const struct bnx2x_phy phy_xgxs = {
11284         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11285         .addr           = 0xff,
11286         .def_md_devad   = 0,
11287         .flags          = 0,
11288         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11289         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11290         .mdio_ctrl      = 0,
11291         .supported      = (SUPPORTED_10baseT_Half |
11292                            SUPPORTED_10baseT_Full |
11293                            SUPPORTED_100baseT_Half |
11294                            SUPPORTED_100baseT_Full |
11295                            SUPPORTED_1000baseT_Full |
11296                            SUPPORTED_2500baseX_Full |
11297                            SUPPORTED_10000baseT_Full |
11298                            SUPPORTED_FIBRE |
11299                            SUPPORTED_Autoneg |
11300                            SUPPORTED_Pause |
11301                            SUPPORTED_Asym_Pause),
11302         .media_type     = ETH_PHY_CX4,
11303         .ver_addr       = 0,
11304         .req_flow_ctrl  = 0,
11305         .req_line_speed = 0,
11306         .speed_cap_mask = 0,
11307         .req_duplex     = 0,
11308         .rsrv           = 0,
11309         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11310         .read_status    = (read_status_t)bnx2x_link_settings_status,
11311         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11312         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11313         .format_fw_ver  = (format_fw_ver_t)NULL,
11314         .hw_reset       = (hw_reset_t)NULL,
11315         .set_link_led   = (set_link_led_t)NULL,
11316         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11317 };
11318 static const struct bnx2x_phy phy_warpcore = {
11319         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11320         .addr           = 0xff,
11321         .def_md_devad   = 0,
11322         .flags          = FLAGS_TX_ERROR_CHECK,
11323         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11324         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11325         .mdio_ctrl      = 0,
11326         .supported      = (SUPPORTED_10baseT_Half |
11327                            SUPPORTED_10baseT_Full |
11328                            SUPPORTED_100baseT_Half |
11329                            SUPPORTED_100baseT_Full |
11330                            SUPPORTED_1000baseT_Full |
11331                            SUPPORTED_10000baseT_Full |
11332                            SUPPORTED_20000baseKR2_Full |
11333                            SUPPORTED_20000baseMLD2_Full |
11334                            SUPPORTED_FIBRE |
11335                            SUPPORTED_Autoneg |
11336                            SUPPORTED_Pause |
11337                            SUPPORTED_Asym_Pause),
11338         .media_type     = ETH_PHY_UNSPECIFIED,
11339         .ver_addr       = 0,
11340         .req_flow_ctrl  = 0,
11341         .req_line_speed = 0,
11342         .speed_cap_mask = 0,
11343         /* req_duplex = */0,
11344         /* rsrv = */0,
11345         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11346         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11347         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11348         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11349         .format_fw_ver  = (format_fw_ver_t)NULL,
11350         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11351         .set_link_led   = (set_link_led_t)NULL,
11352         .phy_specific_func = (phy_specific_func_t)NULL
11353 };
11354
11355
11356 static const struct bnx2x_phy phy_7101 = {
11357         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11358         .addr           = 0xff,
11359         .def_md_devad   = 0,
11360         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11361         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11362         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11363         .mdio_ctrl      = 0,
11364         .supported      = (SUPPORTED_10000baseT_Full |
11365                            SUPPORTED_TP |
11366                            SUPPORTED_Autoneg |
11367                            SUPPORTED_Pause |
11368                            SUPPORTED_Asym_Pause),
11369         .media_type     = ETH_PHY_BASE_T,
11370         .ver_addr       = 0,
11371         .req_flow_ctrl  = 0,
11372         .req_line_speed = 0,
11373         .speed_cap_mask = 0,
11374         .req_duplex     = 0,
11375         .rsrv           = 0,
11376         .config_init    = (config_init_t)bnx2x_7101_config_init,
11377         .read_status    = (read_status_t)bnx2x_7101_read_status,
11378         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11379         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11380         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11381         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11382         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11383         .phy_specific_func = (phy_specific_func_t)NULL
11384 };
11385 static const struct bnx2x_phy phy_8073 = {
11386         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11387         .addr           = 0xff,
11388         .def_md_devad   = 0,
11389         .flags          = 0,
11390         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11391         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11392         .mdio_ctrl      = 0,
11393         .supported      = (SUPPORTED_10000baseT_Full |
11394                            SUPPORTED_2500baseX_Full |
11395                            SUPPORTED_1000baseT_Full |
11396                            SUPPORTED_FIBRE |
11397                            SUPPORTED_Autoneg |
11398                            SUPPORTED_Pause |
11399                            SUPPORTED_Asym_Pause),
11400         .media_type     = ETH_PHY_KR,
11401         .ver_addr       = 0,
11402         .req_flow_ctrl  = 0,
11403         .req_line_speed = 0,
11404         .speed_cap_mask = 0,
11405         .req_duplex     = 0,
11406         .rsrv           = 0,
11407         .config_init    = (config_init_t)bnx2x_8073_config_init,
11408         .read_status    = (read_status_t)bnx2x_8073_read_status,
11409         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11410         .config_loopback = (config_loopback_t)NULL,
11411         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11412         .hw_reset       = (hw_reset_t)NULL,
11413         .set_link_led   = (set_link_led_t)NULL,
11414         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11415 };
11416 static const struct bnx2x_phy phy_8705 = {
11417         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11418         .addr           = 0xff,
11419         .def_md_devad   = 0,
11420         .flags          = FLAGS_INIT_XGXS_FIRST,
11421         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11422         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11423         .mdio_ctrl      = 0,
11424         .supported      = (SUPPORTED_10000baseT_Full |
11425                            SUPPORTED_FIBRE |
11426                            SUPPORTED_Pause |
11427                            SUPPORTED_Asym_Pause),
11428         .media_type     = ETH_PHY_XFP_FIBER,
11429         .ver_addr       = 0,
11430         .req_flow_ctrl  = 0,
11431         .req_line_speed = 0,
11432         .speed_cap_mask = 0,
11433         .req_duplex     = 0,
11434         .rsrv           = 0,
11435         .config_init    = (config_init_t)bnx2x_8705_config_init,
11436         .read_status    = (read_status_t)bnx2x_8705_read_status,
11437         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11438         .config_loopback = (config_loopback_t)NULL,
11439         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11440         .hw_reset       = (hw_reset_t)NULL,
11441         .set_link_led   = (set_link_led_t)NULL,
11442         .phy_specific_func = (phy_specific_func_t)NULL
11443 };
11444 static const struct bnx2x_phy phy_8706 = {
11445         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11446         .addr           = 0xff,
11447         .def_md_devad   = 0,
11448         .flags          = FLAGS_INIT_XGXS_FIRST,
11449         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11450         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11451         .mdio_ctrl      = 0,
11452         .supported      = (SUPPORTED_10000baseT_Full |
11453                            SUPPORTED_1000baseT_Full |
11454                            SUPPORTED_FIBRE |
11455                            SUPPORTED_Pause |
11456                            SUPPORTED_Asym_Pause),
11457         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11458         .ver_addr       = 0,
11459         .req_flow_ctrl  = 0,
11460         .req_line_speed = 0,
11461         .speed_cap_mask = 0,
11462         .req_duplex     = 0,
11463         .rsrv           = 0,
11464         .config_init    = (config_init_t)bnx2x_8706_config_init,
11465         .read_status    = (read_status_t)bnx2x_8706_read_status,
11466         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11467         .config_loopback = (config_loopback_t)NULL,
11468         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11469         .hw_reset       = (hw_reset_t)NULL,
11470         .set_link_led   = (set_link_led_t)NULL,
11471         .phy_specific_func = (phy_specific_func_t)NULL
11472 };
11473
11474 static const struct bnx2x_phy phy_8726 = {
11475         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11476         .addr           = 0xff,
11477         .def_md_devad   = 0,
11478         .flags          = (FLAGS_INIT_XGXS_FIRST |
11479                            FLAGS_TX_ERROR_CHECK),
11480         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11481         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11482         .mdio_ctrl      = 0,
11483         .supported      = (SUPPORTED_10000baseT_Full |
11484                            SUPPORTED_1000baseT_Full |
11485                            SUPPORTED_Autoneg |
11486                            SUPPORTED_FIBRE |
11487                            SUPPORTED_Pause |
11488                            SUPPORTED_Asym_Pause),
11489         .media_type     = ETH_PHY_NOT_PRESENT,
11490         .ver_addr       = 0,
11491         .req_flow_ctrl  = 0,
11492         .req_line_speed = 0,
11493         .speed_cap_mask = 0,
11494         .req_duplex     = 0,
11495         .rsrv           = 0,
11496         .config_init    = (config_init_t)bnx2x_8726_config_init,
11497         .read_status    = (read_status_t)bnx2x_8726_read_status,
11498         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11499         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11500         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11501         .hw_reset       = (hw_reset_t)NULL,
11502         .set_link_led   = (set_link_led_t)NULL,
11503         .phy_specific_func = (phy_specific_func_t)NULL
11504 };
11505
11506 static const struct bnx2x_phy phy_8727 = {
11507         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11508         .addr           = 0xff,
11509         .def_md_devad   = 0,
11510         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11511                            FLAGS_TX_ERROR_CHECK),
11512         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11513         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11514         .mdio_ctrl      = 0,
11515         .supported      = (SUPPORTED_10000baseT_Full |
11516                            SUPPORTED_1000baseT_Full |
11517                            SUPPORTED_FIBRE |
11518                            SUPPORTED_Pause |
11519                            SUPPORTED_Asym_Pause),
11520         .media_type     = ETH_PHY_NOT_PRESENT,
11521         .ver_addr       = 0,
11522         .req_flow_ctrl  = 0,
11523         .req_line_speed = 0,
11524         .speed_cap_mask = 0,
11525         .req_duplex     = 0,
11526         .rsrv           = 0,
11527         .config_init    = (config_init_t)bnx2x_8727_config_init,
11528         .read_status    = (read_status_t)bnx2x_8727_read_status,
11529         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11530         .config_loopback = (config_loopback_t)NULL,
11531         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11532         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11533         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11534         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11535 };
11536 static const struct bnx2x_phy phy_8481 = {
11537         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11538         .addr           = 0xff,
11539         .def_md_devad   = 0,
11540         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11541                           FLAGS_REARM_LATCH_SIGNAL,
11542         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11543         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11544         .mdio_ctrl      = 0,
11545         .supported      = (SUPPORTED_10baseT_Half |
11546                            SUPPORTED_10baseT_Full |
11547                            SUPPORTED_100baseT_Half |
11548                            SUPPORTED_100baseT_Full |
11549                            SUPPORTED_1000baseT_Full |
11550                            SUPPORTED_10000baseT_Full |
11551                            SUPPORTED_TP |
11552                            SUPPORTED_Autoneg |
11553                            SUPPORTED_Pause |
11554                            SUPPORTED_Asym_Pause),
11555         .media_type     = ETH_PHY_BASE_T,
11556         .ver_addr       = 0,
11557         .req_flow_ctrl  = 0,
11558         .req_line_speed = 0,
11559         .speed_cap_mask = 0,
11560         .req_duplex     = 0,
11561         .rsrv           = 0,
11562         .config_init    = (config_init_t)bnx2x_8481_config_init,
11563         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11564         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11565         .config_loopback = (config_loopback_t)NULL,
11566         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11567         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11568         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11569         .phy_specific_func = (phy_specific_func_t)NULL
11570 };
11571
11572 static const struct bnx2x_phy phy_84823 = {
11573         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11574         .addr           = 0xff,
11575         .def_md_devad   = 0,
11576         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11577                            FLAGS_REARM_LATCH_SIGNAL |
11578                            FLAGS_TX_ERROR_CHECK),
11579         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11580         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11581         .mdio_ctrl      = 0,
11582         .supported      = (SUPPORTED_10baseT_Half |
11583                            SUPPORTED_10baseT_Full |
11584                            SUPPORTED_100baseT_Half |
11585                            SUPPORTED_100baseT_Full |
11586                            SUPPORTED_1000baseT_Full |
11587                            SUPPORTED_10000baseT_Full |
11588                            SUPPORTED_TP |
11589                            SUPPORTED_Autoneg |
11590                            SUPPORTED_Pause |
11591                            SUPPORTED_Asym_Pause),
11592         .media_type     = ETH_PHY_BASE_T,
11593         .ver_addr       = 0,
11594         .req_flow_ctrl  = 0,
11595         .req_line_speed = 0,
11596         .speed_cap_mask = 0,
11597         .req_duplex     = 0,
11598         .rsrv           = 0,
11599         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11600         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11601         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11602         .config_loopback = (config_loopback_t)NULL,
11603         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11604         .hw_reset       = (hw_reset_t)NULL,
11605         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11606         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11607 };
11608
11609 static const struct bnx2x_phy phy_84833 = {
11610         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11611         .addr           = 0xff,
11612         .def_md_devad   = 0,
11613         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11614                            FLAGS_REARM_LATCH_SIGNAL |
11615                            FLAGS_TX_ERROR_CHECK),
11616         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11617         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11618         .mdio_ctrl      = 0,
11619         .supported      = (SUPPORTED_100baseT_Half |
11620                            SUPPORTED_100baseT_Full |
11621                            SUPPORTED_1000baseT_Full |
11622                            SUPPORTED_10000baseT_Full |
11623                            SUPPORTED_TP |
11624                            SUPPORTED_Autoneg |
11625                            SUPPORTED_Pause |
11626                            SUPPORTED_Asym_Pause),
11627         .media_type     = ETH_PHY_BASE_T,
11628         .ver_addr       = 0,
11629         .req_flow_ctrl  = 0,
11630         .req_line_speed = 0,
11631         .speed_cap_mask = 0,
11632         .req_duplex     = 0,
11633         .rsrv           = 0,
11634         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11635         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11636         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11637         .config_loopback = (config_loopback_t)NULL,
11638         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11639         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11640         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11641         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11642 };
11643
11644 static const struct bnx2x_phy phy_84834 = {
11645         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11646         .addr           = 0xff,
11647         .def_md_devad   = 0,
11648         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11649                             FLAGS_REARM_LATCH_SIGNAL,
11650         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11651         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11652         .mdio_ctrl      = 0,
11653         .supported      = (SUPPORTED_100baseT_Half |
11654                            SUPPORTED_100baseT_Full |
11655                            SUPPORTED_1000baseT_Full |
11656                            SUPPORTED_10000baseT_Full |
11657                            SUPPORTED_TP |
11658                            SUPPORTED_Autoneg |
11659                            SUPPORTED_Pause |
11660                            SUPPORTED_Asym_Pause),
11661         .media_type     = ETH_PHY_BASE_T,
11662         .ver_addr       = 0,
11663         .req_flow_ctrl  = 0,
11664         .req_line_speed = 0,
11665         .speed_cap_mask = 0,
11666         .req_duplex     = 0,
11667         .rsrv           = 0,
11668         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11669         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11670         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11671         .config_loopback = (config_loopback_t)NULL,
11672         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11673         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11674         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11675         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11676 };
11677
11678 static const struct bnx2x_phy phy_54618se = {
11679         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11680         .addr           = 0xff,
11681         .def_md_devad   = 0,
11682         .flags          = FLAGS_INIT_XGXS_FIRST,
11683         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11684         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11685         .mdio_ctrl      = 0,
11686         .supported      = (SUPPORTED_10baseT_Half |
11687                            SUPPORTED_10baseT_Full |
11688                            SUPPORTED_100baseT_Half |
11689                            SUPPORTED_100baseT_Full |
11690                            SUPPORTED_1000baseT_Full |
11691                            SUPPORTED_TP |
11692                            SUPPORTED_Autoneg |
11693                            SUPPORTED_Pause |
11694                            SUPPORTED_Asym_Pause),
11695         .media_type     = ETH_PHY_BASE_T,
11696         .ver_addr       = 0,
11697         .req_flow_ctrl  = 0,
11698         .req_line_speed = 0,
11699         .speed_cap_mask = 0,
11700         /* req_duplex = */0,
11701         /* rsrv = */0,
11702         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11703         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11704         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11705         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11706         .format_fw_ver  = (format_fw_ver_t)NULL,
11707         .hw_reset       = (hw_reset_t)NULL,
11708         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11709         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11710 };
11711 /*****************************************************************/
11712 /*                                                               */
11713 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11714 /*                                                               */
11715 /*****************************************************************/
11716
11717 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11718                                      struct bnx2x_phy *phy, u8 port,
11719                                      u8 phy_index)
11720 {
11721         /* Get the 4 lanes xgxs config rx and tx */
11722         u32 rx = 0, tx = 0, i;
11723         for (i = 0; i < 2; i++) {
11724                 /* INT_PHY and EXT_PHY1 share the same value location in
11725                  * the shmem. When num_phys is greater than 1, than this value
11726                  * applies only to EXT_PHY1
11727                  */
11728                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11729                         rx = REG_RD(bp, shmem_base +
11730                                     offsetof(struct shmem_region,
11731                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11732
11733                         tx = REG_RD(bp, shmem_base +
11734                                     offsetof(struct shmem_region,
11735                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11736                 } else {
11737                         rx = REG_RD(bp, shmem_base +
11738                                     offsetof(struct shmem_region,
11739                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11740
11741                         tx = REG_RD(bp, shmem_base +
11742                                     offsetof(struct shmem_region,
11743                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11744                 }
11745
11746                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11747                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11748
11749                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11750                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11751         }
11752 }
11753
11754 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11755                                     u8 phy_index, u8 port)
11756 {
11757         u32 ext_phy_config = 0;
11758         switch (phy_index) {
11759         case EXT_PHY1:
11760                 ext_phy_config = REG_RD(bp, shmem_base +
11761                                               offsetof(struct shmem_region,
11762                         dev_info.port_hw_config[port].external_phy_config));
11763                 break;
11764         case EXT_PHY2:
11765                 ext_phy_config = REG_RD(bp, shmem_base +
11766                                               offsetof(struct shmem_region,
11767                         dev_info.port_hw_config[port].external_phy_config2));
11768                 break;
11769         default:
11770                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11771                 return -EINVAL;
11772         }
11773
11774         return ext_phy_config;
11775 }
11776 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11777                                   struct bnx2x_phy *phy)
11778 {
11779         u32 phy_addr;
11780         u32 chip_id;
11781         u32 switch_cfg = (REG_RD(bp, shmem_base +
11782                                        offsetof(struct shmem_region,
11783                         dev_info.port_feature_config[port].link_config)) &
11784                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11785         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11786                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11787
11788         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11789         if (USES_WARPCORE(bp)) {
11790                 u32 serdes_net_if;
11791                 phy_addr = REG_RD(bp,
11792                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11793                 *phy = phy_warpcore;
11794                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11795                         phy->flags |= FLAGS_4_PORT_MODE;
11796                 else
11797                         phy->flags &= ~FLAGS_4_PORT_MODE;
11798                         /* Check Dual mode */
11799                 serdes_net_if = (REG_RD(bp, shmem_base +
11800                                         offsetof(struct shmem_region, dev_info.
11801                                         port_hw_config[port].default_cfg)) &
11802                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11803                 /* Set the appropriate supported and flags indications per
11804                  * interface type of the chip
11805                  */
11806                 switch (serdes_net_if) {
11807                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11808                         phy->supported &= (SUPPORTED_10baseT_Half |
11809                                            SUPPORTED_10baseT_Full |
11810                                            SUPPORTED_100baseT_Half |
11811                                            SUPPORTED_100baseT_Full |
11812                                            SUPPORTED_1000baseT_Full |
11813                                            SUPPORTED_FIBRE |
11814                                            SUPPORTED_Autoneg |
11815                                            SUPPORTED_Pause |
11816                                            SUPPORTED_Asym_Pause);
11817                         phy->media_type = ETH_PHY_BASE_T;
11818                         break;
11819                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11820                         phy->supported &= (SUPPORTED_1000baseT_Full |
11821                                            SUPPORTED_10000baseT_Full |
11822                                            SUPPORTED_FIBRE |
11823                                            SUPPORTED_Pause |
11824                                            SUPPORTED_Asym_Pause);
11825                         phy->media_type = ETH_PHY_XFP_FIBER;
11826                         break;
11827                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11828                         phy->supported &= (SUPPORTED_1000baseT_Full |
11829                                            SUPPORTED_10000baseT_Full |
11830                                            SUPPORTED_FIBRE |
11831                                            SUPPORTED_Pause |
11832                                            SUPPORTED_Asym_Pause);
11833                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11834                         break;
11835                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11836                         phy->media_type = ETH_PHY_KR;
11837                         phy->supported &= (SUPPORTED_1000baseT_Full |
11838                                            SUPPORTED_10000baseT_Full |
11839                                            SUPPORTED_FIBRE |
11840                                            SUPPORTED_Autoneg |
11841                                            SUPPORTED_Pause |
11842                                            SUPPORTED_Asym_Pause);
11843                         break;
11844                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11845                         phy->media_type = ETH_PHY_KR;
11846                         phy->flags |= FLAGS_WC_DUAL_MODE;
11847                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11848                                            SUPPORTED_FIBRE |
11849                                            SUPPORTED_Pause |
11850                                            SUPPORTED_Asym_Pause);
11851                         break;
11852                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11853                         phy->media_type = ETH_PHY_KR;
11854                         phy->flags |= FLAGS_WC_DUAL_MODE;
11855                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11856                                            SUPPORTED_10000baseT_Full |
11857                                            SUPPORTED_1000baseT_Full |
11858                                            SUPPORTED_Autoneg |
11859                                            SUPPORTED_FIBRE |
11860                                            SUPPORTED_Pause |
11861                                            SUPPORTED_Asym_Pause);
11862                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11863                         break;
11864                 default:
11865                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11866                                        serdes_net_if);
11867                         break;
11868                 }
11869
11870                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11871                  * was not set as expected. For B0, ECO will be enabled so there
11872                  * won't be an issue there
11873                  */
11874                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11875                         phy->flags |= FLAGS_MDC_MDIO_WA;
11876                 else
11877                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11878         } else {
11879                 switch (switch_cfg) {
11880                 case SWITCH_CFG_1G:
11881                         phy_addr = REG_RD(bp,
11882                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11883                                           port * 0x10);
11884                         *phy = phy_serdes;
11885                         break;
11886                 case SWITCH_CFG_10G:
11887                         phy_addr = REG_RD(bp,
11888                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11889                                           port * 0x18);
11890                         *phy = phy_xgxs;
11891                         break;
11892                 default:
11893                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11894                         return -EINVAL;
11895                 }
11896         }
11897         phy->addr = (u8)phy_addr;
11898         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11899                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11900                                             port);
11901         if (CHIP_IS_E2(bp))
11902                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11903         else
11904                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11905
11906         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11907                    port, phy->addr, phy->mdio_ctrl);
11908
11909         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11910         return 0;
11911 }
11912
11913 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11914                                   u8 phy_index,
11915                                   u32 shmem_base,
11916                                   u32 shmem2_base,
11917                                   u8 port,
11918                                   struct bnx2x_phy *phy)
11919 {
11920         u32 ext_phy_config, phy_type, config2;
11921         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11922         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11923                                                   phy_index, port);
11924         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11925         /* Select the phy type */
11926         switch (phy_type) {
11927         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11928                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11929                 *phy = phy_8073;
11930                 break;
11931         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11932                 *phy = phy_8705;
11933                 break;
11934         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11935                 *phy = phy_8706;
11936                 break;
11937         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11938                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11939                 *phy = phy_8726;
11940                 break;
11941         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11942                 /* BCM8727_NOC => BCM8727 no over current */
11943                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11944                 *phy = phy_8727;
11945                 phy->flags |= FLAGS_NOC;
11946                 break;
11947         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11948         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11949                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11950                 *phy = phy_8727;
11951                 break;
11952         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11953                 *phy = phy_8481;
11954                 break;
11955         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11956                 *phy = phy_84823;
11957                 break;
11958         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11959                 *phy = phy_84833;
11960                 break;
11961         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
11962                 *phy = phy_84834;
11963                 break;
11964         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11965         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11966                 *phy = phy_54618se;
11967                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
11968                         phy->flags |= FLAGS_EEE;
11969                 break;
11970         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11971                 *phy = phy_7101;
11972                 break;
11973         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11974                 *phy = phy_null;
11975                 return -EINVAL;
11976         default:
11977                 *phy = phy_null;
11978                 /* In case external PHY wasn't found */
11979                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11980                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11981                         return -EINVAL;
11982                 return 0;
11983         }
11984
11985         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11986         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11987
11988         /* The shmem address of the phy version is located on different
11989          * structures. In case this structure is too old, do not set
11990          * the address
11991          */
11992         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11993                                         dev_info.shared_hw_config.config2));
11994         if (phy_index == EXT_PHY1) {
11995                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11996                                 port_mb[port].ext_phy_fw_version);
11997
11998                 /* Check specific mdc mdio settings */
11999                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12000                         mdc_mdio_access = config2 &
12001                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12002         } else {
12003                 u32 size = REG_RD(bp, shmem2_base);
12004
12005                 if (size >
12006                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12007                         phy->ver_addr = shmem2_base +
12008                             offsetof(struct shmem2_region,
12009                                      ext_phy_fw_version2[port]);
12010                 }
12011                 /* Check specific mdc mdio settings */
12012                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12013                         mdc_mdio_access = (config2 &
12014                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12015                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12016                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12017         }
12018         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12019
12020         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12021              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12022             (phy->ver_addr)) {
12023                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12024                  * version lower than or equal to 1.39
12025                  */
12026                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12027                 if (((raw_ver & 0x7F) <= 39) &&
12028                     (((raw_ver & 0xF80) >> 7) <= 1))
12029                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12030                                             SUPPORTED_100baseT_Full);
12031         }
12032
12033         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12034                    phy_type, port, phy_index);
12035         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12036                    phy->addr, phy->mdio_ctrl);
12037         return 0;
12038 }
12039
12040 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12041                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12042 {
12043         int status = 0;
12044         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12045         if (phy_index == INT_PHY)
12046                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12047         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12048                                         port, phy);
12049         return status;
12050 }
12051
12052 static void bnx2x_phy_def_cfg(struct link_params *params,
12053                               struct bnx2x_phy *phy,
12054                               u8 phy_index)
12055 {
12056         struct bnx2x *bp = params->bp;
12057         u32 link_config;
12058         /* Populate the default phy configuration for MF mode */
12059         if (phy_index == EXT_PHY2) {
12060                 link_config = REG_RD(bp, params->shmem_base +
12061                                      offsetof(struct shmem_region, dev_info.
12062                         port_feature_config[params->port].link_config2));
12063                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12064                                              offsetof(struct shmem_region,
12065                                                       dev_info.
12066                         port_hw_config[params->port].speed_capability_mask2));
12067         } else {
12068                 link_config = REG_RD(bp, params->shmem_base +
12069                                      offsetof(struct shmem_region, dev_info.
12070                                 port_feature_config[params->port].link_config));
12071                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12072                                              offsetof(struct shmem_region,
12073                                                       dev_info.
12074                         port_hw_config[params->port].speed_capability_mask));
12075         }
12076         DP(NETIF_MSG_LINK,
12077            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12078            phy_index, link_config, phy->speed_cap_mask);
12079
12080         phy->req_duplex = DUPLEX_FULL;
12081         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12082         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12083                 phy->req_duplex = DUPLEX_HALF;
12084         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12085                 phy->req_line_speed = SPEED_10;
12086                 break;
12087         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12088                 phy->req_duplex = DUPLEX_HALF;
12089         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12090                 phy->req_line_speed = SPEED_100;
12091                 break;
12092         case PORT_FEATURE_LINK_SPEED_1G:
12093                 phy->req_line_speed = SPEED_1000;
12094                 break;
12095         case PORT_FEATURE_LINK_SPEED_2_5G:
12096                 phy->req_line_speed = SPEED_2500;
12097                 break;
12098         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12099                 phy->req_line_speed = SPEED_10000;
12100                 break;
12101         default:
12102                 phy->req_line_speed = SPEED_AUTO_NEG;
12103                 break;
12104         }
12105
12106         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12107         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12108                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12109                 break;
12110         case PORT_FEATURE_FLOW_CONTROL_TX:
12111                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12112                 break;
12113         case PORT_FEATURE_FLOW_CONTROL_RX:
12114                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12115                 break;
12116         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12117                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12118                 break;
12119         default:
12120                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12121                 break;
12122         }
12123 }
12124
12125 u32 bnx2x_phy_selection(struct link_params *params)
12126 {
12127         u32 phy_config_swapped, prio_cfg;
12128         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12129
12130         phy_config_swapped = params->multi_phy_config &
12131                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12132
12133         prio_cfg = params->multi_phy_config &
12134                         PORT_HW_CFG_PHY_SELECTION_MASK;
12135
12136         if (phy_config_swapped) {
12137                 switch (prio_cfg) {
12138                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12139                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12140                      break;
12141                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12142                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12143                      break;
12144                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12145                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12146                      break;
12147                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12148                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12149                      break;
12150                 }
12151         } else
12152                 return_cfg = prio_cfg;
12153
12154         return return_cfg;
12155 }
12156
12157 int bnx2x_phy_probe(struct link_params *params)
12158 {
12159         u8 phy_index, actual_phy_idx;
12160         u32 phy_config_swapped, sync_offset, media_types;
12161         struct bnx2x *bp = params->bp;
12162         struct bnx2x_phy *phy;
12163         params->num_phys = 0;
12164         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12165         phy_config_swapped = params->multi_phy_config &
12166                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12167
12168         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12169               phy_index++) {
12170                 actual_phy_idx = phy_index;
12171                 if (phy_config_swapped) {
12172                         if (phy_index == EXT_PHY1)
12173                                 actual_phy_idx = EXT_PHY2;
12174                         else if (phy_index == EXT_PHY2)
12175                                 actual_phy_idx = EXT_PHY1;
12176                 }
12177                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12178                                " actual_phy_idx %x\n", phy_config_swapped,
12179                            phy_index, actual_phy_idx);
12180                 phy = &params->phy[actual_phy_idx];
12181                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12182                                        params->shmem2_base, params->port,
12183                                        phy) != 0) {
12184                         params->num_phys = 0;
12185                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12186                                    phy_index);
12187                         for (phy_index = INT_PHY;
12188                               phy_index < MAX_PHYS;
12189                               phy_index++)
12190                                 *phy = phy_null;
12191                         return -EINVAL;
12192                 }
12193                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12194                         break;
12195
12196                 if (params->feature_config_flags &
12197                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12198                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12199
12200                 if (!(params->feature_config_flags &
12201                       FEATURE_CONFIG_MT_SUPPORT))
12202                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12203
12204                 sync_offset = params->shmem_base +
12205                         offsetof(struct shmem_region,
12206                         dev_info.port_hw_config[params->port].media_type);
12207                 media_types = REG_RD(bp, sync_offset);
12208
12209                 /* Update media type for non-PMF sync only for the first time
12210                  * In case the media type changes afterwards, it will be updated
12211                  * using the update_status function
12212                  */
12213                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12214                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12215                                      actual_phy_idx))) == 0) {
12216                         media_types |= ((phy->media_type &
12217                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12218                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12219                                  actual_phy_idx));
12220                 }
12221                 REG_WR(bp, sync_offset, media_types);
12222
12223                 bnx2x_phy_def_cfg(params, phy, phy_index);
12224                 params->num_phys++;
12225         }
12226
12227         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12228         return 0;
12229 }
12230
12231 static void bnx2x_init_bmac_loopback(struct link_params *params,
12232                                      struct link_vars *vars)
12233 {
12234         struct bnx2x *bp = params->bp;
12235                 vars->link_up = 1;
12236                 vars->line_speed = SPEED_10000;
12237                 vars->duplex = DUPLEX_FULL;
12238                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12239                 vars->mac_type = MAC_TYPE_BMAC;
12240
12241                 vars->phy_flags = PHY_XGXS_FLAG;
12242
12243                 bnx2x_xgxs_deassert(params);
12244
12245                 /* set bmac loopback */
12246                 bnx2x_bmac_enable(params, vars, 1, 1);
12247
12248                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12249 }
12250
12251 static void bnx2x_init_emac_loopback(struct link_params *params,
12252                                      struct link_vars *vars)
12253 {
12254         struct bnx2x *bp = params->bp;
12255                 vars->link_up = 1;
12256                 vars->line_speed = SPEED_1000;
12257                 vars->duplex = DUPLEX_FULL;
12258                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12259                 vars->mac_type = MAC_TYPE_EMAC;
12260
12261                 vars->phy_flags = PHY_XGXS_FLAG;
12262
12263                 bnx2x_xgxs_deassert(params);
12264                 /* set bmac loopback */
12265                 bnx2x_emac_enable(params, vars, 1);
12266                 bnx2x_emac_program(params, vars);
12267                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12268 }
12269
12270 static void bnx2x_init_xmac_loopback(struct link_params *params,
12271                                      struct link_vars *vars)
12272 {
12273         struct bnx2x *bp = params->bp;
12274         vars->link_up = 1;
12275         if (!params->req_line_speed[0])
12276                 vars->line_speed = SPEED_10000;
12277         else
12278                 vars->line_speed = params->req_line_speed[0];
12279         vars->duplex = DUPLEX_FULL;
12280         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12281         vars->mac_type = MAC_TYPE_XMAC;
12282         vars->phy_flags = PHY_XGXS_FLAG;
12283         /* Set WC to loopback mode since link is required to provide clock
12284          * to the XMAC in 20G mode
12285          */
12286         bnx2x_set_aer_mmd(params, &params->phy[0]);
12287         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12288         params->phy[INT_PHY].config_loopback(
12289                         &params->phy[INT_PHY],
12290                         params);
12291
12292         bnx2x_xmac_enable(params, vars, 1);
12293         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12294 }
12295
12296 static void bnx2x_init_umac_loopback(struct link_params *params,
12297                                      struct link_vars *vars)
12298 {
12299         struct bnx2x *bp = params->bp;
12300         vars->link_up = 1;
12301         vars->line_speed = SPEED_1000;
12302         vars->duplex = DUPLEX_FULL;
12303         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12304         vars->mac_type = MAC_TYPE_UMAC;
12305         vars->phy_flags = PHY_XGXS_FLAG;
12306         bnx2x_umac_enable(params, vars, 1);
12307
12308         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12309 }
12310
12311 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12312                                      struct link_vars *vars)
12313 {
12314         struct bnx2x *bp = params->bp;
12315         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12316         vars->link_up = 1;
12317         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12318         vars->duplex = DUPLEX_FULL;
12319         if (params->req_line_speed[0] == SPEED_1000)
12320                 vars->line_speed = SPEED_1000;
12321         else if ((params->req_line_speed[0] == SPEED_20000) ||
12322                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12323                 vars->line_speed = SPEED_20000;
12324         else
12325                 vars->line_speed = SPEED_10000;
12326
12327         if (!USES_WARPCORE(bp))
12328                 bnx2x_xgxs_deassert(params);
12329         bnx2x_link_initialize(params, vars);
12330
12331         if (params->req_line_speed[0] == SPEED_1000) {
12332                 if (USES_WARPCORE(bp))
12333                         bnx2x_umac_enable(params, vars, 0);
12334                 else {
12335                         bnx2x_emac_program(params, vars);
12336                         bnx2x_emac_enable(params, vars, 0);
12337                 }
12338         } else {
12339                 if (USES_WARPCORE(bp))
12340                         bnx2x_xmac_enable(params, vars, 0);
12341                 else
12342                         bnx2x_bmac_enable(params, vars, 0, 1);
12343         }
12344
12345         if (params->loopback_mode == LOOPBACK_XGXS) {
12346                 /* Set 10G XGXS loopback */
12347                 int_phy->config_loopback(int_phy, params);
12348         } else {
12349                 /* Set external phy loopback */
12350                 u8 phy_index;
12351                 for (phy_index = EXT_PHY1;
12352                       phy_index < params->num_phys; phy_index++)
12353                         if (params->phy[phy_index].config_loopback)
12354                                 params->phy[phy_index].config_loopback(
12355                                         &params->phy[phy_index],
12356                                         params);
12357         }
12358         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12359
12360         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12361 }
12362
12363 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12364 {
12365         struct bnx2x *bp = params->bp;
12366         u8 val = en * 0x1F;
12367
12368         /* Open / close the gate between the NIG and the BRB */
12369         if (!CHIP_IS_E1x(bp))
12370                 val |= en * 0x20;
12371         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12372
12373         if (!CHIP_IS_E1(bp)) {
12374                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12375                        en*0x3);
12376         }
12377
12378         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12379                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12380 }
12381 static int bnx2x_avoid_link_flap(struct link_params *params,
12382                                             struct link_vars *vars)
12383 {
12384         u32 phy_idx;
12385         u32 dont_clear_stat, lfa_sts;
12386         struct bnx2x *bp = params->bp;
12387
12388         /* Sync the link parameters */
12389         bnx2x_link_status_update(params, vars);
12390
12391         /*
12392          * The module verification was already done by previous link owner,
12393          * so this call is meant only to get warning message
12394          */
12395
12396         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12397                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12398                 if (phy->phy_specific_func) {
12399                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12400                         phy->phy_specific_func(phy, params, PHY_INIT);
12401                 }
12402                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12403                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12404                     (phy->media_type == ETH_PHY_DA_TWINAX))
12405                         bnx2x_verify_sfp_module(phy, params);
12406         }
12407         lfa_sts = REG_RD(bp, params->lfa_base +
12408                          offsetof(struct shmem_lfa,
12409                                   lfa_sts));
12410
12411         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12412
12413         /* Re-enable the NIG/MAC */
12414         if (CHIP_IS_E3(bp)) {
12415                 if (!dont_clear_stat) {
12416                         REG_WR(bp, GRCBASE_MISC +
12417                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12418                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12419                                 params->port));
12420                         REG_WR(bp, GRCBASE_MISC +
12421                                MISC_REGISTERS_RESET_REG_2_SET,
12422                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12423                                 params->port));
12424                 }
12425                 if (vars->line_speed < SPEED_10000)
12426                         bnx2x_umac_enable(params, vars, 0);
12427                 else
12428                         bnx2x_xmac_enable(params, vars, 0);
12429         } else {
12430                 if (vars->line_speed < SPEED_10000)
12431                         bnx2x_emac_enable(params, vars, 0);
12432                 else
12433                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12434         }
12435
12436         /* Increment LFA count */
12437         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12438                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12439                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12440                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12441         /* Clear link flap reason */
12442         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12443
12444         REG_WR(bp, params->lfa_base +
12445                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12446
12447         /* Disable NIG DRAIN */
12448         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12449
12450         /* Enable interrupts */
12451         bnx2x_link_int_enable(params);
12452         return 0;
12453 }
12454
12455 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12456                                          struct link_vars *vars,
12457                                          int lfa_status)
12458 {
12459         u32 lfa_sts, cfg_idx, tmp_val;
12460         struct bnx2x *bp = params->bp;
12461
12462         bnx2x_link_reset(params, vars, 1);
12463
12464         if (!params->lfa_base)
12465                 return;
12466         /* Store the new link parameters */
12467         REG_WR(bp, params->lfa_base +
12468                offsetof(struct shmem_lfa, req_duplex),
12469                params->req_duplex[0] | (params->req_duplex[1] << 16));
12470
12471         REG_WR(bp, params->lfa_base +
12472                offsetof(struct shmem_lfa, req_flow_ctrl),
12473                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12474
12475         REG_WR(bp, params->lfa_base +
12476                offsetof(struct shmem_lfa, req_line_speed),
12477                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12478
12479         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12480                 REG_WR(bp, params->lfa_base +
12481                        offsetof(struct shmem_lfa,
12482                                 speed_cap_mask[cfg_idx]),
12483                        params->speed_cap_mask[cfg_idx]);
12484         }
12485
12486         tmp_val = REG_RD(bp, params->lfa_base +
12487                          offsetof(struct shmem_lfa, additional_config));
12488         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12489         tmp_val |= params->req_fc_auto_adv;
12490
12491         REG_WR(bp, params->lfa_base +
12492                offsetof(struct shmem_lfa, additional_config), tmp_val);
12493
12494         lfa_sts = REG_RD(bp, params->lfa_base +
12495                          offsetof(struct shmem_lfa, lfa_sts));
12496
12497         /* Clear the "Don't Clear Statistics" bit, and set reason */
12498         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12499
12500         /* Set link flap reason */
12501         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12502         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12503                     LFA_LINK_FLAP_REASON_OFFSET);
12504
12505         /* Increment link flap counter */
12506         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12507                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12508                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12509                     << LINK_FLAP_COUNT_OFFSET));
12510         REG_WR(bp, params->lfa_base +
12511                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12512         /* Proceed with regular link initialization */
12513 }
12514
12515 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12516 {
12517         int lfa_status;
12518         struct bnx2x *bp = params->bp;
12519         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12520         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12521                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12522         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12523                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12524         vars->link_status = 0;
12525         vars->phy_link_up = 0;
12526         vars->link_up = 0;
12527         vars->line_speed = 0;
12528         vars->duplex = DUPLEX_FULL;
12529         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12530         vars->mac_type = MAC_TYPE_NONE;
12531         vars->phy_flags = 0;
12532         vars->check_kr2_recovery_cnt = 0;
12533         params->link_flags = PHY_INITIALIZED;
12534         /* Driver opens NIG-BRB filters */
12535         bnx2x_set_rx_filter(params, 1);
12536         /* Check if link flap can be avoided */
12537         lfa_status = bnx2x_check_lfa(params);
12538
12539         if (lfa_status == 0) {
12540                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12541                 return bnx2x_avoid_link_flap(params, vars);
12542         }
12543
12544         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12545                        lfa_status);
12546         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12547
12548         /* Disable attentions */
12549         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12550                        (NIG_MASK_XGXS0_LINK_STATUS |
12551                         NIG_MASK_XGXS0_LINK10G |
12552                         NIG_MASK_SERDES0_LINK_STATUS |
12553                         NIG_MASK_MI_INT));
12554
12555         bnx2x_emac_init(params, vars);
12556
12557         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12558                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12559
12560         if (params->num_phys == 0) {
12561                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12562                 return -EINVAL;
12563         }
12564         set_phy_vars(params, vars);
12565
12566         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12567         switch (params->loopback_mode) {
12568         case LOOPBACK_BMAC:
12569                 bnx2x_init_bmac_loopback(params, vars);
12570                 break;
12571         case LOOPBACK_EMAC:
12572                 bnx2x_init_emac_loopback(params, vars);
12573                 break;
12574         case LOOPBACK_XMAC:
12575                 bnx2x_init_xmac_loopback(params, vars);
12576                 break;
12577         case LOOPBACK_UMAC:
12578                 bnx2x_init_umac_loopback(params, vars);
12579                 break;
12580         case LOOPBACK_XGXS:
12581         case LOOPBACK_EXT_PHY:
12582                 bnx2x_init_xgxs_loopback(params, vars);
12583                 break;
12584         default:
12585                 if (!CHIP_IS_E3(bp)) {
12586                         if (params->switch_cfg == SWITCH_CFG_10G)
12587                                 bnx2x_xgxs_deassert(params);
12588                         else
12589                                 bnx2x_serdes_deassert(bp, params->port);
12590                 }
12591                 bnx2x_link_initialize(params, vars);
12592                 msleep(30);
12593                 bnx2x_link_int_enable(params);
12594                 break;
12595         }
12596         bnx2x_update_mng(params, vars->link_status);
12597
12598         bnx2x_update_mng_eee(params, vars->eee_status);
12599         return 0;
12600 }
12601
12602 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12603                      u8 reset_ext_phy)
12604 {
12605         struct bnx2x *bp = params->bp;
12606         u8 phy_index, port = params->port, clear_latch_ind = 0;
12607         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12608         /* Disable attentions */
12609         vars->link_status = 0;
12610         bnx2x_update_mng(params, vars->link_status);
12611         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12612                               SHMEM_EEE_ACTIVE_BIT);
12613         bnx2x_update_mng_eee(params, vars->eee_status);
12614         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12615                        (NIG_MASK_XGXS0_LINK_STATUS |
12616                         NIG_MASK_XGXS0_LINK10G |
12617                         NIG_MASK_SERDES0_LINK_STATUS |
12618                         NIG_MASK_MI_INT));
12619
12620         /* Activate nig drain */
12621         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12622
12623         /* Disable nig egress interface */
12624         if (!CHIP_IS_E3(bp)) {
12625                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12626                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12627         }
12628
12629                 if (!CHIP_IS_E3(bp)) {
12630                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12631                 } else {
12632                         bnx2x_set_xmac_rxtx(params, 0);
12633                         bnx2x_set_umac_rxtx(params, 0);
12634                 }
12635         /* Disable emac */
12636         if (!CHIP_IS_E3(bp))
12637                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12638
12639         usleep_range(10000, 20000);
12640         /* The PHY reset is controlled by GPIO 1
12641          * Hold it as vars low
12642          */
12643          /* Clear link led */
12644         bnx2x_set_mdio_emac_per_phy(bp, params);
12645         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12646
12647         if (reset_ext_phy) {
12648                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12649                       phy_index++) {
12650                         if (params->phy[phy_index].link_reset) {
12651                                 bnx2x_set_aer_mmd(params,
12652                                                   &params->phy[phy_index]);
12653                                 params->phy[phy_index].link_reset(
12654                                         &params->phy[phy_index],
12655                                         params);
12656                         }
12657                         if (params->phy[phy_index].flags &
12658                             FLAGS_REARM_LATCH_SIGNAL)
12659                                 clear_latch_ind = 1;
12660                 }
12661         }
12662
12663         if (clear_latch_ind) {
12664                 /* Clear latching indication */
12665                 bnx2x_rearm_latch_signal(bp, port, 0);
12666                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12667                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12668         }
12669         if (params->phy[INT_PHY].link_reset)
12670                 params->phy[INT_PHY].link_reset(
12671                         &params->phy[INT_PHY], params);
12672
12673         /* Disable nig ingress interface */
12674         if (!CHIP_IS_E3(bp)) {
12675                 /* Reset BigMac */
12676                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12677                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12678                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12679                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12680         } else {
12681                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12682                 bnx2x_set_xumac_nig(params, 0, 0);
12683                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12684                     MISC_REGISTERS_RESET_REG_2_XMAC)
12685                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12686                                XMAC_CTRL_REG_SOFT_RESET);
12687         }
12688         vars->link_up = 0;
12689         vars->phy_flags = 0;
12690         return 0;
12691 }
12692 int bnx2x_lfa_reset(struct link_params *params,
12693                                struct link_vars *vars)
12694 {
12695         struct bnx2x *bp = params->bp;
12696         vars->link_up = 0;
12697         vars->phy_flags = 0;
12698         params->link_flags &= ~PHY_INITIALIZED;
12699         if (!params->lfa_base)
12700                 return bnx2x_link_reset(params, vars, 1);
12701         /*
12702          * Activate NIG drain so that during this time the device won't send
12703          * anything while it is unable to response.
12704          */
12705         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12706
12707         /*
12708          * Close gracefully the gate from BMAC to NIG such that no half packets
12709          * are passed.
12710          */
12711         if (!CHIP_IS_E3(bp))
12712                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12713
12714         if (CHIP_IS_E3(bp)) {
12715                 bnx2x_set_xmac_rxtx(params, 0);
12716                 bnx2x_set_umac_rxtx(params, 0);
12717         }
12718         /* Wait 10ms for the pipe to clean up*/
12719         usleep_range(10000, 20000);
12720
12721         /* Clean the NIG-BRB using the network filters in a way that will
12722          * not cut a packet in the middle.
12723          */
12724         bnx2x_set_rx_filter(params, 0);
12725
12726         /*
12727          * Re-open the gate between the BMAC and the NIG, after verifying the
12728          * gate to the BRB is closed, otherwise packets may arrive to the
12729          * firmware before driver had initialized it. The target is to achieve
12730          * minimum management protocol down time.
12731          */
12732         if (!CHIP_IS_E3(bp))
12733                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12734
12735         if (CHIP_IS_E3(bp)) {
12736                 bnx2x_set_xmac_rxtx(params, 1);
12737                 bnx2x_set_umac_rxtx(params, 1);
12738         }
12739         /* Disable NIG drain */
12740         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12741         return 0;
12742 }
12743
12744 /****************************************************************************/
12745 /*                              Common function                             */
12746 /****************************************************************************/
12747 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12748                                       u32 shmem_base_path[],
12749                                       u32 shmem2_base_path[], u8 phy_index,
12750                                       u32 chip_id)
12751 {
12752         struct bnx2x_phy phy[PORT_MAX];
12753         struct bnx2x_phy *phy_blk[PORT_MAX];
12754         u16 val;
12755         s8 port = 0;
12756         s8 port_of_path = 0;
12757         u32 swap_val, swap_override;
12758         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12759         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12760         port ^= (swap_val && swap_override);
12761         bnx2x_ext_phy_hw_reset(bp, port);
12762         /* PART1 - Reset both phys */
12763         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12764                 u32 shmem_base, shmem2_base;
12765                 /* In E2, same phy is using for port0 of the two paths */
12766                 if (CHIP_IS_E1x(bp)) {
12767                         shmem_base = shmem_base_path[0];
12768                         shmem2_base = shmem2_base_path[0];
12769                         port_of_path = port;
12770                 } else {
12771                         shmem_base = shmem_base_path[port];
12772                         shmem2_base = shmem2_base_path[port];
12773                         port_of_path = 0;
12774                 }
12775
12776                 /* Extract the ext phy address for the port */
12777                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12778                                        port_of_path, &phy[port]) !=
12779                     0) {
12780                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12781                         return -EINVAL;
12782                 }
12783                 /* Disable attentions */
12784                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12785                                port_of_path*4,
12786                                (NIG_MASK_XGXS0_LINK_STATUS |
12787                                 NIG_MASK_XGXS0_LINK10G |
12788                                 NIG_MASK_SERDES0_LINK_STATUS |
12789                                 NIG_MASK_MI_INT));
12790
12791                 /* Need to take the phy out of low power mode in order
12792                  * to write to access its registers
12793                  */
12794                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12795                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12796                                port);
12797
12798                 /* Reset the phy */
12799                 bnx2x_cl45_write(bp, &phy[port],
12800                                  MDIO_PMA_DEVAD,
12801                                  MDIO_PMA_REG_CTRL,
12802                                  1<<15);
12803         }
12804
12805         /* Add delay of 150ms after reset */
12806         msleep(150);
12807
12808         if (phy[PORT_0].addr & 0x1) {
12809                 phy_blk[PORT_0] = &(phy[PORT_1]);
12810                 phy_blk[PORT_1] = &(phy[PORT_0]);
12811         } else {
12812                 phy_blk[PORT_0] = &(phy[PORT_0]);
12813                 phy_blk[PORT_1] = &(phy[PORT_1]);
12814         }
12815
12816         /* PART2 - Download firmware to both phys */
12817         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12818                 if (CHIP_IS_E1x(bp))
12819                         port_of_path = port;
12820                 else
12821                         port_of_path = 0;
12822
12823                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12824                            phy_blk[port]->addr);
12825                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12826                                                       port_of_path))
12827                         return -EINVAL;
12828
12829                 /* Only set bit 10 = 1 (Tx power down) */
12830                 bnx2x_cl45_read(bp, phy_blk[port],
12831                                 MDIO_PMA_DEVAD,
12832                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12833
12834                 /* Phase1 of TX_POWER_DOWN reset */
12835                 bnx2x_cl45_write(bp, phy_blk[port],
12836                                  MDIO_PMA_DEVAD,
12837                                  MDIO_PMA_REG_TX_POWER_DOWN,
12838                                  (val | 1<<10));
12839         }
12840
12841         /* Toggle Transmitter: Power down and then up with 600ms delay
12842          * between
12843          */
12844         msleep(600);
12845
12846         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12847         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12848                 /* Phase2 of POWER_DOWN_RESET */
12849                 /* Release bit 10 (Release Tx power down) */
12850                 bnx2x_cl45_read(bp, phy_blk[port],
12851                                 MDIO_PMA_DEVAD,
12852                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12853
12854                 bnx2x_cl45_write(bp, phy_blk[port],
12855                                 MDIO_PMA_DEVAD,
12856                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12857                 usleep_range(15000, 30000);
12858
12859                 /* Read modify write the SPI-ROM version select register */
12860                 bnx2x_cl45_read(bp, phy_blk[port],
12861                                 MDIO_PMA_DEVAD,
12862                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12863                 bnx2x_cl45_write(bp, phy_blk[port],
12864                                  MDIO_PMA_DEVAD,
12865                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12866
12867                 /* set GPIO2 back to LOW */
12868                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12869                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12870         }
12871         return 0;
12872 }
12873 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12874                                       u32 shmem_base_path[],
12875                                       u32 shmem2_base_path[], u8 phy_index,
12876                                       u32 chip_id)
12877 {
12878         u32 val;
12879         s8 port;
12880         struct bnx2x_phy phy;
12881         /* Use port1 because of the static port-swap */
12882         /* Enable the module detection interrupt */
12883         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12884         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12885                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12886         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12887
12888         bnx2x_ext_phy_hw_reset(bp, 0);
12889         usleep_range(5000, 10000);
12890         for (port = 0; port < PORT_MAX; port++) {
12891                 u32 shmem_base, shmem2_base;
12892
12893                 /* In E2, same phy is using for port0 of the two paths */
12894                 if (CHIP_IS_E1x(bp)) {
12895                         shmem_base = shmem_base_path[0];
12896                         shmem2_base = shmem2_base_path[0];
12897                 } else {
12898                         shmem_base = shmem_base_path[port];
12899                         shmem2_base = shmem2_base_path[port];
12900                 }
12901                 /* Extract the ext phy address for the port */
12902                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12903                                        port, &phy) !=
12904                     0) {
12905                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12906                         return -EINVAL;
12907                 }
12908
12909                 /* Reset phy*/
12910                 bnx2x_cl45_write(bp, &phy,
12911                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12912
12913
12914                 /* Set fault module detected LED on */
12915                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12916                                MISC_REGISTERS_GPIO_HIGH,
12917                                port);
12918         }
12919
12920         return 0;
12921 }
12922 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12923                                          u8 *io_gpio, u8 *io_port)
12924 {
12925
12926         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12927                                           offsetof(struct shmem_region,
12928                                 dev_info.port_hw_config[PORT_0].default_cfg));
12929         switch (phy_gpio_reset) {
12930         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12931                 *io_gpio = 0;
12932                 *io_port = 0;
12933                 break;
12934         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12935                 *io_gpio = 1;
12936                 *io_port = 0;
12937                 break;
12938         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12939                 *io_gpio = 2;
12940                 *io_port = 0;
12941                 break;
12942         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12943                 *io_gpio = 3;
12944                 *io_port = 0;
12945                 break;
12946         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12947                 *io_gpio = 0;
12948                 *io_port = 1;
12949                 break;
12950         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12951                 *io_gpio = 1;
12952                 *io_port = 1;
12953                 break;
12954         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12955                 *io_gpio = 2;
12956                 *io_port = 1;
12957                 break;
12958         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12959                 *io_gpio = 3;
12960                 *io_port = 1;
12961                 break;
12962         default:
12963                 /* Don't override the io_gpio and io_port */
12964                 break;
12965         }
12966 }
12967
12968 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12969                                       u32 shmem_base_path[],
12970                                       u32 shmem2_base_path[], u8 phy_index,
12971                                       u32 chip_id)
12972 {
12973         s8 port, reset_gpio;
12974         u32 swap_val, swap_override;
12975         struct bnx2x_phy phy[PORT_MAX];
12976         struct bnx2x_phy *phy_blk[PORT_MAX];
12977         s8 port_of_path;
12978         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12979         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12980
12981         reset_gpio = MISC_REGISTERS_GPIO_1;
12982         port = 1;
12983
12984         /* Retrieve the reset gpio/port which control the reset.
12985          * Default is GPIO1, PORT1
12986          */
12987         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12988                                      (u8 *)&reset_gpio, (u8 *)&port);
12989
12990         /* Calculate the port based on port swap */
12991         port ^= (swap_val && swap_override);
12992
12993         /* Initiate PHY reset*/
12994         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12995                        port);
12996         usleep_range(1000, 2000);
12997         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12998                        port);
12999
13000         usleep_range(5000, 10000);
13001
13002         /* PART1 - Reset both phys */
13003         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13004                 u32 shmem_base, shmem2_base;
13005
13006                 /* In E2, same phy is using for port0 of the two paths */
13007                 if (CHIP_IS_E1x(bp)) {
13008                         shmem_base = shmem_base_path[0];
13009                         shmem2_base = shmem2_base_path[0];
13010                         port_of_path = port;
13011                 } else {
13012                         shmem_base = shmem_base_path[port];
13013                         shmem2_base = shmem2_base_path[port];
13014                         port_of_path = 0;
13015                 }
13016
13017                 /* Extract the ext phy address for the port */
13018                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13019                                        port_of_path, &phy[port]) !=
13020                                        0) {
13021                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13022                         return -EINVAL;
13023                 }
13024                 /* disable attentions */
13025                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13026                                port_of_path*4,
13027                                (NIG_MASK_XGXS0_LINK_STATUS |
13028                                 NIG_MASK_XGXS0_LINK10G |
13029                                 NIG_MASK_SERDES0_LINK_STATUS |
13030                                 NIG_MASK_MI_INT));
13031
13032
13033                 /* Reset the phy */
13034                 bnx2x_cl45_write(bp, &phy[port],
13035                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13036         }
13037
13038         /* Add delay of 150ms after reset */
13039         msleep(150);
13040         if (phy[PORT_0].addr & 0x1) {
13041                 phy_blk[PORT_0] = &(phy[PORT_1]);
13042                 phy_blk[PORT_1] = &(phy[PORT_0]);
13043         } else {
13044                 phy_blk[PORT_0] = &(phy[PORT_0]);
13045                 phy_blk[PORT_1] = &(phy[PORT_1]);
13046         }
13047         /* PART2 - Download firmware to both phys */
13048         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13049                 if (CHIP_IS_E1x(bp))
13050                         port_of_path = port;
13051                 else
13052                         port_of_path = 0;
13053                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13054                            phy_blk[port]->addr);
13055                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13056                                                       port_of_path))
13057                         return -EINVAL;
13058                 /* Disable PHY transmitter output */
13059                 bnx2x_cl45_write(bp, phy_blk[port],
13060                                  MDIO_PMA_DEVAD,
13061                                  MDIO_PMA_REG_TX_DISABLE, 1);
13062
13063         }
13064         return 0;
13065 }
13066
13067 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13068                                                 u32 shmem_base_path[],
13069                                                 u32 shmem2_base_path[],
13070                                                 u8 phy_index,
13071                                                 u32 chip_id)
13072 {
13073         u8 reset_gpios;
13074         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13075         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13076         udelay(10);
13077         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13078         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13079                 reset_gpios);
13080         return 0;
13081 }
13082
13083 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13084                                      u32 shmem2_base_path[], u8 phy_index,
13085                                      u32 ext_phy_type, u32 chip_id)
13086 {
13087         int rc = 0;
13088
13089         switch (ext_phy_type) {
13090         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13091                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13092                                                 shmem2_base_path,
13093                                                 phy_index, chip_id);
13094                 break;
13095         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13096         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13097         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13098                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13099                                                 shmem2_base_path,
13100                                                 phy_index, chip_id);
13101                 break;
13102
13103         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13104                 /* GPIO1 affects both ports, so there's need to pull
13105                  * it for single port alone
13106                  */
13107                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13108                                                 shmem2_base_path,
13109                                                 phy_index, chip_id);
13110                 break;
13111         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13112         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13113                 /* GPIO3's are linked, and so both need to be toggled
13114                  * to obtain required 2us pulse.
13115                  */
13116                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13117                                                 shmem2_base_path,
13118                                                 phy_index, chip_id);
13119                 break;
13120         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13121                 rc = -EINVAL;
13122                 break;
13123         default:
13124                 DP(NETIF_MSG_LINK,
13125                            "ext_phy 0x%x common init not required\n",
13126                            ext_phy_type);
13127                 break;
13128         }
13129
13130         if (rc)
13131                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13132                                       " Port %d\n",
13133                          0);
13134         return rc;
13135 }
13136
13137 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13138                           u32 shmem2_base_path[], u32 chip_id)
13139 {
13140         int rc = 0;
13141         u32 phy_ver, val;
13142         u8 phy_index = 0;
13143         u32 ext_phy_type, ext_phy_config;
13144
13145         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13146         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13147         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13148         if (CHIP_IS_E3(bp)) {
13149                 /* Enable EPIO */
13150                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13151                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13152         }
13153         /* Check if common init was already done */
13154         phy_ver = REG_RD(bp, shmem_base_path[0] +
13155                          offsetof(struct shmem_region,
13156                                   port_mb[PORT_0].ext_phy_fw_version));
13157         if (phy_ver) {
13158                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13159                                phy_ver);
13160                 return 0;
13161         }
13162
13163         /* Read the ext_phy_type for arbitrary port(0) */
13164         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13165               phy_index++) {
13166                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13167                                                           shmem_base_path[0],
13168                                                           phy_index, 0);
13169                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13170                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13171                                                 shmem2_base_path,
13172                                                 phy_index, ext_phy_type,
13173                                                 chip_id);
13174         }
13175         return rc;
13176 }
13177
13178 static void bnx2x_check_over_curr(struct link_params *params,
13179                                   struct link_vars *vars)
13180 {
13181         struct bnx2x *bp = params->bp;
13182         u32 cfg_pin;
13183         u8 port = params->port;
13184         u32 pin_val;
13185
13186         cfg_pin = (REG_RD(bp, params->shmem_base +
13187                           offsetof(struct shmem_region,
13188                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13189                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13190                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13191
13192         /* Ignore check if no external input PIN available */
13193         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13194                 return;
13195
13196         if (!pin_val) {
13197                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13198                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13199                                             " been detected and the power to "
13200                                             "that SFP+ module has been removed"
13201                                             " to prevent failure of the card."
13202                                             " Please remove the SFP+ module and"
13203                                             " restart the system to clear this"
13204                                             " error.\n",
13205                          params->port);
13206                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13207                         bnx2x_warpcore_power_module(params, 0);
13208                 }
13209         } else
13210                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13211 }
13212
13213 /* Returns 0 if no change occured since last check; 1 otherwise. */
13214 static u8 bnx2x_analyze_link_error(struct link_params *params,
13215                                     struct link_vars *vars, u32 status,
13216                                     u32 phy_flag, u32 link_flag, u8 notify)
13217 {
13218         struct bnx2x *bp = params->bp;
13219         /* Compare new value with previous value */
13220         u8 led_mode;
13221         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13222
13223         if ((status ^ old_status) == 0)
13224                 return 0;
13225
13226         /* If values differ */
13227         switch (phy_flag) {
13228         case PHY_HALF_OPEN_CONN_FLAG:
13229                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13230                 break;
13231         case PHY_SFP_TX_FAULT_FLAG:
13232                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13233                 break;
13234         default:
13235                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13236         }
13237         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13238            old_status, status);
13239
13240         /* a. Update shmem->link_status accordingly
13241          * b. Update link_vars->link_up
13242          */
13243         if (status) {
13244                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13245                 vars->link_status |= link_flag;
13246                 vars->link_up = 0;
13247                 vars->phy_flags |= phy_flag;
13248
13249                 /* activate nig drain */
13250                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13251                 /* Set LED mode to off since the PHY doesn't know about these
13252                  * errors
13253                  */
13254                 led_mode = LED_MODE_OFF;
13255         } else {
13256                 vars->link_status |= LINK_STATUS_LINK_UP;
13257                 vars->link_status &= ~link_flag;
13258                 vars->link_up = 1;
13259                 vars->phy_flags &= ~phy_flag;
13260                 led_mode = LED_MODE_OPER;
13261
13262                 /* Clear nig drain */
13263                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13264         }
13265         bnx2x_sync_link(params, vars);
13266         /* Update the LED according to the link state */
13267         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13268
13269         /* Update link status in the shared memory */
13270         bnx2x_update_mng(params, vars->link_status);
13271
13272         /* C. Trigger General Attention */
13273         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13274         if (notify)
13275                 bnx2x_notify_link_changed(bp);
13276
13277         return 1;
13278 }
13279
13280 /******************************************************************************
13281 * Description:
13282 *       This function checks for half opened connection change indication.
13283 *       When such change occurs, it calls the bnx2x_analyze_link_error
13284 *       to check if Remote Fault is set or cleared. Reception of remote fault
13285 *       status message in the MAC indicates that the peer's MAC has detected
13286 *       a fault, for example, due to break in the TX side of fiber.
13287 *
13288 ******************************************************************************/
13289 int bnx2x_check_half_open_conn(struct link_params *params,
13290                                 struct link_vars *vars,
13291                                 u8 notify)
13292 {
13293         struct bnx2x *bp = params->bp;
13294         u32 lss_status = 0;
13295         u32 mac_base;
13296         /* In case link status is physically up @ 10G do */
13297         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13298             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13299                 return 0;
13300
13301         if (CHIP_IS_E3(bp) &&
13302             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13303               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13304                 /* Check E3 XMAC */
13305                 /* Note that link speed cannot be queried here, since it may be
13306                  * zero while link is down. In case UMAC is active, LSS will
13307                  * simply not be set
13308                  */
13309                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13310
13311                 /* Clear stick bits (Requires rising edge) */
13312                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13313                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13314                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13315                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13316                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13317                         lss_status = 1;
13318
13319                 bnx2x_analyze_link_error(params, vars, lss_status,
13320                                          PHY_HALF_OPEN_CONN_FLAG,
13321                                          LINK_STATUS_NONE, notify);
13322         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13323                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13324                 /* Check E1X / E2 BMAC */
13325                 u32 lss_status_reg;
13326                 u32 wb_data[2];
13327                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13328                         NIG_REG_INGRESS_BMAC0_MEM;
13329                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13330                 if (CHIP_IS_E2(bp))
13331                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13332                 else
13333                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13334
13335                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13336                 lss_status = (wb_data[0] > 0);
13337
13338                 bnx2x_analyze_link_error(params, vars, lss_status,
13339                                          PHY_HALF_OPEN_CONN_FLAG,
13340                                          LINK_STATUS_NONE, notify);
13341         }
13342         return 0;
13343 }
13344 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13345                                          struct link_params *params,
13346                                          struct link_vars *vars)
13347 {
13348         struct bnx2x *bp = params->bp;
13349         u32 cfg_pin, value = 0;
13350         u8 led_change, port = params->port;
13351
13352         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13353         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13354                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13355                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13356                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13357
13358         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13359                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13360                 return;
13361         }
13362
13363         led_change = bnx2x_analyze_link_error(params, vars, value,
13364                                               PHY_SFP_TX_FAULT_FLAG,
13365                                               LINK_STATUS_SFP_TX_FAULT, 1);
13366
13367         if (led_change) {
13368                 /* Change TX_Fault led, set link status for further syncs */
13369                 u8 led_mode;
13370
13371                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13372                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13373                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13374                 } else {
13375                         led_mode = MISC_REGISTERS_GPIO_LOW;
13376                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13377                 }
13378
13379                 /* If module is unapproved, led should be on regardless */
13380                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13381                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13382                            led_mode);
13383                         bnx2x_set_e3_module_fault_led(params, led_mode);
13384                 }
13385         }
13386 }
13387 static void bnx2x_disable_kr2(struct link_params *params,
13388                               struct link_vars *vars,
13389                               struct bnx2x_phy *phy)
13390 {
13391         struct bnx2x *bp = params->bp;
13392         int i;
13393         static struct bnx2x_reg_set reg_set[] = {
13394                 /* Step 1 - Program the TX/RX alignment markers */
13395                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13396                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13397                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13398                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13399                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13400                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13401                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13402                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13403                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13404                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13405                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13406                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13407                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13408                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13409                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13410         };
13411         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13412
13413         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
13414                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13415                                  reg_set[i].val);
13416         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13417         bnx2x_update_link_attr(params, vars->link_attr_sync);
13418
13419         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
13420         /* Restart AN on leading lane */
13421         bnx2x_warpcore_restart_AN_KR(phy, params);
13422 }
13423
13424 static void bnx2x_kr2_recovery(struct link_params *params,
13425                                struct link_vars *vars,
13426                                struct bnx2x_phy *phy)
13427 {
13428         struct bnx2x *bp = params->bp;
13429         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13430         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13431         bnx2x_warpcore_restart_AN_KR(phy, params);
13432 }
13433
13434 static void bnx2x_check_kr2_wa(struct link_params *params,
13435                                struct link_vars *vars,
13436                                struct bnx2x_phy *phy)
13437 {
13438         struct bnx2x *bp = params->bp;
13439         u16 base_page, next_page, not_kr2_device, lane;
13440         int sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13441
13442         if (!sigdet) {
13443                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
13444                         bnx2x_kr2_recovery(params, vars, phy);
13445                 return;
13446         }
13447
13448         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13449          * since some switches tend to reinit the AN process and clear the
13450          * advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13451          * and recovered many times
13452          */
13453         if (vars->check_kr2_recovery_cnt > 0) {
13454                 vars->check_kr2_recovery_cnt--;
13455                 return;
13456         }
13457         lane = bnx2x_get_warpcore_lane(phy, params);
13458         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13459                           MDIO_AER_BLOCK_AER_REG, lane);
13460         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13461                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13462         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13463                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13464         bnx2x_set_aer_mmd(params, phy);
13465
13466         /* CL73 has not begun yet */
13467         if (base_page == 0) {
13468                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
13469                         bnx2x_kr2_recovery(params, vars, phy);
13470                 return;
13471         }
13472
13473         /* In case NP bit is not set in the BasePage, or it is set,
13474          * but only KX is advertised, declare this link partner as non-KR2
13475          * device.
13476          */
13477         not_kr2_device = (((base_page & 0x8000) == 0) ||
13478                           (((base_page & 0x8000) &&
13479                             ((next_page & 0xe0) == 0x2))));
13480
13481         /* In case KR2 is already disabled, check if we need to re-enable it */
13482         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13483                 if (!not_kr2_device) {
13484                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13485                                        next_page);
13486                         bnx2x_kr2_recovery(params, vars, phy);
13487                 }
13488                 return;
13489         }
13490         /* KR2 is enabled, but not KR2 device */
13491         if (not_kr2_device) {
13492                 /* Disable KR2 on both lanes */
13493                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13494                 bnx2x_disable_kr2(params, vars, phy);
13495                 return;
13496         }
13497 }
13498
13499 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13500 {
13501         u16 phy_idx;
13502         struct bnx2x *bp = params->bp;
13503         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13504                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13505                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13506                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13507                             0)
13508                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13509                         break;
13510                 }
13511         }
13512
13513         if (CHIP_IS_E3(bp)) {
13514                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13515                 bnx2x_set_aer_mmd(params, phy);
13516                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13517                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13518                         bnx2x_check_kr2_wa(params, vars, phy);
13519                 bnx2x_check_over_curr(params, vars);
13520                 if (vars->rx_tx_asic_rst)
13521                         bnx2x_warpcore_config_runtime(phy, params, vars);
13522
13523                 if ((REG_RD(bp, params->shmem_base +
13524                             offsetof(struct shmem_region, dev_info.
13525                                 port_hw_config[params->port].default_cfg))
13526                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13527                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13528                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13529                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13530                         } else if (vars->link_status &
13531                                 LINK_STATUS_SFP_TX_FAULT) {
13532                                 /* Clean trail, interrupt corrects the leds */
13533                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13534                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13535                                 /* Update link status in the shared memory */
13536                                 bnx2x_update_mng(params, vars->link_status);
13537                         }
13538                 }
13539         }
13540 }
13541
13542 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13543                              u32 shmem_base,
13544                              u32 shmem2_base,
13545                              u8 port)
13546 {
13547         u8 phy_index, fan_failure_det_req = 0;
13548         struct bnx2x_phy phy;
13549         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13550               phy_index++) {
13551                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13552                                        port, &phy)
13553                     != 0) {
13554                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13555                         return 0;
13556                 }
13557                 fan_failure_det_req |= (phy.flags &
13558                                         FLAGS_FAN_FAILURE_DET_REQ);
13559         }
13560         return fan_failure_det_req;
13561 }
13562
13563 void bnx2x_hw_reset_phy(struct link_params *params)
13564 {
13565         u8 phy_index;
13566         struct bnx2x *bp = params->bp;
13567         bnx2x_update_mng(params, 0);
13568         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13569                        (NIG_MASK_XGXS0_LINK_STATUS |
13570                         NIG_MASK_XGXS0_LINK10G |
13571                         NIG_MASK_SERDES0_LINK_STATUS |
13572                         NIG_MASK_MI_INT));
13573
13574         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13575               phy_index++) {
13576                 if (params->phy[phy_index].hw_reset) {
13577                         params->phy[phy_index].hw_reset(
13578                                 &params->phy[phy_index],
13579                                 params);
13580                         params->phy[phy_index] = phy_null;
13581                 }
13582         }
13583 }
13584
13585 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13586                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13587                             u8 port)
13588 {
13589         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13590         u32 val;
13591         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13592         if (CHIP_IS_E3(bp)) {
13593                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13594                                               shmem_base,
13595                                               port,
13596                                               &gpio_num,
13597                                               &gpio_port) != 0)
13598                         return;
13599         } else {
13600                 struct bnx2x_phy phy;
13601                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13602                       phy_index++) {
13603                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13604                                                shmem2_base, port, &phy)
13605                             != 0) {
13606                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13607                                 return;
13608                         }
13609                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13610                                 gpio_num = MISC_REGISTERS_GPIO_3;
13611                                 gpio_port = port;
13612                                 break;
13613                         }
13614                 }
13615         }
13616
13617         if (gpio_num == 0xff)
13618                 return;
13619
13620         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13621         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13622
13623         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13624         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13625         gpio_port ^= (swap_val && swap_override);
13626
13627         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13628                 (gpio_num + (gpio_port << 2));
13629
13630         sync_offset = shmem_base +
13631                 offsetof(struct shmem_region,
13632                          dev_info.port_hw_config[port].aeu_int_mask);
13633         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13634
13635         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13636                        gpio_num, gpio_port, vars->aeu_int_mask);
13637
13638         if (port == 0)
13639                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13640         else
13641                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13642
13643         /* Open appropriate AEU for interrupts */
13644         aeu_mask = REG_RD(bp, offset);
13645         aeu_mask |= vars->aeu_int_mask;
13646         REG_WR(bp, offset, aeu_mask);
13647
13648         /* Enable the GPIO to trigger interrupt */
13649         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13650         val |= 1 << (gpio_num + (gpio_port << 2));
13651         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13652 }