1 /* Copyright 2008-2013 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
31 struct link_params *params,
32 u8 dev_addr, u16 addr, u8 byte_cnt,
34 /********************************************************/
36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
38 #define ETH_MIN_PACKET_SIZE 60
39 #define ETH_MAX_PACKET_SIZE 1500
40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
41 #define MDIO_ACCESS_TIMEOUT 1000
43 #define I2C_SWITCH_WIDTH 2
46 #define I2C_WA_RETRY_CNT 3
47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
48 #define MCPR_IMC_COMMAND_READ_OP 1
49 #define MCPR_IMC_COMMAND_WRITE_OP 2
51 /* LED Blink rate that will achieve ~15.9Hz */
52 #define LED_BLINK_RATE_VAL_E3 354
53 #define LED_BLINK_RATE_VAL_E1X_E2 480
54 /***********************************************************/
55 /* Shortcut definitions */
56 /***********************************************************/
58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
60 #define NIG_STATUS_EMAC0_MI_INT \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
62 #define NIG_STATUS_XGXS0_LINK10G \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
64 #define NIG_STATUS_XGXS0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
68 #define NIG_STATUS_SERDES0_LINK_STATUS \
69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
70 #define NIG_MASK_MI_INT \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
72 #define NIG_MASK_XGXS0_LINK10G \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
74 #define NIG_MASK_XGXS0_LINK_STATUS \
75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
76 #define NIG_MASK_SERDES0_LINK_STATUS \
77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
79 #define MDIO_AN_CL73_OR_37_COMPLETE \
80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
83 #define XGXS_RESET_BITS \
84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
90 #define SERDES_RESET_BITS \
91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
99 #define AUTONEG_PARALLEL \
100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
101 #define AUTONEG_SGMII_FIBER_AUTODET \
102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
109 #define GP_STATUS_SPEED_MASK \
110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
117 #define GP_STATUS_10G_HIG \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
119 #define GP_STATUS_10G_CX4 \
120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
122 #define GP_STATUS_10G_KX4 \
123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
145 #define LINK_UPDATE_MASK \
146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
147 LINK_STATUS_LINK_UP | \
148 LINK_STATUS_PHYSICAL_LINK_FLAG | \
149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
157 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
158 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
159 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
162 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
163 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
164 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
165 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
167 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
168 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
169 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
171 #define SFP_EEPROM_OPTIONS_ADDR 0x40
172 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
173 #define SFP_EEPROM_OPTIONS_SIZE 2
175 #define EDC_MODE_LINEAR 0x0022
176 #define EDC_MODE_LIMITING 0x0044
177 #define EDC_MODE_PASSIVE_DAC 0x0055
178 #define EDC_MODE_ACTIVE_DAC 0x0066
181 #define DCBX_INVALID_COS (0xFF)
183 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
184 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
185 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
186 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
187 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
189 #define MAX_PACKET_SIZE (9700)
190 #define MAX_KR_LINK_RETRY 4
192 /**********************************************************/
194 /**********************************************************/
196 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
197 bnx2x_cl45_write(_bp, _phy, \
198 (_phy)->def_md_devad, \
199 (_bank + (_addr & 0xf)), \
202 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
203 bnx2x_cl45_read(_bp, _phy, \
204 (_phy)->def_md_devad, \
205 (_bank + (_addr & 0xf)), \
208 static int bnx2x_check_half_open_conn(struct link_params *params,
209 struct link_vars *vars, u8 notify);
210 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
211 struct link_params *params);
213 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
215 u32 val = REG_RD(bp, reg);
218 REG_WR(bp, reg, val);
222 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
224 u32 val = REG_RD(bp, reg);
227 REG_WR(bp, reg, val);
232 * bnx2x_check_lfa - This function checks if link reinitialization is required,
233 * or link flap can be avoided.
235 * @params: link parameters
236 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
239 static int bnx2x_check_lfa(struct link_params *params)
241 u32 link_status, cfg_idx, lfa_mask, cfg_size;
242 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
243 u32 saved_val, req_val, eee_status;
244 struct bnx2x *bp = params->bp;
247 REG_RD(bp, params->lfa_base +
248 offsetof(struct shmem_lfa, additional_config));
250 /* NOTE: must be first condition checked -
251 * to verify DCC bit is cleared in any case!
253 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
254 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
255 REG_WR(bp, params->lfa_base +
256 offsetof(struct shmem_lfa, additional_config),
257 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
258 return LFA_DCC_LFA_DISABLED;
261 /* Verify that link is up */
262 link_status = REG_RD(bp, params->shmem_base +
263 offsetof(struct shmem_region,
264 port_mb[params->port].link_status));
265 if (!(link_status & LINK_STATUS_LINK_UP))
266 return LFA_LINK_DOWN;
268 /* if loaded after BOOT from SAN, don't flap the link in any case and
269 * rely on link set by preboot driver
271 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
274 /* Verify that loopback mode is not set */
275 if (params->loopback_mode)
276 return LFA_LOOPBACK_ENABLED;
278 /* Verify that MFW supports LFA */
279 if (!params->lfa_base)
280 return LFA_MFW_IS_TOO_OLD;
282 if (params->num_phys == 3) {
284 lfa_mask = 0xffffffff;
291 saved_val = REG_RD(bp, params->lfa_base +
292 offsetof(struct shmem_lfa, req_duplex));
293 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
294 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
295 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
296 (saved_val & lfa_mask), (req_val & lfa_mask));
297 return LFA_DUPLEX_MISMATCH;
299 /* Compare Flow Control */
300 saved_val = REG_RD(bp, params->lfa_base +
301 offsetof(struct shmem_lfa, req_flow_ctrl));
302 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
303 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
304 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
305 (saved_val & lfa_mask), (req_val & lfa_mask));
306 return LFA_FLOW_CTRL_MISMATCH;
308 /* Compare Link Speed */
309 saved_val = REG_RD(bp, params->lfa_base +
310 offsetof(struct shmem_lfa, req_line_speed));
311 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
312 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
313 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
314 (saved_val & lfa_mask), (req_val & lfa_mask));
315 return LFA_LINK_SPEED_MISMATCH;
318 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
319 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
320 offsetof(struct shmem_lfa,
321 speed_cap_mask[cfg_idx]));
323 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
324 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
326 params->speed_cap_mask[cfg_idx]);
327 return LFA_SPEED_CAP_MISMATCH;
331 cur_req_fc_auto_adv =
332 REG_RD(bp, params->lfa_base +
333 offsetof(struct shmem_lfa, additional_config)) &
334 REQ_FC_AUTO_ADV_MASK;
336 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
337 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
338 cur_req_fc_auto_adv, params->req_fc_auto_adv);
339 return LFA_FLOW_CTRL_MISMATCH;
342 eee_status = REG_RD(bp, params->shmem2_base +
343 offsetof(struct shmem2_region,
344 eee_status[params->port]));
346 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
347 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
348 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
349 (params->eee_mode & EEE_MODE_ADV_LPI))) {
350 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
352 return LFA_EEE_MISMATCH;
355 /* LFA conditions are met */
358 /******************************************************************/
359 /* EPIO/GPIO section */
360 /******************************************************************/
361 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
363 u32 epio_mask, gp_oenable;
367 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
371 epio_mask = 1 << epio_pin;
372 /* Set this EPIO to output */
373 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
374 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
376 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
378 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
380 u32 epio_mask, gp_output, gp_oenable;
384 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
387 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
388 epio_mask = 1 << epio_pin;
389 /* Set this EPIO to output */
390 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
392 gp_output |= epio_mask;
394 gp_output &= ~epio_mask;
396 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
398 /* Set the value for this EPIO */
399 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
400 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
403 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
405 if (pin_cfg == PIN_CFG_NA)
407 if (pin_cfg >= PIN_CFG_EPIO0) {
408 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
410 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
411 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
412 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
416 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
418 if (pin_cfg == PIN_CFG_NA)
420 if (pin_cfg >= PIN_CFG_EPIO0) {
421 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
423 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
424 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
425 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
430 /******************************************************************/
432 /******************************************************************/
433 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
435 /* ETS disabled configuration*/
436 struct bnx2x *bp = params->bp;
438 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
440 /* mapping between entry priority to client number (0,1,2 -debug and
441 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
443 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
444 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
447 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
448 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
449 * as strict. Bits 0,1,2 - debug and management entries, 3 -
450 * COS0 entry, 4 - COS1 entry.
451 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
452 * bit4 bit3 bit2 bit1 bit0
453 * MCP and debug are strict
456 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
457 /* defines which entries (clients) are subjected to WFQ arbitration */
458 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
459 /* For strict priority entries defines the number of consecutive
460 * slots for the highest priority.
462 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
463 /* mapping between the CREDIT_WEIGHT registers and actual client
466 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
467 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
468 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
470 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
471 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
472 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
473 /* ETS mode disable */
474 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
475 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
476 * weight for COS0/COS1.
478 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
479 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
480 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
481 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
482 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
483 /* Defines the number of consecutive slots for the strict priority */
484 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
486 /******************************************************************************
488 * Getting min_w_val will be set according to line speed .
490 ******************************************************************************/
491 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
494 /* Calculate min_w_val.*/
496 if (vars->line_speed == SPEED_20000)
497 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
499 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
501 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
502 /* If the link isn't up (static configuration for example ) The
503 * link will be according to 20GBPS.
507 /******************************************************************************
509 * Getting credit upper bound form min_w_val.
511 ******************************************************************************/
512 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
514 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
516 return credit_upper_bound;
518 /******************************************************************************
520 * Set credit upper bound for NIG.
522 ******************************************************************************/
523 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
524 const struct link_params *params,
527 struct bnx2x *bp = params->bp;
528 const u8 port = params->port;
529 const u32 credit_upper_bound =
530 bnx2x_ets_get_credit_upper_bound(min_w_val);
532 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
533 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
534 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
535 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
536 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
537 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
538 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
539 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
540 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
541 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
542 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
543 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
546 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
548 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
550 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
554 /******************************************************************************
556 * Will return the NIG ETS registers to init values.Except
557 * credit_upper_bound.
558 * That isn't used in this configuration (No WFQ is enabled) and will be
559 * configured acording to spec
561 ******************************************************************************/
562 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
563 const struct link_vars *vars)
565 struct bnx2x *bp = params->bp;
566 const u8 port = params->port;
567 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
568 /* Mapping between entry priority to client number (0,1,2 -debug and
569 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
570 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
571 * reset value or init tool
574 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
575 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
577 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
578 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
580 /* For strict priority entries defines the number of consecutive
581 * slots for the highest priority.
583 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
584 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
585 /* Mapping between the CREDIT_WEIGHT registers and actual client
590 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
591 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
594 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
596 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
599 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
600 * as strict. Bits 0,1,2 - debug and management entries, 3 -
601 * COS0 entry, 4 - COS1 entry.
602 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
603 * bit4 bit3 bit2 bit1 bit0
604 * MCP and debug are strict
607 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
609 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
610 /* defines which entries (clients) are subjected to WFQ arbitration */
611 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
612 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
614 /* Please notice the register address are note continuous and a
615 * for here is note appropriate.In 2 port mode port0 only COS0-5
616 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
617 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
618 * are never used for WFQ
620 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
621 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
623 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
625 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
626 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
627 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
628 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
629 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
630 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
631 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
633 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
634 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
635 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
638 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
640 /******************************************************************************
642 * Set credit upper bound for PBF.
644 ******************************************************************************/
645 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
646 const struct link_params *params,
649 struct bnx2x *bp = params->bp;
650 const u32 credit_upper_bound =
651 bnx2x_ets_get_credit_upper_bound(min_w_val);
652 const u8 port = params->port;
653 u32 base_upper_bound = 0;
656 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
657 * port mode port1 has COS0-2 that can be used for WFQ.
660 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
661 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
663 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
664 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
667 for (i = 0; i < max_cos; i++)
668 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
671 /******************************************************************************
673 * Will return the PBF ETS registers to init values.Except
674 * credit_upper_bound.
675 * That isn't used in this configuration (No WFQ is enabled) and will be
676 * configured acording to spec
678 ******************************************************************************/
679 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
681 struct bnx2x *bp = params->bp;
682 const u8 port = params->port;
683 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
688 /* Mapping between entry priority to client number 0 - COS0
689 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
690 * TODO_ETS - Should be done by reset value or init tool
693 /* 0x688 (|011|0 10|00 1|000) */
694 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
696 /* (10 1|100 |011|0 10|00 1|000) */
697 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
699 /* TODO_ETS - Should be done by reset value or init tool */
701 /* 0x688 (|011|0 10|00 1|000)*/
702 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
704 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
705 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
707 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
708 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
711 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
712 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
715 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
716 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
717 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
720 base_weight = PBF_REG_COS0_WEIGHT_P0;
721 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
723 base_weight = PBF_REG_COS0_WEIGHT_P1;
724 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
727 for (i = 0; i < max_cos; i++)
728 REG_WR(bp, base_weight + (0x4 * i), 0);
730 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
732 /******************************************************************************
734 * E3B0 disable will return basicly the values to init values.
736 ******************************************************************************/
737 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
738 const struct link_vars *vars)
740 struct bnx2x *bp = params->bp;
742 if (!CHIP_IS_E3B0(bp)) {
744 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
748 bnx2x_ets_e3b0_nig_disabled(params, vars);
750 bnx2x_ets_e3b0_pbf_disabled(params);
755 /******************************************************************************
757 * Disable will return basicly the values to init values.
759 ******************************************************************************/
760 int bnx2x_ets_disabled(struct link_params *params,
761 struct link_vars *vars)
763 struct bnx2x *bp = params->bp;
764 int bnx2x_status = 0;
766 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
767 bnx2x_ets_e2e3a0_disabled(params);
768 else if (CHIP_IS_E3B0(bp))
769 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
771 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
778 /******************************************************************************
780 * Set the COS mappimg to SP and BW until this point all the COS are not
782 ******************************************************************************/
783 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
784 const struct bnx2x_ets_params *ets_params,
785 const u8 cos_sp_bitmap,
786 const u8 cos_bw_bitmap)
788 struct bnx2x *bp = params->bp;
789 const u8 port = params->port;
790 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
791 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
792 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
793 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
795 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
796 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
798 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
799 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
801 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
802 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
803 nig_cli_subject2wfq_bitmap);
805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
806 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
807 pbf_cli_subject2wfq_bitmap);
812 /******************************************************************************
814 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
815 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
816 ******************************************************************************/
817 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
819 const u32 min_w_val_nig,
820 const u32 min_w_val_pbf,
825 u32 nig_reg_adress_crd_weight = 0;
826 u32 pbf_reg_adress_crd_weight = 0;
827 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
828 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
829 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
833 nig_reg_adress_crd_weight =
834 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
835 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
836 pbf_reg_adress_crd_weight = (port) ?
837 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
840 nig_reg_adress_crd_weight = (port) ?
841 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
843 pbf_reg_adress_crd_weight = (port) ?
844 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
847 nig_reg_adress_crd_weight = (port) ?
848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
851 pbf_reg_adress_crd_weight = (port) ?
852 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
857 nig_reg_adress_crd_weight =
858 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
859 pbf_reg_adress_crd_weight =
860 PBF_REG_COS3_WEIGHT_P0;
865 nig_reg_adress_crd_weight =
866 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
867 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
872 nig_reg_adress_crd_weight =
873 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
874 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
878 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
880 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
884 /******************************************************************************
886 * Calculate the total BW.A value of 0 isn't legal.
888 ******************************************************************************/
889 static int bnx2x_ets_e3b0_get_total_bw(
890 const struct link_params *params,
891 struct bnx2x_ets_params *ets_params,
894 struct bnx2x *bp = params->bp;
896 u8 is_bw_cos_exist = 0;
899 /* Calculate total BW requested */
900 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
901 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
903 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
904 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
906 /* This is to prevent a state when ramrods
909 ets_params->cos[cos_idx].params.bw_params.bw
913 ets_params->cos[cos_idx].params.bw_params.bw;
917 /* Check total BW is valid */
918 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
919 if (*total_bw == 0) {
921 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
925 "bnx2x_ets_E3B0_config total BW should be 100\n");
926 /* We can handle a case whre the BW isn't 100 this can happen
927 * if the TC are joined.
933 /******************************************************************************
935 * Invalidate all the sp_pri_to_cos.
937 ******************************************************************************/
938 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
941 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
942 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
944 /******************************************************************************
946 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
947 * according to sp_pri_to_cos.
949 ******************************************************************************/
950 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
951 u8 *sp_pri_to_cos, const u8 pri,
954 struct bnx2x *bp = params->bp;
955 const u8 port = params->port;
956 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
957 DCBX_E3B0_MAX_NUM_COS_PORT0;
959 if (pri >= max_num_of_cos) {
960 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
961 "parameter Illegal strict priority\n");
965 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
966 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
967 "parameter There can't be two COS's with "
968 "the same strict pri\n");
972 sp_pri_to_cos[pri] = cos_entry;
977 /******************************************************************************
979 * Returns the correct value according to COS and priority in
980 * the sp_pri_cli register.
982 ******************************************************************************/
983 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
989 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
990 (pri_set + pri_offset));
994 /******************************************************************************
996 * Returns the correct value according to COS and priority in the
997 * sp_pri_cli register for NIG.
999 ******************************************************************************/
1000 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1002 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1003 const u8 nig_cos_offset = 3;
1004 const u8 nig_pri_offset = 3;
1006 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1010 /******************************************************************************
1012 * Returns the correct value according to COS and priority in the
1013 * sp_pri_cli register for PBF.
1015 ******************************************************************************/
1016 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1018 const u8 pbf_cos_offset = 0;
1019 const u8 pbf_pri_offset = 0;
1021 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1026 /******************************************************************************
1028 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1029 * according to sp_pri_to_cos.(which COS has higher priority)
1031 ******************************************************************************/
1032 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1035 struct bnx2x *bp = params->bp;
1037 const u8 port = params->port;
1038 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1039 u64 pri_cli_nig = 0x210;
1040 u32 pri_cli_pbf = 0x0;
1043 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1044 DCBX_E3B0_MAX_NUM_COS_PORT0;
1046 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1048 /* Set all the strict priority first */
1049 for (i = 0; i < max_num_of_cos; i++) {
1050 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1051 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1053 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1054 "invalid cos entry\n");
1058 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1059 sp_pri_to_cos[i], pri_set);
1061 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1062 sp_pri_to_cos[i], pri_set);
1063 pri_bitmask = 1 << sp_pri_to_cos[i];
1064 /* COS is used remove it from bitmap.*/
1065 if (!(pri_bitmask & cos_bit_to_set)) {
1067 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1068 "invalid There can't be two COS's with"
1069 " the same strict pri\n");
1072 cos_bit_to_set &= ~pri_bitmask;
1077 /* Set all the Non strict priority i= COS*/
1078 for (i = 0; i < max_num_of_cos; i++) {
1079 pri_bitmask = 1 << i;
1080 /* Check if COS was already used for SP */
1081 if (pri_bitmask & cos_bit_to_set) {
1082 /* COS wasn't used for SP */
1083 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1086 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1088 /* COS is used remove it from bitmap.*/
1089 cos_bit_to_set &= ~pri_bitmask;
1094 if (pri_set != max_num_of_cos) {
1095 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1096 "entries were set\n");
1101 /* Only 6 usable clients*/
1102 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1105 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1107 /* Only 9 usable clients*/
1108 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1109 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1111 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1113 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1121 /******************************************************************************
1123 * Configure the COS to ETS according to BW and SP settings.
1124 ******************************************************************************/
1125 int bnx2x_ets_e3b0_config(const struct link_params *params,
1126 const struct link_vars *vars,
1127 struct bnx2x_ets_params *ets_params)
1129 struct bnx2x *bp = params->bp;
1130 int bnx2x_status = 0;
1131 const u8 port = params->port;
1133 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1134 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1135 u8 cos_bw_bitmap = 0;
1136 u8 cos_sp_bitmap = 0;
1137 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1138 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1139 DCBX_E3B0_MAX_NUM_COS_PORT0;
1142 if (!CHIP_IS_E3B0(bp)) {
1144 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1148 if ((ets_params->num_of_cos > max_num_of_cos)) {
1149 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1150 "isn't supported\n");
1154 /* Prepare sp strict priority parameters*/
1155 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1157 /* Prepare BW parameters*/
1158 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1162 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1166 /* Upper bound is set according to current link speed (min_w_val
1167 * should be the same for upper bound and COS credit val).
1169 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1170 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1173 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1174 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1175 cos_bw_bitmap |= (1 << cos_entry);
1176 /* The function also sets the BW in HW(not the mappin
1179 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1180 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1182 ets_params->cos[cos_entry].params.bw_params.bw,
1184 } else if (bnx2x_cos_state_strict ==
1185 ets_params->cos[cos_entry].state){
1186 cos_sp_bitmap |= (1 << cos_entry);
1188 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1191 ets_params->cos[cos_entry].params.sp_params.pri,
1196 "bnx2x_ets_e3b0_config cos state not valid\n");
1201 "bnx2x_ets_e3b0_config set cos bw failed\n");
1202 return bnx2x_status;
1206 /* Set SP register (which COS has higher priority) */
1207 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1212 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1213 return bnx2x_status;
1216 /* Set client mapping of BW and strict */
1217 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1222 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1223 return bnx2x_status;
1227 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1229 /* ETS disabled configuration */
1230 struct bnx2x *bp = params->bp;
1231 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1232 /* Defines which entries (clients) are subjected to WFQ arbitration
1236 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1237 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1238 * client numbers (WEIGHT_0 does not actually have to represent
1240 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1241 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1243 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1246 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1248 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1250 /* ETS mode enabled*/
1251 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1253 /* Defines the number of consecutive slots for the strict priority */
1254 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1255 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1256 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1257 * entry, 4 - COS1 entry.
1258 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1259 * bit4 bit3 bit2 bit1 bit0
1260 * MCP and debug are strict
1262 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1264 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1265 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1266 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1267 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1268 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1271 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1274 /* ETS disabled configuration*/
1275 struct bnx2x *bp = params->bp;
1276 const u32 total_bw = cos0_bw + cos1_bw;
1277 u32 cos0_credit_weight = 0;
1278 u32 cos1_credit_weight = 0;
1280 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1285 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1289 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1291 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1294 bnx2x_ets_bw_limit_common(params);
1296 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1297 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1299 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1300 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1303 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1305 /* ETS disabled configuration*/
1306 struct bnx2x *bp = params->bp;
1309 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1310 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1311 * as strict. Bits 0,1,2 - debug and management entries,
1312 * 3 - COS0 entry, 4 - COS1 entry.
1313 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1314 * bit4 bit3 bit2 bit1 bit0
1315 * MCP and debug are strict
1317 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1318 /* For strict priority entries defines the number of consecutive slots
1319 * for the highest priority.
1321 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1322 /* ETS mode disable */
1323 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1324 /* Defines the number of consecutive slots for the strict priority */
1325 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1327 /* Defines the number of consecutive slots for the strict priority */
1328 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1330 /* Mapping between entry priority to client number (0,1,2 -debug and
1331 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1333 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1334 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1335 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1337 val = (!strict_cos) ? 0x2318 : 0x22E0;
1338 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1343 /******************************************************************/
1345 /******************************************************************/
1346 static void bnx2x_update_pfc_xmac(struct link_params *params,
1347 struct link_vars *vars,
1350 struct bnx2x *bp = params->bp;
1352 u32 pause_val, pfc0_val, pfc1_val;
1354 /* XMAC base adrr */
1355 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1357 /* Initialize pause and pfc registers */
1358 pause_val = 0x18000;
1359 pfc0_val = 0xFFFF8000;
1362 /* No PFC support */
1363 if (!(params->feature_config_flags &
1364 FEATURE_CONFIG_PFC_ENABLED)) {
1366 /* RX flow control - Process pause frame in receive direction
1368 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1369 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1371 /* TX flow control - Send pause packet when buffer is full */
1372 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1373 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1374 } else {/* PFC support */
1375 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1376 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1377 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1378 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1379 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1380 /* Write pause and PFC registers */
1381 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1382 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1383 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1384 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1388 /* Write pause and PFC registers */
1389 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1390 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1391 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1394 /* Set MAC address for source TX Pause/PFC frames */
1395 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1396 ((params->mac_addr[2] << 24) |
1397 (params->mac_addr[3] << 16) |
1398 (params->mac_addr[4] << 8) |
1399 (params->mac_addr[5])));
1400 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1401 ((params->mac_addr[0] << 8) |
1402 (params->mac_addr[1])));
1407 /******************************************************************/
1408 /* MAC/PBF section */
1409 /******************************************************************/
1410 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1413 u32 new_mode, cur_mode;
1415 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1416 * (a value of 49==0x31) and make sure that the AUTO poll is off
1418 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1420 if (USES_WARPCORE(bp))
1421 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1423 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1425 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1426 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1429 new_mode = cur_mode &
1430 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1431 new_mode |= clc_cnt;
1432 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1434 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1435 cur_mode, new_mode);
1436 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1440 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1441 struct link_params *params)
1444 /* Set mdio clock per phy */
1445 for (phy_index = INT_PHY; phy_index < params->num_phys;
1447 bnx2x_set_mdio_clk(bp, params->chip_id,
1448 params->phy[phy_index].mdio_ctrl);
1451 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1453 u32 port4mode_ovwr_val;
1454 /* Check 4-port override enabled */
1455 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1456 if (port4mode_ovwr_val & (1<<0)) {
1457 /* Return 4-port mode override value */
1458 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1460 /* Return 4-port mode from input pin */
1461 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1464 static void bnx2x_emac_init(struct link_params *params,
1465 struct link_vars *vars)
1467 /* reset and unreset the emac core */
1468 struct bnx2x *bp = params->bp;
1469 u8 port = params->port;
1470 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1474 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1475 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1480 /* init emac - use read-modify-write */
1481 /* self clear reset */
1482 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1483 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1487 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1488 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1490 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1494 } while (val & EMAC_MODE_RESET);
1496 bnx2x_set_mdio_emac_per_phy(bp, params);
1497 /* Set mac address */
1498 val = ((params->mac_addr[0] << 8) |
1499 params->mac_addr[1]);
1500 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1502 val = ((params->mac_addr[2] << 24) |
1503 (params->mac_addr[3] << 16) |
1504 (params->mac_addr[4] << 8) |
1505 params->mac_addr[5]);
1506 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1509 static void bnx2x_set_xumac_nig(struct link_params *params,
1513 struct bnx2x *bp = params->bp;
1515 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1517 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1519 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1520 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1523 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1525 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1527 struct bnx2x *bp = params->bp;
1528 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1529 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1531 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1533 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1534 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1536 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1537 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1538 /* Disable RX and TX */
1539 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1542 static void bnx2x_umac_enable(struct link_params *params,
1543 struct link_vars *vars, u8 lb)
1546 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1547 struct bnx2x *bp = params->bp;
1549 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1550 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1551 usleep_range(1000, 2000);
1553 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1554 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1556 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1558 /* This register opens the gate for the UMAC despite its name */
1559 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1561 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1562 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1563 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1564 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1565 switch (vars->line_speed) {
1579 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1583 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1584 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1586 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1587 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1589 if (vars->duplex == DUPLEX_HALF)
1590 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1592 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1595 /* Configure UMAC for EEE */
1596 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1597 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1598 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1599 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1600 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1602 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1605 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1606 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1607 ((params->mac_addr[2] << 24) |
1608 (params->mac_addr[3] << 16) |
1609 (params->mac_addr[4] << 8) |
1610 (params->mac_addr[5])));
1611 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1612 ((params->mac_addr[0] << 8) |
1613 (params->mac_addr[1])));
1615 /* Enable RX and TX */
1616 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1617 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1618 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1619 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1622 /* Remove SW Reset */
1623 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1625 /* Check loopback mode */
1627 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1628 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1630 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1631 * length used by the MAC receive logic to check frames.
1633 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1634 bnx2x_set_xumac_nig(params,
1635 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1636 vars->mac_type = MAC_TYPE_UMAC;
1640 /* Define the XMAC mode */
1641 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1643 struct bnx2x *bp = params->bp;
1644 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1646 /* In 4-port mode, need to set the mode only once, so if XMAC is
1647 * already out of reset, it means the mode has already been set,
1648 * and it must not* reset the XMAC again, since it controls both
1652 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1653 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1654 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1656 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1657 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1659 "XMAC already out of reset in 4-port mode\n");
1664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1665 MISC_REGISTERS_RESET_REG_2_XMAC);
1666 usleep_range(1000, 2000);
1668 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1669 MISC_REGISTERS_RESET_REG_2_XMAC);
1671 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1673 /* Set the number of ports on the system side to up to 2 */
1674 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1676 /* Set the number of ports on the Warp Core to 10G */
1677 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1679 /* Set the number of ports on the system side to 1 */
1680 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1681 if (max_speed == SPEED_10000) {
1683 "Init XMAC to 10G x 1 port per path\n");
1684 /* Set the number of ports on the Warp Core to 10G */
1685 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1688 "Init XMAC to 20G x 2 ports per path\n");
1689 /* Set the number of ports on the Warp Core to 20G */
1690 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1695 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1696 usleep_range(1000, 2000);
1698 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1699 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1703 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1705 u8 port = params->port;
1706 struct bnx2x *bp = params->bp;
1707 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1710 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1711 MISC_REGISTERS_RESET_REG_2_XMAC) {
1712 /* Send an indication to change the state in the NIG back to XON
1713 * Clearing this bit enables the next set of this bit to get
1716 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1717 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1718 (pfc_ctrl & ~(1<<1)));
1719 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1720 (pfc_ctrl | (1<<1)));
1721 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1722 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1724 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1726 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1727 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1731 static int bnx2x_xmac_enable(struct link_params *params,
1732 struct link_vars *vars, u8 lb)
1735 struct bnx2x *bp = params->bp;
1736 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1738 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1740 bnx2x_xmac_init(params, vars->line_speed);
1742 /* This register determines on which events the MAC will assert
1743 * error on the i/f to the NIG along w/ EOP.
1746 /* This register tells the NIG whether to send traffic to UMAC
1749 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1751 /* When XMAC is in XLGMII mode, disable sending idles for fault
1754 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1755 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1756 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1757 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1758 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1759 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1760 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1761 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1763 /* Set Max packet size */
1764 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1766 /* CRC append for Tx packets */
1767 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1770 bnx2x_update_pfc_xmac(params, vars, 0);
1772 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1773 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1774 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1775 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1780 /* Enable TX and RX */
1781 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1783 /* Set MAC in XLGMII mode for dual-mode */
1784 if ((vars->line_speed == SPEED_20000) &&
1785 (params->phy[INT_PHY].supported &
1786 SUPPORTED_20000baseKR2_Full))
1787 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1789 /* Check loopback mode */
1791 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1792 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1793 bnx2x_set_xumac_nig(params,
1794 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1796 vars->mac_type = MAC_TYPE_XMAC;
1801 static int bnx2x_emac_enable(struct link_params *params,
1802 struct link_vars *vars, u8 lb)
1804 struct bnx2x *bp = params->bp;
1805 u8 port = params->port;
1806 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1809 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1812 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1813 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1815 /* enable emac and not bmac */
1816 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1819 if (vars->phy_flags & PHY_XGXS_FLAG) {
1820 u32 ser_lane = ((params->lane_config &
1821 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1822 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1824 DP(NETIF_MSG_LINK, "XGXS\n");
1825 /* select the master lanes (out of 0-3) */
1826 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1828 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1830 } else { /* SerDes */
1831 DP(NETIF_MSG_LINK, "SerDes\n");
1833 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1836 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1837 EMAC_RX_MODE_RESET);
1838 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1839 EMAC_TX_MODE_RESET);
1841 /* pause enable/disable */
1842 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1843 EMAC_RX_MODE_FLOW_EN);
1845 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1846 (EMAC_TX_MODE_EXT_PAUSE_EN |
1847 EMAC_TX_MODE_FLOW_EN));
1848 if (!(params->feature_config_flags &
1849 FEATURE_CONFIG_PFC_ENABLED)) {
1850 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1851 bnx2x_bits_en(bp, emac_base +
1852 EMAC_REG_EMAC_RX_MODE,
1853 EMAC_RX_MODE_FLOW_EN);
1855 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1856 bnx2x_bits_en(bp, emac_base +
1857 EMAC_REG_EMAC_TX_MODE,
1858 (EMAC_TX_MODE_EXT_PAUSE_EN |
1859 EMAC_TX_MODE_FLOW_EN));
1861 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1862 EMAC_TX_MODE_FLOW_EN);
1864 /* KEEP_VLAN_TAG, promiscuous */
1865 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1866 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1868 /* Setting this bit causes MAC control frames (except for pause
1869 * frames) to be passed on for processing. This setting has no
1870 * affect on the operation of the pause frames. This bit effects
1871 * all packets regardless of RX Parser packet sorting logic.
1872 * Turn the PFC off to make sure we are in Xon state before
1875 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1876 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1877 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1878 /* Enable PFC again */
1879 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1880 EMAC_REG_RX_PFC_MODE_RX_EN |
1881 EMAC_REG_RX_PFC_MODE_TX_EN |
1882 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1884 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1886 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1888 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1889 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1891 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1894 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1899 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1902 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1904 /* Enable emac for jumbo packets */
1905 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1906 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1907 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1910 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1912 /* Disable the NIG in/out to the bmac */
1913 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1914 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1915 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1917 /* Enable the NIG in/out to the emac */
1918 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1920 if ((params->feature_config_flags &
1921 FEATURE_CONFIG_PFC_ENABLED) ||
1922 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1925 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1926 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1928 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1930 vars->mac_type = MAC_TYPE_EMAC;
1934 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1935 struct link_vars *vars)
1938 struct bnx2x *bp = params->bp;
1939 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1940 NIG_REG_INGRESS_BMAC0_MEM;
1943 if ((!(params->feature_config_flags &
1944 FEATURE_CONFIG_PFC_ENABLED)) &&
1945 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1946 /* Enable BigMAC to react on received Pause packets */
1950 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1954 if (!(params->feature_config_flags &
1955 FEATURE_CONFIG_PFC_ENABLED) &&
1956 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1960 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1963 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1964 struct link_vars *vars,
1967 /* Set rx control: Strip CRC and enable BigMAC to relay
1968 * control packets to the system as well
1971 struct bnx2x *bp = params->bp;
1972 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1973 NIG_REG_INGRESS_BMAC0_MEM;
1976 if ((!(params->feature_config_flags &
1977 FEATURE_CONFIG_PFC_ENABLED)) &&
1978 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1979 /* Enable BigMAC to react on received Pause packets */
1983 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1988 if (!(params->feature_config_flags &
1989 FEATURE_CONFIG_PFC_ENABLED) &&
1990 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1994 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1996 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1997 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1998 /* Enable PFC RX & TX & STATS and set 8 COS */
2000 wb_data[0] |= (1<<0); /* RX */
2001 wb_data[0] |= (1<<1); /* TX */
2002 wb_data[0] |= (1<<2); /* Force initial Xon */
2003 wb_data[0] |= (1<<3); /* 8 cos */
2004 wb_data[0] |= (1<<5); /* STATS */
2006 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2008 /* Clear the force Xon */
2009 wb_data[0] &= ~(1<<2);
2011 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2012 /* Disable PFC RX & TX & STATS and set 8 COS */
2017 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2019 /* Set Time (based unit is 512 bit time) between automatic
2020 * re-sending of PP packets amd enable automatic re-send of
2021 * Per-Priroity Packet as long as pp_gen is asserted and
2022 * pp_disable is low.
2025 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2026 val |= (1<<16); /* enable automatic re-send */
2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2034 val = 0x3; /* Enable RX and TX */
2036 val |= 0x4; /* Local loopback */
2037 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2039 /* When PFC enabled, Pass pause frames towards the NIG. */
2040 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2041 val |= ((1<<6)|(1<<5));
2045 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2048 /******************************************************************************
2050 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2051 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2052 ******************************************************************************/
2053 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2055 u32 priority_mask, u8 port)
2057 u32 nig_reg_rx_priority_mask_add = 0;
2059 switch (cos_entry) {
2061 nig_reg_rx_priority_mask_add = (port) ?
2062 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2063 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2066 nig_reg_rx_priority_mask_add = (port) ?
2067 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2068 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2071 nig_reg_rx_priority_mask_add = (port) ?
2072 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2073 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2078 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2083 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2088 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2092 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2096 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2098 struct bnx2x *bp = params->bp;
2100 REG_WR(bp, params->shmem_base +
2101 offsetof(struct shmem_region,
2102 port_mb[params->port].link_status), link_status);
2105 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2107 struct bnx2x *bp = params->bp;
2109 if (SHMEM2_HAS(bp, link_attr_sync))
2110 REG_WR(bp, params->shmem2_base +
2111 offsetof(struct shmem2_region,
2112 link_attr_sync[params->port]), link_attr);
2115 static void bnx2x_update_pfc_nig(struct link_params *params,
2116 struct link_vars *vars,
2117 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2119 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2120 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2121 u32 pkt_priority_to_cos = 0;
2122 struct bnx2x *bp = params->bp;
2123 u8 port = params->port;
2125 int set_pfc = params->feature_config_flags &
2126 FEATURE_CONFIG_PFC_ENABLED;
2127 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2129 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2130 * MAC control frames (that are not pause packets)
2131 * will be forwarded to the XCM.
2133 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2134 NIG_REG_LLH0_XCM_MASK);
2135 /* NIG params will override non PFC params, since it's possible to
2136 * do transition from PFC to SAFC
2146 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2147 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2152 llfc_out_en = nig_params->llfc_out_en;
2153 llfc_enable = nig_params->llfc_enable;
2154 pause_enable = nig_params->pause_enable;
2155 } else /* Default non PFC mode - PAUSE */
2158 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2159 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2164 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2165 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2166 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2167 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2168 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2169 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2170 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2171 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2173 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2174 NIG_REG_PPP_ENABLE_0, ppp_enable);
2176 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2177 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2179 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2180 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2182 /* Output enable for RX_XCM # IF */
2183 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2184 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2186 /* HW PFC TX enable */
2187 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2188 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2192 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2194 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2195 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2196 nig_params->rx_cos_priority_mask[i], port);
2198 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2199 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2200 nig_params->llfc_high_priority_classes);
2202 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2203 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2204 nig_params->llfc_low_priority_classes);
2206 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2207 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2208 pkt_priority_to_cos);
2211 int bnx2x_update_pfc(struct link_params *params,
2212 struct link_vars *vars,
2213 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2215 /* The PFC and pause are orthogonal to one another, meaning when
2216 * PFC is enabled, the pause are disabled, and when PFC is
2217 * disabled, pause are set according to the pause result.
2220 struct bnx2x *bp = params->bp;
2221 int bnx2x_status = 0;
2222 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2224 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2225 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2227 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2229 bnx2x_update_mng(params, vars->link_status);
2231 /* Update NIG params */
2232 bnx2x_update_pfc_nig(params, vars, pfc_params);
2235 return bnx2x_status;
2237 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2239 if (CHIP_IS_E3(bp)) {
2240 if (vars->mac_type == MAC_TYPE_XMAC)
2241 bnx2x_update_pfc_xmac(params, vars, 0);
2243 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2245 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2247 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2248 bnx2x_emac_enable(params, vars, 0);
2249 return bnx2x_status;
2252 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2254 bnx2x_update_pfc_bmac1(params, vars);
2257 if ((params->feature_config_flags &
2258 FEATURE_CONFIG_PFC_ENABLED) ||
2259 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2261 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2263 return bnx2x_status;
2266 static int bnx2x_bmac1_enable(struct link_params *params,
2267 struct link_vars *vars,
2270 struct bnx2x *bp = params->bp;
2271 u8 port = params->port;
2272 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2273 NIG_REG_INGRESS_BMAC0_MEM;
2277 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2282 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2286 wb_data[0] = ((params->mac_addr[2] << 24) |
2287 (params->mac_addr[3] << 16) |
2288 (params->mac_addr[4] << 8) |
2289 params->mac_addr[5]);
2290 wb_data[1] = ((params->mac_addr[0] << 8) |
2291 params->mac_addr[1]);
2292 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2298 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2302 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2305 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2307 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2309 bnx2x_update_pfc_bmac1(params, vars);
2312 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2314 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2316 /* Set cnt max size */
2317 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2319 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2321 /* Configure SAFC */
2322 wb_data[0] = 0x1000200;
2324 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2330 static int bnx2x_bmac2_enable(struct link_params *params,
2331 struct link_vars *vars,
2334 struct bnx2x *bp = params->bp;
2335 u8 port = params->port;
2336 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2337 NIG_REG_INGRESS_BMAC0_MEM;
2340 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2344 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2347 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2350 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2356 wb_data[0] = ((params->mac_addr[2] << 24) |
2357 (params->mac_addr[3] << 16) |
2358 (params->mac_addr[4] << 8) |
2359 params->mac_addr[5]);
2360 wb_data[1] = ((params->mac_addr[0] << 8) |
2361 params->mac_addr[1]);
2362 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2367 /* Configure SAFC */
2368 wb_data[0] = 0x1000200;
2370 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2375 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2377 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2381 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2383 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2385 /* Set cnt max size */
2386 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2388 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2390 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2395 static int bnx2x_bmac_enable(struct link_params *params,
2396 struct link_vars *vars,
2397 u8 is_lb, u8 reset_bmac)
2400 u8 port = params->port;
2401 struct bnx2x *bp = params->bp;
2403 /* Reset and unreset the BigMac */
2405 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2406 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2407 usleep_range(1000, 2000);
2410 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2411 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2413 /* Enable access for bmac registers */
2414 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2416 /* Enable BMAC according to BMAC type*/
2418 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2420 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2421 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2422 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2423 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2425 if ((params->feature_config_flags &
2426 FEATURE_CONFIG_PFC_ENABLED) ||
2427 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2429 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2430 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2431 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2432 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2433 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2434 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2436 vars->mac_type = MAC_TYPE_BMAC;
2440 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2442 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2443 NIG_REG_INGRESS_BMAC0_MEM;
2445 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2448 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2450 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2451 /* Only if the bmac is out of reset */
2452 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2453 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2455 /* Clear Rx Enable bit in BMAC_CONTROL register */
2456 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2458 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2460 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2461 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2462 usleep_range(1000, 2000);
2466 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2469 struct bnx2x *bp = params->bp;
2470 u8 port = params->port;
2475 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2477 /* Wait for init credit */
2478 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2479 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2480 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2482 while ((init_crd != crd) && count) {
2483 usleep_range(5000, 10000);
2484 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2487 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2488 if (init_crd != crd) {
2489 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2494 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2495 line_speed == SPEED_10 ||
2496 line_speed == SPEED_100 ||
2497 line_speed == SPEED_1000 ||
2498 line_speed == SPEED_2500) {
2499 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2500 /* Update threshold */
2501 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2502 /* Update init credit */
2503 init_crd = 778; /* (800-18-4) */
2506 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2508 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2509 /* Update threshold */
2510 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2511 /* Update init credit */
2512 switch (line_speed) {
2514 init_crd = thresh + 553 - 22;
2517 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2522 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2523 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2524 line_speed, init_crd);
2526 /* Probe the credit changes */
2527 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2528 usleep_range(5000, 10000);
2529 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2532 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2537 * bnx2x_get_emac_base - retrive emac base address
2539 * @bp: driver handle
2540 * @mdc_mdio_access: access type
2543 * This function selects the MDC/MDIO access (through emac0 or
2544 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2545 * phy has a default access mode, which could also be overridden
2546 * by nvram configuration. This parameter, whether this is the
2547 * default phy configuration, or the nvram overrun
2548 * configuration, is passed here as mdc_mdio_access and selects
2549 * the emac_base for the CL45 read/writes operations
2551 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2552 u32 mdc_mdio_access, u8 port)
2555 switch (mdc_mdio_access) {
2556 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2558 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2559 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2560 emac_base = GRCBASE_EMAC1;
2562 emac_base = GRCBASE_EMAC0;
2564 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2565 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2566 emac_base = GRCBASE_EMAC0;
2568 emac_base = GRCBASE_EMAC1;
2570 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2571 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2573 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2574 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2583 /******************************************************************/
2584 /* CL22 access functions */
2585 /******************************************************************/
2586 static int bnx2x_cl22_write(struct bnx2x *bp,
2587 struct bnx2x_phy *phy,
2593 /* Switch to CL22 */
2594 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2595 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2596 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2599 tmp = ((phy->addr << 21) | (reg << 16) | val |
2600 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2601 EMAC_MDIO_COMM_START_BUSY);
2602 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2604 for (i = 0; i < 50; i++) {
2607 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2608 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2613 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2614 DP(NETIF_MSG_LINK, "write phy register failed\n");
2617 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2621 static int bnx2x_cl22_read(struct bnx2x *bp,
2622 struct bnx2x_phy *phy,
2623 u16 reg, u16 *ret_val)
2629 /* Switch to CL22 */
2630 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2631 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2632 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2635 val = ((phy->addr << 21) | (reg << 16) |
2636 EMAC_MDIO_COMM_COMMAND_READ_22 |
2637 EMAC_MDIO_COMM_START_BUSY);
2638 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2640 for (i = 0; i < 50; i++) {
2643 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2644 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2645 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2650 if (val & EMAC_MDIO_COMM_START_BUSY) {
2651 DP(NETIF_MSG_LINK, "read phy register failed\n");
2656 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2660 /******************************************************************/
2661 /* CL45 access functions */
2662 /******************************************************************/
2663 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2664 u8 devad, u16 reg, u16 *ret_val)
2670 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2671 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2672 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2673 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2676 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2677 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2678 EMAC_MDIO_STATUS_10MB);
2680 val = ((phy->addr << 21) | (devad << 16) | reg |
2681 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2682 EMAC_MDIO_COMM_START_BUSY);
2683 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2685 for (i = 0; i < 50; i++) {
2688 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2689 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2694 if (val & EMAC_MDIO_COMM_START_BUSY) {
2695 DP(NETIF_MSG_LINK, "read phy register failed\n");
2696 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2701 val = ((phy->addr << 21) | (devad << 16) |
2702 EMAC_MDIO_COMM_COMMAND_READ_45 |
2703 EMAC_MDIO_COMM_START_BUSY);
2704 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2706 for (i = 0; i < 50; i++) {
2709 val = REG_RD(bp, phy->mdio_ctrl +
2710 EMAC_REG_EMAC_MDIO_COMM);
2711 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2712 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2716 if (val & EMAC_MDIO_COMM_START_BUSY) {
2717 DP(NETIF_MSG_LINK, "read phy register failed\n");
2718 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2723 /* Work around for E3 A0 */
2724 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2725 phy->flags ^= FLAGS_DUMMY_READ;
2726 if (phy->flags & FLAGS_DUMMY_READ) {
2728 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2732 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2733 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2734 EMAC_MDIO_STATUS_10MB);
2738 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2739 u8 devad, u16 reg, u16 val)
2745 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2746 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2747 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2748 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2751 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2752 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2753 EMAC_MDIO_STATUS_10MB);
2756 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2757 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2758 EMAC_MDIO_COMM_START_BUSY);
2759 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2761 for (i = 0; i < 50; i++) {
2764 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2765 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2770 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2771 DP(NETIF_MSG_LINK, "write phy register failed\n");
2772 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2776 tmp = ((phy->addr << 21) | (devad << 16) | val |
2777 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2778 EMAC_MDIO_COMM_START_BUSY);
2779 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2781 for (i = 0; i < 50; i++) {
2784 tmp = REG_RD(bp, phy->mdio_ctrl +
2785 EMAC_REG_EMAC_MDIO_COMM);
2786 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2791 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2792 DP(NETIF_MSG_LINK, "write phy register failed\n");
2793 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2797 /* Work around for E3 A0 */
2798 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2799 phy->flags ^= FLAGS_DUMMY_READ;
2800 if (phy->flags & FLAGS_DUMMY_READ) {
2802 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2805 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2806 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2807 EMAC_MDIO_STATUS_10MB);
2811 /******************************************************************/
2813 /******************************************************************/
2814 static u8 bnx2x_eee_has_cap(struct link_params *params)
2816 struct bnx2x *bp = params->bp;
2818 if (REG_RD(bp, params->shmem2_base) <=
2819 offsetof(struct shmem2_region, eee_status[params->port]))
2825 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2827 switch (nvram_mode) {
2828 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2829 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2831 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2832 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2834 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2835 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2845 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2847 switch (idle_timer) {
2848 case EEE_MODE_NVRAM_BALANCED_TIME:
2849 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2851 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2852 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2854 case EEE_MODE_NVRAM_LATENCY_TIME:
2855 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2858 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2865 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2867 u32 eee_mode, eee_idle;
2868 struct bnx2x *bp = params->bp;
2870 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2871 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2872 /* time value in eee_mode --> used directly*/
2873 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2875 /* hsi value in eee_mode --> time */
2876 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2877 EEE_MODE_NVRAM_MASK,
2882 /* hsi values in nvram --> time*/
2883 eee_mode = ((REG_RD(bp, params->shmem_base +
2884 offsetof(struct shmem_region, dev_info.
2885 port_feature_config[params->port].
2887 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2888 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2890 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2897 static int bnx2x_eee_set_timers(struct link_params *params,
2898 struct link_vars *vars)
2900 u32 eee_idle = 0, eee_mode;
2901 struct bnx2x *bp = params->bp;
2903 eee_idle = bnx2x_eee_calc_timer(params);
2906 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2908 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2909 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2910 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2911 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2915 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2916 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2917 /* eee_idle in 1u --> eee_status in 16u */
2919 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2920 SHMEM_EEE_TIME_OUTPUT_BIT;
2922 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2924 vars->eee_status |= eee_mode;
2930 static int bnx2x_eee_initial_config(struct link_params *params,
2931 struct link_vars *vars, u8 mode)
2933 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2935 /* Propogate params' bits --> vars (for migration exposure) */
2936 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2937 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2939 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2941 if (params->eee_mode & EEE_MODE_ADV_LPI)
2942 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2944 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2946 return bnx2x_eee_set_timers(params, vars);
2949 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2950 struct link_params *params,
2951 struct link_vars *vars)
2953 struct bnx2x *bp = params->bp;
2955 /* Make Certain LPI is disabled */
2956 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2958 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2960 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2965 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2966 struct link_params *params,
2967 struct link_vars *vars, u8 modes)
2969 struct bnx2x *bp = params->bp;
2972 /* Mask events preventing LPI generation */
2973 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2975 if (modes & SHMEM_EEE_10G_ADV) {
2976 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2979 if (modes & SHMEM_EEE_1G_ADV) {
2980 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2984 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2986 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2987 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2992 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2994 struct bnx2x *bp = params->bp;
2996 if (bnx2x_eee_has_cap(params))
2997 REG_WR(bp, params->shmem2_base +
2998 offsetof(struct shmem2_region,
2999 eee_status[params->port]), eee_status);
3002 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3003 struct link_params *params,
3004 struct link_vars *vars)
3006 struct bnx2x *bp = params->bp;
3007 u16 adv = 0, lp = 0;
3011 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3012 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3015 lp_adv |= SHMEM_EEE_100M_ADV;
3017 if (vars->line_speed == SPEED_100)
3019 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3023 lp_adv |= SHMEM_EEE_1G_ADV;
3025 if (vars->line_speed == SPEED_1000)
3027 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3031 lp_adv |= SHMEM_EEE_10G_ADV;
3033 if (vars->line_speed == SPEED_10000)
3035 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3039 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3040 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3043 DP(NETIF_MSG_LINK, "EEE is active\n");
3044 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3049 /******************************************************************/
3050 /* BSC access functions from E3 */
3051 /******************************************************************/
3052 static void bnx2x_bsc_module_sel(struct link_params *params)
3055 u32 board_cfg, sfp_ctrl;
3056 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3057 struct bnx2x *bp = params->bp;
3058 u8 port = params->port;
3059 /* Read I2C output PINs */
3060 board_cfg = REG_RD(bp, params->shmem_base +
3061 offsetof(struct shmem_region,
3062 dev_info.shared_hw_config.board));
3063 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3064 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3065 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3067 /* Read I2C output value */
3068 sfp_ctrl = REG_RD(bp, params->shmem_base +
3069 offsetof(struct shmem_region,
3070 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3071 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3072 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3073 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3074 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3075 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3078 static int bnx2x_bsc_read(struct link_params *params,
3089 if (xfer_cnt > 16) {
3090 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3094 bnx2x_bsc_module_sel(params);
3096 xfer_cnt = 16 - lc_addr;
3098 /* Enable the engine */
3099 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3100 val |= MCPR_IMC_COMMAND_ENABLE;
3101 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3103 /* Program slave device ID */
3104 val = (sl_devid << 16) | sl_addr;
3105 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3107 /* Start xfer with 0 byte to update the address pointer ???*/
3108 val = (MCPR_IMC_COMMAND_ENABLE) |
3109 (MCPR_IMC_COMMAND_WRITE_OP <<
3110 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3111 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3112 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3114 /* Poll for completion */
3116 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3117 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3119 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3121 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3130 /* Start xfer with read op */
3131 val = (MCPR_IMC_COMMAND_ENABLE) |
3132 (MCPR_IMC_COMMAND_READ_OP <<
3133 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3134 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3136 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3138 /* Poll for completion */
3140 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3141 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3143 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3145 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3153 for (i = (lc_addr >> 2); i < 4; i++) {
3154 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3156 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3157 ((data_array[i] & 0x0000ff00) << 8) |
3158 ((data_array[i] & 0x00ff0000) >> 8) |
3159 ((data_array[i] & 0xff000000) >> 24);
3165 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3166 u8 devad, u16 reg, u16 or_val)
3169 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3170 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3173 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3174 struct bnx2x_phy *phy,
3175 u8 devad, u16 reg, u16 and_val)
3178 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3179 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3182 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3183 u8 devad, u16 reg, u16 *ret_val)
3186 /* Probe for the phy according to the given phy_addr, and execute
3187 * the read request on it
3189 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3190 if (params->phy[phy_index].addr == phy_addr) {
3191 return bnx2x_cl45_read(params->bp,
3192 ¶ms->phy[phy_index], devad,
3199 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3200 u8 devad, u16 reg, u16 val)
3203 /* Probe for the phy according to the given phy_addr, and execute
3204 * the write request on it
3206 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3207 if (params->phy[phy_index].addr == phy_addr) {
3208 return bnx2x_cl45_write(params->bp,
3209 ¶ms->phy[phy_index], devad,
3215 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3216 struct link_params *params)
3219 struct bnx2x *bp = params->bp;
3220 u32 path_swap, path_swap_ovr;
3224 port = params->port;
3226 if (bnx2x_is_4_port_mode(bp)) {
3227 u32 port_swap, port_swap_ovr;
3229 /* Figure out path swap value */
3230 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3231 if (path_swap_ovr & 0x1)
3232 path_swap = (path_swap_ovr & 0x2);
3234 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3239 /* Figure out port swap value */
3240 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3241 if (port_swap_ovr & 0x1)
3242 port_swap = (port_swap_ovr & 0x2);
3244 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3249 lane = (port<<1) + path;
3250 } else { /* Two port mode - no port swap */
3252 /* Figure out path swap value */
3254 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3255 if (path_swap_ovr & 0x1) {
3256 path_swap = (path_swap_ovr & 0x2);
3259 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3269 static void bnx2x_set_aer_mmd(struct link_params *params,
3270 struct bnx2x_phy *phy)
3273 u16 offset, aer_val;
3274 struct bnx2x *bp = params->bp;
3275 ser_lane = ((params->lane_config &
3276 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3277 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3279 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3280 (phy->addr + ser_lane) : 0;
3282 if (USES_WARPCORE(bp)) {
3283 aer_val = bnx2x_get_warpcore_lane(phy, params);
3284 /* In Dual-lane mode, two lanes are joined together,
3285 * so in order to configure them, the AER broadcast method is
3287 * 0x200 is the broadcast address for lanes 0,1
3288 * 0x201 is the broadcast address for lanes 2,3
3290 if (phy->flags & FLAGS_WC_DUAL_MODE)
3291 aer_val = (aer_val >> 1) | 0x200;
3292 } else if (CHIP_IS_E2(bp))
3293 aer_val = 0x3800 + offset - 1;
3295 aer_val = 0x3800 + offset;
3297 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3298 MDIO_AER_BLOCK_AER_REG, aer_val);
3302 /******************************************************************/
3303 /* Internal phy section */
3304 /******************************************************************/
3306 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3308 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3311 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3312 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3314 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3320 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3324 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3326 val = SERDES_RESET_BITS << (port*16);
3328 /* Reset and unreset the SerDes/XGXS */
3329 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3331 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3333 bnx2x_set_serdes_access(bp, port);
3335 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3336 DEFAULT_PHY_DEV_ADDR);
3339 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3340 struct link_params *params,
3343 struct bnx2x *bp = params->bp;
3346 /* Set correct devad */
3347 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3348 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3354 static void bnx2x_xgxs_deassert(struct link_params *params)
3356 struct bnx2x *bp = params->bp;
3359 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3360 port = params->port;
3362 val = XGXS_RESET_BITS << (port*16);
3364 /* Reset and unreset the SerDes/XGXS */
3365 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3367 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3368 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params,
3372 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3373 struct link_params *params, u16 *ieee_fc)
3375 struct bnx2x *bp = params->bp;
3376 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3377 /* Resolve pause mode and advertisement Please refer to Table
3378 * 28B-3 of the 802.3ab-1999 spec
3381 switch (phy->req_flow_ctrl) {
3382 case BNX2X_FLOW_CTRL_AUTO:
3383 switch (params->req_fc_auto_adv) {
3384 case BNX2X_FLOW_CTRL_BOTH:
3385 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3387 case BNX2X_FLOW_CTRL_RX:
3388 case BNX2X_FLOW_CTRL_TX:
3390 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3396 case BNX2X_FLOW_CTRL_TX:
3397 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3400 case BNX2X_FLOW_CTRL_RX:
3401 case BNX2X_FLOW_CTRL_BOTH:
3402 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405 case BNX2X_FLOW_CTRL_NONE:
3407 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3410 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3413 static void set_phy_vars(struct link_params *params,
3414 struct link_vars *vars)
3416 struct bnx2x *bp = params->bp;
3417 u8 actual_phy_idx, phy_index, link_cfg_idx;
3418 u8 phy_config_swapped = params->multi_phy_config &
3419 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3420 for (phy_index = INT_PHY; phy_index < params->num_phys;
3422 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3423 actual_phy_idx = phy_index;
3424 if (phy_config_swapped) {
3425 if (phy_index == EXT_PHY1)
3426 actual_phy_idx = EXT_PHY2;
3427 else if (phy_index == EXT_PHY2)
3428 actual_phy_idx = EXT_PHY1;
3430 params->phy[actual_phy_idx].req_flow_ctrl =
3431 params->req_flow_ctrl[link_cfg_idx];
3433 params->phy[actual_phy_idx].req_line_speed =
3434 params->req_line_speed[link_cfg_idx];
3436 params->phy[actual_phy_idx].speed_cap_mask =
3437 params->speed_cap_mask[link_cfg_idx];
3439 params->phy[actual_phy_idx].req_duplex =
3440 params->req_duplex[link_cfg_idx];
3442 if (params->req_line_speed[link_cfg_idx] ==
3444 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3446 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3447 " speed_cap_mask %x\n",
3448 params->phy[actual_phy_idx].req_flow_ctrl,
3449 params->phy[actual_phy_idx].req_line_speed,
3450 params->phy[actual_phy_idx].speed_cap_mask);
3454 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3455 struct bnx2x_phy *phy,
3456 struct link_vars *vars)
3459 struct bnx2x *bp = params->bp;
3460 /* Read modify write pause advertizing */
3461 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3463 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3465 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3466 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3467 if ((vars->ieee_fc &
3468 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3469 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3470 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3472 if ((vars->ieee_fc &
3473 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3474 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3475 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3477 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3478 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3481 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3483 switch (pause_result) { /* ASYM P ASYM P */
3484 case 0xb: /* 1 0 1 1 */
3485 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3488 case 0xe: /* 1 1 1 0 */
3489 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3492 case 0x5: /* 0 1 0 1 */
3493 case 0x7: /* 0 1 1 1 */
3494 case 0xd: /* 1 1 0 1 */
3495 case 0xf: /* 1 1 1 1 */
3496 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3502 if (pause_result & (1<<0))
3503 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3504 if (pause_result & (1<<1))
3505 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3509 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3510 struct link_params *params,
3511 struct link_vars *vars)
3513 u16 ld_pause; /* local */
3514 u16 lp_pause; /* link partner */
3516 struct bnx2x *bp = params->bp;
3517 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3518 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3519 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3520 } else if (CHIP_IS_E3(bp) &&
3521 SINGLE_MEDIA_DIRECT(params)) {
3522 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3523 u16 gp_status, gp_mask;
3524 bnx2x_cl45_read(bp, phy,
3525 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3527 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3528 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3530 if ((gp_status & gp_mask) == gp_mask) {
3531 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3532 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3533 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3534 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3536 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3537 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3538 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3539 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3540 ld_pause = ((ld_pause &
3541 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3543 lp_pause = ((lp_pause &
3544 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3548 bnx2x_cl45_read(bp, phy,
3550 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3551 bnx2x_cl45_read(bp, phy,
3553 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3555 pause_result = (ld_pause &
3556 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3557 pause_result |= (lp_pause &
3558 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3559 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3560 bnx2x_pause_resolve(vars, pause_result);
3564 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3565 struct link_params *params,
3566 struct link_vars *vars)
3569 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3570 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3571 /* Update the advertised flow-controled of LD/LP in AN */
3572 if (phy->req_line_speed == SPEED_AUTO_NEG)
3573 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3574 /* But set the flow-control result as the requested one */
3575 vars->flow_ctrl = phy->req_flow_ctrl;
3576 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3577 vars->flow_ctrl = params->req_fc_auto_adv;
3578 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3580 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3584 /******************************************************************/
3585 /* Warpcore section */
3586 /******************************************************************/
3587 /* The init_internal_warpcore should mirror the xgxs,
3588 * i.e. reset the lane (if needed), set aer for the
3589 * init configuration, and set/clear SGMII flag. Internal
3590 * phy init is done purely in phy_init stage.
3592 #define WC_TX_DRIVER(post2, idriver, ipre) \
3593 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3594 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3595 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3597 #define WC_TX_FIR(post, main, pre) \
3598 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3599 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3600 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3602 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3603 struct link_params *params,
3604 struct link_vars *vars)
3606 struct bnx2x *bp = params->bp;
3608 static struct bnx2x_reg_set reg_set[] = {
3609 /* Step 1 - Program the TX/RX alignment markers */
3610 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3611 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3612 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3613 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3614 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3615 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3616 /* Step 2 - Configure the NP registers */
3617 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3618 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3619 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3620 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3621 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3622 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3623 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3624 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3625 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3627 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3629 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3630 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3632 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3633 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3636 /* Start KR2 work-around timer which handles BCM8073 link-parner */
3637 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3638 bnx2x_update_link_attr(params, vars->link_attr_sync);
3641 static void bnx2x_disable_kr2(struct link_params *params,
3642 struct link_vars *vars,
3643 struct bnx2x_phy *phy)
3645 struct bnx2x *bp = params->bp;
3647 static struct bnx2x_reg_set reg_set[] = {
3648 /* Step 1 - Program the TX/RX alignment markers */
3649 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3652 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3653 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3654 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3655 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3656 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3658 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3659 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3660 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3661 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3662 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3663 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3665 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3667 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3668 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3670 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3671 bnx2x_update_link_attr(params, vars->link_attr_sync);
3673 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3676 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3677 struct link_params *params)
3679 struct bnx2x *bp = params->bp;
3681 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3682 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3683 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3684 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3685 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3688 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3689 struct link_params *params)
3691 /* Restart autoneg on the leading lane only */
3692 struct bnx2x *bp = params->bp;
3693 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3694 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3695 MDIO_AER_BLOCK_AER_REG, lane);
3696 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3697 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3700 bnx2x_set_aer_mmd(params, phy);
3703 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3704 struct link_params *params,
3705 struct link_vars *vars) {
3706 u16 lane, i, cl72_ctrl, an_adv = 0;
3707 struct bnx2x *bp = params->bp;
3708 static struct bnx2x_reg_set reg_set[] = {
3709 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3710 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3711 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3712 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3713 /* Disable Autoneg: re-enable it after adv is done. */
3714 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3715 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3716 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3718 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3719 /* Set to default registers that may be overriden by 10G force */
3720 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3721 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3724 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3725 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3726 cl72_ctrl &= 0x08ff;
3727 cl72_ctrl |= 0x3800;
3728 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3729 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3731 /* Check adding advertisement for 1G KX */
3732 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3733 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3734 (vars->line_speed == SPEED_1000)) {
3735 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3738 /* Enable CL37 1G Parallel Detect */
3739 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3740 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3742 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3743 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3744 (vars->line_speed == SPEED_10000)) {
3745 /* Check adding advertisement for 10G KR */
3747 /* Enable 10G Parallel Detect */
3748 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3749 MDIO_AER_BLOCK_AER_REG, 0);
3751 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3752 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3753 bnx2x_set_aer_mmd(params, phy);
3754 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3757 /* Set Transmit PMD settings */
3758 lane = bnx2x_get_warpcore_lane(phy, params);
3759 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3760 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3761 WC_TX_DRIVER(0x02, 0x06, 0x09));
3762 /* Configure the next lane if dual mode */
3763 if (phy->flags & FLAGS_WC_DUAL_MODE)
3764 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3765 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3766 WC_TX_DRIVER(0x02, 0x06, 0x09));
3767 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3768 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3770 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3774 /* Advertised speeds */
3775 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3776 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3778 /* Advertised and set FEC (Forward Error Correction) */
3779 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3780 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3781 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3782 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3784 /* Enable CL37 BAM */
3785 if (REG_RD(bp, params->shmem_base +
3786 offsetof(struct shmem_region, dev_info.
3787 port_hw_config[params->port].default_cfg)) &
3788 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3789 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3790 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3792 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3795 /* Advertise pause */
3796 bnx2x_ext_phy_set_pause(params, phy, vars);
3797 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3798 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3799 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3801 /* Over 1G - AN local device user page 1 */
3802 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3803 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3805 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3806 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3807 (phy->req_line_speed == SPEED_20000)) {
3809 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3810 MDIO_AER_BLOCK_AER_REG, lane);
3812 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3813 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3816 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3818 bnx2x_set_aer_mmd(params, phy);
3820 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3822 /* Enable Auto-Detect to support 1G over CL37 as well */
3823 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3824 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3826 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3827 * parallel-detect loop when CL73 and CL37 are enabled.
3829 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3830 MDIO_AER_BLOCK_AER_REG, 0);
3831 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3832 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
3833 bnx2x_set_aer_mmd(params, phy);
3835 bnx2x_disable_kr2(params, vars, phy);
3838 /* Enable Autoneg: only on the main lane */
3839 bnx2x_warpcore_restart_AN_KR(phy, params);
3842 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3843 struct link_params *params,
3844 struct link_vars *vars)
3846 struct bnx2x *bp = params->bp;
3848 static struct bnx2x_reg_set reg_set[] = {
3849 /* Disable Autoneg */
3850 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3851 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3853 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3854 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3855 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3856 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3857 /* Leave cl72 training enable, needed for KR */
3858 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3861 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3862 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3865 lane = bnx2x_get_warpcore_lane(phy, params);
3866 /* Global registers */
3867 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3868 MDIO_AER_BLOCK_AER_REG, 0);
3869 /* Disable CL36 PCS Tx */
3870 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3871 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3872 val16 &= ~(0x0011 << lane);
3873 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3874 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3876 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3877 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3878 val16 |= (0x0303 << (lane << 1));
3879 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3880 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3882 bnx2x_set_aer_mmd(params, phy);
3883 /* Set speed via PMA/PMD register */
3884 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3885 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3887 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3888 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3890 /* Enable encoded forced speed */
3891 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3892 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3894 /* Turn TX scramble payload only the 64/66 scrambler */
3895 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3896 MDIO_WC_REG_TX66_CONTROL, 0x9);
3898 /* Turn RX scramble payload only the 64/66 scrambler */
3899 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3902 /* Set and clear loopback to cause a reset to 64/66 decoder */
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3905 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3906 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3910 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3911 struct link_params *params,
3914 struct bnx2x *bp = params->bp;
3915 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3916 u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3918 /* Hold rxSeqStart */
3919 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3920 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3922 /* Hold tx_fifo_reset */
3923 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3924 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3926 /* Disable CL73 AN */
3927 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3929 /* Disable 100FX Enable and Auto-Detect */
3930 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3931 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3933 /* Disable 100FX Idle detect */
3934 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3935 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3937 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3938 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3939 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3941 /* Turn off auto-detect & fiber mode */
3942 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3943 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3946 /* Set filter_force_link, disable_false_link and parallel_detect */
3947 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3948 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3949 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3950 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3951 ((val | 0x0006) & 0xFFFE));
3954 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3955 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3957 misc1_val &= ~(0x1f);
3961 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3962 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3964 cfg_tap_val = REG_RD(bp, params->shmem_base +
3965 offsetof(struct shmem_region, dev_info.
3966 port_hw_config[params->port].
3969 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3971 tx_drv_brdct = (cfg_tap_val &
3972 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3973 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3977 /* TAP values are controlled by nvram, if value there isn't 0 */
3979 tap_val = (u16)tx_equal;
3981 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3984 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
3987 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3989 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3990 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3992 /* Set Transmit PMD settings */
3993 lane = bnx2x_get_warpcore_lane(phy, params);
3994 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3995 MDIO_WC_REG_TX_FIR_TAP,
3996 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3997 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3998 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4001 /* Enable fiber mode, enable and invert sig_det */
4002 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4003 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4005 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4006 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4007 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4009 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4011 /* 10G XFI Full Duplex */
4012 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4013 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4015 /* Release tx_fifo_reset */
4016 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4019 /* Release rxSeqStart */
4020 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4021 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4024 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4025 struct link_params *params)
4028 struct bnx2x *bp = params->bp;
4029 /* Set global registers, so set AER lane to 0 */
4030 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4031 MDIO_AER_BLOCK_AER_REG, 0);
4033 /* Disable sequencer */
4034 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4035 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4037 bnx2x_set_aer_mmd(params, phy);
4039 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4040 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4041 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4042 MDIO_AN_REG_CTRL, 0);
4044 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4045 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4048 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4049 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4051 /* Set 20G KR2 force speed */
4052 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4053 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4055 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4056 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4058 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4059 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4062 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4063 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4067 /* Enable sequencer (over lane 0) */
4068 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4069 MDIO_AER_BLOCK_AER_REG, 0);
4071 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4072 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4074 bnx2x_set_aer_mmd(params, phy);
4077 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4078 struct bnx2x_phy *phy,
4081 /* Rx0 anaRxControl1G */
4082 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4083 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4085 /* Rx2 anaRxControl1G */
4086 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4087 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4089 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4090 MDIO_WC_REG_RX66_SCW0, 0xE070);
4092 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4093 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4095 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4096 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4098 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4099 MDIO_WC_REG_RX66_SCW3, 0x8090);
4101 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4102 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4104 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4105 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4107 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4108 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4110 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4111 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4113 /* Serdes Digital Misc1 */
4114 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4115 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4117 /* Serdes Digital4 Misc3 */
4118 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4119 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4121 /* Set Transmit PMD settings */
4122 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4123 MDIO_WC_REG_TX_FIR_TAP,
4124 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4125 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4126 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4127 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4128 WC_TX_DRIVER(0x02, 0x02, 0x02));
4131 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4132 struct link_params *params,
4136 struct bnx2x *bp = params->bp;
4137 u16 val16, digctrl_kx1, digctrl_kx2;
4139 /* Clear XFI clock comp in non-10G single lane mode. */
4140 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4141 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4143 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4145 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4147 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4148 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4150 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4152 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4153 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4155 switch (phy->req_line_speed) {
4166 "Speed not supported: 0x%x\n", phy->req_line_speed);
4170 if (phy->req_duplex == DUPLEX_FULL)
4173 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4174 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4176 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4177 phy->req_line_speed);
4178 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4179 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4180 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4183 /* SGMII Slave mode and disable signal detect */
4184 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4185 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4189 digctrl_kx1 &= 0xff4a;
4191 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4192 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4195 /* Turn off parallel detect */
4196 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4197 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4198 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4199 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4200 (digctrl_kx2 & ~(1<<2)));
4202 /* Re-enable parallel detect */
4203 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4204 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4205 (digctrl_kx2 | (1<<2)));
4207 /* Enable autodet */
4208 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4209 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4210 (digctrl_kx1 | 0x10));
4213 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4214 struct bnx2x_phy *phy,
4218 /* Take lane out of reset after configuration is finished */
4219 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4220 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4225 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4226 MDIO_WC_REG_DIGITAL5_MISC6, val);
4227 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4228 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4230 /* Clear SFI/XFI link settings registers */
4231 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4232 struct link_params *params,
4235 struct bnx2x *bp = params->bp;
4237 static struct bnx2x_reg_set wc_regs[] = {
4238 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4239 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4240 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4241 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4242 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4244 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4246 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4248 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4249 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4250 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4251 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4253 /* Set XFI clock comp as default. */
4254 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4255 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4257 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4258 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4261 lane = bnx2x_get_warpcore_lane(phy, params);
4262 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4263 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4267 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4269 u32 shmem_base, u8 port,
4270 u8 *gpio_num, u8 *gpio_port)
4275 if (CHIP_IS_E3(bp)) {
4276 cfg_pin = (REG_RD(bp, shmem_base +
4277 offsetof(struct shmem_region,
4278 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4279 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4280 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4282 /* Should not happen. This function called upon interrupt
4283 * triggered by GPIO ( since EPIO can only generate interrupts
4285 * So if this function was called and none of the GPIOs was set,
4286 * it means the shit hit the fan.
4288 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4289 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4291 "No cfg pin %x for module detect indication\n",
4296 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4297 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4299 *gpio_num = MISC_REGISTERS_GPIO_3;
4306 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4307 struct link_params *params)
4309 struct bnx2x *bp = params->bp;
4310 u8 gpio_num, gpio_port;
4312 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4313 params->shmem_base, params->port,
4314 &gpio_num, &gpio_port) != 0)
4316 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4318 /* Call the handling function in case module is detected */
4324 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4325 struct link_params *params)
4327 u16 gp2_status_reg0, lane;
4328 struct bnx2x *bp = params->bp;
4330 lane = bnx2x_get_warpcore_lane(phy, params);
4332 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4335 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4338 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4339 struct link_params *params,
4340 struct link_vars *vars)
4342 struct bnx2x *bp = params->bp;
4344 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4346 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4348 if (!vars->turn_to_run_wc_rt)
4351 if (vars->rx_tx_asic_rst) {
4352 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4353 serdes_net_if = (REG_RD(bp, params->shmem_base +
4354 offsetof(struct shmem_region, dev_info.
4355 port_hw_config[params->port].default_cfg)) &
4356 PORT_HW_CFG_NET_SERDES_IF_MASK);
4358 switch (serdes_net_if) {
4359 case PORT_HW_CFG_NET_SERDES_IF_KR:
4360 /* Do we get link yet? */
4361 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4363 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4365 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4367 if (lnkup_kr || lnkup) {
4368 vars->rx_tx_asic_rst = 0;
4370 /* Reset the lane to see if link comes up.*/
4371 bnx2x_warpcore_reset_lane(bp, phy, 1);
4372 bnx2x_warpcore_reset_lane(bp, phy, 0);
4374 /* Restart Autoneg */
4375 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4376 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4378 vars->rx_tx_asic_rst--;
4379 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4380 vars->rx_tx_asic_rst);
4388 } /*params->rx_tx_asic_rst*/
4391 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4392 struct link_params *params)
4394 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4395 struct bnx2x *bp = params->bp;
4396 bnx2x_warpcore_clear_regs(phy, params, lane);
4397 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4399 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4400 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4401 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4403 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4404 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4408 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4409 struct bnx2x_phy *phy,
4412 struct bnx2x *bp = params->bp;
4414 u8 port = params->port;
4416 cfg_pin = REG_RD(bp, params->shmem_base +
4417 offsetof(struct shmem_region,
4418 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4419 PORT_HW_CFG_E3_TX_LASER_MASK;
4420 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4421 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4423 /* For 20G, the expected pin to be used is 3 pins after the current */
4424 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4425 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4426 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4429 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4430 struct link_params *params,
4431 struct link_vars *vars)
4433 struct bnx2x *bp = params->bp;
4436 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4437 serdes_net_if = (REG_RD(bp, params->shmem_base +
4438 offsetof(struct shmem_region, dev_info.
4439 port_hw_config[params->port].default_cfg)) &
4440 PORT_HW_CFG_NET_SERDES_IF_MASK);
4441 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4442 "serdes_net_if = 0x%x\n",
4443 vars->line_speed, serdes_net_if);
4444 bnx2x_set_aer_mmd(params, phy);
4445 bnx2x_warpcore_reset_lane(bp, phy, 1);
4446 vars->phy_flags |= PHY_XGXS_FLAG;
4447 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4448 (phy->req_line_speed &&
4449 ((phy->req_line_speed == SPEED_100) ||
4450 (phy->req_line_speed == SPEED_10)))) {
4451 vars->phy_flags |= PHY_SGMII_FLAG;
4452 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4453 bnx2x_warpcore_clear_regs(phy, params, lane);
4454 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4456 switch (serdes_net_if) {
4457 case PORT_HW_CFG_NET_SERDES_IF_KR:
4458 /* Enable KR Auto Neg */
4459 if (params->loopback_mode != LOOPBACK_EXT)
4460 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4462 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4463 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4467 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4468 bnx2x_warpcore_clear_regs(phy, params, lane);
4469 if (vars->line_speed == SPEED_10000) {
4470 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4471 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4473 if (SINGLE_MEDIA_DIRECT(params)) {
4474 DP(NETIF_MSG_LINK, "1G Fiber\n");
4477 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4480 bnx2x_warpcore_set_sgmii_speed(phy,
4488 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4489 /* Issue Module detection if module is plugged, or
4490 * enabled transmitter to avoid current leakage in case
4491 * no module is connected
4493 if ((params->loopback_mode == LOOPBACK_NONE) ||
4494 (params->loopback_mode == LOOPBACK_EXT)) {
4495 if (bnx2x_is_sfp_module_plugged(phy, params))
4496 bnx2x_sfp_module_detection(phy, params);
4498 bnx2x_sfp_e3_set_transmitter(params,
4502 bnx2x_warpcore_config_sfi(phy, params);
4505 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4506 if (vars->line_speed != SPEED_20000) {
4507 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4510 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4511 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4512 /* Issue Module detection */
4514 bnx2x_sfp_module_detection(phy, params);
4516 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4517 if (!params->loopback_mode) {
4518 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4520 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4521 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4526 "Unsupported Serdes Net Interface 0x%x\n",
4532 /* Take lane out of reset after configuration is finished */
4533 bnx2x_warpcore_reset_lane(bp, phy, 0);
4534 DP(NETIF_MSG_LINK, "Exit config init\n");
4537 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4538 struct link_params *params)
4540 struct bnx2x *bp = params->bp;
4542 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4543 bnx2x_set_mdio_emac_per_phy(bp, params);
4544 bnx2x_set_aer_mmd(params, phy);
4545 /* Global register */
4546 bnx2x_warpcore_reset_lane(bp, phy, 1);
4548 /* Clear loopback settings (if any) */
4550 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4551 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4553 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4554 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4556 /* Update those 1-copy registers */
4557 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4558 MDIO_AER_BLOCK_AER_REG, 0);
4559 /* Enable 1G MDIO (1-copy) */
4560 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4561 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4564 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4565 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4566 lane = bnx2x_get_warpcore_lane(phy, params);
4567 /* Disable CL36 PCS Tx */
4568 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4569 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4570 val16 |= (0x11 << lane);
4571 if (phy->flags & FLAGS_WC_DUAL_MODE)
4572 val16 |= (0x22 << lane);
4573 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4574 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4576 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4577 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4578 val16 &= ~(0x0303 << (lane << 1));
4579 val16 |= (0x0101 << (lane << 1));
4580 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4581 val16 &= ~(0x0c0c << (lane << 1));
4582 val16 |= (0x0404 << (lane << 1));
4585 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4586 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4588 bnx2x_set_aer_mmd(params, phy);
4592 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4593 struct link_params *params)
4595 struct bnx2x *bp = params->bp;
4598 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4599 params->loopback_mode, phy->req_line_speed);
4601 if (phy->req_line_speed < SPEED_10000 ||
4602 phy->supported & SUPPORTED_20000baseKR2_Full) {
4603 /* 10/100/1000/20G-KR2 */
4605 /* Update those 1-copy registers */
4606 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4607 MDIO_AER_BLOCK_AER_REG, 0);
4608 /* Enable 1G MDIO (1-copy) */
4609 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4610 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4612 /* Set 1G loopback based on lane (1-copy) */
4613 lane = bnx2x_get_warpcore_lane(phy, params);
4614 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4615 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4617 if (phy->flags & FLAGS_WC_DUAL_MODE)
4619 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4620 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4623 /* Switch back to 4-copy registers */
4624 bnx2x_set_aer_mmd(params, phy);
4626 /* 10G / 20G-DXGXS */
4627 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4628 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4630 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4631 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4637 static void bnx2x_sync_link(struct link_params *params,
4638 struct link_vars *vars)
4640 struct bnx2x *bp = params->bp;
4642 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4643 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4644 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4645 if (vars->link_up) {
4646 DP(NETIF_MSG_LINK, "phy link up\n");
4648 vars->phy_link_up = 1;
4649 vars->duplex = DUPLEX_FULL;
4650 switch (vars->link_status &
4651 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4653 vars->duplex = DUPLEX_HALF;
4656 vars->line_speed = SPEED_10;
4660 vars->duplex = DUPLEX_HALF;
4664 vars->line_speed = SPEED_100;
4668 vars->duplex = DUPLEX_HALF;
4671 vars->line_speed = SPEED_1000;
4675 vars->duplex = DUPLEX_HALF;
4678 vars->line_speed = SPEED_2500;
4682 vars->line_speed = SPEED_10000;
4685 vars->line_speed = SPEED_20000;
4690 vars->flow_ctrl = 0;
4691 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4692 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4694 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4695 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4697 if (!vars->flow_ctrl)
4698 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4700 if (vars->line_speed &&
4701 ((vars->line_speed == SPEED_10) ||
4702 (vars->line_speed == SPEED_100))) {
4703 vars->phy_flags |= PHY_SGMII_FLAG;
4705 vars->phy_flags &= ~PHY_SGMII_FLAG;
4707 if (vars->line_speed &&
4708 USES_WARPCORE(bp) &&
4709 (vars->line_speed == SPEED_1000))
4710 vars->phy_flags |= PHY_SGMII_FLAG;
4711 /* Anything 10 and over uses the bmac */
4712 link_10g_plus = (vars->line_speed >= SPEED_10000);
4714 if (link_10g_plus) {
4715 if (USES_WARPCORE(bp))
4716 vars->mac_type = MAC_TYPE_XMAC;
4718 vars->mac_type = MAC_TYPE_BMAC;
4720 if (USES_WARPCORE(bp))
4721 vars->mac_type = MAC_TYPE_UMAC;
4723 vars->mac_type = MAC_TYPE_EMAC;
4725 } else { /* Link down */
4726 DP(NETIF_MSG_LINK, "phy link down\n");
4728 vars->phy_link_up = 0;
4730 vars->line_speed = 0;
4731 vars->duplex = DUPLEX_FULL;
4732 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4734 /* Indicate no mac active */
4735 vars->mac_type = MAC_TYPE_NONE;
4736 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4737 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4738 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4739 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4743 void bnx2x_link_status_update(struct link_params *params,
4744 struct link_vars *vars)
4746 struct bnx2x *bp = params->bp;
4747 u8 port = params->port;
4748 u32 sync_offset, media_types;
4749 /* Update PHY configuration */
4750 set_phy_vars(params, vars);
4752 vars->link_status = REG_RD(bp, params->shmem_base +
4753 offsetof(struct shmem_region,
4754 port_mb[port].link_status));
4756 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4757 if (params->loopback_mode != LOOPBACK_NONE &&
4758 params->loopback_mode != LOOPBACK_EXT)
4759 vars->link_status |= LINK_STATUS_LINK_UP;
4761 if (bnx2x_eee_has_cap(params))
4762 vars->eee_status = REG_RD(bp, params->shmem2_base +
4763 offsetof(struct shmem2_region,
4764 eee_status[params->port]));
4766 vars->phy_flags = PHY_XGXS_FLAG;
4767 bnx2x_sync_link(params, vars);
4768 /* Sync media type */
4769 sync_offset = params->shmem_base +
4770 offsetof(struct shmem_region,
4771 dev_info.port_hw_config[port].media_type);
4772 media_types = REG_RD(bp, sync_offset);
4774 params->phy[INT_PHY].media_type =
4775 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4776 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4777 params->phy[EXT_PHY1].media_type =
4778 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4779 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4780 params->phy[EXT_PHY2].media_type =
4781 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4782 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4783 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4785 /* Sync AEU offset */
4786 sync_offset = params->shmem_base +
4787 offsetof(struct shmem_region,
4788 dev_info.port_hw_config[port].aeu_int_mask);
4790 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4792 /* Sync PFC status */
4793 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4794 params->feature_config_flags |=
4795 FEATURE_CONFIG_PFC_ENABLED;
4797 params->feature_config_flags &=
4798 ~FEATURE_CONFIG_PFC_ENABLED;
4800 if (SHMEM2_HAS(bp, link_attr_sync))
4801 vars->link_attr_sync = SHMEM2_RD(bp,
4802 link_attr_sync[params->port]);
4804 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4805 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4806 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4807 vars->line_speed, vars->duplex, vars->flow_ctrl);
4810 static void bnx2x_set_master_ln(struct link_params *params,
4811 struct bnx2x_phy *phy)
4813 struct bnx2x *bp = params->bp;
4814 u16 new_master_ln, ser_lane;
4815 ser_lane = ((params->lane_config &
4816 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4817 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4819 /* Set the master_ln for AN */
4820 CL22_RD_OVER_CL45(bp, phy,
4821 MDIO_REG_BANK_XGXS_BLOCK2,
4822 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4825 CL22_WR_OVER_CL45(bp, phy,
4826 MDIO_REG_BANK_XGXS_BLOCK2 ,
4827 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4828 (new_master_ln | ser_lane));
4831 static int bnx2x_reset_unicore(struct link_params *params,
4832 struct bnx2x_phy *phy,
4835 struct bnx2x *bp = params->bp;
4838 CL22_RD_OVER_CL45(bp, phy,
4839 MDIO_REG_BANK_COMBO_IEEE0,
4840 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4842 /* Reset the unicore */
4843 CL22_WR_OVER_CL45(bp, phy,
4844 MDIO_REG_BANK_COMBO_IEEE0,
4845 MDIO_COMBO_IEEE0_MII_CONTROL,
4847 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4849 bnx2x_set_serdes_access(bp, params->port);
4851 /* Wait for the reset to self clear */
4852 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4855 /* The reset erased the previous bank value */
4856 CL22_RD_OVER_CL45(bp, phy,
4857 MDIO_REG_BANK_COMBO_IEEE0,
4858 MDIO_COMBO_IEEE0_MII_CONTROL,
4861 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4867 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4870 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4875 static void bnx2x_set_swap_lanes(struct link_params *params,
4876 struct bnx2x_phy *phy)
4878 struct bnx2x *bp = params->bp;
4879 /* Each two bits represents a lane number:
4880 * No swap is 0123 => 0x1b no need to enable the swap
4882 u16 rx_lane_swap, tx_lane_swap;
4884 rx_lane_swap = ((params->lane_config &
4885 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4886 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4887 tx_lane_swap = ((params->lane_config &
4888 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4889 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4891 if (rx_lane_swap != 0x1b) {
4892 CL22_WR_OVER_CL45(bp, phy,
4893 MDIO_REG_BANK_XGXS_BLOCK2,
4894 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4896 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4897 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4899 CL22_WR_OVER_CL45(bp, phy,
4900 MDIO_REG_BANK_XGXS_BLOCK2,
4901 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4904 if (tx_lane_swap != 0x1b) {
4905 CL22_WR_OVER_CL45(bp, phy,
4906 MDIO_REG_BANK_XGXS_BLOCK2,
4907 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4909 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4911 CL22_WR_OVER_CL45(bp, phy,
4912 MDIO_REG_BANK_XGXS_BLOCK2,
4913 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4917 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4918 struct link_params *params)
4920 struct bnx2x *bp = params->bp;
4922 CL22_RD_OVER_CL45(bp, phy,
4923 MDIO_REG_BANK_SERDES_DIGITAL,
4924 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4926 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4927 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4929 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4930 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4931 phy->speed_cap_mask, control2);
4932 CL22_WR_OVER_CL45(bp, phy,
4933 MDIO_REG_BANK_SERDES_DIGITAL,
4934 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4937 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4938 (phy->speed_cap_mask &
4939 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4940 DP(NETIF_MSG_LINK, "XGXS\n");
4942 CL22_WR_OVER_CL45(bp, phy,
4943 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4944 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4945 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4947 CL22_RD_OVER_CL45(bp, phy,
4948 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4949 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4954 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4956 CL22_WR_OVER_CL45(bp, phy,
4957 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4958 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4961 /* Disable parallel detection of HiG */
4962 CL22_WR_OVER_CL45(bp, phy,
4963 MDIO_REG_BANK_XGXS_BLOCK2,
4964 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4965 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4966 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4970 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4971 struct link_params *params,
4972 struct link_vars *vars,
4975 struct bnx2x *bp = params->bp;
4979 CL22_RD_OVER_CL45(bp, phy,
4980 MDIO_REG_BANK_COMBO_IEEE0,
4981 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4983 /* CL37 Autoneg Enabled */
4984 if (vars->line_speed == SPEED_AUTO_NEG)
4985 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4986 else /* CL37 Autoneg Disabled */
4987 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4988 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4990 CL22_WR_OVER_CL45(bp, phy,
4991 MDIO_REG_BANK_COMBO_IEEE0,
4992 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4994 /* Enable/Disable Autodetection */
4996 CL22_RD_OVER_CL45(bp, phy,
4997 MDIO_REG_BANK_SERDES_DIGITAL,
4998 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4999 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5000 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5001 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5002 if (vars->line_speed == SPEED_AUTO_NEG)
5003 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5005 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5007 CL22_WR_OVER_CL45(bp, phy,
5008 MDIO_REG_BANK_SERDES_DIGITAL,
5009 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5011 /* Enable TetonII and BAM autoneg */
5012 CL22_RD_OVER_CL45(bp, phy,
5013 MDIO_REG_BANK_BAM_NEXT_PAGE,
5014 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5016 if (vars->line_speed == SPEED_AUTO_NEG) {
5017 /* Enable BAM aneg Mode and TetonII aneg Mode */
5018 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5019 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5021 /* TetonII and BAM Autoneg Disabled */
5022 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5023 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5025 CL22_WR_OVER_CL45(bp, phy,
5026 MDIO_REG_BANK_BAM_NEXT_PAGE,
5027 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5031 /* Enable Cl73 FSM status bits */
5032 CL22_WR_OVER_CL45(bp, phy,
5033 MDIO_REG_BANK_CL73_USERB0,
5034 MDIO_CL73_USERB0_CL73_UCTRL,
5037 /* Enable BAM Station Manager*/
5038 CL22_WR_OVER_CL45(bp, phy,
5039 MDIO_REG_BANK_CL73_USERB0,
5040 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5041 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5042 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5043 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5045 /* Advertise CL73 link speeds */
5046 CL22_RD_OVER_CL45(bp, phy,
5047 MDIO_REG_BANK_CL73_IEEEB1,
5048 MDIO_CL73_IEEEB1_AN_ADV2,
5050 if (phy->speed_cap_mask &
5051 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5052 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5053 if (phy->speed_cap_mask &
5054 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5055 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5057 CL22_WR_OVER_CL45(bp, phy,
5058 MDIO_REG_BANK_CL73_IEEEB1,
5059 MDIO_CL73_IEEEB1_AN_ADV2,
5062 /* CL73 Autoneg Enabled */
5063 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5065 } else /* CL73 Autoneg Disabled */
5068 CL22_WR_OVER_CL45(bp, phy,
5069 MDIO_REG_BANK_CL73_IEEEB0,
5070 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5073 /* Program SerDes, forced speed */
5074 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5075 struct link_params *params,
5076 struct link_vars *vars)
5078 struct bnx2x *bp = params->bp;
5081 /* Program duplex, disable autoneg and sgmii*/
5082 CL22_RD_OVER_CL45(bp, phy,
5083 MDIO_REG_BANK_COMBO_IEEE0,
5084 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5085 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5086 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5087 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5088 if (phy->req_duplex == DUPLEX_FULL)
5089 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5090 CL22_WR_OVER_CL45(bp, phy,
5091 MDIO_REG_BANK_COMBO_IEEE0,
5092 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5095 * - needed only if the speed is greater than 1G (2.5G or 10G)
5097 CL22_RD_OVER_CL45(bp, phy,
5098 MDIO_REG_BANK_SERDES_DIGITAL,
5099 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5100 /* Clearing the speed value before setting the right speed */
5101 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5103 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5104 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5106 if (!((vars->line_speed == SPEED_1000) ||
5107 (vars->line_speed == SPEED_100) ||
5108 (vars->line_speed == SPEED_10))) {
5110 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5111 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5112 if (vars->line_speed == SPEED_10000)
5114 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5117 CL22_WR_OVER_CL45(bp, phy,
5118 MDIO_REG_BANK_SERDES_DIGITAL,
5119 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5123 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5124 struct link_params *params)
5126 struct bnx2x *bp = params->bp;
5129 /* Set extended capabilities */
5130 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5131 val |= MDIO_OVER_1G_UP1_2_5G;
5132 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5133 val |= MDIO_OVER_1G_UP1_10G;
5134 CL22_WR_OVER_CL45(bp, phy,
5135 MDIO_REG_BANK_OVER_1G,
5136 MDIO_OVER_1G_UP1, val);
5138 CL22_WR_OVER_CL45(bp, phy,
5139 MDIO_REG_BANK_OVER_1G,
5140 MDIO_OVER_1G_UP3, 0x400);
5143 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5144 struct link_params *params,
5147 struct bnx2x *bp = params->bp;
5149 /* For AN, we are always publishing full duplex */
5151 CL22_WR_OVER_CL45(bp, phy,
5152 MDIO_REG_BANK_COMBO_IEEE0,
5153 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5154 CL22_RD_OVER_CL45(bp, phy,
5155 MDIO_REG_BANK_CL73_IEEEB1,
5156 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5157 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5158 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5159 CL22_WR_OVER_CL45(bp, phy,
5160 MDIO_REG_BANK_CL73_IEEEB1,
5161 MDIO_CL73_IEEEB1_AN_ADV1, val);
5164 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5165 struct link_params *params,
5168 struct bnx2x *bp = params->bp;
5171 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5172 /* Enable and restart BAM/CL37 aneg */
5175 CL22_RD_OVER_CL45(bp, phy,
5176 MDIO_REG_BANK_CL73_IEEEB0,
5177 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5180 CL22_WR_OVER_CL45(bp, phy,
5181 MDIO_REG_BANK_CL73_IEEEB0,
5182 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5184 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5185 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5188 CL22_RD_OVER_CL45(bp, phy,
5189 MDIO_REG_BANK_COMBO_IEEE0,
5190 MDIO_COMBO_IEEE0_MII_CONTROL,
5193 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5195 CL22_WR_OVER_CL45(bp, phy,
5196 MDIO_REG_BANK_COMBO_IEEE0,
5197 MDIO_COMBO_IEEE0_MII_CONTROL,
5199 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5200 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5204 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5205 struct link_params *params,
5206 struct link_vars *vars)
5208 struct bnx2x *bp = params->bp;
5211 /* In SGMII mode, the unicore is always slave */
5213 CL22_RD_OVER_CL45(bp, phy,
5214 MDIO_REG_BANK_SERDES_DIGITAL,
5215 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5217 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5218 /* Set sgmii mode (and not fiber) */
5219 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5220 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5221 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5222 CL22_WR_OVER_CL45(bp, phy,
5223 MDIO_REG_BANK_SERDES_DIGITAL,
5224 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5227 /* If forced speed */
5228 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5229 /* Set speed, disable autoneg */
5232 CL22_RD_OVER_CL45(bp, phy,
5233 MDIO_REG_BANK_COMBO_IEEE0,
5234 MDIO_COMBO_IEEE0_MII_CONTROL,
5236 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5237 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5238 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5240 switch (vars->line_speed) {
5243 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5247 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5250 /* There is nothing to set for 10M */
5253 /* Invalid speed for SGMII */
5254 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5259 /* Setting the full duplex */
5260 if (phy->req_duplex == DUPLEX_FULL)
5262 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5263 CL22_WR_OVER_CL45(bp, phy,
5264 MDIO_REG_BANK_COMBO_IEEE0,
5265 MDIO_COMBO_IEEE0_MII_CONTROL,
5268 } else { /* AN mode */
5269 /* Enable and restart AN */
5270 bnx2x_restart_autoneg(phy, params, 0);
5276 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5277 struct link_params *params)
5279 struct bnx2x *bp = params->bp;
5280 u16 pd_10g, status2_1000x;
5281 if (phy->req_line_speed != SPEED_AUTO_NEG)
5283 CL22_RD_OVER_CL45(bp, phy,
5284 MDIO_REG_BANK_SERDES_DIGITAL,
5285 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5287 CL22_RD_OVER_CL45(bp, phy,
5288 MDIO_REG_BANK_SERDES_DIGITAL,
5289 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5291 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5292 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5297 CL22_RD_OVER_CL45(bp, phy,
5298 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5299 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5302 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5303 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5310 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5311 struct link_params *params,
5312 struct link_vars *vars,
5315 u16 ld_pause; /* local driver */
5316 u16 lp_pause; /* link partner */
5318 struct bnx2x *bp = params->bp;
5320 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5321 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5322 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5323 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5325 CL22_RD_OVER_CL45(bp, phy,
5326 MDIO_REG_BANK_CL73_IEEEB1,
5327 MDIO_CL73_IEEEB1_AN_ADV1,
5329 CL22_RD_OVER_CL45(bp, phy,
5330 MDIO_REG_BANK_CL73_IEEEB1,
5331 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5333 pause_result = (ld_pause &
5334 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5335 pause_result |= (lp_pause &
5336 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5337 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5339 CL22_RD_OVER_CL45(bp, phy,
5340 MDIO_REG_BANK_COMBO_IEEE0,
5341 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5343 CL22_RD_OVER_CL45(bp, phy,
5344 MDIO_REG_BANK_COMBO_IEEE0,
5345 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5347 pause_result = (ld_pause &
5348 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5349 pause_result |= (lp_pause &
5350 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5351 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5353 bnx2x_pause_resolve(vars, pause_result);
5357 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5358 struct link_params *params,
5359 struct link_vars *vars,
5362 struct bnx2x *bp = params->bp;
5363 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5365 /* Resolve from gp_status in case of AN complete and not sgmii */
5366 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5367 /* Update the advertised flow-controled of LD/LP in AN */
5368 if (phy->req_line_speed == SPEED_AUTO_NEG)
5369 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5370 /* But set the flow-control result as the requested one */
5371 vars->flow_ctrl = phy->req_flow_ctrl;
5372 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5373 vars->flow_ctrl = params->req_fc_auto_adv;
5374 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5375 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5376 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5377 vars->flow_ctrl = params->req_fc_auto_adv;
5380 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5382 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5385 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5386 struct link_params *params)
5388 struct bnx2x *bp = params->bp;
5389 u16 rx_status, ustat_val, cl37_fsm_received;
5390 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5391 /* Step 1: Make sure signal is detected */
5392 CL22_RD_OVER_CL45(bp, phy,
5396 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5397 (MDIO_RX0_RX_STATUS_SIGDET)) {
5398 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5399 "rx_status(0x80b0) = 0x%x\n", rx_status);
5400 CL22_WR_OVER_CL45(bp, phy,
5401 MDIO_REG_BANK_CL73_IEEEB0,
5402 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5403 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5406 /* Step 2: Check CL73 state machine */
5407 CL22_RD_OVER_CL45(bp, phy,
5408 MDIO_REG_BANK_CL73_USERB0,
5409 MDIO_CL73_USERB0_CL73_USTAT1,
5412 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5413 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5414 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5415 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5416 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5417 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5420 /* Step 3: Check CL37 Message Pages received to indicate LP
5421 * supports only CL37
5423 CL22_RD_OVER_CL45(bp, phy,
5424 MDIO_REG_BANK_REMOTE_PHY,
5425 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5426 &cl37_fsm_received);
5427 if ((cl37_fsm_received &
5428 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5429 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5430 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5431 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5432 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5433 "misc_rx_status(0x8330) = 0x%x\n",
5437 /* The combined cl37/cl73 fsm state information indicating that
5438 * we are connected to a device which does not support cl73, but
5439 * does support cl37 BAM. In this case we disable cl73 and
5440 * restart cl37 auto-neg
5444 CL22_WR_OVER_CL45(bp, phy,
5445 MDIO_REG_BANK_CL73_IEEEB0,
5446 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5448 /* Restart CL37 autoneg */
5449 bnx2x_restart_autoneg(phy, params, 0);
5450 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5453 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5454 struct link_params *params,
5455 struct link_vars *vars,
5458 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5459 vars->link_status |=
5460 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5462 if (bnx2x_direct_parallel_detect_used(phy, params))
5463 vars->link_status |=
5464 LINK_STATUS_PARALLEL_DETECTION_USED;
5466 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5467 struct link_params *params,
5468 struct link_vars *vars,
5473 struct bnx2x *bp = params->bp;
5474 if (phy->req_line_speed == SPEED_AUTO_NEG)
5475 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5477 DP(NETIF_MSG_LINK, "phy link up\n");
5479 vars->phy_link_up = 1;
5480 vars->link_status |= LINK_STATUS_LINK_UP;
5482 switch (speed_mask) {
5484 vars->line_speed = SPEED_10;
5485 if (is_duplex == DUPLEX_FULL)
5486 vars->link_status |= LINK_10TFD;
5488 vars->link_status |= LINK_10THD;
5491 case GP_STATUS_100M:
5492 vars->line_speed = SPEED_100;
5493 if (is_duplex == DUPLEX_FULL)
5494 vars->link_status |= LINK_100TXFD;
5496 vars->link_status |= LINK_100TXHD;
5500 case GP_STATUS_1G_KX:
5501 vars->line_speed = SPEED_1000;
5502 if (is_duplex == DUPLEX_FULL)
5503 vars->link_status |= LINK_1000TFD;
5505 vars->link_status |= LINK_1000THD;
5508 case GP_STATUS_2_5G:
5509 vars->line_speed = SPEED_2500;
5510 if (is_duplex == DUPLEX_FULL)
5511 vars->link_status |= LINK_2500TFD;
5513 vars->link_status |= LINK_2500THD;
5519 "link speed unsupported gp_status 0x%x\n",
5523 case GP_STATUS_10G_KX4:
5524 case GP_STATUS_10G_HIG:
5525 case GP_STATUS_10G_CX4:
5526 case GP_STATUS_10G_KR:
5527 case GP_STATUS_10G_SFI:
5528 case GP_STATUS_10G_XFI:
5529 vars->line_speed = SPEED_10000;
5530 vars->link_status |= LINK_10GTFD;
5532 case GP_STATUS_20G_DXGXS:
5533 case GP_STATUS_20G_KR2:
5534 vars->line_speed = SPEED_20000;
5535 vars->link_status |= LINK_20GTFD;
5539 "link speed unsupported gp_status 0x%x\n",
5543 } else { /* link_down */
5544 DP(NETIF_MSG_LINK, "phy link down\n");
5546 vars->phy_link_up = 0;
5548 vars->duplex = DUPLEX_FULL;
5549 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5550 vars->mac_type = MAC_TYPE_NONE;
5552 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5553 vars->phy_link_up, vars->line_speed);
5557 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5558 struct link_params *params,
5559 struct link_vars *vars)
5561 struct bnx2x *bp = params->bp;
5563 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5566 /* Read gp_status */
5567 CL22_RD_OVER_CL45(bp, phy,
5568 MDIO_REG_BANK_GP_STATUS,
5569 MDIO_GP_STATUS_TOP_AN_STATUS1,
5571 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5572 duplex = DUPLEX_FULL;
5573 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5575 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5576 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5577 gp_status, link_up, speed_mask);
5578 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5583 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5584 if (SINGLE_MEDIA_DIRECT(params)) {
5585 vars->duplex = duplex;
5586 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5587 if (phy->req_line_speed == SPEED_AUTO_NEG)
5588 bnx2x_xgxs_an_resolve(phy, params, vars,
5591 } else { /* Link_down */
5592 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5593 SINGLE_MEDIA_DIRECT(params)) {
5594 /* Check signal is detected */
5595 bnx2x_check_fallback_to_cl37(phy, params);
5599 /* Read LP advertised speeds*/
5600 if (SINGLE_MEDIA_DIRECT(params) &&
5601 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5604 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5605 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5607 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5608 vars->link_status |=
5609 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5610 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5611 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5612 vars->link_status |=
5613 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5615 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5616 MDIO_OVER_1G_LP_UP1, &val);
5618 if (val & MDIO_OVER_1G_UP1_2_5G)
5619 vars->link_status |=
5620 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5621 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5622 vars->link_status |=
5623 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5626 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5627 vars->duplex, vars->flow_ctrl, vars->link_status);
5631 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5632 struct link_params *params,
5633 struct link_vars *vars)
5635 struct bnx2x *bp = params->bp;
5637 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5639 lane = bnx2x_get_warpcore_lane(phy, params);
5640 /* Read gp_status */
5641 if ((params->loopback_mode) &&
5642 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5643 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5644 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5645 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5646 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5648 } else if ((phy->req_line_speed > SPEED_10000) &&
5649 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5651 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5653 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5655 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5656 temp_link_up, link_up);
5659 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5661 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5662 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5664 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5665 /* Check for either KR, 1G, or AN up. */
5666 link_up = ((gp_status1 >> 8) |
5667 (gp_status1 >> 12) |
5670 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5672 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5673 MDIO_AN_REG_STATUS, &an_link);
5674 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5675 MDIO_AN_REG_STATUS, &an_link);
5676 link_up |= (an_link & (1<<2));
5678 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5680 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5681 /* Check Autoneg complete */
5682 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5683 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5685 if (gp_status4 & ((1<<12)<<lane))
5686 vars->link_status |=
5687 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5689 /* Check parallel detect used */
5690 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5691 MDIO_WC_REG_PAR_DET_10G_STATUS,
5694 vars->link_status |=
5695 LINK_STATUS_PARALLEL_DETECTION_USED;
5697 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5698 vars->duplex = duplex;
5702 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5703 SINGLE_MEDIA_DIRECT(params)) {
5706 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5707 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5709 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5710 vars->link_status |=
5711 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5712 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5713 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5714 vars->link_status |=
5715 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5717 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5718 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5720 if (val & MDIO_OVER_1G_UP1_2_5G)
5721 vars->link_status |=
5722 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5723 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5724 vars->link_status |=
5725 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5731 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5732 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5734 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5735 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5737 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5739 if ((lane & 1) == 0)
5742 link_up = !!link_up;
5744 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5747 /* In case of KR link down, start up the recovering procedure */
5748 if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5749 (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5750 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5752 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5753 vars->duplex, vars->flow_ctrl, vars->link_status);
5756 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5758 struct bnx2x *bp = params->bp;
5759 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5765 CL22_RD_OVER_CL45(bp, phy,
5766 MDIO_REG_BANK_OVER_1G,
5767 MDIO_OVER_1G_LP_UP2, &lp_up2);
5769 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5770 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5771 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5772 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5777 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5778 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5779 CL22_RD_OVER_CL45(bp, phy,
5781 MDIO_TX0_TX_DRIVER, &tx_driver);
5783 /* Replace tx_driver bits [15:12] */
5785 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5786 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5787 tx_driver |= lp_up2;
5788 CL22_WR_OVER_CL45(bp, phy,
5790 MDIO_TX0_TX_DRIVER, tx_driver);
5795 static int bnx2x_emac_program(struct link_params *params,
5796 struct link_vars *vars)
5798 struct bnx2x *bp = params->bp;
5799 u8 port = params->port;
5802 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5803 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5805 (EMAC_MODE_25G_MODE |
5806 EMAC_MODE_PORT_MII_10M |
5807 EMAC_MODE_HALF_DUPLEX));
5808 switch (vars->line_speed) {
5810 mode |= EMAC_MODE_PORT_MII_10M;
5814 mode |= EMAC_MODE_PORT_MII;
5818 mode |= EMAC_MODE_PORT_GMII;
5822 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5826 /* 10G not valid for EMAC */
5827 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5832 if (vars->duplex == DUPLEX_HALF)
5833 mode |= EMAC_MODE_HALF_DUPLEX;
5835 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5838 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5842 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5843 struct link_params *params)
5847 struct bnx2x *bp = params->bp;
5849 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5850 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5851 CL22_WR_OVER_CL45(bp, phy,
5853 MDIO_RX0_RX_EQ_BOOST,
5854 phy->rx_preemphasis[i]);
5857 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5858 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5859 CL22_WR_OVER_CL45(bp, phy,
5862 phy->tx_preemphasis[i]);
5866 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5867 struct link_params *params,
5868 struct link_vars *vars)
5870 struct bnx2x *bp = params->bp;
5871 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5872 (params->loopback_mode == LOOPBACK_XGXS));
5873 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5874 if (SINGLE_MEDIA_DIRECT(params) &&
5875 (params->feature_config_flags &
5876 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5877 bnx2x_set_preemphasis(phy, params);
5879 /* Forced speed requested? */
5880 if (vars->line_speed != SPEED_AUTO_NEG ||
5881 (SINGLE_MEDIA_DIRECT(params) &&
5882 params->loopback_mode == LOOPBACK_EXT)) {
5883 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5885 /* Disable autoneg */
5886 bnx2x_set_autoneg(phy, params, vars, 0);
5888 /* Program speed and duplex */
5889 bnx2x_program_serdes(phy, params, vars);
5891 } else { /* AN_mode */
5892 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5895 bnx2x_set_brcm_cl37_advertisement(phy, params);
5897 /* Program duplex & pause advertisement (for aneg) */
5898 bnx2x_set_ieee_aneg_advertisement(phy, params,
5901 /* Enable autoneg */
5902 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5904 /* Enable and restart AN */
5905 bnx2x_restart_autoneg(phy, params, enable_cl73);
5908 } else { /* SGMII mode */
5909 DP(NETIF_MSG_LINK, "SGMII\n");
5911 bnx2x_initialize_sgmii_process(phy, params, vars);
5915 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5916 struct link_params *params,
5917 struct link_vars *vars)
5920 vars->phy_flags |= PHY_XGXS_FLAG;
5921 if ((phy->req_line_speed &&
5922 ((phy->req_line_speed == SPEED_100) ||
5923 (phy->req_line_speed == SPEED_10))) ||
5924 (!phy->req_line_speed &&
5925 (phy->speed_cap_mask >=
5926 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5927 (phy->speed_cap_mask <
5928 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5929 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5930 vars->phy_flags |= PHY_SGMII_FLAG;
5932 vars->phy_flags &= ~PHY_SGMII_FLAG;
5934 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5935 bnx2x_set_aer_mmd(params, phy);
5936 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5937 bnx2x_set_master_ln(params, phy);
5939 rc = bnx2x_reset_unicore(params, phy, 0);
5940 /* Reset the SerDes and wait for reset bit return low */
5944 bnx2x_set_aer_mmd(params, phy);
5945 /* Setting the masterLn_def again after the reset */
5946 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5947 bnx2x_set_master_ln(params, phy);
5948 bnx2x_set_swap_lanes(params, phy);
5954 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5955 struct bnx2x_phy *phy,
5956 struct link_params *params)
5959 /* Wait for soft reset to get cleared up to 1 sec */
5960 for (cnt = 0; cnt < 1000; cnt++) {
5961 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5962 bnx2x_cl22_read(bp, phy,
5963 MDIO_PMA_REG_CTRL, &ctrl);
5965 bnx2x_cl45_read(bp, phy,
5967 MDIO_PMA_REG_CTRL, &ctrl);
5968 if (!(ctrl & (1<<15)))
5970 usleep_range(1000, 2000);
5974 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5977 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5981 static void bnx2x_link_int_enable(struct link_params *params)
5983 u8 port = params->port;
5985 struct bnx2x *bp = params->bp;
5987 /* Setting the status to report on link up for either XGXS or SerDes */
5988 if (CHIP_IS_E3(bp)) {
5989 mask = NIG_MASK_XGXS0_LINK_STATUS;
5990 if (!(SINGLE_MEDIA_DIRECT(params)))
5991 mask |= NIG_MASK_MI_INT;
5992 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5993 mask = (NIG_MASK_XGXS0_LINK10G |
5994 NIG_MASK_XGXS0_LINK_STATUS);
5995 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5996 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5997 params->phy[INT_PHY].type !=
5998 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5999 mask |= NIG_MASK_MI_INT;
6000 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6003 } else { /* SerDes */
6004 mask = NIG_MASK_SERDES0_LINK_STATUS;
6005 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6006 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6007 params->phy[INT_PHY].type !=
6008 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6009 mask |= NIG_MASK_MI_INT;
6010 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6014 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6017 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6018 (params->switch_cfg == SWITCH_CFG_10G),
6019 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6020 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6021 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6022 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6023 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6024 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6025 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6026 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6029 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6032 u32 latch_status = 0;
6034 /* Disable the MI INT ( external phy int ) by writing 1 to the
6035 * status register. Link down indication is high-active-signal,
6036 * so in this case we need to write the status to clear the XOR
6038 /* Read Latched signals */
6039 latch_status = REG_RD(bp,
6040 NIG_REG_LATCH_STATUS_0 + port*8);
6041 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6042 /* Handle only those with latched-signal=up.*/
6045 NIG_REG_STATUS_INTERRUPT_PORT0
6047 NIG_STATUS_EMAC0_MI_INT);
6050 NIG_REG_STATUS_INTERRUPT_PORT0
6052 NIG_STATUS_EMAC0_MI_INT);
6054 if (latch_status & 1) {
6056 /* For all latched-signal=up : Re-Arm Latch signals */
6057 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6058 (latch_status & 0xfffe) | (latch_status & 1));
6060 /* For all latched-signal=up,Write original_signal to status */
6063 static void bnx2x_link_int_ack(struct link_params *params,
6064 struct link_vars *vars, u8 is_10g_plus)
6066 struct bnx2x *bp = params->bp;
6067 u8 port = params->port;
6069 /* First reset all status we assume only one line will be
6072 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6073 (NIG_STATUS_XGXS0_LINK10G |
6074 NIG_STATUS_XGXS0_LINK_STATUS |
6075 NIG_STATUS_SERDES0_LINK_STATUS));
6076 if (vars->phy_link_up) {
6077 if (USES_WARPCORE(bp))
6078 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6081 mask = NIG_STATUS_XGXS0_LINK10G;
6082 else if (params->switch_cfg == SWITCH_CFG_10G) {
6083 /* Disable the link interrupt by writing 1 to
6084 * the relevant lane in the status register
6087 ((params->lane_config &
6088 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6089 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6090 mask = ((1 << ser_lane) <<
6091 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6093 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6095 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6098 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6103 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6106 u32 mask = 0xf0000000;
6109 u8 remove_leading_zeros = 1;
6111 /* Need more than 10chars for this format */
6119 digit = ((num & mask) >> shift);
6120 if (digit == 0 && remove_leading_zeros) {
6123 } else if (digit < 0xa)
6124 *str_ptr = digit + '0';
6126 *str_ptr = digit - 0xa + 'a';
6127 remove_leading_zeros = 0;
6135 remove_leading_zeros = 1;
6142 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6149 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6155 u8 *ver_p = version;
6156 u16 remain_len = len;
6157 if (version == NULL || params == NULL)
6161 /* Extract first external phy*/
6163 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6165 if (params->phy[EXT_PHY1].format_fw_ver) {
6166 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6169 ver_p += (len - remain_len);
6171 if ((params->num_phys == MAX_PHYS) &&
6172 (params->phy[EXT_PHY2].ver_addr != 0)) {
6173 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6174 if (params->phy[EXT_PHY2].format_fw_ver) {
6178 status |= params->phy[EXT_PHY2].format_fw_ver(
6182 ver_p = version + (len - remain_len);
6189 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6190 struct link_params *params)
6192 u8 port = params->port;
6193 struct bnx2x *bp = params->bp;
6195 if (phy->req_line_speed != SPEED_1000) {
6198 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6200 if (!CHIP_IS_E3(bp)) {
6201 /* Change the uni_phy_addr in the nig */
6202 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6205 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6209 bnx2x_cl45_write(bp, phy,
6211 (MDIO_REG_BANK_AER_BLOCK +
6212 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6215 bnx2x_cl45_write(bp, phy,
6217 (MDIO_REG_BANK_CL73_IEEEB0 +
6218 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6221 /* Set aer mmd back */
6222 bnx2x_set_aer_mmd(params, phy);
6224 if (!CHIP_IS_E3(bp)) {
6226 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6231 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6232 bnx2x_cl45_read(bp, phy, 5,
6233 (MDIO_REG_BANK_COMBO_IEEE0 +
6234 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6236 bnx2x_cl45_write(bp, phy, 5,
6237 (MDIO_REG_BANK_COMBO_IEEE0 +
6238 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6240 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6244 int bnx2x_set_led(struct link_params *params,
6245 struct link_vars *vars, u8 mode, u32 speed)
6247 u8 port = params->port;
6248 u16 hw_led_mode = params->hw_led_mode;
6252 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6253 struct bnx2x *bp = params->bp;
6254 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6255 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6256 speed, hw_led_mode);
6258 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6259 if (params->phy[phy_idx].set_link_led) {
6260 params->phy[phy_idx].set_link_led(
6261 ¶ms->phy[phy_idx], params, mode);
6266 case LED_MODE_FRONT_PANEL_OFF:
6268 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6269 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6270 SHARED_HW_CFG_LED_MAC1);
6272 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6273 if (params->phy[EXT_PHY1].type ==
6274 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6275 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6276 EMAC_LED_100MB_OVERRIDE |
6277 EMAC_LED_10MB_OVERRIDE);
6279 tmp |= EMAC_LED_OVERRIDE;
6281 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6285 /* For all other phys, OPER mode is same as ON, so in case
6286 * link is down, do nothing
6291 if (((params->phy[EXT_PHY1].type ==
6292 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6293 (params->phy[EXT_PHY1].type ==
6294 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6295 CHIP_IS_E2(bp) && params->num_phys == 2) {
6296 /* This is a work-around for E2+8727 Configurations */
6297 if (mode == LED_MODE_ON ||
6298 speed == SPEED_10000){
6299 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6300 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6302 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6303 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6304 (tmp | EMAC_LED_OVERRIDE));
6305 /* Return here without enabling traffic
6306 * LED blink and setting rate in ON mode.
6307 * In oper mode, enabling LED blink
6308 * and setting rate is needed.
6310 if (mode == LED_MODE_ON)
6313 } else if (SINGLE_MEDIA_DIRECT(params)) {
6314 /* This is a work-around for HW issue found when link
6317 if ((!CHIP_IS_E3(bp)) ||
6319 mode == LED_MODE_ON))
6320 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6322 if (CHIP_IS_E1x(bp) ||
6324 (mode == LED_MODE_ON))
6325 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6327 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6329 } else if ((params->phy[EXT_PHY1].type ==
6330 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6331 (mode == LED_MODE_ON)) {
6332 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6333 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6334 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6335 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6336 /* Break here; otherwise, it'll disable the
6337 * intended override.
6341 u32 nig_led_mode = ((params->hw_led_mode <<
6342 SHARED_HW_CFG_LED_MODE_SHIFT) ==
6343 SHARED_HW_CFG_LED_EXTPHY2) ?
6344 (SHARED_HW_CFG_LED_PHY1 >>
6345 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6346 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6350 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6351 /* Set blinking rate to ~15.9Hz */
6353 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6354 LED_BLINK_RATE_VAL_E3);
6356 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6357 LED_BLINK_RATE_VAL_E1X_E2);
6358 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6360 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6361 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6362 (tmp & (~EMAC_LED_OVERRIDE)));
6364 if (CHIP_IS_E1(bp) &&
6365 ((speed == SPEED_2500) ||
6366 (speed == SPEED_1000) ||
6367 (speed == SPEED_100) ||
6368 (speed == SPEED_10))) {
6369 /* For speeds less than 10G LED scheme is different */
6370 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6372 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6374 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6381 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6389 /* This function comes to reflect the actual link state read DIRECTLY from the
6392 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6395 struct bnx2x *bp = params->bp;
6396 u16 gp_status = 0, phy_index = 0;
6397 u8 ext_phy_link_up = 0, serdes_phy_type;
6398 struct link_vars temp_vars;
6399 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6401 if (CHIP_IS_E3(bp)) {
6403 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6405 /* Check 20G link */
6406 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6408 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6412 /* Check 10G link and below*/
6413 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6414 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6415 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6417 gp_status = ((gp_status >> 8) & 0xf) |
6418 ((gp_status >> 12) & 0xf);
6419 link_up = gp_status & (1 << lane);
6424 CL22_RD_OVER_CL45(bp, int_phy,
6425 MDIO_REG_BANK_GP_STATUS,
6426 MDIO_GP_STATUS_TOP_AN_STATUS1,
6428 /* Link is up only if both local phy and external phy are up */
6429 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6432 /* In XGXS loopback mode, do not check external PHY */
6433 if (params->loopback_mode == LOOPBACK_XGXS)
6436 switch (params->num_phys) {
6438 /* No external PHY */
6441 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6442 ¶ms->phy[EXT_PHY1],
6443 params, &temp_vars);
6445 case 3: /* Dual Media */
6446 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6448 serdes_phy_type = ((params->phy[phy_index].media_type ==
6449 ETH_PHY_SFPP_10G_FIBER) ||
6450 (params->phy[phy_index].media_type ==
6451 ETH_PHY_SFP_1G_FIBER) ||
6452 (params->phy[phy_index].media_type ==
6453 ETH_PHY_XFP_FIBER) ||
6454 (params->phy[phy_index].media_type ==
6455 ETH_PHY_DA_TWINAX));
6457 if (is_serdes != serdes_phy_type)
6459 if (params->phy[phy_index].read_status) {
6461 params->phy[phy_index].read_status(
6462 ¶ms->phy[phy_index],
6463 params, &temp_vars);
6468 if (ext_phy_link_up)
6473 static int bnx2x_link_initialize(struct link_params *params,
6474 struct link_vars *vars)
6477 u8 phy_index, non_ext_phy;
6478 struct bnx2x *bp = params->bp;
6479 /* In case of external phy existence, the line speed would be the
6480 * line speed linked up by the external phy. In case it is direct
6481 * only, then the line_speed during initialization will be
6482 * equal to the req_line_speed
6484 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6486 /* Initialize the internal phy in case this is a direct board
6487 * (no external phys), or this board has external phy which requires
6490 if (!USES_WARPCORE(bp))
6491 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6492 /* init ext phy and enable link state int */
6493 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6494 (params->loopback_mode == LOOPBACK_XGXS));
6497 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6498 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6499 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6500 if (vars->line_speed == SPEED_AUTO_NEG &&
6503 bnx2x_set_parallel_detection(phy, params);
6504 if (params->phy[INT_PHY].config_init)
6505 params->phy[INT_PHY].config_init(phy, params, vars);
6508 /* Re-read this value in case it was changed inside config_init due to
6509 * limitations of optic module
6511 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6513 /* Init external phy*/
6515 if (params->phy[INT_PHY].supported &
6517 vars->link_status |= LINK_STATUS_SERDES_LINK;
6519 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6521 /* No need to initialize second phy in case of first
6522 * phy only selection. In case of second phy, we do
6523 * need to initialize the first phy, since they are
6526 if (params->phy[phy_index].supported &
6528 vars->link_status |= LINK_STATUS_SERDES_LINK;
6530 if (phy_index == EXT_PHY2 &&
6531 (bnx2x_phy_selection(params) ==
6532 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6534 "Not initializing second phy\n");
6537 params->phy[phy_index].config_init(
6538 ¶ms->phy[phy_index],
6542 /* Reset the interrupt indication after phy was initialized */
6543 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6545 (NIG_STATUS_XGXS0_LINK10G |
6546 NIG_STATUS_XGXS0_LINK_STATUS |
6547 NIG_STATUS_SERDES0_LINK_STATUS |
6552 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6553 struct link_params *params)
6555 /* Reset the SerDes/XGXS */
6556 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6557 (0x1ff << (params->port*16)));
6560 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6561 struct link_params *params)
6563 struct bnx2x *bp = params->bp;
6567 gpio_port = BP_PATH(bp);
6569 gpio_port = params->port;
6570 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6571 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6573 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6574 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6576 DP(NETIF_MSG_LINK, "reset external PHY\n");
6579 static int bnx2x_update_link_down(struct link_params *params,
6580 struct link_vars *vars)
6582 struct bnx2x *bp = params->bp;
6583 u8 port = params->port;
6585 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6586 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6587 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6588 /* Indicate no mac active */
6589 vars->mac_type = MAC_TYPE_NONE;
6591 /* Update shared memory */
6592 vars->link_status &= ~LINK_UPDATE_MASK;
6593 vars->line_speed = 0;
6594 bnx2x_update_mng(params, vars->link_status);
6596 /* Activate nig drain */
6597 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6600 if (!CHIP_IS_E3(bp))
6601 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6603 usleep_range(10000, 20000);
6604 /* Reset BigMac/Xmac */
6605 if (CHIP_IS_E1x(bp) ||
6607 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6609 if (CHIP_IS_E3(bp)) {
6610 /* Prevent LPI Generation by chip */
6611 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6613 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6615 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6616 SHMEM_EEE_ACTIVE_BIT);
6618 bnx2x_update_mng_eee(params, vars->eee_status);
6619 bnx2x_set_xmac_rxtx(params, 0);
6620 bnx2x_set_umac_rxtx(params, 0);
6626 static int bnx2x_update_link_up(struct link_params *params,
6627 struct link_vars *vars,
6630 struct bnx2x *bp = params->bp;
6631 u8 phy_idx, port = params->port;
6634 vars->link_status |= (LINK_STATUS_LINK_UP |
6635 LINK_STATUS_PHYSICAL_LINK_FLAG);
6636 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6638 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6639 vars->link_status |=
6640 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6642 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6643 vars->link_status |=
6644 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6645 if (USES_WARPCORE(bp)) {
6647 if (bnx2x_xmac_enable(params, vars, 0) ==
6649 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6651 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6652 vars->link_status &= ~LINK_STATUS_LINK_UP;
6655 bnx2x_umac_enable(params, vars, 0);
6656 bnx2x_set_led(params, vars,
6657 LED_MODE_OPER, vars->line_speed);
6659 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6660 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6661 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6662 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6663 (params->port << 2), 1);
6664 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6665 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6666 (params->port << 2), 0xfc20);
6669 if ((CHIP_IS_E1x(bp) ||
6672 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6674 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6676 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6677 vars->link_status &= ~LINK_STATUS_LINK_UP;
6680 bnx2x_set_led(params, vars,
6681 LED_MODE_OPER, SPEED_10000);
6683 rc = bnx2x_emac_program(params, vars);
6684 bnx2x_emac_enable(params, vars, 0);
6687 if ((vars->link_status &
6688 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6689 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6690 SINGLE_MEDIA_DIRECT(params))
6691 bnx2x_set_gmii_tx_driver(params);
6696 if (CHIP_IS_E1x(bp))
6697 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6701 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6703 /* Update shared memory */
6704 bnx2x_update_mng(params, vars->link_status);
6705 bnx2x_update_mng_eee(params, vars->eee_status);
6706 /* Check remote fault */
6707 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6708 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6709 bnx2x_check_half_open_conn(params, vars, 0);
6716 /* The bnx2x_link_update function should be called upon link
6718 * Link is considered up as follows:
6719 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6721 * - SINGLE_MEDIA - The link between the 577xx and the external
6722 * phy (XGXS) need to up as well as the external link of the
6724 * - DUAL_MEDIA - The link between the 577xx and the first
6725 * external phy needs to be up, and at least one of the 2
6726 * external phy link must be up.
6728 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6730 struct bnx2x *bp = params->bp;
6731 struct link_vars phy_vars[MAX_PHYS];
6732 u8 port = params->port;
6733 u8 link_10g_plus, phy_index;
6734 u8 ext_phy_link_up = 0, cur_link_up;
6737 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6738 u8 active_external_phy = INT_PHY;
6739 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6740 vars->link_status &= ~LINK_UPDATE_MASK;
6741 for (phy_index = INT_PHY; phy_index < params->num_phys;
6743 phy_vars[phy_index].flow_ctrl = 0;
6744 phy_vars[phy_index].link_status = 0;
6745 phy_vars[phy_index].line_speed = 0;
6746 phy_vars[phy_index].duplex = DUPLEX_FULL;
6747 phy_vars[phy_index].phy_link_up = 0;
6748 phy_vars[phy_index].link_up = 0;
6749 phy_vars[phy_index].fault_detected = 0;
6750 /* different consideration, since vars holds inner state */
6751 phy_vars[phy_index].eee_status = vars->eee_status;
6754 if (USES_WARPCORE(bp))
6755 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6757 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6758 port, (vars->phy_flags & PHY_XGXS_FLAG),
6759 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6761 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6763 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6764 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6766 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6768 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6769 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6770 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6773 if (!CHIP_IS_E3(bp))
6774 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6777 * Check external link change only for external phys, and apply
6778 * priority selection between them in case the link on both phys
6779 * is up. Note that instead of the common vars, a temporary
6780 * vars argument is used since each phy may have different link/
6781 * speed/duplex result
6783 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6785 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6786 if (!phy->read_status)
6788 /* Read link status and params of this ext phy */
6789 cur_link_up = phy->read_status(phy, params,
6790 &phy_vars[phy_index]);
6792 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6795 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6800 if (!ext_phy_link_up) {
6801 ext_phy_link_up = 1;
6802 active_external_phy = phy_index;
6804 switch (bnx2x_phy_selection(params)) {
6805 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6806 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6807 /* In this option, the first PHY makes sure to pass the
6808 * traffic through itself only.
6809 * Its not clear how to reset the link on the second phy
6811 active_external_phy = EXT_PHY1;
6813 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6814 /* In this option, the first PHY makes sure to pass the
6815 * traffic through the second PHY.
6817 active_external_phy = EXT_PHY2;
6820 /* Link indication on both PHYs with the following cases
6822 * - FIRST_PHY means that second phy wasn't initialized,
6823 * hence its link is expected to be down
6824 * - SECOND_PHY means that first phy should not be able
6825 * to link up by itself (using configuration)
6826 * - DEFAULT should be overriden during initialiazation
6828 DP(NETIF_MSG_LINK, "Invalid link indication"
6829 "mpc=0x%x. DISABLING LINK !!!\n",
6830 params->multi_phy_config);
6831 ext_phy_link_up = 0;
6836 prev_line_speed = vars->line_speed;
6838 * Read the status of the internal phy. In case of
6839 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6840 * otherwise this is the link between the 577xx and the first
6843 if (params->phy[INT_PHY].read_status)
6844 params->phy[INT_PHY].read_status(
6845 ¶ms->phy[INT_PHY],
6847 /* The INT_PHY flow control reside in the vars. This include the
6848 * case where the speed or flow control are not set to AUTO.
6849 * Otherwise, the active external phy flow control result is set
6850 * to the vars. The ext_phy_line_speed is needed to check if the
6851 * speed is different between the internal phy and external phy.
6852 * This case may be result of intermediate link speed change.
6854 if (active_external_phy > INT_PHY) {
6855 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6856 /* Link speed is taken from the XGXS. AN and FC result from
6859 vars->link_status |= phy_vars[active_external_phy].link_status;
6861 /* if active_external_phy is first PHY and link is up - disable
6862 * disable TX on second external PHY
6864 if (active_external_phy == EXT_PHY1) {
6865 if (params->phy[EXT_PHY2].phy_specific_func) {
6867 "Disabling TX on EXT_PHY2\n");
6868 params->phy[EXT_PHY2].phy_specific_func(
6869 ¶ms->phy[EXT_PHY2],
6870 params, DISABLE_TX);
6874 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6875 vars->duplex = phy_vars[active_external_phy].duplex;
6876 if (params->phy[active_external_phy].supported &
6878 vars->link_status |= LINK_STATUS_SERDES_LINK;
6880 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6882 vars->eee_status = phy_vars[active_external_phy].eee_status;
6884 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6885 active_external_phy);
6888 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6890 if (params->phy[phy_index].flags &
6891 FLAGS_REARM_LATCH_SIGNAL) {
6892 bnx2x_rearm_latch_signal(bp, port,
6894 active_external_phy);
6898 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6899 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6900 vars->link_status, ext_phy_line_speed);
6901 /* Upon link speed change set the NIG into drain mode. Comes to
6902 * deals with possible FIFO glitch due to clk change when speed
6903 * is decreased without link down indicator
6906 if (vars->phy_link_up) {
6907 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6908 (ext_phy_line_speed != vars->line_speed)) {
6909 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6910 " different than the external"
6911 " link speed %d\n", vars->line_speed,
6912 ext_phy_line_speed);
6913 vars->phy_link_up = 0;
6914 } else if (prev_line_speed != vars->line_speed) {
6915 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6917 usleep_range(1000, 2000);
6921 /* Anything 10 and over uses the bmac */
6922 link_10g_plus = (vars->line_speed >= SPEED_10000);
6924 bnx2x_link_int_ack(params, vars, link_10g_plus);
6926 /* In case external phy link is up, and internal link is down
6927 * (not initialized yet probably after link initialization, it
6928 * needs to be initialized.
6929 * Note that after link down-up as result of cable plug, the xgxs
6930 * link would probably become up again without the need
6933 if (!(SINGLE_MEDIA_DIRECT(params))) {
6934 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6935 " init_preceding = %d\n", ext_phy_link_up,
6937 params->phy[EXT_PHY1].flags &
6938 FLAGS_INIT_XGXS_FIRST);
6939 if (!(params->phy[EXT_PHY1].flags &
6940 FLAGS_INIT_XGXS_FIRST)
6941 && ext_phy_link_up && !vars->phy_link_up) {
6942 vars->line_speed = ext_phy_line_speed;
6943 if (vars->line_speed < SPEED_1000)
6944 vars->phy_flags |= PHY_SGMII_FLAG;
6946 vars->phy_flags &= ~PHY_SGMII_FLAG;
6948 if (params->phy[INT_PHY].config_init)
6949 params->phy[INT_PHY].config_init(
6950 ¶ms->phy[INT_PHY], params,
6954 /* Link is up only if both local phy and external phy (in case of
6955 * non-direct board) are up and no fault detected on active PHY.
6957 vars->link_up = (vars->phy_link_up &&
6959 SINGLE_MEDIA_DIRECT(params)) &&
6960 (phy_vars[active_external_phy].fault_detected == 0));
6962 /* Update the PFC configuration in case it was changed */
6963 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6964 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6966 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6969 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6971 rc = bnx2x_update_link_down(params, vars);
6973 /* Update MCP link status was changed */
6974 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6975 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6980 /*****************************************************************************/
6981 /* External Phy section */
6982 /*****************************************************************************/
6983 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6985 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6986 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6987 usleep_range(1000, 2000);
6988 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6989 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6992 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6993 u32 spirom_ver, u32 ver_addr)
6995 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6996 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6999 REG_WR(bp, ver_addr, spirom_ver);
7002 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7003 struct bnx2x_phy *phy,
7006 u16 fw_ver1, fw_ver2;
7008 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7009 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7010 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7011 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7012 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7016 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7017 struct bnx2x_phy *phy,
7018 struct link_vars *vars)
7021 bnx2x_cl45_read(bp, phy,
7023 MDIO_AN_REG_STATUS, &val);
7024 bnx2x_cl45_read(bp, phy,
7026 MDIO_AN_REG_STATUS, &val);
7028 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7029 if ((val & (1<<0)) == 0)
7030 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7033 /******************************************************************/
7034 /* common BCM8073/BCM8727 PHY SECTION */
7035 /******************************************************************/
7036 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7037 struct link_params *params,
7038 struct link_vars *vars)
7040 struct bnx2x *bp = params->bp;
7041 if (phy->req_line_speed == SPEED_10 ||
7042 phy->req_line_speed == SPEED_100) {
7043 vars->flow_ctrl = phy->req_flow_ctrl;
7047 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7048 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7050 u16 ld_pause; /* local */
7051 u16 lp_pause; /* link partner */
7052 bnx2x_cl45_read(bp, phy,
7054 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7056 bnx2x_cl45_read(bp, phy,
7058 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7059 pause_result = (ld_pause &
7060 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7061 pause_result |= (lp_pause &
7062 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7064 bnx2x_pause_resolve(vars, pause_result);
7065 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7069 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7070 struct bnx2x_phy *phy,
7074 u16 fw_ver1, fw_msgout;
7077 /* Boot port from external ROM */
7079 bnx2x_cl45_write(bp, phy,
7081 MDIO_PMA_REG_GEN_CTRL,
7084 /* Ucode reboot and rst */
7085 bnx2x_cl45_write(bp, phy,
7087 MDIO_PMA_REG_GEN_CTRL,
7090 bnx2x_cl45_write(bp, phy,
7092 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7094 /* Reset internal microprocessor */
7095 bnx2x_cl45_write(bp, phy,
7097 MDIO_PMA_REG_GEN_CTRL,
7098 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7100 /* Release srst bit */
7101 bnx2x_cl45_write(bp, phy,
7103 MDIO_PMA_REG_GEN_CTRL,
7104 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7106 /* Delay 100ms per the PHY specifications */
7109 /* 8073 sometimes taking longer to download */
7114 "bnx2x_8073_8727_external_rom_boot port %x:"
7115 "Download failed. fw version = 0x%x\n",
7121 bnx2x_cl45_read(bp, phy,
7123 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7124 bnx2x_cl45_read(bp, phy,
7126 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7128 usleep_range(1000, 2000);
7129 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7130 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7131 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7133 /* Clear ser_boot_ctl bit */
7134 bnx2x_cl45_write(bp, phy,
7136 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7137 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7140 "bnx2x_8073_8727_external_rom_boot port %x:"
7141 "Download complete. fw version = 0x%x\n",
7147 /******************************************************************/
7148 /* BCM8073 PHY SECTION */
7149 /******************************************************************/
7150 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7152 /* This is only required for 8073A1, version 102 only */
7155 /* Read 8073 HW revision*/
7156 bnx2x_cl45_read(bp, phy,
7158 MDIO_PMA_REG_8073_CHIP_REV, &val);
7161 /* No need to workaround in 8073 A1 */
7165 bnx2x_cl45_read(bp, phy,
7167 MDIO_PMA_REG_ROM_VER2, &val);
7169 /* SNR should be applied only for version 0x102 */
7176 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7178 u16 val, cnt, cnt1 ;
7180 bnx2x_cl45_read(bp, phy,
7182 MDIO_PMA_REG_8073_CHIP_REV, &val);
7185 /* No need to workaround in 8073 A1 */
7188 /* XAUI workaround in 8073 A0: */
7190 /* After loading the boot ROM and restarting Autoneg, poll
7194 for (cnt = 0; cnt < 1000; cnt++) {
7195 bnx2x_cl45_read(bp, phy,
7197 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7199 /* If bit [14] = 0 or bit [13] = 0, continue on with
7200 * system initialization (XAUI work-around not required, as
7201 * these bits indicate 2.5G or 1G link up).
7203 if (!(val & (1<<14)) || !(val & (1<<13))) {
7204 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7206 } else if (!(val & (1<<15))) {
7207 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7208 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7209 * MSB (bit15) goes to 1 (indicating that the XAUI
7210 * workaround has completed), then continue on with
7211 * system initialization.
7213 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7214 bnx2x_cl45_read(bp, phy,
7216 MDIO_PMA_REG_8073_XAUI_WA, &val);
7217 if (val & (1<<15)) {
7219 "XAUI workaround has completed\n");
7222 usleep_range(3000, 6000);
7226 usleep_range(3000, 6000);
7228 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7232 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7234 /* Force KR or KX */
7235 bnx2x_cl45_write(bp, phy,
7236 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7237 bnx2x_cl45_write(bp, phy,
7238 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7239 bnx2x_cl45_write(bp, phy,
7240 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7241 bnx2x_cl45_write(bp, phy,
7242 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7245 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7246 struct bnx2x_phy *phy,
7247 struct link_vars *vars)
7250 struct bnx2x *bp = params->bp;
7251 bnx2x_cl45_read(bp, phy,
7252 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7254 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7255 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7256 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7257 if ((vars->ieee_fc &
7258 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7259 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7260 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7262 if ((vars->ieee_fc &
7263 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7264 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7265 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7267 if ((vars->ieee_fc &
7268 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7269 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7270 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7273 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7275 bnx2x_cl45_write(bp, phy,
7276 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7280 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7281 struct link_params *params,
7284 struct bnx2x *bp = params->bp;
7288 bnx2x_cl45_write(bp, phy,
7289 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7290 bnx2x_cl45_write(bp, phy,
7291 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7296 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7297 struct link_params *params,
7298 struct link_vars *vars)
7300 struct bnx2x *bp = params->bp;
7303 DP(NETIF_MSG_LINK, "Init 8073\n");
7306 gpio_port = BP_PATH(bp);
7308 gpio_port = params->port;
7309 /* Restore normal power mode*/
7310 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7311 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7313 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7314 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7316 bnx2x_8073_specific_func(phy, params, PHY_INIT);
7317 bnx2x_8073_set_pause_cl37(params, phy, vars);
7319 bnx2x_cl45_read(bp, phy,
7320 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7322 bnx2x_cl45_read(bp, phy,
7323 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7325 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7327 /* Swap polarity if required - Must be done only in non-1G mode */
7328 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7329 /* Configure the 8073 to swap _P and _N of the KR lines */
7330 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7331 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7332 bnx2x_cl45_read(bp, phy,
7334 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7335 bnx2x_cl45_write(bp, phy,
7337 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7342 /* Enable CL37 BAM */
7343 if (REG_RD(bp, params->shmem_base +
7344 offsetof(struct shmem_region, dev_info.
7345 port_hw_config[params->port].default_cfg)) &
7346 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7348 bnx2x_cl45_read(bp, phy,
7350 MDIO_AN_REG_8073_BAM, &val);
7351 bnx2x_cl45_write(bp, phy,
7353 MDIO_AN_REG_8073_BAM, val | 1);
7354 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7356 if (params->loopback_mode == LOOPBACK_EXT) {
7357 bnx2x_807x_force_10G(bp, phy);
7358 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7361 bnx2x_cl45_write(bp, phy,
7362 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7364 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7365 if (phy->req_line_speed == SPEED_10000) {
7367 } else if (phy->req_line_speed == SPEED_2500) {
7369 /* Note that 2.5G works only when used with 1G
7376 if (phy->speed_cap_mask &
7377 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7380 /* Note that 2.5G works only when used with 1G advertisement */
7381 if (phy->speed_cap_mask &
7382 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7383 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7385 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7388 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7389 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7391 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7392 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7393 (phy->req_line_speed == SPEED_2500)) {
7395 /* Allow 2.5G for A1 and above */
7396 bnx2x_cl45_read(bp, phy,
7397 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7399 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7405 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7409 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7410 /* Add support for CL37 (passive mode) II */
7412 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7413 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7414 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7417 /* Add support for CL37 (passive mode) III */
7418 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7420 /* The SNR will improve about 2db by changing BW and FEE main
7421 * tap. Rest commands are executed after link is up
7422 * Change FFE main cursor to 5 in EDC register
7424 if (bnx2x_8073_is_snr_needed(bp, phy))
7425 bnx2x_cl45_write(bp, phy,
7426 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7429 /* Enable FEC (Forware Error Correction) Request in the AN */
7430 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7432 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7434 bnx2x_ext_phy_set_pause(params, phy, vars);
7436 /* Restart autoneg */
7438 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7439 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7440 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7444 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7445 struct link_params *params,
7446 struct link_vars *vars)
7448 struct bnx2x *bp = params->bp;
7451 u16 link_status = 0;
7452 u16 an1000_status = 0;
7454 bnx2x_cl45_read(bp, phy,
7455 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7457 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7459 /* Clear the interrupt LASI status register */
7460 bnx2x_cl45_read(bp, phy,
7461 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7462 bnx2x_cl45_read(bp, phy,
7463 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7464 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7466 bnx2x_cl45_read(bp, phy,
7467 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7469 /* Check the LASI */
7470 bnx2x_cl45_read(bp, phy,
7471 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7473 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7475 /* Check the link status */
7476 bnx2x_cl45_read(bp, phy,
7477 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7478 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7480 bnx2x_cl45_read(bp, phy,
7481 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7482 bnx2x_cl45_read(bp, phy,
7483 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7484 link_up = ((val1 & 4) == 4);
7485 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7488 ((phy->req_line_speed != SPEED_10000))) {
7489 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7492 bnx2x_cl45_read(bp, phy,
7493 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7494 bnx2x_cl45_read(bp, phy,
7495 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7497 /* Check the link status on 1.1.2 */
7498 bnx2x_cl45_read(bp, phy,
7499 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7500 bnx2x_cl45_read(bp, phy,
7501 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7502 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7503 "an_link_status=0x%x\n", val2, val1, an1000_status);
7505 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7506 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7507 /* The SNR will improve about 2dbby changing the BW and FEE main
7508 * tap. The 1st write to change FFE main tap is set before
7509 * restart AN. Change PLL Bandwidth in EDC register
7511 bnx2x_cl45_write(bp, phy,
7512 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7515 /* Change CDR Bandwidth in EDC register */
7516 bnx2x_cl45_write(bp, phy,
7517 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7520 bnx2x_cl45_read(bp, phy,
7521 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7524 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7525 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7527 vars->line_speed = SPEED_10000;
7528 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7530 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7532 vars->line_speed = SPEED_2500;
7533 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7535 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7537 vars->line_speed = SPEED_1000;
7538 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7542 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7547 /* Swap polarity if required */
7548 if (params->lane_config &
7549 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7550 /* Configure the 8073 to swap P and N of the KR lines */
7551 bnx2x_cl45_read(bp, phy,
7553 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7554 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7555 * when it`s in 10G mode.
7557 if (vars->line_speed == SPEED_1000) {
7558 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7564 bnx2x_cl45_write(bp, phy,
7566 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7569 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7570 bnx2x_8073_resolve_fc(phy, params, vars);
7571 vars->duplex = DUPLEX_FULL;
7574 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7575 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7576 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7579 vars->link_status |=
7580 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7582 vars->link_status |=
7583 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7589 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7590 struct link_params *params)
7592 struct bnx2x *bp = params->bp;
7595 gpio_port = BP_PATH(bp);
7597 gpio_port = params->port;
7598 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7600 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7601 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7605 /******************************************************************/
7606 /* BCM8705 PHY SECTION */
7607 /******************************************************************/
7608 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7609 struct link_params *params,
7610 struct link_vars *vars)
7612 struct bnx2x *bp = params->bp;
7613 DP(NETIF_MSG_LINK, "init 8705\n");
7614 /* Restore normal power mode*/
7615 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7616 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7618 bnx2x_ext_phy_hw_reset(bp, params->port);
7619 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7620 bnx2x_wait_reset_complete(bp, phy, params);
7622 bnx2x_cl45_write(bp, phy,
7623 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7624 bnx2x_cl45_write(bp, phy,
7625 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7626 bnx2x_cl45_write(bp, phy,
7627 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7628 bnx2x_cl45_write(bp, phy,
7629 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7630 /* BCM8705 doesn't have microcode, hence the 0 */
7631 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7635 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7636 struct link_params *params,
7637 struct link_vars *vars)
7641 struct bnx2x *bp = params->bp;
7642 DP(NETIF_MSG_LINK, "read status 8705\n");
7643 bnx2x_cl45_read(bp, phy,
7644 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7645 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7647 bnx2x_cl45_read(bp, phy,
7648 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7649 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7651 bnx2x_cl45_read(bp, phy,
7652 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7654 bnx2x_cl45_read(bp, phy,
7655 MDIO_PMA_DEVAD, 0xc809, &val1);
7656 bnx2x_cl45_read(bp, phy,
7657 MDIO_PMA_DEVAD, 0xc809, &val1);
7659 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7660 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7662 vars->line_speed = SPEED_10000;
7663 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7668 /******************************************************************/
7669 /* SFP+ module Section */
7670 /******************************************************************/
7671 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7672 struct bnx2x_phy *phy,
7675 struct bnx2x *bp = params->bp;
7676 /* Disable transmitter only for bootcodes which can enable it afterwards
7680 if (params->feature_config_flags &
7681 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7682 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7684 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7688 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7689 bnx2x_cl45_write(bp, phy,
7691 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7694 static u8 bnx2x_get_gpio_port(struct link_params *params)
7697 u32 swap_val, swap_override;
7698 struct bnx2x *bp = params->bp;
7700 gpio_port = BP_PATH(bp);
7702 gpio_port = params->port;
7703 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7704 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7705 return gpio_port ^ (swap_val && swap_override);
7708 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7709 struct bnx2x_phy *phy,
7713 u8 port = params->port;
7714 struct bnx2x *bp = params->bp;
7717 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7718 tx_en_mode = REG_RD(bp, params->shmem_base +
7719 offsetof(struct shmem_region,
7720 dev_info.port_hw_config[port].sfp_ctrl)) &
7721 PORT_HW_CFG_TX_LASER_MASK;
7722 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7723 "mode = %x\n", tx_en, port, tx_en_mode);
7724 switch (tx_en_mode) {
7725 case PORT_HW_CFG_TX_LASER_MDIO:
7727 bnx2x_cl45_read(bp, phy,
7729 MDIO_PMA_REG_PHY_IDENTIFIER,
7737 bnx2x_cl45_write(bp, phy,
7739 MDIO_PMA_REG_PHY_IDENTIFIER,
7742 case PORT_HW_CFG_TX_LASER_GPIO0:
7743 case PORT_HW_CFG_TX_LASER_GPIO1:
7744 case PORT_HW_CFG_TX_LASER_GPIO2:
7745 case PORT_HW_CFG_TX_LASER_GPIO3:
7748 u8 gpio_port, gpio_mode;
7750 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7752 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7754 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7755 gpio_port = bnx2x_get_gpio_port(params);
7756 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7760 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7765 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7766 struct bnx2x_phy *phy,
7769 struct bnx2x *bp = params->bp;
7770 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7772 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7774 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7777 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7778 struct link_params *params,
7779 u8 dev_addr, u16 addr, u8 byte_cnt,
7780 u8 *o_buf, u8 is_init)
7782 struct bnx2x *bp = params->bp;
7785 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7787 "Reading from eeprom is limited to 0xf\n");
7790 /* Set the read command byte count */
7791 bnx2x_cl45_write(bp, phy,
7792 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7793 (byte_cnt | (dev_addr << 8)));
7795 /* Set the read command address */
7796 bnx2x_cl45_write(bp, phy,
7797 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7800 /* Activate read command */
7801 bnx2x_cl45_write(bp, phy,
7802 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7805 /* Wait up to 500us for command complete status */
7806 for (i = 0; i < 100; i++) {
7807 bnx2x_cl45_read(bp, phy,
7809 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7810 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7811 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7816 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7817 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7819 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7820 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7824 /* Read the buffer */
7825 for (i = 0; i < byte_cnt; i++) {
7826 bnx2x_cl45_read(bp, phy,
7828 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7829 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7832 for (i = 0; i < 100; i++) {
7833 bnx2x_cl45_read(bp, phy,
7835 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7836 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7837 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7839 usleep_range(1000, 2000);
7844 static void bnx2x_warpcore_power_module(struct link_params *params,
7848 struct bnx2x *bp = params->bp;
7850 pin_cfg = (REG_RD(bp, params->shmem_base +
7851 offsetof(struct shmem_region,
7852 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7853 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7854 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7856 if (pin_cfg == PIN_CFG_NA)
7858 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7860 /* Low ==> corresponding SFP+ module is powered
7861 * high ==> the SFP+ module is powered down
7863 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7865 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7866 struct link_params *params,
7868 u16 addr, u8 byte_cnt,
7869 u8 *o_buf, u8 is_init)
7872 u8 i, j = 0, cnt = 0;
7875 struct bnx2x *bp = params->bp;
7877 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7879 "Reading from eeprom is limited to 16 bytes\n");
7883 /* 4 byte aligned address */
7884 addr32 = addr & (~0x3);
7886 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7887 bnx2x_warpcore_power_module(params, 0);
7888 /* Note that 100us are not enough here */
7889 usleep_range(1000, 2000);
7890 bnx2x_warpcore_power_module(params, 1);
7892 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7894 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7897 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7898 o_buf[j] = *((u8 *)data_array + i);
7906 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7907 struct link_params *params,
7908 u8 dev_addr, u16 addr, u8 byte_cnt,
7909 u8 *o_buf, u8 is_init)
7911 struct bnx2x *bp = params->bp;
7914 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7916 "Reading from eeprom is limited to 0xf\n");
7920 /* Set 2-wire transfer rate of SFP+ module EEPROM
7921 * to 100Khz since some DACs(direct attached cables) do
7922 * not work at 400Khz.
7924 bnx2x_cl45_write(bp, phy,
7926 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7927 ((dev_addr << 8) | 1));
7929 /* Need to read from 1.8000 to clear it */
7930 bnx2x_cl45_read(bp, phy,
7932 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7935 /* Set the read command byte count */
7936 bnx2x_cl45_write(bp, phy,
7938 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7939 ((byte_cnt < 2) ? 2 : byte_cnt));
7941 /* Set the read command address */
7942 bnx2x_cl45_write(bp, phy,
7944 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7946 /* Set the destination address */
7947 bnx2x_cl45_write(bp, phy,
7950 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7952 /* Activate read command */
7953 bnx2x_cl45_write(bp, phy,
7955 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7957 /* Wait appropriate time for two-wire command to finish before
7958 * polling the status register
7960 usleep_range(1000, 2000);
7962 /* Wait up to 500us for command complete status */
7963 for (i = 0; i < 100; i++) {
7964 bnx2x_cl45_read(bp, phy,
7966 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7967 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7968 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7973 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7974 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7976 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7977 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7981 /* Read the buffer */
7982 for (i = 0; i < byte_cnt; i++) {
7983 bnx2x_cl45_read(bp, phy,
7985 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7986 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7989 for (i = 0; i < 100; i++) {
7990 bnx2x_cl45_read(bp, phy,
7992 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7993 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7994 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7996 usleep_range(1000, 2000);
8001 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8002 struct link_params *params, u8 dev_addr,
8003 u16 addr, u16 byte_cnt, u8 *o_buf)
8006 struct bnx2x *bp = params->bp;
8008 u8 *user_data = o_buf;
8009 read_sfp_module_eeprom_func_p read_func;
8011 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8012 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8016 switch (phy->type) {
8017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8018 read_func = bnx2x_8726_read_sfp_module_eeprom;
8020 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8021 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8022 read_func = bnx2x_8727_read_sfp_module_eeprom;
8024 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8025 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8031 while (!rc && (byte_cnt > 0)) {
8032 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8033 SFP_EEPROM_PAGE_SIZE : byte_cnt;
8034 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8036 byte_cnt -= xfer_size;
8037 user_data += xfer_size;
8043 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8044 struct link_params *params,
8047 struct bnx2x *bp = params->bp;
8048 u32 sync_offset = 0, phy_idx, media_types;
8049 u8 gport, val[2], check_limiting_mode = 0;
8050 *edc_mode = EDC_MODE_LIMITING;
8051 phy->media_type = ETH_PHY_UNSPECIFIED;
8052 /* First check for copper cable */
8053 if (bnx2x_read_sfp_module_eeprom(phy,
8056 SFP_EEPROM_CON_TYPE_ADDR,
8059 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8064 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8066 u8 copper_module_type;
8067 phy->media_type = ETH_PHY_DA_TWINAX;
8068 /* Check if its active cable (includes SFP+ module)
8071 if (bnx2x_read_sfp_module_eeprom(phy,
8074 SFP_EEPROM_FC_TX_TECH_ADDR,
8076 &copper_module_type) != 0) {
8078 "Failed to read copper-cable-type"
8079 " from SFP+ EEPROM\n");
8083 if (copper_module_type &
8084 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8085 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8086 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8087 *edc_mode = EDC_MODE_ACTIVE_DAC;
8089 check_limiting_mode = 1;
8091 *edc_mode = EDC_MODE_PASSIVE_DAC;
8092 /* Even in case PASSIVE_DAC indication is not set,
8093 * treat it as a passive DAC cable, since some cables
8094 * don't have this indication.
8096 if (copper_module_type &
8097 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8099 "Passive Copper cable detected\n");
8102 "Unknown copper-cable-type\n");
8107 case SFP_EEPROM_CON_TYPE_VAL_LC:
8108 case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8109 check_limiting_mode = 1;
8110 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8111 SFP_EEPROM_COMP_CODE_LR_MASK |
8112 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8113 DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8114 gport = params->port;
8115 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8116 if (phy->req_line_speed != SPEED_1000) {
8117 phy->req_line_speed = SPEED_1000;
8118 if (!CHIP_IS_E1x(bp)) {
8119 gport = BP_PATH(bp) +
8120 (params->port << 1);
8123 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8127 int idx, cfg_idx = 0;
8128 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8129 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8130 if (params->phy[idx].type == phy->type) {
8131 cfg_idx = LINK_CONFIG_IDX(idx);
8135 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8136 phy->req_line_speed = params->req_line_speed[cfg_idx];
8140 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8144 sync_offset = params->shmem_base +
8145 offsetof(struct shmem_region,
8146 dev_info.port_hw_config[params->port].media_type);
8147 media_types = REG_RD(bp, sync_offset);
8148 /* Update media type for non-PMF sync */
8149 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8150 if (&(params->phy[phy_idx]) == phy) {
8151 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8152 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8153 media_types |= ((phy->media_type &
8154 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8155 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8159 REG_WR(bp, sync_offset, media_types);
8160 if (check_limiting_mode) {
8161 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8162 if (bnx2x_read_sfp_module_eeprom(phy,
8165 SFP_EEPROM_OPTIONS_ADDR,
8166 SFP_EEPROM_OPTIONS_SIZE,
8169 "Failed to read Option field from module EEPROM\n");
8172 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8173 *edc_mode = EDC_MODE_LINEAR;
8175 *edc_mode = EDC_MODE_LIMITING;
8177 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8180 /* This function read the relevant field from the module (SFP+), and verify it
8181 * is compliant with this board
8183 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8184 struct link_params *params)
8186 struct bnx2x *bp = params->bp;
8188 u32 fw_resp, fw_cmd_param;
8189 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8190 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8191 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8192 val = REG_RD(bp, params->shmem_base +
8193 offsetof(struct shmem_region, dev_info.
8194 port_feature_config[params->port].config));
8195 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8196 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8197 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8201 if (params->feature_config_flags &
8202 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8203 /* Use specific phy request */
8204 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8205 } else if (params->feature_config_flags &
8206 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8207 /* Use first phy request only in case of non-dual media*/
8208 if (DUAL_MEDIA(params)) {
8210 "FW does not support OPT MDL verification\n");
8213 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8215 /* No support in OPT MDL detection */
8217 "FW does not support OPT MDL verification\n");
8221 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8222 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8223 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8224 DP(NETIF_MSG_LINK, "Approved module\n");
8228 /* Format the warning message */
8229 if (bnx2x_read_sfp_module_eeprom(phy,
8232 SFP_EEPROM_VENDOR_NAME_ADDR,
8233 SFP_EEPROM_VENDOR_NAME_SIZE,
8235 vendor_name[0] = '\0';
8237 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8238 if (bnx2x_read_sfp_module_eeprom(phy,
8241 SFP_EEPROM_PART_NO_ADDR,
8242 SFP_EEPROM_PART_NO_SIZE,
8244 vendor_pn[0] = '\0';
8246 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8248 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8249 " Port %d from %s part number %s\n",
8250 params->port, vendor_name, vendor_pn);
8251 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8252 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8253 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8257 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8258 struct link_params *params)
8263 struct bnx2x *bp = params->bp;
8265 /* Initialization time after hot-plug may take up to 300ms for
8266 * some phys type ( e.g. JDSU )
8269 for (timeout = 0; timeout < 60; timeout++) {
8270 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8271 rc = bnx2x_warpcore_read_sfp_module_eeprom(
8272 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8275 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8280 "SFP+ module initialization took %d ms\n",
8284 usleep_range(5000, 10000);
8286 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8291 static void bnx2x_8727_power_module(struct bnx2x *bp,
8292 struct bnx2x_phy *phy,
8294 /* Make sure GPIOs are not using for LED mode */
8296 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8297 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8299 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8300 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8301 * where the 1st bit is the over-current(only input), and 2nd bit is
8302 * for power( only output )
8304 * In case of NOC feature is disabled and power is up, set GPIO control
8305 * as input to enable listening of over-current indication
8307 if (phy->flags & FLAGS_NOC)
8312 /* Set GPIO control to OUTPUT, and set the power bit
8313 * to according to the is_power_up
8317 bnx2x_cl45_write(bp, phy,
8319 MDIO_PMA_REG_8727_GPIO_CTRL,
8323 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8324 struct bnx2x_phy *phy,
8327 u16 cur_limiting_mode;
8329 bnx2x_cl45_read(bp, phy,
8331 MDIO_PMA_REG_ROM_VER2,
8332 &cur_limiting_mode);
8333 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8336 if (edc_mode == EDC_MODE_LIMITING) {
8337 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8338 bnx2x_cl45_write(bp, phy,
8340 MDIO_PMA_REG_ROM_VER2,
8342 } else { /* LRM mode ( default )*/
8344 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8346 /* Changing to LRM mode takes quite few seconds. So do it only
8347 * if current mode is limiting (default is LRM)
8349 if (cur_limiting_mode != EDC_MODE_LIMITING)
8352 bnx2x_cl45_write(bp, phy,
8354 MDIO_PMA_REG_LRM_MODE,
8356 bnx2x_cl45_write(bp, phy,
8358 MDIO_PMA_REG_ROM_VER2,
8360 bnx2x_cl45_write(bp, phy,
8362 MDIO_PMA_REG_MISC_CTRL0,
8364 bnx2x_cl45_write(bp, phy,
8366 MDIO_PMA_REG_LRM_MODE,
8372 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8373 struct bnx2x_phy *phy,
8378 bnx2x_cl45_read(bp, phy,
8380 MDIO_PMA_REG_PHY_IDENTIFIER,
8383 bnx2x_cl45_write(bp, phy,
8385 MDIO_PMA_REG_PHY_IDENTIFIER,
8386 (phy_identifier & ~(1<<9)));
8388 bnx2x_cl45_read(bp, phy,
8390 MDIO_PMA_REG_ROM_VER2,
8392 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8393 bnx2x_cl45_write(bp, phy,
8395 MDIO_PMA_REG_ROM_VER2,
8396 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8398 bnx2x_cl45_write(bp, phy,
8400 MDIO_PMA_REG_PHY_IDENTIFIER,
8401 (phy_identifier | (1<<9)));
8406 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8407 struct link_params *params,
8410 struct bnx2x *bp = params->bp;
8414 bnx2x_sfp_set_transmitter(params, phy, 0);
8417 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8418 bnx2x_sfp_set_transmitter(params, phy, 1);
8421 bnx2x_cl45_write(bp, phy,
8422 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8424 bnx2x_cl45_write(bp, phy,
8425 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8427 bnx2x_cl45_write(bp, phy,
8428 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8429 /* Make MOD_ABS give interrupt on change */
8430 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8431 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8434 if (phy->flags & FLAGS_NOC)
8436 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8437 * status which reflect SFP+ module over-current
8439 if (!(phy->flags & FLAGS_NOC))
8440 val &= 0xff8f; /* Reset bits 4-6 */
8441 bnx2x_cl45_write(bp, phy,
8442 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8446 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8452 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8455 struct bnx2x *bp = params->bp;
8457 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8458 offsetof(struct shmem_region,
8459 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8460 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8461 switch (fault_led_gpio) {
8462 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8464 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8465 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8466 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8467 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8469 u8 gpio_port = bnx2x_get_gpio_port(params);
8470 u16 gpio_pin = fault_led_gpio -
8471 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8472 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8473 "pin %x port %x mode %x\n",
8474 gpio_pin, gpio_port, gpio_mode);
8475 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8479 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8484 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8488 u8 port = params->port;
8489 struct bnx2x *bp = params->bp;
8490 pin_cfg = (REG_RD(bp, params->shmem_base +
8491 offsetof(struct shmem_region,
8492 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8493 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8494 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8495 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8496 gpio_mode, pin_cfg);
8497 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8500 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8503 struct bnx2x *bp = params->bp;
8504 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8505 if (CHIP_IS_E3(bp)) {
8506 /* Low ==> if SFP+ module is supported otherwise
8507 * High ==> if SFP+ module is not on the approved vendor list
8509 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8511 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8514 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8515 struct link_params *params)
8517 struct bnx2x *bp = params->bp;
8518 bnx2x_warpcore_power_module(params, 0);
8519 /* Put Warpcore in low power mode */
8520 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8522 /* Put LCPLL in low power mode */
8523 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8524 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8525 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8528 static void bnx2x_power_sfp_module(struct link_params *params,
8529 struct bnx2x_phy *phy,
8532 struct bnx2x *bp = params->bp;
8533 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8535 switch (phy->type) {
8536 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8537 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8538 bnx2x_8727_power_module(params->bp, phy, power);
8540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8541 bnx2x_warpcore_power_module(params, power);
8547 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8548 struct bnx2x_phy *phy,
8552 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8553 struct bnx2x *bp = params->bp;
8555 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8556 /* This is a global register which controls all lanes */
8557 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8558 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8559 val &= ~(0xf << (lane << 2));
8562 case EDC_MODE_LINEAR:
8563 case EDC_MODE_LIMITING:
8564 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8566 case EDC_MODE_PASSIVE_DAC:
8567 case EDC_MODE_ACTIVE_DAC:
8568 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8574 val |= (mode << (lane << 2));
8575 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8576 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8578 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8579 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8581 /* Restart microcode to re-read the new mode */
8582 bnx2x_warpcore_reset_lane(bp, phy, 1);
8583 bnx2x_warpcore_reset_lane(bp, phy, 0);
8587 static void bnx2x_set_limiting_mode(struct link_params *params,
8588 struct bnx2x_phy *phy,
8591 switch (phy->type) {
8592 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8593 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8595 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8596 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8597 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8599 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8600 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8605 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8606 struct link_params *params)
8608 struct bnx2x *bp = params->bp;
8612 u32 val = REG_RD(bp, params->shmem_base +
8613 offsetof(struct shmem_region, dev_info.
8614 port_feature_config[params->port].config));
8615 /* Enabled transmitter by default */
8616 bnx2x_sfp_set_transmitter(params, phy, 1);
8617 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8619 /* Power up module */
8620 bnx2x_power_sfp_module(params, phy, 1);
8621 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8622 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8624 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8625 /* Check SFP+ module compatibility */
8626 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8628 /* Turn on fault module-detected led */
8629 bnx2x_set_sfp_module_fault_led(params,
8630 MISC_REGISTERS_GPIO_HIGH);
8632 /* Check if need to power down the SFP+ module */
8633 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8634 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8635 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8636 bnx2x_power_sfp_module(params, phy, 0);
8640 /* Turn off fault module-detected led */
8641 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8644 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8645 * is done automatically
8647 bnx2x_set_limiting_mode(params, phy, edc_mode);
8649 /* Disable transmit for this module if the module is not approved, and
8650 * laser needs to be disabled.
8653 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8654 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8655 bnx2x_sfp_set_transmitter(params, phy, 0);
8660 void bnx2x_handle_module_detect_int(struct link_params *params)
8662 struct bnx2x *bp = params->bp;
8663 struct bnx2x_phy *phy;
8665 u8 gpio_num, gpio_port;
8666 if (CHIP_IS_E3(bp)) {
8667 phy = ¶ms->phy[INT_PHY];
8668 /* Always enable TX laser,will be disabled in case of fault */
8669 bnx2x_sfp_set_transmitter(params, phy, 1);
8671 phy = ¶ms->phy[EXT_PHY1];
8673 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8674 params->port, &gpio_num, &gpio_port) ==
8676 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8680 /* Set valid module led off */
8681 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8683 /* Get current gpio val reflecting module plugged in / out*/
8684 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8686 /* Call the handling function in case module is detected */
8687 if (gpio_val == 0) {
8688 bnx2x_set_mdio_emac_per_phy(bp, params);
8689 bnx2x_set_aer_mmd(params, phy);
8691 bnx2x_power_sfp_module(params, phy, 1);
8692 bnx2x_set_gpio_int(bp, gpio_num,
8693 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8695 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8696 bnx2x_sfp_module_detection(phy, params);
8697 if (CHIP_IS_E3(bp)) {
8699 /* In case WC is out of reset, reconfigure the
8700 * link speed while taking into account 1G
8701 * module limitation.
8703 bnx2x_cl45_read(bp, phy,
8705 MDIO_WC_REG_DIGITAL5_MISC6,
8707 if ((!rx_tx_in_reset) &&
8708 (params->link_flags &
8710 bnx2x_warpcore_reset_lane(bp, phy, 1);
8711 bnx2x_warpcore_config_sfi(phy, params);
8712 bnx2x_warpcore_reset_lane(bp, phy, 0);
8716 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8719 bnx2x_set_gpio_int(bp, gpio_num,
8720 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8722 /* Module was plugged out.
8723 * Disable transmit for this module
8725 phy->media_type = ETH_PHY_NOT_PRESENT;
8729 /******************************************************************/
8730 /* Used by 8706 and 8727 */
8731 /******************************************************************/
8732 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8733 struct bnx2x_phy *phy,
8734 u16 alarm_status_offset,
8735 u16 alarm_ctrl_offset)
8737 u16 alarm_status, val;
8738 bnx2x_cl45_read(bp, phy,
8739 MDIO_PMA_DEVAD, alarm_status_offset,
8741 bnx2x_cl45_read(bp, phy,
8742 MDIO_PMA_DEVAD, alarm_status_offset,
8744 /* Mask or enable the fault event. */
8745 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8746 if (alarm_status & (1<<0))
8750 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8752 /******************************************************************/
8753 /* common BCM8706/BCM8726 PHY SECTION */
8754 /******************************************************************/
8755 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8756 struct link_params *params,
8757 struct link_vars *vars)
8760 u16 val1, val2, rx_sd, pcs_status;
8761 struct bnx2x *bp = params->bp;
8762 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8764 bnx2x_cl45_read(bp, phy,
8765 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8767 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8768 MDIO_PMA_LASI_TXCTRL);
8770 /* Clear LASI indication*/
8771 bnx2x_cl45_read(bp, phy,
8772 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8773 bnx2x_cl45_read(bp, phy,
8774 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8775 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8777 bnx2x_cl45_read(bp, phy,
8778 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8779 bnx2x_cl45_read(bp, phy,
8780 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8781 bnx2x_cl45_read(bp, phy,
8782 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8783 bnx2x_cl45_read(bp, phy,
8784 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8786 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8787 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8788 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8789 * are set, or if the autoneg bit 1 is set
8791 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8794 vars->line_speed = SPEED_1000;
8796 vars->line_speed = SPEED_10000;
8797 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8798 vars->duplex = DUPLEX_FULL;
8801 /* Capture 10G link fault. Read twice to clear stale value. */
8802 if (vars->line_speed == SPEED_10000) {
8803 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8804 MDIO_PMA_LASI_TXSTAT, &val1);
8805 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8806 MDIO_PMA_LASI_TXSTAT, &val1);
8808 vars->fault_detected = 1;
8814 /******************************************************************/
8815 /* BCM8706 PHY SECTION */
8816 /******************************************************************/
8817 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8818 struct link_params *params,
8819 struct link_vars *vars)
8823 struct bnx2x *bp = params->bp;
8825 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8826 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8828 bnx2x_ext_phy_hw_reset(bp, params->port);
8829 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8830 bnx2x_wait_reset_complete(bp, phy, params);
8832 /* Wait until fw is loaded */
8833 for (cnt = 0; cnt < 100; cnt++) {
8834 bnx2x_cl45_read(bp, phy,
8835 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8838 usleep_range(10000, 20000);
8840 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8841 if ((params->feature_config_flags &
8842 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8845 for (i = 0; i < 4; i++) {
8846 reg = MDIO_XS_8706_REG_BANK_RX0 +
8847 i*(MDIO_XS_8706_REG_BANK_RX1 -
8848 MDIO_XS_8706_REG_BANK_RX0);
8849 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8850 /* Clear first 3 bits of the control */
8852 /* Set control bits according to configuration */
8853 val |= (phy->rx_preemphasis[i] & 0x7);
8854 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8855 " reg 0x%x <-- val 0x%x\n", reg, val);
8856 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8860 if (phy->req_line_speed == SPEED_10000) {
8861 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8863 bnx2x_cl45_write(bp, phy,
8865 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8866 bnx2x_cl45_write(bp, phy,
8867 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8869 /* Arm LASI for link and Tx fault. */
8870 bnx2x_cl45_write(bp, phy,
8871 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8873 /* Force 1Gbps using autoneg with 1G advertisement */
8875 /* Allow CL37 through CL73 */
8876 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8877 bnx2x_cl45_write(bp, phy,
8878 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8880 /* Enable Full-Duplex advertisement on CL37 */
8881 bnx2x_cl45_write(bp, phy,
8882 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8883 /* Enable CL37 AN */
8884 bnx2x_cl45_write(bp, phy,
8885 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8887 bnx2x_cl45_write(bp, phy,
8888 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8890 /* Enable clause 73 AN */
8891 bnx2x_cl45_write(bp, phy,
8892 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8893 bnx2x_cl45_write(bp, phy,
8894 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8896 bnx2x_cl45_write(bp, phy,
8897 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8900 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8902 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8903 * power mode, if TX Laser is disabled
8906 tx_en_mode = REG_RD(bp, params->shmem_base +
8907 offsetof(struct shmem_region,
8908 dev_info.port_hw_config[params->port].sfp_ctrl))
8909 & PORT_HW_CFG_TX_LASER_MASK;
8911 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8912 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8913 bnx2x_cl45_read(bp, phy,
8914 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8916 bnx2x_cl45_write(bp, phy,
8917 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8923 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8924 struct link_params *params,
8925 struct link_vars *vars)
8927 return bnx2x_8706_8726_read_status(phy, params, vars);
8930 /******************************************************************/
8931 /* BCM8726 PHY SECTION */
8932 /******************************************************************/
8933 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8934 struct link_params *params)
8936 struct bnx2x *bp = params->bp;
8937 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8938 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8941 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8942 struct link_params *params)
8944 struct bnx2x *bp = params->bp;
8945 /* Need to wait 100ms after reset */
8948 /* Micro controller re-boot */
8949 bnx2x_cl45_write(bp, phy,
8950 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8952 /* Set soft reset */
8953 bnx2x_cl45_write(bp, phy,
8955 MDIO_PMA_REG_GEN_CTRL,
8956 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8958 bnx2x_cl45_write(bp, phy,
8960 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8962 bnx2x_cl45_write(bp, phy,
8964 MDIO_PMA_REG_GEN_CTRL,
8965 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8967 /* Wait for 150ms for microcode load */
8970 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8971 bnx2x_cl45_write(bp, phy,
8973 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8976 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8979 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8980 struct link_params *params,
8981 struct link_vars *vars)
8983 struct bnx2x *bp = params->bp;
8985 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8987 bnx2x_cl45_read(bp, phy,
8988 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8990 if (val1 & (1<<15)) {
8991 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8993 vars->line_speed = 0;
9000 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9001 struct link_params *params,
9002 struct link_vars *vars)
9004 struct bnx2x *bp = params->bp;
9005 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9007 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9008 bnx2x_wait_reset_complete(bp, phy, params);
9010 bnx2x_8726_external_rom_boot(phy, params);
9012 /* Need to call module detected on initialization since the module
9013 * detection triggered by actual module insertion might occur before
9014 * driver is loaded, and when driver is loaded, it reset all
9015 * registers, including the transmitter
9017 bnx2x_sfp_module_detection(phy, params);
9019 if (phy->req_line_speed == SPEED_1000) {
9020 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9021 bnx2x_cl45_write(bp, phy,
9022 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9023 bnx2x_cl45_write(bp, phy,
9024 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9025 bnx2x_cl45_write(bp, phy,
9026 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9027 bnx2x_cl45_write(bp, phy,
9028 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9030 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9031 (phy->speed_cap_mask &
9032 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9033 ((phy->speed_cap_mask &
9034 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9035 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9036 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9037 /* Set Flow control */
9038 bnx2x_ext_phy_set_pause(params, phy, vars);
9039 bnx2x_cl45_write(bp, phy,
9040 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9041 bnx2x_cl45_write(bp, phy,
9042 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9043 bnx2x_cl45_write(bp, phy,
9044 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9045 bnx2x_cl45_write(bp, phy,
9046 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9047 bnx2x_cl45_write(bp, phy,
9048 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9049 /* Enable RX-ALARM control to receive interrupt for 1G speed
9052 bnx2x_cl45_write(bp, phy,
9053 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9054 bnx2x_cl45_write(bp, phy,
9055 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9058 } else { /* Default 10G. Set only LASI control */
9059 bnx2x_cl45_write(bp, phy,
9060 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9063 /* Set TX PreEmphasis if needed */
9064 if ((params->feature_config_flags &
9065 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9067 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9068 phy->tx_preemphasis[0],
9069 phy->tx_preemphasis[1]);
9070 bnx2x_cl45_write(bp, phy,
9072 MDIO_PMA_REG_8726_TX_CTRL1,
9073 phy->tx_preemphasis[0]);
9075 bnx2x_cl45_write(bp, phy,
9077 MDIO_PMA_REG_8726_TX_CTRL2,
9078 phy->tx_preemphasis[1]);
9085 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9086 struct link_params *params)
9088 struct bnx2x *bp = params->bp;
9089 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9090 /* Set serial boot control for external load */
9091 bnx2x_cl45_write(bp, phy,
9093 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9096 /******************************************************************/
9097 /* BCM8727 PHY SECTION */
9098 /******************************************************************/
9100 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9101 struct link_params *params, u8 mode)
9103 struct bnx2x *bp = params->bp;
9104 u16 led_mode_bitmask = 0;
9105 u16 gpio_pins_bitmask = 0;
9107 /* Only NOC flavor requires to set the LED specifically */
9108 if (!(phy->flags & FLAGS_NOC))
9111 case LED_MODE_FRONT_PANEL_OFF:
9113 led_mode_bitmask = 0;
9114 gpio_pins_bitmask = 0x03;
9117 led_mode_bitmask = 0;
9118 gpio_pins_bitmask = 0x02;
9121 led_mode_bitmask = 0x60;
9122 gpio_pins_bitmask = 0x11;
9125 bnx2x_cl45_read(bp, phy,
9127 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9130 val |= led_mode_bitmask;
9131 bnx2x_cl45_write(bp, phy,
9133 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9135 bnx2x_cl45_read(bp, phy,
9137 MDIO_PMA_REG_8727_GPIO_CTRL,
9140 val |= gpio_pins_bitmask;
9141 bnx2x_cl45_write(bp, phy,
9143 MDIO_PMA_REG_8727_GPIO_CTRL,
9146 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9147 struct link_params *params) {
9148 u32 swap_val, swap_override;
9150 /* The PHY reset is controlled by GPIO 1. Fake the port number
9151 * to cancel the swap done in set_gpio()
9153 struct bnx2x *bp = params->bp;
9154 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9155 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9156 port = (swap_val && swap_override) ^ 1;
9157 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9158 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9161 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9162 struct link_params *params)
9164 struct bnx2x *bp = params->bp;
9166 /* Set option 1G speed */
9167 if ((phy->req_line_speed == SPEED_1000) ||
9168 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9169 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9170 bnx2x_cl45_write(bp, phy,
9171 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9172 bnx2x_cl45_write(bp, phy,
9173 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9174 bnx2x_cl45_read(bp, phy,
9175 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9176 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9177 /* Power down the XAUI until link is up in case of dual-media
9180 if (DUAL_MEDIA(params)) {
9181 bnx2x_cl45_read(bp, phy,
9183 MDIO_PMA_REG_8727_PCS_GP, &val);
9185 bnx2x_cl45_write(bp, phy,
9187 MDIO_PMA_REG_8727_PCS_GP, val);
9189 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9190 ((phy->speed_cap_mask &
9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9192 ((phy->speed_cap_mask &
9193 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9194 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9196 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9197 bnx2x_cl45_write(bp, phy,
9198 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9199 bnx2x_cl45_write(bp, phy,
9200 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9202 /* Since the 8727 has only single reset pin, need to set the 10G
9203 * registers although it is default
9205 bnx2x_cl45_write(bp, phy,
9206 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9208 bnx2x_cl45_write(bp, phy,
9209 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9210 bnx2x_cl45_write(bp, phy,
9211 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9212 bnx2x_cl45_write(bp, phy,
9213 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9218 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9219 struct link_params *params,
9220 struct link_vars *vars)
9223 u16 tmp1, mod_abs, tmp2;
9224 struct bnx2x *bp = params->bp;
9225 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9227 bnx2x_wait_reset_complete(bp, phy, params);
9229 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9231 bnx2x_8727_specific_func(phy, params, PHY_INIT);
9232 /* Initially configure MOD_ABS to interrupt when module is
9235 bnx2x_cl45_read(bp, phy,
9236 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9237 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9238 * When the EDC is off it locks onto a reference clock and avoids
9242 if (!(phy->flags & FLAGS_NOC))
9244 bnx2x_cl45_write(bp, phy,
9245 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9247 /* Enable/Disable PHY transmitter output */
9248 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9250 bnx2x_8727_power_module(bp, phy, 1);
9252 bnx2x_cl45_read(bp, phy,
9253 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9255 bnx2x_cl45_read(bp, phy,
9256 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9258 bnx2x_8727_config_speed(phy, params);
9261 /* Set TX PreEmphasis if needed */
9262 if ((params->feature_config_flags &
9263 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9264 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9265 phy->tx_preemphasis[0],
9266 phy->tx_preemphasis[1]);
9267 bnx2x_cl45_write(bp, phy,
9268 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9269 phy->tx_preemphasis[0]);
9271 bnx2x_cl45_write(bp, phy,
9272 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9273 phy->tx_preemphasis[1]);
9276 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9277 * power mode, if TX Laser is disabled
9279 tx_en_mode = REG_RD(bp, params->shmem_base +
9280 offsetof(struct shmem_region,
9281 dev_info.port_hw_config[params->port].sfp_ctrl))
9282 & PORT_HW_CFG_TX_LASER_MASK;
9284 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9286 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9287 bnx2x_cl45_read(bp, phy,
9288 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9291 bnx2x_cl45_write(bp, phy,
9292 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9293 bnx2x_cl45_read(bp, phy,
9294 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9296 bnx2x_cl45_write(bp, phy,
9297 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9304 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9305 struct link_params *params)
9307 struct bnx2x *bp = params->bp;
9308 u16 mod_abs, rx_alarm_status;
9309 u32 val = REG_RD(bp, params->shmem_base +
9310 offsetof(struct shmem_region, dev_info.
9311 port_feature_config[params->port].
9313 bnx2x_cl45_read(bp, phy,
9315 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9316 if (mod_abs & (1<<8)) {
9318 /* Module is absent */
9320 "MOD_ABS indication show module is absent\n");
9321 phy->media_type = ETH_PHY_NOT_PRESENT;
9322 /* 1. Set mod_abs to detect next module
9324 * 2. Set EDC off by setting OPTXLOS signal input to low
9326 * When the EDC is off it locks onto a reference clock and
9327 * avoids becoming 'lost'.
9330 if (!(phy->flags & FLAGS_NOC))
9332 bnx2x_cl45_write(bp, phy,
9334 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9336 /* Clear RX alarm since it stays up as long as
9337 * the mod_abs wasn't changed
9339 bnx2x_cl45_read(bp, phy,
9341 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9344 /* Module is present */
9346 "MOD_ABS indication show module is present\n");
9347 /* First disable transmitter, and if the module is ok, the
9348 * module_detection will enable it
9349 * 1. Set mod_abs to detect next module absent event ( bit 8)
9350 * 2. Restore the default polarity of the OPRXLOS signal and
9351 * this signal will then correctly indicate the presence or
9352 * absence of the Rx signal. (bit 9)
9355 if (!(phy->flags & FLAGS_NOC))
9357 bnx2x_cl45_write(bp, phy,
9359 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9361 /* Clear RX alarm since it stays up as long as the mod_abs
9362 * wasn't changed. This is need to be done before calling the
9363 * module detection, otherwise it will clear* the link update
9366 bnx2x_cl45_read(bp, phy,
9368 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9371 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9372 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9373 bnx2x_sfp_set_transmitter(params, phy, 0);
9375 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9376 bnx2x_sfp_module_detection(phy, params);
9378 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9380 /* Reconfigure link speed based on module type limitations */
9381 bnx2x_8727_config_speed(phy, params);
9384 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9386 /* No need to check link status in case of module plugged in/out */
9389 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9390 struct link_params *params,
9391 struct link_vars *vars)
9394 struct bnx2x *bp = params->bp;
9395 u8 link_up = 0, oc_port = params->port;
9396 u16 link_status = 0;
9397 u16 rx_alarm_status, lasi_ctrl, val1;
9399 /* If PHY is not initialized, do not check link status */
9400 bnx2x_cl45_read(bp, phy,
9401 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9406 /* Check the LASI on Rx */
9407 bnx2x_cl45_read(bp, phy,
9408 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9410 vars->line_speed = 0;
9411 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9413 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9414 MDIO_PMA_LASI_TXCTRL);
9416 bnx2x_cl45_read(bp, phy,
9417 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9419 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9422 bnx2x_cl45_read(bp, phy,
9423 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9425 /* If a module is present and there is need to check
9428 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9429 /* Check over-current using 8727 GPIO0 input*/
9430 bnx2x_cl45_read(bp, phy,
9431 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9434 if ((val1 & (1<<8)) == 0) {
9435 if (!CHIP_IS_E1x(bp))
9436 oc_port = BP_PATH(bp) + (params->port << 1);
9438 "8727 Power fault has been detected on port %d\n",
9440 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9441 "been detected and the power to "
9442 "that SFP+ module has been removed "
9443 "to prevent failure of the card. "
9444 "Please remove the SFP+ module and "
9445 "restart the system to clear this "
9448 /* Disable all RX_ALARMs except for mod_abs */
9449 bnx2x_cl45_write(bp, phy,
9451 MDIO_PMA_LASI_RXCTRL, (1<<5));
9453 bnx2x_cl45_read(bp, phy,
9455 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9456 /* Wait for module_absent_event */
9458 bnx2x_cl45_write(bp, phy,
9460 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9461 /* Clear RX alarm */
9462 bnx2x_cl45_read(bp, phy,
9464 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9465 bnx2x_8727_power_module(params->bp, phy, 0);
9468 } /* Over current check */
9470 /* When module absent bit is set, check module */
9471 if (rx_alarm_status & (1<<5)) {
9472 bnx2x_8727_handle_mod_abs(phy, params);
9473 /* Enable all mod_abs and link detection bits */
9474 bnx2x_cl45_write(bp, phy,
9475 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9479 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9480 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9481 bnx2x_sfp_set_transmitter(params, phy, 1);
9483 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9487 bnx2x_cl45_read(bp, phy,
9489 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9491 /* Bits 0..2 --> speed detected,
9492 * Bits 13..15--> link is down
9494 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9496 vars->line_speed = SPEED_10000;
9497 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9499 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9501 vars->line_speed = SPEED_1000;
9502 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9506 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9510 /* Capture 10G link fault. */
9511 if (vars->line_speed == SPEED_10000) {
9512 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9513 MDIO_PMA_LASI_TXSTAT, &val1);
9515 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9516 MDIO_PMA_LASI_TXSTAT, &val1);
9518 if (val1 & (1<<0)) {
9519 vars->fault_detected = 1;
9524 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9525 vars->duplex = DUPLEX_FULL;
9526 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9529 if ((DUAL_MEDIA(params)) &&
9530 (phy->req_line_speed == SPEED_1000)) {
9531 bnx2x_cl45_read(bp, phy,
9533 MDIO_PMA_REG_8727_PCS_GP, &val1);
9534 /* In case of dual-media board and 1G, power up the XAUI side,
9535 * otherwise power it down. For 10G it is done automatically
9541 bnx2x_cl45_write(bp, phy,
9543 MDIO_PMA_REG_8727_PCS_GP, val1);
9548 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9549 struct link_params *params)
9551 struct bnx2x *bp = params->bp;
9553 /* Enable/Disable PHY transmitter output */
9554 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9556 /* Disable Transmitter */
9557 bnx2x_sfp_set_transmitter(params, phy, 0);
9559 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9563 /******************************************************************/
9564 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9565 /******************************************************************/
9566 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9570 u16 val, fw_ver2, cnt, i;
9571 static struct bnx2x_reg_set reg_set[] = {
9572 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9573 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9574 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9575 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9576 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9580 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9581 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9582 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9583 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9586 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9587 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9588 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9589 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9590 reg_set[i].reg, reg_set[i].val);
9592 for (cnt = 0; cnt < 100; cnt++) {
9593 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9599 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9600 "phy fw version(1)\n");
9601 bnx2x_save_spirom_version(bp, port, 0,
9607 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9608 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9609 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9610 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9611 for (cnt = 0; cnt < 100; cnt++) {
9612 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9618 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9620 bnx2x_save_spirom_version(bp, port, 0,
9625 /* lower 16 bits of the register SPI_FW_STATUS */
9626 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9627 /* upper 16 bits of register SPI_FW_STATUS */
9628 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9630 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9635 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9636 struct bnx2x_phy *phy)
9639 static struct bnx2x_reg_set reg_set[] = {
9640 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9641 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9642 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9643 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9644 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9645 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9646 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9648 /* PHYC_CTL_LED_CTL */
9649 bnx2x_cl45_read(bp, phy,
9651 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9655 bnx2x_cl45_write(bp, phy,
9657 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9659 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9660 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9663 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9664 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9665 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9667 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9669 /* stretch_en for LED3*/
9670 bnx2x_cl45_read_or_write(bp, phy,
9671 MDIO_PMA_DEVAD, offset,
9672 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9675 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9676 struct link_params *params,
9679 struct bnx2x *bp = params->bp;
9682 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9683 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9684 /* Save spirom version */
9685 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9687 /* This phy uses the NIG latch mechanism since link indication
9688 * arrives through its LED4 and not via its LASI signal, so we
9689 * get steady signal instead of clear on read
9691 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9692 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9694 bnx2x_848xx_set_led(bp, phy);
9699 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9700 struct link_params *params,
9701 struct link_vars *vars)
9703 struct bnx2x *bp = params->bp;
9704 u16 autoneg_val, an_1000_val, an_10_100_val;
9706 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9707 bnx2x_cl45_write(bp, phy,
9708 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9710 /* set 1000 speed advertisement */
9711 bnx2x_cl45_read(bp, phy,
9712 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9715 bnx2x_ext_phy_set_pause(params, phy, vars);
9716 bnx2x_cl45_read(bp, phy,
9718 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9720 bnx2x_cl45_read(bp, phy,
9721 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9723 /* Disable forced speed */
9724 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9725 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9727 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9728 (phy->speed_cap_mask &
9729 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9730 (phy->req_line_speed == SPEED_1000)) {
9731 an_1000_val |= (1<<8);
9732 autoneg_val |= (1<<9 | 1<<12);
9733 if (phy->req_duplex == DUPLEX_FULL)
9734 an_1000_val |= (1<<9);
9735 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9737 an_1000_val &= ~((1<<8) | (1<<9));
9739 bnx2x_cl45_write(bp, phy,
9740 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9743 /* Set 10/100 speed advertisement */
9744 if (phy->req_line_speed == SPEED_AUTO_NEG) {
9745 if (phy->speed_cap_mask &
9746 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9747 /* Enable autoneg and restart autoneg for legacy speeds
9749 autoneg_val |= (1<<9 | 1<<12);
9750 an_10_100_val |= (1<<8);
9751 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9754 if (phy->speed_cap_mask &
9755 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9756 /* Enable autoneg and restart autoneg for legacy speeds
9758 autoneg_val |= (1<<9 | 1<<12);
9759 an_10_100_val |= (1<<7);
9760 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9763 if ((phy->speed_cap_mask &
9764 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9765 (phy->supported & SUPPORTED_10baseT_Full)) {
9766 an_10_100_val |= (1<<6);
9767 autoneg_val |= (1<<9 | 1<<12);
9768 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9771 if ((phy->speed_cap_mask &
9772 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9773 (phy->supported & SUPPORTED_10baseT_Half)) {
9774 an_10_100_val |= (1<<5);
9775 autoneg_val |= (1<<9 | 1<<12);
9776 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9780 /* Only 10/100 are allowed to work in FORCE mode */
9781 if ((phy->req_line_speed == SPEED_100) &&
9783 (SUPPORTED_100baseT_Half |
9784 SUPPORTED_100baseT_Full))) {
9785 autoneg_val |= (1<<13);
9786 /* Enabled AUTO-MDIX when autoneg is disabled */
9787 bnx2x_cl45_write(bp, phy,
9788 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9789 (1<<15 | 1<<9 | 7<<0));
9790 /* The PHY needs this set even for forced link. */
9791 an_10_100_val |= (1<<8) | (1<<7);
9792 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9794 if ((phy->req_line_speed == SPEED_10) &&
9796 (SUPPORTED_10baseT_Half |
9797 SUPPORTED_10baseT_Full))) {
9798 /* Enabled AUTO-MDIX when autoneg is disabled */
9799 bnx2x_cl45_write(bp, phy,
9800 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9801 (1<<15 | 1<<9 | 7<<0));
9802 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9805 bnx2x_cl45_write(bp, phy,
9806 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9809 if (phy->req_duplex == DUPLEX_FULL)
9810 autoneg_val |= (1<<8);
9812 /* Always write this if this is not 84833/4.
9813 * For 84833/4, write it only when it's a forced speed.
9815 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9816 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9817 ((autoneg_val & (1<<12)) == 0))
9818 bnx2x_cl45_write(bp, phy,
9820 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9822 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9823 (phy->speed_cap_mask &
9824 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9825 (phy->req_line_speed == SPEED_10000)) {
9826 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9827 /* Restart autoneg for 10G*/
9829 bnx2x_cl45_read_or_write(
9832 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9834 bnx2x_cl45_write(bp, phy,
9835 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9838 bnx2x_cl45_write(bp, phy,
9840 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9846 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9847 struct link_params *params,
9848 struct link_vars *vars)
9850 struct bnx2x *bp = params->bp;
9851 /* Restore normal power mode*/
9852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9853 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9856 bnx2x_ext_phy_hw_reset(bp, params->port);
9857 bnx2x_wait_reset_complete(bp, phy, params);
9859 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9860 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9863 #define PHY84833_CMDHDLR_WAIT 300
9864 #define PHY84833_CMDHDLR_MAX_ARGS 5
9865 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9866 struct link_params *params, u16 fw_cmd,
9867 u16 cmd_args[], int argc)
9871 struct bnx2x *bp = params->bp;
9872 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9873 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9874 MDIO_84833_CMD_HDLR_STATUS,
9875 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9876 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9877 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9878 MDIO_84833_CMD_HDLR_STATUS, &val);
9879 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9881 usleep_range(1000, 2000);
9883 if (idx >= PHY84833_CMDHDLR_WAIT) {
9884 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9888 /* Prepare argument(s) and issue command */
9889 for (idx = 0; idx < argc; idx++) {
9890 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9891 MDIO_84833_CMD_HDLR_DATA1 + idx,
9894 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9895 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9896 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9897 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9898 MDIO_84833_CMD_HDLR_STATUS, &val);
9899 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9900 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9902 usleep_range(1000, 2000);
9904 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9905 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9906 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9909 /* Gather returning data */
9910 for (idx = 0; idx < argc; idx++) {
9911 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9912 MDIO_84833_CMD_HDLR_DATA1 + idx,
9915 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9916 MDIO_84833_CMD_HDLR_STATUS,
9917 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9921 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9922 struct link_params *params,
9923 struct link_vars *vars)
9926 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9928 struct bnx2x *bp = params->bp;
9930 /* Check for configuration. */
9931 pair_swap = REG_RD(bp, params->shmem_base +
9932 offsetof(struct shmem_region,
9933 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9934 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9939 /* Only the second argument is used for this command */
9940 data[1] = (u16)pair_swap;
9942 status = bnx2x_84833_cmd_hdlr(phy, params,
9943 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9945 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9950 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9951 u32 shmem_base_path[],
9957 if (CHIP_IS_E3(bp)) {
9958 /* Assume that these will be GPIOs, not EPIOs. */
9959 for (idx = 0; idx < 2; idx++) {
9960 /* Map config param to register bit. */
9961 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9962 offsetof(struct shmem_region,
9963 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9964 reset_pin[idx] = (reset_pin[idx] &
9965 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9966 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9967 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9968 reset_pin[idx] = (1 << reset_pin[idx]);
9970 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9972 /* E2, look from diff place of shmem. */
9973 for (idx = 0; idx < 2; idx++) {
9974 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9975 offsetof(struct shmem_region,
9976 dev_info.port_hw_config[0].default_cfg));
9977 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9978 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9979 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9980 reset_pin[idx] = (1 << reset_pin[idx]);
9982 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9988 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9989 struct link_params *params)
9991 struct bnx2x *bp = params->bp;
9993 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9994 offsetof(struct shmem2_region,
9995 other_shmem_base_addr));
9997 u32 shmem_base_path[2];
9999 /* Work around for 84833 LED failure inside RESET status */
10000 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10001 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10002 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10003 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10004 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10005 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10007 shmem_base_path[0] = params->shmem_base;
10008 shmem_base_path[1] = other_shmem_base_addr;
10010 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10013 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10015 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10021 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10022 struct link_params *params,
10023 struct link_vars *vars)
10026 struct bnx2x *bp = params->bp;
10029 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10031 /* Prevent Phy from working in EEE and advertising it */
10032 rc = bnx2x_84833_cmd_hdlr(phy, params,
10033 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10035 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10039 return bnx2x_eee_disable(phy, params, vars);
10042 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10043 struct link_params *params,
10044 struct link_vars *vars)
10047 struct bnx2x *bp = params->bp;
10050 rc = bnx2x_84833_cmd_hdlr(phy, params,
10051 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10053 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10057 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10060 #define PHY84833_CONSTANT_LATENCY 1193
10061 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10062 struct link_params *params,
10063 struct link_vars *vars)
10065 struct bnx2x *bp = params->bp;
10066 u8 port, initialize = 1;
10068 u32 actual_phy_selection;
10069 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10072 usleep_range(1000, 2000);
10074 if (!(CHIP_IS_E1x(bp)))
10075 port = BP_PATH(bp);
10077 port = params->port;
10079 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10080 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10081 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10085 bnx2x_cl45_write(bp, phy,
10087 MDIO_PMA_REG_CTRL, 0x8000);
10090 bnx2x_wait_reset_complete(bp, phy, params);
10092 /* Wait for GPHY to come out of reset */
10094 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10095 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10096 /* BCM84823 requires that XGXS links up first @ 10G for normal
10100 temp = vars->line_speed;
10101 vars->line_speed = SPEED_10000;
10102 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10103 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10104 vars->line_speed = temp;
10107 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10108 MDIO_CTL_REG_84823_MEDIA, &val);
10109 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10110 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10111 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10112 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10113 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10115 if (CHIP_IS_E3(bp)) {
10116 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10117 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10119 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10120 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10123 actual_phy_selection = bnx2x_phy_selection(params);
10125 switch (actual_phy_selection) {
10126 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10127 /* Do nothing. Essentially this is like the priority copper */
10129 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10130 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10132 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10133 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10135 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10136 /* Do nothing here. The first PHY won't be initialized at all */
10138 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10139 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10143 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10144 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10146 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10147 MDIO_CTL_REG_84823_MEDIA, val);
10148 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10149 params->multi_phy_config, val);
10151 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10152 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10153 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10155 /* Keep AutogrEEEn disabled. */
10158 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10159 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10160 rc = bnx2x_84833_cmd_hdlr(phy, params,
10161 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10162 PHY84833_CMDHDLR_MAX_ARGS);
10164 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10167 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10169 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10170 /* 84833 PHY has a better feature and doesn't need to support this. */
10171 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10172 u32 cms_enable = REG_RD(bp, params->shmem_base +
10173 offsetof(struct shmem_region,
10174 dev_info.port_hw_config[params->port].default_cfg)) &
10175 PORT_HW_CFG_ENABLE_CMS_MASK;
10177 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10178 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10180 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10182 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10183 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10184 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10187 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10188 MDIO_84833_TOP_CFG_FW_REV, &val);
10190 /* Configure EEE support */
10191 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10192 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10193 bnx2x_eee_has_cap(params)) {
10194 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10196 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10197 bnx2x_8483x_disable_eee(phy, params, vars);
10201 if ((phy->req_duplex == DUPLEX_FULL) &&
10202 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10203 (bnx2x_eee_calc_timer(params) ||
10204 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10205 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10207 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10209 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10213 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10216 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10217 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10218 /* Bring PHY out of super isolate mode as the final step. */
10219 bnx2x_cl45_read_and_write(bp, phy,
10221 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10222 (u16)~MDIO_84833_SUPER_ISOLATE);
10227 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10228 struct link_params *params,
10229 struct link_vars *vars)
10231 struct bnx2x *bp = params->bp;
10232 u16 val, val1, val2;
10236 /* Check 10G-BaseT link status */
10237 /* Check PMD signal ok */
10238 bnx2x_cl45_read(bp, phy,
10239 MDIO_AN_DEVAD, 0xFFFA, &val1);
10240 bnx2x_cl45_read(bp, phy,
10241 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10243 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10245 /* Check link 10G */
10246 if (val2 & (1<<11)) {
10247 vars->line_speed = SPEED_10000;
10248 vars->duplex = DUPLEX_FULL;
10250 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10251 } else { /* Check Legacy speed link */
10252 u16 legacy_status, legacy_speed;
10254 /* Enable expansion register 0x42 (Operation mode status) */
10255 bnx2x_cl45_write(bp, phy,
10257 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10259 /* Get legacy speed operation status */
10260 bnx2x_cl45_read(bp, phy,
10262 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10265 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10267 link_up = ((legacy_status & (1<<11)) == (1<<11));
10268 legacy_speed = (legacy_status & (3<<9));
10269 if (legacy_speed == (0<<9))
10270 vars->line_speed = SPEED_10;
10271 else if (legacy_speed == (1<<9))
10272 vars->line_speed = SPEED_100;
10273 else if (legacy_speed == (2<<9))
10274 vars->line_speed = SPEED_1000;
10275 else { /* Should not happen: Treat as link down */
10276 vars->line_speed = 0;
10281 if (legacy_status & (1<<8))
10282 vars->duplex = DUPLEX_FULL;
10284 vars->duplex = DUPLEX_HALF;
10287 "Link is up in %dMbps, is_duplex_full= %d\n",
10289 (vars->duplex == DUPLEX_FULL));
10290 /* Check legacy speed AN resolution */
10291 bnx2x_cl45_read(bp, phy,
10293 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10296 vars->link_status |=
10297 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10298 bnx2x_cl45_read(bp, phy,
10300 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10302 if ((val & (1<<0)) == 0)
10303 vars->link_status |=
10304 LINK_STATUS_PARALLEL_DETECTION_USED;
10308 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10310 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10312 /* Read LP advertised speeds */
10313 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10314 MDIO_AN_REG_CL37_FC_LP, &val);
10316 vars->link_status |=
10317 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10319 vars->link_status |=
10320 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10322 vars->link_status |=
10323 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10325 vars->link_status |=
10326 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10328 vars->link_status |=
10329 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10331 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10332 MDIO_AN_REG_1000T_STATUS, &val);
10335 vars->link_status |=
10336 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10338 vars->link_status |=
10339 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10341 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10342 MDIO_AN_REG_MASTER_STATUS, &val);
10345 vars->link_status |=
10346 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10348 /* Determine if EEE was negotiated */
10349 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10350 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10351 bnx2x_eee_an_resolve(phy, params, vars);
10357 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10361 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10362 status = bnx2x_format_ver(spirom_ver, str, len);
10366 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10367 struct link_params *params)
10369 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10370 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10371 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10372 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10375 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10376 struct link_params *params)
10378 bnx2x_cl45_write(params->bp, phy,
10379 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10380 bnx2x_cl45_write(params->bp, phy,
10381 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10384 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10385 struct link_params *params)
10387 struct bnx2x *bp = params->bp;
10391 if (!(CHIP_IS_E1x(bp)))
10392 port = BP_PATH(bp);
10394 port = params->port;
10396 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10397 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10398 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10401 bnx2x_cl45_read(bp, phy,
10403 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10404 val16 |= MDIO_84833_SUPER_ISOLATE;
10405 bnx2x_cl45_write(bp, phy,
10407 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10411 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10412 struct link_params *params, u8 mode)
10414 struct bnx2x *bp = params->bp;
10418 if (!(CHIP_IS_E1x(bp)))
10419 port = BP_PATH(bp);
10421 port = params->port;
10426 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10428 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10429 SHARED_HW_CFG_LED_EXTPHY1) {
10431 /* Set LED masks */
10432 bnx2x_cl45_write(bp, phy,
10434 MDIO_PMA_REG_8481_LED1_MASK,
10437 bnx2x_cl45_write(bp, phy,
10439 MDIO_PMA_REG_8481_LED2_MASK,
10442 bnx2x_cl45_write(bp, phy,
10444 MDIO_PMA_REG_8481_LED3_MASK,
10447 bnx2x_cl45_write(bp, phy,
10449 MDIO_PMA_REG_8481_LED5_MASK,
10453 bnx2x_cl45_write(bp, phy,
10455 MDIO_PMA_REG_8481_LED1_MASK,
10459 case LED_MODE_FRONT_PANEL_OFF:
10461 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10464 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10465 SHARED_HW_CFG_LED_EXTPHY1) {
10467 /* Set LED masks */
10468 bnx2x_cl45_write(bp, phy,
10470 MDIO_PMA_REG_8481_LED1_MASK,
10473 bnx2x_cl45_write(bp, phy,
10475 MDIO_PMA_REG_8481_LED2_MASK,
10478 bnx2x_cl45_write(bp, phy,
10480 MDIO_PMA_REG_8481_LED3_MASK,
10483 bnx2x_cl45_write(bp, phy,
10485 MDIO_PMA_REG_8481_LED5_MASK,
10489 bnx2x_cl45_write(bp, phy,
10491 MDIO_PMA_REG_8481_LED1_MASK,
10494 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10495 /* Disable MI_INT interrupt before setting LED4
10496 * source to constant off.
10498 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10501 params->link_flags |=
10502 LINK_FLAGS_INT_DISABLED;
10506 NIG_REG_MASK_INTERRUPT_PORT0 +
10510 bnx2x_cl45_write(bp, phy,
10512 MDIO_PMA_REG_8481_SIGNAL_MASK,
10519 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10521 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10522 SHARED_HW_CFG_LED_EXTPHY1) {
10523 /* Set control reg */
10524 bnx2x_cl45_read(bp, phy,
10526 MDIO_PMA_REG_8481_LINK_SIGNAL,
10531 bnx2x_cl45_write(bp, phy,
10533 MDIO_PMA_REG_8481_LINK_SIGNAL,
10536 /* Set LED masks */
10537 bnx2x_cl45_write(bp, phy,
10539 MDIO_PMA_REG_8481_LED1_MASK,
10542 bnx2x_cl45_write(bp, phy,
10544 MDIO_PMA_REG_8481_LED2_MASK,
10547 bnx2x_cl45_write(bp, phy,
10549 MDIO_PMA_REG_8481_LED3_MASK,
10552 bnx2x_cl45_write(bp, phy,
10554 MDIO_PMA_REG_8481_LED5_MASK,
10557 bnx2x_cl45_write(bp, phy,
10559 MDIO_PMA_REG_8481_LED1_MASK,
10562 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10563 /* Disable MI_INT interrupt before setting LED4
10564 * source to constant on.
10566 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10569 params->link_flags |=
10570 LINK_FLAGS_INT_DISABLED;
10574 NIG_REG_MASK_INTERRUPT_PORT0 +
10578 bnx2x_cl45_write(bp, phy,
10580 MDIO_PMA_REG_8481_SIGNAL_MASK,
10586 case LED_MODE_OPER:
10588 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10590 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10591 SHARED_HW_CFG_LED_EXTPHY1) {
10593 /* Set control reg */
10594 bnx2x_cl45_read(bp, phy,
10596 MDIO_PMA_REG_8481_LINK_SIGNAL,
10600 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10601 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10602 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10603 bnx2x_cl45_write(bp, phy,
10605 MDIO_PMA_REG_8481_LINK_SIGNAL,
10609 /* Set LED masks */
10610 bnx2x_cl45_write(bp, phy,
10612 MDIO_PMA_REG_8481_LED1_MASK,
10615 bnx2x_cl45_write(bp, phy,
10617 MDIO_PMA_REG_8481_LED2_MASK,
10620 bnx2x_cl45_write(bp, phy,
10622 MDIO_PMA_REG_8481_LED3_MASK,
10625 bnx2x_cl45_write(bp, phy,
10627 MDIO_PMA_REG_8481_LED5_MASK,
10631 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10632 * sources are all wired through LED1, rather than only
10633 * 10G in other modes.
10635 val = ((params->hw_led_mode <<
10636 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10637 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10639 bnx2x_cl45_write(bp, phy,
10641 MDIO_PMA_REG_8481_LED1_MASK,
10644 /* Tell LED3 to blink on source */
10645 bnx2x_cl45_read(bp, phy,
10647 MDIO_PMA_REG_8481_LINK_SIGNAL,
10650 val |= (1<<6); /* A83B[8:6]= 1 */
10651 bnx2x_cl45_write(bp, phy,
10653 MDIO_PMA_REG_8481_LINK_SIGNAL,
10656 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10657 /* Restore LED4 source to external link,
10658 * and re-enable interrupts.
10660 bnx2x_cl45_write(bp, phy,
10662 MDIO_PMA_REG_8481_SIGNAL_MASK,
10664 if (params->link_flags &
10665 LINK_FLAGS_INT_DISABLED) {
10666 bnx2x_link_int_enable(params);
10667 params->link_flags &=
10668 ~LINK_FLAGS_INT_DISABLED;
10675 /* This is a workaround for E3+84833 until autoneg
10676 * restart is fixed in f/w
10678 if (CHIP_IS_E3(bp)) {
10679 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10680 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10684 /******************************************************************/
10685 /* 54618SE PHY SECTION */
10686 /******************************************************************/
10687 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10688 struct link_params *params,
10691 struct bnx2x *bp = params->bp;
10695 /* Configure LED4: set to INTR (0x6). */
10696 /* Accessing shadow register 0xe. */
10697 bnx2x_cl22_write(bp, phy,
10698 MDIO_REG_GPHY_SHADOW,
10699 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10700 bnx2x_cl22_read(bp, phy,
10701 MDIO_REG_GPHY_SHADOW,
10703 temp &= ~(0xf << 4);
10704 temp |= (0x6 << 4);
10705 bnx2x_cl22_write(bp, phy,
10706 MDIO_REG_GPHY_SHADOW,
10707 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10708 /* Configure INTR based on link status change. */
10709 bnx2x_cl22_write(bp, phy,
10710 MDIO_REG_INTR_MASK,
10711 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10716 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10717 struct link_params *params,
10718 struct link_vars *vars)
10720 struct bnx2x *bp = params->bp;
10722 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10725 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10726 usleep_range(1000, 2000);
10728 /* This works with E3 only, no need to check the chip
10729 * before determining the port.
10731 port = params->port;
10733 cfg_pin = (REG_RD(bp, params->shmem_base +
10734 offsetof(struct shmem_region,
10735 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10736 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10737 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10739 /* Drive pin high to bring the GPHY out of reset. */
10740 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10742 /* wait for GPHY to reset */
10746 bnx2x_cl22_write(bp, phy,
10747 MDIO_PMA_REG_CTRL, 0x8000);
10748 bnx2x_wait_reset_complete(bp, phy, params);
10750 /* Wait for GPHY to reset */
10754 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10755 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10756 bnx2x_cl22_write(bp, phy,
10757 MDIO_REG_GPHY_SHADOW,
10758 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10759 bnx2x_cl22_read(bp, phy,
10760 MDIO_REG_GPHY_SHADOW,
10762 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10763 bnx2x_cl22_write(bp, phy,
10764 MDIO_REG_GPHY_SHADOW,
10765 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10768 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10769 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10771 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10772 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10773 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10775 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10777 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10779 /* Read all advertisement */
10780 bnx2x_cl22_read(bp, phy,
10784 bnx2x_cl22_read(bp, phy,
10788 bnx2x_cl22_read(bp, phy,
10792 /* Disable forced speed */
10793 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10794 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10797 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10798 (phy->speed_cap_mask &
10799 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10800 (phy->req_line_speed == SPEED_1000)) {
10801 an_1000_val |= (1<<8);
10802 autoneg_val |= (1<<9 | 1<<12);
10803 if (phy->req_duplex == DUPLEX_FULL)
10804 an_1000_val |= (1<<9);
10805 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10807 an_1000_val &= ~((1<<8) | (1<<9));
10809 bnx2x_cl22_write(bp, phy,
10812 bnx2x_cl22_read(bp, phy,
10816 /* Advertise 10/100 link speed */
10817 if (phy->req_line_speed == SPEED_AUTO_NEG) {
10818 if (phy->speed_cap_mask &
10819 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10820 an_10_100_val |= (1<<5);
10821 autoneg_val |= (1<<9 | 1<<12);
10822 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
10824 if (phy->speed_cap_mask &
10825 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
10826 an_10_100_val |= (1<<6);
10827 autoneg_val |= (1<<9 | 1<<12);
10828 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
10830 if (phy->speed_cap_mask &
10831 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10832 an_10_100_val |= (1<<7);
10833 autoneg_val |= (1<<9 | 1<<12);
10834 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
10836 if (phy->speed_cap_mask &
10837 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10838 an_10_100_val |= (1<<8);
10839 autoneg_val |= (1<<9 | 1<<12);
10840 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
10844 /* Only 10/100 are allowed to work in FORCE mode */
10845 if (phy->req_line_speed == SPEED_100) {
10846 autoneg_val |= (1<<13);
10847 /* Enabled AUTO-MDIX when autoneg is disabled */
10848 bnx2x_cl22_write(bp, phy,
10850 (1<<15 | 1<<9 | 7<<0));
10851 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10853 if (phy->req_line_speed == SPEED_10) {
10854 /* Enabled AUTO-MDIX when autoneg is disabled */
10855 bnx2x_cl22_write(bp, phy,
10857 (1<<15 | 1<<9 | 7<<0));
10858 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10861 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10864 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10865 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10866 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10867 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10869 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10871 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10873 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10874 bnx2x_eee_disable(phy, params, vars);
10875 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10876 (phy->req_duplex == DUPLEX_FULL) &&
10877 (bnx2x_eee_calc_timer(params) ||
10878 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10879 /* Need to advertise EEE only when requested,
10880 * and either no LPI assertion was requested,
10881 * or it was requested and a valid timer was set.
10882 * Also notice full duplex is required for EEE.
10884 bnx2x_eee_advertise(phy, params, vars,
10887 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10888 bnx2x_eee_disable(phy, params, vars);
10891 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10892 SHMEM_EEE_SUPPORTED_SHIFT;
10894 if (phy->flags & FLAGS_EEE) {
10895 /* Handle legacy auto-grEEEn */
10896 if (params->feature_config_flags &
10897 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10899 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10902 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10904 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10905 MDIO_AN_REG_EEE_ADV, temp);
10909 bnx2x_cl22_write(bp, phy,
10911 an_10_100_val | fc_val);
10913 if (phy->req_duplex == DUPLEX_FULL)
10914 autoneg_val |= (1<<8);
10916 bnx2x_cl22_write(bp, phy,
10917 MDIO_PMA_REG_CTRL, autoneg_val);
10923 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10924 struct link_params *params, u8 mode)
10926 struct bnx2x *bp = params->bp;
10929 bnx2x_cl22_write(bp, phy,
10930 MDIO_REG_GPHY_SHADOW,
10931 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10932 bnx2x_cl22_read(bp, phy,
10933 MDIO_REG_GPHY_SHADOW,
10937 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10939 case LED_MODE_FRONT_PANEL_OFF:
10943 case LED_MODE_OPER:
10952 bnx2x_cl22_write(bp, phy,
10953 MDIO_REG_GPHY_SHADOW,
10954 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10959 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10960 struct link_params *params)
10962 struct bnx2x *bp = params->bp;
10966 /* In case of no EPIO routed to reset the GPHY, put it
10967 * in low power mode.
10969 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10970 /* This works with E3 only, no need to check the chip
10971 * before determining the port.
10973 port = params->port;
10974 cfg_pin = (REG_RD(bp, params->shmem_base +
10975 offsetof(struct shmem_region,
10976 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10977 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10978 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10980 /* Drive pin low to put GPHY in reset. */
10981 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10984 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10985 struct link_params *params,
10986 struct link_vars *vars)
10988 struct bnx2x *bp = params->bp;
10991 u16 legacy_status, legacy_speed;
10993 /* Get speed operation status */
10994 bnx2x_cl22_read(bp, phy,
10995 MDIO_REG_GPHY_AUX_STATUS,
10997 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10999 /* Read status to clear the PHY interrupt. */
11000 bnx2x_cl22_read(bp, phy,
11001 MDIO_REG_INTR_STATUS,
11004 link_up = ((legacy_status & (1<<2)) == (1<<2));
11007 legacy_speed = (legacy_status & (7<<8));
11008 if (legacy_speed == (7<<8)) {
11009 vars->line_speed = SPEED_1000;
11010 vars->duplex = DUPLEX_FULL;
11011 } else if (legacy_speed == (6<<8)) {
11012 vars->line_speed = SPEED_1000;
11013 vars->duplex = DUPLEX_HALF;
11014 } else if (legacy_speed == (5<<8)) {
11015 vars->line_speed = SPEED_100;
11016 vars->duplex = DUPLEX_FULL;
11018 /* Omitting 100Base-T4 for now */
11019 else if (legacy_speed == (3<<8)) {
11020 vars->line_speed = SPEED_100;
11021 vars->duplex = DUPLEX_HALF;
11022 } else if (legacy_speed == (2<<8)) {
11023 vars->line_speed = SPEED_10;
11024 vars->duplex = DUPLEX_FULL;
11025 } else if (legacy_speed == (1<<8)) {
11026 vars->line_speed = SPEED_10;
11027 vars->duplex = DUPLEX_HALF;
11028 } else /* Should not happen */
11029 vars->line_speed = 0;
11032 "Link is up in %dMbps, is_duplex_full= %d\n",
11034 (vars->duplex == DUPLEX_FULL));
11036 /* Check legacy speed AN resolution */
11037 bnx2x_cl22_read(bp, phy,
11041 vars->link_status |=
11042 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11043 bnx2x_cl22_read(bp, phy,
11046 if ((val & (1<<0)) == 0)
11047 vars->link_status |=
11048 LINK_STATUS_PARALLEL_DETECTION_USED;
11050 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11053 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11055 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11056 /* Report LP advertised speeds */
11057 bnx2x_cl22_read(bp, phy, 0x5, &val);
11060 vars->link_status |=
11061 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11063 vars->link_status |=
11064 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11066 vars->link_status |=
11067 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11069 vars->link_status |=
11070 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11072 vars->link_status |=
11073 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11075 bnx2x_cl22_read(bp, phy, 0xa, &val);
11077 vars->link_status |=
11078 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11080 vars->link_status |=
11081 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11083 if ((phy->flags & FLAGS_EEE) &&
11084 bnx2x_eee_has_cap(params))
11085 bnx2x_eee_an_resolve(phy, params, vars);
11091 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11092 struct link_params *params)
11094 struct bnx2x *bp = params->bp;
11096 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11098 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11100 /* Enable master/slave manual mmode and set to master */
11101 /* mii write 9 [bits set 11 12] */
11102 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11104 /* forced 1G and disable autoneg */
11105 /* set val [mii read 0] */
11106 /* set val [expr $val & [bits clear 6 12 13]] */
11107 /* set val [expr $val | [bits set 6 8]] */
11108 /* mii write 0 $val */
11109 bnx2x_cl22_read(bp, phy, 0x00, &val);
11110 val &= ~((1<<6) | (1<<12) | (1<<13));
11111 val |= (1<<6) | (1<<8);
11112 bnx2x_cl22_write(bp, phy, 0x00, val);
11114 /* Set external loopback and Tx using 6dB coding */
11115 /* mii write 0x18 7 */
11116 /* set val [mii read 0x18] */
11117 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11118 bnx2x_cl22_write(bp, phy, 0x18, 7);
11119 bnx2x_cl22_read(bp, phy, 0x18, &val);
11120 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11122 /* This register opens the gate for the UMAC despite its name */
11123 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11125 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11126 * length used by the MAC receive logic to check frames.
11128 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11131 /******************************************************************/
11132 /* SFX7101 PHY SECTION */
11133 /******************************************************************/
11134 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11135 struct link_params *params)
11137 struct bnx2x *bp = params->bp;
11138 /* SFX7101_XGXS_TEST1 */
11139 bnx2x_cl45_write(bp, phy,
11140 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11143 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11144 struct link_params *params,
11145 struct link_vars *vars)
11147 u16 fw_ver1, fw_ver2, val;
11148 struct bnx2x *bp = params->bp;
11149 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11151 /* Restore normal power mode*/
11152 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11153 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11155 bnx2x_ext_phy_hw_reset(bp, params->port);
11156 bnx2x_wait_reset_complete(bp, phy, params);
11158 bnx2x_cl45_write(bp, phy,
11159 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11160 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11161 bnx2x_cl45_write(bp, phy,
11162 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11164 bnx2x_ext_phy_set_pause(params, phy, vars);
11165 /* Restart autoneg */
11166 bnx2x_cl45_read(bp, phy,
11167 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11169 bnx2x_cl45_write(bp, phy,
11170 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11172 /* Save spirom version */
11173 bnx2x_cl45_read(bp, phy,
11174 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11176 bnx2x_cl45_read(bp, phy,
11177 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11178 bnx2x_save_spirom_version(bp, params->port,
11179 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11183 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11184 struct link_params *params,
11185 struct link_vars *vars)
11187 struct bnx2x *bp = params->bp;
11190 bnx2x_cl45_read(bp, phy,
11191 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11192 bnx2x_cl45_read(bp, phy,
11193 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11194 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11196 bnx2x_cl45_read(bp, phy,
11197 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11198 bnx2x_cl45_read(bp, phy,
11199 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11200 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11202 link_up = ((val1 & 4) == 4);
11203 /* If link is up print the AN outcome of the SFX7101 PHY */
11205 bnx2x_cl45_read(bp, phy,
11206 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11208 vars->line_speed = SPEED_10000;
11209 vars->duplex = DUPLEX_FULL;
11210 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11211 val2, (val2 & (1<<14)));
11212 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11213 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11215 /* Read LP advertised speeds */
11216 if (val2 & (1<<11))
11217 vars->link_status |=
11218 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11223 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11227 str[0] = (spirom_ver & 0xFF);
11228 str[1] = (spirom_ver & 0xFF00) >> 8;
11229 str[2] = (spirom_ver & 0xFF0000) >> 16;
11230 str[3] = (spirom_ver & 0xFF000000) >> 24;
11236 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11240 bnx2x_cl45_read(bp, phy,
11242 MDIO_PMA_REG_7101_RESET, &val);
11244 for (cnt = 0; cnt < 10; cnt++) {
11246 /* Writes a self-clearing reset */
11247 bnx2x_cl45_write(bp, phy,
11249 MDIO_PMA_REG_7101_RESET,
11251 /* Wait for clear */
11252 bnx2x_cl45_read(bp, phy,
11254 MDIO_PMA_REG_7101_RESET, &val);
11256 if ((val & (1<<15)) == 0)
11261 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11262 struct link_params *params) {
11263 /* Low power mode is controlled by GPIO 2 */
11264 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11265 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11266 /* The PHY reset is controlled by GPIO 1 */
11267 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11268 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11271 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11272 struct link_params *params, u8 mode)
11275 struct bnx2x *bp = params->bp;
11277 case LED_MODE_FRONT_PANEL_OFF:
11284 case LED_MODE_OPER:
11288 bnx2x_cl45_write(bp, phy,
11290 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11294 /******************************************************************/
11295 /* STATIC PHY DECLARATION */
11296 /******************************************************************/
11298 static const struct bnx2x_phy phy_null = {
11299 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11302 .flags = FLAGS_INIT_XGXS_FIRST,
11303 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11304 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11307 .media_type = ETH_PHY_NOT_PRESENT,
11309 .req_flow_ctrl = 0,
11310 .req_line_speed = 0,
11311 .speed_cap_mask = 0,
11314 .config_init = (config_init_t)NULL,
11315 .read_status = (read_status_t)NULL,
11316 .link_reset = (link_reset_t)NULL,
11317 .config_loopback = (config_loopback_t)NULL,
11318 .format_fw_ver = (format_fw_ver_t)NULL,
11319 .hw_reset = (hw_reset_t)NULL,
11320 .set_link_led = (set_link_led_t)NULL,
11321 .phy_specific_func = (phy_specific_func_t)NULL
11324 static const struct bnx2x_phy phy_serdes = {
11325 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11329 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11330 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11332 .supported = (SUPPORTED_10baseT_Half |
11333 SUPPORTED_10baseT_Full |
11334 SUPPORTED_100baseT_Half |
11335 SUPPORTED_100baseT_Full |
11336 SUPPORTED_1000baseT_Full |
11337 SUPPORTED_2500baseX_Full |
11339 SUPPORTED_Autoneg |
11341 SUPPORTED_Asym_Pause),
11342 .media_type = ETH_PHY_BASE_T,
11344 .req_flow_ctrl = 0,
11345 .req_line_speed = 0,
11346 .speed_cap_mask = 0,
11349 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11350 .read_status = (read_status_t)bnx2x_link_settings_status,
11351 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11352 .config_loopback = (config_loopback_t)NULL,
11353 .format_fw_ver = (format_fw_ver_t)NULL,
11354 .hw_reset = (hw_reset_t)NULL,
11355 .set_link_led = (set_link_led_t)NULL,
11356 .phy_specific_func = (phy_specific_func_t)NULL
11359 static const struct bnx2x_phy phy_xgxs = {
11360 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11364 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11365 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11367 .supported = (SUPPORTED_10baseT_Half |
11368 SUPPORTED_10baseT_Full |
11369 SUPPORTED_100baseT_Half |
11370 SUPPORTED_100baseT_Full |
11371 SUPPORTED_1000baseT_Full |
11372 SUPPORTED_2500baseX_Full |
11373 SUPPORTED_10000baseT_Full |
11375 SUPPORTED_Autoneg |
11377 SUPPORTED_Asym_Pause),
11378 .media_type = ETH_PHY_CX4,
11380 .req_flow_ctrl = 0,
11381 .req_line_speed = 0,
11382 .speed_cap_mask = 0,
11385 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11386 .read_status = (read_status_t)bnx2x_link_settings_status,
11387 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11388 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11389 .format_fw_ver = (format_fw_ver_t)NULL,
11390 .hw_reset = (hw_reset_t)NULL,
11391 .set_link_led = (set_link_led_t)NULL,
11392 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11394 static const struct bnx2x_phy phy_warpcore = {
11395 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11398 .flags = FLAGS_TX_ERROR_CHECK,
11399 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11400 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11402 .supported = (SUPPORTED_10baseT_Half |
11403 SUPPORTED_10baseT_Full |
11404 SUPPORTED_100baseT_Half |
11405 SUPPORTED_100baseT_Full |
11406 SUPPORTED_1000baseT_Full |
11407 SUPPORTED_10000baseT_Full |
11408 SUPPORTED_20000baseKR2_Full |
11409 SUPPORTED_20000baseMLD2_Full |
11411 SUPPORTED_Autoneg |
11413 SUPPORTED_Asym_Pause),
11414 .media_type = ETH_PHY_UNSPECIFIED,
11416 .req_flow_ctrl = 0,
11417 .req_line_speed = 0,
11418 .speed_cap_mask = 0,
11419 /* req_duplex = */0,
11421 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11422 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11423 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11424 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11425 .format_fw_ver = (format_fw_ver_t)NULL,
11426 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11427 .set_link_led = (set_link_led_t)NULL,
11428 .phy_specific_func = (phy_specific_func_t)NULL
11432 static const struct bnx2x_phy phy_7101 = {
11433 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11436 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11437 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11438 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11440 .supported = (SUPPORTED_10000baseT_Full |
11442 SUPPORTED_Autoneg |
11444 SUPPORTED_Asym_Pause),
11445 .media_type = ETH_PHY_BASE_T,
11447 .req_flow_ctrl = 0,
11448 .req_line_speed = 0,
11449 .speed_cap_mask = 0,
11452 .config_init = (config_init_t)bnx2x_7101_config_init,
11453 .read_status = (read_status_t)bnx2x_7101_read_status,
11454 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11455 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11456 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11457 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11458 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11459 .phy_specific_func = (phy_specific_func_t)NULL
11461 static const struct bnx2x_phy phy_8073 = {
11462 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11466 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11467 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11469 .supported = (SUPPORTED_10000baseT_Full |
11470 SUPPORTED_2500baseX_Full |
11471 SUPPORTED_1000baseT_Full |
11473 SUPPORTED_Autoneg |
11475 SUPPORTED_Asym_Pause),
11476 .media_type = ETH_PHY_KR,
11478 .req_flow_ctrl = 0,
11479 .req_line_speed = 0,
11480 .speed_cap_mask = 0,
11483 .config_init = (config_init_t)bnx2x_8073_config_init,
11484 .read_status = (read_status_t)bnx2x_8073_read_status,
11485 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11486 .config_loopback = (config_loopback_t)NULL,
11487 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11488 .hw_reset = (hw_reset_t)NULL,
11489 .set_link_led = (set_link_led_t)NULL,
11490 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11492 static const struct bnx2x_phy phy_8705 = {
11493 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11496 .flags = FLAGS_INIT_XGXS_FIRST,
11497 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11498 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11500 .supported = (SUPPORTED_10000baseT_Full |
11503 SUPPORTED_Asym_Pause),
11504 .media_type = ETH_PHY_XFP_FIBER,
11506 .req_flow_ctrl = 0,
11507 .req_line_speed = 0,
11508 .speed_cap_mask = 0,
11511 .config_init = (config_init_t)bnx2x_8705_config_init,
11512 .read_status = (read_status_t)bnx2x_8705_read_status,
11513 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11514 .config_loopback = (config_loopback_t)NULL,
11515 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11516 .hw_reset = (hw_reset_t)NULL,
11517 .set_link_led = (set_link_led_t)NULL,
11518 .phy_specific_func = (phy_specific_func_t)NULL
11520 static const struct bnx2x_phy phy_8706 = {
11521 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11524 .flags = FLAGS_INIT_XGXS_FIRST,
11525 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11526 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11528 .supported = (SUPPORTED_10000baseT_Full |
11529 SUPPORTED_1000baseT_Full |
11532 SUPPORTED_Asym_Pause),
11533 .media_type = ETH_PHY_SFPP_10G_FIBER,
11535 .req_flow_ctrl = 0,
11536 .req_line_speed = 0,
11537 .speed_cap_mask = 0,
11540 .config_init = (config_init_t)bnx2x_8706_config_init,
11541 .read_status = (read_status_t)bnx2x_8706_read_status,
11542 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11543 .config_loopback = (config_loopback_t)NULL,
11544 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11545 .hw_reset = (hw_reset_t)NULL,
11546 .set_link_led = (set_link_led_t)NULL,
11547 .phy_specific_func = (phy_specific_func_t)NULL
11550 static const struct bnx2x_phy phy_8726 = {
11551 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11554 .flags = (FLAGS_INIT_XGXS_FIRST |
11555 FLAGS_TX_ERROR_CHECK),
11556 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11557 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11559 .supported = (SUPPORTED_10000baseT_Full |
11560 SUPPORTED_1000baseT_Full |
11561 SUPPORTED_Autoneg |
11564 SUPPORTED_Asym_Pause),
11565 .media_type = ETH_PHY_NOT_PRESENT,
11567 .req_flow_ctrl = 0,
11568 .req_line_speed = 0,
11569 .speed_cap_mask = 0,
11572 .config_init = (config_init_t)bnx2x_8726_config_init,
11573 .read_status = (read_status_t)bnx2x_8726_read_status,
11574 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11575 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11576 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11577 .hw_reset = (hw_reset_t)NULL,
11578 .set_link_led = (set_link_led_t)NULL,
11579 .phy_specific_func = (phy_specific_func_t)NULL
11582 static const struct bnx2x_phy phy_8727 = {
11583 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11586 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11587 FLAGS_TX_ERROR_CHECK),
11588 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11589 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11591 .supported = (SUPPORTED_10000baseT_Full |
11592 SUPPORTED_1000baseT_Full |
11595 SUPPORTED_Asym_Pause),
11596 .media_type = ETH_PHY_NOT_PRESENT,
11598 .req_flow_ctrl = 0,
11599 .req_line_speed = 0,
11600 .speed_cap_mask = 0,
11603 .config_init = (config_init_t)bnx2x_8727_config_init,
11604 .read_status = (read_status_t)bnx2x_8727_read_status,
11605 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11606 .config_loopback = (config_loopback_t)NULL,
11607 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11608 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11609 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11610 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11612 static const struct bnx2x_phy phy_8481 = {
11613 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11616 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11617 FLAGS_REARM_LATCH_SIGNAL,
11618 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11619 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11621 .supported = (SUPPORTED_10baseT_Half |
11622 SUPPORTED_10baseT_Full |
11623 SUPPORTED_100baseT_Half |
11624 SUPPORTED_100baseT_Full |
11625 SUPPORTED_1000baseT_Full |
11626 SUPPORTED_10000baseT_Full |
11628 SUPPORTED_Autoneg |
11630 SUPPORTED_Asym_Pause),
11631 .media_type = ETH_PHY_BASE_T,
11633 .req_flow_ctrl = 0,
11634 .req_line_speed = 0,
11635 .speed_cap_mask = 0,
11638 .config_init = (config_init_t)bnx2x_8481_config_init,
11639 .read_status = (read_status_t)bnx2x_848xx_read_status,
11640 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11641 .config_loopback = (config_loopback_t)NULL,
11642 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11643 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11644 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11645 .phy_specific_func = (phy_specific_func_t)NULL
11648 static const struct bnx2x_phy phy_84823 = {
11649 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11652 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11653 FLAGS_REARM_LATCH_SIGNAL |
11654 FLAGS_TX_ERROR_CHECK),
11655 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11656 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11658 .supported = (SUPPORTED_10baseT_Half |
11659 SUPPORTED_10baseT_Full |
11660 SUPPORTED_100baseT_Half |
11661 SUPPORTED_100baseT_Full |
11662 SUPPORTED_1000baseT_Full |
11663 SUPPORTED_10000baseT_Full |
11665 SUPPORTED_Autoneg |
11667 SUPPORTED_Asym_Pause),
11668 .media_type = ETH_PHY_BASE_T,
11670 .req_flow_ctrl = 0,
11671 .req_line_speed = 0,
11672 .speed_cap_mask = 0,
11675 .config_init = (config_init_t)bnx2x_848x3_config_init,
11676 .read_status = (read_status_t)bnx2x_848xx_read_status,
11677 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11678 .config_loopback = (config_loopback_t)NULL,
11679 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11680 .hw_reset = (hw_reset_t)NULL,
11681 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11682 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11685 static const struct bnx2x_phy phy_84833 = {
11686 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11689 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11690 FLAGS_REARM_LATCH_SIGNAL |
11691 FLAGS_TX_ERROR_CHECK),
11692 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11693 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11695 .supported = (SUPPORTED_100baseT_Half |
11696 SUPPORTED_100baseT_Full |
11697 SUPPORTED_1000baseT_Full |
11698 SUPPORTED_10000baseT_Full |
11700 SUPPORTED_Autoneg |
11702 SUPPORTED_Asym_Pause),
11703 .media_type = ETH_PHY_BASE_T,
11705 .req_flow_ctrl = 0,
11706 .req_line_speed = 0,
11707 .speed_cap_mask = 0,
11710 .config_init = (config_init_t)bnx2x_848x3_config_init,
11711 .read_status = (read_status_t)bnx2x_848xx_read_status,
11712 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11713 .config_loopback = (config_loopback_t)NULL,
11714 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11715 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11716 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11717 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11720 static const struct bnx2x_phy phy_84834 = {
11721 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11724 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11725 FLAGS_REARM_LATCH_SIGNAL,
11726 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11727 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11729 .supported = (SUPPORTED_100baseT_Half |
11730 SUPPORTED_100baseT_Full |
11731 SUPPORTED_1000baseT_Full |
11732 SUPPORTED_10000baseT_Full |
11734 SUPPORTED_Autoneg |
11736 SUPPORTED_Asym_Pause),
11737 .media_type = ETH_PHY_BASE_T,
11739 .req_flow_ctrl = 0,
11740 .req_line_speed = 0,
11741 .speed_cap_mask = 0,
11744 .config_init = (config_init_t)bnx2x_848x3_config_init,
11745 .read_status = (read_status_t)bnx2x_848xx_read_status,
11746 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11747 .config_loopback = (config_loopback_t)NULL,
11748 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11749 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11750 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11751 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11754 static const struct bnx2x_phy phy_54618se = {
11755 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11758 .flags = FLAGS_INIT_XGXS_FIRST,
11759 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11760 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11762 .supported = (SUPPORTED_10baseT_Half |
11763 SUPPORTED_10baseT_Full |
11764 SUPPORTED_100baseT_Half |
11765 SUPPORTED_100baseT_Full |
11766 SUPPORTED_1000baseT_Full |
11768 SUPPORTED_Autoneg |
11770 SUPPORTED_Asym_Pause),
11771 .media_type = ETH_PHY_BASE_T,
11773 .req_flow_ctrl = 0,
11774 .req_line_speed = 0,
11775 .speed_cap_mask = 0,
11776 /* req_duplex = */0,
11778 .config_init = (config_init_t)bnx2x_54618se_config_init,
11779 .read_status = (read_status_t)bnx2x_54618se_read_status,
11780 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11781 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11782 .format_fw_ver = (format_fw_ver_t)NULL,
11783 .hw_reset = (hw_reset_t)NULL,
11784 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11785 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11787 /*****************************************************************/
11789 /* Populate the phy according. Main function: bnx2x_populate_phy */
11791 /*****************************************************************/
11793 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11794 struct bnx2x_phy *phy, u8 port,
11797 /* Get the 4 lanes xgxs config rx and tx */
11798 u32 rx = 0, tx = 0, i;
11799 for (i = 0; i < 2; i++) {
11800 /* INT_PHY and EXT_PHY1 share the same value location in
11801 * the shmem. When num_phys is greater than 1, than this value
11802 * applies only to EXT_PHY1
11804 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11805 rx = REG_RD(bp, shmem_base +
11806 offsetof(struct shmem_region,
11807 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11809 tx = REG_RD(bp, shmem_base +
11810 offsetof(struct shmem_region,
11811 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11813 rx = REG_RD(bp, shmem_base +
11814 offsetof(struct shmem_region,
11815 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11817 tx = REG_RD(bp, shmem_base +
11818 offsetof(struct shmem_region,
11819 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11822 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11823 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11825 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11826 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11830 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11831 u8 phy_index, u8 port)
11833 u32 ext_phy_config = 0;
11834 switch (phy_index) {
11836 ext_phy_config = REG_RD(bp, shmem_base +
11837 offsetof(struct shmem_region,
11838 dev_info.port_hw_config[port].external_phy_config));
11841 ext_phy_config = REG_RD(bp, shmem_base +
11842 offsetof(struct shmem_region,
11843 dev_info.port_hw_config[port].external_phy_config2));
11846 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11850 return ext_phy_config;
11852 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11853 struct bnx2x_phy *phy)
11857 u32 switch_cfg = (REG_RD(bp, shmem_base +
11858 offsetof(struct shmem_region,
11859 dev_info.port_feature_config[port].link_config)) &
11860 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11861 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11862 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11864 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11865 if (USES_WARPCORE(bp)) {
11867 phy_addr = REG_RD(bp,
11868 MISC_REG_WC0_CTRL_PHY_ADDR);
11869 *phy = phy_warpcore;
11870 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11871 phy->flags |= FLAGS_4_PORT_MODE;
11873 phy->flags &= ~FLAGS_4_PORT_MODE;
11874 /* Check Dual mode */
11875 serdes_net_if = (REG_RD(bp, shmem_base +
11876 offsetof(struct shmem_region, dev_info.
11877 port_hw_config[port].default_cfg)) &
11878 PORT_HW_CFG_NET_SERDES_IF_MASK);
11879 /* Set the appropriate supported and flags indications per
11880 * interface type of the chip
11882 switch (serdes_net_if) {
11883 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11884 phy->supported &= (SUPPORTED_10baseT_Half |
11885 SUPPORTED_10baseT_Full |
11886 SUPPORTED_100baseT_Half |
11887 SUPPORTED_100baseT_Full |
11888 SUPPORTED_1000baseT_Full |
11890 SUPPORTED_Autoneg |
11892 SUPPORTED_Asym_Pause);
11893 phy->media_type = ETH_PHY_BASE_T;
11895 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11896 phy->supported &= (SUPPORTED_1000baseT_Full |
11897 SUPPORTED_10000baseT_Full |
11900 SUPPORTED_Asym_Pause);
11901 phy->media_type = ETH_PHY_XFP_FIBER;
11903 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11904 phy->supported &= (SUPPORTED_1000baseT_Full |
11905 SUPPORTED_10000baseT_Full |
11908 SUPPORTED_Asym_Pause);
11909 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11911 case PORT_HW_CFG_NET_SERDES_IF_KR:
11912 phy->media_type = ETH_PHY_KR;
11913 phy->supported &= (SUPPORTED_1000baseT_Full |
11914 SUPPORTED_10000baseT_Full |
11916 SUPPORTED_Autoneg |
11918 SUPPORTED_Asym_Pause);
11920 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11921 phy->media_type = ETH_PHY_KR;
11922 phy->flags |= FLAGS_WC_DUAL_MODE;
11923 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11926 SUPPORTED_Asym_Pause);
11928 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11929 phy->media_type = ETH_PHY_KR;
11930 phy->flags |= FLAGS_WC_DUAL_MODE;
11931 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11932 SUPPORTED_10000baseT_Full |
11933 SUPPORTED_1000baseT_Full |
11934 SUPPORTED_Autoneg |
11937 SUPPORTED_Asym_Pause);
11938 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11941 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11946 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11947 * was not set as expected. For B0, ECO will be enabled so there
11948 * won't be an issue there
11950 if (CHIP_REV(bp) == CHIP_REV_Ax)
11951 phy->flags |= FLAGS_MDC_MDIO_WA;
11953 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11955 switch (switch_cfg) {
11956 case SWITCH_CFG_1G:
11957 phy_addr = REG_RD(bp,
11958 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11962 case SWITCH_CFG_10G:
11963 phy_addr = REG_RD(bp,
11964 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11969 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11973 phy->addr = (u8)phy_addr;
11974 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11975 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11977 if (CHIP_IS_E2(bp))
11978 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11980 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11982 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11983 port, phy->addr, phy->mdio_ctrl);
11985 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11989 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11994 struct bnx2x_phy *phy)
11996 u32 ext_phy_config, phy_type, config2;
11997 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11998 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12000 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12001 /* Select the phy type */
12002 switch (phy_type) {
12003 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12004 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12007 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12010 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12014 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12018 /* BCM8727_NOC => BCM8727 no over current */
12019 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12021 phy->flags |= FLAGS_NOC;
12023 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12024 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12025 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12028 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12031 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12034 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12037 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12040 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12041 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12042 *phy = phy_54618se;
12043 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12044 phy->flags |= FLAGS_EEE;
12046 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12049 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12054 /* In case external PHY wasn't found */
12055 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12056 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12061 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12062 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12064 /* The shmem address of the phy version is located on different
12065 * structures. In case this structure is too old, do not set
12068 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12069 dev_info.shared_hw_config.config2));
12070 if (phy_index == EXT_PHY1) {
12071 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12072 port_mb[port].ext_phy_fw_version);
12074 /* Check specific mdc mdio settings */
12075 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12076 mdc_mdio_access = config2 &
12077 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12079 u32 size = REG_RD(bp, shmem2_base);
12082 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12083 phy->ver_addr = shmem2_base +
12084 offsetof(struct shmem2_region,
12085 ext_phy_fw_version2[port]);
12087 /* Check specific mdc mdio settings */
12088 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12089 mdc_mdio_access = (config2 &
12090 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12091 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12092 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12094 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12096 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12097 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12099 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12100 * version lower than or equal to 1.39
12102 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12103 if (((raw_ver & 0x7F) <= 39) &&
12104 (((raw_ver & 0xF80) >> 7) <= 1))
12105 phy->supported &= ~(SUPPORTED_100baseT_Half |
12106 SUPPORTED_100baseT_Full);
12109 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12110 phy_type, port, phy_index);
12111 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12112 phy->addr, phy->mdio_ctrl);
12116 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12117 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12120 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12121 if (phy_index == INT_PHY)
12122 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12123 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12128 static void bnx2x_phy_def_cfg(struct link_params *params,
12129 struct bnx2x_phy *phy,
12132 struct bnx2x *bp = params->bp;
12134 /* Populate the default phy configuration for MF mode */
12135 if (phy_index == EXT_PHY2) {
12136 link_config = REG_RD(bp, params->shmem_base +
12137 offsetof(struct shmem_region, dev_info.
12138 port_feature_config[params->port].link_config2));
12139 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12140 offsetof(struct shmem_region,
12142 port_hw_config[params->port].speed_capability_mask2));
12144 link_config = REG_RD(bp, params->shmem_base +
12145 offsetof(struct shmem_region, dev_info.
12146 port_feature_config[params->port].link_config));
12147 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12148 offsetof(struct shmem_region,
12150 port_hw_config[params->port].speed_capability_mask));
12153 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12154 phy_index, link_config, phy->speed_cap_mask);
12156 phy->req_duplex = DUPLEX_FULL;
12157 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12158 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12159 phy->req_duplex = DUPLEX_HALF;
12160 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12161 phy->req_line_speed = SPEED_10;
12163 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12164 phy->req_duplex = DUPLEX_HALF;
12165 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12166 phy->req_line_speed = SPEED_100;
12168 case PORT_FEATURE_LINK_SPEED_1G:
12169 phy->req_line_speed = SPEED_1000;
12171 case PORT_FEATURE_LINK_SPEED_2_5G:
12172 phy->req_line_speed = SPEED_2500;
12174 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12175 phy->req_line_speed = SPEED_10000;
12178 phy->req_line_speed = SPEED_AUTO_NEG;
12182 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12183 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12184 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12186 case PORT_FEATURE_FLOW_CONTROL_TX:
12187 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12189 case PORT_FEATURE_FLOW_CONTROL_RX:
12190 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12192 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12193 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12196 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12201 u32 bnx2x_phy_selection(struct link_params *params)
12203 u32 phy_config_swapped, prio_cfg;
12204 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12206 phy_config_swapped = params->multi_phy_config &
12207 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12209 prio_cfg = params->multi_phy_config &
12210 PORT_HW_CFG_PHY_SELECTION_MASK;
12212 if (phy_config_swapped) {
12213 switch (prio_cfg) {
12214 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12215 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12217 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12218 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12220 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12221 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12223 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12224 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12228 return_cfg = prio_cfg;
12233 int bnx2x_phy_probe(struct link_params *params)
12235 u8 phy_index, actual_phy_idx;
12236 u32 phy_config_swapped, sync_offset, media_types;
12237 struct bnx2x *bp = params->bp;
12238 struct bnx2x_phy *phy;
12239 params->num_phys = 0;
12240 DP(NETIF_MSG_LINK, "Begin phy probe\n");
12241 phy_config_swapped = params->multi_phy_config &
12242 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12244 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12246 actual_phy_idx = phy_index;
12247 if (phy_config_swapped) {
12248 if (phy_index == EXT_PHY1)
12249 actual_phy_idx = EXT_PHY2;
12250 else if (phy_index == EXT_PHY2)
12251 actual_phy_idx = EXT_PHY1;
12253 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12254 " actual_phy_idx %x\n", phy_config_swapped,
12255 phy_index, actual_phy_idx);
12256 phy = ¶ms->phy[actual_phy_idx];
12257 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12258 params->shmem2_base, params->port,
12260 params->num_phys = 0;
12261 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12263 for (phy_index = INT_PHY;
12264 phy_index < MAX_PHYS;
12269 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12272 if (params->feature_config_flags &
12273 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12274 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12276 if (!(params->feature_config_flags &
12277 FEATURE_CONFIG_MT_SUPPORT))
12278 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12280 sync_offset = params->shmem_base +
12281 offsetof(struct shmem_region,
12282 dev_info.port_hw_config[params->port].media_type);
12283 media_types = REG_RD(bp, sync_offset);
12285 /* Update media type for non-PMF sync only for the first time
12286 * In case the media type changes afterwards, it will be updated
12287 * using the update_status function
12289 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12290 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12291 actual_phy_idx))) == 0) {
12292 media_types |= ((phy->media_type &
12293 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12294 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12297 REG_WR(bp, sync_offset, media_types);
12299 bnx2x_phy_def_cfg(params, phy, phy_index);
12300 params->num_phys++;
12303 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12307 static void bnx2x_init_bmac_loopback(struct link_params *params,
12308 struct link_vars *vars)
12310 struct bnx2x *bp = params->bp;
12312 vars->line_speed = SPEED_10000;
12313 vars->duplex = DUPLEX_FULL;
12314 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12315 vars->mac_type = MAC_TYPE_BMAC;
12317 vars->phy_flags = PHY_XGXS_FLAG;
12319 bnx2x_xgxs_deassert(params);
12321 /* Set bmac loopback */
12322 bnx2x_bmac_enable(params, vars, 1, 1);
12324 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12327 static void bnx2x_init_emac_loopback(struct link_params *params,
12328 struct link_vars *vars)
12330 struct bnx2x *bp = params->bp;
12332 vars->line_speed = SPEED_1000;
12333 vars->duplex = DUPLEX_FULL;
12334 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12335 vars->mac_type = MAC_TYPE_EMAC;
12337 vars->phy_flags = PHY_XGXS_FLAG;
12339 bnx2x_xgxs_deassert(params);
12340 /* Set bmac loopback */
12341 bnx2x_emac_enable(params, vars, 1);
12342 bnx2x_emac_program(params, vars);
12343 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12346 static void bnx2x_init_xmac_loopback(struct link_params *params,
12347 struct link_vars *vars)
12349 struct bnx2x *bp = params->bp;
12351 if (!params->req_line_speed[0])
12352 vars->line_speed = SPEED_10000;
12354 vars->line_speed = params->req_line_speed[0];
12355 vars->duplex = DUPLEX_FULL;
12356 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12357 vars->mac_type = MAC_TYPE_XMAC;
12358 vars->phy_flags = PHY_XGXS_FLAG;
12359 /* Set WC to loopback mode since link is required to provide clock
12360 * to the XMAC in 20G mode
12362 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12363 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12364 params->phy[INT_PHY].config_loopback(
12365 ¶ms->phy[INT_PHY],
12368 bnx2x_xmac_enable(params, vars, 1);
12369 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12372 static void bnx2x_init_umac_loopback(struct link_params *params,
12373 struct link_vars *vars)
12375 struct bnx2x *bp = params->bp;
12377 vars->line_speed = SPEED_1000;
12378 vars->duplex = DUPLEX_FULL;
12379 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12380 vars->mac_type = MAC_TYPE_UMAC;
12381 vars->phy_flags = PHY_XGXS_FLAG;
12382 bnx2x_umac_enable(params, vars, 1);
12384 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12387 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12388 struct link_vars *vars)
12390 struct bnx2x *bp = params->bp;
12391 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
12393 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12394 vars->duplex = DUPLEX_FULL;
12395 if (params->req_line_speed[0] == SPEED_1000)
12396 vars->line_speed = SPEED_1000;
12397 else if ((params->req_line_speed[0] == SPEED_20000) ||
12398 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12399 vars->line_speed = SPEED_20000;
12401 vars->line_speed = SPEED_10000;
12403 if (!USES_WARPCORE(bp))
12404 bnx2x_xgxs_deassert(params);
12405 bnx2x_link_initialize(params, vars);
12407 if (params->req_line_speed[0] == SPEED_1000) {
12408 if (USES_WARPCORE(bp))
12409 bnx2x_umac_enable(params, vars, 0);
12411 bnx2x_emac_program(params, vars);
12412 bnx2x_emac_enable(params, vars, 0);
12415 if (USES_WARPCORE(bp))
12416 bnx2x_xmac_enable(params, vars, 0);
12418 bnx2x_bmac_enable(params, vars, 0, 1);
12421 if (params->loopback_mode == LOOPBACK_XGXS) {
12422 /* Set 10G XGXS loopback */
12423 int_phy->config_loopback(int_phy, params);
12425 /* Set external phy loopback */
12427 for (phy_index = EXT_PHY1;
12428 phy_index < params->num_phys; phy_index++)
12429 if (params->phy[phy_index].config_loopback)
12430 params->phy[phy_index].config_loopback(
12431 ¶ms->phy[phy_index],
12434 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12436 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12439 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12441 struct bnx2x *bp = params->bp;
12442 u8 val = en * 0x1F;
12444 /* Open / close the gate between the NIG and the BRB */
12445 if (!CHIP_IS_E1x(bp))
12447 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12449 if (!CHIP_IS_E1(bp)) {
12450 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12454 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12455 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12457 static int bnx2x_avoid_link_flap(struct link_params *params,
12458 struct link_vars *vars)
12461 u32 dont_clear_stat, lfa_sts;
12462 struct bnx2x *bp = params->bp;
12464 /* Sync the link parameters */
12465 bnx2x_link_status_update(params, vars);
12468 * The module verification was already done by previous link owner,
12469 * so this call is meant only to get warning message
12472 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12473 struct bnx2x_phy *phy = ¶ms->phy[phy_idx];
12474 if (phy->phy_specific_func) {
12475 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12476 phy->phy_specific_func(phy, params, PHY_INIT);
12478 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12479 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12480 (phy->media_type == ETH_PHY_DA_TWINAX))
12481 bnx2x_verify_sfp_module(phy, params);
12483 lfa_sts = REG_RD(bp, params->lfa_base +
12484 offsetof(struct shmem_lfa,
12487 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12489 /* Re-enable the NIG/MAC */
12490 if (CHIP_IS_E3(bp)) {
12491 if (!dont_clear_stat) {
12492 REG_WR(bp, GRCBASE_MISC +
12493 MISC_REGISTERS_RESET_REG_2_CLEAR,
12494 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12496 REG_WR(bp, GRCBASE_MISC +
12497 MISC_REGISTERS_RESET_REG_2_SET,
12498 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12501 if (vars->line_speed < SPEED_10000)
12502 bnx2x_umac_enable(params, vars, 0);
12504 bnx2x_xmac_enable(params, vars, 0);
12506 if (vars->line_speed < SPEED_10000)
12507 bnx2x_emac_enable(params, vars, 0);
12509 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12512 /* Increment LFA count */
12513 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12514 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12515 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12516 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12517 /* Clear link flap reason */
12518 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12520 REG_WR(bp, params->lfa_base +
12521 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12523 /* Disable NIG DRAIN */
12524 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12526 /* Enable interrupts */
12527 bnx2x_link_int_enable(params);
12531 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12532 struct link_vars *vars,
12535 u32 lfa_sts, cfg_idx, tmp_val;
12536 struct bnx2x *bp = params->bp;
12538 bnx2x_link_reset(params, vars, 1);
12540 if (!params->lfa_base)
12542 /* Store the new link parameters */
12543 REG_WR(bp, params->lfa_base +
12544 offsetof(struct shmem_lfa, req_duplex),
12545 params->req_duplex[0] | (params->req_duplex[1] << 16));
12547 REG_WR(bp, params->lfa_base +
12548 offsetof(struct shmem_lfa, req_flow_ctrl),
12549 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12551 REG_WR(bp, params->lfa_base +
12552 offsetof(struct shmem_lfa, req_line_speed),
12553 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12555 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12556 REG_WR(bp, params->lfa_base +
12557 offsetof(struct shmem_lfa,
12558 speed_cap_mask[cfg_idx]),
12559 params->speed_cap_mask[cfg_idx]);
12562 tmp_val = REG_RD(bp, params->lfa_base +
12563 offsetof(struct shmem_lfa, additional_config));
12564 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12565 tmp_val |= params->req_fc_auto_adv;
12567 REG_WR(bp, params->lfa_base +
12568 offsetof(struct shmem_lfa, additional_config), tmp_val);
12570 lfa_sts = REG_RD(bp, params->lfa_base +
12571 offsetof(struct shmem_lfa, lfa_sts));
12573 /* Clear the "Don't Clear Statistics" bit, and set reason */
12574 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12576 /* Set link flap reason */
12577 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12578 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12579 LFA_LINK_FLAP_REASON_OFFSET);
12581 /* Increment link flap counter */
12582 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12583 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12584 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12585 << LINK_FLAP_COUNT_OFFSET));
12586 REG_WR(bp, params->lfa_base +
12587 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12588 /* Proceed with regular link initialization */
12591 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12594 struct bnx2x *bp = params->bp;
12595 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12596 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12597 params->req_line_speed[0], params->req_flow_ctrl[0]);
12598 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12599 params->req_line_speed[1], params->req_flow_ctrl[1]);
12600 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12601 vars->link_status = 0;
12602 vars->phy_link_up = 0;
12604 vars->line_speed = 0;
12605 vars->duplex = DUPLEX_FULL;
12606 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12607 vars->mac_type = MAC_TYPE_NONE;
12608 vars->phy_flags = 0;
12609 vars->check_kr2_recovery_cnt = 0;
12610 params->link_flags = PHY_INITIALIZED;
12611 /* Driver opens NIG-BRB filters */
12612 bnx2x_set_rx_filter(params, 1);
12613 /* Check if link flap can be avoided */
12614 lfa_status = bnx2x_check_lfa(params);
12616 if (lfa_status == 0) {
12617 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12618 return bnx2x_avoid_link_flap(params, vars);
12621 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12623 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12625 /* Disable attentions */
12626 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12627 (NIG_MASK_XGXS0_LINK_STATUS |
12628 NIG_MASK_XGXS0_LINK10G |
12629 NIG_MASK_SERDES0_LINK_STATUS |
12632 bnx2x_emac_init(params, vars);
12634 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12635 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12637 if (params->num_phys == 0) {
12638 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12641 set_phy_vars(params, vars);
12643 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12644 switch (params->loopback_mode) {
12645 case LOOPBACK_BMAC:
12646 bnx2x_init_bmac_loopback(params, vars);
12648 case LOOPBACK_EMAC:
12649 bnx2x_init_emac_loopback(params, vars);
12651 case LOOPBACK_XMAC:
12652 bnx2x_init_xmac_loopback(params, vars);
12654 case LOOPBACK_UMAC:
12655 bnx2x_init_umac_loopback(params, vars);
12657 case LOOPBACK_XGXS:
12658 case LOOPBACK_EXT_PHY:
12659 bnx2x_init_xgxs_loopback(params, vars);
12662 if (!CHIP_IS_E3(bp)) {
12663 if (params->switch_cfg == SWITCH_CFG_10G)
12664 bnx2x_xgxs_deassert(params);
12666 bnx2x_serdes_deassert(bp, params->port);
12668 bnx2x_link_initialize(params, vars);
12670 bnx2x_link_int_enable(params);
12673 bnx2x_update_mng(params, vars->link_status);
12675 bnx2x_update_mng_eee(params, vars->eee_status);
12679 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12682 struct bnx2x *bp = params->bp;
12683 u8 phy_index, port = params->port, clear_latch_ind = 0;
12684 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12685 /* Disable attentions */
12686 vars->link_status = 0;
12687 bnx2x_update_mng(params, vars->link_status);
12688 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12689 SHMEM_EEE_ACTIVE_BIT);
12690 bnx2x_update_mng_eee(params, vars->eee_status);
12691 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12692 (NIG_MASK_XGXS0_LINK_STATUS |
12693 NIG_MASK_XGXS0_LINK10G |
12694 NIG_MASK_SERDES0_LINK_STATUS |
12697 /* Activate nig drain */
12698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12700 /* Disable nig egress interface */
12701 if (!CHIP_IS_E3(bp)) {
12702 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12703 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12706 if (!CHIP_IS_E3(bp)) {
12707 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12709 bnx2x_set_xmac_rxtx(params, 0);
12710 bnx2x_set_umac_rxtx(params, 0);
12713 if (!CHIP_IS_E3(bp))
12714 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12716 usleep_range(10000, 20000);
12717 /* The PHY reset is controlled by GPIO 1
12718 * Hold it as vars low
12720 /* Clear link led */
12721 bnx2x_set_mdio_emac_per_phy(bp, params);
12722 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12724 if (reset_ext_phy) {
12725 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12727 if (params->phy[phy_index].link_reset) {
12728 bnx2x_set_aer_mmd(params,
12729 ¶ms->phy[phy_index]);
12730 params->phy[phy_index].link_reset(
12731 ¶ms->phy[phy_index],
12734 if (params->phy[phy_index].flags &
12735 FLAGS_REARM_LATCH_SIGNAL)
12736 clear_latch_ind = 1;
12740 if (clear_latch_ind) {
12741 /* Clear latching indication */
12742 bnx2x_rearm_latch_signal(bp, port, 0);
12743 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12744 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12746 if (params->phy[INT_PHY].link_reset)
12747 params->phy[INT_PHY].link_reset(
12748 ¶ms->phy[INT_PHY], params);
12750 /* Disable nig ingress interface */
12751 if (!CHIP_IS_E3(bp)) {
12753 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12754 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12755 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12756 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12758 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12759 bnx2x_set_xumac_nig(params, 0, 0);
12760 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12761 MISC_REGISTERS_RESET_REG_2_XMAC)
12762 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12763 XMAC_CTRL_REG_SOFT_RESET);
12766 vars->phy_flags = 0;
12769 int bnx2x_lfa_reset(struct link_params *params,
12770 struct link_vars *vars)
12772 struct bnx2x *bp = params->bp;
12774 vars->phy_flags = 0;
12775 params->link_flags &= ~PHY_INITIALIZED;
12776 if (!params->lfa_base)
12777 return bnx2x_link_reset(params, vars, 1);
12779 * Activate NIG drain so that during this time the device won't send
12780 * anything while it is unable to response.
12782 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12785 * Close gracefully the gate from BMAC to NIG such that no half packets
12788 if (!CHIP_IS_E3(bp))
12789 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12791 if (CHIP_IS_E3(bp)) {
12792 bnx2x_set_xmac_rxtx(params, 0);
12793 bnx2x_set_umac_rxtx(params, 0);
12795 /* Wait 10ms for the pipe to clean up*/
12796 usleep_range(10000, 20000);
12798 /* Clean the NIG-BRB using the network filters in a way that will
12799 * not cut a packet in the middle.
12801 bnx2x_set_rx_filter(params, 0);
12804 * Re-open the gate between the BMAC and the NIG, after verifying the
12805 * gate to the BRB is closed, otherwise packets may arrive to the
12806 * firmware before driver had initialized it. The target is to achieve
12807 * minimum management protocol down time.
12809 if (!CHIP_IS_E3(bp))
12810 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12812 if (CHIP_IS_E3(bp)) {
12813 bnx2x_set_xmac_rxtx(params, 1);
12814 bnx2x_set_umac_rxtx(params, 1);
12816 /* Disable NIG drain */
12817 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12821 /****************************************************************************/
12822 /* Common function */
12823 /****************************************************************************/
12824 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12825 u32 shmem_base_path[],
12826 u32 shmem2_base_path[], u8 phy_index,
12829 struct bnx2x_phy phy[PORT_MAX];
12830 struct bnx2x_phy *phy_blk[PORT_MAX];
12833 s8 port_of_path = 0;
12834 u32 swap_val, swap_override;
12835 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12836 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12837 port ^= (swap_val && swap_override);
12838 bnx2x_ext_phy_hw_reset(bp, port);
12839 /* PART1 - Reset both phys */
12840 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12841 u32 shmem_base, shmem2_base;
12842 /* In E2, same phy is using for port0 of the two paths */
12843 if (CHIP_IS_E1x(bp)) {
12844 shmem_base = shmem_base_path[0];
12845 shmem2_base = shmem2_base_path[0];
12846 port_of_path = port;
12848 shmem_base = shmem_base_path[port];
12849 shmem2_base = shmem2_base_path[port];
12853 /* Extract the ext phy address for the port */
12854 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12855 port_of_path, &phy[port]) !=
12857 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12860 /* Disable attentions */
12861 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12863 (NIG_MASK_XGXS0_LINK_STATUS |
12864 NIG_MASK_XGXS0_LINK10G |
12865 NIG_MASK_SERDES0_LINK_STATUS |
12868 /* Need to take the phy out of low power mode in order
12869 * to write to access its registers
12871 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12872 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12875 /* Reset the phy */
12876 bnx2x_cl45_write(bp, &phy[port],
12882 /* Add delay of 150ms after reset */
12885 if (phy[PORT_0].addr & 0x1) {
12886 phy_blk[PORT_0] = &(phy[PORT_1]);
12887 phy_blk[PORT_1] = &(phy[PORT_0]);
12889 phy_blk[PORT_0] = &(phy[PORT_0]);
12890 phy_blk[PORT_1] = &(phy[PORT_1]);
12893 /* PART2 - Download firmware to both phys */
12894 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12895 if (CHIP_IS_E1x(bp))
12896 port_of_path = port;
12900 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12901 phy_blk[port]->addr);
12902 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12906 /* Only set bit 10 = 1 (Tx power down) */
12907 bnx2x_cl45_read(bp, phy_blk[port],
12909 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12911 /* Phase1 of TX_POWER_DOWN reset */
12912 bnx2x_cl45_write(bp, phy_blk[port],
12914 MDIO_PMA_REG_TX_POWER_DOWN,
12918 /* Toggle Transmitter: Power down and then up with 600ms delay
12923 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12924 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12925 /* Phase2 of POWER_DOWN_RESET */
12926 /* Release bit 10 (Release Tx power down) */
12927 bnx2x_cl45_read(bp, phy_blk[port],
12929 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12931 bnx2x_cl45_write(bp, phy_blk[port],
12933 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12934 usleep_range(15000, 30000);
12936 /* Read modify write the SPI-ROM version select register */
12937 bnx2x_cl45_read(bp, phy_blk[port],
12939 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12940 bnx2x_cl45_write(bp, phy_blk[port],
12942 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12944 /* set GPIO2 back to LOW */
12945 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12946 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12950 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12951 u32 shmem_base_path[],
12952 u32 shmem2_base_path[], u8 phy_index,
12957 struct bnx2x_phy phy;
12958 /* Use port1 because of the static port-swap */
12959 /* Enable the module detection interrupt */
12960 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12961 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12962 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12963 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12965 bnx2x_ext_phy_hw_reset(bp, 0);
12966 usleep_range(5000, 10000);
12967 for (port = 0; port < PORT_MAX; port++) {
12968 u32 shmem_base, shmem2_base;
12970 /* In E2, same phy is using for port0 of the two paths */
12971 if (CHIP_IS_E1x(bp)) {
12972 shmem_base = shmem_base_path[0];
12973 shmem2_base = shmem2_base_path[0];
12975 shmem_base = shmem_base_path[port];
12976 shmem2_base = shmem2_base_path[port];
12978 /* Extract the ext phy address for the port */
12979 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12982 DP(NETIF_MSG_LINK, "populate phy failed\n");
12987 bnx2x_cl45_write(bp, &phy,
12988 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12991 /* Set fault module detected LED on */
12992 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12993 MISC_REGISTERS_GPIO_HIGH,
12999 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13000 u8 *io_gpio, u8 *io_port)
13003 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13004 offsetof(struct shmem_region,
13005 dev_info.port_hw_config[PORT_0].default_cfg));
13006 switch (phy_gpio_reset) {
13007 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13011 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13015 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13019 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13023 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13027 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13031 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13035 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13040 /* Don't override the io_gpio and io_port */
13045 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13046 u32 shmem_base_path[],
13047 u32 shmem2_base_path[], u8 phy_index,
13050 s8 port, reset_gpio;
13051 u32 swap_val, swap_override;
13052 struct bnx2x_phy phy[PORT_MAX];
13053 struct bnx2x_phy *phy_blk[PORT_MAX];
13055 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13056 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13058 reset_gpio = MISC_REGISTERS_GPIO_1;
13061 /* Retrieve the reset gpio/port which control the reset.
13062 * Default is GPIO1, PORT1
13064 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13065 (u8 *)&reset_gpio, (u8 *)&port);
13067 /* Calculate the port based on port swap */
13068 port ^= (swap_val && swap_override);
13070 /* Initiate PHY reset*/
13071 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13073 usleep_range(1000, 2000);
13074 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13077 usleep_range(5000, 10000);
13079 /* PART1 - Reset both phys */
13080 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13081 u32 shmem_base, shmem2_base;
13083 /* In E2, same phy is using for port0 of the two paths */
13084 if (CHIP_IS_E1x(bp)) {
13085 shmem_base = shmem_base_path[0];
13086 shmem2_base = shmem2_base_path[0];
13087 port_of_path = port;
13089 shmem_base = shmem_base_path[port];
13090 shmem2_base = shmem2_base_path[port];
13094 /* Extract the ext phy address for the port */
13095 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13096 port_of_path, &phy[port]) !=
13098 DP(NETIF_MSG_LINK, "populate phy failed\n");
13101 /* disable attentions */
13102 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13104 (NIG_MASK_XGXS0_LINK_STATUS |
13105 NIG_MASK_XGXS0_LINK10G |
13106 NIG_MASK_SERDES0_LINK_STATUS |
13110 /* Reset the phy */
13111 bnx2x_cl45_write(bp, &phy[port],
13112 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13115 /* Add delay of 150ms after reset */
13117 if (phy[PORT_0].addr & 0x1) {
13118 phy_blk[PORT_0] = &(phy[PORT_1]);
13119 phy_blk[PORT_1] = &(phy[PORT_0]);
13121 phy_blk[PORT_0] = &(phy[PORT_0]);
13122 phy_blk[PORT_1] = &(phy[PORT_1]);
13124 /* PART2 - Download firmware to both phys */
13125 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13126 if (CHIP_IS_E1x(bp))
13127 port_of_path = port;
13130 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13131 phy_blk[port]->addr);
13132 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13135 /* Disable PHY transmitter output */
13136 bnx2x_cl45_write(bp, phy_blk[port],
13138 MDIO_PMA_REG_TX_DISABLE, 1);
13144 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13145 u32 shmem_base_path[],
13146 u32 shmem2_base_path[],
13151 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13152 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13154 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13155 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13160 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13161 u32 shmem2_base_path[], u8 phy_index,
13162 u32 ext_phy_type, u32 chip_id)
13166 switch (ext_phy_type) {
13167 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13168 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13170 phy_index, chip_id);
13172 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13173 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13175 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13177 phy_index, chip_id);
13180 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13181 /* GPIO1 affects both ports, so there's need to pull
13182 * it for single port alone
13184 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13186 phy_index, chip_id);
13188 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13189 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13190 /* GPIO3's are linked, and so both need to be toggled
13191 * to obtain required 2us pulse.
13193 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13195 phy_index, chip_id);
13197 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13202 "ext_phy 0x%x common init not required\n",
13208 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13214 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13215 u32 shmem2_base_path[], u32 chip_id)
13220 u32 ext_phy_type, ext_phy_config;
13222 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13223 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13224 DP(NETIF_MSG_LINK, "Begin common phy init\n");
13225 if (CHIP_IS_E3(bp)) {
13227 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13228 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13230 /* Check if common init was already done */
13231 phy_ver = REG_RD(bp, shmem_base_path[0] +
13232 offsetof(struct shmem_region,
13233 port_mb[PORT_0].ext_phy_fw_version));
13235 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13240 /* Read the ext_phy_type for arbitrary port(0) */
13241 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13243 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13244 shmem_base_path[0],
13246 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13247 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13249 phy_index, ext_phy_type,
13255 static void bnx2x_check_over_curr(struct link_params *params,
13256 struct link_vars *vars)
13258 struct bnx2x *bp = params->bp;
13260 u8 port = params->port;
13263 cfg_pin = (REG_RD(bp, params->shmem_base +
13264 offsetof(struct shmem_region,
13265 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13266 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13267 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13269 /* Ignore check if no external input PIN available */
13270 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13274 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13275 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13276 " been detected and the power to "
13277 "that SFP+ module has been removed"
13278 " to prevent failure of the card."
13279 " Please remove the SFP+ module and"
13280 " restart the system to clear this"
13283 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13284 bnx2x_warpcore_power_module(params, 0);
13287 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13290 /* Returns 0 if no change occured since last check; 1 otherwise. */
13291 static u8 bnx2x_analyze_link_error(struct link_params *params,
13292 struct link_vars *vars, u32 status,
13293 u32 phy_flag, u32 link_flag, u8 notify)
13295 struct bnx2x *bp = params->bp;
13296 /* Compare new value with previous value */
13298 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13300 if ((status ^ old_status) == 0)
13303 /* If values differ */
13304 switch (phy_flag) {
13305 case PHY_HALF_OPEN_CONN_FLAG:
13306 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13308 case PHY_SFP_TX_FAULT_FLAG:
13309 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13312 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13314 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13315 old_status, status);
13317 /* Do not touch the link in case physical link down */
13318 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13321 /* a. Update shmem->link_status accordingly
13322 * b. Update link_vars->link_up
13325 vars->link_status &= ~LINK_STATUS_LINK_UP;
13326 vars->link_status |= link_flag;
13328 vars->phy_flags |= phy_flag;
13330 /* activate nig drain */
13331 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13332 /* Set LED mode to off since the PHY doesn't know about these
13335 led_mode = LED_MODE_OFF;
13337 vars->link_status |= LINK_STATUS_LINK_UP;
13338 vars->link_status &= ~link_flag;
13340 vars->phy_flags &= ~phy_flag;
13341 led_mode = LED_MODE_OPER;
13343 /* Clear nig drain */
13344 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13346 bnx2x_sync_link(params, vars);
13347 /* Update the LED according to the link state */
13348 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13350 /* Update link status in the shared memory */
13351 bnx2x_update_mng(params, vars->link_status);
13353 /* C. Trigger General Attention */
13354 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13356 bnx2x_notify_link_changed(bp);
13361 /******************************************************************************
13363 * This function checks for half opened connection change indication.
13364 * When such change occurs, it calls the bnx2x_analyze_link_error
13365 * to check if Remote Fault is set or cleared. Reception of remote fault
13366 * status message in the MAC indicates that the peer's MAC has detected
13367 * a fault, for example, due to break in the TX side of fiber.
13369 ******************************************************************************/
13370 static int bnx2x_check_half_open_conn(struct link_params *params,
13371 struct link_vars *vars,
13374 struct bnx2x *bp = params->bp;
13375 u32 lss_status = 0;
13377 /* In case link status is physically up @ 10G do */
13378 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13379 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13382 if (CHIP_IS_E3(bp) &&
13383 (REG_RD(bp, MISC_REG_RESET_REG_2) &
13384 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13385 /* Check E3 XMAC */
13386 /* Note that link speed cannot be queried here, since it may be
13387 * zero while link is down. In case UMAC is active, LSS will
13388 * simply not be set
13390 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13392 /* Clear stick bits (Requires rising edge) */
13393 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13394 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13395 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13396 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13397 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13400 bnx2x_analyze_link_error(params, vars, lss_status,
13401 PHY_HALF_OPEN_CONN_FLAG,
13402 LINK_STATUS_NONE, notify);
13403 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13404 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13405 /* Check E1X / E2 BMAC */
13406 u32 lss_status_reg;
13408 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13409 NIG_REG_INGRESS_BMAC0_MEM;
13410 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13411 if (CHIP_IS_E2(bp))
13412 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13414 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13416 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13417 lss_status = (wb_data[0] > 0);
13419 bnx2x_analyze_link_error(params, vars, lss_status,
13420 PHY_HALF_OPEN_CONN_FLAG,
13421 LINK_STATUS_NONE, notify);
13425 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13426 struct link_params *params,
13427 struct link_vars *vars)
13429 struct bnx2x *bp = params->bp;
13430 u32 cfg_pin, value = 0;
13431 u8 led_change, port = params->port;
13433 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13434 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13435 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13436 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13437 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13439 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13440 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13444 led_change = bnx2x_analyze_link_error(params, vars, value,
13445 PHY_SFP_TX_FAULT_FLAG,
13446 LINK_STATUS_SFP_TX_FAULT, 1);
13449 /* Change TX_Fault led, set link status for further syncs */
13452 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13453 led_mode = MISC_REGISTERS_GPIO_HIGH;
13454 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13456 led_mode = MISC_REGISTERS_GPIO_LOW;
13457 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13460 /* If module is unapproved, led should be on regardless */
13461 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13462 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13464 bnx2x_set_e3_module_fault_led(params, led_mode);
13468 static void bnx2x_kr2_recovery(struct link_params *params,
13469 struct link_vars *vars,
13470 struct bnx2x_phy *phy)
13472 struct bnx2x *bp = params->bp;
13473 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13474 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13475 bnx2x_warpcore_restart_AN_KR(phy, params);
13478 static void bnx2x_check_kr2_wa(struct link_params *params,
13479 struct link_vars *vars,
13480 struct bnx2x_phy *phy)
13482 struct bnx2x *bp = params->bp;
13483 u16 base_page, next_page, not_kr2_device, lane;
13486 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13487 * Since some switches tend to reinit the AN process and clear the
13488 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13489 * and recovered many times
13491 if (vars->check_kr2_recovery_cnt > 0) {
13492 vars->check_kr2_recovery_cnt--;
13496 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13498 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13499 bnx2x_kr2_recovery(params, vars, phy);
13500 DP(NETIF_MSG_LINK, "No sigdet\n");
13505 lane = bnx2x_get_warpcore_lane(phy, params);
13506 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13507 MDIO_AER_BLOCK_AER_REG, lane);
13508 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13509 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13510 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13511 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13512 bnx2x_set_aer_mmd(params, phy);
13514 /* CL73 has not begun yet */
13515 if (base_page == 0) {
13516 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13517 bnx2x_kr2_recovery(params, vars, phy);
13518 DP(NETIF_MSG_LINK, "No BP\n");
13523 /* In case NP bit is not set in the BasePage, or it is set,
13524 * but only KX is advertised, declare this link partner as non-KR2
13527 not_kr2_device = (((base_page & 0x8000) == 0) ||
13528 (((base_page & 0x8000) &&
13529 ((next_page & 0xe0) == 0x20))));
13531 /* In case KR2 is already disabled, check if we need to re-enable it */
13532 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13533 if (!not_kr2_device) {
13534 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13536 bnx2x_kr2_recovery(params, vars, phy);
13540 /* KR2 is enabled, but not KR2 device */
13541 if (not_kr2_device) {
13542 /* Disable KR2 on both lanes */
13543 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13544 bnx2x_disable_kr2(params, vars, phy);
13545 /* Restart AN on leading lane */
13546 bnx2x_warpcore_restart_AN_KR(phy, params);
13551 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13554 struct bnx2x *bp = params->bp;
13555 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13556 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13557 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13558 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13560 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13565 if (CHIP_IS_E3(bp)) {
13566 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13567 bnx2x_set_aer_mmd(params, phy);
13568 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13569 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13570 bnx2x_check_kr2_wa(params, vars, phy);
13571 bnx2x_check_over_curr(params, vars);
13572 if (vars->rx_tx_asic_rst)
13573 bnx2x_warpcore_config_runtime(phy, params, vars);
13575 if ((REG_RD(bp, params->shmem_base +
13576 offsetof(struct shmem_region, dev_info.
13577 port_hw_config[params->port].default_cfg))
13578 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13579 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13580 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13581 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13582 } else if (vars->link_status &
13583 LINK_STATUS_SFP_TX_FAULT) {
13584 /* Clean trail, interrupt corrects the leds */
13585 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13586 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13587 /* Update link status in the shared memory */
13588 bnx2x_update_mng(params, vars->link_status);
13594 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13599 u8 phy_index, fan_failure_det_req = 0;
13600 struct bnx2x_phy phy;
13601 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13603 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13606 DP(NETIF_MSG_LINK, "populate phy failed\n");
13609 fan_failure_det_req |= (phy.flags &
13610 FLAGS_FAN_FAILURE_DET_REQ);
13612 return fan_failure_det_req;
13615 void bnx2x_hw_reset_phy(struct link_params *params)
13618 struct bnx2x *bp = params->bp;
13619 bnx2x_update_mng(params, 0);
13620 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13621 (NIG_MASK_XGXS0_LINK_STATUS |
13622 NIG_MASK_XGXS0_LINK10G |
13623 NIG_MASK_SERDES0_LINK_STATUS |
13626 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13628 if (params->phy[phy_index].hw_reset) {
13629 params->phy[phy_index].hw_reset(
13630 ¶ms->phy[phy_index],
13632 params->phy[phy_index] = phy_null;
13637 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13638 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13641 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13643 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13644 if (CHIP_IS_E3(bp)) {
13645 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13652 struct bnx2x_phy phy;
13653 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13655 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13656 shmem2_base, port, &phy)
13658 DP(NETIF_MSG_LINK, "populate phy failed\n");
13661 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13662 gpio_num = MISC_REGISTERS_GPIO_3;
13669 if (gpio_num == 0xff)
13672 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13673 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13675 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13676 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13677 gpio_port ^= (swap_val && swap_override);
13679 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13680 (gpio_num + (gpio_port << 2));
13682 sync_offset = shmem_base +
13683 offsetof(struct shmem_region,
13684 dev_info.port_hw_config[port].aeu_int_mask);
13685 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13687 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13688 gpio_num, gpio_port, vars->aeu_int_mask);
13691 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13693 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13695 /* Open appropriate AEU for interrupts */
13696 aeu_mask = REG_RD(bp, offset);
13697 aeu_mask |= vars->aeu_int_mask;
13698 REG_WR(bp, offset, aeu_mask);
13700 /* Enable the GPIO to trigger interrupt */
13701 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13702 val |= 1 << (gpio_num + (gpio_port << 2));
13703 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);