drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 158         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 159         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 160
 161
 162 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 163         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 164         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 165         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 166
 167 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 168         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 169         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 170
 171 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 172         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 173 #define SFP_EEPROM_OPTIONS_SIZE                 2
 174
 175 #define EDC_MODE_LINEAR                         0x0022
 176 #define EDC_MODE_LIMITING                               0x0044
 177 #define EDC_MODE_PASSIVE_DAC                    0x0055
 178
 179 /* ETS defines*/
 180 #define DCBX_INVALID_COS                                        (0xFF)
 181
 182 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 183 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 184 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 185 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 186 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 187
 188 #define MAX_PACKET_SIZE                                 (9700)
 189 #define MAX_KR_LINK_RETRY                               4
 190
 191 /**********************************************************/
 192 /*                     INTERFACE                          */
 193 /**********************************************************/
 194
 195 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 196         bnx2x_cl45_write(_bp, _phy, \
 197                 (_phy)->def_md_devad, \
 198                 (_bank + (_addr & 0xf)), \
 199                 _val)
 200
 201 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 202         bnx2x_cl45_read(_bp, _phy, \
 203                 (_phy)->def_md_devad, \
 204                 (_bank + (_addr & 0xf)), \
 205                 _val)
 206
 207 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 208 {
 209         u32 val = REG_RD(bp, reg);
 210
 211         val |= bits;
 212         REG_WR(bp, reg, val);
 213         return val;
 214 }
 215
 216 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 217 {
 218         u32 val = REG_RD(bp, reg);
 219
 220         val &= ~bits;
 221         REG_WR(bp, reg, val);
 222         return val;
 223 }
 224
 225 /*
 226  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 227  *                   or link flap can be avoided.
 228  *
 229  * @params:     link parameters
 230  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 231  *         condition code.
 232  */
 233 static int bnx2x_check_lfa(struct link_params *params)
 234 {
 235         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 236         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 237         u32 saved_val, req_val, eee_status;
 238         struct bnx2x *bp = params->bp;
 239
 240         additional_config =
 241                 REG_RD(bp, params->lfa_base +
 242                            offsetof(struct shmem_lfa, additional_config));
 243
 244         /* NOTE: must be first condition checked -
 245         * to verify DCC bit is cleared in any case!
 246         */
 247         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 248                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 249                 REG_WR(bp, params->lfa_base +
 250                            offsetof(struct shmem_lfa, additional_config),
 251                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 252                 return LFA_DCC_LFA_DISABLED;
 253         }
 254
 255         /* Verify that link is up */
 256         link_status = REG_RD(bp, params->shmem_base +
 257                              offsetof(struct shmem_region,
 258                                       port_mb[params->port].link_status));
 259         if (!(link_status & LINK_STATUS_LINK_UP))
 260                 return LFA_LINK_DOWN;
 261
 262         /* if loaded after BOOT from SAN, don't flap the link in any case and
 263          * rely on link set by preboot driver
 264          */
 265         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 266                 return 0;
 267
 268         /* Verify that loopback mode is not set */
 269         if (params->loopback_mode)
 270                 return LFA_LOOPBACK_ENABLED;
 271
 272         /* Verify that MFW supports LFA */
 273         if (!params->lfa_base)
 274                 return LFA_MFW_IS_TOO_OLD;
 275
 276         if (params->num_phys == 3) {
 277                 cfg_size = 2;
 278                 lfa_mask = 0xffffffff;
 279         } else {
 280                 cfg_size = 1;
 281                 lfa_mask = 0xffff;
 282         }
 283
 284         /* Compare Duplex */
 285         saved_val = REG_RD(bp, params->lfa_base +
 286                            offsetof(struct shmem_lfa, req_duplex));
 287         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 288         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 289                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 290                                (saved_val & lfa_mask), (req_val & lfa_mask));
 291                 return LFA_DUPLEX_MISMATCH;
 292         }
 293         /* Compare Flow Control */
 294         saved_val = REG_RD(bp, params->lfa_base +
 295                            offsetof(struct shmem_lfa, req_flow_ctrl));
 296         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 297         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 298                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 299                                (saved_val & lfa_mask), (req_val & lfa_mask));
 300                 return LFA_FLOW_CTRL_MISMATCH;
 301         }
 302         /* Compare Link Speed */
 303         saved_val = REG_RD(bp, params->lfa_base +
 304                            offsetof(struct shmem_lfa, req_line_speed));
 305         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 306         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 307                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 308                                (saved_val & lfa_mask), (req_val & lfa_mask));
 309                 return LFA_LINK_SPEED_MISMATCH;
 310         }
 311
 312         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 313                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 314                                             offsetof(struct shmem_lfa,
 315                                                      speed_cap_mask[cfg_idx]));
 316
 317                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 318                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 319                                        cur_speed_cap_mask,
 320                                        params->speed_cap_mask[cfg_idx]);
 321                         return LFA_SPEED_CAP_MISMATCH;
 322                 }
 323         }
 324
 325         cur_req_fc_auto_adv =
 326                 REG_RD(bp, params->lfa_base +
 327                        offsetof(struct shmem_lfa, additional_config)) &
 328                 REQ_FC_AUTO_ADV_MASK;
 329
 330         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 331                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 332                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 333                 return LFA_FLOW_CTRL_MISMATCH;
 334         }
 335
 336         eee_status = REG_RD(bp, params->shmem2_base +
 337                             offsetof(struct shmem2_region,
 338                                      eee_status[params->port]));
 339
 340         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 341              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 342             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 343              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 344                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 345                                eee_status);
 346                 return LFA_EEE_MISMATCH;
 347         }
 348
 349         /* LFA conditions are met */
 350         return 0;
 351 }
 352 /******************************************************************/
 353 /*                      EPIO/GPIO section                         */
 354 /******************************************************************/
 355 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 356 {
 357         u32 epio_mask, gp_oenable;
 358         *en = 0;
 359         /* Sanity check */
 360         if (epio_pin > 31) {
 361                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 362                 return;
 363         }
 364
 365         epio_mask = 1 << epio_pin;
 366         /* Set this EPIO to output */
 367         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 368         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 369
 370         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 371 }
 372 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 373 {
 374         u32 epio_mask, gp_output, gp_oenable;
 375
 376         /* Sanity check */
 377         if (epio_pin > 31) {
 378                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 379                 return;
 380         }
 381         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 382         epio_mask = 1 << epio_pin;
 383         /* Set this EPIO to output */
 384         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 385         if (en)
 386                 gp_output |= epio_mask;
 387         else
 388                 gp_output &= ~epio_mask;
 389
 390         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 391
 392         /* Set the value for this EPIO */
 393         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 394         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 395 }
 396
 397 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 398 {
 399         if (pin_cfg == PIN_CFG_NA)
 400                 return;
 401         if (pin_cfg >= PIN_CFG_EPIO0) {
 402                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 403         } else {
 404                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 405                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 406                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 407         }
 408 }
 409
 410 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 411 {
 412         if (pin_cfg == PIN_CFG_NA)
 413                 return -EINVAL;
 414         if (pin_cfg >= PIN_CFG_EPIO0) {
 415                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 416         } else {
 417                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 418                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 419                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 420         }
 421         return 0;
 422
 423 }
 424 /******************************************************************/
 425 /*                              ETS section                       */
 426 /******************************************************************/
 427 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 428 {
 429         /* ETS disabled configuration*/
 430         struct bnx2x *bp = params->bp;
 431
 432         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 433
 434         /* mapping between entry  priority to client number (0,1,2 -debug and
 435          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 436          * 3bits client num.
 437          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 438          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 439          */
 440
 441         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 442         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 443          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 444          * COS0 entry, 4 - COS1 entry.
 445          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 446          * bit4   bit3    bit2   bit1     bit0
 447          * MCP and debug are strict
 448          */
 449
 450         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 451         /* defines which entries (clients) are subjected to WFQ arbitration */
 452         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 453         /* For strict priority entries defines the number of consecutive
 454          * slots for the highest priority.
 455          */
 456         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 457         /* mapping between the CREDIT_WEIGHT registers and actual client
 458          * numbers
 459          */
 460         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 461         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 462         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 463
 464         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 466         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 467         /* ETS mode disable */
 468         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 469         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 470          * weight for COS0/COS1.
 471          */
 472         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 473         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 474         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 475         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 476         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 477         /* Defines the number of consecutive slots for the strict priority */
 478         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 479 }
 480 /******************************************************************************
 481 * Description:
 482 *       Getting min_w_val will be set according to line speed .
 483 *.
 484 ******************************************************************************/
 485 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 486 {
 487         u32 min_w_val = 0;
 488         /* Calculate min_w_val.*/
 489         if (vars->link_up) {
 490                 if (vars->line_speed == SPEED_20000)
 491                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 492                 else
 493                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 494         } else
 495                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 496         /* If the link isn't up (static configuration for example ) The
 497          * link will be according to 20GBPS.
 498          */
 499         return min_w_val;
 500 }
 501 /******************************************************************************
 502 * Description:
 503 *       Getting credit upper bound form min_w_val.
 504 *.
 505 ******************************************************************************/
 506 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 507 {
 508         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 509                                                 MAX_PACKET_SIZE);
 510         return credit_upper_bound;
 511 }
 512 /******************************************************************************
 513 * Description:
 514 *       Set credit upper bound for NIG.
 515 *.
 516 ******************************************************************************/
 517 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 518         const struct link_params *params,
 519         const u32 min_w_val)
 520 {
 521         struct bnx2x *bp = params->bp;
 522         const u8 port = params->port;
 523         const u32 credit_upper_bound =
 524             bnx2x_ets_get_credit_upper_bound(min_w_val);
 525
 526         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 527                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 528         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 529                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 531                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 532         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 533                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 534         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 535                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 536         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 537                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 538
 539         if (!port) {
 540                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 541                         credit_upper_bound);
 542                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 543                         credit_upper_bound);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 545                         credit_upper_bound);
 546         }
 547 }
 548 /******************************************************************************
 549 * Description:
 550 *       Will return the NIG ETS registers to init values.Except
 551 *       credit_upper_bound.
 552 *       That isn't used in this configuration (No WFQ is enabled) and will be
 553 *       configured acording to spec
 554 *.
 555 ******************************************************************************/
 556 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 557                                         const struct link_vars *vars)
 558 {
 559         struct bnx2x *bp = params->bp;
 560         const u8 port = params->port;
 561         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 562         /* Mapping between entry  priority to client number (0,1,2 -debug and
 563          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 564          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 565          * reset value or init tool
 566          */
 567         if (port) {
 568                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 570         } else {
 571                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 573         }
 574         /* For strict priority entries defines the number of consecutive
 575          * slots for the highest priority.
 576          */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 578                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 579         /* Mapping between the CREDIT_WEIGHT registers and actual client
 580          * numbers
 581          */
 582         if (port) {
 583                 /*Port 1 has 6 COS*/
 584                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 586         } else {
 587                 /*Port 0 has 9 COS*/
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 589                        0x43210876);
 590                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 591         }
 592
 593         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 594          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 595          * COS0 entry, 4 - COS1 entry.
 596          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 597          * bit4   bit3    bit2   bit1     bit0
 598          * MCP and debug are strict
 599          */
 600         if (port)
 601                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 602         else
 603                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 604         /* defines which entries (clients) are subjected to WFQ arbitration */
 605         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 606                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 607
 608         /* Please notice the register address are note continuous and a
 609          * for here is note appropriate.In 2 port mode port0 only COS0-5
 610          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 611          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 612          * are never used for WFQ
 613          */
 614         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 615                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 616         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 617                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 618         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 619                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 620         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 621                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 622         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 623                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 624         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 625                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 626         if (!port) {
 627                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 628                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 629                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 630         }
 631
 632         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 633 }
 634 /******************************************************************************
 635 * Description:
 636 *       Set credit upper bound for PBF.
 637 *.
 638 ******************************************************************************/
 639 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 640         const struct link_params *params,
 641         const u32 min_w_val)
 642 {
 643         struct bnx2x *bp = params->bp;
 644         const u32 credit_upper_bound =
 645             bnx2x_ets_get_credit_upper_bound(min_w_val);
 646         const u8 port = params->port;
 647         u32 base_upper_bound = 0;
 648         u8 max_cos = 0;
 649         u8 i = 0;
 650         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 651          * port mode port1 has COS0-2 that can be used for WFQ.
 652          */
 653         if (!port) {
 654                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 655                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 656         } else {
 657                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 658                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 659         }
 660
 661         for (i = 0; i < max_cos; i++)
 662                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 663 }
 664
 665 /******************************************************************************
 666 * Description:
 667 *       Will return the PBF ETS registers to init values.Except
 668 *       credit_upper_bound.
 669 *       That isn't used in this configuration (No WFQ is enabled) and will be
 670 *       configured acording to spec
 671 *.
 672 ******************************************************************************/
 673 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 674 {
 675         struct bnx2x *bp = params->bp;
 676         const u8 port = params->port;
 677         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 678         u8 i = 0;
 679         u32 base_weight = 0;
 680         u8 max_cos = 0;
 681
 682         /* Mapping between entry  priority to client number 0 - COS0
 683          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 684          * TODO_ETS - Should be done by reset value or init tool
 685          */
 686         if (port)
 687                 /*  0x688 (|011|0 10|00 1|000) */
 688                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 689         else
 690                 /*  (10 1|100 |011|0 10|00 1|000) */
 691                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 692
 693         /* TODO_ETS - Should be done by reset value or init tool */
 694         if (port)
 695                 /* 0x688 (|011|0 10|00 1|000)*/
 696                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 697         else
 698         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 699         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 700
 701         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 702                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 703
 704
 705         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 706                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 707
 708         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 709                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 710         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 711          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 712          */
 713         if (!port) {
 714                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 715                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 716         } else {
 717                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 718                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 719         }
 720
 721         for (i = 0; i < max_cos; i++)
 722                 REG_WR(bp, base_weight + (0x4 * i), 0);
 723
 724         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 725 }
 726 /******************************************************************************
 727 * Description:
 728 *       E3B0 disable will return basicly the values to init values.
 729 *.
 730 ******************************************************************************/
 731 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 732                                    const struct link_vars *vars)
 733 {
 734         struct bnx2x *bp = params->bp;
 735
 736         if (!CHIP_IS_E3B0(bp)) {
 737                 DP(NETIF_MSG_LINK,
 738                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 739                 return -EINVAL;
 740         }
 741
 742         bnx2x_ets_e3b0_nig_disabled(params, vars);
 743
 744         bnx2x_ets_e3b0_pbf_disabled(params);
 745
 746         return 0;
 747 }
 748
 749 /******************************************************************************
 750 * Description:
 751 *       Disable will return basicly the values to init values.
 752 *
 753 ******************************************************************************/
 754 int bnx2x_ets_disabled(struct link_params *params,
 755                       struct link_vars *vars)
 756 {
 757         struct bnx2x *bp = params->bp;
 758         int bnx2x_status = 0;
 759
 760         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 761                 bnx2x_ets_e2e3a0_disabled(params);
 762         else if (CHIP_IS_E3B0(bp))
 763                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 764         else {
 765                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 766                 return -EINVAL;
 767         }
 768
 769         return bnx2x_status;
 770 }
 771
 772 /******************************************************************************
 773 * Description
 774 *       Set the COS mappimg to SP and BW until this point all the COS are not
 775 *       set as SP or BW.
 776 ******************************************************************************/
 777 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 778                                   const struct bnx2x_ets_params *ets_params,
 779                                   const u8 cos_sp_bitmap,
 780                                   const u8 cos_bw_bitmap)
 781 {
 782         struct bnx2x *bp = params->bp;
 783         const u8 port = params->port;
 784         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 785         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 786         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 787         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 788
 789         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 790                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 791
 792         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 793                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 794
 795         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 796                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 797                nig_cli_subject2wfq_bitmap);
 798
 799         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 800                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 801                pbf_cli_subject2wfq_bitmap);
 802
 803         return 0;
 804 }
 805
 806 /******************************************************************************
 807 * Description:
 808 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 809 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 810 ******************************************************************************/
 811 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 812                                      const u8 cos_entry,
 813                                      const u32 min_w_val_nig,
 814                                      const u32 min_w_val_pbf,
 815                                      const u16 total_bw,
 816                                      const u8 bw,
 817                                      const u8 port)
 818 {
 819         u32 nig_reg_adress_crd_weight = 0;
 820         u32 pbf_reg_adress_crd_weight = 0;
 821         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 822         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 823         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 824
 825         switch (cos_entry) {
 826         case 0:
 827             nig_reg_adress_crd_weight =
 828                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 829                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 830              pbf_reg_adress_crd_weight = (port) ?
 831                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 832              break;
 833         case 1:
 834              nig_reg_adress_crd_weight = (port) ?
 835                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 836                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 837              pbf_reg_adress_crd_weight = (port) ?
 838                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 839              break;
 840         case 2:
 841              nig_reg_adress_crd_weight = (port) ?
 842                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 843                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 844
 845                  pbf_reg_adress_crd_weight = (port) ?
 846                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 847              break;
 848         case 3:
 849             if (port)
 850                         return -EINVAL;
 851              nig_reg_adress_crd_weight =
 852                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 853              pbf_reg_adress_crd_weight =
 854                  PBF_REG_COS3_WEIGHT_P0;
 855              break;
 856         case 4:
 857             if (port)
 858                 return -EINVAL;
 859              nig_reg_adress_crd_weight =
 860                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 861              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 862              break;
 863         case 5:
 864             if (port)
 865                 return -EINVAL;
 866              nig_reg_adress_crd_weight =
 867                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 868              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 869              break;
 870         }
 871
 872         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 873
 874         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 875
 876         return 0;
 877 }
 878 /******************************************************************************
 879 * Description:
 880 *       Calculate the total BW.A value of 0 isn't legal.
 881 *
 882 ******************************************************************************/
 883 static int bnx2x_ets_e3b0_get_total_bw(
 884         const struct link_params *params,
 885         struct bnx2x_ets_params *ets_params,
 886         u16 *total_bw)
 887 {
 888         struct bnx2x *bp = params->bp;
 889         u8 cos_idx = 0;
 890         u8 is_bw_cos_exist = 0;
 891
 892         *total_bw = 0 ;
 893         /* Calculate total BW requested */
 894         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 895                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 896                         is_bw_cos_exist = 1;
 897                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 898                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 899                                                    "was set to 0\n");
 900                                 /* This is to prevent a state when ramrods
 901                                  * can't be sent
 902                                  */
 903                                 ets_params->cos[cos_idx].params.bw_params.bw
 904                                          = 1;
 905                         }
 906                         *total_bw +=
 907                                 ets_params->cos[cos_idx].params.bw_params.bw;
 908                 }
 909         }
 910
 911         /* Check total BW is valid */
 912         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 913                 if (*total_bw == 0) {
 914                         DP(NETIF_MSG_LINK,
 915                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 916                         return -EINVAL;
 917                 }
 918                 DP(NETIF_MSG_LINK,
 919                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 920                 /* We can handle a case whre the BW isn't 100 this can happen
 921                  * if the TC are joined.
 922                  */
 923         }
 924         return 0;
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Invalidate all the sp_pri_to_cos.
 930 *
 931 ******************************************************************************/
 932 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 933 {
 934         u8 pri = 0;
 935         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 936                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 937 }
 938 /******************************************************************************
 939 * Description:
 940 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 941 *       according to sp_pri_to_cos.
 942 *
 943 ******************************************************************************/
 944 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 945                                             u8 *sp_pri_to_cos, const u8 pri,
 946                                             const u8 cos_entry)
 947 {
 948         struct bnx2x *bp = params->bp;
 949         const u8 port = params->port;
 950         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 951                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 952
 953         if (pri >= max_num_of_cos) {
 954                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 955                    "parameter Illegal strict priority\n");
 956             return -EINVAL;
 957         }
 958
 959         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 960                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 961                                    "parameter There can't be two COS's with "
 962                                    "the same strict pri\n");
 963                 return -EINVAL;
 964         }
 965
 966         sp_pri_to_cos[pri] = cos_entry;
 967         return 0;
 968
 969 }
 970
 971 /******************************************************************************
 972 * Description:
 973 *       Returns the correct value according to COS and priority in
 974 *       the sp_pri_cli register.
 975 *
 976 ******************************************************************************/
 977 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 978                                          const u8 pri_set,
 979                                          const u8 pri_offset,
 980                                          const u8 entry_size)
 981 {
 982         u64 pri_cli_nig = 0;
 983         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 984                                                     (pri_set + pri_offset));
 985
 986         return pri_cli_nig;
 987 }
 988 /******************************************************************************
 989 * Description:
 990 *       Returns the correct value according to COS and priority in the
 991 *       sp_pri_cli register for NIG.
 992 *
 993 ******************************************************************************/
 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 995 {
 996         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 997         const u8 nig_cos_offset = 3;
 998         const u8 nig_pri_offset = 3;
 999
1000         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1001                 nig_pri_offset, 4);
1002
1003 }
1004 /******************************************************************************
1005 * Description:
1006 *       Returns the correct value according to COS and priority in the
1007 *       sp_pri_cli register for PBF.
1008 *
1009 ******************************************************************************/
1010 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1011 {
1012         const u8 pbf_cos_offset = 0;
1013         const u8 pbf_pri_offset = 0;
1014
1015         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1016                 pbf_pri_offset, 3);
1017
1018 }
1019
1020 /******************************************************************************
1021 * Description:
1022 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1023 *       according to sp_pri_to_cos.(which COS has higher priority)
1024 *
1025 ******************************************************************************/
1026 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1027                                              u8 *sp_pri_to_cos)
1028 {
1029         struct bnx2x *bp = params->bp;
1030         u8 i = 0;
1031         const u8 port = params->port;
1032         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1033         u64 pri_cli_nig = 0x210;
1034         u32 pri_cli_pbf = 0x0;
1035         u8 pri_set = 0;
1036         u8 pri_bitmask = 0;
1037         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1038                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1039
1040         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1041
1042         /* Set all the strict priority first */
1043         for (i = 0; i < max_num_of_cos; i++) {
1044                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1045                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1046                                 DP(NETIF_MSG_LINK,
1047                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1048                                            "invalid cos entry\n");
1049                                 return -EINVAL;
1050                         }
1051
1052                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1053                             sp_pri_to_cos[i], pri_set);
1054
1055                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1056                             sp_pri_to_cos[i], pri_set);
1057                         pri_bitmask = 1 << sp_pri_to_cos[i];
1058                         /* COS is used remove it from bitmap.*/
1059                         if (!(pri_bitmask & cos_bit_to_set)) {
1060                                 DP(NETIF_MSG_LINK,
1061                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1062                                         "invalid There can't be two COS's with"
1063                                         " the same strict pri\n");
1064                                 return -EINVAL;
1065                         }
1066                         cos_bit_to_set &= ~pri_bitmask;
1067                         pri_set++;
1068                 }
1069         }
1070
1071         /* Set all the Non strict priority i= COS*/
1072         for (i = 0; i < max_num_of_cos; i++) {
1073                 pri_bitmask = 1 << i;
1074                 /* Check if COS was already used for SP */
1075                 if (pri_bitmask & cos_bit_to_set) {
1076                         /* COS wasn't used for SP */
1077                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1078                             i, pri_set);
1079
1080                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1081                             i, pri_set);
1082                         /* COS is used remove it from bitmap.*/
1083                         cos_bit_to_set &= ~pri_bitmask;
1084                         pri_set++;
1085                 }
1086         }
1087
1088         if (pri_set != max_num_of_cos) {
1089                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1090                                    "entries were set\n");
1091                 return -EINVAL;
1092         }
1093
1094         if (port) {
1095                 /* Only 6 usable clients*/
1096                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1097                        (u32)pri_cli_nig);
1098
1099                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1100         } else {
1101                 /* Only 9 usable clients*/
1102                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1103                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1104
1105                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1106                        pri_cli_nig_lsb);
1107                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1108                        pri_cli_nig_msb);
1109
1110                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1111         }
1112         return 0;
1113 }
1114
1115 /******************************************************************************
1116 * Description:
1117 *       Configure the COS to ETS according to BW and SP settings.
1118 ******************************************************************************/
1119 int bnx2x_ets_e3b0_config(const struct link_params *params,
1120                          const struct link_vars *vars,
1121                          struct bnx2x_ets_params *ets_params)
1122 {
1123         struct bnx2x *bp = params->bp;
1124         int bnx2x_status = 0;
1125         const u8 port = params->port;
1126         u16 total_bw = 0;
1127         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1128         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1129         u8 cos_bw_bitmap = 0;
1130         u8 cos_sp_bitmap = 0;
1131         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1132         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1133                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1134         u8 cos_entry = 0;
1135
1136         if (!CHIP_IS_E3B0(bp)) {
1137                 DP(NETIF_MSG_LINK,
1138                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1139                 return -EINVAL;
1140         }
1141
1142         if ((ets_params->num_of_cos > max_num_of_cos)) {
1143                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1144                                    "isn't supported\n");
1145                 return -EINVAL;
1146         }
1147
1148         /* Prepare sp strict priority parameters*/
1149         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1150
1151         /* Prepare BW parameters*/
1152         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1153                                                    &total_bw);
1154         if (bnx2x_status) {
1155                 DP(NETIF_MSG_LINK,
1156                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1157                 return -EINVAL;
1158         }
1159
1160         /* Upper bound is set according to current link speed (min_w_val
1161          * should be the same for upper bound and COS credit val).
1162          */
1163         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1164         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1165
1166
1167         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1168                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1169                         cos_bw_bitmap |= (1 << cos_entry);
1170                         /* The function also sets the BW in HW(not the mappin
1171                          * yet)
1172                          */
1173                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1174                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1175                                 total_bw,
1176                                 ets_params->cos[cos_entry].params.bw_params.bw,
1177                                  port);
1178                 } else if (bnx2x_cos_state_strict ==
1179                         ets_params->cos[cos_entry].state){
1180                         cos_sp_bitmap |= (1 << cos_entry);
1181
1182                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1183                                 params,
1184                                 sp_pri_to_cos,
1185                                 ets_params->cos[cos_entry].params.sp_params.pri,
1186                                 cos_entry);
1187
1188                 } else {
1189                         DP(NETIF_MSG_LINK,
1190                            "bnx2x_ets_e3b0_config cos state not valid\n");
1191                         return -EINVAL;
1192                 }
1193                 if (bnx2x_status) {
1194                         DP(NETIF_MSG_LINK,
1195                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1196                         return bnx2x_status;
1197                 }
1198         }
1199
1200         /* Set SP register (which COS has higher priority) */
1201         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1202                                                          sp_pri_to_cos);
1203
1204         if (bnx2x_status) {
1205                 DP(NETIF_MSG_LINK,
1206                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1207                 return bnx2x_status;
1208         }
1209
1210         /* Set client mapping of BW and strict */
1211         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1212                                               cos_sp_bitmap,
1213                                               cos_bw_bitmap);
1214
1215         if (bnx2x_status) {
1216                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1217                 return bnx2x_status;
1218         }
1219         return 0;
1220 }
1221 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1222 {
1223         /* ETS disabled configuration */
1224         struct bnx2x *bp = params->bp;
1225         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1226         /* Defines which entries (clients) are subjected to WFQ arbitration
1227          * COS0 0x8
1228          * COS1 0x10
1229          */
1230         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1231         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1232          * client numbers (WEIGHT_0 does not actually have to represent
1233          * client 0)
1234          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1235          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1236          */
1237         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1238
1239         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1240                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1241         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1242                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1243
1244         /* ETS mode enabled*/
1245         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1246
1247         /* Defines the number of consecutive slots for the strict priority */
1248         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1249         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1250          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1251          * entry, 4 - COS1 entry.
1252          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1253          * bit4   bit3    bit2     bit1    bit0
1254          * MCP and debug are strict
1255          */
1256         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1257
1258         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1259         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1260                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1262                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1263 }
1264
1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1266                         const u32 cos1_bw)
1267 {
1268         /* ETS disabled configuration*/
1269         struct bnx2x *bp = params->bp;
1270         const u32 total_bw = cos0_bw + cos1_bw;
1271         u32 cos0_credit_weight = 0;
1272         u32 cos1_credit_weight = 0;
1273
1274         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1275
1276         if ((!total_bw) ||
1277             (!cos0_bw) ||
1278             (!cos1_bw)) {
1279                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1280                 return;
1281         }
1282
1283         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1284                 total_bw;
1285         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1286                 total_bw;
1287
1288         bnx2x_ets_bw_limit_common(params);
1289
1290         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1292
1293         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1294         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1295 }
1296
1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1298 {
1299         /* ETS disabled configuration*/
1300         struct bnx2x *bp = params->bp;
1301         u32 val = 0;
1302
1303         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1304         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1305          * as strict.  Bits 0,1,2 - debug and management entries,
1306          * 3 - COS0 entry, 4 - COS1 entry.
1307          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1308          *  bit4   bit3   bit2      bit1     bit0
1309          * MCP and debug are strict
1310          */
1311         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1312         /* For strict priority entries defines the number of consecutive slots
1313          * for the highest priority.
1314          */
1315         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1316         /* ETS mode disable */
1317         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1318         /* Defines the number of consecutive slots for the strict priority */
1319         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1320
1321         /* Defines the number of consecutive slots for the strict priority */
1322         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1323
1324         /* Mapping between entry  priority to client number (0,1,2 -debug and
1325          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326          * 3bits client num.
1327          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1328          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1329          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1330          */
1331         val = (!strict_cos) ? 0x2318 : 0x22E0;
1332         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1333
1334         return 0;
1335 }
1336
1337 /******************************************************************/
1338 /*                      PFC section                               */
1339 /******************************************************************/
1340 static void bnx2x_update_pfc_xmac(struct link_params *params,
1341                                   struct link_vars *vars,
1342                                   u8 is_lb)
1343 {
1344         struct bnx2x *bp = params->bp;
1345         u32 xmac_base;
1346         u32 pause_val, pfc0_val, pfc1_val;
1347
1348         /* XMAC base adrr */
1349         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1350
1351         /* Initialize pause and pfc registers */
1352         pause_val = 0x18000;
1353         pfc0_val = 0xFFFF8000;
1354         pfc1_val = 0x2;
1355
1356         /* No PFC support */
1357         if (!(params->feature_config_flags &
1358               FEATURE_CONFIG_PFC_ENABLED)) {
1359
1360                 /* RX flow control - Process pause frame in receive direction
1361                  */
1362                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364
1365                 /* TX flow control - Send pause packet when buffer is full */
1366                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1367                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1368         } else {/* PFC support */
1369                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1370                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1371                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1372                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1373                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374                 /* Write pause and PFC registers */
1375                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1376                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1377                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1378                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1379
1380         }
1381
1382         /* Write pause and PFC registers */
1383         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1384         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1385         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1386
1387
1388         /* Set MAC address for source TX Pause/PFC frames */
1389         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1390                ((params->mac_addr[2] << 24) |
1391                 (params->mac_addr[3] << 16) |
1392                 (params->mac_addr[4] << 8) |
1393                 (params->mac_addr[5])));
1394         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1395                ((params->mac_addr[0] << 8) |
1396                 (params->mac_addr[1])));
1397
1398         udelay(30);
1399 }
1400
1401
1402 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1403                                     u32 pfc_frames_sent[2],
1404                                     u32 pfc_frames_received[2])
1405 {
1406         /* Read pfc statistic */
1407         struct bnx2x *bp = params->bp;
1408         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1409         u32 val_xon = 0;
1410         u32 val_xoff = 0;
1411
1412         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1413
1414         /* PFC received frames */
1415         val_xoff = REG_RD(bp, emac_base +
1416                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1417         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1418         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1419         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1420
1421         pfc_frames_received[0] = val_xon + val_xoff;
1422
1423         /* PFC received sent */
1424         val_xoff = REG_RD(bp, emac_base +
1425                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1426         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1427         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1428         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1429
1430         pfc_frames_sent[0] = val_xon + val_xoff;
1431 }
1432
1433 /* Read pfc statistic*/
1434 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1435                          u32 pfc_frames_sent[2],
1436                          u32 pfc_frames_received[2])
1437 {
1438         /* Read pfc statistic */
1439         struct bnx2x *bp = params->bp;
1440
1441         DP(NETIF_MSG_LINK, "pfc statistic\n");
1442
1443         if (!vars->link_up)
1444                 return;
1445
1446         if (vars->mac_type == MAC_TYPE_EMAC) {
1447                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1448                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1449                                         pfc_frames_received);
1450         }
1451 }
1452 /******************************************************************/
1453 /*                      MAC/PBF section                           */
1454 /******************************************************************/
1455 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1456                                u32 emac_base)
1457 {
1458         u32 new_mode, cur_mode;
1459         u32 clc_cnt;
1460         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1461          * (a value of 49==0x31) and make sure that the AUTO poll is off
1462          */
1463         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1464
1465         if (USES_WARPCORE(bp))
1466                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1467         else
1468                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1469
1470         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1471             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1472                 return;
1473
1474         new_mode = cur_mode &
1475                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1476         new_mode |= clc_cnt;
1477         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1478
1479         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1480            cur_mode, new_mode);
1481         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1482         udelay(40);
1483 }
1484
1485 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1486                                         struct link_params *params)
1487 {
1488         u8 phy_index;
1489         /* Set mdio clock per phy */
1490         for (phy_index = INT_PHY; phy_index < params->num_phys;
1491               phy_index++)
1492                 bnx2x_set_mdio_clk(bp, params->chip_id,
1493                                    params->phy[phy_index].mdio_ctrl);
1494 }
1495
1496 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1497 {
1498         u32 port4mode_ovwr_val;
1499         /* Check 4-port override enabled */
1500         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1501         if (port4mode_ovwr_val & (1<<0)) {
1502                 /* Return 4-port mode override value */
1503                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1504         }
1505         /* Return 4-port mode from input pin */
1506         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1507 }
1508
1509 static void bnx2x_emac_init(struct link_params *params,
1510                             struct link_vars *vars)
1511 {
1512         /* reset and unreset the emac core */
1513         struct bnx2x *bp = params->bp;
1514         u8 port = params->port;
1515         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1516         u32 val;
1517         u16 timeout;
1518
1519         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1520                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1521         udelay(5);
1522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1524
1525         /* init emac - use read-modify-write */
1526         /* self clear reset */
1527         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1529
1530         timeout = 200;
1531         do {
1532                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1533                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1534                 if (!timeout) {
1535                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1536                         return;
1537                 }
1538                 timeout--;
1539         } while (val & EMAC_MODE_RESET);
1540
1541         bnx2x_set_mdio_emac_per_phy(bp, params);
1542         /* Set mac address */
1543         val = ((params->mac_addr[0] << 8) |
1544                 params->mac_addr[1]);
1545         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1546
1547         val = ((params->mac_addr[2] << 24) |
1548                (params->mac_addr[3] << 16) |
1549                (params->mac_addr[4] << 8) |
1550                 params->mac_addr[5]);
1551         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1552 }
1553
1554 static void bnx2x_set_xumac_nig(struct link_params *params,
1555                                 u16 tx_pause_en,
1556                                 u8 enable)
1557 {
1558         struct bnx2x *bp = params->bp;
1559
1560         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1561                enable);
1562         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1563                enable);
1564         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1565                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1566 }
1567
1568 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1569 {
1570         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1571         u32 val;
1572         struct bnx2x *bp = params->bp;
1573         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1574                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1575                 return;
1576         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1577         if (en)
1578                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1579                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1580         else
1581                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1582                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1583         /* Disable RX and TX */
1584         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1585 }
1586
1587 static void bnx2x_umac_enable(struct link_params *params,
1588                             struct link_vars *vars, u8 lb)
1589 {
1590         u32 val;
1591         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1592         struct bnx2x *bp = params->bp;
1593         /* Reset UMAC */
1594         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1595                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1596         usleep_range(1000, 2000);
1597
1598         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1599                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1600
1601         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1602
1603         /* This register opens the gate for the UMAC despite its name */
1604         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1605
1606         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1607                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1608                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1609                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1610         switch (vars->line_speed) {
1611         case SPEED_10:
1612                 val |= (0<<2);
1613                 break;
1614         case SPEED_100:
1615                 val |= (1<<2);
1616                 break;
1617         case SPEED_1000:
1618                 val |= (2<<2);
1619                 break;
1620         case SPEED_2500:
1621                 val |= (3<<2);
1622                 break;
1623         default:
1624                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1625                                vars->line_speed);
1626                 break;
1627         }
1628         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1629                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1630
1631         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1632                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1633
1634         if (vars->duplex == DUPLEX_HALF)
1635                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1636
1637         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1638         udelay(50);
1639
1640         /* Configure UMAC for EEE */
1641         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1642                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1643                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1644                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1645                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1646         } else {
1647                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1648         }
1649
1650         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1651         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1652                ((params->mac_addr[2] << 24) |
1653                 (params->mac_addr[3] << 16) |
1654                 (params->mac_addr[4] << 8) |
1655                 (params->mac_addr[5])));
1656         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1657                ((params->mac_addr[0] << 8) |
1658                 (params->mac_addr[1])));
1659
1660         /* Enable RX and TX */
1661         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1662         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1663                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1664         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1665         udelay(50);
1666
1667         /* Remove SW Reset */
1668         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1669
1670         /* Check loopback mode */
1671         if (lb)
1672                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1673         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1674
1675         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1676          * length used by the MAC receive logic to check frames.
1677          */
1678         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1679         bnx2x_set_xumac_nig(params,
1680                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1681         vars->mac_type = MAC_TYPE_UMAC;
1682
1683 }
1684
1685 /* Define the XMAC mode */
1686 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1687 {
1688         struct bnx2x *bp = params->bp;
1689         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1690
1691         /* In 4-port mode, need to set the mode only once, so if XMAC is
1692          * already out of reset, it means the mode has already been set,
1693          * and it must not* reset the XMAC again, since it controls both
1694          * ports of the path
1695          */
1696
1697         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1698              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1699              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1700             is_port4mode &&
1701             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1702              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1703                 DP(NETIF_MSG_LINK,
1704                    "XMAC already out of reset in 4-port mode\n");
1705                 return;
1706         }
1707
1708         /* Hard reset */
1709         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1710                MISC_REGISTERS_RESET_REG_2_XMAC);
1711         usleep_range(1000, 2000);
1712
1713         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1714                MISC_REGISTERS_RESET_REG_2_XMAC);
1715         if (is_port4mode) {
1716                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1717
1718                 /* Set the number of ports on the system side to up to 2 */
1719                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1720
1721                 /* Set the number of ports on the Warp Core to 10G */
1722                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1723         } else {
1724                 /* Set the number of ports on the system side to 1 */
1725                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1726                 if (max_speed == SPEED_10000) {
1727                         DP(NETIF_MSG_LINK,
1728                            "Init XMAC to 10G x 1 port per path\n");
1729                         /* Set the number of ports on the Warp Core to 10G */
1730                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1731                 } else {
1732                         DP(NETIF_MSG_LINK,
1733                            "Init XMAC to 20G x 2 ports per path\n");
1734                         /* Set the number of ports on the Warp Core to 20G */
1735                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1736                 }
1737         }
1738         /* Soft reset */
1739         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1740                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1741         usleep_range(1000, 2000);
1742
1743         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1744                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1745
1746 }
1747
1748 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1749 {
1750         u8 port = params->port;
1751         struct bnx2x *bp = params->bp;
1752         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1753         u32 val;
1754
1755         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1756             MISC_REGISTERS_RESET_REG_2_XMAC) {
1757                 /* Send an indication to change the state in the NIG back to XON
1758                  * Clearing this bit enables the next set of this bit to get
1759                  * rising edge
1760                  */
1761                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1762                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1763                        (pfc_ctrl & ~(1<<1)));
1764                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1765                        (pfc_ctrl | (1<<1)));
1766                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1767                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1768                 if (en)
1769                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1770                 else
1771                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1772                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1773         }
1774 }
1775
1776 static int bnx2x_xmac_enable(struct link_params *params,
1777                              struct link_vars *vars, u8 lb)
1778 {
1779         u32 val, xmac_base;
1780         struct bnx2x *bp = params->bp;
1781         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1782
1783         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1784
1785         bnx2x_xmac_init(params, vars->line_speed);
1786
1787         /* This register determines on which events the MAC will assert
1788          * error on the i/f to the NIG along w/ EOP.
1789          */
1790
1791         /* This register tells the NIG whether to send traffic to UMAC
1792          * or XMAC
1793          */
1794         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1795
1796         /* When XMAC is in XLGMII mode, disable sending idles for fault
1797          * detection.
1798          */
1799         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1800                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1801                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1802                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1803                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1804                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1805                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1806                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1807         }
1808         /* Set Max packet size */
1809         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1810
1811         /* CRC append for Tx packets */
1812         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1813
1814         /* update PFC */
1815         bnx2x_update_pfc_xmac(params, vars, 0);
1816
1817         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1818                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1819                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1820                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1821         } else {
1822                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1823         }
1824
1825         /* Enable TX and RX */
1826         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1827
1828         /* Set MAC in XLGMII mode for dual-mode */
1829         if ((vars->line_speed == SPEED_20000) &&
1830             (params->phy[INT_PHY].supported &
1831              SUPPORTED_20000baseKR2_Full))
1832                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1833
1834         /* Check loopback mode */
1835         if (lb)
1836                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1837         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1838         bnx2x_set_xumac_nig(params,
1839                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1840
1841         vars->mac_type = MAC_TYPE_XMAC;
1842
1843         return 0;
1844 }
1845
1846 static int bnx2x_emac_enable(struct link_params *params,
1847                              struct link_vars *vars, u8 lb)
1848 {
1849         struct bnx2x *bp = params->bp;
1850         u8 port = params->port;
1851         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1852         u32 val;
1853
1854         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1855
1856         /* Disable BMAC */
1857         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1858                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1859
1860         /* enable emac and not bmac */
1861         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1862
1863         /* ASIC */
1864         if (vars->phy_flags & PHY_XGXS_FLAG) {
1865                 u32 ser_lane = ((params->lane_config &
1866                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1867                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1868
1869                 DP(NETIF_MSG_LINK, "XGXS\n");
1870                 /* select the master lanes (out of 0-3) */
1871                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1872                 /* select XGXS */
1873                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1874
1875         } else { /* SerDes */
1876                 DP(NETIF_MSG_LINK, "SerDes\n");
1877                 /* select SerDes */
1878                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1879         }
1880
1881         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1882                       EMAC_RX_MODE_RESET);
1883         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1884                       EMAC_TX_MODE_RESET);
1885
1886                 /* pause enable/disable */
1887                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1888                                EMAC_RX_MODE_FLOW_EN);
1889
1890                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1891                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1892                                 EMAC_TX_MODE_FLOW_EN));
1893                 if (!(params->feature_config_flags &
1894                       FEATURE_CONFIG_PFC_ENABLED)) {
1895                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1896                                 bnx2x_bits_en(bp, emac_base +
1897                                               EMAC_REG_EMAC_RX_MODE,
1898                                               EMAC_RX_MODE_FLOW_EN);
1899
1900                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1901                                 bnx2x_bits_en(bp, emac_base +
1902                                               EMAC_REG_EMAC_TX_MODE,
1903                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1904                                                EMAC_TX_MODE_FLOW_EN));
1905                 } else
1906                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1907                                       EMAC_TX_MODE_FLOW_EN);
1908
1909         /* KEEP_VLAN_TAG, promiscuous */
1910         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1911         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1912
1913         /* Setting this bit causes MAC control frames (except for pause
1914          * frames) to be passed on for processing. This setting has no
1915          * affect on the operation of the pause frames. This bit effects
1916          * all packets regardless of RX Parser packet sorting logic.
1917          * Turn the PFC off to make sure we are in Xon state before
1918          * enabling it.
1919          */
1920         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1921         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923                 /* Enable PFC again */
1924                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1925                         EMAC_REG_RX_PFC_MODE_RX_EN |
1926                         EMAC_REG_RX_PFC_MODE_TX_EN |
1927                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1928
1929                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1930                         ((0x0101 <<
1931                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1932                          (0x00ff <<
1933                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1934                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1935         }
1936         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1937
1938         /* Set Loopback */
1939         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1940         if (lb)
1941                 val |= 0x810;
1942         else
1943                 val &= ~0x810;
1944         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1945
1946         /* Enable emac */
1947         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1948
1949         /* Enable emac for jumbo packets */
1950         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1951                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1952                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1953
1954         /* Strip CRC */
1955         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1956
1957         /* Disable the NIG in/out to the bmac */
1958         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1959         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1960         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1961
1962         /* Enable the NIG in/out to the emac */
1963         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1964         val = 0;
1965         if ((params->feature_config_flags &
1966               FEATURE_CONFIG_PFC_ENABLED) ||
1967             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1968                 val = 1;
1969
1970         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1971         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1972
1973         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1974
1975         vars->mac_type = MAC_TYPE_EMAC;
1976         return 0;
1977 }
1978
1979 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1980                                    struct link_vars *vars)
1981 {
1982         u32 wb_data[2];
1983         struct bnx2x *bp = params->bp;
1984         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1985                 NIG_REG_INGRESS_BMAC0_MEM;
1986
1987         u32 val = 0x14;
1988         if ((!(params->feature_config_flags &
1989               FEATURE_CONFIG_PFC_ENABLED)) &&
1990                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1991                 /* Enable BigMAC to react on received Pause packets */
1992                 val |= (1<<5);
1993         wb_data[0] = val;
1994         wb_data[1] = 0;
1995         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1996
1997         /* TX control */
1998         val = 0xc0;
1999         if (!(params->feature_config_flags &
2000               FEATURE_CONFIG_PFC_ENABLED) &&
2001                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2002                 val |= 0x800000;
2003         wb_data[0] = val;
2004         wb_data[1] = 0;
2005         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2006 }
2007
2008 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2009                                    struct link_vars *vars,
2010                                    u8 is_lb)
2011 {
2012         /* Set rx control: Strip CRC and enable BigMAC to relay
2013          * control packets to the system as well
2014          */
2015         u32 wb_data[2];
2016         struct bnx2x *bp = params->bp;
2017         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2018                 NIG_REG_INGRESS_BMAC0_MEM;
2019         u32 val = 0x14;
2020
2021         if ((!(params->feature_config_flags &
2022               FEATURE_CONFIG_PFC_ENABLED)) &&
2023                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2024                 /* Enable BigMAC to react on received Pause packets */
2025                 val |= (1<<5);
2026         wb_data[0] = val;
2027         wb_data[1] = 0;
2028         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2029         udelay(30);
2030
2031         /* Tx control */
2032         val = 0xc0;
2033         if (!(params->feature_config_flags &
2034                                 FEATURE_CONFIG_PFC_ENABLED) &&
2035             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2036                 val |= 0x800000;
2037         wb_data[0] = val;
2038         wb_data[1] = 0;
2039         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2040
2041         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2042                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2043                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2044                 wb_data[0] = 0x0;
2045                 wb_data[0] |= (1<<0);  /* RX */
2046                 wb_data[0] |= (1<<1);  /* TX */
2047                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2048                 wb_data[0] |= (1<<3);  /* 8 cos */
2049                 wb_data[0] |= (1<<5);  /* STATS */
2050                 wb_data[1] = 0;
2051                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2052                             wb_data, 2);
2053                 /* Clear the force Xon */
2054                 wb_data[0] &= ~(1<<2);
2055         } else {
2056                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2057                 /* Disable PFC RX & TX & STATS and set 8 COS */
2058                 wb_data[0] = 0x8;
2059                 wb_data[1] = 0;
2060         }
2061
2062         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2063
2064         /* Set Time (based unit is 512 bit time) between automatic
2065          * re-sending of PP packets amd enable automatic re-send of
2066          * Per-Priroity Packet as long as pp_gen is asserted and
2067          * pp_disable is low.
2068          */
2069         val = 0x8000;
2070         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2071                 val |= (1<<16); /* enable automatic re-send */
2072
2073         wb_data[0] = val;
2074         wb_data[1] = 0;
2075         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2076                     wb_data, 2);
2077
2078         /* mac control */
2079         val = 0x3; /* Enable RX and TX */
2080         if (is_lb) {
2081                 val |= 0x4; /* Local loopback */
2082                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2083         }
2084         /* When PFC enabled, Pass pause frames towards the NIG. */
2085         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2086                 val |= ((1<<6)|(1<<5));
2087
2088         wb_data[0] = val;
2089         wb_data[1] = 0;
2090         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2091 }
2092
2093 /******************************************************************************
2094 * Description:
2095 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2096 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2097 ******************************************************************************/
2098 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2099                                            u8 cos_entry,
2100                                            u32 priority_mask, u8 port)
2101 {
2102         u32 nig_reg_rx_priority_mask_add = 0;
2103
2104         switch (cos_entry) {
2105         case 0:
2106              nig_reg_rx_priority_mask_add = (port) ?
2107                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2108                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2109              break;
2110         case 1:
2111             nig_reg_rx_priority_mask_add = (port) ?
2112                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2113                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2114             break;
2115         case 2:
2116             nig_reg_rx_priority_mask_add = (port) ?
2117                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2118                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2119             break;
2120         case 3:
2121             if (port)
2122                 return -EINVAL;
2123             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2124             break;
2125         case 4:
2126             if (port)
2127                 return -EINVAL;
2128             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2129             break;
2130         case 5:
2131             if (port)
2132                 return -EINVAL;
2133             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2134             break;
2135         }
2136
2137         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2138
2139         return 0;
2140 }
2141 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2142 {
2143         struct bnx2x *bp = params->bp;
2144
2145         REG_WR(bp, params->shmem_base +
2146                offsetof(struct shmem_region,
2147                         port_mb[params->port].link_status), link_status);
2148 }
2149
2150 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2151 {
2152         struct bnx2x *bp = params->bp;
2153
2154         if (SHMEM2_HAS(bp, link_attr_sync))
2155                 REG_WR(bp, params->shmem2_base +
2156                        offsetof(struct shmem2_region,
2157                                 link_attr_sync[params->port]), link_attr);
2158 }
2159
2160 static void bnx2x_update_pfc_nig(struct link_params *params,
2161                 struct link_vars *vars,
2162                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2163 {
2164         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2165         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2166         u32 pkt_priority_to_cos = 0;
2167         struct bnx2x *bp = params->bp;
2168         u8 port = params->port;
2169
2170         int set_pfc = params->feature_config_flags &
2171                 FEATURE_CONFIG_PFC_ENABLED;
2172         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2173
2174         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2175          * MAC control frames (that are not pause packets)
2176          * will be forwarded to the XCM.
2177          */
2178         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2179                           NIG_REG_LLH0_XCM_MASK);
2180         /* NIG params will override non PFC params, since it's possible to
2181          * do transition from PFC to SAFC
2182          */
2183         if (set_pfc) {
2184                 pause_enable = 0;
2185                 llfc_out_en = 0;
2186                 llfc_enable = 0;
2187                 if (CHIP_IS_E3(bp))
2188                         ppp_enable = 0;
2189                 else
2190                         ppp_enable = 1;
2191                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2192                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2193                 xcm_out_en = 0;
2194                 hwpfc_enable = 1;
2195         } else  {
2196                 if (nig_params) {
2197                         llfc_out_en = nig_params->llfc_out_en;
2198                         llfc_enable = nig_params->llfc_enable;
2199                         pause_enable = nig_params->pause_enable;
2200                 } else  /* Default non PFC mode - PAUSE */
2201                         pause_enable = 1;
2202
2203                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2204                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2205                 xcm_out_en = 1;
2206         }
2207
2208         if (CHIP_IS_E3(bp))
2209                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2210                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2211         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2212                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2213         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2214                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2215         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2216                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2217
2218         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2219                NIG_REG_PPP_ENABLE_0, ppp_enable);
2220
2221         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2222                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2223
2224         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2225                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2226
2227         /* Output enable for RX_XCM # IF */
2228         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2229                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2230
2231         /* HW PFC TX enable */
2232         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2233                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2234
2235         if (nig_params) {
2236                 u8 i = 0;
2237                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2238
2239                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2240                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2241                 nig_params->rx_cos_priority_mask[i], port);
2242
2243                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2244                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2245                        nig_params->llfc_high_priority_classes);
2246
2247                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2248                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2249                        nig_params->llfc_low_priority_classes);
2250         }
2251         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2252                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2253                pkt_priority_to_cos);
2254 }
2255
2256 int bnx2x_update_pfc(struct link_params *params,
2257                       struct link_vars *vars,
2258                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2259 {
2260         /* The PFC and pause are orthogonal to one another, meaning when
2261          * PFC is enabled, the pause are disabled, and when PFC is
2262          * disabled, pause are set according to the pause result.
2263          */
2264         u32 val;
2265         struct bnx2x *bp = params->bp;
2266         int bnx2x_status = 0;
2267         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2268
2269         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2270                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2271         else
2272                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2273
2274         bnx2x_update_mng(params, vars->link_status);
2275
2276         /* Update NIG params */
2277         bnx2x_update_pfc_nig(params, vars, pfc_params);
2278
2279         if (!vars->link_up)
2280                 return bnx2x_status;
2281
2282         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2283
2284         if (CHIP_IS_E3(bp)) {
2285                 if (vars->mac_type == MAC_TYPE_XMAC)
2286                         bnx2x_update_pfc_xmac(params, vars, 0);
2287         } else {
2288                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2289                 if ((val &
2290                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2291                     == 0) {
2292                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2293                         bnx2x_emac_enable(params, vars, 0);
2294                         return bnx2x_status;
2295                 }
2296                 if (CHIP_IS_E2(bp))
2297                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2298                 else
2299                         bnx2x_update_pfc_bmac1(params, vars);
2300
2301                 val = 0;
2302                 if ((params->feature_config_flags &
2303                      FEATURE_CONFIG_PFC_ENABLED) ||
2304                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2305                         val = 1;
2306                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2307         }
2308         return bnx2x_status;
2309 }
2310
2311 static int bnx2x_bmac1_enable(struct link_params *params,
2312                               struct link_vars *vars,
2313                               u8 is_lb)
2314 {
2315         struct bnx2x *bp = params->bp;
2316         u8 port = params->port;
2317         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2318                                NIG_REG_INGRESS_BMAC0_MEM;
2319         u32 wb_data[2];
2320         u32 val;
2321
2322         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2323
2324         /* XGXS control */
2325         wb_data[0] = 0x3c;
2326         wb_data[1] = 0;
2327         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2328                     wb_data, 2);
2329
2330         /* TX MAC SA */
2331         wb_data[0] = ((params->mac_addr[2] << 24) |
2332                        (params->mac_addr[3] << 16) |
2333                        (params->mac_addr[4] << 8) |
2334                         params->mac_addr[5]);
2335         wb_data[1] = ((params->mac_addr[0] << 8) |
2336                         params->mac_addr[1]);
2337         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2338
2339         /* MAC control */
2340         val = 0x3;
2341         if (is_lb) {
2342                 val |= 0x4;
2343                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2344         }
2345         wb_data[0] = val;
2346         wb_data[1] = 0;
2347         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2348
2349         /* Set rx mtu */
2350         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2351         wb_data[1] = 0;
2352         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2353
2354         bnx2x_update_pfc_bmac1(params, vars);
2355
2356         /* Set tx mtu */
2357         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2358         wb_data[1] = 0;
2359         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2360
2361         /* Set cnt max size */
2362         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2363         wb_data[1] = 0;
2364         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2365
2366         /* Configure SAFC */
2367         wb_data[0] = 0x1000200;
2368         wb_data[1] = 0;
2369         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2370                     wb_data, 2);
2371
2372         return 0;
2373 }
2374
2375 static int bnx2x_bmac2_enable(struct link_params *params,
2376                               struct link_vars *vars,
2377                               u8 is_lb)
2378 {
2379         struct bnx2x *bp = params->bp;
2380         u8 port = params->port;
2381         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2382                                NIG_REG_INGRESS_BMAC0_MEM;
2383         u32 wb_data[2];
2384
2385         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2386
2387         wb_data[0] = 0;
2388         wb_data[1] = 0;
2389         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2390         udelay(30);
2391
2392         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2393         wb_data[0] = 0x3c;
2394         wb_data[1] = 0;
2395         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2396                     wb_data, 2);
2397
2398         udelay(30);
2399
2400         /* TX MAC SA */
2401         wb_data[0] = ((params->mac_addr[2] << 24) |
2402                        (params->mac_addr[3] << 16) |
2403                        (params->mac_addr[4] << 8) |
2404                         params->mac_addr[5]);
2405         wb_data[1] = ((params->mac_addr[0] << 8) |
2406                         params->mac_addr[1]);
2407         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2408                     wb_data, 2);
2409
2410         udelay(30);
2411
2412         /* Configure SAFC */
2413         wb_data[0] = 0x1000200;
2414         wb_data[1] = 0;
2415         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2416                     wb_data, 2);
2417         udelay(30);
2418
2419         /* Set RX MTU */
2420         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2421         wb_data[1] = 0;
2422         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2423         udelay(30);
2424
2425         /* Set TX MTU */
2426         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2427         wb_data[1] = 0;
2428         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2429         udelay(30);
2430         /* Set cnt max size */
2431         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2432         wb_data[1] = 0;
2433         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2434         udelay(30);
2435         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2436
2437         return 0;
2438 }
2439
2440 static int bnx2x_bmac_enable(struct link_params *params,
2441                              struct link_vars *vars,
2442                              u8 is_lb, u8 reset_bmac)
2443 {
2444         int rc = 0;
2445         u8 port = params->port;
2446         struct bnx2x *bp = params->bp;
2447         u32 val;
2448         /* Reset and unreset the BigMac */
2449         if (reset_bmac) {
2450                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2451                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2452                 usleep_range(1000, 2000);
2453         }
2454
2455         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2456                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2457
2458         /* Enable access for bmac registers */
2459         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2460
2461         /* Enable BMAC according to BMAC type*/
2462         if (CHIP_IS_E2(bp))
2463                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2464         else
2465                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2466         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2467         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2468         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2469         val = 0;
2470         if ((params->feature_config_flags &
2471               FEATURE_CONFIG_PFC_ENABLED) ||
2472             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2473                 val = 1;
2474         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2475         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2476         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2477         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2478         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2479         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2480
2481         vars->mac_type = MAC_TYPE_BMAC;
2482         return rc;
2483 }
2484
2485 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2486 {
2487         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2488                         NIG_REG_INGRESS_BMAC0_MEM;
2489         u32 wb_data[2];
2490         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2491
2492         if (CHIP_IS_E2(bp))
2493                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2494         else
2495                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2496         /* Only if the bmac is out of reset */
2497         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2498                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2499             nig_bmac_enable) {
2500                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2501                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2502                 if (en)
2503                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2504                 else
2505                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2506                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2507                 usleep_range(1000, 2000);
2508         }
2509 }
2510
2511 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2512                             u32 line_speed)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u8 port = params->port;
2516         u32 init_crd, crd;
2517         u32 count = 1000;
2518
2519         /* Disable port */
2520         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2521
2522         /* Wait for init credit */
2523         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2524         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2526
2527         while ((init_crd != crd) && count) {
2528                 usleep_range(5000, 10000);
2529                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2530                 count--;
2531         }
2532         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2533         if (init_crd != crd) {
2534                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2535                           init_crd, crd);
2536                 return -EINVAL;
2537         }
2538
2539         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2540             line_speed == SPEED_10 ||
2541             line_speed == SPEED_100 ||
2542             line_speed == SPEED_1000 ||
2543             line_speed == SPEED_2500) {
2544                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2545                 /* Update threshold */
2546                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2547                 /* Update init credit */
2548                 init_crd = 778;         /* (800-18-4) */
2549
2550         } else {
2551                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2552                               ETH_OVREHEAD)/16;
2553                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2554                 /* Update threshold */
2555                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2556                 /* Update init credit */
2557                 switch (line_speed) {
2558                 case SPEED_10000:
2559                         init_crd = thresh + 553 - 22;
2560                         break;
2561                 default:
2562                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2563                                   line_speed);
2564                         return -EINVAL;
2565                 }
2566         }
2567         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2568         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2569                  line_speed, init_crd);
2570
2571         /* Probe the credit changes */
2572         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2573         usleep_range(5000, 10000);
2574         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2575
2576         /* Enable port */
2577         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2578         return 0;
2579 }
2580
2581 /**
2582  * bnx2x_get_emac_base - retrive emac base address
2583  *
2584  * @bp:                 driver handle
2585  * @mdc_mdio_access:    access type
2586  * @port:               port id
2587  *
2588  * This function selects the MDC/MDIO access (through emac0 or
2589  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2590  * phy has a default access mode, which could also be overridden
2591  * by nvram configuration. This parameter, whether this is the
2592  * default phy configuration, or the nvram overrun
2593  * configuration, is passed here as mdc_mdio_access and selects
2594  * the emac_base for the CL45 read/writes operations
2595  */
2596 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2597                                u32 mdc_mdio_access, u8 port)
2598 {
2599         u32 emac_base = 0;
2600         switch (mdc_mdio_access) {
2601         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2602                 break;
2603         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2604                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2605                         emac_base = GRCBASE_EMAC1;
2606                 else
2607                         emac_base = GRCBASE_EMAC0;
2608                 break;
2609         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2610                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2611                         emac_base = GRCBASE_EMAC0;
2612                 else
2613                         emac_base = GRCBASE_EMAC1;
2614                 break;
2615         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2616                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2617                 break;
2618         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2619                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2620                 break;
2621         default:
2622                 break;
2623         }
2624         return emac_base;
2625
2626 }
2627
2628 /******************************************************************/
2629 /*                      CL22 access functions                     */
2630 /******************************************************************/
2631 static int bnx2x_cl22_write(struct bnx2x *bp,
2632                                        struct bnx2x_phy *phy,
2633                                        u16 reg, u16 val)
2634 {
2635         u32 tmp, mode;
2636         u8 i;
2637         int rc = 0;
2638         /* Switch to CL22 */
2639         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2640         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2641                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2642
2643         /* Address */
2644         tmp = ((phy->addr << 21) | (reg << 16) | val |
2645                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2646                EMAC_MDIO_COMM_START_BUSY);
2647         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2648
2649         for (i = 0; i < 50; i++) {
2650                 udelay(10);
2651
2652                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2653                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2654                         udelay(5);
2655                         break;
2656                 }
2657         }
2658         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2659                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2660                 rc = -EFAULT;
2661         }
2662         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2663         return rc;
2664 }
2665
2666 static int bnx2x_cl22_read(struct bnx2x *bp,
2667                                       struct bnx2x_phy *phy,
2668                                       u16 reg, u16 *ret_val)
2669 {
2670         u32 val, mode;
2671         u16 i;
2672         int rc = 0;
2673
2674         /* Switch to CL22 */
2675         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2676         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2677                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2678
2679         /* Address */
2680         val = ((phy->addr << 21) | (reg << 16) |
2681                EMAC_MDIO_COMM_COMMAND_READ_22 |
2682                EMAC_MDIO_COMM_START_BUSY);
2683         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2684
2685         for (i = 0; i < 50; i++) {
2686                 udelay(10);
2687
2688                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2689                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2690                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2691                         udelay(5);
2692                         break;
2693                 }
2694         }
2695         if (val & EMAC_MDIO_COMM_START_BUSY) {
2696                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2697
2698                 *ret_val = 0;
2699                 rc = -EFAULT;
2700         }
2701         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2702         return rc;
2703 }
2704
2705 /******************************************************************/
2706 /*                      CL45 access functions                     */
2707 /******************************************************************/
2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2709                            u8 devad, u16 reg, u16 *ret_val)
2710 {
2711         u32 val;
2712         u16 i;
2713         int rc = 0;
2714         u32 chip_id;
2715         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2716                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2717                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2718                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2719         }
2720
2721         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2722                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2723                               EMAC_MDIO_STATUS_10MB);
2724         /* Address */
2725         val = ((phy->addr << 21) | (devad << 16) | reg |
2726                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2727                EMAC_MDIO_COMM_START_BUSY);
2728         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2729
2730         for (i = 0; i < 50; i++) {
2731                 udelay(10);
2732
2733                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2734                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2735                         udelay(5);
2736                         break;
2737                 }
2738         }
2739         if (val & EMAC_MDIO_COMM_START_BUSY) {
2740                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2741                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2742                 *ret_val = 0;
2743                 rc = -EFAULT;
2744         } else {
2745                 /* Data */
2746                 val = ((phy->addr << 21) | (devad << 16) |
2747                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2748                        EMAC_MDIO_COMM_START_BUSY);
2749                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2750
2751                 for (i = 0; i < 50; i++) {
2752                         udelay(10);
2753
2754                         val = REG_RD(bp, phy->mdio_ctrl +
2755                                      EMAC_REG_EMAC_MDIO_COMM);
2756                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2757                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2758                                 break;
2759                         }
2760                 }
2761                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2762                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2763                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2764                         *ret_val = 0;
2765                         rc = -EFAULT;
2766                 }
2767         }
2768         /* Work around for E3 A0 */
2769         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2770                 phy->flags ^= FLAGS_DUMMY_READ;
2771                 if (phy->flags & FLAGS_DUMMY_READ) {
2772                         u16 temp_val;
2773                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2774                 }
2775         }
2776
2777         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2778                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2779                                EMAC_MDIO_STATUS_10MB);
2780         return rc;
2781 }
2782
2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2784                             u8 devad, u16 reg, u16 val)
2785 {
2786         u32 tmp;
2787         u8 i;
2788         int rc = 0;
2789         u32 chip_id;
2790         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2791                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2792                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2793                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2794         }
2795
2796         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2797                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2798                               EMAC_MDIO_STATUS_10MB);
2799
2800         /* Address */
2801         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2802                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2803                EMAC_MDIO_COMM_START_BUSY);
2804         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2805
2806         for (i = 0; i < 50; i++) {
2807                 udelay(10);
2808
2809                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2810                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2811                         udelay(5);
2812                         break;
2813                 }
2814         }
2815         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2816                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2817                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2818                 rc = -EFAULT;
2819         } else {
2820                 /* Data */
2821                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2822                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2823                        EMAC_MDIO_COMM_START_BUSY);
2824                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2825
2826                 for (i = 0; i < 50; i++) {
2827                         udelay(10);
2828
2829                         tmp = REG_RD(bp, phy->mdio_ctrl +
2830                                      EMAC_REG_EMAC_MDIO_COMM);
2831                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2832                                 udelay(5);
2833                                 break;
2834                         }
2835                 }
2836                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2837                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2838                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2839                         rc = -EFAULT;
2840                 }
2841         }
2842         /* Work around for E3 A0 */
2843         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2844                 phy->flags ^= FLAGS_DUMMY_READ;
2845                 if (phy->flags & FLAGS_DUMMY_READ) {
2846                         u16 temp_val;
2847                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2848                 }
2849         }
2850         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2851                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2852                                EMAC_MDIO_STATUS_10MB);
2853         return rc;
2854 }
2855
2856 /******************************************************************/
2857 /*                      EEE section                                */
2858 /******************************************************************/
2859 static u8 bnx2x_eee_has_cap(struct link_params *params)
2860 {
2861         struct bnx2x *bp = params->bp;
2862
2863         if (REG_RD(bp, params->shmem2_base) <=
2864                    offsetof(struct shmem2_region, eee_status[params->port]))
2865                 return 0;
2866
2867         return 1;
2868 }
2869
2870 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2871 {
2872         switch (nvram_mode) {
2873         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2874                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2875                 break;
2876         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2877                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2878                 break;
2879         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2880                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2881                 break;
2882         default:
2883                 *idle_timer = 0;
2884                 break;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2891 {
2892         switch (idle_timer) {
2893         case EEE_MODE_NVRAM_BALANCED_TIME:
2894                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2895                 break;
2896         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2897                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2898                 break;
2899         case EEE_MODE_NVRAM_LATENCY_TIME:
2900                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2901                 break;
2902         default:
2903                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2904                 break;
2905         }
2906
2907         return 0;
2908 }
2909
2910 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2911 {
2912         u32 eee_mode, eee_idle;
2913         struct bnx2x *bp = params->bp;
2914
2915         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2916                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2917                         /* time value in eee_mode --> used directly*/
2918                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2919                 } else {
2920                         /* hsi value in eee_mode --> time */
2921                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2922                                                     EEE_MODE_NVRAM_MASK,
2923                                                     &eee_idle))
2924                                 return 0;
2925                 }
2926         } else {
2927                 /* hsi values in nvram --> time*/
2928                 eee_mode = ((REG_RD(bp, params->shmem_base +
2929                                     offsetof(struct shmem_region, dev_info.
2930                                     port_feature_config[params->port].
2931                                     eee_power_mode)) &
2932                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2933                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2934
2935                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2936                         return 0;
2937         }
2938
2939         return eee_idle;
2940 }
2941
2942 static int bnx2x_eee_set_timers(struct link_params *params,
2943                                    struct link_vars *vars)
2944 {
2945         u32 eee_idle = 0, eee_mode;
2946         struct bnx2x *bp = params->bp;
2947
2948         eee_idle = bnx2x_eee_calc_timer(params);
2949
2950         if (eee_idle) {
2951                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2952                        eee_idle);
2953         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2954                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2955                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2956                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2957                 return -EINVAL;
2958         }
2959
2960         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2961         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2962                 /* eee_idle in 1u --> eee_status in 16u */
2963                 eee_idle >>= 4;
2964                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2965                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2966         } else {
2967                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2968                         return -EINVAL;
2969                 vars->eee_status |= eee_mode;
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int bnx2x_eee_initial_config(struct link_params *params,
2976                                      struct link_vars *vars, u8 mode)
2977 {
2978         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2979
2980         /* Propogate params' bits --> vars (for migration exposure) */
2981         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2982                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2983         else
2984                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2985
2986         if (params->eee_mode & EEE_MODE_ADV_LPI)
2987                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2988         else
2989                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2990
2991         return bnx2x_eee_set_timers(params, vars);
2992 }
2993
2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2995                                 struct link_params *params,
2996                                 struct link_vars *vars)
2997 {
2998         struct bnx2x *bp = params->bp;
2999
3000         /* Make Certain LPI is disabled */
3001         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3002
3003         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3004
3005         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3006
3007         return 0;
3008 }
3009
3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3011                                   struct link_params *params,
3012                                   struct link_vars *vars, u8 modes)
3013 {
3014         struct bnx2x *bp = params->bp;
3015         u16 val = 0;
3016
3017         /* Mask events preventing LPI generation */
3018         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3019
3020         if (modes & SHMEM_EEE_10G_ADV) {
3021                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3022                 val |= 0x8;
3023         }
3024         if (modes & SHMEM_EEE_1G_ADV) {
3025                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3026                 val |= 0x4;
3027         }
3028
3029         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3030
3031         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3032         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3033
3034         return 0;
3035 }
3036
3037 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3038 {
3039         struct bnx2x *bp = params->bp;
3040
3041         if (bnx2x_eee_has_cap(params))
3042                 REG_WR(bp, params->shmem2_base +
3043                        offsetof(struct shmem2_region,
3044                                 eee_status[params->port]), eee_status);
3045 }
3046
3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3048                                   struct link_params *params,
3049                                   struct link_vars *vars)
3050 {
3051         struct bnx2x *bp = params->bp;
3052         u16 adv = 0, lp = 0;
3053         u32 lp_adv = 0;
3054         u8 neg = 0;
3055
3056         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3057         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3058
3059         if (lp & 0x2) {
3060                 lp_adv |= SHMEM_EEE_100M_ADV;
3061                 if (adv & 0x2) {
3062                         if (vars->line_speed == SPEED_100)
3063                                 neg = 1;
3064                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3065                 }
3066         }
3067         if (lp & 0x14) {
3068                 lp_adv |= SHMEM_EEE_1G_ADV;
3069                 if (adv & 0x14) {
3070                         if (vars->line_speed == SPEED_1000)
3071                                 neg = 1;
3072                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3073                 }
3074         }
3075         if (lp & 0x68) {
3076                 lp_adv |= SHMEM_EEE_10G_ADV;
3077                 if (adv & 0x68) {
3078                         if (vars->line_speed == SPEED_10000)
3079                                 neg = 1;
3080                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3081                 }
3082         }
3083
3084         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3085         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3086
3087         if (neg) {
3088                 DP(NETIF_MSG_LINK, "EEE is active\n");
3089                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3090         }
3091
3092 }
3093
3094 /******************************************************************/
3095 /*                      BSC access functions from E3              */
3096 /******************************************************************/
3097 static void bnx2x_bsc_module_sel(struct link_params *params)
3098 {
3099         int idx;
3100         u32 board_cfg, sfp_ctrl;
3101         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3102         struct bnx2x *bp = params->bp;
3103         u8 port = params->port;
3104         /* Read I2C output PINs */
3105         board_cfg = REG_RD(bp, params->shmem_base +
3106                            offsetof(struct shmem_region,
3107                                     dev_info.shared_hw_config.board));
3108         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3109         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3110                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3111
3112         /* Read I2C output value */
3113         sfp_ctrl = REG_RD(bp, params->shmem_base +
3114                           offsetof(struct shmem_region,
3115                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3116         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3117         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3118         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3119         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3120                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3121 }
3122
3123 static int bnx2x_bsc_read(struct link_params *params,
3124                           struct bnx2x_phy *phy,
3125                           u8 sl_devid,
3126                           u16 sl_addr,
3127                           u8 lc_addr,
3128                           u8 xfer_cnt,
3129                           u32 *data_array)
3130 {
3131         u32 val, i;
3132         int rc = 0;
3133         struct bnx2x *bp = params->bp;
3134
3135         if (xfer_cnt > 16) {
3136                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137                                         xfer_cnt);
3138                 return -EINVAL;
3139         }
3140         bnx2x_bsc_module_sel(params);
3141
3142         xfer_cnt = 16 - lc_addr;
3143
3144         /* Enable the engine */
3145         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146         val |= MCPR_IMC_COMMAND_ENABLE;
3147         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
3149         /* Program slave device ID */
3150         val = (sl_devid << 16) | sl_addr;
3151         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
3153         /* Start xfer with 0 byte to update the address pointer ???*/
3154         val = (MCPR_IMC_COMMAND_ENABLE) |
3155               (MCPR_IMC_COMMAND_WRITE_OP <<
3156                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
3160         /* Poll for completion */
3161         i = 0;
3162         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164                 udelay(10);
3165                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166                 if (i++ > 1000) {
3167                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168                                                                 i);
3169                         rc = -EFAULT;
3170                         break;
3171                 }
3172         }
3173         if (rc == -EFAULT)
3174                 return rc;
3175
3176         /* Start xfer with read op */
3177         val = (MCPR_IMC_COMMAND_ENABLE) |
3178                 (MCPR_IMC_COMMAND_READ_OP <<
3179                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181                   (xfer_cnt);
3182         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
3184         /* Poll for completion */
3185         i = 0;
3186         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188                 udelay(10);
3189                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190                 if (i++ > 1000) {
3191                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192                         rc = -EFAULT;
3193                         break;
3194                 }
3195         }
3196         if (rc == -EFAULT)
3197                 return rc;
3198
3199         for (i = (lc_addr >> 2); i < 4; i++) {
3200                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201 #ifdef __BIG_ENDIAN
3202                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203                                 ((data_array[i] & 0x0000ff00) << 8) |
3204                                 ((data_array[i] & 0x00ff0000) >> 8) |
3205                                 ((data_array[i] & 0xff000000) >> 24);
3206 #endif
3207         }
3208         return rc;
3209 }
3210
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212                                      u8 devad, u16 reg, u16 or_val)
3213 {
3214         u16 val;
3215         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217 }
3218
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220                                       struct bnx2x_phy *phy,
3221                                       u8 devad, u16 reg, u16 and_val)
3222 {
3223         u16 val;
3224         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226 }
3227
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229                    u8 devad, u16 reg, u16 *ret_val)
3230 {
3231         u8 phy_index;
3232         /* Probe for the phy according to the given phy_addr, and execute
3233          * the read request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_read(params->bp,
3238                                                &params->phy[phy_index], devad,
3239                                                reg, ret_val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246                     u8 devad, u16 reg, u16 val)
3247 {
3248         u8 phy_index;
3249         /* Probe for the phy according to the given phy_addr, and execute
3250          * the write request on it
3251          */
3252         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253                 if (params->phy[phy_index].addr == phy_addr) {
3254                         return bnx2x_cl45_write(params->bp,
3255                                                 &params->phy[phy_index], devad,
3256                                                 reg, val);
3257                 }
3258         }
3259         return -EINVAL;
3260 }
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262                                   struct link_params *params)
3263 {
3264         u8 lane = 0;
3265         struct bnx2x *bp = params->bp;
3266         u32 path_swap, path_swap_ovr;
3267         u8 path, port;
3268
3269         path = BP_PATH(bp);
3270         port = params->port;
3271
3272         if (bnx2x_is_4_port_mode(bp)) {
3273                 u32 port_swap, port_swap_ovr;
3274
3275                 /* Figure out path swap value */
3276                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277                 if (path_swap_ovr & 0x1)
3278                         path_swap = (path_swap_ovr & 0x2);
3279                 else
3280                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282                 if (path_swap)
3283                         path = path ^ 1;
3284
3285                 /* Figure out port swap value */
3286                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287                 if (port_swap_ovr & 0x1)
3288                         port_swap = (port_swap_ovr & 0x2);
3289                 else
3290                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292                 if (port_swap)
3293                         port = port ^ 1;
3294
3295                 lane = (port<<1) + path;
3296         } else { /* Two port mode - no port swap */
3297
3298                 /* Figure out path swap value */
3299                 path_swap_ovr =
3300                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301                 if (path_swap_ovr & 0x1) {
3302                         path_swap = (path_swap_ovr & 0x2);
3303                 } else {
3304                         path_swap =
3305                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306                 }
3307                 if (path_swap)
3308                         path = path ^ 1;
3309
3310                 lane = path << 1 ;
3311         }
3312         return lane;
3313 }
3314
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316                               struct bnx2x_phy *phy)
3317 {
3318         u32 ser_lane;
3319         u16 offset, aer_val;
3320         struct bnx2x *bp = params->bp;
3321         ser_lane = ((params->lane_config &
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
3325         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326                 (phy->addr + ser_lane) : 0;
3327
3328         if (USES_WARPCORE(bp)) {
3329                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330                 /* In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386                                      struct link_params *params,
3387                                      u32 action)
3388 {
3389         struct bnx2x *bp = params->bp;
3390         switch (action) {
3391         case PHY_INIT:
3392                 /* Set correct devad */
3393                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395                        phy->def_md_devad);
3396                 break;
3397         }
3398 }
3399
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3401 {
3402         struct bnx2x *bp = params->bp;
3403         u8 port;
3404         u32 val;
3405         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406         port = params->port;
3407
3408         val = XGXS_RESET_BITS << (port*16);
3409
3410         /* Reset and unreset the SerDes/XGXS */
3411         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412         udelay(500);
3413         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415                                  PHY_INIT);
3416 }
3417
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419                                      struct link_params *params, u16 *ieee_fc)
3420 {
3421         struct bnx2x *bp = params->bp;
3422         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423         /* Resolve pause mode and advertisement Please refer to Table
3424          * 28B-3 of the 802.3ab-1999 spec
3425          */
3426
3427         switch (phy->req_flow_ctrl) {
3428         case BNX2X_FLOW_CTRL_AUTO:
3429                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3430                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3431                 else
3432                         *ieee_fc |=
3433                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3434                 break;
3435
3436         case BNX2X_FLOW_CTRL_TX:
3437                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3438                 break;
3439
3440         case BNX2X_FLOW_CTRL_RX:
3441         case BNX2X_FLOW_CTRL_BOTH:
3442                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3443                 break;
3444
3445         case BNX2X_FLOW_CTRL_NONE:
3446         default:
3447                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3448                 break;
3449         }
3450         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3451 }
3452
3453 static void set_phy_vars(struct link_params *params,
3454                          struct link_vars *vars)
3455 {
3456         struct bnx2x *bp = params->bp;
3457         u8 actual_phy_idx, phy_index, link_cfg_idx;
3458         u8 phy_config_swapped = params->multi_phy_config &
3459                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3460         for (phy_index = INT_PHY; phy_index < params->num_phys;
3461               phy_index++) {
3462                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3463                 actual_phy_idx = phy_index;
3464                 if (phy_config_swapped) {
3465                         if (phy_index == EXT_PHY1)
3466                                 actual_phy_idx = EXT_PHY2;
3467                         else if (phy_index == EXT_PHY2)
3468                                 actual_phy_idx = EXT_PHY1;
3469                 }
3470                 params->phy[actual_phy_idx].req_flow_ctrl =
3471                         params->req_flow_ctrl[link_cfg_idx];
3472
3473                 params->phy[actual_phy_idx].req_line_speed =
3474                         params->req_line_speed[link_cfg_idx];
3475
3476                 params->phy[actual_phy_idx].speed_cap_mask =
3477                         params->speed_cap_mask[link_cfg_idx];
3478
3479                 params->phy[actual_phy_idx].req_duplex =
3480                         params->req_duplex[link_cfg_idx];
3481
3482                 if (params->req_line_speed[link_cfg_idx] ==
3483                     SPEED_AUTO_NEG)
3484                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3485
3486                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3487                            " speed_cap_mask %x\n",
3488                            params->phy[actual_phy_idx].req_flow_ctrl,
3489                            params->phy[actual_phy_idx].req_line_speed,
3490                            params->phy[actual_phy_idx].speed_cap_mask);
3491         }
3492 }
3493
3494 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3495                                     struct bnx2x_phy *phy,
3496                                     struct link_vars *vars)
3497 {
3498         u16 val;
3499         struct bnx2x *bp = params->bp;
3500         /* Read modify write pause advertizing */
3501         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3502
3503         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3504
3505         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3506         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3507         if ((vars->ieee_fc &
3508             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3509             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3510                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3511         }
3512         if ((vars->ieee_fc &
3513             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3514             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3515                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3516         }
3517         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3518         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3519 }
3520
3521 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3522 {                                               /*  LD      LP   */
3523         switch (pause_result) {                 /* ASYM P ASYM P */
3524         case 0xb:                               /*   1  0   1  1 */
3525                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3526                 break;
3527
3528         case 0xe:                               /*   1  1   1  0 */
3529                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3530                 break;
3531
3532         case 0x5:                               /*   0  1   0  1 */
3533         case 0x7:                               /*   0  1   1  1 */
3534         case 0xd:                               /*   1  1   0  1 */
3535         case 0xf:                               /*   1  1   1  1 */
3536                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3537                 break;
3538
3539         default:
3540                 break;
3541         }
3542         if (pause_result & (1<<0))
3543                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3544         if (pause_result & (1<<1))
3545                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3546
3547 }
3548
3549 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3550                                         struct link_params *params,
3551                                         struct link_vars *vars)
3552 {
3553         u16 ld_pause;           /* local */
3554         u16 lp_pause;           /* link partner */
3555         u16 pause_result;
3556         struct bnx2x *bp = params->bp;
3557         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3558                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3559                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3560         } else if (CHIP_IS_E3(bp) &&
3561                 SINGLE_MEDIA_DIRECT(params)) {
3562                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3563                 u16 gp_status, gp_mask;
3564                 bnx2x_cl45_read(bp, phy,
3565                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3566                                 &gp_status);
3567                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3568                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3569                         lane;
3570                 if ((gp_status & gp_mask) == gp_mask) {
3571                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3572                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3573                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3574                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3575                 } else {
3576                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3577                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3578                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3579                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3580                         ld_pause = ((ld_pause &
3581                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3582                                     << 3);
3583                         lp_pause = ((lp_pause &
3584                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3585                                     << 3);
3586                 }
3587         } else {
3588                 bnx2x_cl45_read(bp, phy,
3589                                 MDIO_AN_DEVAD,
3590                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3591                 bnx2x_cl45_read(bp, phy,
3592                                 MDIO_AN_DEVAD,
3593                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3594         }
3595         pause_result = (ld_pause &
3596                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3597         pause_result |= (lp_pause &
3598                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3599         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3600         bnx2x_pause_resolve(vars, pause_result);
3601
3602 }
3603
3604 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3605                                    struct link_params *params,
3606                                    struct link_vars *vars)
3607 {
3608         u8 ret = 0;
3609         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3610         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3611                 /* Update the advertised flow-controled of LD/LP in AN */
3612                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3613                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3614                 /* But set the flow-control result as the requested one */
3615                 vars->flow_ctrl = phy->req_flow_ctrl;
3616         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3617                 vars->flow_ctrl = params->req_fc_auto_adv;
3618         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3619                 ret = 1;
3620                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3621         }
3622         return ret;
3623 }
3624 /******************************************************************/
3625 /*                      Warpcore section                          */
3626 /******************************************************************/
3627 /* The init_internal_warpcore should mirror the xgxs,
3628  * i.e. reset the lane (if needed), set aer for the
3629  * init configuration, and set/clear SGMII flag. Internal
3630  * phy init is done purely in phy_init stage.
3631  */
3632 #define WC_TX_DRIVER(post2, idriver, ipre) \
3633         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3634          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3635          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3636
3637 #define WC_TX_FIR(post, main, pre) \
3638         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3639          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3640          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3641
3642 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3643                                          struct link_params *params,
3644                                          struct link_vars *vars)
3645 {
3646         struct bnx2x *bp = params->bp;
3647         u16 i;
3648         static struct bnx2x_reg_set reg_set[] = {
3649                 /* Step 1 - Program the TX/RX alignment markers */
3650                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3651                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3652                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3653                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3654                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3655                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3656                 /* Step 2 - Configure the NP registers */
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3658                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3659                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3662                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3663                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3666         };
3667         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3668
3669         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3670                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3671
3672         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3673                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3674                                  reg_set[i].val);
3675
3676         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3677         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3678         bnx2x_update_link_attr(params, vars->link_attr_sync);
3679 }
3680
3681 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3682                                                struct link_params *params)
3683 {
3684         struct bnx2x *bp = params->bp;
3685
3686         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3687         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3688                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3689         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3690                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3691 }
3692
3693 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3694                                          struct link_params *params)
3695 {
3696         /* Restart autoneg on the leading lane only */
3697         struct bnx2x *bp = params->bp;
3698         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3699         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3700                           MDIO_AER_BLOCK_AER_REG, lane);
3701         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3702                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3703
3704         /* Restore AER */
3705         bnx2x_set_aer_mmd(params, phy);
3706 }
3707
3708 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3709                                         struct link_params *params,
3710                                         struct link_vars *vars) {
3711         u16 lane, i, cl72_ctrl, an_adv = 0;
3712         u16 ucode_ver;
3713         struct bnx2x *bp = params->bp;
3714         static struct bnx2x_reg_set reg_set[] = {
3715                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3716                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3717                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3718                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3719                 /* Disable Autoneg: re-enable it after adv is done. */
3720                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3721                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3722                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3723         };
3724         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3725         /* Set to default registers that may be overriden by 10G force */
3726         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3727                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3728                                  reg_set[i].val);
3729
3730         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3731                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3732         cl72_ctrl &= 0x08ff;
3733         cl72_ctrl |= 0x3800;
3734         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3735                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3736
3737         /* Check adding advertisement for 1G KX */
3738         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3739              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3740             (vars->line_speed == SPEED_1000)) {
3741                 u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3742                 an_adv |= (1<<5);
3743
3744                 /* Enable CL37 1G Parallel Detect */
3745                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3746                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3747         }
3748         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3749              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3750             (vars->line_speed ==  SPEED_10000)) {
3751                 /* Check adding advertisement for 10G KR */
3752                 an_adv |= (1<<7);
3753                 /* Enable 10G Parallel Detect */
3754                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3755                                   MDIO_AER_BLOCK_AER_REG, 0);
3756
3757                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3758                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3759                 bnx2x_set_aer_mmd(params, phy);
3760                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3761         }
3762
3763         /* Set Transmit PMD settings */
3764         lane = bnx2x_get_warpcore_lane(phy, params);
3765         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3766                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3767                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3768         /* Configure the next lane if dual mode */
3769         if (phy->flags & FLAGS_WC_DUAL_MODE)
3770                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3772                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3773         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3774                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3775                          0x03f0);
3776         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3778                          0x03f0);
3779
3780         /* Advertised speeds */
3781         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3782                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3783
3784         /* Advertised and set FEC (Forward Error Correction) */
3785         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3786                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3787                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3788                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3789
3790         /* Enable CL37 BAM */
3791         if (REG_RD(bp, params->shmem_base +
3792                    offsetof(struct shmem_region, dev_info.
3793                             port_hw_config[params->port].default_cfg)) &
3794             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3795                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3796                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3797                                          1);
3798                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3799         }
3800
3801         /* Advertise pause */
3802         bnx2x_ext_phy_set_pause(params, phy, vars);
3803         /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3804          */
3805         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3806                         MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver);
3807         if (ucode_ver < 0xd108) {
3808                 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n",
3809                                ucode_ver);
3810                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3811         }
3812         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3813                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3814
3815         /* Over 1G - AN local device user page 1 */
3816         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3818
3819         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3820              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3821             (phy->req_line_speed == SPEED_20000)) {
3822
3823                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3824                                   MDIO_AER_BLOCK_AER_REG, lane);
3825
3826                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3827                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3828                                          (1<<11));
3829
3830                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3831                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3832                 bnx2x_set_aer_mmd(params, phy);
3833
3834                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3835         }
3836
3837         /* Enable Autoneg: only on the main lane */
3838         bnx2x_warpcore_restart_AN_KR(phy, params);
3839 }
3840
3841 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3842                                       struct link_params *params,
3843                                       struct link_vars *vars)
3844 {
3845         struct bnx2x *bp = params->bp;
3846         u16 val16, i, lane;
3847         static struct bnx2x_reg_set reg_set[] = {
3848                 /* Disable Autoneg */
3849                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3850                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3851                         0x3f00},
3852                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3853                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3854                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3855                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3856                 /* Leave cl72 training enable, needed for KR */
3857                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3858         };
3859
3860         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3861                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3862                                  reg_set[i].val);
3863
3864         lane = bnx2x_get_warpcore_lane(phy, params);
3865         /* Global registers */
3866         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3867                           MDIO_AER_BLOCK_AER_REG, 0);
3868         /* Disable CL36 PCS Tx */
3869         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3870                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3871         val16 &= ~(0x0011 << lane);
3872         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3873                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3874
3875         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3876                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3877         val16 |= (0x0303 << (lane << 1));
3878         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3880         /* Restore AER */
3881         bnx2x_set_aer_mmd(params, phy);
3882         /* Set speed via PMA/PMD register */
3883         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3884                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3885
3886         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3887                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3888
3889         /* Enable encoded forced speed */
3890         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3892
3893         /* Turn TX scramble payload only the 64/66 scrambler */
3894         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3895                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3896
3897         /* Turn RX scramble payload only the 64/66 scrambler */
3898         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3899                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3900
3901         /* Set and clear loopback to cause a reset to 64/66 decoder */
3902         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3903                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3904         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3905                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3906
3907 }
3908
3909 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3910                                        struct link_params *params,
3911                                        u8 is_xfi)
3912 {
3913         struct bnx2x *bp = params->bp;
3914         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3915         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3916
3917         /* Hold rxSeqStart */
3918         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3919                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3920
3921         /* Hold tx_fifo_reset */
3922         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3923                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3924
3925         /* Disable CL73 AN */
3926         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3927
3928         /* Disable 100FX Enable and Auto-Detect */
3929         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3930                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3931
3932         /* Disable 100FX Idle detect */
3933         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3934                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3935
3936         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3937         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3938                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3939
3940         /* Turn off auto-detect & fiber mode */
3941         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3942                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3943                                   0xFFEE);
3944
3945         /* Set filter_force_link, disable_false_link and parallel_detect */
3946         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3947                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3948         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3949                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3950                          ((val | 0x0006) & 0xFFFE));
3951
3952         /* Set XFI / SFI */
3953         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3954                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3955
3956         misc1_val &= ~(0x1f);
3957
3958         if (is_xfi) {
3959                 misc1_val |= 0x5;
3960                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3961                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3962         } else {
3963                 cfg_tap_val = REG_RD(bp, params->shmem_base +
3964                                      offsetof(struct shmem_region, dev_info.
3965                                               port_hw_config[params->port].
3966                                               sfi_tap_values));
3967
3968                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3969
3970                 tx_drv_brdct = (cfg_tap_val &
3971                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3972                                PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3973
3974                 misc1_val |= 0x9;
3975
3976                 /* TAP values are controlled by nvram, if value there isn't 0 */
3977                 if (tx_equal)
3978                         tap_val = (u16)tx_equal;
3979                 else
3980                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3981
3982                 if (tx_drv_brdct)
3983                         tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
3984                                                      0x06);
3985                 else
3986                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3987         }
3988         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3990
3991         /* Set Transmit PMD settings */
3992         lane = bnx2x_get_warpcore_lane(phy, params);
3993         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3994                          MDIO_WC_REG_TX_FIR_TAP,
3995                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3996         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3997                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3998                          tx_driver_val);
3999
4000         /* Enable fiber mode, enable and invert sig_det */
4001         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4002                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4003
4004         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4005         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4006                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4007
4008         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4009
4010         /* 10G XFI Full Duplex */
4011         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4012                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4013
4014         /* Release tx_fifo_reset */
4015         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4016                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4017                                   0xFFFE);
4018         /* Release rxSeqStart */
4019         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4020                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4021 }
4022
4023 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4024                                              struct link_params *params)
4025 {
4026         u16 val;
4027         struct bnx2x *bp = params->bp;
4028         /* Set global registers, so set AER lane to 0 */
4029         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4030                           MDIO_AER_BLOCK_AER_REG, 0);
4031
4032         /* Disable sequencer */
4033         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4034                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4035
4036         bnx2x_set_aer_mmd(params, phy);
4037
4038         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4039                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4040         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4041                          MDIO_AN_REG_CTRL, 0);
4042         /* Turn off CL73 */
4043         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4044                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4045         val &= ~(1<<5);
4046         val |= (1<<6);
4047         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4049
4050         /* Set 20G KR2 force speed */
4051         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4052                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4053
4054         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4055                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4056
4057         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4058                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4059         val &= ~(3<<14);
4060         val |= (1<<15);
4061         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4063         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4064                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4065
4066         /* Enable sequencer (over lane 0) */
4067         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4068                           MDIO_AER_BLOCK_AER_REG, 0);
4069
4070         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4071                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4072
4073         bnx2x_set_aer_mmd(params, phy);
4074 }
4075
4076 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4077                                          struct bnx2x_phy *phy,
4078                                          u16 lane)
4079 {
4080         /* Rx0 anaRxControl1G */
4081         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4082                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4083
4084         /* Rx2 anaRxControl1G */
4085         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4087
4088         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4089                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4090
4091         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4093
4094         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4096
4097         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4099
4100         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4101                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4102
4103         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4105
4106         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4108
4109         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4110                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4111
4112         /* Serdes Digital Misc1 */
4113         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4114                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4115
4116         /* Serdes Digital4 Misc3 */
4117         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4118                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4119
4120         /* Set Transmit PMD settings */
4121         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4122                          MDIO_WC_REG_TX_FIR_TAP,
4123                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4124                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4125         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4127                          WC_TX_DRIVER(0x02, 0x02, 0x02));
4128 }
4129
4130 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4131                                            struct link_params *params,
4132                                            u8 fiber_mode,
4133                                            u8 always_autoneg)
4134 {
4135         struct bnx2x *bp = params->bp;
4136         u16 val16, digctrl_kx1, digctrl_kx2;
4137
4138         /* Clear XFI clock comp in non-10G single lane mode. */
4139         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4140                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4141
4142         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4143
4144         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4145                 /* SGMII Autoneg */
4146                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4147                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4148                                          0x1000);
4149                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4150         } else {
4151                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4152                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4153                 val16 &= 0xcebf;
4154                 switch (phy->req_line_speed) {
4155                 case SPEED_10:
4156                         break;
4157                 case SPEED_100:
4158                         val16 |= 0x2000;
4159                         break;
4160                 case SPEED_1000:
4161                         val16 |= 0x0040;
4162                         break;
4163                 default:
4164                         DP(NETIF_MSG_LINK,
4165                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4166                         return;
4167                 }
4168
4169                 if (phy->req_duplex == DUPLEX_FULL)
4170                         val16 |= 0x0100;
4171
4172                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4174
4175                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4176                                phy->req_line_speed);
4177                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4178                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4179                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4180         }
4181
4182         /* SGMII Slave mode and disable signal detect */
4183         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4184                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4185         if (fiber_mode)
4186                 digctrl_kx1 = 1;
4187         else
4188                 digctrl_kx1 &= 0xff4a;
4189
4190         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4191                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4192                         digctrl_kx1);
4193
4194         /* Turn off parallel detect */
4195         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4196                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4197         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4198                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4199                         (digctrl_kx2 & ~(1<<2)));
4200
4201         /* Re-enable parallel detect */
4202         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4203                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4204                         (digctrl_kx2 | (1<<2)));
4205
4206         /* Enable autodet */
4207         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4208                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4209                         (digctrl_kx1 | 0x10));
4210 }
4211
4212 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4213                                       struct bnx2x_phy *phy,
4214                                       u8 reset)
4215 {
4216         u16 val;
4217         /* Take lane out of reset after configuration is finished */
4218         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4219                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4220         if (reset)
4221                 val |= 0xC000;
4222         else
4223                 val &= 0x3FFF;
4224         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4225                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4226         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4227                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4228 }
4229 /* Clear SFI/XFI link settings registers */
4230 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4231                                       struct link_params *params,
4232                                       u16 lane)
4233 {
4234         struct bnx2x *bp = params->bp;
4235         u16 i;
4236         static struct bnx2x_reg_set wc_regs[] = {
4237                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4238                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4239                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4240                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4241                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4242                         0x0195},
4243                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4244                         0x0007},
4245                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4246                         0x0002},
4247                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4248                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4249                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4250                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4251         };
4252         /* Set XFI clock comp as default. */
4253         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4254                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4255
4256         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4257                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4258                                  wc_regs[i].val);
4259
4260         lane = bnx2x_get_warpcore_lane(phy, params);
4261         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4262                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4263
4264 }
4265
4266 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4267                                                 u32 chip_id,
4268                                                 u32 shmem_base, u8 port,
4269                                                 u8 *gpio_num, u8 *gpio_port)
4270 {
4271         u32 cfg_pin;
4272         *gpio_num = 0;
4273         *gpio_port = 0;
4274         if (CHIP_IS_E3(bp)) {
4275                 cfg_pin = (REG_RD(bp, shmem_base +
4276                                 offsetof(struct shmem_region,
4277                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4278                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4279                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4280
4281                 /* Should not happen. This function called upon interrupt
4282                  * triggered by GPIO ( since EPIO can only generate interrupts
4283                  * to MCP).
4284                  * So if this function was called and none of the GPIOs was set,
4285                  * it means the shit hit the fan.
4286                  */
4287                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4288                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4289                         DP(NETIF_MSG_LINK,
4290                            "No cfg pin %x for module detect indication\n",
4291                            cfg_pin);
4292                         return -EINVAL;
4293                 }
4294
4295                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4296                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4297         } else {
4298                 *gpio_num = MISC_REGISTERS_GPIO_3;
4299                 *gpio_port = port;
4300         }
4301
4302         return 0;
4303 }
4304
4305 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4306                                        struct link_params *params)
4307 {
4308         struct bnx2x *bp = params->bp;
4309         u8 gpio_num, gpio_port;
4310         u32 gpio_val;
4311         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4312                                       params->shmem_base, params->port,
4313                                       &gpio_num, &gpio_port) != 0)
4314                 return 0;
4315         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4316
4317         /* Call the handling function in case module is detected */
4318         if (gpio_val == 0)
4319                 return 1;
4320         else
4321                 return 0;
4322 }
4323 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4324                                      struct link_params *params)
4325 {
4326         u16 gp2_status_reg0, lane;
4327         struct bnx2x *bp = params->bp;
4328
4329         lane = bnx2x_get_warpcore_lane(phy, params);
4330
4331         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4332                                  &gp2_status_reg0);
4333
4334         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4335 }
4336
4337 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4338                                           struct link_params *params,
4339                                           struct link_vars *vars)
4340 {
4341         struct bnx2x *bp = params->bp;
4342         u32 serdes_net_if;
4343         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4344         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4345
4346         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4347
4348         if (!vars->turn_to_run_wc_rt)
4349                 return;
4350
4351         /* Return if there is no link partner */
4352         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4353                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4354                 return;
4355         }
4356
4357         if (vars->rx_tx_asic_rst) {
4358                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4359                                 offsetof(struct shmem_region, dev_info.
4360                                 port_hw_config[params->port].default_cfg)) &
4361                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4362
4363                 switch (serdes_net_if) {
4364                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4365                         /* Do we get link yet? */
4366                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4367                                         &gp_status1);
4368                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4369                                 /*10G KR*/
4370                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4371
4372                         DP(NETIF_MSG_LINK,
4373                                 "gp_status1 0x%x\n", gp_status1);
4374
4375                         if (lnkup_kr || lnkup) {
4376                                         vars->rx_tx_asic_rst = 0;
4377                                         DP(NETIF_MSG_LINK,
4378                                         "link up, rx_tx_asic_rst 0x%x\n",
4379                                         vars->rx_tx_asic_rst);
4380                         } else {
4381                                 /* Reset the lane to see if link comes up.*/
4382                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4383                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4384
4385                                 /* Restart Autoneg */
4386                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4387                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4388
4389                                 vars->rx_tx_asic_rst--;
4390                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4391                                 vars->rx_tx_asic_rst);
4392                         }
4393                         break;
4394
4395                 default:
4396                         break;
4397                 }
4398
4399         } /*params->rx_tx_asic_rst*/
4400
4401 }
4402 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4403                                       struct link_params *params)
4404 {
4405         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4406         struct bnx2x *bp = params->bp;
4407         bnx2x_warpcore_clear_regs(phy, params, lane);
4408         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4409              SPEED_10000) &&
4410             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4411                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4412                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4413         } else {
4414                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4415                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4416         }
4417 }
4418
4419 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4420                                          struct bnx2x_phy *phy,
4421                                          u8 tx_en)
4422 {
4423         struct bnx2x *bp = params->bp;
4424         u32 cfg_pin;
4425         u8 port = params->port;
4426
4427         cfg_pin = REG_RD(bp, params->shmem_base +
4428                          offsetof(struct shmem_region,
4429                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4430                 PORT_HW_CFG_E3_TX_LASER_MASK;
4431         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4432         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4433
4434         /* For 20G, the expected pin to be used is 3 pins after the current */
4435         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4436         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4437                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4438 }
4439
4440 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4441                                        struct link_params *params,
4442                                        struct link_vars *vars)
4443 {
4444         struct bnx2x *bp = params->bp;
4445         u32 serdes_net_if;
4446         u8 fiber_mode;
4447         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4448         serdes_net_if = (REG_RD(bp, params->shmem_base +
4449                          offsetof(struct shmem_region, dev_info.
4450                                   port_hw_config[params->port].default_cfg)) &
4451                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4452         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4453                            "serdes_net_if = 0x%x\n",
4454                        vars->line_speed, serdes_net_if);
4455         bnx2x_set_aer_mmd(params, phy);
4456         bnx2x_warpcore_reset_lane(bp, phy, 1);
4457         vars->phy_flags |= PHY_XGXS_FLAG;
4458         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4459             (phy->req_line_speed &&
4460              ((phy->req_line_speed == SPEED_100) ||
4461               (phy->req_line_speed == SPEED_10)))) {
4462                 vars->phy_flags |= PHY_SGMII_FLAG;
4463                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4464                 bnx2x_warpcore_clear_regs(phy, params, lane);
4465                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4466         } else {
4467                 switch (serdes_net_if) {
4468                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4469                         /* Enable KR Auto Neg */
4470                         if (params->loopback_mode != LOOPBACK_EXT)
4471                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4472                         else {
4473                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4474                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4475                         }
4476                         break;
4477
4478                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4479                         bnx2x_warpcore_clear_regs(phy, params, lane);
4480                         if (vars->line_speed == SPEED_10000) {
4481                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4482                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4483                         } else {
4484                                 if (SINGLE_MEDIA_DIRECT(params)) {
4485                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4486                                         fiber_mode = 1;
4487                                 } else {
4488                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4489                                         fiber_mode = 0;
4490                                 }
4491                                 bnx2x_warpcore_set_sgmii_speed(phy,
4492                                                                 params,
4493                                                                 fiber_mode,
4494                                                                 0);
4495                         }
4496
4497                         break;
4498
4499                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4500                         /* Issue Module detection if module is plugged, or
4501                          * enabled transmitter to avoid current leakage in case
4502                          * no module is connected
4503                          */
4504                         if (bnx2x_is_sfp_module_plugged(phy, params))
4505                                 bnx2x_sfp_module_detection(phy, params);
4506                         else
4507                                 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
4508
4509                         bnx2x_warpcore_config_sfi(phy, params);
4510                         break;
4511
4512                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4513                         if (vars->line_speed != SPEED_20000) {
4514                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4515                                 return;
4516                         }
4517                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4518                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4519                         /* Issue Module detection */
4520
4521                         bnx2x_sfp_module_detection(phy, params);
4522                         break;
4523                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4524                         if (!params->loopback_mode) {
4525                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4526                         } else {
4527                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4528                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4529                         }
4530                         break;
4531                 default:
4532                         DP(NETIF_MSG_LINK,
4533                            "Unsupported Serdes Net Interface 0x%x\n",
4534                            serdes_net_if);
4535                         return;
4536                 }
4537         }
4538
4539         /* Take lane out of reset after configuration is finished */
4540         bnx2x_warpcore_reset_lane(bp, phy, 0);
4541         DP(NETIF_MSG_LINK, "Exit config init\n");
4542 }
4543
4544 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4545                                       struct link_params *params)
4546 {
4547         struct bnx2x *bp = params->bp;
4548         u16 val16, lane;
4549         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4550         bnx2x_set_mdio_emac_per_phy(bp, params);
4551         bnx2x_set_aer_mmd(params, phy);
4552         /* Global register */
4553         bnx2x_warpcore_reset_lane(bp, phy, 1);
4554
4555         /* Clear loopback settings (if any) */
4556         /* 10G & 20G */
4557         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4558                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4559
4560         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4561                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4562
4563         /* Update those 1-copy registers */
4564         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4565                           MDIO_AER_BLOCK_AER_REG, 0);
4566         /* Enable 1G MDIO (1-copy) */
4567         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4568                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4569                                   ~0x10);
4570
4571         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4572                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4573         lane = bnx2x_get_warpcore_lane(phy, params);
4574         /* Disable CL36 PCS Tx */
4575         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4576                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4577         val16 |= (0x11 << lane);
4578         if (phy->flags & FLAGS_WC_DUAL_MODE)
4579                 val16 |= (0x22 << lane);
4580         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4581                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4582
4583         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4584                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4585         val16 &= ~(0x0303 << (lane << 1));
4586         val16 |= (0x0101 << (lane << 1));
4587         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4588                 val16 &= ~(0x0c0c << (lane << 1));
4589                 val16 |= (0x0404 << (lane << 1));
4590         }
4591
4592         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4593                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4594         /* Restore AER */
4595         bnx2x_set_aer_mmd(params, phy);
4596
4597 }
4598
4599 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4600                                         struct link_params *params)
4601 {
4602         struct bnx2x *bp = params->bp;
4603         u16 val16;
4604         u32 lane;
4605         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4606                        params->loopback_mode, phy->req_line_speed);
4607
4608         if (phy->req_line_speed < SPEED_10000 ||
4609             phy->supported & SUPPORTED_20000baseKR2_Full) {
4610                 /* 10/100/1000/20G-KR2 */
4611
4612                 /* Update those 1-copy registers */
4613                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4614                                   MDIO_AER_BLOCK_AER_REG, 0);
4615                 /* Enable 1G MDIO (1-copy) */
4616                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4617                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4618                                          0x10);
4619                 /* Set 1G loopback based on lane (1-copy) */
4620                 lane = bnx2x_get_warpcore_lane(phy, params);
4621                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4622                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4623                 val16 |= (1<<lane);
4624                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4625                         val16 |= (2<<lane);
4626                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4627                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4628                                  val16);
4629
4630                 /* Switch back to 4-copy registers */
4631                 bnx2x_set_aer_mmd(params, phy);
4632         } else {
4633                 /* 10G / 20G-DXGXS */
4634                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4635                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4636                                          0x4000);
4637                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4638                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4639         }
4640 }
4641
4642
4643
4644 static void bnx2x_sync_link(struct link_params *params,
4645                              struct link_vars *vars)
4646 {
4647         struct bnx2x *bp = params->bp;
4648         u8 link_10g_plus;
4649         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4650                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4651         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4652         if (vars->link_up) {
4653                 DP(NETIF_MSG_LINK, "phy link up\n");
4654
4655                 vars->phy_link_up = 1;
4656                 vars->duplex = DUPLEX_FULL;
4657                 switch (vars->link_status &
4658                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4659                 case LINK_10THD:
4660                         vars->duplex = DUPLEX_HALF;
4661                         /* Fall thru */
4662                 case LINK_10TFD:
4663                         vars->line_speed = SPEED_10;
4664                         break;
4665
4666                 case LINK_100TXHD:
4667                         vars->duplex = DUPLEX_HALF;
4668                         /* Fall thru */
4669                 case LINK_100T4:
4670                 case LINK_100TXFD:
4671                         vars->line_speed = SPEED_100;
4672                         break;
4673
4674                 case LINK_1000THD:
4675                         vars->duplex = DUPLEX_HALF;
4676                         /* Fall thru */
4677                 case LINK_1000TFD:
4678                         vars->line_speed = SPEED_1000;
4679                         break;
4680
4681                 case LINK_2500THD:
4682                         vars->duplex = DUPLEX_HALF;
4683                         /* Fall thru */
4684                 case LINK_2500TFD:
4685                         vars->line_speed = SPEED_2500;
4686                         break;
4687
4688                 case LINK_10GTFD:
4689                         vars->line_speed = SPEED_10000;
4690                         break;
4691                 case LINK_20GTFD:
4692                         vars->line_speed = SPEED_20000;
4693                         break;
4694                 default:
4695                         break;
4696                 }
4697                 vars->flow_ctrl = 0;
4698                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4699                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4700
4701                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4702                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4703
4704                 if (!vars->flow_ctrl)
4705                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4706
4707                 if (vars->line_speed &&
4708                     ((vars->line_speed == SPEED_10) ||
4709                      (vars->line_speed == SPEED_100))) {
4710                         vars->phy_flags |= PHY_SGMII_FLAG;
4711                 } else {
4712                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4713                 }
4714                 if (vars->line_speed &&
4715                     USES_WARPCORE(bp) &&
4716                     (vars->line_speed == SPEED_1000))
4717                         vars->phy_flags |= PHY_SGMII_FLAG;
4718                 /* Anything 10 and over uses the bmac */
4719                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4720
4721                 if (link_10g_plus) {
4722                         if (USES_WARPCORE(bp))
4723                                 vars->mac_type = MAC_TYPE_XMAC;
4724                         else
4725                                 vars->mac_type = MAC_TYPE_BMAC;
4726                 } else {
4727                         if (USES_WARPCORE(bp))
4728                                 vars->mac_type = MAC_TYPE_UMAC;
4729                         else
4730                                 vars->mac_type = MAC_TYPE_EMAC;
4731                 }
4732         } else { /* Link down */
4733                 DP(NETIF_MSG_LINK, "phy link down\n");
4734
4735                 vars->phy_link_up = 0;
4736
4737                 vars->line_speed = 0;
4738                 vars->duplex = DUPLEX_FULL;
4739                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4740
4741                 /* Indicate no mac active */
4742                 vars->mac_type = MAC_TYPE_NONE;
4743                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4744                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4745                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4746                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4747         }
4748 }
4749
4750 void bnx2x_link_status_update(struct link_params *params,
4751                               struct link_vars *vars)
4752 {
4753         struct bnx2x *bp = params->bp;
4754         u8 port = params->port;
4755         u32 sync_offset, media_types;
4756         /* Update PHY configuration */
4757         set_phy_vars(params, vars);
4758
4759         vars->link_status = REG_RD(bp, params->shmem_base +
4760                                    offsetof(struct shmem_region,
4761                                             port_mb[port].link_status));
4762
4763         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4764         if (bp->link_params.loopback_mode != LOOPBACK_NONE &&
4765             bp->link_params.loopback_mode != LOOPBACK_EXT)
4766                 vars->link_status |= LINK_STATUS_LINK_UP;
4767
4768         if (bnx2x_eee_has_cap(params))
4769                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4770                                           offsetof(struct shmem2_region,
4771                                                    eee_status[params->port]));
4772
4773         vars->phy_flags = PHY_XGXS_FLAG;
4774         bnx2x_sync_link(params, vars);
4775         /* Sync media type */
4776         sync_offset = params->shmem_base +
4777                         offsetof(struct shmem_region,
4778                                  dev_info.port_hw_config[port].media_type);
4779         media_types = REG_RD(bp, sync_offset);
4780
4781         params->phy[INT_PHY].media_type =
4782                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4783                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4784         params->phy[EXT_PHY1].media_type =
4785                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4786                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4787         params->phy[EXT_PHY2].media_type =
4788                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4789                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4790         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4791
4792         /* Sync AEU offset */
4793         sync_offset = params->shmem_base +
4794                         offsetof(struct shmem_region,
4795                                  dev_info.port_hw_config[port].aeu_int_mask);
4796
4797         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4798
4799         /* Sync PFC status */
4800         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4801                 params->feature_config_flags |=
4802                                         FEATURE_CONFIG_PFC_ENABLED;
4803         else
4804                 params->feature_config_flags &=
4805                                         ~FEATURE_CONFIG_PFC_ENABLED;
4806
4807         if (SHMEM2_HAS(bp, link_attr_sync))
4808                 vars->link_attr_sync = SHMEM2_RD(bp,
4809                                                  link_attr_sync[params->port]);
4810
4811         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4812                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4813         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4814                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4815 }
4816
4817 static void bnx2x_set_master_ln(struct link_params *params,
4818                                 struct bnx2x_phy *phy)
4819 {
4820         struct bnx2x *bp = params->bp;
4821         u16 new_master_ln, ser_lane;
4822         ser_lane = ((params->lane_config &
4823                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4824                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4825
4826         /* Set the master_ln for AN */
4827         CL22_RD_OVER_CL45(bp, phy,
4828                           MDIO_REG_BANK_XGXS_BLOCK2,
4829                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4830                           &new_master_ln);
4831
4832         CL22_WR_OVER_CL45(bp, phy,
4833                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4834                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4835                           (new_master_ln | ser_lane));
4836 }
4837
4838 static int bnx2x_reset_unicore(struct link_params *params,
4839                                struct bnx2x_phy *phy,
4840                                u8 set_serdes)
4841 {
4842         struct bnx2x *bp = params->bp;
4843         u16 mii_control;
4844         u16 i;
4845         CL22_RD_OVER_CL45(bp, phy,
4846                           MDIO_REG_BANK_COMBO_IEEE0,
4847                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4848
4849         /* Reset the unicore */
4850         CL22_WR_OVER_CL45(bp, phy,
4851                           MDIO_REG_BANK_COMBO_IEEE0,
4852                           MDIO_COMBO_IEEE0_MII_CONTROL,
4853                           (mii_control |
4854                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4855         if (set_serdes)
4856                 bnx2x_set_serdes_access(bp, params->port);
4857
4858         /* Wait for the reset to self clear */
4859         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4860                 udelay(5);
4861
4862                 /* The reset erased the previous bank value */
4863                 CL22_RD_OVER_CL45(bp, phy,
4864                                   MDIO_REG_BANK_COMBO_IEEE0,
4865                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4866                                   &mii_control);
4867
4868                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4869                         udelay(5);
4870                         return 0;
4871                 }
4872         }
4873
4874         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4875                               " Port %d\n",
4876                          params->port);
4877         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4878         return -EINVAL;
4879
4880 }
4881
4882 static void bnx2x_set_swap_lanes(struct link_params *params,
4883                                  struct bnx2x_phy *phy)
4884 {
4885         struct bnx2x *bp = params->bp;
4886         /* Each two bits represents a lane number:
4887          * No swap is 0123 => 0x1b no need to enable the swap
4888          */
4889         u16 rx_lane_swap, tx_lane_swap;
4890
4891         rx_lane_swap = ((params->lane_config &
4892                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4893                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4894         tx_lane_swap = ((params->lane_config &
4895                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4896                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4897
4898         if (rx_lane_swap != 0x1b) {
4899                 CL22_WR_OVER_CL45(bp, phy,
4900                                   MDIO_REG_BANK_XGXS_BLOCK2,
4901                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4902                                   (rx_lane_swap |
4903                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4904                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4905         } else {
4906                 CL22_WR_OVER_CL45(bp, phy,
4907                                   MDIO_REG_BANK_XGXS_BLOCK2,
4908                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4909         }
4910
4911         if (tx_lane_swap != 0x1b) {
4912                 CL22_WR_OVER_CL45(bp, phy,
4913                                   MDIO_REG_BANK_XGXS_BLOCK2,
4914                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4915                                   (tx_lane_swap |
4916                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4917         } else {
4918                 CL22_WR_OVER_CL45(bp, phy,
4919                                   MDIO_REG_BANK_XGXS_BLOCK2,
4920                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4921         }
4922 }
4923
4924 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4925                                          struct link_params *params)
4926 {
4927         struct bnx2x *bp = params->bp;
4928         u16 control2;
4929         CL22_RD_OVER_CL45(bp, phy,
4930                           MDIO_REG_BANK_SERDES_DIGITAL,
4931                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4932                           &control2);
4933         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4934                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4935         else
4936                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4937         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4938                 phy->speed_cap_mask, control2);
4939         CL22_WR_OVER_CL45(bp, phy,
4940                           MDIO_REG_BANK_SERDES_DIGITAL,
4941                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4942                           control2);
4943
4944         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4945              (phy->speed_cap_mask &
4946                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4947                 DP(NETIF_MSG_LINK, "XGXS\n");
4948
4949                 CL22_WR_OVER_CL45(bp, phy,
4950                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4951                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4952                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4953
4954                 CL22_RD_OVER_CL45(bp, phy,
4955                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4956                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4957                                   &control2);
4958
4959
4960                 control2 |=
4961                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4962
4963                 CL22_WR_OVER_CL45(bp, phy,
4964                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4965                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4966                                   control2);
4967
4968                 /* Disable parallel detection of HiG */
4969                 CL22_WR_OVER_CL45(bp, phy,
4970                                   MDIO_REG_BANK_XGXS_BLOCK2,
4971                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4972                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4973                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4974         }
4975 }
4976
4977 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4978                               struct link_params *params,
4979                               struct link_vars *vars,
4980                               u8 enable_cl73)
4981 {
4982         struct bnx2x *bp = params->bp;
4983         u16 reg_val;
4984
4985         /* CL37 Autoneg */
4986         CL22_RD_OVER_CL45(bp, phy,
4987                           MDIO_REG_BANK_COMBO_IEEE0,
4988                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4989
4990         /* CL37 Autoneg Enabled */
4991         if (vars->line_speed == SPEED_AUTO_NEG)
4992                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4993         else /* CL37 Autoneg Disabled */
4994                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4995                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4996
4997         CL22_WR_OVER_CL45(bp, phy,
4998                           MDIO_REG_BANK_COMBO_IEEE0,
4999                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5000
5001         /* Enable/Disable Autodetection */
5002
5003         CL22_RD_OVER_CL45(bp, phy,
5004                           MDIO_REG_BANK_SERDES_DIGITAL,
5005                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5006         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5007                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5008         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5009         if (vars->line_speed == SPEED_AUTO_NEG)
5010                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5011         else
5012                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5013
5014         CL22_WR_OVER_CL45(bp, phy,
5015                           MDIO_REG_BANK_SERDES_DIGITAL,
5016                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5017
5018         /* Enable TetonII and BAM autoneg */
5019         CL22_RD_OVER_CL45(bp, phy,
5020                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5021                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5022                           &reg_val);
5023         if (vars->line_speed == SPEED_AUTO_NEG) {
5024                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5025                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5026                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5027         } else {
5028                 /* TetonII and BAM Autoneg Disabled */
5029                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5030                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5031         }
5032         CL22_WR_OVER_CL45(bp, phy,
5033                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5034                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5035                           reg_val);
5036
5037         if (enable_cl73) {
5038                 /* Enable Cl73 FSM status bits */
5039                 CL22_WR_OVER_CL45(bp, phy,
5040                                   MDIO_REG_BANK_CL73_USERB0,
5041                                   MDIO_CL73_USERB0_CL73_UCTRL,
5042                                   0xe);
5043
5044                 /* Enable BAM Station Manager*/
5045                 CL22_WR_OVER_CL45(bp, phy,
5046                         MDIO_REG_BANK_CL73_USERB0,
5047                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5048                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5049                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5050                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5051
5052                 /* Advertise CL73 link speeds */
5053                 CL22_RD_OVER_CL45(bp, phy,
5054                                   MDIO_REG_BANK_CL73_IEEEB1,
5055                                   MDIO_CL73_IEEEB1_AN_ADV2,
5056                                   &reg_val);
5057                 if (phy->speed_cap_mask &
5058                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5059                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5060                 if (phy->speed_cap_mask &
5061                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5062                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5063
5064                 CL22_WR_OVER_CL45(bp, phy,
5065                                   MDIO_REG_BANK_CL73_IEEEB1,
5066                                   MDIO_CL73_IEEEB1_AN_ADV2,
5067                                   reg_val);
5068
5069                 /* CL73 Autoneg Enabled */
5070                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5071
5072         } else /* CL73 Autoneg Disabled */
5073                 reg_val = 0;
5074
5075         CL22_WR_OVER_CL45(bp, phy,
5076                           MDIO_REG_BANK_CL73_IEEEB0,
5077                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5078 }
5079
5080 /* Program SerDes, forced speed */
5081 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5082                                  struct link_params *params,
5083                                  struct link_vars *vars)
5084 {
5085         struct bnx2x *bp = params->bp;
5086         u16 reg_val;
5087
5088         /* Program duplex, disable autoneg and sgmii*/
5089         CL22_RD_OVER_CL45(bp, phy,
5090                           MDIO_REG_BANK_COMBO_IEEE0,
5091                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5092         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5093                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5094                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5095         if (phy->req_duplex == DUPLEX_FULL)
5096                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5097         CL22_WR_OVER_CL45(bp, phy,
5098                           MDIO_REG_BANK_COMBO_IEEE0,
5099                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5100
5101         /* Program speed
5102          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5103          */
5104         CL22_RD_OVER_CL45(bp, phy,
5105                           MDIO_REG_BANK_SERDES_DIGITAL,
5106                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5107         /* Clearing the speed value before setting the right speed */
5108         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5109
5110         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5111                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5112
5113         if (!((vars->line_speed == SPEED_1000) ||
5114               (vars->line_speed == SPEED_100) ||
5115               (vars->line_speed == SPEED_10))) {
5116
5117                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5118                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5119                 if (vars->line_speed == SPEED_10000)
5120                         reg_val |=
5121                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5122         }
5123
5124         CL22_WR_OVER_CL45(bp, phy,
5125                           MDIO_REG_BANK_SERDES_DIGITAL,
5126                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5127
5128 }
5129
5130 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5131                                               struct link_params *params)
5132 {
5133         struct bnx2x *bp = params->bp;
5134         u16 val = 0;
5135
5136         /* Set extended capabilities */
5137         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5138                 val |= MDIO_OVER_1G_UP1_2_5G;
5139         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5140                 val |= MDIO_OVER_1G_UP1_10G;
5141         CL22_WR_OVER_CL45(bp, phy,
5142                           MDIO_REG_BANK_OVER_1G,
5143                           MDIO_OVER_1G_UP1, val);
5144
5145         CL22_WR_OVER_CL45(bp, phy,
5146                           MDIO_REG_BANK_OVER_1G,
5147                           MDIO_OVER_1G_UP3, 0x400);
5148 }
5149
5150 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5151                                               struct link_params *params,
5152                                               u16 ieee_fc)
5153 {
5154         struct bnx2x *bp = params->bp;
5155         u16 val;
5156         /* For AN, we are always publishing full duplex */
5157
5158         CL22_WR_OVER_CL45(bp, phy,
5159                           MDIO_REG_BANK_COMBO_IEEE0,
5160                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5161         CL22_RD_OVER_CL45(bp, phy,
5162                           MDIO_REG_BANK_CL73_IEEEB1,
5163                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5164         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5165         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5166         CL22_WR_OVER_CL45(bp, phy,
5167                           MDIO_REG_BANK_CL73_IEEEB1,
5168                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5169 }
5170
5171 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5172                                   struct link_params *params,
5173                                   u8 enable_cl73)
5174 {
5175         struct bnx2x *bp = params->bp;
5176         u16 mii_control;
5177
5178         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5179         /* Enable and restart BAM/CL37 aneg */
5180
5181         if (enable_cl73) {
5182                 CL22_RD_OVER_CL45(bp, phy,
5183                                   MDIO_REG_BANK_CL73_IEEEB0,
5184                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5185                                   &mii_control);
5186
5187                 CL22_WR_OVER_CL45(bp, phy,
5188                                   MDIO_REG_BANK_CL73_IEEEB0,
5189                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5190                                   (mii_control |
5191                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5192                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5193         } else {
5194
5195                 CL22_RD_OVER_CL45(bp, phy,
5196                                   MDIO_REG_BANK_COMBO_IEEE0,
5197                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5198                                   &mii_control);
5199                 DP(NETIF_MSG_LINK,
5200                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5201                          mii_control);
5202                 CL22_WR_OVER_CL45(bp, phy,
5203                                   MDIO_REG_BANK_COMBO_IEEE0,
5204                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5205                                   (mii_control |
5206                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5207                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5208         }
5209 }
5210
5211 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5212                                            struct link_params *params,
5213                                            struct link_vars *vars)
5214 {
5215         struct bnx2x *bp = params->bp;
5216         u16 control1;
5217
5218         /* In SGMII mode, the unicore is always slave */
5219
5220         CL22_RD_OVER_CL45(bp, phy,
5221                           MDIO_REG_BANK_SERDES_DIGITAL,
5222                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5223                           &control1);
5224         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5225         /* Set sgmii mode (and not fiber) */
5226         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5227                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5228                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5229         CL22_WR_OVER_CL45(bp, phy,
5230                           MDIO_REG_BANK_SERDES_DIGITAL,
5231                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5232                           control1);
5233
5234         /* If forced speed */
5235         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5236                 /* Set speed, disable autoneg */
5237                 u16 mii_control;
5238
5239                 CL22_RD_OVER_CL45(bp, phy,
5240                                   MDIO_REG_BANK_COMBO_IEEE0,
5241                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5242                                   &mii_control);
5243                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5244                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5245                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5246
5247                 switch (vars->line_speed) {
5248                 case SPEED_100:
5249                         mii_control |=
5250                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5251                         break;
5252                 case SPEED_1000:
5253                         mii_control |=
5254                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5255                         break;
5256                 case SPEED_10:
5257                         /* There is nothing to set for 10M */
5258                         break;
5259                 default:
5260                         /* Invalid speed for SGMII */
5261                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5262                                   vars->line_speed);
5263                         break;
5264                 }
5265
5266                 /* Setting the full duplex */
5267                 if (phy->req_duplex == DUPLEX_FULL)
5268                         mii_control |=
5269                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5270                 CL22_WR_OVER_CL45(bp, phy,
5271                                   MDIO_REG_BANK_COMBO_IEEE0,
5272                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5273                                   mii_control);
5274
5275         } else { /* AN mode */
5276                 /* Enable and restart AN */
5277                 bnx2x_restart_autoneg(phy, params, 0);
5278         }
5279 }
5280
5281 /* Link management
5282  */
5283 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5284                                              struct link_params *params)
5285 {
5286         struct bnx2x *bp = params->bp;
5287         u16 pd_10g, status2_1000x;
5288         if (phy->req_line_speed != SPEED_AUTO_NEG)
5289                 return 0;
5290         CL22_RD_OVER_CL45(bp, phy,
5291                           MDIO_REG_BANK_SERDES_DIGITAL,
5292                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5293                           &status2_1000x);
5294         CL22_RD_OVER_CL45(bp, phy,
5295                           MDIO_REG_BANK_SERDES_DIGITAL,
5296                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5297                           &status2_1000x);
5298         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5299                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5300                          params->port);
5301                 return 1;
5302         }
5303
5304         CL22_RD_OVER_CL45(bp, phy,
5305                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5306                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5307                           &pd_10g);
5308
5309         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5310                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5311                          params->port);
5312                 return 1;
5313         }
5314         return 0;
5315 }
5316
5317 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5318                                 struct link_params *params,
5319                                 struct link_vars *vars,
5320                                 u32 gp_status)
5321 {
5322         u16 ld_pause;   /* local driver */
5323         u16 lp_pause;   /* link partner */
5324         u16 pause_result;
5325         struct bnx2x *bp = params->bp;
5326         if ((gp_status &
5327              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5328               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5329             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5330              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5331
5332                 CL22_RD_OVER_CL45(bp, phy,
5333                                   MDIO_REG_BANK_CL73_IEEEB1,
5334                                   MDIO_CL73_IEEEB1_AN_ADV1,
5335                                   &ld_pause);
5336                 CL22_RD_OVER_CL45(bp, phy,
5337                                   MDIO_REG_BANK_CL73_IEEEB1,
5338                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5339                                   &lp_pause);
5340                 pause_result = (ld_pause &
5341                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5342                 pause_result |= (lp_pause &
5343                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5344                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5345         } else {
5346                 CL22_RD_OVER_CL45(bp, phy,
5347                                   MDIO_REG_BANK_COMBO_IEEE0,
5348                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5349                                   &ld_pause);
5350                 CL22_RD_OVER_CL45(bp, phy,
5351                         MDIO_REG_BANK_COMBO_IEEE0,
5352                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5353                         &lp_pause);
5354                 pause_result = (ld_pause &
5355                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5356                 pause_result |= (lp_pause &
5357                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5358                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5359         }
5360         bnx2x_pause_resolve(vars, pause_result);
5361
5362 }
5363
5364 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5365                                     struct link_params *params,
5366                                     struct link_vars *vars,
5367                                     u32 gp_status)
5368 {
5369         struct bnx2x *bp = params->bp;
5370         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5371
5372         /* Resolve from gp_status in case of AN complete and not sgmii */
5373         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5374                 /* Update the advertised flow-controled of LD/LP in AN */
5375                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5376                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5377                 /* But set the flow-control result as the requested one */
5378                 vars->flow_ctrl = phy->req_flow_ctrl;
5379         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5380                 vars->flow_ctrl = params->req_fc_auto_adv;
5381         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5382                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5383                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5384                         vars->flow_ctrl = params->req_fc_auto_adv;
5385                         return;
5386                 }
5387                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5388         }
5389         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5390 }
5391
5392 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5393                                          struct link_params *params)
5394 {
5395         struct bnx2x *bp = params->bp;
5396         u16 rx_status, ustat_val, cl37_fsm_received;
5397         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5398         /* Step 1: Make sure signal is detected */
5399         CL22_RD_OVER_CL45(bp, phy,
5400                           MDIO_REG_BANK_RX0,
5401                           MDIO_RX0_RX_STATUS,
5402                           &rx_status);
5403         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5404             (MDIO_RX0_RX_STATUS_SIGDET)) {
5405                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5406                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5407                 CL22_WR_OVER_CL45(bp, phy,
5408                                   MDIO_REG_BANK_CL73_IEEEB0,
5409                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5410                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5411                 return;
5412         }
5413         /* Step 2: Check CL73 state machine */
5414         CL22_RD_OVER_CL45(bp, phy,
5415                           MDIO_REG_BANK_CL73_USERB0,
5416                           MDIO_CL73_USERB0_CL73_USTAT1,
5417                           &ustat_val);
5418         if ((ustat_val &
5419              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5420               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5421             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5422               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5423                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5424                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5425                 return;
5426         }
5427         /* Step 3: Check CL37 Message Pages received to indicate LP
5428          * supports only CL37
5429          */
5430         CL22_RD_OVER_CL45(bp, phy,
5431                           MDIO_REG_BANK_REMOTE_PHY,
5432                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5433                           &cl37_fsm_received);
5434         if ((cl37_fsm_received &
5435              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5436              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5437             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5438               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5439                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5440                              "misc_rx_status(0x8330) = 0x%x\n",
5441                          cl37_fsm_received);
5442                 return;
5443         }
5444         /* The combined cl37/cl73 fsm state information indicating that
5445          * we are connected to a device which does not support cl73, but
5446          * does support cl37 BAM. In this case we disable cl73 and
5447          * restart cl37 auto-neg
5448          */
5449
5450         /* Disable CL73 */
5451         CL22_WR_OVER_CL45(bp, phy,
5452                           MDIO_REG_BANK_CL73_IEEEB0,
5453                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5454                           0);
5455         /* Restart CL37 autoneg */
5456         bnx2x_restart_autoneg(phy, params, 0);
5457         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5458 }
5459
5460 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5461                                   struct link_params *params,
5462                                   struct link_vars *vars,
5463                                   u32 gp_status)
5464 {
5465         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5466                 vars->link_status |=
5467                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5468
5469         if (bnx2x_direct_parallel_detect_used(phy, params))
5470                 vars->link_status |=
5471                         LINK_STATUS_PARALLEL_DETECTION_USED;
5472 }
5473 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5474                                      struct link_params *params,
5475                                       struct link_vars *vars,
5476                                       u16 is_link_up,
5477                                       u16 speed_mask,
5478                                       u16 is_duplex)
5479 {
5480         struct bnx2x *bp = params->bp;
5481         if (phy->req_line_speed == SPEED_AUTO_NEG)
5482                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5483         if (is_link_up) {
5484                 DP(NETIF_MSG_LINK, "phy link up\n");
5485
5486                 vars->phy_link_up = 1;
5487                 vars->link_status |= LINK_STATUS_LINK_UP;
5488
5489                 switch (speed_mask) {
5490                 case GP_STATUS_10M:
5491                         vars->line_speed = SPEED_10;
5492                         if (is_duplex == DUPLEX_FULL)
5493                                 vars->link_status |= LINK_10TFD;
5494                         else
5495                                 vars->link_status |= LINK_10THD;
5496                         break;
5497
5498                 case GP_STATUS_100M:
5499                         vars->line_speed = SPEED_100;
5500                         if (is_duplex == DUPLEX_FULL)
5501                                 vars->link_status |= LINK_100TXFD;
5502                         else
5503                                 vars->link_status |= LINK_100TXHD;
5504                         break;
5505
5506                 case GP_STATUS_1G:
5507                 case GP_STATUS_1G_KX:
5508                         vars->line_speed = SPEED_1000;
5509                         if (is_duplex == DUPLEX_FULL)
5510                                 vars->link_status |= LINK_1000TFD;
5511                         else
5512                                 vars->link_status |= LINK_1000THD;
5513                         break;
5514
5515                 case GP_STATUS_2_5G:
5516                         vars->line_speed = SPEED_2500;
5517                         if (is_duplex == DUPLEX_FULL)
5518                                 vars->link_status |= LINK_2500TFD;
5519                         else
5520                                 vars->link_status |= LINK_2500THD;
5521                         break;
5522
5523                 case GP_STATUS_5G:
5524                 case GP_STATUS_6G:
5525                         DP(NETIF_MSG_LINK,
5526                                  "link speed unsupported  gp_status 0x%x\n",
5527                                   speed_mask);
5528                         return -EINVAL;
5529
5530                 case GP_STATUS_10G_KX4:
5531                 case GP_STATUS_10G_HIG:
5532                 case GP_STATUS_10G_CX4:
5533                 case GP_STATUS_10G_KR:
5534                 case GP_STATUS_10G_SFI:
5535                 case GP_STATUS_10G_XFI:
5536                         vars->line_speed = SPEED_10000;
5537                         vars->link_status |= LINK_10GTFD;
5538                         break;
5539                 case GP_STATUS_20G_DXGXS:
5540                 case GP_STATUS_20G_KR2:
5541                         vars->line_speed = SPEED_20000;
5542                         vars->link_status |= LINK_20GTFD;
5543                         break;
5544                 default:
5545                         DP(NETIF_MSG_LINK,
5546                                   "link speed unsupported gp_status 0x%x\n",
5547                                   speed_mask);
5548                         return -EINVAL;
5549                 }
5550         } else { /* link_down */
5551                 DP(NETIF_MSG_LINK, "phy link down\n");
5552
5553                 vars->phy_link_up = 0;
5554
5555                 vars->duplex = DUPLEX_FULL;
5556                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5557                 vars->mac_type = MAC_TYPE_NONE;
5558         }
5559         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5560                     vars->phy_link_up, vars->line_speed);
5561         return 0;
5562 }
5563
5564 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5565                                       struct link_params *params,
5566                                       struct link_vars *vars)
5567 {
5568         struct bnx2x *bp = params->bp;
5569
5570         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5571         int rc = 0;
5572
5573         /* Read gp_status */
5574         CL22_RD_OVER_CL45(bp, phy,
5575                           MDIO_REG_BANK_GP_STATUS,
5576                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5577                           &gp_status);
5578         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5579                 duplex = DUPLEX_FULL;
5580         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5581                 link_up = 1;
5582         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5583         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5584                        gp_status, link_up, speed_mask);
5585         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5586                                          duplex);
5587         if (rc == -EINVAL)
5588                 return rc;
5589
5590         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5591                 if (SINGLE_MEDIA_DIRECT(params)) {
5592                         vars->duplex = duplex;
5593                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5594                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5595                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5596                                                       gp_status);
5597                 }
5598         } else { /* Link_down */
5599                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5600                     SINGLE_MEDIA_DIRECT(params)) {
5601                         /* Check signal is detected */
5602                         bnx2x_check_fallback_to_cl37(phy, params);
5603                 }
5604         }
5605
5606         /* Read LP advertised speeds*/
5607         if (SINGLE_MEDIA_DIRECT(params) &&
5608             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5609                 u16 val;
5610
5611                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5612                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5613
5614                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5615                         vars->link_status |=
5616                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5617                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5618                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5619                         vars->link_status |=
5620                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5621
5622                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5623                                   MDIO_OVER_1G_LP_UP1, &val);
5624
5625                 if (val & MDIO_OVER_1G_UP1_2_5G)
5626                         vars->link_status |=
5627                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5628                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5629                         vars->link_status |=
5630                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5631         }
5632
5633         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5634                    vars->duplex, vars->flow_ctrl, vars->link_status);
5635         return rc;
5636 }
5637
5638 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5639                                      struct link_params *params,
5640                                      struct link_vars *vars)
5641 {
5642         struct bnx2x *bp = params->bp;
5643         u8 lane;
5644         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5645         int rc = 0;
5646         lane = bnx2x_get_warpcore_lane(phy, params);
5647         /* Read gp_status */
5648         if ((params->loopback_mode) &&
5649             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5650                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5651                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5652                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5653                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5654                 link_up &= 0x1;
5655         } else if ((phy->req_line_speed > SPEED_10000) &&
5656                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5657                 u16 temp_link_up;
5658                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5659                                 1, &temp_link_up);
5660                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5661                                 1, &link_up);
5662                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5663                                temp_link_up, link_up);
5664                 link_up &= (1<<2);
5665                 if (link_up)
5666                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5667         } else {
5668                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5669                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5670                                 &gp_status1);
5671                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5672                 /* Check for either KR, 1G, or AN up. */
5673                 link_up = ((gp_status1 >> 8) |
5674                            (gp_status1 >> 12) |
5675                            (gp_status1)) &
5676                         (1 << lane);
5677                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5678                         u16 an_link;
5679                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5680                                         MDIO_AN_REG_STATUS, &an_link);
5681                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5682                                         MDIO_AN_REG_STATUS, &an_link);
5683                         link_up |= (an_link & (1<<2));
5684                 }
5685                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5686                         u16 pd, gp_status4;
5687                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5688                                 /* Check Autoneg complete */
5689                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5690                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5691                                                 &gp_status4);
5692                                 if (gp_status4 & ((1<<12)<<lane))
5693                                         vars->link_status |=
5694                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5695
5696                                 /* Check parallel detect used */
5697                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5698                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5699                                                 &pd);
5700                                 if (pd & (1<<15))
5701                                         vars->link_status |=
5702                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5703                         }
5704                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5705                         vars->duplex = duplex;
5706                 }
5707         }
5708
5709         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5710             SINGLE_MEDIA_DIRECT(params)) {
5711                 u16 val;
5712
5713                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5714                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5715
5716                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5717                         vars->link_status |=
5718                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5719                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5720                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5721                         vars->link_status |=
5722                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5723
5724                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5725                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5726
5727                 if (val & MDIO_OVER_1G_UP1_2_5G)
5728                         vars->link_status |=
5729                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5730                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5731                         vars->link_status |=
5732                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5733
5734         }
5735
5736
5737         if (lane < 2) {
5738                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5739                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5740         } else {
5741                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5742                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5743         }
5744         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5745
5746         if ((lane & 1) == 0)
5747                 gp_speed <<= 8;
5748         gp_speed &= 0x3f00;
5749         link_up = !!link_up;
5750
5751         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5752                                          duplex);
5753
5754         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5755                    vars->duplex, vars->flow_ctrl, vars->link_status);
5756         return rc;
5757 }
5758 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5759 {
5760         struct bnx2x *bp = params->bp;
5761         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5762         u16 lp_up2;
5763         u16 tx_driver;
5764         u16 bank;
5765
5766         /* Read precomp */
5767         CL22_RD_OVER_CL45(bp, phy,
5768                           MDIO_REG_BANK_OVER_1G,
5769                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5770
5771         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5772         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5773                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5774                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5775
5776         if (lp_up2 == 0)
5777                 return;
5778
5779         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5780               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5781                 CL22_RD_OVER_CL45(bp, phy,
5782                                   bank,
5783                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5784
5785                 /* Replace tx_driver bits [15:12] */
5786                 if (lp_up2 !=
5787                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5788                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5789                         tx_driver |= lp_up2;
5790                         CL22_WR_OVER_CL45(bp, phy,
5791                                           bank,
5792                                           MDIO_TX0_TX_DRIVER, tx_driver);
5793                 }
5794         }
5795 }
5796
5797 static int bnx2x_emac_program(struct link_params *params,
5798                               struct link_vars *vars)
5799 {
5800         struct bnx2x *bp = params->bp;
5801         u8 port = params->port;
5802         u16 mode = 0;
5803
5804         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5805         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5806                        EMAC_REG_EMAC_MODE,
5807                        (EMAC_MODE_25G_MODE |
5808                         EMAC_MODE_PORT_MII_10M |
5809                         EMAC_MODE_HALF_DUPLEX));
5810         switch (vars->line_speed) {
5811         case SPEED_10:
5812                 mode |= EMAC_MODE_PORT_MII_10M;
5813                 break;
5814
5815         case SPEED_100:
5816                 mode |= EMAC_MODE_PORT_MII;
5817                 break;
5818
5819         case SPEED_1000:
5820                 mode |= EMAC_MODE_PORT_GMII;
5821                 break;
5822
5823         case SPEED_2500:
5824                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5825                 break;
5826
5827         default:
5828                 /* 10G not valid for EMAC */
5829                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5830                            vars->line_speed);
5831                 return -EINVAL;
5832         }
5833
5834         if (vars->duplex == DUPLEX_HALF)
5835                 mode |= EMAC_MODE_HALF_DUPLEX;
5836         bnx2x_bits_en(bp,
5837                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5838                       mode);
5839
5840         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5841         return 0;
5842 }
5843
5844 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5845                                   struct link_params *params)
5846 {
5847
5848         u16 bank, i = 0;
5849         struct bnx2x *bp = params->bp;
5850
5851         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5852               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5853                         CL22_WR_OVER_CL45(bp, phy,
5854                                           bank,
5855                                           MDIO_RX0_RX_EQ_BOOST,
5856                                           phy->rx_preemphasis[i]);
5857         }
5858
5859         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5860                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5861                         CL22_WR_OVER_CL45(bp, phy,
5862                                           bank,
5863                                           MDIO_TX0_TX_DRIVER,
5864                                           phy->tx_preemphasis[i]);
5865         }
5866 }
5867
5868 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5869                                    struct link_params *params,
5870                                    struct link_vars *vars)
5871 {
5872         struct bnx2x *bp = params->bp;
5873         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5874                           (params->loopback_mode == LOOPBACK_XGXS));
5875         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5876                 if (SINGLE_MEDIA_DIRECT(params) &&
5877                     (params->feature_config_flags &
5878                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5879                         bnx2x_set_preemphasis(phy, params);
5880
5881                 /* Forced speed requested? */
5882                 if (vars->line_speed != SPEED_AUTO_NEG ||
5883                     (SINGLE_MEDIA_DIRECT(params) &&
5884                      params->loopback_mode == LOOPBACK_EXT)) {
5885                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5886
5887                         /* Disable autoneg */
5888                         bnx2x_set_autoneg(phy, params, vars, 0);
5889
5890                         /* Program speed and duplex */
5891                         bnx2x_program_serdes(phy, params, vars);
5892
5893                 } else { /* AN_mode */
5894                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5895
5896                         /* AN enabled */
5897                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5898
5899                         /* Program duplex & pause advertisement (for aneg) */
5900                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5901                                                           vars->ieee_fc);
5902
5903                         /* Enable autoneg */
5904                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5905
5906                         /* Enable and restart AN */
5907                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5908                 }
5909
5910         } else { /* SGMII mode */
5911                 DP(NETIF_MSG_LINK, "SGMII\n");
5912
5913                 bnx2x_initialize_sgmii_process(phy, params, vars);
5914         }
5915 }
5916
5917 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5918                           struct link_params *params,
5919                           struct link_vars *vars)
5920 {
5921         int rc;
5922         vars->phy_flags |= PHY_XGXS_FLAG;
5923         if ((phy->req_line_speed &&
5924              ((phy->req_line_speed == SPEED_100) ||
5925               (phy->req_line_speed == SPEED_10))) ||
5926             (!phy->req_line_speed &&
5927              (phy->speed_cap_mask >=
5928               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5929              (phy->speed_cap_mask <
5930               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5931             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5932                 vars->phy_flags |= PHY_SGMII_FLAG;
5933         else
5934                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5935
5936         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5937         bnx2x_set_aer_mmd(params, phy);
5938         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5939                 bnx2x_set_master_ln(params, phy);
5940
5941         rc = bnx2x_reset_unicore(params, phy, 0);
5942         /* Reset the SerDes and wait for reset bit return low */
5943         if (rc)
5944                 return rc;
5945
5946         bnx2x_set_aer_mmd(params, phy);
5947         /* Setting the masterLn_def again after the reset */
5948         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5949                 bnx2x_set_master_ln(params, phy);
5950                 bnx2x_set_swap_lanes(params, phy);
5951         }
5952
5953         return rc;
5954 }
5955
5956 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5957                                      struct bnx2x_phy *phy,
5958                                      struct link_params *params)
5959 {
5960         u16 cnt, ctrl;
5961         /* Wait for soft reset to get cleared up to 1 sec */
5962         for (cnt = 0; cnt < 1000; cnt++) {
5963                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5964                         bnx2x_cl22_read(bp, phy,
5965                                 MDIO_PMA_REG_CTRL, &ctrl);
5966                 else
5967                         bnx2x_cl45_read(bp, phy,
5968                                 MDIO_PMA_DEVAD,
5969                                 MDIO_PMA_REG_CTRL, &ctrl);
5970                 if (!(ctrl & (1<<15)))
5971                         break;
5972                 usleep_range(1000, 2000);
5973         }
5974
5975         if (cnt == 1000)
5976                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5977                                       " Port %d\n",
5978                          params->port);
5979         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5980         return cnt;
5981 }
5982
5983 static void bnx2x_link_int_enable(struct link_params *params)
5984 {
5985         u8 port = params->port;
5986         u32 mask;
5987         struct bnx2x *bp = params->bp;
5988
5989         /* Setting the status to report on link up for either XGXS or SerDes */
5990         if (CHIP_IS_E3(bp)) {
5991                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5992                 if (!(SINGLE_MEDIA_DIRECT(params)))
5993                         mask |= NIG_MASK_MI_INT;
5994         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5995                 mask = (NIG_MASK_XGXS0_LINK10G |
5996                         NIG_MASK_XGXS0_LINK_STATUS);
5997                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5998                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5999                         params->phy[INT_PHY].type !=
6000                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6001                         mask |= NIG_MASK_MI_INT;
6002                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6003                 }
6004
6005         } else { /* SerDes */
6006                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6007                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6008                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6009                         params->phy[INT_PHY].type !=
6010                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6011                         mask |= NIG_MASK_MI_INT;
6012                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6013                 }
6014         }
6015         bnx2x_bits_en(bp,
6016                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6017                       mask);
6018
6019         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6020                  (params->switch_cfg == SWITCH_CFG_10G),
6021                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6022         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6023                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6024                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6025                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6026         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6027            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6028            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6029 }
6030
6031 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6032                                      u8 exp_mi_int)
6033 {
6034         u32 latch_status = 0;
6035
6036         /* Disable the MI INT ( external phy int ) by writing 1 to the
6037          * status register. Link down indication is high-active-signal,
6038          * so in this case we need to write the status to clear the XOR
6039          */
6040         /* Read Latched signals */
6041         latch_status = REG_RD(bp,
6042                                     NIG_REG_LATCH_STATUS_0 + port*8);
6043         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6044         /* Handle only those with latched-signal=up.*/
6045         if (exp_mi_int)
6046                 bnx2x_bits_en(bp,
6047                               NIG_REG_STATUS_INTERRUPT_PORT0
6048                               + port*4,
6049                               NIG_STATUS_EMAC0_MI_INT);
6050         else
6051                 bnx2x_bits_dis(bp,
6052                                NIG_REG_STATUS_INTERRUPT_PORT0
6053                                + port*4,
6054                                NIG_STATUS_EMAC0_MI_INT);
6055
6056         if (latch_status & 1) {
6057
6058                 /* For all latched-signal=up : Re-Arm Latch signals */
6059                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6060                        (latch_status & 0xfffe) | (latch_status & 1));
6061         }
6062         /* For all latched-signal=up,Write original_signal to status */
6063 }
6064
6065 static void bnx2x_link_int_ack(struct link_params *params,
6066                                struct link_vars *vars, u8 is_10g_plus)
6067 {
6068         struct bnx2x *bp = params->bp;
6069         u8 port = params->port;
6070         u32 mask;
6071         /* First reset all status we assume only one line will be
6072          * change at a time
6073          */
6074         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6075                        (NIG_STATUS_XGXS0_LINK10G |
6076                         NIG_STATUS_XGXS0_LINK_STATUS |
6077                         NIG_STATUS_SERDES0_LINK_STATUS));
6078         if (vars->phy_link_up) {
6079                 if (USES_WARPCORE(bp))
6080                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6081                 else {
6082                         if (is_10g_plus)
6083                                 mask = NIG_STATUS_XGXS0_LINK10G;
6084                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6085                                 /* Disable the link interrupt by writing 1 to
6086                                  * the relevant lane in the status register
6087                                  */
6088                                 u32 ser_lane =
6089                                         ((params->lane_config &
6090                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6091                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6092                                 mask = ((1 << ser_lane) <<
6093                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6094                         } else
6095                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6096                 }
6097                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6098                                mask);
6099                 bnx2x_bits_en(bp,
6100                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6101                               mask);
6102         }
6103 }
6104
6105 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6106 {
6107         u8 *str_ptr = str;
6108         u32 mask = 0xf0000000;
6109         u8 shift = 8*4;
6110         u8 digit;
6111         u8 remove_leading_zeros = 1;
6112         if (*len < 10) {
6113                 /* Need more than 10chars for this format */
6114                 *str_ptr = '\0';
6115                 (*len)--;
6116                 return -EINVAL;
6117         }
6118         while (shift > 0) {
6119
6120                 shift -= 4;
6121                 digit = ((num & mask) >> shift);
6122                 if (digit == 0 && remove_leading_zeros) {
6123                         mask = mask >> 4;
6124                         continue;
6125                 } else if (digit < 0xa)
6126                         *str_ptr = digit + '0';
6127                 else
6128                         *str_ptr = digit - 0xa + 'a';
6129                 remove_leading_zeros = 0;
6130                 str_ptr++;
6131                 (*len)--;
6132                 mask = mask >> 4;
6133                 if (shift == 4*4) {
6134                         *str_ptr = '.';
6135                         str_ptr++;
6136                         (*len)--;
6137                         remove_leading_zeros = 1;
6138                 }
6139         }
6140         return 0;
6141 }
6142
6143
6144 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6145 {
6146         str[0] = '\0';
6147         (*len)--;
6148         return 0;
6149 }
6150
6151 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6152                                  u16 len)
6153 {
6154         struct bnx2x *bp;
6155         u32 spirom_ver = 0;
6156         int status = 0;
6157         u8 *ver_p = version;
6158         u16 remain_len = len;
6159         if (version == NULL || params == NULL)
6160                 return -EINVAL;
6161         bp = params->bp;
6162
6163         /* Extract first external phy*/
6164         version[0] = '\0';
6165         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6166
6167         if (params->phy[EXT_PHY1].format_fw_ver) {
6168                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6169                                                               ver_p,
6170                                                               &remain_len);
6171                 ver_p += (len - remain_len);
6172         }
6173         if ((params->num_phys == MAX_PHYS) &&
6174             (params->phy[EXT_PHY2].ver_addr != 0)) {
6175                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6176                 if (params->phy[EXT_PHY2].format_fw_ver) {
6177                         *ver_p = '/';
6178                         ver_p++;
6179                         remain_len--;
6180                         status |= params->phy[EXT_PHY2].format_fw_ver(
6181                                 spirom_ver,
6182                                 ver_p,
6183                                 &remain_len);
6184                         ver_p = version + (len - remain_len);
6185                 }
6186         }
6187         *ver_p = '\0';
6188         return status;
6189 }
6190
6191 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6192                                     struct link_params *params)
6193 {
6194         u8 port = params->port;
6195         struct bnx2x *bp = params->bp;
6196
6197         if (phy->req_line_speed != SPEED_1000) {
6198                 u32 md_devad = 0;
6199
6200                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6201
6202                 if (!CHIP_IS_E3(bp)) {
6203                         /* Change the uni_phy_addr in the nig */
6204                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6205                                                port*0x18));
6206
6207                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6208                                0x5);
6209                 }
6210
6211                 bnx2x_cl45_write(bp, phy,
6212                                  5,
6213                                  (MDIO_REG_BANK_AER_BLOCK +
6214                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6215                                  0x2800);
6216
6217                 bnx2x_cl45_write(bp, phy,
6218                                  5,
6219                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6220                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6221                                  0x6041);
6222                 msleep(200);
6223                 /* Set aer mmd back */
6224                 bnx2x_set_aer_mmd(params, phy);
6225
6226                 if (!CHIP_IS_E3(bp)) {
6227                         /* And md_devad */
6228                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6229                                md_devad);
6230                 }
6231         } else {
6232                 u16 mii_ctrl;
6233                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6234                 bnx2x_cl45_read(bp, phy, 5,
6235                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6236                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6237                                 &mii_ctrl);
6238                 bnx2x_cl45_write(bp, phy, 5,
6239                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6240                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6241                                  mii_ctrl |
6242                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6243         }
6244 }
6245
6246 int bnx2x_set_led(struct link_params *params,
6247                   struct link_vars *vars, u8 mode, u32 speed)
6248 {
6249         u8 port = params->port;
6250         u16 hw_led_mode = params->hw_led_mode;
6251         int rc = 0;
6252         u8 phy_idx;
6253         u32 tmp;
6254         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6255         struct bnx2x *bp = params->bp;
6256         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6257         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6258                  speed, hw_led_mode);
6259         /* In case */
6260         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6261                 if (params->phy[phy_idx].set_link_led) {
6262                         params->phy[phy_idx].set_link_led(
6263                                 &params->phy[phy_idx], params, mode);
6264                 }
6265         }
6266
6267         switch (mode) {
6268         case LED_MODE_FRONT_PANEL_OFF:
6269         case LED_MODE_OFF:
6270                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6271                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6272                        SHARED_HW_CFG_LED_MAC1);
6273
6274                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6275                 if (params->phy[EXT_PHY1].type ==
6276                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6277                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6278                                 EMAC_LED_100MB_OVERRIDE |
6279                                 EMAC_LED_10MB_OVERRIDE);
6280                 else
6281                         tmp |= EMAC_LED_OVERRIDE;
6282
6283                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6284                 break;
6285
6286         case LED_MODE_OPER:
6287                 /* For all other phys, OPER mode is same as ON, so in case
6288                  * link is down, do nothing
6289                  */
6290                 if (!vars->link_up)
6291                         break;
6292         case LED_MODE_ON:
6293                 if (((params->phy[EXT_PHY1].type ==
6294                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6295                          (params->phy[EXT_PHY1].type ==
6296                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6297                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6298                         /* This is a work-around for E2+8727 Configurations */
6299                         if (mode == LED_MODE_ON ||
6300                                 speed == SPEED_10000){
6301                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6302                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6303
6304                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6305                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6306                                         (tmp | EMAC_LED_OVERRIDE));
6307                                 /* Return here without enabling traffic
6308                                  * LED blink and setting rate in ON mode.
6309                                  * In oper mode, enabling LED blink
6310                                  * and setting rate is needed.
6311                                  */
6312                                 if (mode == LED_MODE_ON)
6313                                         return rc;
6314                         }
6315                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6316                         /* This is a work-around for HW issue found when link
6317                          * is up in CL73
6318                          */
6319                         if ((!CHIP_IS_E3(bp)) ||
6320                             (CHIP_IS_E3(bp) &&
6321                              mode == LED_MODE_ON))
6322                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6323
6324                         if (CHIP_IS_E1x(bp) ||
6325                             CHIP_IS_E2(bp) ||
6326                             (mode == LED_MODE_ON))
6327                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6328                         else
6329                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6330                                        hw_led_mode);
6331                 } else if ((params->phy[EXT_PHY1].type ==
6332                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6333                            (mode == LED_MODE_ON)) {
6334                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6335                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6336                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6337                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6338                         /* Break here; otherwise, it'll disable the
6339                          * intended override.
6340                          */
6341                         break;
6342                 } else
6343                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6344                                hw_led_mode);
6345
6346                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6347                 /* Set blinking rate to ~15.9Hz */
6348                 if (CHIP_IS_E3(bp))
6349                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6350                                LED_BLINK_RATE_VAL_E3);
6351                 else
6352                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6353                                LED_BLINK_RATE_VAL_E1X_E2);
6354                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6355                        port*4, 1);
6356                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6357                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6358                         (tmp & (~EMAC_LED_OVERRIDE)));
6359
6360                 if (CHIP_IS_E1(bp) &&
6361                     ((speed == SPEED_2500) ||
6362                      (speed == SPEED_1000) ||
6363                      (speed == SPEED_100) ||
6364                      (speed == SPEED_10))) {
6365                         /* For speeds less than 10G LED scheme is different */
6366                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6367                                + port*4, 1);
6368                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6369                                port*4, 0);
6370                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6371                                port*4, 1);
6372                 }
6373                 break;
6374
6375         default:
6376                 rc = -EINVAL;
6377                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6378                          mode);
6379                 break;
6380         }
6381         return rc;
6382
6383 }
6384
6385 /* This function comes to reflect the actual link state read DIRECTLY from the
6386  * HW
6387  */
6388 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6389                     u8 is_serdes)
6390 {
6391         struct bnx2x *bp = params->bp;
6392         u16 gp_status = 0, phy_index = 0;
6393         u8 ext_phy_link_up = 0, serdes_phy_type;
6394         struct link_vars temp_vars;
6395         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6396
6397         if (CHIP_IS_E3(bp)) {
6398                 u16 link_up;
6399                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6400                     > SPEED_10000) {
6401                         /* Check 20G link */
6402                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6403                                         1, &link_up);
6404                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6405                                         1, &link_up);
6406                         link_up &= (1<<2);
6407                 } else {
6408                         /* Check 10G link and below*/
6409                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6410                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6411                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6412                                         &gp_status);
6413                         gp_status = ((gp_status >> 8) & 0xf) |
6414                                 ((gp_status >> 12) & 0xf);
6415                         link_up = gp_status & (1 << lane);
6416                 }
6417                 if (!link_up)
6418                         return -ESRCH;
6419         } else {
6420                 CL22_RD_OVER_CL45(bp, int_phy,
6421                           MDIO_REG_BANK_GP_STATUS,
6422                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6423                           &gp_status);
6424         /* Link is up only if both local phy and external phy are up */
6425         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6426                 return -ESRCH;
6427         }
6428         /* In XGXS loopback mode, do not check external PHY */
6429         if (params->loopback_mode == LOOPBACK_XGXS)
6430                 return 0;
6431
6432         switch (params->num_phys) {
6433         case 1:
6434                 /* No external PHY */
6435                 return 0;
6436         case 2:
6437                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6438                         &params->phy[EXT_PHY1],
6439                         params, &temp_vars);
6440                 break;
6441         case 3: /* Dual Media */
6442                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6443                       phy_index++) {
6444                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6445                                             ETH_PHY_SFPP_10G_FIBER) ||
6446                                            (params->phy[phy_index].media_type ==
6447                                             ETH_PHY_SFP_1G_FIBER) ||
6448                                            (params->phy[phy_index].media_type ==
6449                                             ETH_PHY_XFP_FIBER) ||
6450                                            (params->phy[phy_index].media_type ==
6451                                             ETH_PHY_DA_TWINAX));
6452
6453                         if (is_serdes != serdes_phy_type)
6454                                 continue;
6455                         if (params->phy[phy_index].read_status) {
6456                                 ext_phy_link_up |=
6457                                         params->phy[phy_index].read_status(
6458                                                 &params->phy[phy_index],
6459                                                 params, &temp_vars);
6460                         }
6461                 }
6462                 break;
6463         }
6464         if (ext_phy_link_up)
6465                 return 0;
6466         return -ESRCH;
6467 }
6468
6469 static int bnx2x_link_initialize(struct link_params *params,
6470                                  struct link_vars *vars)
6471 {
6472         int rc = 0;
6473         u8 phy_index, non_ext_phy;
6474         struct bnx2x *bp = params->bp;
6475         /* In case of external phy existence, the line speed would be the
6476          * line speed linked up by the external phy. In case it is direct
6477          * only, then the line_speed during initialization will be
6478          * equal to the req_line_speed
6479          */
6480         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6481
6482         /* Initialize the internal phy in case this is a direct board
6483          * (no external phys), or this board has external phy which requires
6484          * to first.
6485          */
6486         if (!USES_WARPCORE(bp))
6487                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6488         /* init ext phy and enable link state int */
6489         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6490                        (params->loopback_mode == LOOPBACK_XGXS));
6491
6492         if (non_ext_phy ||
6493             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6494             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6495                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6496                 if (vars->line_speed == SPEED_AUTO_NEG &&
6497                     (CHIP_IS_E1x(bp) ||
6498                      CHIP_IS_E2(bp)))
6499                         bnx2x_set_parallel_detection(phy, params);
6500                         if (params->phy[INT_PHY].config_init)
6501                                 params->phy[INT_PHY].config_init(phy,
6502                                                                  params,
6503                                                                  vars);
6504         }
6505
6506         /* Init external phy*/
6507         if (non_ext_phy) {
6508                 if (params->phy[INT_PHY].supported &
6509                     SUPPORTED_FIBRE)
6510                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6511         } else {
6512                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6513                       phy_index++) {
6514                         /* No need to initialize second phy in case of first
6515                          * phy only selection. In case of second phy, we do
6516                          * need to initialize the first phy, since they are
6517                          * connected.
6518                          */
6519                         if (params->phy[phy_index].supported &
6520                             SUPPORTED_FIBRE)
6521                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6522
6523                         if (phy_index == EXT_PHY2 &&
6524                             (bnx2x_phy_selection(params) ==
6525                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6526                                 DP(NETIF_MSG_LINK,
6527                                    "Not initializing second phy\n");
6528                                 continue;
6529                         }
6530                         params->phy[phy_index].config_init(
6531                                 &params->phy[phy_index],
6532                                 params, vars);
6533                 }
6534         }
6535         /* Reset the interrupt indication after phy was initialized */
6536         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6537                        params->port*4,
6538                        (NIG_STATUS_XGXS0_LINK10G |
6539                         NIG_STATUS_XGXS0_LINK_STATUS |
6540                         NIG_STATUS_SERDES0_LINK_STATUS |
6541                         NIG_MASK_MI_INT));
6542         return rc;
6543 }
6544
6545 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6546                                  struct link_params *params)
6547 {
6548         /* Reset the SerDes/XGXS */
6549         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6550                (0x1ff << (params->port*16)));
6551 }
6552
6553 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6554                                         struct link_params *params)
6555 {
6556         struct bnx2x *bp = params->bp;
6557         u8 gpio_port;
6558         /* HW reset */
6559         if (CHIP_IS_E2(bp))
6560                 gpio_port = BP_PATH(bp);
6561         else
6562                 gpio_port = params->port;
6563         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6564                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6565                        gpio_port);
6566         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6567                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6568                        gpio_port);
6569         DP(NETIF_MSG_LINK, "reset external PHY\n");
6570 }
6571
6572 static int bnx2x_update_link_down(struct link_params *params,
6573                                   struct link_vars *vars)
6574 {
6575         struct bnx2x *bp = params->bp;
6576         u8 port = params->port;
6577
6578         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6579         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6580         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6581         /* Indicate no mac active */
6582         vars->mac_type = MAC_TYPE_NONE;
6583
6584         /* Update shared memory */
6585         vars->link_status &= ~LINK_UPDATE_MASK;
6586         vars->line_speed = 0;
6587         bnx2x_update_mng(params, vars->link_status);
6588
6589         /* Activate nig drain */
6590         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6591
6592         /* Disable emac */
6593         if (!CHIP_IS_E3(bp))
6594                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6595
6596         usleep_range(10000, 20000);
6597         /* Reset BigMac/Xmac */
6598         if (CHIP_IS_E1x(bp) ||
6599             CHIP_IS_E2(bp))
6600                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6601
6602         if (CHIP_IS_E3(bp)) {
6603                 /* Prevent LPI Generation by chip */
6604                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6605                        0);
6606                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6607                        0);
6608                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6609                                       SHMEM_EEE_ACTIVE_BIT);
6610
6611                 bnx2x_update_mng_eee(params, vars->eee_status);
6612                 bnx2x_set_xmac_rxtx(params, 0);
6613                 bnx2x_set_umac_rxtx(params, 0);
6614         }
6615
6616         return 0;
6617 }
6618
6619 static int bnx2x_update_link_up(struct link_params *params,
6620                                 struct link_vars *vars,
6621                                 u8 link_10g)
6622 {
6623         struct bnx2x *bp = params->bp;
6624         u8 phy_idx, port = params->port;
6625         int rc = 0;
6626
6627         vars->link_status |= (LINK_STATUS_LINK_UP |
6628                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6629         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6630
6631         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6632                 vars->link_status |=
6633                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6634
6635         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6636                 vars->link_status |=
6637                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6638         if (USES_WARPCORE(bp)) {
6639                 if (link_10g) {
6640                         if (bnx2x_xmac_enable(params, vars, 0) ==
6641                             -ESRCH) {
6642                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6643                                 vars->link_up = 0;
6644                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6645                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6646                         }
6647                 } else
6648                         bnx2x_umac_enable(params, vars, 0);
6649                 bnx2x_set_led(params, vars,
6650                               LED_MODE_OPER, vars->line_speed);
6651
6652                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6653                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6654                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6655                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6656                                (params->port << 2), 1);
6657                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6658                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6659                                (params->port << 2), 0xfc20);
6660                 }
6661         }
6662         if ((CHIP_IS_E1x(bp) ||
6663              CHIP_IS_E2(bp))) {
6664                 if (link_10g) {
6665                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6666                             -ESRCH) {
6667                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6668                                 vars->link_up = 0;
6669                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6670                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6671                         }
6672
6673                         bnx2x_set_led(params, vars,
6674                                       LED_MODE_OPER, SPEED_10000);
6675                 } else {
6676                         rc = bnx2x_emac_program(params, vars);
6677                         bnx2x_emac_enable(params, vars, 0);
6678
6679                         /* AN complete? */
6680                         if ((vars->link_status &
6681                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6682                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6683                             SINGLE_MEDIA_DIRECT(params))
6684                                 bnx2x_set_gmii_tx_driver(params);
6685                 }
6686         }
6687
6688         /* PBF - link up */
6689         if (CHIP_IS_E1x(bp))
6690                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6691                                        vars->line_speed);
6692
6693         /* Disable drain */
6694         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6695
6696         /* Update shared memory */
6697         bnx2x_update_mng(params, vars->link_status);
6698         bnx2x_update_mng_eee(params, vars->eee_status);
6699         /* Check remote fault */
6700         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6701                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6702                         bnx2x_check_half_open_conn(params, vars, 0);
6703                         break;
6704                 }
6705         }
6706         msleep(20);
6707         return rc;
6708 }
6709 /* The bnx2x_link_update function should be called upon link
6710  * interrupt.
6711  * Link is considered up as follows:
6712  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6713  *   to be up
6714  * - SINGLE_MEDIA - The link between the 577xx and the external
6715  *   phy (XGXS) need to up as well as the external link of the
6716  *   phy (PHY_EXT1)
6717  * - DUAL_MEDIA - The link between the 577xx and the first
6718  *   external phy needs to be up, and at least one of the 2
6719  *   external phy link must be up.
6720  */
6721 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6722 {
6723         struct bnx2x *bp = params->bp;
6724         struct link_vars phy_vars[MAX_PHYS];
6725         u8 port = params->port;
6726         u8 link_10g_plus, phy_index;
6727         u8 ext_phy_link_up = 0, cur_link_up;
6728         int rc = 0;
6729         u8 is_mi_int = 0;
6730         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6731         u8 active_external_phy = INT_PHY;
6732         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6733         vars->link_status &= ~LINK_UPDATE_MASK;
6734         for (phy_index = INT_PHY; phy_index < params->num_phys;
6735               phy_index++) {
6736                 phy_vars[phy_index].flow_ctrl = 0;
6737                 phy_vars[phy_index].link_status = 0;
6738                 phy_vars[phy_index].line_speed = 0;
6739                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6740                 phy_vars[phy_index].phy_link_up = 0;
6741                 phy_vars[phy_index].link_up = 0;
6742                 phy_vars[phy_index].fault_detected = 0;
6743                 /* different consideration, since vars holds inner state */
6744                 phy_vars[phy_index].eee_status = vars->eee_status;
6745         }
6746
6747         if (USES_WARPCORE(bp))
6748                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6749
6750         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6751                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6752                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6753
6754         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6755                                 port*0x18) > 0);
6756         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6757                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6758                  is_mi_int,
6759                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6760
6761         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6762           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6763           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6764
6765         /* Disable emac */
6766         if (!CHIP_IS_E3(bp))
6767                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6768
6769         /* Step 1:
6770          * Check external link change only for external phys, and apply
6771          * priority selection between them in case the link on both phys
6772          * is up. Note that instead of the common vars, a temporary
6773          * vars argument is used since each phy may have different link/
6774          * speed/duplex result
6775          */
6776         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6777               phy_index++) {
6778                 struct bnx2x_phy *phy = &params->phy[phy_index];
6779                 if (!phy->read_status)
6780                         continue;
6781                 /* Read link status and params of this ext phy */
6782                 cur_link_up = phy->read_status(phy, params,
6783                                                &phy_vars[phy_index]);
6784                 if (cur_link_up) {
6785                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6786                                    phy_index);
6787                 } else {
6788                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6789                                    phy_index);
6790                         continue;
6791                 }
6792
6793                 if (!ext_phy_link_up) {
6794                         ext_phy_link_up = 1;
6795                         active_external_phy = phy_index;
6796                 } else {
6797                         switch (bnx2x_phy_selection(params)) {
6798                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6799                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6800                         /* In this option, the first PHY makes sure to pass the
6801                          * traffic through itself only.
6802                          * Its not clear how to reset the link on the second phy
6803                          */
6804                                 active_external_phy = EXT_PHY1;
6805                                 break;
6806                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6807                         /* In this option, the first PHY makes sure to pass the
6808                          * traffic through the second PHY.
6809                          */
6810                                 active_external_phy = EXT_PHY2;
6811                                 break;
6812                         default:
6813                         /* Link indication on both PHYs with the following cases
6814                          * is invalid:
6815                          * - FIRST_PHY means that second phy wasn't initialized,
6816                          * hence its link is expected to be down
6817                          * - SECOND_PHY means that first phy should not be able
6818                          * to link up by itself (using configuration)
6819                          * - DEFAULT should be overriden during initialiazation
6820                          */
6821                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6822                                            "mpc=0x%x. DISABLING LINK !!!\n",
6823                                            params->multi_phy_config);
6824                                 ext_phy_link_up = 0;
6825                                 break;
6826                         }
6827                 }
6828         }
6829         prev_line_speed = vars->line_speed;
6830         /* Step 2:
6831          * Read the status of the internal phy. In case of
6832          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6833          * otherwise this is the link between the 577xx and the first
6834          * external phy
6835          */
6836         if (params->phy[INT_PHY].read_status)
6837                 params->phy[INT_PHY].read_status(
6838                         &params->phy[INT_PHY],
6839                         params, vars);
6840         /* The INT_PHY flow control reside in the vars. This include the
6841          * case where the speed or flow control are not set to AUTO.
6842          * Otherwise, the active external phy flow control result is set
6843          * to the vars. The ext_phy_line_speed is needed to check if the
6844          * speed is different between the internal phy and external phy.
6845          * This case may be result of intermediate link speed change.
6846          */
6847         if (active_external_phy > INT_PHY) {
6848                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6849                 /* Link speed is taken from the XGXS. AN and FC result from
6850                  * the external phy.
6851                  */
6852                 vars->link_status |= phy_vars[active_external_phy].link_status;
6853
6854                 /* if active_external_phy is first PHY and link is up - disable
6855                  * disable TX on second external PHY
6856                  */
6857                 if (active_external_phy == EXT_PHY1) {
6858                         if (params->phy[EXT_PHY2].phy_specific_func) {
6859                                 DP(NETIF_MSG_LINK,
6860                                    "Disabling TX on EXT_PHY2\n");
6861                                 params->phy[EXT_PHY2].phy_specific_func(
6862                                         &params->phy[EXT_PHY2],
6863                                         params, DISABLE_TX);
6864                         }
6865                 }
6866
6867                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6868                 vars->duplex = phy_vars[active_external_phy].duplex;
6869                 if (params->phy[active_external_phy].supported &
6870                     SUPPORTED_FIBRE)
6871                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6872                 else
6873                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6874
6875                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6876
6877                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6878                            active_external_phy);
6879         }
6880
6881         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6882               phy_index++) {
6883                 if (params->phy[phy_index].flags &
6884                     FLAGS_REARM_LATCH_SIGNAL) {
6885                         bnx2x_rearm_latch_signal(bp, port,
6886                                                  phy_index ==
6887                                                  active_external_phy);
6888                         break;
6889                 }
6890         }
6891         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6892                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6893                    vars->link_status, ext_phy_line_speed);
6894         /* Upon link speed change set the NIG into drain mode. Comes to
6895          * deals with possible FIFO glitch due to clk change when speed
6896          * is decreased without link down indicator
6897          */
6898
6899         if (vars->phy_link_up) {
6900                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6901                     (ext_phy_line_speed != vars->line_speed)) {
6902                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6903                                    " different than the external"
6904                                    " link speed %d\n", vars->line_speed,
6905                                    ext_phy_line_speed);
6906                         vars->phy_link_up = 0;
6907                 } else if (prev_line_speed != vars->line_speed) {
6908                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6909                                0);
6910                         usleep_range(1000, 2000);
6911                 }
6912         }
6913
6914         /* Anything 10 and over uses the bmac */
6915         link_10g_plus = (vars->line_speed >= SPEED_10000);
6916
6917         bnx2x_link_int_ack(params, vars, link_10g_plus);
6918
6919         /* In case external phy link is up, and internal link is down
6920          * (not initialized yet probably after link initialization, it
6921          * needs to be initialized.
6922          * Note that after link down-up as result of cable plug, the xgxs
6923          * link would probably become up again without the need
6924          * initialize it
6925          */
6926         if (!(SINGLE_MEDIA_DIRECT(params))) {
6927                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6928                            " init_preceding = %d\n", ext_phy_link_up,
6929                            vars->phy_link_up,
6930                            params->phy[EXT_PHY1].flags &
6931                            FLAGS_INIT_XGXS_FIRST);
6932                 if (!(params->phy[EXT_PHY1].flags &
6933                       FLAGS_INIT_XGXS_FIRST)
6934                     && ext_phy_link_up && !vars->phy_link_up) {
6935                         vars->line_speed = ext_phy_line_speed;
6936                         if (vars->line_speed < SPEED_1000)
6937                                 vars->phy_flags |= PHY_SGMII_FLAG;
6938                         else
6939                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6940
6941                         if (params->phy[INT_PHY].config_init)
6942                                 params->phy[INT_PHY].config_init(
6943                                         &params->phy[INT_PHY], params,
6944                                                 vars);
6945                 }
6946         }
6947         /* Link is up only if both local phy and external phy (in case of
6948          * non-direct board) are up and no fault detected on active PHY.
6949          */
6950         vars->link_up = (vars->phy_link_up &&
6951                          (ext_phy_link_up ||
6952                           SINGLE_MEDIA_DIRECT(params)) &&
6953                          (phy_vars[active_external_phy].fault_detected == 0));
6954
6955         /* Update the PFC configuration in case it was changed */
6956         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6957                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6958         else
6959                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6960
6961         if (vars->link_up)
6962                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6963         else
6964                 rc = bnx2x_update_link_down(params, vars);
6965
6966         /* Update MCP link status was changed */
6967         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6968                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6969
6970         return rc;
6971 }
6972
6973 /*****************************************************************************/
6974 /*                          External Phy section                             */
6975 /*****************************************************************************/
6976 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6977 {
6978         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6979                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6980         usleep_range(1000, 2000);
6981         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6982                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6983 }
6984
6985 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6986                                       u32 spirom_ver, u32 ver_addr)
6987 {
6988         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6989                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6990
6991         if (ver_addr)
6992                 REG_WR(bp, ver_addr, spirom_ver);
6993 }
6994
6995 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6996                                       struct bnx2x_phy *phy,
6997                                       u8 port)
6998 {
6999         u16 fw_ver1, fw_ver2;
7000
7001         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7002                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7003         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7004                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7005         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7006                                   phy->ver_addr);
7007 }
7008
7009 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7010                                        struct bnx2x_phy *phy,
7011                                        struct link_vars *vars)
7012 {
7013         u16 val;
7014         bnx2x_cl45_read(bp, phy,
7015                         MDIO_AN_DEVAD,
7016                         MDIO_AN_REG_STATUS, &val);
7017         bnx2x_cl45_read(bp, phy,
7018                         MDIO_AN_DEVAD,
7019                         MDIO_AN_REG_STATUS, &val);
7020         if (val & (1<<5))
7021                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7022         if ((val & (1<<0)) == 0)
7023                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7024 }
7025
7026 /******************************************************************/
7027 /*              common BCM8073/BCM8727 PHY SECTION                */
7028 /******************************************************************/
7029 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7030                                   struct link_params *params,
7031                                   struct link_vars *vars)
7032 {
7033         struct bnx2x *bp = params->bp;
7034         if (phy->req_line_speed == SPEED_10 ||
7035             phy->req_line_speed == SPEED_100) {
7036                 vars->flow_ctrl = phy->req_flow_ctrl;
7037                 return;
7038         }
7039
7040         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7041             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7042                 u16 pause_result;
7043                 u16 ld_pause;           /* local */
7044                 u16 lp_pause;           /* link partner */
7045                 bnx2x_cl45_read(bp, phy,
7046                                 MDIO_AN_DEVAD,
7047                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7048
7049                 bnx2x_cl45_read(bp, phy,
7050                                 MDIO_AN_DEVAD,
7051                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7052                 pause_result = (ld_pause &
7053                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7054                 pause_result |= (lp_pause &
7055                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7056
7057                 bnx2x_pause_resolve(vars, pause_result);
7058                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7059                            pause_result);
7060         }
7061 }
7062 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7063                                              struct bnx2x_phy *phy,
7064                                              u8 port)
7065 {
7066         u32 count = 0;
7067         u16 fw_ver1, fw_msgout;
7068         int rc = 0;
7069
7070         /* Boot port from external ROM  */
7071         /* EDC grst */
7072         bnx2x_cl45_write(bp, phy,
7073                          MDIO_PMA_DEVAD,
7074                          MDIO_PMA_REG_GEN_CTRL,
7075                          0x0001);
7076
7077         /* Ucode reboot and rst */
7078         bnx2x_cl45_write(bp, phy,
7079                          MDIO_PMA_DEVAD,
7080                          MDIO_PMA_REG_GEN_CTRL,
7081                          0x008c);
7082
7083         bnx2x_cl45_write(bp, phy,
7084                          MDIO_PMA_DEVAD,
7085                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7086
7087         /* Reset internal microprocessor */
7088         bnx2x_cl45_write(bp, phy,
7089                          MDIO_PMA_DEVAD,
7090                          MDIO_PMA_REG_GEN_CTRL,
7091                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7092
7093         /* Release srst bit */
7094         bnx2x_cl45_write(bp, phy,
7095                          MDIO_PMA_DEVAD,
7096                          MDIO_PMA_REG_GEN_CTRL,
7097                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7098
7099         /* Delay 100ms per the PHY specifications */
7100         msleep(100);
7101
7102         /* 8073 sometimes taking longer to download */
7103         do {
7104                 count++;
7105                 if (count > 300) {
7106                         DP(NETIF_MSG_LINK,
7107                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7108                                  "Download failed. fw version = 0x%x\n",
7109                                  port, fw_ver1);
7110                         rc = -EINVAL;
7111                         break;
7112                 }
7113
7114                 bnx2x_cl45_read(bp, phy,
7115                                 MDIO_PMA_DEVAD,
7116                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7117                 bnx2x_cl45_read(bp, phy,
7118                                 MDIO_PMA_DEVAD,
7119                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7120
7121                 usleep_range(1000, 2000);
7122         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7123                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7124                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7125
7126         /* Clear ser_boot_ctl bit */
7127         bnx2x_cl45_write(bp, phy,
7128                          MDIO_PMA_DEVAD,
7129                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7130         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7131
7132         DP(NETIF_MSG_LINK,
7133                  "bnx2x_8073_8727_external_rom_boot port %x:"
7134                  "Download complete. fw version = 0x%x\n",
7135                  port, fw_ver1);
7136
7137         return rc;
7138 }
7139
7140 /******************************************************************/
7141 /*                      BCM8073 PHY SECTION                       */
7142 /******************************************************************/
7143 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7144 {
7145         /* This is only required for 8073A1, version 102 only */
7146         u16 val;
7147
7148         /* Read 8073 HW revision*/
7149         bnx2x_cl45_read(bp, phy,
7150                         MDIO_PMA_DEVAD,
7151                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7152
7153         if (val != 1) {
7154                 /* No need to workaround in 8073 A1 */
7155                 return 0;
7156         }
7157
7158         bnx2x_cl45_read(bp, phy,
7159                         MDIO_PMA_DEVAD,
7160                         MDIO_PMA_REG_ROM_VER2, &val);
7161
7162         /* SNR should be applied only for version 0x102 */
7163         if (val != 0x102)
7164                 return 0;
7165
7166         return 1;
7167 }
7168
7169 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7170 {
7171         u16 val, cnt, cnt1 ;
7172
7173         bnx2x_cl45_read(bp, phy,
7174                         MDIO_PMA_DEVAD,
7175                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7176
7177         if (val > 0) {
7178                 /* No need to workaround in 8073 A1 */
7179                 return 0;
7180         }
7181         /* XAUI workaround in 8073 A0: */
7182
7183         /* After loading the boot ROM and restarting Autoneg, poll
7184          * Dev1, Reg $C820:
7185          */
7186
7187         for (cnt = 0; cnt < 1000; cnt++) {
7188                 bnx2x_cl45_read(bp, phy,
7189                                 MDIO_PMA_DEVAD,
7190                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7191                                 &val);
7192                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7193                    * system initialization (XAUI work-around not required, as
7194                    * these bits indicate 2.5G or 1G link up).
7195                    */
7196                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7197                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7198                         return 0;
7199                 } else if (!(val & (1<<15))) {
7200                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7201                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7202                          * MSB (bit15) goes to 1 (indicating that the XAUI
7203                          * workaround has completed), then continue on with
7204                          * system initialization.
7205                          */
7206                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7207                                 bnx2x_cl45_read(bp, phy,
7208                                         MDIO_PMA_DEVAD,
7209                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7210                                 if (val & (1<<15)) {
7211                                         DP(NETIF_MSG_LINK,
7212                                           "XAUI workaround has completed\n");
7213                                         return 0;
7214                                  }
7215                                  usleep_range(3000, 6000);
7216                         }
7217                         break;
7218                 }
7219                 usleep_range(3000, 6000);
7220         }
7221         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7222         return -EINVAL;
7223 }
7224
7225 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7226 {
7227         /* Force KR or KX */
7228         bnx2x_cl45_write(bp, phy,
7229                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7230         bnx2x_cl45_write(bp, phy,
7231                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7232         bnx2x_cl45_write(bp, phy,
7233                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7234         bnx2x_cl45_write(bp, phy,
7235                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7236 }
7237
7238 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7239                                       struct bnx2x_phy *phy,
7240                                       struct link_vars *vars)
7241 {
7242         u16 cl37_val;
7243         struct bnx2x *bp = params->bp;
7244         bnx2x_cl45_read(bp, phy,
7245                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7246
7247         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7248         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7249         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7250         if ((vars->ieee_fc &
7251             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7252             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7253                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7254         }
7255         if ((vars->ieee_fc &
7256             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7257             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7258                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7259         }
7260         if ((vars->ieee_fc &
7261             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7262             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7263                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7264         }
7265         DP(NETIF_MSG_LINK,
7266                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7267
7268         bnx2x_cl45_write(bp, phy,
7269                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7270         msleep(500);
7271 }
7272
7273 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7274                                      struct link_params *params,
7275                                      u32 action)
7276 {
7277         struct bnx2x *bp = params->bp;
7278         switch (action) {
7279         case PHY_INIT:
7280                 /* Enable LASI */
7281                 bnx2x_cl45_write(bp, phy,
7282                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7283                 bnx2x_cl45_write(bp, phy,
7284                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7285                 break;
7286         }
7287 }
7288
7289 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7290                                   struct link_params *params,
7291                                   struct link_vars *vars)
7292 {
7293         struct bnx2x *bp = params->bp;
7294         u16 val = 0, tmp1;
7295         u8 gpio_port;
7296         DP(NETIF_MSG_LINK, "Init 8073\n");
7297
7298         if (CHIP_IS_E2(bp))
7299                 gpio_port = BP_PATH(bp);
7300         else
7301                 gpio_port = params->port;
7302         /* Restore normal power mode*/
7303         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7304                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7305
7306         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7307                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7308
7309         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7310         bnx2x_8073_set_pause_cl37(params, phy, vars);
7311
7312         bnx2x_cl45_read(bp, phy,
7313                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7314
7315         bnx2x_cl45_read(bp, phy,
7316                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7317
7318         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7319
7320         /* Swap polarity if required - Must be done only in non-1G mode */
7321         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7322                 /* Configure the 8073 to swap _P and _N of the KR lines */
7323                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7324                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7325                 bnx2x_cl45_read(bp, phy,
7326                                 MDIO_PMA_DEVAD,
7327                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7328                 bnx2x_cl45_write(bp, phy,
7329                                  MDIO_PMA_DEVAD,
7330                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7331                                  (val | (3<<9)));
7332         }
7333
7334
7335         /* Enable CL37 BAM */
7336         if (REG_RD(bp, params->shmem_base +
7337                          offsetof(struct shmem_region, dev_info.
7338                                   port_hw_config[params->port].default_cfg)) &
7339             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7340
7341                 bnx2x_cl45_read(bp, phy,
7342                                 MDIO_AN_DEVAD,
7343                                 MDIO_AN_REG_8073_BAM, &val);
7344                 bnx2x_cl45_write(bp, phy,
7345                                  MDIO_AN_DEVAD,
7346                                  MDIO_AN_REG_8073_BAM, val | 1);
7347                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7348         }
7349         if (params->loopback_mode == LOOPBACK_EXT) {
7350                 bnx2x_807x_force_10G(bp, phy);
7351                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7352                 return 0;
7353         } else {
7354                 bnx2x_cl45_write(bp, phy,
7355                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7356         }
7357         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7358                 if (phy->req_line_speed == SPEED_10000) {
7359                         val = (1<<7);
7360                 } else if (phy->req_line_speed ==  SPEED_2500) {
7361                         val = (1<<5);
7362                         /* Note that 2.5G works only when used with 1G
7363                          * advertisement
7364                          */
7365                 } else
7366                         val = (1<<5);
7367         } else {
7368                 val = 0;
7369                 if (phy->speed_cap_mask &
7370                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7371                         val |= (1<<7);
7372
7373                 /* Note that 2.5G works only when used with 1G advertisement */
7374                 if (phy->speed_cap_mask &
7375                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7376                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7377                         val |= (1<<5);
7378                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7379         }
7380
7381         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7382         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7383
7384         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7385              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7386             (phy->req_line_speed == SPEED_2500)) {
7387                 u16 phy_ver;
7388                 /* Allow 2.5G for A1 and above */
7389                 bnx2x_cl45_read(bp, phy,
7390                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7391                                 &phy_ver);
7392                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7393                 if (phy_ver > 0)
7394                         tmp1 |= 1;
7395                 else
7396                         tmp1 &= 0xfffe;
7397         } else {
7398                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7399                 tmp1 &= 0xfffe;
7400         }
7401
7402         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7403         /* Add support for CL37 (passive mode) II */
7404
7405         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7406         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7407                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7408                                   0x20 : 0x40)));
7409
7410         /* Add support for CL37 (passive mode) III */
7411         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7412
7413         /* The SNR will improve about 2db by changing BW and FEE main
7414          * tap. Rest commands are executed after link is up
7415          * Change FFE main cursor to 5 in EDC register
7416          */
7417         if (bnx2x_8073_is_snr_needed(bp, phy))
7418                 bnx2x_cl45_write(bp, phy,
7419                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7420                                  0xFB0C);
7421
7422         /* Enable FEC (Forware Error Correction) Request in the AN */
7423         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7424         tmp1 |= (1<<15);
7425         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7426
7427         bnx2x_ext_phy_set_pause(params, phy, vars);
7428
7429         /* Restart autoneg */
7430         msleep(500);
7431         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7432         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7433                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7434         return 0;
7435 }
7436
7437 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7438                                  struct link_params *params,
7439                                  struct link_vars *vars)
7440 {
7441         struct bnx2x *bp = params->bp;
7442         u8 link_up = 0;
7443         u16 val1, val2;
7444         u16 link_status = 0;
7445         u16 an1000_status = 0;
7446
7447         bnx2x_cl45_read(bp, phy,
7448                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7449
7450         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7451
7452         /* Clear the interrupt LASI status register */
7453         bnx2x_cl45_read(bp, phy,
7454                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7455         bnx2x_cl45_read(bp, phy,
7456                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7457         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7458         /* Clear MSG-OUT */
7459         bnx2x_cl45_read(bp, phy,
7460                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7461
7462         /* Check the LASI */
7463         bnx2x_cl45_read(bp, phy,
7464                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7465
7466         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7467
7468         /* Check the link status */
7469         bnx2x_cl45_read(bp, phy,
7470                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7471         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7472
7473         bnx2x_cl45_read(bp, phy,
7474                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7475         bnx2x_cl45_read(bp, phy,
7476                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7477         link_up = ((val1 & 4) == 4);
7478         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7479
7480         if (link_up &&
7481              ((phy->req_line_speed != SPEED_10000))) {
7482                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7483                         return 0;
7484         }
7485         bnx2x_cl45_read(bp, phy,
7486                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7487         bnx2x_cl45_read(bp, phy,
7488                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7489
7490         /* Check the link status on 1.1.2 */
7491         bnx2x_cl45_read(bp, phy,
7492                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7493         bnx2x_cl45_read(bp, phy,
7494                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7495         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7496                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7497
7498         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7499         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7500                 /* The SNR will improve about 2dbby changing the BW and FEE main
7501                  * tap. The 1st write to change FFE main tap is set before
7502                  * restart AN. Change PLL Bandwidth in EDC register
7503                  */
7504                 bnx2x_cl45_write(bp, phy,
7505                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7506                                  0x26BC);
7507
7508                 /* Change CDR Bandwidth in EDC register */
7509                 bnx2x_cl45_write(bp, phy,
7510                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7511                                  0x0333);
7512         }
7513         bnx2x_cl45_read(bp, phy,
7514                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7515                         &link_status);
7516
7517         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7518         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7519                 link_up = 1;
7520                 vars->line_speed = SPEED_10000;
7521                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7522                            params->port);
7523         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7524                 link_up = 1;
7525                 vars->line_speed = SPEED_2500;
7526                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7527                            params->port);
7528         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7529                 link_up = 1;
7530                 vars->line_speed = SPEED_1000;
7531                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7532                            params->port);
7533         } else {
7534                 link_up = 0;
7535                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7536                            params->port);
7537         }
7538
7539         if (link_up) {
7540                 /* Swap polarity if required */
7541                 if (params->lane_config &
7542                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7543                         /* Configure the 8073 to swap P and N of the KR lines */
7544                         bnx2x_cl45_read(bp, phy,
7545                                         MDIO_XS_DEVAD,
7546                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7547                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7548                          * when it`s in 10G mode.
7549                          */
7550                         if (vars->line_speed == SPEED_1000) {
7551                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7552                                               "the 8073\n");
7553                                 val1 |= (1<<3);
7554                         } else
7555                                 val1 &= ~(1<<3);
7556
7557                         bnx2x_cl45_write(bp, phy,
7558                                          MDIO_XS_DEVAD,
7559                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7560                                          val1);
7561                 }
7562                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7563                 bnx2x_8073_resolve_fc(phy, params, vars);
7564                 vars->duplex = DUPLEX_FULL;
7565         }
7566
7567         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7568                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7569                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7570
7571                 if (val1 & (1<<5))
7572                         vars->link_status |=
7573                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7574                 if (val1 & (1<<7))
7575                         vars->link_status |=
7576                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7577         }
7578
7579         return link_up;
7580 }
7581
7582 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7583                                   struct link_params *params)
7584 {
7585         struct bnx2x *bp = params->bp;
7586         u8 gpio_port;
7587         if (CHIP_IS_E2(bp))
7588                 gpio_port = BP_PATH(bp);
7589         else
7590                 gpio_port = params->port;
7591         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7592            gpio_port);
7593         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7594                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7595                        gpio_port);
7596 }
7597
7598 /******************************************************************/
7599 /*                      BCM8705 PHY SECTION                       */
7600 /******************************************************************/
7601 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7602                                   struct link_params *params,
7603                                   struct link_vars *vars)
7604 {
7605         struct bnx2x *bp = params->bp;
7606         DP(NETIF_MSG_LINK, "init 8705\n");
7607         /* Restore normal power mode*/
7608         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7609                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7610         /* HW reset */
7611         bnx2x_ext_phy_hw_reset(bp, params->port);
7612         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7613         bnx2x_wait_reset_complete(bp, phy, params);
7614
7615         bnx2x_cl45_write(bp, phy,
7616                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7617         bnx2x_cl45_write(bp, phy,
7618                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7619         bnx2x_cl45_write(bp, phy,
7620                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7621         bnx2x_cl45_write(bp, phy,
7622                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7623         /* BCM8705 doesn't have microcode, hence the 0 */
7624         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7625         return 0;
7626 }
7627
7628 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7629                                  struct link_params *params,
7630                                  struct link_vars *vars)
7631 {
7632         u8 link_up = 0;
7633         u16 val1, rx_sd;
7634         struct bnx2x *bp = params->bp;
7635         DP(NETIF_MSG_LINK, "read status 8705\n");
7636         bnx2x_cl45_read(bp, phy,
7637                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7638         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7639
7640         bnx2x_cl45_read(bp, phy,
7641                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7642         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7643
7644         bnx2x_cl45_read(bp, phy,
7645                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7646
7647         bnx2x_cl45_read(bp, phy,
7648                       MDIO_PMA_DEVAD, 0xc809, &val1);
7649         bnx2x_cl45_read(bp, phy,
7650                       MDIO_PMA_DEVAD, 0xc809, &val1);
7651
7652         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7653         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7654         if (link_up) {
7655                 vars->line_speed = SPEED_10000;
7656                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7657         }
7658         return link_up;
7659 }
7660
7661 /******************************************************************/
7662 /*                      SFP+ module Section                       */
7663 /******************************************************************/
7664 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7665                                            struct bnx2x_phy *phy,
7666                                            u8 pmd_dis)
7667 {
7668         struct bnx2x *bp = params->bp;
7669         /* Disable transmitter only for bootcodes which can enable it afterwards
7670          * (for D3 link)
7671          */
7672         if (pmd_dis) {
7673                 if (params->feature_config_flags &
7674                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7675                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7676                 else {
7677                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7678                         return;
7679                 }
7680         } else
7681                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7682         bnx2x_cl45_write(bp, phy,
7683                          MDIO_PMA_DEVAD,
7684                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7685 }
7686
7687 static u8 bnx2x_get_gpio_port(struct link_params *params)
7688 {
7689         u8 gpio_port;
7690         u32 swap_val, swap_override;
7691         struct bnx2x *bp = params->bp;
7692         if (CHIP_IS_E2(bp))
7693                 gpio_port = BP_PATH(bp);
7694         else
7695                 gpio_port = params->port;
7696         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7697         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7698         return gpio_port ^ (swap_val && swap_override);
7699 }
7700
7701 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7702                                            struct bnx2x_phy *phy,
7703                                            u8 tx_en)
7704 {
7705         u16 val;
7706         u8 port = params->port;
7707         struct bnx2x *bp = params->bp;
7708         u32 tx_en_mode;
7709
7710         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7711         tx_en_mode = REG_RD(bp, params->shmem_base +
7712                             offsetof(struct shmem_region,
7713                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7714                 PORT_HW_CFG_TX_LASER_MASK;
7715         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7716                            "mode = %x\n", tx_en, port, tx_en_mode);
7717         switch (tx_en_mode) {
7718         case PORT_HW_CFG_TX_LASER_MDIO:
7719
7720                 bnx2x_cl45_read(bp, phy,
7721                                 MDIO_PMA_DEVAD,
7722                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7723                                 &val);
7724
7725                 if (tx_en)
7726                         val &= ~(1<<15);
7727                 else
7728                         val |= (1<<15);
7729
7730                 bnx2x_cl45_write(bp, phy,
7731                                  MDIO_PMA_DEVAD,
7732                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7733                                  val);
7734         break;
7735         case PORT_HW_CFG_TX_LASER_GPIO0:
7736         case PORT_HW_CFG_TX_LASER_GPIO1:
7737         case PORT_HW_CFG_TX_LASER_GPIO2:
7738         case PORT_HW_CFG_TX_LASER_GPIO3:
7739         {
7740                 u16 gpio_pin;
7741                 u8 gpio_port, gpio_mode;
7742                 if (tx_en)
7743                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7744                 else
7745                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7746
7747                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7748                 gpio_port = bnx2x_get_gpio_port(params);
7749                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7750                 break;
7751         }
7752         default:
7753                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7754                 break;
7755         }
7756 }
7757
7758 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7759                                       struct bnx2x_phy *phy,
7760                                       u8 tx_en)
7761 {
7762         struct bnx2x *bp = params->bp;
7763         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7764         if (CHIP_IS_E3(bp))
7765                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7766         else
7767                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7768 }
7769
7770 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7771                                              struct link_params *params,
7772                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7773                                              u8 *o_buf, u8 is_init)
7774 {
7775         struct bnx2x *bp = params->bp;
7776         u16 val = 0;
7777         u16 i;
7778         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7779                 DP(NETIF_MSG_LINK,
7780                    "Reading from eeprom is limited to 0xf\n");
7781                 return -EINVAL;
7782         }
7783         /* Set the read command byte count */
7784         bnx2x_cl45_write(bp, phy,
7785                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7786                          (byte_cnt | (dev_addr << 8)));
7787
7788         /* Set the read command address */
7789         bnx2x_cl45_write(bp, phy,
7790                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7791                          addr);
7792
7793         /* Activate read command */
7794         bnx2x_cl45_write(bp, phy,
7795                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7796                          0x2c0f);
7797
7798         /* Wait up to 500us for command complete status */
7799         for (i = 0; i < 100; i++) {
7800                 bnx2x_cl45_read(bp, phy,
7801                                 MDIO_PMA_DEVAD,
7802                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7803                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7804                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7805                         break;
7806                 udelay(5);
7807         }
7808
7809         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7810                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7811                 DP(NETIF_MSG_LINK,
7812                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7813                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7814                 return -EINVAL;
7815         }
7816
7817         /* Read the buffer */
7818         for (i = 0; i < byte_cnt; i++) {
7819                 bnx2x_cl45_read(bp, phy,
7820                                 MDIO_PMA_DEVAD,
7821                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7822                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7823         }
7824
7825         for (i = 0; i < 100; i++) {
7826                 bnx2x_cl45_read(bp, phy,
7827                                 MDIO_PMA_DEVAD,
7828                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7829                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7830                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7831                         return 0;
7832                 usleep_range(1000, 2000);
7833         }
7834         return -EINVAL;
7835 }
7836
7837 static void bnx2x_warpcore_power_module(struct link_params *params,
7838                                         u8 power)
7839 {
7840         u32 pin_cfg;
7841         struct bnx2x *bp = params->bp;
7842
7843         pin_cfg = (REG_RD(bp, params->shmem_base +
7844                           offsetof(struct shmem_region,
7845                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7846                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7847                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7848
7849         if (pin_cfg == PIN_CFG_NA)
7850                 return;
7851         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7852                        power, pin_cfg);
7853         /* Low ==> corresponding SFP+ module is powered
7854          * high ==> the SFP+ module is powered down
7855          */
7856         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7857 }
7858 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7859                                                  struct link_params *params,
7860                                                  u8 dev_addr,
7861                                                  u16 addr, u8 byte_cnt,
7862                                                  u8 *o_buf, u8 is_init)
7863 {
7864         int rc = 0;
7865         u8 i, j = 0, cnt = 0;
7866         u32 data_array[4];
7867         u16 addr32;
7868         struct bnx2x *bp = params->bp;
7869
7870         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7871                 DP(NETIF_MSG_LINK,
7872                    "Reading from eeprom is limited to 16 bytes\n");
7873                 return -EINVAL;
7874         }
7875
7876         /* 4 byte aligned address */
7877         addr32 = addr & (~0x3);
7878         do {
7879                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7880                         bnx2x_warpcore_power_module(params, 0);
7881                         /* Note that 100us are not enough here */
7882                         usleep_range(1000, 2000);
7883                         bnx2x_warpcore_power_module(params, 1);
7884                 }
7885                 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt,
7886                                     data_array);
7887         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7888
7889         if (rc == 0) {
7890                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7891                         o_buf[j] = *((u8 *)data_array + i);
7892                         j++;
7893                 }
7894         }
7895
7896         return rc;
7897 }
7898
7899 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7900                                              struct link_params *params,
7901                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7902                                              u8 *o_buf, u8 is_init)
7903 {
7904         struct bnx2x *bp = params->bp;
7905         u16 val, i;
7906
7907         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7908                 DP(NETIF_MSG_LINK,
7909                    "Reading from eeprom is limited to 0xf\n");
7910                 return -EINVAL;
7911         }
7912
7913         /* Set 2-wire transfer rate of SFP+ module EEPROM
7914          * to 100Khz since some DACs(direct attached cables) do
7915          * not work at 400Khz.
7916          */
7917         bnx2x_cl45_write(bp, phy,
7918                          MDIO_PMA_DEVAD,
7919                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7920                          ((dev_addr << 8) | 1));
7921
7922         /* Need to read from 1.8000 to clear it */
7923         bnx2x_cl45_read(bp, phy,
7924                         MDIO_PMA_DEVAD,
7925                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7926                         &val);
7927
7928         /* Set the read command byte count */
7929         bnx2x_cl45_write(bp, phy,
7930                          MDIO_PMA_DEVAD,
7931                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7932                          ((byte_cnt < 2) ? 2 : byte_cnt));
7933
7934         /* Set the read command address */
7935         bnx2x_cl45_write(bp, phy,
7936                          MDIO_PMA_DEVAD,
7937                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7938                          addr);
7939         /* Set the destination address */
7940         bnx2x_cl45_write(bp, phy,
7941                          MDIO_PMA_DEVAD,
7942                          0x8004,
7943                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7944
7945         /* Activate read command */
7946         bnx2x_cl45_write(bp, phy,
7947                          MDIO_PMA_DEVAD,
7948                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7949                          0x8002);
7950         /* Wait appropriate time for two-wire command to finish before
7951          * polling the status register
7952          */
7953         usleep_range(1000, 2000);
7954
7955         /* Wait up to 500us for command complete status */
7956         for (i = 0; i < 100; i++) {
7957                 bnx2x_cl45_read(bp, phy,
7958                                 MDIO_PMA_DEVAD,
7959                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7960                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7961                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7962                         break;
7963                 udelay(5);
7964         }
7965
7966         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7967                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7968                 DP(NETIF_MSG_LINK,
7969                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7970                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7971                 return -EFAULT;
7972         }
7973
7974         /* Read the buffer */
7975         for (i = 0; i < byte_cnt; i++) {
7976                 bnx2x_cl45_read(bp, phy,
7977                                 MDIO_PMA_DEVAD,
7978                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7979                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7980         }
7981
7982         for (i = 0; i < 100; i++) {
7983                 bnx2x_cl45_read(bp, phy,
7984                                 MDIO_PMA_DEVAD,
7985                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7986                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7987                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7988                         return 0;
7989                 usleep_range(1000, 2000);
7990         }
7991
7992         return -EINVAL;
7993 }
7994 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7995                                  struct link_params *params, u8 dev_addr,
7996                                  u16 addr, u16 byte_cnt, u8 *o_buf)
7997 {
7998         int rc = 0;
7999         struct bnx2x *bp = params->bp;
8000         u8 xfer_size;
8001         u8 *user_data = o_buf;
8002         read_sfp_module_eeprom_func_p read_func;
8003
8004         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8005                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8006                 return -EINVAL;
8007         }
8008
8009         switch (phy->type) {
8010         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8011                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8012                 break;
8013         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8014         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8015                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8016                 break;
8017         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8018                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8019                 break;
8020         default:
8021                 return -EOPNOTSUPP;
8022         }
8023
8024         while (!rc && (byte_cnt > 0)) {
8025                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8026                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8027                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8028                                user_data, 0);
8029                 byte_cnt -= xfer_size;
8030                 user_data += xfer_size;
8031                 addr += xfer_size;
8032         }
8033         return rc;
8034 }
8035
8036 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8037                               struct link_params *params,
8038                               u16 *edc_mode)
8039 {
8040         struct bnx2x *bp = params->bp;
8041         u32 sync_offset = 0, phy_idx, media_types;
8042         u8 gport, val[2], check_limiting_mode = 0;
8043         *edc_mode = EDC_MODE_LIMITING;
8044         phy->media_type = ETH_PHY_UNSPECIFIED;
8045         /* First check for copper cable */
8046         if (bnx2x_read_sfp_module_eeprom(phy,
8047                                          params,
8048                                          I2C_DEV_ADDR_A0,
8049                                          SFP_EEPROM_CON_TYPE_ADDR,
8050                                          2,
8051                                          (u8 *)val) != 0) {
8052                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8053                 return -EINVAL;
8054         }
8055
8056         switch (val[0]) {
8057         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8058         {
8059                 u8 copper_module_type;
8060                 phy->media_type = ETH_PHY_DA_TWINAX;
8061                 /* Check if its active cable (includes SFP+ module)
8062                  * of passive cable
8063                  */
8064                 if (bnx2x_read_sfp_module_eeprom(phy,
8065                                                params,
8066                                                I2C_DEV_ADDR_A0,
8067                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8068                                                1,
8069                                                &copper_module_type) != 0) {
8070                         DP(NETIF_MSG_LINK,
8071                                 "Failed to read copper-cable-type"
8072                                 " from SFP+ EEPROM\n");
8073                         return -EINVAL;
8074                 }
8075
8076                 if (copper_module_type &
8077                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8078                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8079                         check_limiting_mode = 1;
8080                 } else if (copper_module_type &
8081                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8082                                 DP(NETIF_MSG_LINK,
8083                                    "Passive Copper cable detected\n");
8084                                 *edc_mode =
8085                                       EDC_MODE_PASSIVE_DAC;
8086                 } else {
8087                         DP(NETIF_MSG_LINK,
8088                            "Unknown copper-cable-type 0x%x !!!\n",
8089                            copper_module_type);
8090                         return -EINVAL;
8091                 }
8092                 break;
8093         }
8094         case SFP_EEPROM_CON_TYPE_VAL_LC:
8095         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8096                 check_limiting_mode = 1;
8097                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8098                                SFP_EEPROM_COMP_CODE_LR_MASK |
8099                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8100                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8101                         gport = params->port;
8102                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8103                         if (phy->req_line_speed != SPEED_1000) {
8104                                 phy->req_line_speed = SPEED_1000;
8105                                 if (!CHIP_IS_E1x(bp)) {
8106                                         gport = BP_PATH(bp) +
8107                                         (params->port << 1);
8108                                 }
8109                                 netdev_err(bp->dev,
8110                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8111                                            gport);
8112                         }
8113                 } else {
8114                         int idx, cfg_idx = 0;
8115                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8116                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8117                                 if (params->phy[idx].type == phy->type) {
8118                                         cfg_idx = LINK_CONFIG_IDX(idx);
8119                                         break;
8120                                 }
8121                         }
8122                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8123                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8124                 }
8125                 break;
8126         default:
8127                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8128                          val[0]);
8129                 return -EINVAL;
8130         }
8131         sync_offset = params->shmem_base +
8132                 offsetof(struct shmem_region,
8133                          dev_info.port_hw_config[params->port].media_type);
8134         media_types = REG_RD(bp, sync_offset);
8135         /* Update media type for non-PMF sync */
8136         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8137                 if (&(params->phy[phy_idx]) == phy) {
8138                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8139                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8140                         media_types |= ((phy->media_type &
8141                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8142                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8143                         break;
8144                 }
8145         }
8146         REG_WR(bp, sync_offset, media_types);
8147         if (check_limiting_mode) {
8148                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8149                 if (bnx2x_read_sfp_module_eeprom(phy,
8150                                                  params,
8151                                                  I2C_DEV_ADDR_A0,
8152                                                  SFP_EEPROM_OPTIONS_ADDR,
8153                                                  SFP_EEPROM_OPTIONS_SIZE,
8154                                                  options) != 0) {
8155                         DP(NETIF_MSG_LINK,
8156                            "Failed to read Option field from module EEPROM\n");
8157                         return -EINVAL;
8158                 }
8159                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8160                         *edc_mode = EDC_MODE_LINEAR;
8161                 else
8162                         *edc_mode = EDC_MODE_LIMITING;
8163         }
8164         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8165         return 0;
8166 }
8167 /* This function read the relevant field from the module (SFP+), and verify it
8168  * is compliant with this board
8169  */
8170 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8171                                    struct link_params *params)
8172 {
8173         struct bnx2x *bp = params->bp;
8174         u32 val, cmd;
8175         u32 fw_resp, fw_cmd_param;
8176         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8177         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8178         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8179         val = REG_RD(bp, params->shmem_base +
8180                          offsetof(struct shmem_region, dev_info.
8181                                   port_feature_config[params->port].config));
8182         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8183             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8184                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8185                 return 0;
8186         }
8187
8188         if (params->feature_config_flags &
8189             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8190                 /* Use specific phy request */
8191                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8192         } else if (params->feature_config_flags &
8193                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8194                 /* Use first phy request only in case of non-dual media*/
8195                 if (DUAL_MEDIA(params)) {
8196                         DP(NETIF_MSG_LINK,
8197                            "FW does not support OPT MDL verification\n");
8198                         return -EINVAL;
8199                 }
8200                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8201         } else {
8202                 /* No support in OPT MDL detection */
8203                 DP(NETIF_MSG_LINK,
8204                    "FW does not support OPT MDL verification\n");
8205                 return -EINVAL;
8206         }
8207
8208         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8209         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8210         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8211                 DP(NETIF_MSG_LINK, "Approved module\n");
8212                 return 0;
8213         }
8214
8215         /* Format the warning message */
8216         if (bnx2x_read_sfp_module_eeprom(phy,
8217                                          params,
8218                                          I2C_DEV_ADDR_A0,
8219                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8220                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8221                                          (u8 *)vendor_name))
8222                 vendor_name[0] = '\0';
8223         else
8224                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8225         if (bnx2x_read_sfp_module_eeprom(phy,
8226                                          params,
8227                                          I2C_DEV_ADDR_A0,
8228                                          SFP_EEPROM_PART_NO_ADDR,
8229                                          SFP_EEPROM_PART_NO_SIZE,
8230                                          (u8 *)vendor_pn))
8231                 vendor_pn[0] = '\0';
8232         else
8233                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8234
8235         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8236                               " Port %d from %s part number %s\n",
8237                          params->port, vendor_name, vendor_pn);
8238         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8239             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8240                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8241         return -EINVAL;
8242 }
8243
8244 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8245                                                  struct link_params *params)
8246
8247 {
8248         u8 val;
8249         int rc;
8250         struct bnx2x *bp = params->bp;
8251         u16 timeout;
8252         /* Initialization time after hot-plug may take up to 300ms for
8253          * some phys type ( e.g. JDSU )
8254          */
8255
8256         for (timeout = 0; timeout < 60; timeout++) {
8257                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8258                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8259                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8260                                 1);
8261                 else
8262                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8263                                                           I2C_DEV_ADDR_A0,
8264                                                           1, 1, &val);
8265                 if (rc == 0) {
8266                         DP(NETIF_MSG_LINK,
8267                            "SFP+ module initialization took %d ms\n",
8268                            timeout * 5);
8269                         return 0;
8270                 }
8271                 usleep_range(5000, 10000);
8272         }
8273         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8274                                           1, 1, &val);
8275         return rc;
8276 }
8277
8278 static void bnx2x_8727_power_module(struct bnx2x *bp,
8279                                     struct bnx2x_phy *phy,
8280                                     u8 is_power_up) {
8281         /* Make sure GPIOs are not using for LED mode */
8282         u16 val;
8283         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8284          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8285          * output
8286          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8287          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8288          * where the 1st bit is the over-current(only input), and 2nd bit is
8289          * for power( only output )
8290          *
8291          * In case of NOC feature is disabled and power is up, set GPIO control
8292          *  as input to enable listening of over-current indication
8293          */
8294         if (phy->flags & FLAGS_NOC)
8295                 return;
8296         if (is_power_up)
8297                 val = (1<<4);
8298         else
8299                 /* Set GPIO control to OUTPUT, and set the power bit
8300                  * to according to the is_power_up
8301                  */
8302                 val = (1<<1);
8303
8304         bnx2x_cl45_write(bp, phy,
8305                          MDIO_PMA_DEVAD,
8306                          MDIO_PMA_REG_8727_GPIO_CTRL,
8307                          val);
8308 }
8309
8310 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8311                                         struct bnx2x_phy *phy,
8312                                         u16 edc_mode)
8313 {
8314         u16 cur_limiting_mode;
8315
8316         bnx2x_cl45_read(bp, phy,
8317                         MDIO_PMA_DEVAD,
8318                         MDIO_PMA_REG_ROM_VER2,
8319                         &cur_limiting_mode);
8320         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8321                  cur_limiting_mode);
8322
8323         if (edc_mode == EDC_MODE_LIMITING) {
8324                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8325                 bnx2x_cl45_write(bp, phy,
8326                                  MDIO_PMA_DEVAD,
8327                                  MDIO_PMA_REG_ROM_VER2,
8328                                  EDC_MODE_LIMITING);
8329         } else { /* LRM mode ( default )*/
8330
8331                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8332
8333                 /* Changing to LRM mode takes quite few seconds. So do it only
8334                  * if current mode is limiting (default is LRM)
8335                  */
8336                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8337                         return 0;
8338
8339                 bnx2x_cl45_write(bp, phy,
8340                                  MDIO_PMA_DEVAD,
8341                                  MDIO_PMA_REG_LRM_MODE,
8342                                  0);
8343                 bnx2x_cl45_write(bp, phy,
8344                                  MDIO_PMA_DEVAD,
8345                                  MDIO_PMA_REG_ROM_VER2,
8346                                  0x128);
8347                 bnx2x_cl45_write(bp, phy,
8348                                  MDIO_PMA_DEVAD,
8349                                  MDIO_PMA_REG_MISC_CTRL0,
8350                                  0x4008);
8351                 bnx2x_cl45_write(bp, phy,
8352                                  MDIO_PMA_DEVAD,
8353                                  MDIO_PMA_REG_LRM_MODE,
8354                                  0xaaaa);
8355         }
8356         return 0;
8357 }
8358
8359 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8360                                         struct bnx2x_phy *phy,
8361                                         u16 edc_mode)
8362 {
8363         u16 phy_identifier;
8364         u16 rom_ver2_val;
8365         bnx2x_cl45_read(bp, phy,
8366                         MDIO_PMA_DEVAD,
8367                         MDIO_PMA_REG_PHY_IDENTIFIER,
8368                         &phy_identifier);
8369
8370         bnx2x_cl45_write(bp, phy,
8371                          MDIO_PMA_DEVAD,
8372                          MDIO_PMA_REG_PHY_IDENTIFIER,
8373                          (phy_identifier & ~(1<<9)));
8374
8375         bnx2x_cl45_read(bp, phy,
8376                         MDIO_PMA_DEVAD,
8377                         MDIO_PMA_REG_ROM_VER2,
8378                         &rom_ver2_val);
8379         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8380         bnx2x_cl45_write(bp, phy,
8381                          MDIO_PMA_DEVAD,
8382                          MDIO_PMA_REG_ROM_VER2,
8383                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8384
8385         bnx2x_cl45_write(bp, phy,
8386                          MDIO_PMA_DEVAD,
8387                          MDIO_PMA_REG_PHY_IDENTIFIER,
8388                          (phy_identifier | (1<<9)));
8389
8390         return 0;
8391 }
8392
8393 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8394                                      struct link_params *params,
8395                                      u32 action)
8396 {
8397         struct bnx2x *bp = params->bp;
8398         u16 val;
8399         switch (action) {
8400         case DISABLE_TX:
8401                 bnx2x_sfp_set_transmitter(params, phy, 0);
8402                 break;
8403         case ENABLE_TX:
8404                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8405                         bnx2x_sfp_set_transmitter(params, phy, 1);
8406                 break;
8407         case PHY_INIT:
8408                 bnx2x_cl45_write(bp, phy,
8409                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8410                                  (1<<2) | (1<<5));
8411                 bnx2x_cl45_write(bp, phy,
8412                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8413                                  0);
8414                 bnx2x_cl45_write(bp, phy,
8415                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8416                 /* Make MOD_ABS give interrupt on change */
8417                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8418                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8419                                 &val);
8420                 val |= (1<<12);
8421                 if (phy->flags & FLAGS_NOC)
8422                         val |= (3<<5);
8423                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8424                  * status which reflect SFP+ module over-current
8425                  */
8426                 if (!(phy->flags & FLAGS_NOC))
8427                         val &= 0xff8f; /* Reset bits 4-6 */
8428                 bnx2x_cl45_write(bp, phy,
8429                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8430                                  val);
8431                 break;
8432         default:
8433                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8434                    action);
8435                 return;
8436         }
8437 }
8438
8439 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8440                                            u8 gpio_mode)
8441 {
8442         struct bnx2x *bp = params->bp;
8443
8444         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8445                             offsetof(struct shmem_region,
8446                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8447                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8448         switch (fault_led_gpio) {
8449         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8450                 return;
8451         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8452         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8453         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8454         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8455         {
8456                 u8 gpio_port = bnx2x_get_gpio_port(params);
8457                 u16 gpio_pin = fault_led_gpio -
8458                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8459                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8460                                    "pin %x port %x mode %x\n",
8461                                gpio_pin, gpio_port, gpio_mode);
8462                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8463         }
8464         break;
8465         default:
8466                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8467                                fault_led_gpio);
8468         }
8469 }
8470
8471 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8472                                           u8 gpio_mode)
8473 {
8474         u32 pin_cfg;
8475         u8 port = params->port;
8476         struct bnx2x *bp = params->bp;
8477         pin_cfg = (REG_RD(bp, params->shmem_base +
8478                          offsetof(struct shmem_region,
8479                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8480                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8481                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8482         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8483                        gpio_mode, pin_cfg);
8484         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8485 }
8486
8487 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8488                                            u8 gpio_mode)
8489 {
8490         struct bnx2x *bp = params->bp;
8491         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8492         if (CHIP_IS_E3(bp)) {
8493                 /* Low ==> if SFP+ module is supported otherwise
8494                  * High ==> if SFP+ module is not on the approved vendor list
8495                  */
8496                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8497         } else
8498                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8499 }
8500
8501 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8502                                     struct link_params *params)
8503 {
8504         struct bnx2x *bp = params->bp;
8505         bnx2x_warpcore_power_module(params, 0);
8506         /* Put Warpcore in low power mode */
8507         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8508
8509         /* Put LCPLL in low power mode */
8510         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8511         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8512         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8513 }
8514
8515 static void bnx2x_power_sfp_module(struct link_params *params,
8516                                    struct bnx2x_phy *phy,
8517                                    u8 power)
8518 {
8519         struct bnx2x *bp = params->bp;
8520         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8521
8522         switch (phy->type) {
8523         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8524         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8525                 bnx2x_8727_power_module(params->bp, phy, power);
8526                 break;
8527         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8528                 bnx2x_warpcore_power_module(params, power);
8529                 break;
8530         default:
8531                 break;
8532         }
8533 }
8534 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8535                                              struct bnx2x_phy *phy,
8536                                              u16 edc_mode)
8537 {
8538         u16 val = 0;
8539         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8540         struct bnx2x *bp = params->bp;
8541
8542         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8543         /* This is a global register which controls all lanes */
8544         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8545                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8546         val &= ~(0xf << (lane << 2));
8547
8548         switch (edc_mode) {
8549         case EDC_MODE_LINEAR:
8550         case EDC_MODE_LIMITING:
8551                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8552                 break;
8553         case EDC_MODE_PASSIVE_DAC:
8554                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8555                 break;
8556         default:
8557                 break;
8558         }
8559
8560         val |= (mode << (lane << 2));
8561         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8562                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8563         /* A must read */
8564         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8565                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8566
8567         /* Restart microcode to re-read the new mode */
8568         bnx2x_warpcore_reset_lane(bp, phy, 1);
8569         bnx2x_warpcore_reset_lane(bp, phy, 0);
8570
8571 }
8572
8573 static void bnx2x_set_limiting_mode(struct link_params *params,
8574                                     struct bnx2x_phy *phy,
8575                                     u16 edc_mode)
8576 {
8577         switch (phy->type) {
8578         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8579                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8580                 break;
8581         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8582         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8583                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8584                 break;
8585         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8586                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8587                 break;
8588         }
8589 }
8590
8591 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8592                                struct link_params *params)
8593 {
8594         struct bnx2x *bp = params->bp;
8595         u16 edc_mode;
8596         int rc = 0;
8597
8598         u32 val = REG_RD(bp, params->shmem_base +
8599                              offsetof(struct shmem_region, dev_info.
8600                                      port_feature_config[params->port].config));
8601         /* Enabled transmitter by default */
8602         bnx2x_sfp_set_transmitter(params, phy, 1);
8603         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8604                  params->port);
8605         /* Power up module */
8606         bnx2x_power_sfp_module(params, phy, 1);
8607         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8608                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8609                 return -EINVAL;
8610         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8611                 /* Check SFP+ module compatibility */
8612                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8613                 rc = -EINVAL;
8614                 /* Turn on fault module-detected led */
8615                 bnx2x_set_sfp_module_fault_led(params,
8616                                                MISC_REGISTERS_GPIO_HIGH);
8617
8618                 /* Check if need to power down the SFP+ module */
8619                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8620                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8621                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8622                         bnx2x_power_sfp_module(params, phy, 0);
8623                         return rc;
8624                 }
8625         } else {
8626                 /* Turn off fault module-detected led */
8627                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8628         }
8629
8630         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8631          * is done automatically
8632          */
8633         bnx2x_set_limiting_mode(params, phy, edc_mode);
8634
8635         /* Disable transmit for this module if the module is not approved, and
8636          * laser needs to be disabled.
8637          */
8638         if ((rc) &&
8639             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8640              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8641                 bnx2x_sfp_set_transmitter(params, phy, 0);
8642
8643         return rc;
8644 }
8645
8646 void bnx2x_handle_module_detect_int(struct link_params *params)
8647 {
8648         struct bnx2x *bp = params->bp;
8649         struct bnx2x_phy *phy;
8650         u32 gpio_val;
8651         u8 gpio_num, gpio_port;
8652         if (CHIP_IS_E3(bp)) {
8653                 phy = &params->phy[INT_PHY];
8654                 /* Always enable TX laser,will be disabled in case of fault */
8655                 bnx2x_sfp_set_transmitter(params, phy, 1);
8656         } else {
8657                 phy = &params->phy[EXT_PHY1];
8658         }
8659         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8660                                       params->port, &gpio_num, &gpio_port) ==
8661             -EINVAL) {
8662                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8663                 return;
8664         }
8665
8666         /* Set valid module led off */
8667         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8668
8669         /* Get current gpio val reflecting module plugged in / out*/
8670         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8671
8672         /* Call the handling function in case module is detected */
8673         if (gpio_val == 0) {
8674                 bnx2x_set_mdio_emac_per_phy(bp, params);
8675                 bnx2x_set_aer_mmd(params, phy);
8676
8677                 bnx2x_power_sfp_module(params, phy, 1);
8678                 bnx2x_set_gpio_int(bp, gpio_num,
8679                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8680                                    gpio_port);
8681                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8682                         bnx2x_sfp_module_detection(phy, params);
8683                         if (CHIP_IS_E3(bp)) {
8684                                 u16 rx_tx_in_reset;
8685                                 /* In case WC is out of reset, reconfigure the
8686                                  * link speed while taking into account 1G
8687                                  * module limitation.
8688                                  */
8689                                 bnx2x_cl45_read(bp, phy,
8690                                                 MDIO_WC_DEVAD,
8691                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8692                                                 &rx_tx_in_reset);
8693                                 if ((!rx_tx_in_reset) &&
8694                                     (params->link_flags &
8695                                      PHY_INITIALIZED)) {
8696                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8697                                         bnx2x_warpcore_config_sfi(phy, params);
8698                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8699                                 }
8700                         }
8701                 } else {
8702                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8703                 }
8704         } else {
8705                 bnx2x_set_gpio_int(bp, gpio_num,
8706                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8707                                    gpio_port);
8708                 /* Module was plugged out.
8709                  * Disable transmit for this module
8710                  */
8711                 phy->media_type = ETH_PHY_NOT_PRESENT;
8712         }
8713 }
8714
8715 /******************************************************************/
8716 /*              Used by 8706 and 8727                             */
8717 /******************************************************************/
8718 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8719                                  struct bnx2x_phy *phy,
8720                                  u16 alarm_status_offset,
8721                                  u16 alarm_ctrl_offset)
8722 {
8723         u16 alarm_status, val;
8724         bnx2x_cl45_read(bp, phy,
8725                         MDIO_PMA_DEVAD, alarm_status_offset,
8726                         &alarm_status);
8727         bnx2x_cl45_read(bp, phy,
8728                         MDIO_PMA_DEVAD, alarm_status_offset,
8729                         &alarm_status);
8730         /* Mask or enable the fault event. */
8731         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8732         if (alarm_status & (1<<0))
8733                 val &= ~(1<<0);
8734         else
8735                 val |= (1<<0);
8736         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8737 }
8738 /******************************************************************/
8739 /*              common BCM8706/BCM8726 PHY SECTION                */
8740 /******************************************************************/
8741 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8742                                       struct link_params *params,
8743                                       struct link_vars *vars)
8744 {
8745         u8 link_up = 0;
8746         u16 val1, val2, rx_sd, pcs_status;
8747         struct bnx2x *bp = params->bp;
8748         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8749         /* Clear RX Alarm*/
8750         bnx2x_cl45_read(bp, phy,
8751                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8752
8753         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8754                              MDIO_PMA_LASI_TXCTRL);
8755
8756         /* Clear LASI indication*/
8757         bnx2x_cl45_read(bp, phy,
8758                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8759         bnx2x_cl45_read(bp, phy,
8760                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8761         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8762
8763         bnx2x_cl45_read(bp, phy,
8764                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8765         bnx2x_cl45_read(bp, phy,
8766                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8767         bnx2x_cl45_read(bp, phy,
8768                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8769         bnx2x_cl45_read(bp, phy,
8770                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8771
8772         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8773                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8774         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8775          * are set, or if the autoneg bit 1 is set
8776          */
8777         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8778         if (link_up) {
8779                 if (val2 & (1<<1))
8780                         vars->line_speed = SPEED_1000;
8781                 else
8782                         vars->line_speed = SPEED_10000;
8783                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8784                 vars->duplex = DUPLEX_FULL;
8785         }
8786
8787         /* Capture 10G link fault. Read twice to clear stale value. */
8788         if (vars->line_speed == SPEED_10000) {
8789                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8790                             MDIO_PMA_LASI_TXSTAT, &val1);
8791                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8792                             MDIO_PMA_LASI_TXSTAT, &val1);
8793                 if (val1 & (1<<0))
8794                         vars->fault_detected = 1;
8795         }
8796
8797         return link_up;
8798 }
8799
8800 /******************************************************************/
8801 /*                      BCM8706 PHY SECTION                       */
8802 /******************************************************************/
8803 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8804                                  struct link_params *params,
8805                                  struct link_vars *vars)
8806 {
8807         u32 tx_en_mode;
8808         u16 cnt, val, tmp1;
8809         struct bnx2x *bp = params->bp;
8810
8811         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8812                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8813         /* HW reset */
8814         bnx2x_ext_phy_hw_reset(bp, params->port);
8815         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8816         bnx2x_wait_reset_complete(bp, phy, params);
8817
8818         /* Wait until fw is loaded */
8819         for (cnt = 0; cnt < 100; cnt++) {
8820                 bnx2x_cl45_read(bp, phy,
8821                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8822                 if (val)
8823                         break;
8824                 usleep_range(10000, 20000);
8825         }
8826         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8827         if ((params->feature_config_flags &
8828              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8829                 u8 i;
8830                 u16 reg;
8831                 for (i = 0; i < 4; i++) {
8832                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8833                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8834                                    MDIO_XS_8706_REG_BANK_RX0);
8835                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8836                         /* Clear first 3 bits of the control */
8837                         val &= ~0x7;
8838                         /* Set control bits according to configuration */
8839                         val |= (phy->rx_preemphasis[i] & 0x7);
8840                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8841                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8842                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8843                 }
8844         }
8845         /* Force speed */
8846         if (phy->req_line_speed == SPEED_10000) {
8847                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8848
8849                 bnx2x_cl45_write(bp, phy,
8850                                  MDIO_PMA_DEVAD,
8851                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8852                 bnx2x_cl45_write(bp, phy,
8853                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8854                                  0);
8855                 /* Arm LASI for link and Tx fault. */
8856                 bnx2x_cl45_write(bp, phy,
8857                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8858         } else {
8859                 /* Force 1Gbps using autoneg with 1G advertisement */
8860
8861                 /* Allow CL37 through CL73 */
8862                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8863                 bnx2x_cl45_write(bp, phy,
8864                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8865
8866                 /* Enable Full-Duplex advertisement on CL37 */
8867                 bnx2x_cl45_write(bp, phy,
8868                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8869                 /* Enable CL37 AN */
8870                 bnx2x_cl45_write(bp, phy,
8871                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8872                 /* 1G support */
8873                 bnx2x_cl45_write(bp, phy,
8874                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8875
8876                 /* Enable clause 73 AN */
8877                 bnx2x_cl45_write(bp, phy,
8878                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8879                 bnx2x_cl45_write(bp, phy,
8880                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8881                                  0x0400);
8882                 bnx2x_cl45_write(bp, phy,
8883                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8884                                  0x0004);
8885         }
8886         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8887
8888         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8889          * power mode, if TX Laser is disabled
8890          */
8891
8892         tx_en_mode = REG_RD(bp, params->shmem_base +
8893                             offsetof(struct shmem_region,
8894                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8895                         & PORT_HW_CFG_TX_LASER_MASK;
8896
8897         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8898                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8899                 bnx2x_cl45_read(bp, phy,
8900                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8901                 tmp1 |= 0x1;
8902                 bnx2x_cl45_write(bp, phy,
8903                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8904         }
8905
8906         return 0;
8907 }
8908
8909 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8910                                   struct link_params *params,
8911                                   struct link_vars *vars)
8912 {
8913         return bnx2x_8706_8726_read_status(phy, params, vars);
8914 }
8915
8916 /******************************************************************/
8917 /*                      BCM8726 PHY SECTION                       */
8918 /******************************************************************/
8919 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8920                                        struct link_params *params)
8921 {
8922         struct bnx2x *bp = params->bp;
8923         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8924         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8925 }
8926
8927 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8928                                          struct link_params *params)
8929 {
8930         struct bnx2x *bp = params->bp;
8931         /* Need to wait 100ms after reset */
8932         msleep(100);
8933
8934         /* Micro controller re-boot */
8935         bnx2x_cl45_write(bp, phy,
8936                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8937
8938         /* Set soft reset */
8939         bnx2x_cl45_write(bp, phy,
8940                          MDIO_PMA_DEVAD,
8941                          MDIO_PMA_REG_GEN_CTRL,
8942                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8943
8944         bnx2x_cl45_write(bp, phy,
8945                          MDIO_PMA_DEVAD,
8946                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8947
8948         bnx2x_cl45_write(bp, phy,
8949                          MDIO_PMA_DEVAD,
8950                          MDIO_PMA_REG_GEN_CTRL,
8951                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8952
8953         /* Wait for 150ms for microcode load */
8954         msleep(150);
8955
8956         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8957         bnx2x_cl45_write(bp, phy,
8958                          MDIO_PMA_DEVAD,
8959                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8960
8961         msleep(200);
8962         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8963 }
8964
8965 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8966                                  struct link_params *params,
8967                                  struct link_vars *vars)
8968 {
8969         struct bnx2x *bp = params->bp;
8970         u16 val1;
8971         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8972         if (link_up) {
8973                 bnx2x_cl45_read(bp, phy,
8974                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8975                                 &val1);
8976                 if (val1 & (1<<15)) {
8977                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8978                         link_up = 0;
8979                         vars->line_speed = 0;
8980                 }
8981         }
8982         return link_up;
8983 }
8984
8985
8986 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8987                                   struct link_params *params,
8988                                   struct link_vars *vars)
8989 {
8990         struct bnx2x *bp = params->bp;
8991         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8992
8993         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8994         bnx2x_wait_reset_complete(bp, phy, params);
8995
8996         bnx2x_8726_external_rom_boot(phy, params);
8997
8998         /* Need to call module detected on initialization since the module
8999          * detection triggered by actual module insertion might occur before
9000          * driver is loaded, and when driver is loaded, it reset all
9001          * registers, including the transmitter
9002          */
9003         bnx2x_sfp_module_detection(phy, params);
9004
9005         if (phy->req_line_speed == SPEED_1000) {
9006                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9007                 bnx2x_cl45_write(bp, phy,
9008                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9009                 bnx2x_cl45_write(bp, phy,
9010                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9011                 bnx2x_cl45_write(bp, phy,
9012                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9013                 bnx2x_cl45_write(bp, phy,
9014                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9015                                  0x400);
9016         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9017                    (phy->speed_cap_mask &
9018                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9019                    ((phy->speed_cap_mask &
9020                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9021                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9022                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9023                 /* Set Flow control */
9024                 bnx2x_ext_phy_set_pause(params, phy, vars);
9025                 bnx2x_cl45_write(bp, phy,
9026                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9027                 bnx2x_cl45_write(bp, phy,
9028                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9029                 bnx2x_cl45_write(bp, phy,
9030                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9031                 bnx2x_cl45_write(bp, phy,
9032                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9033                 bnx2x_cl45_write(bp, phy,
9034                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9035                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9036                  * change
9037                  */
9038                 bnx2x_cl45_write(bp, phy,
9039                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9040                 bnx2x_cl45_write(bp, phy,
9041                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9042                                  0x400);
9043
9044         } else { /* Default 10G. Set only LASI control */
9045                 bnx2x_cl45_write(bp, phy,
9046                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9047         }
9048
9049         /* Set TX PreEmphasis if needed */
9050         if ((params->feature_config_flags &
9051              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9052                 DP(NETIF_MSG_LINK,
9053                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9054                          phy->tx_preemphasis[0],
9055                          phy->tx_preemphasis[1]);
9056                 bnx2x_cl45_write(bp, phy,
9057                                  MDIO_PMA_DEVAD,
9058                                  MDIO_PMA_REG_8726_TX_CTRL1,
9059                                  phy->tx_preemphasis[0]);
9060
9061                 bnx2x_cl45_write(bp, phy,
9062                                  MDIO_PMA_DEVAD,
9063                                  MDIO_PMA_REG_8726_TX_CTRL2,
9064                                  phy->tx_preemphasis[1]);
9065         }
9066
9067         return 0;
9068
9069 }
9070
9071 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9072                                   struct link_params *params)
9073 {
9074         struct bnx2x *bp = params->bp;
9075         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9076         /* Set serial boot control for external load */
9077         bnx2x_cl45_write(bp, phy,
9078                          MDIO_PMA_DEVAD,
9079                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9080 }
9081
9082 /******************************************************************/
9083 /*                      BCM8727 PHY SECTION                       */
9084 /******************************************************************/
9085
9086 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9087                                     struct link_params *params, u8 mode)
9088 {
9089         struct bnx2x *bp = params->bp;
9090         u16 led_mode_bitmask = 0;
9091         u16 gpio_pins_bitmask = 0;
9092         u16 val;
9093         /* Only NOC flavor requires to set the LED specifically */
9094         if (!(phy->flags & FLAGS_NOC))
9095                 return;
9096         switch (mode) {
9097         case LED_MODE_FRONT_PANEL_OFF:
9098         case LED_MODE_OFF:
9099                 led_mode_bitmask = 0;
9100                 gpio_pins_bitmask = 0x03;
9101                 break;
9102         case LED_MODE_ON:
9103                 led_mode_bitmask = 0;
9104                 gpio_pins_bitmask = 0x02;
9105                 break;
9106         case LED_MODE_OPER:
9107                 led_mode_bitmask = 0x60;
9108                 gpio_pins_bitmask = 0x11;
9109                 break;
9110         }
9111         bnx2x_cl45_read(bp, phy,
9112                         MDIO_PMA_DEVAD,
9113                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9114                         &val);
9115         val &= 0xff8f;
9116         val |= led_mode_bitmask;
9117         bnx2x_cl45_write(bp, phy,
9118                          MDIO_PMA_DEVAD,
9119                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9120                          val);
9121         bnx2x_cl45_read(bp, phy,
9122                         MDIO_PMA_DEVAD,
9123                         MDIO_PMA_REG_8727_GPIO_CTRL,
9124                         &val);
9125         val &= 0xffe0;
9126         val |= gpio_pins_bitmask;
9127         bnx2x_cl45_write(bp, phy,
9128                          MDIO_PMA_DEVAD,
9129                          MDIO_PMA_REG_8727_GPIO_CTRL,
9130                          val);
9131 }
9132 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9133                                 struct link_params *params) {
9134         u32 swap_val, swap_override;
9135         u8 port;
9136         /* The PHY reset is controlled by GPIO 1. Fake the port number
9137          * to cancel the swap done in set_gpio()
9138          */
9139         struct bnx2x *bp = params->bp;
9140         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9141         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9142         port = (swap_val && swap_override) ^ 1;
9143         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9144                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9145 }
9146
9147 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9148                                     struct link_params *params)
9149 {
9150         struct bnx2x *bp = params->bp;
9151         u16 tmp1, val;
9152         /* Set option 1G speed */
9153         if ((phy->req_line_speed == SPEED_1000) ||
9154             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9155                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9156                 bnx2x_cl45_write(bp, phy,
9157                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9158                 bnx2x_cl45_write(bp, phy,
9159                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9160                 bnx2x_cl45_read(bp, phy,
9161                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9162                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9163                 /* Power down the XAUI until link is up in case of dual-media
9164                  * and 1G
9165                  */
9166                 if (DUAL_MEDIA(params)) {
9167                         bnx2x_cl45_read(bp, phy,
9168                                         MDIO_PMA_DEVAD,
9169                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9170                         val |= (3<<10);
9171                         bnx2x_cl45_write(bp, phy,
9172                                          MDIO_PMA_DEVAD,
9173                                          MDIO_PMA_REG_8727_PCS_GP, val);
9174                 }
9175         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9176                    ((phy->speed_cap_mask &
9177                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9178                    ((phy->speed_cap_mask &
9179                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9180                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9181
9182                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9183                 bnx2x_cl45_write(bp, phy,
9184                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9185                 bnx2x_cl45_write(bp, phy,
9186                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9187         } else {
9188                 /* Since the 8727 has only single reset pin, need to set the 10G
9189                  * registers although it is default
9190                  */
9191                 bnx2x_cl45_write(bp, phy,
9192                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9193                                  0x0020);
9194                 bnx2x_cl45_write(bp, phy,
9195                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9196                 bnx2x_cl45_write(bp, phy,
9197                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9198                 bnx2x_cl45_write(bp, phy,
9199                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9200                                  0x0008);
9201         }
9202 }
9203
9204 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9205                                   struct link_params *params,
9206                                   struct link_vars *vars)
9207 {
9208         u32 tx_en_mode;
9209         u16 tmp1, mod_abs, tmp2;
9210         struct bnx2x *bp = params->bp;
9211         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9212
9213         bnx2x_wait_reset_complete(bp, phy, params);
9214
9215         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9216
9217         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9218         /* Initially configure MOD_ABS to interrupt when module is
9219          * presence( bit 8)
9220          */
9221         bnx2x_cl45_read(bp, phy,
9222                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9223         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9224          * When the EDC is off it locks onto a reference clock and avoids
9225          * becoming 'lost'
9226          */
9227         mod_abs &= ~(1<<8);
9228         if (!(phy->flags & FLAGS_NOC))
9229                 mod_abs &= ~(1<<9);
9230         bnx2x_cl45_write(bp, phy,
9231                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9232
9233         /* Enable/Disable PHY transmitter output */
9234         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9235
9236         bnx2x_8727_power_module(bp, phy, 1);
9237
9238         bnx2x_cl45_read(bp, phy,
9239                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9240
9241         bnx2x_cl45_read(bp, phy,
9242                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9243
9244         bnx2x_8727_config_speed(phy, params);
9245
9246
9247         /* Set TX PreEmphasis if needed */
9248         if ((params->feature_config_flags &
9249              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9250                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9251                            phy->tx_preemphasis[0],
9252                            phy->tx_preemphasis[1]);
9253                 bnx2x_cl45_write(bp, phy,
9254                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9255                                  phy->tx_preemphasis[0]);
9256
9257                 bnx2x_cl45_write(bp, phy,
9258                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9259                                  phy->tx_preemphasis[1]);
9260         }
9261
9262         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9263          * power mode, if TX Laser is disabled
9264          */
9265         tx_en_mode = REG_RD(bp, params->shmem_base +
9266                             offsetof(struct shmem_region,
9267                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9268                         & PORT_HW_CFG_TX_LASER_MASK;
9269
9270         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9271
9272                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9273                 bnx2x_cl45_read(bp, phy,
9274                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9275                 tmp2 |= 0x1000;
9276                 tmp2 &= 0xFFEF;
9277                 bnx2x_cl45_write(bp, phy,
9278                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9279                 bnx2x_cl45_read(bp, phy,
9280                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9281                                 &tmp2);
9282                 bnx2x_cl45_write(bp, phy,
9283                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9284                                  (tmp2 & 0x7fff));
9285         }
9286
9287         return 0;
9288 }
9289
9290 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9291                                       struct link_params *params)
9292 {
9293         struct bnx2x *bp = params->bp;
9294         u16 mod_abs, rx_alarm_status;
9295         u32 val = REG_RD(bp, params->shmem_base +
9296                              offsetof(struct shmem_region, dev_info.
9297                                       port_feature_config[params->port].
9298                                       config));
9299         bnx2x_cl45_read(bp, phy,
9300                         MDIO_PMA_DEVAD,
9301                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9302         if (mod_abs & (1<<8)) {
9303
9304                 /* Module is absent */
9305                 DP(NETIF_MSG_LINK,
9306                    "MOD_ABS indication show module is absent\n");
9307                 phy->media_type = ETH_PHY_NOT_PRESENT;
9308                 /* 1. Set mod_abs to detect next module
9309                  *    presence event
9310                  * 2. Set EDC off by setting OPTXLOS signal input to low
9311                  *    (bit 9).
9312                  *    When the EDC is off it locks onto a reference clock and
9313                  *    avoids becoming 'lost'.
9314                  */
9315                 mod_abs &= ~(1<<8);
9316                 if (!(phy->flags & FLAGS_NOC))
9317                         mod_abs &= ~(1<<9);
9318                 bnx2x_cl45_write(bp, phy,
9319                                  MDIO_PMA_DEVAD,
9320                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9321
9322                 /* Clear RX alarm since it stays up as long as
9323                  * the mod_abs wasn't changed
9324                  */
9325                 bnx2x_cl45_read(bp, phy,
9326                                 MDIO_PMA_DEVAD,
9327                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9328
9329         } else {
9330                 /* Module is present */
9331                 DP(NETIF_MSG_LINK,
9332                    "MOD_ABS indication show module is present\n");
9333                 /* First disable transmitter, and if the module is ok, the
9334                  * module_detection will enable it
9335                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9336                  * 2. Restore the default polarity of the OPRXLOS signal and
9337                  * this signal will then correctly indicate the presence or
9338                  * absence of the Rx signal. (bit 9)
9339                  */
9340                 mod_abs |= (1<<8);
9341                 if (!(phy->flags & FLAGS_NOC))
9342                         mod_abs |= (1<<9);
9343                 bnx2x_cl45_write(bp, phy,
9344                                  MDIO_PMA_DEVAD,
9345                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9346
9347                 /* Clear RX alarm since it stays up as long as the mod_abs
9348                  * wasn't changed. This is need to be done before calling the
9349                  * module detection, otherwise it will clear* the link update
9350                  * alarm
9351                  */
9352                 bnx2x_cl45_read(bp, phy,
9353                                 MDIO_PMA_DEVAD,
9354                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9355
9356
9357                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9358                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9359                         bnx2x_sfp_set_transmitter(params, phy, 0);
9360
9361                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9362                         bnx2x_sfp_module_detection(phy, params);
9363                 else
9364                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9365
9366                 /* Reconfigure link speed based on module type limitations */
9367                 bnx2x_8727_config_speed(phy, params);
9368         }
9369
9370         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9371                    rx_alarm_status);
9372         /* No need to check link status in case of module plugged in/out */
9373 }
9374
9375 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9376                                  struct link_params *params,
9377                                  struct link_vars *vars)
9378
9379 {
9380         struct bnx2x *bp = params->bp;
9381         u8 link_up = 0, oc_port = params->port;
9382         u16 link_status = 0;
9383         u16 rx_alarm_status, lasi_ctrl, val1;
9384
9385         /* If PHY is not initialized, do not check link status */
9386         bnx2x_cl45_read(bp, phy,
9387                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9388                         &lasi_ctrl);
9389         if (!lasi_ctrl)
9390                 return 0;
9391
9392         /* Check the LASI on Rx */
9393         bnx2x_cl45_read(bp, phy,
9394                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9395                         &rx_alarm_status);
9396         vars->line_speed = 0;
9397         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9398
9399         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9400                              MDIO_PMA_LASI_TXCTRL);
9401
9402         bnx2x_cl45_read(bp, phy,
9403                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9404
9405         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9406
9407         /* Clear MSG-OUT */
9408         bnx2x_cl45_read(bp, phy,
9409                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9410
9411         /* If a module is present and there is need to check
9412          * for over current
9413          */
9414         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9415                 /* Check over-current using 8727 GPIO0 input*/
9416                 bnx2x_cl45_read(bp, phy,
9417                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9418                                 &val1);
9419
9420                 if ((val1 & (1<<8)) == 0) {
9421                         if (!CHIP_IS_E1x(bp))
9422                                 oc_port = BP_PATH(bp) + (params->port << 1);
9423                         DP(NETIF_MSG_LINK,
9424                            "8727 Power fault has been detected on port %d\n",
9425                            oc_port);
9426                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9427                                             "been detected and the power to "
9428                                             "that SFP+ module has been removed "
9429                                             "to prevent failure of the card. "
9430                                             "Please remove the SFP+ module and "
9431                                             "restart the system to clear this "
9432                                             "error.\n",
9433                          oc_port);
9434                         /* Disable all RX_ALARMs except for mod_abs */
9435                         bnx2x_cl45_write(bp, phy,
9436                                          MDIO_PMA_DEVAD,
9437                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9438
9439                         bnx2x_cl45_read(bp, phy,
9440                                         MDIO_PMA_DEVAD,
9441                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9442                         /* Wait for module_absent_event */
9443                         val1 |= (1<<8);
9444                         bnx2x_cl45_write(bp, phy,
9445                                          MDIO_PMA_DEVAD,
9446                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9447                         /* Clear RX alarm */
9448                         bnx2x_cl45_read(bp, phy,
9449                                 MDIO_PMA_DEVAD,
9450                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9451                         bnx2x_8727_power_module(params->bp, phy, 0);
9452                         return 0;
9453                 }
9454         } /* Over current check */
9455
9456         /* When module absent bit is set, check module */
9457         if (rx_alarm_status & (1<<5)) {
9458                 bnx2x_8727_handle_mod_abs(phy, params);
9459                 /* Enable all mod_abs and link detection bits */
9460                 bnx2x_cl45_write(bp, phy,
9461                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9462                                  ((1<<5) | (1<<2)));
9463         }
9464
9465         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9466                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9467                 bnx2x_sfp_set_transmitter(params, phy, 1);
9468         } else {
9469                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9470                 return 0;
9471         }
9472
9473         bnx2x_cl45_read(bp, phy,
9474                         MDIO_PMA_DEVAD,
9475                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9476
9477         /* Bits 0..2 --> speed detected,
9478          * Bits 13..15--> link is down
9479          */
9480         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9481                 link_up = 1;
9482                 vars->line_speed = SPEED_10000;
9483                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9484                            params->port);
9485         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9486                 link_up = 1;
9487                 vars->line_speed = SPEED_1000;
9488                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9489                            params->port);
9490         } else {
9491                 link_up = 0;
9492                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9493                            params->port);
9494         }
9495
9496         /* Capture 10G link fault. */
9497         if (vars->line_speed == SPEED_10000) {
9498                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9499                             MDIO_PMA_LASI_TXSTAT, &val1);
9500
9501                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9502                             MDIO_PMA_LASI_TXSTAT, &val1);
9503
9504                 if (val1 & (1<<0)) {
9505                         vars->fault_detected = 1;
9506                 }
9507         }
9508
9509         if (link_up) {
9510                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9511                 vars->duplex = DUPLEX_FULL;
9512                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9513         }
9514
9515         if ((DUAL_MEDIA(params)) &&
9516             (phy->req_line_speed == SPEED_1000)) {
9517                 bnx2x_cl45_read(bp, phy,
9518                                 MDIO_PMA_DEVAD,
9519                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9520                 /* In case of dual-media board and 1G, power up the XAUI side,
9521                  * otherwise power it down. For 10G it is done automatically
9522                  */
9523                 if (link_up)
9524                         val1 &= ~(3<<10);
9525                 else
9526                         val1 |= (3<<10);
9527                 bnx2x_cl45_write(bp, phy,
9528                                  MDIO_PMA_DEVAD,
9529                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9530         }
9531         return link_up;
9532 }
9533
9534 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9535                                   struct link_params *params)
9536 {
9537         struct bnx2x *bp = params->bp;
9538
9539         /* Enable/Disable PHY transmitter output */
9540         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9541
9542         /* Disable Transmitter */
9543         bnx2x_sfp_set_transmitter(params, phy, 0);
9544         /* Clear LASI */
9545         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9546
9547 }
9548
9549 /******************************************************************/
9550 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9551 /******************************************************************/
9552 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9553                                             struct bnx2x *bp,
9554                                             u8 port)
9555 {
9556         u16 val, fw_ver2, cnt, i;
9557         static struct bnx2x_reg_set reg_set[] = {
9558                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9559                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9560                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9561                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9562                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9563         };
9564         u16 fw_ver1;
9565
9566         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9567             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9568                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9569                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9570                                 phy->ver_addr);
9571         } else {
9572                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9573                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9574                 for (i = 0; i < ARRAY_SIZE(reg_set);
9575                       i++)
9576                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9577                                          reg_set[i].reg, reg_set[i].val);
9578
9579                 for (cnt = 0; cnt < 100; cnt++) {
9580                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9581                         if (val & 1)
9582                                 break;
9583                         udelay(5);
9584                 }
9585                 if (cnt == 100) {
9586                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9587                                         "phy fw version(1)\n");
9588                         bnx2x_save_spirom_version(bp, port, 0,
9589                                                   phy->ver_addr);
9590                         return;
9591                 }
9592
9593
9594                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9595                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9596                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9597                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9598                 for (cnt = 0; cnt < 100; cnt++) {
9599                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9600                         if (val & 1)
9601                                 break;
9602                         udelay(5);
9603                 }
9604                 if (cnt == 100) {
9605                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9606                                         "version(2)\n");
9607                         bnx2x_save_spirom_version(bp, port, 0,
9608                                                   phy->ver_addr);
9609                         return;
9610                 }
9611
9612                 /* lower 16 bits of the register SPI_FW_STATUS */
9613                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9614                 /* upper 16 bits of register SPI_FW_STATUS */
9615                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9616
9617                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9618                                           phy->ver_addr);
9619         }
9620
9621 }
9622 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9623                                 struct bnx2x_phy *phy)
9624 {
9625         u16 val, offset, i;
9626         static struct bnx2x_reg_set reg_set[] = {
9627                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9628                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9629                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9630                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9631                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9632                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9633                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9634         };
9635         /* PHYC_CTL_LED_CTL */
9636         bnx2x_cl45_read(bp, phy,
9637                         MDIO_PMA_DEVAD,
9638                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9639         val &= 0xFE00;
9640         val |= 0x0092;
9641
9642         bnx2x_cl45_write(bp, phy,
9643                          MDIO_PMA_DEVAD,
9644                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9645
9646         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9647                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9648                                  reg_set[i].val);
9649
9650         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9651             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9652                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9653         else
9654                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9655
9656         /* stretch_en for LED3*/
9657         bnx2x_cl45_read_or_write(bp, phy,
9658                                  MDIO_PMA_DEVAD, offset,
9659                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9660 }
9661
9662 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9663                                       struct link_params *params,
9664                                       u32 action)
9665 {
9666         struct bnx2x *bp = params->bp;
9667         switch (action) {
9668         case PHY_INIT:
9669                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9670                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9671                         /* Save spirom version */
9672                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9673                 }
9674                 /* This phy uses the NIG latch mechanism since link indication
9675                  * arrives through its LED4 and not via its LASI signal, so we
9676                  * get steady signal instead of clear on read
9677                  */
9678                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9679                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9680
9681                 bnx2x_848xx_set_led(bp, phy);
9682                 break;
9683         }
9684 }
9685
9686 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9687                                        struct link_params *params,
9688                                        struct link_vars *vars)
9689 {
9690         struct bnx2x *bp = params->bp;
9691         u16 autoneg_val, an_1000_val, an_10_100_val;
9692
9693         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9694         bnx2x_cl45_write(bp, phy,
9695                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9696
9697         /* set 1000 speed advertisement */
9698         bnx2x_cl45_read(bp, phy,
9699                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9700                         &an_1000_val);
9701
9702         bnx2x_ext_phy_set_pause(params, phy, vars);
9703         bnx2x_cl45_read(bp, phy,
9704                         MDIO_AN_DEVAD,
9705                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9706                         &an_10_100_val);
9707         bnx2x_cl45_read(bp, phy,
9708                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9709                         &autoneg_val);
9710         /* Disable forced speed */
9711         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9712         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9713
9714         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9715              (phy->speed_cap_mask &
9716              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9717             (phy->req_line_speed == SPEED_1000)) {
9718                 an_1000_val |= (1<<8);
9719                 autoneg_val |= (1<<9 | 1<<12);
9720                 if (phy->req_duplex == DUPLEX_FULL)
9721                         an_1000_val |= (1<<9);
9722                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9723         } else
9724                 an_1000_val &= ~((1<<8) | (1<<9));
9725
9726         bnx2x_cl45_write(bp, phy,
9727                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9728                          an_1000_val);
9729
9730         /* set 100 speed advertisement */
9731         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9732              (phy->speed_cap_mask &
9733               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9734                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9735                 an_10_100_val |= (1<<7);
9736                 /* Enable autoneg and restart autoneg for legacy speeds */
9737                 autoneg_val |= (1<<9 | 1<<12);
9738
9739                 if (phy->req_duplex == DUPLEX_FULL)
9740                         an_10_100_val |= (1<<8);
9741                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9742         }
9743         /* set 10 speed advertisement */
9744         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9745              (phy->speed_cap_mask &
9746               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9747                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9748              (phy->supported &
9749               (SUPPORTED_10baseT_Half |
9750                SUPPORTED_10baseT_Full)))) {
9751                 an_10_100_val |= (1<<5);
9752                 autoneg_val |= (1<<9 | 1<<12);
9753                 if (phy->req_duplex == DUPLEX_FULL)
9754                         an_10_100_val |= (1<<6);
9755                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9756         }
9757
9758         /* Only 10/100 are allowed to work in FORCE mode */
9759         if ((phy->req_line_speed == SPEED_100) &&
9760             (phy->supported &
9761              (SUPPORTED_100baseT_Half |
9762               SUPPORTED_100baseT_Full))) {
9763                 autoneg_val |= (1<<13);
9764                 /* Enabled AUTO-MDIX when autoneg is disabled */
9765                 bnx2x_cl45_write(bp, phy,
9766                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9767                                  (1<<15 | 1<<9 | 7<<0));
9768                 /* The PHY needs this set even for forced link. */
9769                 an_10_100_val |= (1<<8) | (1<<7);
9770                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9771         }
9772         if ((phy->req_line_speed == SPEED_10) &&
9773             (phy->supported &
9774              (SUPPORTED_10baseT_Half |
9775               SUPPORTED_10baseT_Full))) {
9776                 /* Enabled AUTO-MDIX when autoneg is disabled */
9777                 bnx2x_cl45_write(bp, phy,
9778                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9779                                  (1<<15 | 1<<9 | 7<<0));
9780                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9781         }
9782
9783         bnx2x_cl45_write(bp, phy,
9784                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9785                          an_10_100_val);
9786
9787         if (phy->req_duplex == DUPLEX_FULL)
9788                 autoneg_val |= (1<<8);
9789
9790         /* Always write this if this is not 84833/4.
9791          * For 84833/4, write it only when it's a forced speed.
9792          */
9793         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9794              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9795             ((autoneg_val & (1<<12)) == 0))
9796                 bnx2x_cl45_write(bp, phy,
9797                          MDIO_AN_DEVAD,
9798                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9799
9800         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9801             (phy->speed_cap_mask &
9802              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9803                 (phy->req_line_speed == SPEED_10000)) {
9804                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9805                         /* Restart autoneg for 10G*/
9806
9807                         bnx2x_cl45_read_or_write(
9808                                 bp, phy,
9809                                 MDIO_AN_DEVAD,
9810                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9811                                 0x1000);
9812                         bnx2x_cl45_write(bp, phy,
9813                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9814                                          0x3200);
9815         } else
9816                 bnx2x_cl45_write(bp, phy,
9817                                  MDIO_AN_DEVAD,
9818                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9819                                  1);
9820
9821         return 0;
9822 }
9823
9824 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9825                                   struct link_params *params,
9826                                   struct link_vars *vars)
9827 {
9828         struct bnx2x *bp = params->bp;
9829         /* Restore normal power mode*/
9830         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9831                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9832
9833         /* HW reset */
9834         bnx2x_ext_phy_hw_reset(bp, params->port);
9835         bnx2x_wait_reset_complete(bp, phy, params);
9836
9837         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9838         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9839 }
9840
9841 #define PHY84833_CMDHDLR_WAIT 300
9842 #define PHY84833_CMDHDLR_MAX_ARGS 5
9843 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9844                                 struct link_params *params, u16 fw_cmd,
9845                                 u16 cmd_args[], int argc)
9846 {
9847         int idx;
9848         u16 val;
9849         struct bnx2x *bp = params->bp;
9850         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9851         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9852                         MDIO_84833_CMD_HDLR_STATUS,
9853                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9854         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9855                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9856                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9857                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9858                         break;
9859                 usleep_range(1000, 2000);
9860         }
9861         if (idx >= PHY84833_CMDHDLR_WAIT) {
9862                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9863                 return -EINVAL;
9864         }
9865
9866         /* Prepare argument(s) and issue command */
9867         for (idx = 0; idx < argc; idx++) {
9868                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9869                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9870                                 cmd_args[idx]);
9871         }
9872         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9873                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9874         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9875                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9876                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9877                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9878                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9879                         break;
9880                 usleep_range(1000, 2000);
9881         }
9882         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9883                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9884                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9885                 return -EINVAL;
9886         }
9887         /* Gather returning data */
9888         for (idx = 0; idx < argc; idx++) {
9889                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9890                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9891                                 &cmd_args[idx]);
9892         }
9893         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9894                         MDIO_84833_CMD_HDLR_STATUS,
9895                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9896         return 0;
9897 }
9898
9899 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9900                                    struct link_params *params,
9901                                    struct link_vars *vars)
9902 {
9903         u32 pair_swap;
9904         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9905         int status;
9906         struct bnx2x *bp = params->bp;
9907
9908         /* Check for configuration. */
9909         pair_swap = REG_RD(bp, params->shmem_base +
9910                            offsetof(struct shmem_region,
9911                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9912                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9913
9914         if (pair_swap == 0)
9915                 return 0;
9916
9917         /* Only the second argument is used for this command */
9918         data[1] = (u16)pair_swap;
9919
9920         status = bnx2x_84833_cmd_hdlr(phy, params,
9921                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9922         if (status == 0)
9923                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9924
9925         return status;
9926 }
9927
9928 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9929                                       u32 shmem_base_path[],
9930                                       u32 chip_id)
9931 {
9932         u32 reset_pin[2];
9933         u32 idx;
9934         u8 reset_gpios;
9935         if (CHIP_IS_E3(bp)) {
9936                 /* Assume that these will be GPIOs, not EPIOs. */
9937                 for (idx = 0; idx < 2; idx++) {
9938                         /* Map config param to register bit. */
9939                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9940                                 offsetof(struct shmem_region,
9941                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9942                         reset_pin[idx] = (reset_pin[idx] &
9943                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9944                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9945                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9946                         reset_pin[idx] = (1 << reset_pin[idx]);
9947                 }
9948                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9949         } else {
9950                 /* E2, look from diff place of shmem. */
9951                 for (idx = 0; idx < 2; idx++) {
9952                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9953                                 offsetof(struct shmem_region,
9954                                 dev_info.port_hw_config[0].default_cfg));
9955                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9956                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9957                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9958                         reset_pin[idx] = (1 << reset_pin[idx]);
9959                 }
9960                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9961         }
9962
9963         return reset_gpios;
9964 }
9965
9966 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9967                                 struct link_params *params)
9968 {
9969         struct bnx2x *bp = params->bp;
9970         u8 reset_gpios;
9971         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9972                                 offsetof(struct shmem2_region,
9973                                 other_shmem_base_addr));
9974
9975         u32 shmem_base_path[2];
9976
9977         /* Work around for 84833 LED failure inside RESET status */
9978         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9979                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9980                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9981         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9982                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9983                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9984
9985         shmem_base_path[0] = params->shmem_base;
9986         shmem_base_path[1] = other_shmem_base_addr;
9987
9988         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9989                                                   params->chip_id);
9990
9991         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9992         udelay(10);
9993         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9994                 reset_gpios);
9995
9996         return 0;
9997 }
9998
9999 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10000                                    struct link_params *params,
10001                                    struct link_vars *vars)
10002 {
10003         int rc;
10004         struct bnx2x *bp = params->bp;
10005         u16 cmd_args = 0;
10006
10007         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10008
10009         /* Prevent Phy from working in EEE and advertising it */
10010         rc = bnx2x_84833_cmd_hdlr(phy, params,
10011                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10012         if (rc) {
10013                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10014                 return rc;
10015         }
10016
10017         return bnx2x_eee_disable(phy, params, vars);
10018 }
10019
10020 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10021                                    struct link_params *params,
10022                                    struct link_vars *vars)
10023 {
10024         int rc;
10025         struct bnx2x *bp = params->bp;
10026         u16 cmd_args = 1;
10027
10028         rc = bnx2x_84833_cmd_hdlr(phy, params,
10029                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10030         if (rc) {
10031                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10032                 return rc;
10033         }
10034
10035         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10036 }
10037
10038 #define PHY84833_CONSTANT_LATENCY 1193
10039 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10040                                    struct link_params *params,
10041                                    struct link_vars *vars)
10042 {
10043         struct bnx2x *bp = params->bp;
10044         u8 port, initialize = 1;
10045         u16 val;
10046         u32 actual_phy_selection;
10047         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10048         int rc = 0;
10049
10050         usleep_range(1000, 2000);
10051
10052         if (!(CHIP_IS_E1x(bp)))
10053                 port = BP_PATH(bp);
10054         else
10055                 port = params->port;
10056
10057         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10058                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10059                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10060                                port);
10061         } else {
10062                 /* MDIO reset */
10063                 bnx2x_cl45_write(bp, phy,
10064                                 MDIO_PMA_DEVAD,
10065                                 MDIO_PMA_REG_CTRL, 0x8000);
10066         }
10067
10068         bnx2x_wait_reset_complete(bp, phy, params);
10069
10070         /* Wait for GPHY to come out of reset */
10071         msleep(50);
10072         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10073             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10074                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10075                  * behavior.
10076                  */
10077                 u16 temp;
10078                 temp = vars->line_speed;
10079                 vars->line_speed = SPEED_10000;
10080                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10081                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10082                 vars->line_speed = temp;
10083         }
10084
10085         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10086                         MDIO_CTL_REG_84823_MEDIA, &val);
10087         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10088                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10089                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10090                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10091                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10092
10093         if (CHIP_IS_E3(bp)) {
10094                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10095                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10096         } else {
10097                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10098                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10099         }
10100
10101         actual_phy_selection = bnx2x_phy_selection(params);
10102
10103         switch (actual_phy_selection) {
10104         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10105                 /* Do nothing. Essentially this is like the priority copper */
10106                 break;
10107         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10108                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10109                 break;
10110         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10111                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10112                 break;
10113         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10114                 /* Do nothing here. The first PHY won't be initialized at all */
10115                 break;
10116         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10117                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10118                 initialize = 0;
10119                 break;
10120         }
10121         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10122                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10123
10124         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10125                          MDIO_CTL_REG_84823_MEDIA, val);
10126         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10127                    params->multi_phy_config, val);
10128
10129         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10130             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10131                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10132
10133                 /* Keep AutogrEEEn disabled. */
10134                 cmd_args[0] = 0x0;
10135                 cmd_args[1] = 0x0;
10136                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10137                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10138                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10139                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10140                         PHY84833_CMDHDLR_MAX_ARGS);
10141                 if (rc)
10142                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10143         }
10144         if (initialize)
10145                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10146         else
10147                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10148         /* 84833 PHY has a better feature and doesn't need to support this. */
10149         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10150                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10151                         offsetof(struct shmem_region,
10152                         dev_info.port_hw_config[params->port].default_cfg)) &
10153                         PORT_HW_CFG_ENABLE_CMS_MASK;
10154
10155                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10156                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10157                 if (cms_enable)
10158                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10159                 else
10160                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10161                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10162                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10163         }
10164
10165         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10166                         MDIO_84833_TOP_CFG_FW_REV, &val);
10167
10168         /* Configure EEE support */
10169         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10170             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10171             bnx2x_eee_has_cap(params)) {
10172                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10173                 if (rc) {
10174                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10175                         bnx2x_8483x_disable_eee(phy, params, vars);
10176                         return rc;
10177                 }
10178
10179                 if ((phy->req_duplex == DUPLEX_FULL) &&
10180                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10181                     (bnx2x_eee_calc_timer(params) ||
10182                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10183                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10184                 else
10185                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10186                 if (rc) {
10187                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10188                         return rc;
10189                 }
10190         } else {
10191                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10192         }
10193
10194         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10195             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10196                 /* Bring PHY out of super isolate mode as the final step. */
10197                 bnx2x_cl45_read_and_write(bp, phy,
10198                                           MDIO_CTL_DEVAD,
10199                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10200                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10201         }
10202         return rc;
10203 }
10204
10205 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10206                                   struct link_params *params,
10207                                   struct link_vars *vars)
10208 {
10209         struct bnx2x *bp = params->bp;
10210         u16 val, val1, val2;
10211         u8 link_up = 0;
10212
10213
10214         /* Check 10G-BaseT link status */
10215         /* Check PMD signal ok */
10216         bnx2x_cl45_read(bp, phy,
10217                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10218         bnx2x_cl45_read(bp, phy,
10219                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10220                         &val2);
10221         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10222
10223         /* Check link 10G */
10224         if (val2 & (1<<11)) {
10225                 vars->line_speed = SPEED_10000;
10226                 vars->duplex = DUPLEX_FULL;
10227                 link_up = 1;
10228                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10229         } else { /* Check Legacy speed link */
10230                 u16 legacy_status, legacy_speed;
10231
10232                 /* Enable expansion register 0x42 (Operation mode status) */
10233                 bnx2x_cl45_write(bp, phy,
10234                                  MDIO_AN_DEVAD,
10235                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10236
10237                 /* Get legacy speed operation status */
10238                 bnx2x_cl45_read(bp, phy,
10239                                 MDIO_AN_DEVAD,
10240                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10241                                 &legacy_status);
10242
10243                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10244                    legacy_status);
10245                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10246                 legacy_speed = (legacy_status & (3<<9));
10247                 if (legacy_speed == (0<<9))
10248                         vars->line_speed = SPEED_10;
10249                 else if (legacy_speed == (1<<9))
10250                         vars->line_speed = SPEED_100;
10251                 else if (legacy_speed == (2<<9))
10252                         vars->line_speed = SPEED_1000;
10253                 else { /* Should not happen: Treat as link down */
10254                         vars->line_speed = 0;
10255                         link_up = 0;
10256                 }
10257
10258                 if (link_up) {
10259                         if (legacy_status & (1<<8))
10260                                 vars->duplex = DUPLEX_FULL;
10261                         else
10262                                 vars->duplex = DUPLEX_HALF;
10263
10264                         DP(NETIF_MSG_LINK,
10265                            "Link is up in %dMbps, is_duplex_full= %d\n",
10266                            vars->line_speed,
10267                            (vars->duplex == DUPLEX_FULL));
10268                         /* Check legacy speed AN resolution */
10269                         bnx2x_cl45_read(bp, phy,
10270                                         MDIO_AN_DEVAD,
10271                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10272                                         &val);
10273                         if (val & (1<<5))
10274                                 vars->link_status |=
10275                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10276                         bnx2x_cl45_read(bp, phy,
10277                                         MDIO_AN_DEVAD,
10278                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10279                                         &val);
10280                         if ((val & (1<<0)) == 0)
10281                                 vars->link_status |=
10282                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10283                 }
10284         }
10285         if (link_up) {
10286                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10287                            vars->line_speed);
10288                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10289
10290                 /* Read LP advertised speeds */
10291                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10292                                 MDIO_AN_REG_CL37_FC_LP, &val);
10293                 if (val & (1<<5))
10294                         vars->link_status |=
10295                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10296                 if (val & (1<<6))
10297                         vars->link_status |=
10298                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10299                 if (val & (1<<7))
10300                         vars->link_status |=
10301                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10302                 if (val & (1<<8))
10303                         vars->link_status |=
10304                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10305                 if (val & (1<<9))
10306                         vars->link_status |=
10307                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10308
10309                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10310                                 MDIO_AN_REG_1000T_STATUS, &val);
10311
10312                 if (val & (1<<10))
10313                         vars->link_status |=
10314                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10315                 if (val & (1<<11))
10316                         vars->link_status |=
10317                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10318
10319                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10320                                 MDIO_AN_REG_MASTER_STATUS, &val);
10321
10322                 if (val & (1<<11))
10323                         vars->link_status |=
10324                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10325
10326                 /* Determine if EEE was negotiated */
10327                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10328                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10329                         bnx2x_eee_an_resolve(phy, params, vars);
10330         }
10331
10332         return link_up;
10333 }
10334
10335 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10336 {
10337         int status = 0;
10338         u32 spirom_ver;
10339         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10340         status = bnx2x_format_ver(spirom_ver, str, len);
10341         return status;
10342 }
10343
10344 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10345                                 struct link_params *params)
10346 {
10347         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10348                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10349         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10350                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10351 }
10352
10353 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10354                                         struct link_params *params)
10355 {
10356         bnx2x_cl45_write(params->bp, phy,
10357                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10358         bnx2x_cl45_write(params->bp, phy,
10359                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10360 }
10361
10362 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10363                                    struct link_params *params)
10364 {
10365         struct bnx2x *bp = params->bp;
10366         u8 port;
10367         u16 val16;
10368
10369         if (!(CHIP_IS_E1x(bp)))
10370                 port = BP_PATH(bp);
10371         else
10372                 port = params->port;
10373
10374         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10375                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10376                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10377                                port);
10378         } else {
10379                 bnx2x_cl45_read(bp, phy,
10380                                 MDIO_CTL_DEVAD,
10381                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10382                 val16 |= MDIO_84833_SUPER_ISOLATE;
10383                 bnx2x_cl45_write(bp, phy,
10384                                  MDIO_CTL_DEVAD,
10385                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10386         }
10387 }
10388
10389 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10390                                      struct link_params *params, u8 mode)
10391 {
10392         struct bnx2x *bp = params->bp;
10393         u16 val;
10394         u8 port;
10395
10396         if (!(CHIP_IS_E1x(bp)))
10397                 port = BP_PATH(bp);
10398         else
10399                 port = params->port;
10400
10401         switch (mode) {
10402         case LED_MODE_OFF:
10403
10404                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10405
10406                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10407                     SHARED_HW_CFG_LED_EXTPHY1) {
10408
10409                         /* Set LED masks */
10410                         bnx2x_cl45_write(bp, phy,
10411                                         MDIO_PMA_DEVAD,
10412                                         MDIO_PMA_REG_8481_LED1_MASK,
10413                                         0x0);
10414
10415                         bnx2x_cl45_write(bp, phy,
10416                                         MDIO_PMA_DEVAD,
10417                                         MDIO_PMA_REG_8481_LED2_MASK,
10418                                         0x0);
10419
10420                         bnx2x_cl45_write(bp, phy,
10421                                         MDIO_PMA_DEVAD,
10422                                         MDIO_PMA_REG_8481_LED3_MASK,
10423                                         0x0);
10424
10425                         bnx2x_cl45_write(bp, phy,
10426                                         MDIO_PMA_DEVAD,
10427                                         MDIO_PMA_REG_8481_LED5_MASK,
10428                                         0x0);
10429
10430                 } else {
10431                         bnx2x_cl45_write(bp, phy,
10432                                          MDIO_PMA_DEVAD,
10433                                          MDIO_PMA_REG_8481_LED1_MASK,
10434                                          0x0);
10435                 }
10436                 break;
10437         case LED_MODE_FRONT_PANEL_OFF:
10438
10439                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10440                    port);
10441
10442                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10443                     SHARED_HW_CFG_LED_EXTPHY1) {
10444
10445                         /* Set LED masks */
10446                         bnx2x_cl45_write(bp, phy,
10447                                          MDIO_PMA_DEVAD,
10448                                          MDIO_PMA_REG_8481_LED1_MASK,
10449                                          0x0);
10450
10451                         bnx2x_cl45_write(bp, phy,
10452                                          MDIO_PMA_DEVAD,
10453                                          MDIO_PMA_REG_8481_LED2_MASK,
10454                                          0x0);
10455
10456                         bnx2x_cl45_write(bp, phy,
10457                                          MDIO_PMA_DEVAD,
10458                                          MDIO_PMA_REG_8481_LED3_MASK,
10459                                          0x0);
10460
10461                         bnx2x_cl45_write(bp, phy,
10462                                          MDIO_PMA_DEVAD,
10463                                          MDIO_PMA_REG_8481_LED5_MASK,
10464                                          0x20);
10465
10466                 } else {
10467                         bnx2x_cl45_write(bp, phy,
10468                                          MDIO_PMA_DEVAD,
10469                                          MDIO_PMA_REG_8481_LED1_MASK,
10470                                          0x0);
10471                         if (phy->type ==
10472                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10473                                 /* Disable MI_INT interrupt before setting LED4
10474                                  * source to constant off.
10475                                  */
10476                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10477                                            params->port*4) &
10478                                     NIG_MASK_MI_INT) {
10479                                         params->link_flags |=
10480                                         LINK_FLAGS_INT_DISABLED;
10481
10482                                         bnx2x_bits_dis(
10483                                                 bp,
10484                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10485                                                 params->port*4,
10486                                                 NIG_MASK_MI_INT);
10487                                 }
10488                                 bnx2x_cl45_write(bp, phy,
10489                                                  MDIO_PMA_DEVAD,
10490                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10491                                                  0x0);
10492                         }
10493                 }
10494                 break;
10495         case LED_MODE_ON:
10496
10497                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10498
10499                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10500                     SHARED_HW_CFG_LED_EXTPHY1) {
10501                         /* Set control reg */
10502                         bnx2x_cl45_read(bp, phy,
10503                                         MDIO_PMA_DEVAD,
10504                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10505                                         &val);
10506                         val &= 0x8000;
10507                         val |= 0x2492;
10508
10509                         bnx2x_cl45_write(bp, phy,
10510                                          MDIO_PMA_DEVAD,
10511                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10512                                          val);
10513
10514                         /* Set LED masks */
10515                         bnx2x_cl45_write(bp, phy,
10516                                          MDIO_PMA_DEVAD,
10517                                          MDIO_PMA_REG_8481_LED1_MASK,
10518                                          0x0);
10519
10520                         bnx2x_cl45_write(bp, phy,
10521                                          MDIO_PMA_DEVAD,
10522                                          MDIO_PMA_REG_8481_LED2_MASK,
10523                                          0x20);
10524
10525                         bnx2x_cl45_write(bp, phy,
10526                                          MDIO_PMA_DEVAD,
10527                                          MDIO_PMA_REG_8481_LED3_MASK,
10528                                          0x20);
10529
10530                         bnx2x_cl45_write(bp, phy,
10531                                          MDIO_PMA_DEVAD,
10532                                          MDIO_PMA_REG_8481_LED5_MASK,
10533                                          0x0);
10534                 } else {
10535                         bnx2x_cl45_write(bp, phy,
10536                                          MDIO_PMA_DEVAD,
10537                                          MDIO_PMA_REG_8481_LED1_MASK,
10538                                          0x20);
10539                         if (phy->type ==
10540                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10541                                 /* Disable MI_INT interrupt before setting LED4
10542                                  * source to constant on.
10543                                  */
10544                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10545                                            params->port*4) &
10546                                     NIG_MASK_MI_INT) {
10547                                         params->link_flags |=
10548                                         LINK_FLAGS_INT_DISABLED;
10549
10550                                         bnx2x_bits_dis(
10551                                                 bp,
10552                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10553                                                 params->port*4,
10554                                                 NIG_MASK_MI_INT);
10555                                 }
10556                                 bnx2x_cl45_write(bp, phy,
10557                                                  MDIO_PMA_DEVAD,
10558                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10559                                                  0x20);
10560                         }
10561                 }
10562                 break;
10563
10564         case LED_MODE_OPER:
10565
10566                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10567
10568                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10569                     SHARED_HW_CFG_LED_EXTPHY1) {
10570
10571                         /* Set control reg */
10572                         bnx2x_cl45_read(bp, phy,
10573                                         MDIO_PMA_DEVAD,
10574                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10575                                         &val);
10576
10577                         if (!((val &
10578                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10579                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10580                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10581                                 bnx2x_cl45_write(bp, phy,
10582                                                  MDIO_PMA_DEVAD,
10583                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10584                                                  0xa492);
10585                         }
10586
10587                         /* Set LED masks */
10588                         bnx2x_cl45_write(bp, phy,
10589                                          MDIO_PMA_DEVAD,
10590                                          MDIO_PMA_REG_8481_LED1_MASK,
10591                                          0x10);
10592
10593                         bnx2x_cl45_write(bp, phy,
10594                                          MDIO_PMA_DEVAD,
10595                                          MDIO_PMA_REG_8481_LED2_MASK,
10596                                          0x80);
10597
10598                         bnx2x_cl45_write(bp, phy,
10599                                          MDIO_PMA_DEVAD,
10600                                          MDIO_PMA_REG_8481_LED3_MASK,
10601                                          0x98);
10602
10603                         bnx2x_cl45_write(bp, phy,
10604                                          MDIO_PMA_DEVAD,
10605                                          MDIO_PMA_REG_8481_LED5_MASK,
10606                                          0x40);
10607
10608                 } else {
10609                         bnx2x_cl45_write(bp, phy,
10610                                          MDIO_PMA_DEVAD,
10611                                          MDIO_PMA_REG_8481_LED1_MASK,
10612                                          0x80);
10613
10614                         /* Tell LED3 to blink on source */
10615                         bnx2x_cl45_read(bp, phy,
10616                                         MDIO_PMA_DEVAD,
10617                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10618                                         &val);
10619                         val &= ~(7<<6);
10620                         val |= (1<<6); /* A83B[8:6]= 1 */
10621                         bnx2x_cl45_write(bp, phy,
10622                                          MDIO_PMA_DEVAD,
10623                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10624                                          val);
10625                         if (phy->type ==
10626                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10627                                 /* Restore LED4 source to external link,
10628                                  * and re-enable interrupts.
10629                                  */
10630                                 bnx2x_cl45_write(bp, phy,
10631                                                  MDIO_PMA_DEVAD,
10632                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10633                                                  0x40);
10634                                 if (params->link_flags &
10635                                     LINK_FLAGS_INT_DISABLED) {
10636                                         bnx2x_link_int_enable(params);
10637                                         params->link_flags &=
10638                                                 ~LINK_FLAGS_INT_DISABLED;
10639                                 }
10640                         }
10641                 }
10642                 break;
10643         }
10644
10645         /* This is a workaround for E3+84833 until autoneg
10646          * restart is fixed in f/w
10647          */
10648         if (CHIP_IS_E3(bp)) {
10649                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10650                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10651         }
10652 }
10653
10654 /******************************************************************/
10655 /*                      54618SE PHY SECTION                       */
10656 /******************************************************************/
10657 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10658                                         struct link_params *params,
10659                                         u32 action)
10660 {
10661         struct bnx2x *bp = params->bp;
10662         u16 temp;
10663         switch (action) {
10664         case PHY_INIT:
10665                 /* Configure LED4: set to INTR (0x6). */
10666                 /* Accessing shadow register 0xe. */
10667                 bnx2x_cl22_write(bp, phy,
10668                                  MDIO_REG_GPHY_SHADOW,
10669                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10670                 bnx2x_cl22_read(bp, phy,
10671                                 MDIO_REG_GPHY_SHADOW,
10672                                 &temp);
10673                 temp &= ~(0xf << 4);
10674                 temp |= (0x6 << 4);
10675                 bnx2x_cl22_write(bp, phy,
10676                                  MDIO_REG_GPHY_SHADOW,
10677                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10678                 /* Configure INTR based on link status change. */
10679                 bnx2x_cl22_write(bp, phy,
10680                                  MDIO_REG_INTR_MASK,
10681                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10682                 break;
10683         }
10684 }
10685
10686 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10687                                                struct link_params *params,
10688                                                struct link_vars *vars)
10689 {
10690         struct bnx2x *bp = params->bp;
10691         u8 port;
10692         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10693         u32 cfg_pin;
10694
10695         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10696         usleep_range(1000, 2000);
10697
10698         /* This works with E3 only, no need to check the chip
10699          * before determining the port.
10700          */
10701         port = params->port;
10702
10703         cfg_pin = (REG_RD(bp, params->shmem_base +
10704                         offsetof(struct shmem_region,
10705                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10706                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10707                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10708
10709         /* Drive pin high to bring the GPHY out of reset. */
10710         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10711
10712         /* wait for GPHY to reset */
10713         msleep(50);
10714
10715         /* reset phy */
10716         bnx2x_cl22_write(bp, phy,
10717                          MDIO_PMA_REG_CTRL, 0x8000);
10718         bnx2x_wait_reset_complete(bp, phy, params);
10719
10720         /* Wait for GPHY to reset */
10721         msleep(50);
10722
10723
10724         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10725         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10726         bnx2x_cl22_write(bp, phy,
10727                         MDIO_REG_GPHY_SHADOW,
10728                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10729         bnx2x_cl22_read(bp, phy,
10730                         MDIO_REG_GPHY_SHADOW,
10731                         &temp);
10732         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10733         bnx2x_cl22_write(bp, phy,
10734                         MDIO_REG_GPHY_SHADOW,
10735                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10736
10737         /* Set up fc */
10738         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10739         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10740         fc_val = 0;
10741         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10742                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10743                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10744
10745         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10746                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10747                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10748
10749         /* Read all advertisement */
10750         bnx2x_cl22_read(bp, phy,
10751                         0x09,
10752                         &an_1000_val);
10753
10754         bnx2x_cl22_read(bp, phy,
10755                         0x04,
10756                         &an_10_100_val);
10757
10758         bnx2x_cl22_read(bp, phy,
10759                         MDIO_PMA_REG_CTRL,
10760                         &autoneg_val);
10761
10762         /* Disable forced speed */
10763         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10764         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10765                            (1<<11));
10766
10767         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10768                         (phy->speed_cap_mask &
10769                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10770                         (phy->req_line_speed == SPEED_1000)) {
10771                 an_1000_val |= (1<<8);
10772                 autoneg_val |= (1<<9 | 1<<12);
10773                 if (phy->req_duplex == DUPLEX_FULL)
10774                         an_1000_val |= (1<<9);
10775                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10776         } else
10777                 an_1000_val &= ~((1<<8) | (1<<9));
10778
10779         bnx2x_cl22_write(bp, phy,
10780                         0x09,
10781                         an_1000_val);
10782         bnx2x_cl22_read(bp, phy,
10783                         0x09,
10784                         &an_1000_val);
10785
10786         /* Set 100 speed advertisement */
10787         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10788                         (phy->speed_cap_mask &
10789                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10790                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10791                 an_10_100_val |= (1<<7);
10792                 /* Enable autoneg and restart autoneg for legacy speeds */
10793                 autoneg_val |= (1<<9 | 1<<12);
10794
10795                 if (phy->req_duplex == DUPLEX_FULL)
10796                         an_10_100_val |= (1<<8);
10797                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10798         }
10799
10800         /* Set 10 speed advertisement */
10801         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10802                         (phy->speed_cap_mask &
10803                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10804                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10805                 an_10_100_val |= (1<<5);
10806                 autoneg_val |= (1<<9 | 1<<12);
10807                 if (phy->req_duplex == DUPLEX_FULL)
10808                         an_10_100_val |= (1<<6);
10809                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10810         }
10811
10812         /* Only 10/100 are allowed to work in FORCE mode */
10813         if (phy->req_line_speed == SPEED_100) {
10814                 autoneg_val |= (1<<13);
10815                 /* Enabled AUTO-MDIX when autoneg is disabled */
10816                 bnx2x_cl22_write(bp, phy,
10817                                 0x18,
10818                                 (1<<15 | 1<<9 | 7<<0));
10819                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10820         }
10821         if (phy->req_line_speed == SPEED_10) {
10822                 /* Enabled AUTO-MDIX when autoneg is disabled */
10823                 bnx2x_cl22_write(bp, phy,
10824                                 0x18,
10825                                 (1<<15 | 1<<9 | 7<<0));
10826                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10827         }
10828
10829         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10830                 int rc;
10831
10832                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10833                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10834                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10835                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10836                 temp &= 0xfffe;
10837                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10838
10839                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10840                 if (rc) {
10841                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10842                         bnx2x_eee_disable(phy, params, vars);
10843                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10844                            (phy->req_duplex == DUPLEX_FULL) &&
10845                            (bnx2x_eee_calc_timer(params) ||
10846                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10847                         /* Need to advertise EEE only when requested,
10848                          * and either no LPI assertion was requested,
10849                          * or it was requested and a valid timer was set.
10850                          * Also notice full duplex is required for EEE.
10851                          */
10852                         bnx2x_eee_advertise(phy, params, vars,
10853                                             SHMEM_EEE_1G_ADV);
10854                 } else {
10855                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10856                         bnx2x_eee_disable(phy, params, vars);
10857                 }
10858         } else {
10859                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10860                                     SHMEM_EEE_SUPPORTED_SHIFT;
10861
10862                 if (phy->flags & FLAGS_EEE) {
10863                         /* Handle legacy auto-grEEEn */
10864                         if (params->feature_config_flags &
10865                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10866                                 temp = 6;
10867                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10868                         } else {
10869                                 temp = 0;
10870                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10871                         }
10872                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10873                                          MDIO_AN_REG_EEE_ADV, temp);
10874                 }
10875         }
10876
10877         bnx2x_cl22_write(bp, phy,
10878                         0x04,
10879                         an_10_100_val | fc_val);
10880
10881         if (phy->req_duplex == DUPLEX_FULL)
10882                 autoneg_val |= (1<<8);
10883
10884         bnx2x_cl22_write(bp, phy,
10885                         MDIO_PMA_REG_CTRL, autoneg_val);
10886
10887         return 0;
10888 }
10889
10890
10891 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10892                                        struct link_params *params, u8 mode)
10893 {
10894         struct bnx2x *bp = params->bp;
10895         u16 temp;
10896
10897         bnx2x_cl22_write(bp, phy,
10898                 MDIO_REG_GPHY_SHADOW,
10899                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10900         bnx2x_cl22_read(bp, phy,
10901                 MDIO_REG_GPHY_SHADOW,
10902                 &temp);
10903         temp &= 0xff00;
10904
10905         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10906         switch (mode) {
10907         case LED_MODE_FRONT_PANEL_OFF:
10908         case LED_MODE_OFF:
10909                 temp |= 0x00ee;
10910                 break;
10911         case LED_MODE_OPER:
10912                 temp |= 0x0001;
10913                 break;
10914         case LED_MODE_ON:
10915                 temp |= 0x00ff;
10916                 break;
10917         default:
10918                 break;
10919         }
10920         bnx2x_cl22_write(bp, phy,
10921                 MDIO_REG_GPHY_SHADOW,
10922                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10923         return;
10924 }
10925
10926
10927 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10928                                      struct link_params *params)
10929 {
10930         struct bnx2x *bp = params->bp;
10931         u32 cfg_pin;
10932         u8 port;
10933
10934         /* In case of no EPIO routed to reset the GPHY, put it
10935          * in low power mode.
10936          */
10937         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10938         /* This works with E3 only, no need to check the chip
10939          * before determining the port.
10940          */
10941         port = params->port;
10942         cfg_pin = (REG_RD(bp, params->shmem_base +
10943                         offsetof(struct shmem_region,
10944                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10945                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10946                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10947
10948         /* Drive pin low to put GPHY in reset. */
10949         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10950 }
10951
10952 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10953                                     struct link_params *params,
10954                                     struct link_vars *vars)
10955 {
10956         struct bnx2x *bp = params->bp;
10957         u16 val;
10958         u8 link_up = 0;
10959         u16 legacy_status, legacy_speed;
10960
10961         /* Get speed operation status */
10962         bnx2x_cl22_read(bp, phy,
10963                         MDIO_REG_GPHY_AUX_STATUS,
10964                         &legacy_status);
10965         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10966
10967         /* Read status to clear the PHY interrupt. */
10968         bnx2x_cl22_read(bp, phy,
10969                         MDIO_REG_INTR_STATUS,
10970                         &val);
10971
10972         link_up = ((legacy_status & (1<<2)) == (1<<2));
10973
10974         if (link_up) {
10975                 legacy_speed = (legacy_status & (7<<8));
10976                 if (legacy_speed == (7<<8)) {
10977                         vars->line_speed = SPEED_1000;
10978                         vars->duplex = DUPLEX_FULL;
10979                 } else if (legacy_speed == (6<<8)) {
10980                         vars->line_speed = SPEED_1000;
10981                         vars->duplex = DUPLEX_HALF;
10982                 } else if (legacy_speed == (5<<8)) {
10983                         vars->line_speed = SPEED_100;
10984                         vars->duplex = DUPLEX_FULL;
10985                 }
10986                 /* Omitting 100Base-T4 for now */
10987                 else if (legacy_speed == (3<<8)) {
10988                         vars->line_speed = SPEED_100;
10989                         vars->duplex = DUPLEX_HALF;
10990                 } else if (legacy_speed == (2<<8)) {
10991                         vars->line_speed = SPEED_10;
10992                         vars->duplex = DUPLEX_FULL;
10993                 } else if (legacy_speed == (1<<8)) {
10994                         vars->line_speed = SPEED_10;
10995                         vars->duplex = DUPLEX_HALF;
10996                 } else /* Should not happen */
10997                         vars->line_speed = 0;
10998
10999                 DP(NETIF_MSG_LINK,
11000                    "Link is up in %dMbps, is_duplex_full= %d\n",
11001                    vars->line_speed,
11002                    (vars->duplex == DUPLEX_FULL));
11003
11004                 /* Check legacy speed AN resolution */
11005                 bnx2x_cl22_read(bp, phy,
11006                                 0x01,
11007                                 &val);
11008                 if (val & (1<<5))
11009                         vars->link_status |=
11010                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11011                 bnx2x_cl22_read(bp, phy,
11012                                 0x06,
11013                                 &val);
11014                 if ((val & (1<<0)) == 0)
11015                         vars->link_status |=
11016                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11017
11018                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11019                            vars->line_speed);
11020
11021                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11022
11023                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11024                         /* Report LP advertised speeds */
11025                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11026
11027                         if (val & (1<<5))
11028                                 vars->link_status |=
11029                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11030                         if (val & (1<<6))
11031                                 vars->link_status |=
11032                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11033                         if (val & (1<<7))
11034                                 vars->link_status |=
11035                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11036                         if (val & (1<<8))
11037                                 vars->link_status |=
11038                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11039                         if (val & (1<<9))
11040                                 vars->link_status |=
11041                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11042
11043                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11044                         if (val & (1<<10))
11045                                 vars->link_status |=
11046                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11047                         if (val & (1<<11))
11048                                 vars->link_status |=
11049                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11050
11051                         if ((phy->flags & FLAGS_EEE) &&
11052                             bnx2x_eee_has_cap(params))
11053                                 bnx2x_eee_an_resolve(phy, params, vars);
11054                 }
11055         }
11056         return link_up;
11057 }
11058
11059 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11060                                           struct link_params *params)
11061 {
11062         struct bnx2x *bp = params->bp;
11063         u16 val;
11064         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11065
11066         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11067
11068         /* Enable master/slave manual mmode and set to master */
11069         /* mii write 9 [bits set 11 12] */
11070         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11071
11072         /* forced 1G and disable autoneg */
11073         /* set val [mii read 0] */
11074         /* set val [expr $val & [bits clear 6 12 13]] */
11075         /* set val [expr $val | [bits set 6 8]] */
11076         /* mii write 0 $val */
11077         bnx2x_cl22_read(bp, phy, 0x00, &val);
11078         val &= ~((1<<6) | (1<<12) | (1<<13));
11079         val |= (1<<6) | (1<<8);
11080         bnx2x_cl22_write(bp, phy, 0x00, val);
11081
11082         /* Set external loopback and Tx using 6dB coding */
11083         /* mii write 0x18 7 */
11084         /* set val [mii read 0x18] */
11085         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11086         bnx2x_cl22_write(bp, phy, 0x18, 7);
11087         bnx2x_cl22_read(bp, phy, 0x18, &val);
11088         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11089
11090         /* This register opens the gate for the UMAC despite its name */
11091         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11092
11093         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11094          * length used by the MAC receive logic to check frames.
11095          */
11096         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11097 }
11098
11099 /******************************************************************/
11100 /*                      SFX7101 PHY SECTION                       */
11101 /******************************************************************/
11102 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11103                                        struct link_params *params)
11104 {
11105         struct bnx2x *bp = params->bp;
11106         /* SFX7101_XGXS_TEST1 */
11107         bnx2x_cl45_write(bp, phy,
11108                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11109 }
11110
11111 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11112                                   struct link_params *params,
11113                                   struct link_vars *vars)
11114 {
11115         u16 fw_ver1, fw_ver2, val;
11116         struct bnx2x *bp = params->bp;
11117         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11118
11119         /* Restore normal power mode*/
11120         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11121                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11122         /* HW reset */
11123         bnx2x_ext_phy_hw_reset(bp, params->port);
11124         bnx2x_wait_reset_complete(bp, phy, params);
11125
11126         bnx2x_cl45_write(bp, phy,
11127                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11128         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11129         bnx2x_cl45_write(bp, phy,
11130                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11131
11132         bnx2x_ext_phy_set_pause(params, phy, vars);
11133         /* Restart autoneg */
11134         bnx2x_cl45_read(bp, phy,
11135                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11136         val |= 0x200;
11137         bnx2x_cl45_write(bp, phy,
11138                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11139
11140         /* Save spirom version */
11141         bnx2x_cl45_read(bp, phy,
11142                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11143
11144         bnx2x_cl45_read(bp, phy,
11145                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11146         bnx2x_save_spirom_version(bp, params->port,
11147                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11148         return 0;
11149 }
11150
11151 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11152                                  struct link_params *params,
11153                                  struct link_vars *vars)
11154 {
11155         struct bnx2x *bp = params->bp;
11156         u8 link_up;
11157         u16 val1, val2;
11158         bnx2x_cl45_read(bp, phy,
11159                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11160         bnx2x_cl45_read(bp, phy,
11161                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11162         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11163                    val2, val1);
11164         bnx2x_cl45_read(bp, phy,
11165                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11166         bnx2x_cl45_read(bp, phy,
11167                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11168         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11169                    val2, val1);
11170         link_up = ((val1 & 4) == 4);
11171         /* If link is up print the AN outcome of the SFX7101 PHY */
11172         if (link_up) {
11173                 bnx2x_cl45_read(bp, phy,
11174                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11175                                 &val2);
11176                 vars->line_speed = SPEED_10000;
11177                 vars->duplex = DUPLEX_FULL;
11178                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11179                            val2, (val2 & (1<<14)));
11180                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11181                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11182
11183                 /* Read LP advertised speeds */
11184                 if (val2 & (1<<11))
11185                         vars->link_status |=
11186                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11187         }
11188         return link_up;
11189 }
11190
11191 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11192 {
11193         if (*len < 5)
11194                 return -EINVAL;
11195         str[0] = (spirom_ver & 0xFF);
11196         str[1] = (spirom_ver & 0xFF00) >> 8;
11197         str[2] = (spirom_ver & 0xFF0000) >> 16;
11198         str[3] = (spirom_ver & 0xFF000000) >> 24;
11199         str[4] = '\0';
11200         *len -= 5;
11201         return 0;
11202 }
11203
11204 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11205 {
11206         u16 val, cnt;
11207
11208         bnx2x_cl45_read(bp, phy,
11209                         MDIO_PMA_DEVAD,
11210                         MDIO_PMA_REG_7101_RESET, &val);
11211
11212         for (cnt = 0; cnt < 10; cnt++) {
11213                 msleep(50);
11214                 /* Writes a self-clearing reset */
11215                 bnx2x_cl45_write(bp, phy,
11216                                  MDIO_PMA_DEVAD,
11217                                  MDIO_PMA_REG_7101_RESET,
11218                                  (val | (1<<15)));
11219                 /* Wait for clear */
11220                 bnx2x_cl45_read(bp, phy,
11221                                 MDIO_PMA_DEVAD,
11222                                 MDIO_PMA_REG_7101_RESET, &val);
11223
11224                 if ((val & (1<<15)) == 0)
11225                         break;
11226         }
11227 }
11228
11229 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11230                                 struct link_params *params) {
11231         /* Low power mode is controlled by GPIO 2 */
11232         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11233                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11234         /* The PHY reset is controlled by GPIO 1 */
11235         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11236                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11237 }
11238
11239 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11240                                     struct link_params *params, u8 mode)
11241 {
11242         u16 val = 0;
11243         struct bnx2x *bp = params->bp;
11244         switch (mode) {
11245         case LED_MODE_FRONT_PANEL_OFF:
11246         case LED_MODE_OFF:
11247                 val = 2;
11248                 break;
11249         case LED_MODE_ON:
11250                 val = 1;
11251                 break;
11252         case LED_MODE_OPER:
11253                 val = 0;
11254                 break;
11255         }
11256         bnx2x_cl45_write(bp, phy,
11257                          MDIO_PMA_DEVAD,
11258                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11259                          val);
11260 }
11261
11262 /******************************************************************/
11263 /*                      STATIC PHY DECLARATION                    */
11264 /******************************************************************/
11265
11266 static const struct bnx2x_phy phy_null = {
11267         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11268         .addr           = 0,
11269         .def_md_devad   = 0,
11270         .flags          = FLAGS_INIT_XGXS_FIRST,
11271         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11272         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11273         .mdio_ctrl      = 0,
11274         .supported      = 0,
11275         .media_type     = ETH_PHY_NOT_PRESENT,
11276         .ver_addr       = 0,
11277         .req_flow_ctrl  = 0,
11278         .req_line_speed = 0,
11279         .speed_cap_mask = 0,
11280         .req_duplex     = 0,
11281         .rsrv           = 0,
11282         .config_init    = (config_init_t)NULL,
11283         .read_status    = (read_status_t)NULL,
11284         .link_reset     = (link_reset_t)NULL,
11285         .config_loopback = (config_loopback_t)NULL,
11286         .format_fw_ver  = (format_fw_ver_t)NULL,
11287         .hw_reset       = (hw_reset_t)NULL,
11288         .set_link_led   = (set_link_led_t)NULL,
11289         .phy_specific_func = (phy_specific_func_t)NULL
11290 };
11291
11292 static const struct bnx2x_phy phy_serdes = {
11293         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11294         .addr           = 0xff,
11295         .def_md_devad   = 0,
11296         .flags          = 0,
11297         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11298         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11299         .mdio_ctrl      = 0,
11300         .supported      = (SUPPORTED_10baseT_Half |
11301                            SUPPORTED_10baseT_Full |
11302                            SUPPORTED_100baseT_Half |
11303                            SUPPORTED_100baseT_Full |
11304                            SUPPORTED_1000baseT_Full |
11305                            SUPPORTED_2500baseX_Full |
11306                            SUPPORTED_TP |
11307                            SUPPORTED_Autoneg |
11308                            SUPPORTED_Pause |
11309                            SUPPORTED_Asym_Pause),
11310         .media_type     = ETH_PHY_BASE_T,
11311         .ver_addr       = 0,
11312         .req_flow_ctrl  = 0,
11313         .req_line_speed = 0,
11314         .speed_cap_mask = 0,
11315         .req_duplex     = 0,
11316         .rsrv           = 0,
11317         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11318         .read_status    = (read_status_t)bnx2x_link_settings_status,
11319         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11320         .config_loopback = (config_loopback_t)NULL,
11321         .format_fw_ver  = (format_fw_ver_t)NULL,
11322         .hw_reset       = (hw_reset_t)NULL,
11323         .set_link_led   = (set_link_led_t)NULL,
11324         .phy_specific_func = (phy_specific_func_t)NULL
11325 };
11326
11327 static const struct bnx2x_phy phy_xgxs = {
11328         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11329         .addr           = 0xff,
11330         .def_md_devad   = 0,
11331         .flags          = 0,
11332         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11333         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11334         .mdio_ctrl      = 0,
11335         .supported      = (SUPPORTED_10baseT_Half |
11336                            SUPPORTED_10baseT_Full |
11337                            SUPPORTED_100baseT_Half |
11338                            SUPPORTED_100baseT_Full |
11339                            SUPPORTED_1000baseT_Full |
11340                            SUPPORTED_2500baseX_Full |
11341                            SUPPORTED_10000baseT_Full |
11342                            SUPPORTED_FIBRE |
11343                            SUPPORTED_Autoneg |
11344                            SUPPORTED_Pause |
11345                            SUPPORTED_Asym_Pause),
11346         .media_type     = ETH_PHY_CX4,
11347         .ver_addr       = 0,
11348         .req_flow_ctrl  = 0,
11349         .req_line_speed = 0,
11350         .speed_cap_mask = 0,
11351         .req_duplex     = 0,
11352         .rsrv           = 0,
11353         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11354         .read_status    = (read_status_t)bnx2x_link_settings_status,
11355         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11356         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11357         .format_fw_ver  = (format_fw_ver_t)NULL,
11358         .hw_reset       = (hw_reset_t)NULL,
11359         .set_link_led   = (set_link_led_t)NULL,
11360         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11361 };
11362 static const struct bnx2x_phy phy_warpcore = {
11363         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11364         .addr           = 0xff,
11365         .def_md_devad   = 0,
11366         .flags          = FLAGS_TX_ERROR_CHECK,
11367         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11368         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11369         .mdio_ctrl      = 0,
11370         .supported      = (SUPPORTED_10baseT_Half |
11371                            SUPPORTED_10baseT_Full |
11372                            SUPPORTED_100baseT_Half |
11373                            SUPPORTED_100baseT_Full |
11374                            SUPPORTED_1000baseT_Full |
11375                            SUPPORTED_10000baseT_Full |
11376                            SUPPORTED_20000baseKR2_Full |
11377                            SUPPORTED_20000baseMLD2_Full |
11378                            SUPPORTED_FIBRE |
11379                            SUPPORTED_Autoneg |
11380                            SUPPORTED_Pause |
11381                            SUPPORTED_Asym_Pause),
11382         .media_type     = ETH_PHY_UNSPECIFIED,
11383         .ver_addr       = 0,
11384         .req_flow_ctrl  = 0,
11385         .req_line_speed = 0,
11386         .speed_cap_mask = 0,
11387         /* req_duplex = */0,
11388         /* rsrv = */0,
11389         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11390         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11391         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11392         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11393         .format_fw_ver  = (format_fw_ver_t)NULL,
11394         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11395         .set_link_led   = (set_link_led_t)NULL,
11396         .phy_specific_func = (phy_specific_func_t)NULL
11397 };
11398
11399
11400 static const struct bnx2x_phy phy_7101 = {
11401         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11402         .addr           = 0xff,
11403         .def_md_devad   = 0,
11404         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11405         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11406         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11407         .mdio_ctrl      = 0,
11408         .supported      = (SUPPORTED_10000baseT_Full |
11409                            SUPPORTED_TP |
11410                            SUPPORTED_Autoneg |
11411                            SUPPORTED_Pause |
11412                            SUPPORTED_Asym_Pause),
11413         .media_type     = ETH_PHY_BASE_T,
11414         .ver_addr       = 0,
11415         .req_flow_ctrl  = 0,
11416         .req_line_speed = 0,
11417         .speed_cap_mask = 0,
11418         .req_duplex     = 0,
11419         .rsrv           = 0,
11420         .config_init    = (config_init_t)bnx2x_7101_config_init,
11421         .read_status    = (read_status_t)bnx2x_7101_read_status,
11422         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11423         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11424         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11425         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11426         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11427         .phy_specific_func = (phy_specific_func_t)NULL
11428 };
11429 static const struct bnx2x_phy phy_8073 = {
11430         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11431         .addr           = 0xff,
11432         .def_md_devad   = 0,
11433         .flags          = 0,
11434         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11435         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11436         .mdio_ctrl      = 0,
11437         .supported      = (SUPPORTED_10000baseT_Full |
11438                            SUPPORTED_2500baseX_Full |
11439                            SUPPORTED_1000baseT_Full |
11440                            SUPPORTED_FIBRE |
11441                            SUPPORTED_Autoneg |
11442                            SUPPORTED_Pause |
11443                            SUPPORTED_Asym_Pause),
11444         .media_type     = ETH_PHY_KR,
11445         .ver_addr       = 0,
11446         .req_flow_ctrl  = 0,
11447         .req_line_speed = 0,
11448         .speed_cap_mask = 0,
11449         .req_duplex     = 0,
11450         .rsrv           = 0,
11451         .config_init    = (config_init_t)bnx2x_8073_config_init,
11452         .read_status    = (read_status_t)bnx2x_8073_read_status,
11453         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11454         .config_loopback = (config_loopback_t)NULL,
11455         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11456         .hw_reset       = (hw_reset_t)NULL,
11457         .set_link_led   = (set_link_led_t)NULL,
11458         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11459 };
11460 static const struct bnx2x_phy phy_8705 = {
11461         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11462         .addr           = 0xff,
11463         .def_md_devad   = 0,
11464         .flags          = FLAGS_INIT_XGXS_FIRST,
11465         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11466         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11467         .mdio_ctrl      = 0,
11468         .supported      = (SUPPORTED_10000baseT_Full |
11469                            SUPPORTED_FIBRE |
11470                            SUPPORTED_Pause |
11471                            SUPPORTED_Asym_Pause),
11472         .media_type     = ETH_PHY_XFP_FIBER,
11473         .ver_addr       = 0,
11474         .req_flow_ctrl  = 0,
11475         .req_line_speed = 0,
11476         .speed_cap_mask = 0,
11477         .req_duplex     = 0,
11478         .rsrv           = 0,
11479         .config_init    = (config_init_t)bnx2x_8705_config_init,
11480         .read_status    = (read_status_t)bnx2x_8705_read_status,
11481         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11482         .config_loopback = (config_loopback_t)NULL,
11483         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11484         .hw_reset       = (hw_reset_t)NULL,
11485         .set_link_led   = (set_link_led_t)NULL,
11486         .phy_specific_func = (phy_specific_func_t)NULL
11487 };
11488 static const struct bnx2x_phy phy_8706 = {
11489         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11490         .addr           = 0xff,
11491         .def_md_devad   = 0,
11492         .flags          = FLAGS_INIT_XGXS_FIRST,
11493         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11494         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11495         .mdio_ctrl      = 0,
11496         .supported      = (SUPPORTED_10000baseT_Full |
11497                            SUPPORTED_1000baseT_Full |
11498                            SUPPORTED_FIBRE |
11499                            SUPPORTED_Pause |
11500                            SUPPORTED_Asym_Pause),
11501         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11502         .ver_addr       = 0,
11503         .req_flow_ctrl  = 0,
11504         .req_line_speed = 0,
11505         .speed_cap_mask = 0,
11506         .req_duplex     = 0,
11507         .rsrv           = 0,
11508         .config_init    = (config_init_t)bnx2x_8706_config_init,
11509         .read_status    = (read_status_t)bnx2x_8706_read_status,
11510         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11511         .config_loopback = (config_loopback_t)NULL,
11512         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11513         .hw_reset       = (hw_reset_t)NULL,
11514         .set_link_led   = (set_link_led_t)NULL,
11515         .phy_specific_func = (phy_specific_func_t)NULL
11516 };
11517
11518 static const struct bnx2x_phy phy_8726 = {
11519         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11520         .addr           = 0xff,
11521         .def_md_devad   = 0,
11522         .flags          = (FLAGS_INIT_XGXS_FIRST |
11523                            FLAGS_TX_ERROR_CHECK),
11524         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11525         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11526         .mdio_ctrl      = 0,
11527         .supported      = (SUPPORTED_10000baseT_Full |
11528                            SUPPORTED_1000baseT_Full |
11529                            SUPPORTED_Autoneg |
11530                            SUPPORTED_FIBRE |
11531                            SUPPORTED_Pause |
11532                            SUPPORTED_Asym_Pause),
11533         .media_type     = ETH_PHY_NOT_PRESENT,
11534         .ver_addr       = 0,
11535         .req_flow_ctrl  = 0,
11536         .req_line_speed = 0,
11537         .speed_cap_mask = 0,
11538         .req_duplex     = 0,
11539         .rsrv           = 0,
11540         .config_init    = (config_init_t)bnx2x_8726_config_init,
11541         .read_status    = (read_status_t)bnx2x_8726_read_status,
11542         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11543         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11544         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11545         .hw_reset       = (hw_reset_t)NULL,
11546         .set_link_led   = (set_link_led_t)NULL,
11547         .phy_specific_func = (phy_specific_func_t)NULL
11548 };
11549
11550 static const struct bnx2x_phy phy_8727 = {
11551         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11552         .addr           = 0xff,
11553         .def_md_devad   = 0,
11554         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11555                            FLAGS_TX_ERROR_CHECK),
11556         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11557         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11558         .mdio_ctrl      = 0,
11559         .supported      = (SUPPORTED_10000baseT_Full |
11560                            SUPPORTED_1000baseT_Full |
11561                            SUPPORTED_FIBRE |
11562                            SUPPORTED_Pause |
11563                            SUPPORTED_Asym_Pause),
11564         .media_type     = ETH_PHY_NOT_PRESENT,
11565         .ver_addr       = 0,
11566         .req_flow_ctrl  = 0,
11567         .req_line_speed = 0,
11568         .speed_cap_mask = 0,
11569         .req_duplex     = 0,
11570         .rsrv           = 0,
11571         .config_init    = (config_init_t)bnx2x_8727_config_init,
11572         .read_status    = (read_status_t)bnx2x_8727_read_status,
11573         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11574         .config_loopback = (config_loopback_t)NULL,
11575         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11576         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11577         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11578         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11579 };
11580 static const struct bnx2x_phy phy_8481 = {
11581         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11582         .addr           = 0xff,
11583         .def_md_devad   = 0,
11584         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11585                           FLAGS_REARM_LATCH_SIGNAL,
11586         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11587         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11588         .mdio_ctrl      = 0,
11589         .supported      = (SUPPORTED_10baseT_Half |
11590                            SUPPORTED_10baseT_Full |
11591                            SUPPORTED_100baseT_Half |
11592                            SUPPORTED_100baseT_Full |
11593                            SUPPORTED_1000baseT_Full |
11594                            SUPPORTED_10000baseT_Full |
11595                            SUPPORTED_TP |
11596                            SUPPORTED_Autoneg |
11597                            SUPPORTED_Pause |
11598                            SUPPORTED_Asym_Pause),
11599         .media_type     = ETH_PHY_BASE_T,
11600         .ver_addr       = 0,
11601         .req_flow_ctrl  = 0,
11602         .req_line_speed = 0,
11603         .speed_cap_mask = 0,
11604         .req_duplex     = 0,
11605         .rsrv           = 0,
11606         .config_init    = (config_init_t)bnx2x_8481_config_init,
11607         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11608         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11609         .config_loopback = (config_loopback_t)NULL,
11610         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11611         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11612         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11613         .phy_specific_func = (phy_specific_func_t)NULL
11614 };
11615
11616 static const struct bnx2x_phy phy_84823 = {
11617         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11618         .addr           = 0xff,
11619         .def_md_devad   = 0,
11620         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11621                            FLAGS_REARM_LATCH_SIGNAL |
11622                            FLAGS_TX_ERROR_CHECK),
11623         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11624         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11625         .mdio_ctrl      = 0,
11626         .supported      = (SUPPORTED_10baseT_Half |
11627                            SUPPORTED_10baseT_Full |
11628                            SUPPORTED_100baseT_Half |
11629                            SUPPORTED_100baseT_Full |
11630                            SUPPORTED_1000baseT_Full |
11631                            SUPPORTED_10000baseT_Full |
11632                            SUPPORTED_TP |
11633                            SUPPORTED_Autoneg |
11634                            SUPPORTED_Pause |
11635                            SUPPORTED_Asym_Pause),
11636         .media_type     = ETH_PHY_BASE_T,
11637         .ver_addr       = 0,
11638         .req_flow_ctrl  = 0,
11639         .req_line_speed = 0,
11640         .speed_cap_mask = 0,
11641         .req_duplex     = 0,
11642         .rsrv           = 0,
11643         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11644         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11645         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11646         .config_loopback = (config_loopback_t)NULL,
11647         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11648         .hw_reset       = (hw_reset_t)NULL,
11649         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11650         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11651 };
11652
11653 static const struct bnx2x_phy phy_84833 = {
11654         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11655         .addr           = 0xff,
11656         .def_md_devad   = 0,
11657         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11658                            FLAGS_REARM_LATCH_SIGNAL |
11659                            FLAGS_TX_ERROR_CHECK),
11660         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11661         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11662         .mdio_ctrl      = 0,
11663         .supported      = (SUPPORTED_100baseT_Half |
11664                            SUPPORTED_100baseT_Full |
11665                            SUPPORTED_1000baseT_Full |
11666                            SUPPORTED_10000baseT_Full |
11667                            SUPPORTED_TP |
11668                            SUPPORTED_Autoneg |
11669                            SUPPORTED_Pause |
11670                            SUPPORTED_Asym_Pause),
11671         .media_type     = ETH_PHY_BASE_T,
11672         .ver_addr       = 0,
11673         .req_flow_ctrl  = 0,
11674         .req_line_speed = 0,
11675         .speed_cap_mask = 0,
11676         .req_duplex     = 0,
11677         .rsrv           = 0,
11678         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11679         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11680         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11681         .config_loopback = (config_loopback_t)NULL,
11682         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11683         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11684         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11685         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11686 };
11687
11688 static const struct bnx2x_phy phy_84834 = {
11689         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11690         .addr           = 0xff,
11691         .def_md_devad   = 0,
11692         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11693                             FLAGS_REARM_LATCH_SIGNAL,
11694         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11695         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11696         .mdio_ctrl      = 0,
11697         .supported      = (SUPPORTED_100baseT_Half |
11698                            SUPPORTED_100baseT_Full |
11699                            SUPPORTED_1000baseT_Full |
11700                            SUPPORTED_10000baseT_Full |
11701                            SUPPORTED_TP |
11702                            SUPPORTED_Autoneg |
11703                            SUPPORTED_Pause |
11704                            SUPPORTED_Asym_Pause),
11705         .media_type     = ETH_PHY_BASE_T,
11706         .ver_addr       = 0,
11707         .req_flow_ctrl  = 0,
11708         .req_line_speed = 0,
11709         .speed_cap_mask = 0,
11710         .req_duplex     = 0,
11711         .rsrv           = 0,
11712         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11713         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11714         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11715         .config_loopback = (config_loopback_t)NULL,
11716         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11717         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11718         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11719         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11720 };
11721
11722 static const struct bnx2x_phy phy_54618se = {
11723         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11724         .addr           = 0xff,
11725         .def_md_devad   = 0,
11726         .flags          = FLAGS_INIT_XGXS_FIRST,
11727         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11728         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11729         .mdio_ctrl      = 0,
11730         .supported      = (SUPPORTED_10baseT_Half |
11731                            SUPPORTED_10baseT_Full |
11732                            SUPPORTED_100baseT_Half |
11733                            SUPPORTED_100baseT_Full |
11734                            SUPPORTED_1000baseT_Full |
11735                            SUPPORTED_TP |
11736                            SUPPORTED_Autoneg |
11737                            SUPPORTED_Pause |
11738                            SUPPORTED_Asym_Pause),
11739         .media_type     = ETH_PHY_BASE_T,
11740         .ver_addr       = 0,
11741         .req_flow_ctrl  = 0,
11742         .req_line_speed = 0,
11743         .speed_cap_mask = 0,
11744         /* req_duplex = */0,
11745         /* rsrv = */0,
11746         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11747         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11748         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11749         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11750         .format_fw_ver  = (format_fw_ver_t)NULL,
11751         .hw_reset       = (hw_reset_t)NULL,
11752         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11753         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11754 };
11755 /*****************************************************************/
11756 /*                                                               */
11757 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11758 /*                                                               */
11759 /*****************************************************************/
11760
11761 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11762                                      struct bnx2x_phy *phy, u8 port,
11763                                      u8 phy_index)
11764 {
11765         /* Get the 4 lanes xgxs config rx and tx */
11766         u32 rx = 0, tx = 0, i;
11767         for (i = 0; i < 2; i++) {
11768                 /* INT_PHY and EXT_PHY1 share the same value location in
11769                  * the shmem. When num_phys is greater than 1, than this value
11770                  * applies only to EXT_PHY1
11771                  */
11772                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11773                         rx = REG_RD(bp, shmem_base +
11774                                     offsetof(struct shmem_region,
11775                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11776
11777                         tx = REG_RD(bp, shmem_base +
11778                                     offsetof(struct shmem_region,
11779                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11780                 } else {
11781                         rx = REG_RD(bp, shmem_base +
11782                                     offsetof(struct shmem_region,
11783                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11784
11785                         tx = REG_RD(bp, shmem_base +
11786                                     offsetof(struct shmem_region,
11787                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11788                 }
11789
11790                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11791                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11792
11793                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11794                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11795         }
11796 }
11797
11798 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11799                                     u8 phy_index, u8 port)
11800 {
11801         u32 ext_phy_config = 0;
11802         switch (phy_index) {
11803         case EXT_PHY1:
11804                 ext_phy_config = REG_RD(bp, shmem_base +
11805                                               offsetof(struct shmem_region,
11806                         dev_info.port_hw_config[port].external_phy_config));
11807                 break;
11808         case EXT_PHY2:
11809                 ext_phy_config = REG_RD(bp, shmem_base +
11810                                               offsetof(struct shmem_region,
11811                         dev_info.port_hw_config[port].external_phy_config2));
11812                 break;
11813         default:
11814                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11815                 return -EINVAL;
11816         }
11817
11818         return ext_phy_config;
11819 }
11820 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11821                                   struct bnx2x_phy *phy)
11822 {
11823         u32 phy_addr;
11824         u32 chip_id;
11825         u32 switch_cfg = (REG_RD(bp, shmem_base +
11826                                        offsetof(struct shmem_region,
11827                         dev_info.port_feature_config[port].link_config)) &
11828                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11829         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11830                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11831
11832         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11833         if (USES_WARPCORE(bp)) {
11834                 u32 serdes_net_if;
11835                 phy_addr = REG_RD(bp,
11836                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11837                 *phy = phy_warpcore;
11838                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11839                         phy->flags |= FLAGS_4_PORT_MODE;
11840                 else
11841                         phy->flags &= ~FLAGS_4_PORT_MODE;
11842                         /* Check Dual mode */
11843                 serdes_net_if = (REG_RD(bp, shmem_base +
11844                                         offsetof(struct shmem_region, dev_info.
11845                                         port_hw_config[port].default_cfg)) &
11846                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11847                 /* Set the appropriate supported and flags indications per
11848                  * interface type of the chip
11849                  */
11850                 switch (serdes_net_if) {
11851                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11852                         phy->supported &= (SUPPORTED_10baseT_Half |
11853                                            SUPPORTED_10baseT_Full |
11854                                            SUPPORTED_100baseT_Half |
11855                                            SUPPORTED_100baseT_Full |
11856                                            SUPPORTED_1000baseT_Full |
11857                                            SUPPORTED_FIBRE |
11858                                            SUPPORTED_Autoneg |
11859                                            SUPPORTED_Pause |
11860                                            SUPPORTED_Asym_Pause);
11861                         phy->media_type = ETH_PHY_BASE_T;
11862                         break;
11863                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11864                         phy->supported &= (SUPPORTED_1000baseT_Full |
11865                                            SUPPORTED_10000baseT_Full |
11866                                            SUPPORTED_FIBRE |
11867                                            SUPPORTED_Pause |
11868                                            SUPPORTED_Asym_Pause);
11869                         phy->media_type = ETH_PHY_XFP_FIBER;
11870                         break;
11871                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11872                         phy->supported &= (SUPPORTED_1000baseT_Full |
11873                                            SUPPORTED_10000baseT_Full |
11874                                            SUPPORTED_FIBRE |
11875                                            SUPPORTED_Pause |
11876                                            SUPPORTED_Asym_Pause);
11877                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11878                         break;
11879                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11880                         phy->media_type = ETH_PHY_KR;
11881                         phy->supported &= (SUPPORTED_1000baseT_Full |
11882                                            SUPPORTED_10000baseT_Full |
11883                                            SUPPORTED_FIBRE |
11884                                            SUPPORTED_Autoneg |
11885                                            SUPPORTED_Pause |
11886                                            SUPPORTED_Asym_Pause);
11887                         break;
11888                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11889                         phy->media_type = ETH_PHY_KR;
11890                         phy->flags |= FLAGS_WC_DUAL_MODE;
11891                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11892                                            SUPPORTED_FIBRE |
11893                                            SUPPORTED_Pause |
11894                                            SUPPORTED_Asym_Pause);
11895                         break;
11896                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11897                         phy->media_type = ETH_PHY_KR;
11898                         phy->flags |= FLAGS_WC_DUAL_MODE;
11899                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11900                                            SUPPORTED_10000baseT_Full |
11901                                            SUPPORTED_1000baseT_Full |
11902                                            SUPPORTED_Autoneg |
11903                                            SUPPORTED_FIBRE |
11904                                            SUPPORTED_Pause |
11905                                            SUPPORTED_Asym_Pause);
11906                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11907                         break;
11908                 default:
11909                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11910                                        serdes_net_if);
11911                         break;
11912                 }
11913
11914                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11915                  * was not set as expected. For B0, ECO will be enabled so there
11916                  * won't be an issue there
11917                  */
11918                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11919                         phy->flags |= FLAGS_MDC_MDIO_WA;
11920                 else
11921                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11922         } else {
11923                 switch (switch_cfg) {
11924                 case SWITCH_CFG_1G:
11925                         phy_addr = REG_RD(bp,
11926                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11927                                           port * 0x10);
11928                         *phy = phy_serdes;
11929                         break;
11930                 case SWITCH_CFG_10G:
11931                         phy_addr = REG_RD(bp,
11932                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11933                                           port * 0x18);
11934                         *phy = phy_xgxs;
11935                         break;
11936                 default:
11937                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11938                         return -EINVAL;
11939                 }
11940         }
11941         phy->addr = (u8)phy_addr;
11942         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11943                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11944                                             port);
11945         if (CHIP_IS_E2(bp))
11946                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11947         else
11948                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11949
11950         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11951                    port, phy->addr, phy->mdio_ctrl);
11952
11953         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11954         return 0;
11955 }
11956
11957 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11958                                   u8 phy_index,
11959                                   u32 shmem_base,
11960                                   u32 shmem2_base,
11961                                   u8 port,
11962                                   struct bnx2x_phy *phy)
11963 {
11964         u32 ext_phy_config, phy_type, config2;
11965         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11966         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11967                                                   phy_index, port);
11968         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11969         /* Select the phy type */
11970         switch (phy_type) {
11971         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11972                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11973                 *phy = phy_8073;
11974                 break;
11975         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11976                 *phy = phy_8705;
11977                 break;
11978         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11979                 *phy = phy_8706;
11980                 break;
11981         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11982                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11983                 *phy = phy_8726;
11984                 break;
11985         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11986                 /* BCM8727_NOC => BCM8727 no over current */
11987                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11988                 *phy = phy_8727;
11989                 phy->flags |= FLAGS_NOC;
11990                 break;
11991         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11992         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11993                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11994                 *phy = phy_8727;
11995                 break;
11996         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11997                 *phy = phy_8481;
11998                 break;
11999         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12000                 *phy = phy_84823;
12001                 break;
12002         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12003                 *phy = phy_84833;
12004                 break;
12005         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12006                 *phy = phy_84834;
12007                 break;
12008         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12009         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12010                 *phy = phy_54618se;
12011                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12012                         phy->flags |= FLAGS_EEE;
12013                 break;
12014         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12015                 *phy = phy_7101;
12016                 break;
12017         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12018                 *phy = phy_null;
12019                 return -EINVAL;
12020         default:
12021                 *phy = phy_null;
12022                 /* In case external PHY wasn't found */
12023                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12024                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12025                         return -EINVAL;
12026                 return 0;
12027         }
12028
12029         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12030         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12031
12032         /* The shmem address of the phy version is located on different
12033          * structures. In case this structure is too old, do not set
12034          * the address
12035          */
12036         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12037                                         dev_info.shared_hw_config.config2));
12038         if (phy_index == EXT_PHY1) {
12039                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12040                                 port_mb[port].ext_phy_fw_version);
12041
12042                 /* Check specific mdc mdio settings */
12043                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12044                         mdc_mdio_access = config2 &
12045                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12046         } else {
12047                 u32 size = REG_RD(bp, shmem2_base);
12048
12049                 if (size >
12050                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12051                         phy->ver_addr = shmem2_base +
12052                             offsetof(struct shmem2_region,
12053                                      ext_phy_fw_version2[port]);
12054                 }
12055                 /* Check specific mdc mdio settings */
12056                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12057                         mdc_mdio_access = (config2 &
12058                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12059                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12060                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12061         }
12062         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12063
12064         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12065              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12066             (phy->ver_addr)) {
12067                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12068                  * version lower than or equal to 1.39
12069                  */
12070                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12071                 if (((raw_ver & 0x7F) <= 39) &&
12072                     (((raw_ver & 0xF80) >> 7) <= 1))
12073                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12074                                             SUPPORTED_100baseT_Full);
12075         }
12076
12077         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12078                    phy_type, port, phy_index);
12079         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12080                    phy->addr, phy->mdio_ctrl);
12081         return 0;
12082 }
12083
12084 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12085                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12086 {
12087         int status = 0;
12088         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12089         if (phy_index == INT_PHY)
12090                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12091         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12092                                         port, phy);
12093         return status;
12094 }
12095
12096 static void bnx2x_phy_def_cfg(struct link_params *params,
12097                               struct bnx2x_phy *phy,
12098                               u8 phy_index)
12099 {
12100         struct bnx2x *bp = params->bp;
12101         u32 link_config;
12102         /* Populate the default phy configuration for MF mode */
12103         if (phy_index == EXT_PHY2) {
12104                 link_config = REG_RD(bp, params->shmem_base +
12105                                      offsetof(struct shmem_region, dev_info.
12106                         port_feature_config[params->port].link_config2));
12107                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12108                                              offsetof(struct shmem_region,
12109                                                       dev_info.
12110                         port_hw_config[params->port].speed_capability_mask2));
12111         } else {
12112                 link_config = REG_RD(bp, params->shmem_base +
12113                                      offsetof(struct shmem_region, dev_info.
12114                                 port_feature_config[params->port].link_config));
12115                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12116                                              offsetof(struct shmem_region,
12117                                                       dev_info.
12118                         port_hw_config[params->port].speed_capability_mask));
12119         }
12120         DP(NETIF_MSG_LINK,
12121            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12122            phy_index, link_config, phy->speed_cap_mask);
12123
12124         phy->req_duplex = DUPLEX_FULL;
12125         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12126         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12127                 phy->req_duplex = DUPLEX_HALF;
12128         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12129                 phy->req_line_speed = SPEED_10;
12130                 break;
12131         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12132                 phy->req_duplex = DUPLEX_HALF;
12133         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12134                 phy->req_line_speed = SPEED_100;
12135                 break;
12136         case PORT_FEATURE_LINK_SPEED_1G:
12137                 phy->req_line_speed = SPEED_1000;
12138                 break;
12139         case PORT_FEATURE_LINK_SPEED_2_5G:
12140                 phy->req_line_speed = SPEED_2500;
12141                 break;
12142         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12143                 phy->req_line_speed = SPEED_10000;
12144                 break;
12145         default:
12146                 phy->req_line_speed = SPEED_AUTO_NEG;
12147                 break;
12148         }
12149
12150         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12151         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12152                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12153                 break;
12154         case PORT_FEATURE_FLOW_CONTROL_TX:
12155                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12156                 break;
12157         case PORT_FEATURE_FLOW_CONTROL_RX:
12158                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12159                 break;
12160         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12161                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12162                 break;
12163         default:
12164                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12165                 break;
12166         }
12167 }
12168
12169 u32 bnx2x_phy_selection(struct link_params *params)
12170 {
12171         u32 phy_config_swapped, prio_cfg;
12172         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12173
12174         phy_config_swapped = params->multi_phy_config &
12175                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12176
12177         prio_cfg = params->multi_phy_config &
12178                         PORT_HW_CFG_PHY_SELECTION_MASK;
12179
12180         if (phy_config_swapped) {
12181                 switch (prio_cfg) {
12182                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12183                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12184                      break;
12185                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12186                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12187                      break;
12188                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12189                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12190                      break;
12191                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12192                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12193                      break;
12194                 }
12195         } else
12196                 return_cfg = prio_cfg;
12197
12198         return return_cfg;
12199 }
12200
12201 int bnx2x_phy_probe(struct link_params *params)
12202 {
12203         u8 phy_index, actual_phy_idx;
12204         u32 phy_config_swapped, sync_offset, media_types;
12205         struct bnx2x *bp = params->bp;
12206         struct bnx2x_phy *phy;
12207         params->num_phys = 0;
12208         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12209         phy_config_swapped = params->multi_phy_config &
12210                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12211
12212         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12213               phy_index++) {
12214                 actual_phy_idx = phy_index;
12215                 if (phy_config_swapped) {
12216                         if (phy_index == EXT_PHY1)
12217                                 actual_phy_idx = EXT_PHY2;
12218                         else if (phy_index == EXT_PHY2)
12219                                 actual_phy_idx = EXT_PHY1;
12220                 }
12221                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12222                                " actual_phy_idx %x\n", phy_config_swapped,
12223                            phy_index, actual_phy_idx);
12224                 phy = &params->phy[actual_phy_idx];
12225                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12226                                        params->shmem2_base, params->port,
12227                                        phy) != 0) {
12228                         params->num_phys = 0;
12229                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12230                                    phy_index);
12231                         for (phy_index = INT_PHY;
12232                               phy_index < MAX_PHYS;
12233                               phy_index++)
12234                                 *phy = phy_null;
12235                         return -EINVAL;
12236                 }
12237                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12238                         break;
12239
12240                 if (params->feature_config_flags &
12241                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12242                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12243
12244                 if (!(params->feature_config_flags &
12245                       FEATURE_CONFIG_MT_SUPPORT))
12246                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12247
12248                 sync_offset = params->shmem_base +
12249                         offsetof(struct shmem_region,
12250                         dev_info.port_hw_config[params->port].media_type);
12251                 media_types = REG_RD(bp, sync_offset);
12252
12253                 /* Update media type for non-PMF sync only for the first time
12254                  * In case the media type changes afterwards, it will be updated
12255                  * using the update_status function
12256                  */
12257                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12258                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12259                                      actual_phy_idx))) == 0) {
12260                         media_types |= ((phy->media_type &
12261                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12262                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12263                                  actual_phy_idx));
12264                 }
12265                 REG_WR(bp, sync_offset, media_types);
12266
12267                 bnx2x_phy_def_cfg(params, phy, phy_index);
12268                 params->num_phys++;
12269         }
12270
12271         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12272         return 0;
12273 }
12274
12275 static void bnx2x_init_bmac_loopback(struct link_params *params,
12276                                      struct link_vars *vars)
12277 {
12278         struct bnx2x *bp = params->bp;
12279                 vars->link_up = 1;
12280                 vars->line_speed = SPEED_10000;
12281                 vars->duplex = DUPLEX_FULL;
12282                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12283                 vars->mac_type = MAC_TYPE_BMAC;
12284
12285                 vars->phy_flags = PHY_XGXS_FLAG;
12286
12287                 bnx2x_xgxs_deassert(params);
12288
12289                 /* set bmac loopback */
12290                 bnx2x_bmac_enable(params, vars, 1, 1);
12291
12292                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12293 }
12294
12295 static void bnx2x_init_emac_loopback(struct link_params *params,
12296                                      struct link_vars *vars)
12297 {
12298         struct bnx2x *bp = params->bp;
12299                 vars->link_up = 1;
12300                 vars->line_speed = SPEED_1000;
12301                 vars->duplex = DUPLEX_FULL;
12302                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12303                 vars->mac_type = MAC_TYPE_EMAC;
12304
12305                 vars->phy_flags = PHY_XGXS_FLAG;
12306
12307                 bnx2x_xgxs_deassert(params);
12308                 /* set bmac loopback */
12309                 bnx2x_emac_enable(params, vars, 1);
12310                 bnx2x_emac_program(params, vars);
12311                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12312 }
12313
12314 static void bnx2x_init_xmac_loopback(struct link_params *params,
12315                                      struct link_vars *vars)
12316 {
12317         struct bnx2x *bp = params->bp;
12318         vars->link_up = 1;
12319         if (!params->req_line_speed[0])
12320                 vars->line_speed = SPEED_10000;
12321         else
12322                 vars->line_speed = params->req_line_speed[0];
12323         vars->duplex = DUPLEX_FULL;
12324         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12325         vars->mac_type = MAC_TYPE_XMAC;
12326         vars->phy_flags = PHY_XGXS_FLAG;
12327         /* Set WC to loopback mode since link is required to provide clock
12328          * to the XMAC in 20G mode
12329          */
12330         bnx2x_set_aer_mmd(params, &params->phy[0]);
12331         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12332         params->phy[INT_PHY].config_loopback(
12333                         &params->phy[INT_PHY],
12334                         params);
12335
12336         bnx2x_xmac_enable(params, vars, 1);
12337         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12338 }
12339
12340 static void bnx2x_init_umac_loopback(struct link_params *params,
12341                                      struct link_vars *vars)
12342 {
12343         struct bnx2x *bp = params->bp;
12344         vars->link_up = 1;
12345         vars->line_speed = SPEED_1000;
12346         vars->duplex = DUPLEX_FULL;
12347         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12348         vars->mac_type = MAC_TYPE_UMAC;
12349         vars->phy_flags = PHY_XGXS_FLAG;
12350         bnx2x_umac_enable(params, vars, 1);
12351
12352         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12353 }
12354
12355 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12356                                      struct link_vars *vars)
12357 {
12358         struct bnx2x *bp = params->bp;
12359         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12360         vars->link_up = 1;
12361         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12362         vars->duplex = DUPLEX_FULL;
12363         if (params->req_line_speed[0] == SPEED_1000)
12364                 vars->line_speed = SPEED_1000;
12365         else if ((params->req_line_speed[0] == SPEED_20000) ||
12366                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12367                 vars->line_speed = SPEED_20000;
12368         else
12369                 vars->line_speed = SPEED_10000;
12370
12371         if (!USES_WARPCORE(bp))
12372                 bnx2x_xgxs_deassert(params);
12373         bnx2x_link_initialize(params, vars);
12374
12375         if (params->req_line_speed[0] == SPEED_1000) {
12376                 if (USES_WARPCORE(bp))
12377                         bnx2x_umac_enable(params, vars, 0);
12378                 else {
12379                         bnx2x_emac_program(params, vars);
12380                         bnx2x_emac_enable(params, vars, 0);
12381                 }
12382         } else {
12383                 if (USES_WARPCORE(bp))
12384                         bnx2x_xmac_enable(params, vars, 0);
12385                 else
12386                         bnx2x_bmac_enable(params, vars, 0, 1);
12387         }
12388
12389         if (params->loopback_mode == LOOPBACK_XGXS) {
12390                 /* Set 10G XGXS loopback */
12391                 int_phy->config_loopback(int_phy, params);
12392         } else {
12393                 /* Set external phy loopback */
12394                 u8 phy_index;
12395                 for (phy_index = EXT_PHY1;
12396                       phy_index < params->num_phys; phy_index++)
12397                         if (params->phy[phy_index].config_loopback)
12398                                 params->phy[phy_index].config_loopback(
12399                                         &params->phy[phy_index],
12400                                         params);
12401         }
12402         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12403
12404         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12405 }
12406
12407 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12408 {
12409         struct bnx2x *bp = params->bp;
12410         u8 val = en * 0x1F;
12411
12412         /* Open / close the gate between the NIG and the BRB */
12413         if (!CHIP_IS_E1x(bp))
12414                 val |= en * 0x20;
12415         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12416
12417         if (!CHIP_IS_E1(bp)) {
12418                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12419                        en*0x3);
12420         }
12421
12422         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12423                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12424 }
12425 static int bnx2x_avoid_link_flap(struct link_params *params,
12426                                             struct link_vars *vars)
12427 {
12428         u32 phy_idx;
12429         u32 dont_clear_stat, lfa_sts;
12430         struct bnx2x *bp = params->bp;
12431
12432         /* Sync the link parameters */
12433         bnx2x_link_status_update(params, vars);
12434
12435         /*
12436          * The module verification was already done by previous link owner,
12437          * so this call is meant only to get warning message
12438          */
12439
12440         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12441                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12442                 if (phy->phy_specific_func) {
12443                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12444                         phy->phy_specific_func(phy, params, PHY_INIT);
12445                 }
12446                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12447                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12448                     (phy->media_type == ETH_PHY_DA_TWINAX))
12449                         bnx2x_verify_sfp_module(phy, params);
12450         }
12451         lfa_sts = REG_RD(bp, params->lfa_base +
12452                          offsetof(struct shmem_lfa,
12453                                   lfa_sts));
12454
12455         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12456
12457         /* Re-enable the NIG/MAC */
12458         if (CHIP_IS_E3(bp)) {
12459                 if (!dont_clear_stat) {
12460                         REG_WR(bp, GRCBASE_MISC +
12461                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12462                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12463                                 params->port));
12464                         REG_WR(bp, GRCBASE_MISC +
12465                                MISC_REGISTERS_RESET_REG_2_SET,
12466                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12467                                 params->port));
12468                 }
12469                 if (vars->line_speed < SPEED_10000)
12470                         bnx2x_umac_enable(params, vars, 0);
12471                 else
12472                         bnx2x_xmac_enable(params, vars, 0);
12473         } else {
12474                 if (vars->line_speed < SPEED_10000)
12475                         bnx2x_emac_enable(params, vars, 0);
12476                 else
12477                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12478         }
12479
12480         /* Increment LFA count */
12481         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12482                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12483                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12484                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12485         /* Clear link flap reason */
12486         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12487
12488         REG_WR(bp, params->lfa_base +
12489                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12490
12491         /* Disable NIG DRAIN */
12492         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12493
12494         /* Enable interrupts */
12495         bnx2x_link_int_enable(params);
12496         return 0;
12497 }
12498
12499 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12500                                          struct link_vars *vars,
12501                                          int lfa_status)
12502 {
12503         u32 lfa_sts, cfg_idx, tmp_val;
12504         struct bnx2x *bp = params->bp;
12505
12506         bnx2x_link_reset(params, vars, 1);
12507
12508         if (!params->lfa_base)
12509                 return;
12510         /* Store the new link parameters */
12511         REG_WR(bp, params->lfa_base +
12512                offsetof(struct shmem_lfa, req_duplex),
12513                params->req_duplex[0] | (params->req_duplex[1] << 16));
12514
12515         REG_WR(bp, params->lfa_base +
12516                offsetof(struct shmem_lfa, req_flow_ctrl),
12517                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12518
12519         REG_WR(bp, params->lfa_base +
12520                offsetof(struct shmem_lfa, req_line_speed),
12521                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12522
12523         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12524                 REG_WR(bp, params->lfa_base +
12525                        offsetof(struct shmem_lfa,
12526                                 speed_cap_mask[cfg_idx]),
12527                        params->speed_cap_mask[cfg_idx]);
12528         }
12529
12530         tmp_val = REG_RD(bp, params->lfa_base +
12531                          offsetof(struct shmem_lfa, additional_config));
12532         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12533         tmp_val |= params->req_fc_auto_adv;
12534
12535         REG_WR(bp, params->lfa_base +
12536                offsetof(struct shmem_lfa, additional_config), tmp_val);
12537
12538         lfa_sts = REG_RD(bp, params->lfa_base +
12539                          offsetof(struct shmem_lfa, lfa_sts));
12540
12541         /* Clear the "Don't Clear Statistics" bit, and set reason */
12542         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12543
12544         /* Set link flap reason */
12545         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12546         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12547                     LFA_LINK_FLAP_REASON_OFFSET);
12548
12549         /* Increment link flap counter */
12550         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12551                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12552                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12553                     << LINK_FLAP_COUNT_OFFSET));
12554         REG_WR(bp, params->lfa_base +
12555                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12556         /* Proceed with regular link initialization */
12557 }
12558
12559 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12560 {
12561         int lfa_status;
12562         struct bnx2x *bp = params->bp;
12563         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12564         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12565                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12566         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12567                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12568         vars->link_status = 0;
12569         vars->phy_link_up = 0;
12570         vars->link_up = 0;
12571         vars->line_speed = 0;
12572         vars->duplex = DUPLEX_FULL;
12573         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12574         vars->mac_type = MAC_TYPE_NONE;
12575         vars->phy_flags = 0;
12576         vars->check_kr2_recovery_cnt = 0;
12577         params->link_flags = PHY_INITIALIZED;
12578         /* Driver opens NIG-BRB filters */
12579         bnx2x_set_rx_filter(params, 1);
12580         /* Check if link flap can be avoided */
12581         lfa_status = bnx2x_check_lfa(params);
12582
12583         if (lfa_status == 0) {
12584                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12585                 return bnx2x_avoid_link_flap(params, vars);
12586         }
12587
12588         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12589                        lfa_status);
12590         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12591
12592         /* Disable attentions */
12593         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12594                        (NIG_MASK_XGXS0_LINK_STATUS |
12595                         NIG_MASK_XGXS0_LINK10G |
12596                         NIG_MASK_SERDES0_LINK_STATUS |
12597                         NIG_MASK_MI_INT));
12598
12599         bnx2x_emac_init(params, vars);
12600
12601         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12602                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12603
12604         if (params->num_phys == 0) {
12605                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12606                 return -EINVAL;
12607         }
12608         set_phy_vars(params, vars);
12609
12610         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12611         switch (params->loopback_mode) {
12612         case LOOPBACK_BMAC:
12613                 bnx2x_init_bmac_loopback(params, vars);
12614                 break;
12615         case LOOPBACK_EMAC:
12616                 bnx2x_init_emac_loopback(params, vars);
12617                 break;
12618         case LOOPBACK_XMAC:
12619                 bnx2x_init_xmac_loopback(params, vars);
12620                 break;
12621         case LOOPBACK_UMAC:
12622                 bnx2x_init_umac_loopback(params, vars);
12623                 break;
12624         case LOOPBACK_XGXS:
12625         case LOOPBACK_EXT_PHY:
12626                 bnx2x_init_xgxs_loopback(params, vars);
12627                 break;
12628         default:
12629                 if (!CHIP_IS_E3(bp)) {
12630                         if (params->switch_cfg == SWITCH_CFG_10G)
12631                                 bnx2x_xgxs_deassert(params);
12632                         else
12633                                 bnx2x_serdes_deassert(bp, params->port);
12634                 }
12635                 bnx2x_link_initialize(params, vars);
12636                 msleep(30);
12637                 bnx2x_link_int_enable(params);
12638                 break;
12639         }
12640         bnx2x_update_mng(params, vars->link_status);
12641
12642         bnx2x_update_mng_eee(params, vars->eee_status);
12643         return 0;
12644 }
12645
12646 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12647                      u8 reset_ext_phy)
12648 {
12649         struct bnx2x *bp = params->bp;
12650         u8 phy_index, port = params->port, clear_latch_ind = 0;
12651         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12652         /* Disable attentions */
12653         vars->link_status = 0;
12654         bnx2x_update_mng(params, vars->link_status);
12655         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12656                               SHMEM_EEE_ACTIVE_BIT);
12657         bnx2x_update_mng_eee(params, vars->eee_status);
12658         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12659                        (NIG_MASK_XGXS0_LINK_STATUS |
12660                         NIG_MASK_XGXS0_LINK10G |
12661                         NIG_MASK_SERDES0_LINK_STATUS |
12662                         NIG_MASK_MI_INT));
12663
12664         /* Activate nig drain */
12665         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12666
12667         /* Disable nig egress interface */
12668         if (!CHIP_IS_E3(bp)) {
12669                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12670                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12671         }
12672
12673                 if (!CHIP_IS_E3(bp)) {
12674                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12675                 } else {
12676                         bnx2x_set_xmac_rxtx(params, 0);
12677                         bnx2x_set_umac_rxtx(params, 0);
12678                 }
12679         /* Disable emac */
12680         if (!CHIP_IS_E3(bp))
12681                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12682
12683         usleep_range(10000, 20000);
12684         /* The PHY reset is controlled by GPIO 1
12685          * Hold it as vars low
12686          */
12687          /* Clear link led */
12688         bnx2x_set_mdio_emac_per_phy(bp, params);
12689         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12690
12691         if (reset_ext_phy) {
12692                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12693                       phy_index++) {
12694                         if (params->phy[phy_index].link_reset) {
12695                                 bnx2x_set_aer_mmd(params,
12696                                                   &params->phy[phy_index]);
12697                                 params->phy[phy_index].link_reset(
12698                                         &params->phy[phy_index],
12699                                         params);
12700                         }
12701                         if (params->phy[phy_index].flags &
12702                             FLAGS_REARM_LATCH_SIGNAL)
12703                                 clear_latch_ind = 1;
12704                 }
12705         }
12706
12707         if (clear_latch_ind) {
12708                 /* Clear latching indication */
12709                 bnx2x_rearm_latch_signal(bp, port, 0);
12710                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12711                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12712         }
12713         if (params->phy[INT_PHY].link_reset)
12714                 params->phy[INT_PHY].link_reset(
12715                         &params->phy[INT_PHY], params);
12716
12717         /* Disable nig ingress interface */
12718         if (!CHIP_IS_E3(bp)) {
12719                 /* Reset BigMac */
12720                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12721                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12722                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12723                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12724         } else {
12725                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12726                 bnx2x_set_xumac_nig(params, 0, 0);
12727                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12728                     MISC_REGISTERS_RESET_REG_2_XMAC)
12729                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12730                                XMAC_CTRL_REG_SOFT_RESET);
12731         }
12732         vars->link_up = 0;
12733         vars->phy_flags = 0;
12734         return 0;
12735 }
12736 int bnx2x_lfa_reset(struct link_params *params,
12737                                struct link_vars *vars)
12738 {
12739         struct bnx2x *bp = params->bp;
12740         vars->link_up = 0;
12741         vars->phy_flags = 0;
12742         params->link_flags &= ~PHY_INITIALIZED;
12743         if (!params->lfa_base)
12744                 return bnx2x_link_reset(params, vars, 1);
12745         /*
12746          * Activate NIG drain so that during this time the device won't send
12747          * anything while it is unable to response.
12748          */
12749         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12750
12751         /*
12752          * Close gracefully the gate from BMAC to NIG such that no half packets
12753          * are passed.
12754          */
12755         if (!CHIP_IS_E3(bp))
12756                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12757
12758         if (CHIP_IS_E3(bp)) {
12759                 bnx2x_set_xmac_rxtx(params, 0);
12760                 bnx2x_set_umac_rxtx(params, 0);
12761         }
12762         /* Wait 10ms for the pipe to clean up*/
12763         usleep_range(10000, 20000);
12764
12765         /* Clean the NIG-BRB using the network filters in a way that will
12766          * not cut a packet in the middle.
12767          */
12768         bnx2x_set_rx_filter(params, 0);
12769
12770         /*
12771          * Re-open the gate between the BMAC and the NIG, after verifying the
12772          * gate to the BRB is closed, otherwise packets may arrive to the
12773          * firmware before driver had initialized it. The target is to achieve
12774          * minimum management protocol down time.
12775          */
12776         if (!CHIP_IS_E3(bp))
12777                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12778
12779         if (CHIP_IS_E3(bp)) {
12780                 bnx2x_set_xmac_rxtx(params, 1);
12781                 bnx2x_set_umac_rxtx(params, 1);
12782         }
12783         /* Disable NIG drain */
12784         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12785         return 0;
12786 }
12787
12788 /****************************************************************************/
12789 /*                              Common function                             */
12790 /****************************************************************************/
12791 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12792                                       u32 shmem_base_path[],
12793                                       u32 shmem2_base_path[], u8 phy_index,
12794                                       u32 chip_id)
12795 {
12796         struct bnx2x_phy phy[PORT_MAX];
12797         struct bnx2x_phy *phy_blk[PORT_MAX];
12798         u16 val;
12799         s8 port = 0;
12800         s8 port_of_path = 0;
12801         u32 swap_val, swap_override;
12802         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12803         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12804         port ^= (swap_val && swap_override);
12805         bnx2x_ext_phy_hw_reset(bp, port);
12806         /* PART1 - Reset both phys */
12807         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12808                 u32 shmem_base, shmem2_base;
12809                 /* In E2, same phy is using for port0 of the two paths */
12810                 if (CHIP_IS_E1x(bp)) {
12811                         shmem_base = shmem_base_path[0];
12812                         shmem2_base = shmem2_base_path[0];
12813                         port_of_path = port;
12814                 } else {
12815                         shmem_base = shmem_base_path[port];
12816                         shmem2_base = shmem2_base_path[port];
12817                         port_of_path = 0;
12818                 }
12819
12820                 /* Extract the ext phy address for the port */
12821                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12822                                        port_of_path, &phy[port]) !=
12823                     0) {
12824                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12825                         return -EINVAL;
12826                 }
12827                 /* Disable attentions */
12828                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12829                                port_of_path*4,
12830                                (NIG_MASK_XGXS0_LINK_STATUS |
12831                                 NIG_MASK_XGXS0_LINK10G |
12832                                 NIG_MASK_SERDES0_LINK_STATUS |
12833                                 NIG_MASK_MI_INT));
12834
12835                 /* Need to take the phy out of low power mode in order
12836                  * to write to access its registers
12837                  */
12838                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12839                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12840                                port);
12841
12842                 /* Reset the phy */
12843                 bnx2x_cl45_write(bp, &phy[port],
12844                                  MDIO_PMA_DEVAD,
12845                                  MDIO_PMA_REG_CTRL,
12846                                  1<<15);
12847         }
12848
12849         /* Add delay of 150ms after reset */
12850         msleep(150);
12851
12852         if (phy[PORT_0].addr & 0x1) {
12853                 phy_blk[PORT_0] = &(phy[PORT_1]);
12854                 phy_blk[PORT_1] = &(phy[PORT_0]);
12855         } else {
12856                 phy_blk[PORT_0] = &(phy[PORT_0]);
12857                 phy_blk[PORT_1] = &(phy[PORT_1]);
12858         }
12859
12860         /* PART2 - Download firmware to both phys */
12861         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12862                 if (CHIP_IS_E1x(bp))
12863                         port_of_path = port;
12864                 else
12865                         port_of_path = 0;
12866
12867                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12868                            phy_blk[port]->addr);
12869                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12870                                                       port_of_path))
12871                         return -EINVAL;
12872
12873                 /* Only set bit 10 = 1 (Tx power down) */
12874                 bnx2x_cl45_read(bp, phy_blk[port],
12875                                 MDIO_PMA_DEVAD,
12876                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12877
12878                 /* Phase1 of TX_POWER_DOWN reset */
12879                 bnx2x_cl45_write(bp, phy_blk[port],
12880                                  MDIO_PMA_DEVAD,
12881                                  MDIO_PMA_REG_TX_POWER_DOWN,
12882                                  (val | 1<<10));
12883         }
12884
12885         /* Toggle Transmitter: Power down and then up with 600ms delay
12886          * between
12887          */
12888         msleep(600);
12889
12890         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12891         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12892                 /* Phase2 of POWER_DOWN_RESET */
12893                 /* Release bit 10 (Release Tx power down) */
12894                 bnx2x_cl45_read(bp, phy_blk[port],
12895                                 MDIO_PMA_DEVAD,
12896                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12897
12898                 bnx2x_cl45_write(bp, phy_blk[port],
12899                                 MDIO_PMA_DEVAD,
12900                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12901                 usleep_range(15000, 30000);
12902
12903                 /* Read modify write the SPI-ROM version select register */
12904                 bnx2x_cl45_read(bp, phy_blk[port],
12905                                 MDIO_PMA_DEVAD,
12906                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12907                 bnx2x_cl45_write(bp, phy_blk[port],
12908                                  MDIO_PMA_DEVAD,
12909                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12910
12911                 /* set GPIO2 back to LOW */
12912                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12913                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12914         }
12915         return 0;
12916 }
12917 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12918                                       u32 shmem_base_path[],
12919                                       u32 shmem2_base_path[], u8 phy_index,
12920                                       u32 chip_id)
12921 {
12922         u32 val;
12923         s8 port;
12924         struct bnx2x_phy phy;
12925         /* Use port1 because of the static port-swap */
12926         /* Enable the module detection interrupt */
12927         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12928         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12929                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12930         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12931
12932         bnx2x_ext_phy_hw_reset(bp, 0);
12933         usleep_range(5000, 10000);
12934         for (port = 0; port < PORT_MAX; port++) {
12935                 u32 shmem_base, shmem2_base;
12936
12937                 /* In E2, same phy is using for port0 of the two paths */
12938                 if (CHIP_IS_E1x(bp)) {
12939                         shmem_base = shmem_base_path[0];
12940                         shmem2_base = shmem2_base_path[0];
12941                 } else {
12942                         shmem_base = shmem_base_path[port];
12943                         shmem2_base = shmem2_base_path[port];
12944                 }
12945                 /* Extract the ext phy address for the port */
12946                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12947                                        port, &phy) !=
12948                     0) {
12949                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12950                         return -EINVAL;
12951                 }
12952
12953                 /* Reset phy*/
12954                 bnx2x_cl45_write(bp, &phy,
12955                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12956
12957
12958                 /* Set fault module detected LED on */
12959                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12960                                MISC_REGISTERS_GPIO_HIGH,
12961                                port);
12962         }
12963
12964         return 0;
12965 }
12966 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12967                                          u8 *io_gpio, u8 *io_port)
12968 {
12969
12970         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12971                                           offsetof(struct shmem_region,
12972                                 dev_info.port_hw_config[PORT_0].default_cfg));
12973         switch (phy_gpio_reset) {
12974         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12975                 *io_gpio = 0;
12976                 *io_port = 0;
12977                 break;
12978         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12979                 *io_gpio = 1;
12980                 *io_port = 0;
12981                 break;
12982         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12983                 *io_gpio = 2;
12984                 *io_port = 0;
12985                 break;
12986         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12987                 *io_gpio = 3;
12988                 *io_port = 0;
12989                 break;
12990         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12991                 *io_gpio = 0;
12992                 *io_port = 1;
12993                 break;
12994         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12995                 *io_gpio = 1;
12996                 *io_port = 1;
12997                 break;
12998         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12999                 *io_gpio = 2;
13000                 *io_port = 1;
13001                 break;
13002         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13003                 *io_gpio = 3;
13004                 *io_port = 1;
13005                 break;
13006         default:
13007                 /* Don't override the io_gpio and io_port */
13008                 break;
13009         }
13010 }
13011
13012 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13013                                       u32 shmem_base_path[],
13014                                       u32 shmem2_base_path[], u8 phy_index,
13015                                       u32 chip_id)
13016 {
13017         s8 port, reset_gpio;
13018         u32 swap_val, swap_override;
13019         struct bnx2x_phy phy[PORT_MAX];
13020         struct bnx2x_phy *phy_blk[PORT_MAX];
13021         s8 port_of_path;
13022         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13023         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13024
13025         reset_gpio = MISC_REGISTERS_GPIO_1;
13026         port = 1;
13027
13028         /* Retrieve the reset gpio/port which control the reset.
13029          * Default is GPIO1, PORT1
13030          */
13031         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13032                                      (u8 *)&reset_gpio, (u8 *)&port);
13033
13034         /* Calculate the port based on port swap */
13035         port ^= (swap_val && swap_override);
13036
13037         /* Initiate PHY reset*/
13038         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13039                        port);
13040         usleep_range(1000, 2000);
13041         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13042                        port);
13043
13044         usleep_range(5000, 10000);
13045
13046         /* PART1 - Reset both phys */
13047         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13048                 u32 shmem_base, shmem2_base;
13049
13050                 /* In E2, same phy is using for port0 of the two paths */
13051                 if (CHIP_IS_E1x(bp)) {
13052                         shmem_base = shmem_base_path[0];
13053                         shmem2_base = shmem2_base_path[0];
13054                         port_of_path = port;
13055                 } else {
13056                         shmem_base = shmem_base_path[port];
13057                         shmem2_base = shmem2_base_path[port];
13058                         port_of_path = 0;
13059                 }
13060
13061                 /* Extract the ext phy address for the port */
13062                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13063                                        port_of_path, &phy[port]) !=
13064                                        0) {
13065                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13066                         return -EINVAL;
13067                 }
13068                 /* disable attentions */
13069                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13070                                port_of_path*4,
13071                                (NIG_MASK_XGXS0_LINK_STATUS |
13072                                 NIG_MASK_XGXS0_LINK10G |
13073                                 NIG_MASK_SERDES0_LINK_STATUS |
13074                                 NIG_MASK_MI_INT));
13075
13076
13077                 /* Reset the phy */
13078                 bnx2x_cl45_write(bp, &phy[port],
13079                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13080         }
13081
13082         /* Add delay of 150ms after reset */
13083         msleep(150);
13084         if (phy[PORT_0].addr & 0x1) {
13085                 phy_blk[PORT_0] = &(phy[PORT_1]);
13086                 phy_blk[PORT_1] = &(phy[PORT_0]);
13087         } else {
13088                 phy_blk[PORT_0] = &(phy[PORT_0]);
13089                 phy_blk[PORT_1] = &(phy[PORT_1]);
13090         }
13091         /* PART2 - Download firmware to both phys */
13092         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13093                 if (CHIP_IS_E1x(bp))
13094                         port_of_path = port;
13095                 else
13096                         port_of_path = 0;
13097                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13098                            phy_blk[port]->addr);
13099                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13100                                                       port_of_path))
13101                         return -EINVAL;
13102                 /* Disable PHY transmitter output */
13103                 bnx2x_cl45_write(bp, phy_blk[port],
13104                                  MDIO_PMA_DEVAD,
13105                                  MDIO_PMA_REG_TX_DISABLE, 1);
13106
13107         }
13108         return 0;
13109 }
13110
13111 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13112                                                 u32 shmem_base_path[],
13113                                                 u32 shmem2_base_path[],
13114                                                 u8 phy_index,
13115                                                 u32 chip_id)
13116 {
13117         u8 reset_gpios;
13118         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13119         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13120         udelay(10);
13121         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13122         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13123                 reset_gpios);
13124         return 0;
13125 }
13126
13127 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13128                                      u32 shmem2_base_path[], u8 phy_index,
13129                                      u32 ext_phy_type, u32 chip_id)
13130 {
13131         int rc = 0;
13132
13133         switch (ext_phy_type) {
13134         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13135                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13136                                                 shmem2_base_path,
13137                                                 phy_index, chip_id);
13138                 break;
13139         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13140         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13141         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13142                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13143                                                 shmem2_base_path,
13144                                                 phy_index, chip_id);
13145                 break;
13146
13147         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13148                 /* GPIO1 affects both ports, so there's need to pull
13149                  * it for single port alone
13150                  */
13151                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13152                                                 shmem2_base_path,
13153                                                 phy_index, chip_id);
13154                 break;
13155         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13156         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13157                 /* GPIO3's are linked, and so both need to be toggled
13158                  * to obtain required 2us pulse.
13159                  */
13160                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13161                                                 shmem2_base_path,
13162                                                 phy_index, chip_id);
13163                 break;
13164         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13165                 rc = -EINVAL;
13166                 break;
13167         default:
13168                 DP(NETIF_MSG_LINK,
13169                            "ext_phy 0x%x common init not required\n",
13170                            ext_phy_type);
13171                 break;
13172         }
13173
13174         if (rc)
13175                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13176                                       " Port %d\n",
13177                          0);
13178         return rc;
13179 }
13180
13181 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13182                           u32 shmem2_base_path[], u32 chip_id)
13183 {
13184         int rc = 0;
13185         u32 phy_ver, val;
13186         u8 phy_index = 0;
13187         u32 ext_phy_type, ext_phy_config;
13188
13189         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13190         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13191         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13192         if (CHIP_IS_E3(bp)) {
13193                 /* Enable EPIO */
13194                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13195                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13196         }
13197         /* Check if common init was already done */
13198         phy_ver = REG_RD(bp, shmem_base_path[0] +
13199                          offsetof(struct shmem_region,
13200                                   port_mb[PORT_0].ext_phy_fw_version));
13201         if (phy_ver) {
13202                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13203                                phy_ver);
13204                 return 0;
13205         }
13206
13207         /* Read the ext_phy_type for arbitrary port(0) */
13208         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13209               phy_index++) {
13210                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13211                                                           shmem_base_path[0],
13212                                                           phy_index, 0);
13213                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13214                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13215                                                 shmem2_base_path,
13216                                                 phy_index, ext_phy_type,
13217                                                 chip_id);
13218         }
13219         return rc;
13220 }
13221
13222 static void bnx2x_check_over_curr(struct link_params *params,
13223                                   struct link_vars *vars)
13224 {
13225         struct bnx2x *bp = params->bp;
13226         u32 cfg_pin;
13227         u8 port = params->port;
13228         u32 pin_val;
13229
13230         cfg_pin = (REG_RD(bp, params->shmem_base +
13231                           offsetof(struct shmem_region,
13232                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13233                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13234                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13235
13236         /* Ignore check if no external input PIN available */
13237         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13238                 return;
13239
13240         if (!pin_val) {
13241                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13242                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13243                                             " been detected and the power to "
13244                                             "that SFP+ module has been removed"
13245                                             " to prevent failure of the card."
13246                                             " Please remove the SFP+ module and"
13247                                             " restart the system to clear this"
13248                                             " error.\n",
13249                          params->port);
13250                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13251                         bnx2x_warpcore_power_module(params, 0);
13252                 }
13253         } else
13254                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13255 }
13256
13257 /* Returns 0 if no change occured since last check; 1 otherwise. */
13258 static u8 bnx2x_analyze_link_error(struct link_params *params,
13259                                     struct link_vars *vars, u32 status,
13260                                     u32 phy_flag, u32 link_flag, u8 notify)
13261 {
13262         struct bnx2x *bp = params->bp;
13263         /* Compare new value with previous value */
13264         u8 led_mode;
13265         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13266
13267         if ((status ^ old_status) == 0)
13268                 return 0;
13269
13270         /* If values differ */
13271         switch (phy_flag) {
13272         case PHY_HALF_OPEN_CONN_FLAG:
13273                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13274                 break;
13275         case PHY_SFP_TX_FAULT_FLAG:
13276                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13277                 break;
13278         default:
13279                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13280         }
13281         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13282            old_status, status);
13283
13284         /* a. Update shmem->link_status accordingly
13285          * b. Update link_vars->link_up
13286          */
13287         if (status) {
13288                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13289                 vars->link_status |= link_flag;
13290                 vars->link_up = 0;
13291                 vars->phy_flags |= phy_flag;
13292
13293                 /* activate nig drain */
13294                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13295                 /* Set LED mode to off since the PHY doesn't know about these
13296                  * errors
13297                  */
13298                 led_mode = LED_MODE_OFF;
13299         } else {
13300                 vars->link_status |= LINK_STATUS_LINK_UP;
13301                 vars->link_status &= ~link_flag;
13302                 vars->link_up = 1;
13303                 vars->phy_flags &= ~phy_flag;
13304                 led_mode = LED_MODE_OPER;
13305
13306                 /* Clear nig drain */
13307                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13308         }
13309         bnx2x_sync_link(params, vars);
13310         /* Update the LED according to the link state */
13311         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13312
13313         /* Update link status in the shared memory */
13314         bnx2x_update_mng(params, vars->link_status);
13315
13316         /* C. Trigger General Attention */
13317         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13318         if (notify)
13319                 bnx2x_notify_link_changed(bp);
13320
13321         return 1;
13322 }
13323
13324 /******************************************************************************
13325 * Description:
13326 *       This function checks for half opened connection change indication.
13327 *       When such change occurs, it calls the bnx2x_analyze_link_error
13328 *       to check if Remote Fault is set or cleared. Reception of remote fault
13329 *       status message in the MAC indicates that the peer's MAC has detected
13330 *       a fault, for example, due to break in the TX side of fiber.
13331 *
13332 ******************************************************************************/
13333 int bnx2x_check_half_open_conn(struct link_params *params,
13334                                 struct link_vars *vars,
13335                                 u8 notify)
13336 {
13337         struct bnx2x *bp = params->bp;
13338         u32 lss_status = 0;
13339         u32 mac_base;
13340         /* In case link status is physically up @ 10G do */
13341         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13342             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13343                 return 0;
13344
13345         if (CHIP_IS_E3(bp) &&
13346             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13347               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13348                 /* Check E3 XMAC */
13349                 /* Note that link speed cannot be queried here, since it may be
13350                  * zero while link is down. In case UMAC is active, LSS will
13351                  * simply not be set
13352                  */
13353                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13354
13355                 /* Clear stick bits (Requires rising edge) */
13356                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13357                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13358                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13359                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13360                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13361                         lss_status = 1;
13362
13363                 bnx2x_analyze_link_error(params, vars, lss_status,
13364                                          PHY_HALF_OPEN_CONN_FLAG,
13365                                          LINK_STATUS_NONE, notify);
13366         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13367                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13368                 /* Check E1X / E2 BMAC */
13369                 u32 lss_status_reg;
13370                 u32 wb_data[2];
13371                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13372                         NIG_REG_INGRESS_BMAC0_MEM;
13373                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13374                 if (CHIP_IS_E2(bp))
13375                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13376                 else
13377                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13378
13379                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13380                 lss_status = (wb_data[0] > 0);
13381
13382                 bnx2x_analyze_link_error(params, vars, lss_status,
13383                                          PHY_HALF_OPEN_CONN_FLAG,
13384                                          LINK_STATUS_NONE, notify);
13385         }
13386         return 0;
13387 }
13388 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13389                                          struct link_params *params,
13390                                          struct link_vars *vars)
13391 {
13392         struct bnx2x *bp = params->bp;
13393         u32 cfg_pin, value = 0;
13394         u8 led_change, port = params->port;
13395
13396         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13397         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13398                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13399                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13400                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13401
13402         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13403                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13404                 return;
13405         }
13406
13407         led_change = bnx2x_analyze_link_error(params, vars, value,
13408                                               PHY_SFP_TX_FAULT_FLAG,
13409                                               LINK_STATUS_SFP_TX_FAULT, 1);
13410
13411         if (led_change) {
13412                 /* Change TX_Fault led, set link status for further syncs */
13413                 u8 led_mode;
13414
13415                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13416                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13417                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13418                 } else {
13419                         led_mode = MISC_REGISTERS_GPIO_LOW;
13420                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13421                 }
13422
13423                 /* If module is unapproved, led should be on regardless */
13424                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13425                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13426                            led_mode);
13427                         bnx2x_set_e3_module_fault_led(params, led_mode);
13428                 }
13429         }
13430 }
13431 static void bnx2x_disable_kr2(struct link_params *params,
13432                               struct link_vars *vars,
13433                               struct bnx2x_phy *phy)
13434 {
13435         struct bnx2x *bp = params->bp;
13436         int i;
13437         static struct bnx2x_reg_set reg_set[] = {
13438                 /* Step 1 - Program the TX/RX alignment markers */
13439                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13440                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13441                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13442                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13443                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13444                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13445                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13446                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13447                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13448                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13449                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13450                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13451                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13452                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13453                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13454         };
13455         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13456
13457         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
13458                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13459                                  reg_set[i].val);
13460         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13461         bnx2x_update_link_attr(params, vars->link_attr_sync);
13462
13463         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
13464         /* Restart AN on leading lane */
13465         bnx2x_warpcore_restart_AN_KR(phy, params);
13466 }
13467
13468 static void bnx2x_kr2_recovery(struct link_params *params,
13469                                struct link_vars *vars,
13470                                struct bnx2x_phy *phy)
13471 {
13472         struct bnx2x *bp = params->bp;
13473         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13474         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13475         bnx2x_warpcore_restart_AN_KR(phy, params);
13476 }
13477
13478 static void bnx2x_check_kr2_wa(struct link_params *params,
13479                                struct link_vars *vars,
13480                                struct bnx2x_phy *phy)
13481 {
13482         struct bnx2x *bp = params->bp;
13483         u16 base_page, next_page, not_kr2_device, lane;
13484         int sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13485
13486         if (!sigdet) {
13487                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
13488                         bnx2x_kr2_recovery(params, vars, phy);
13489                 return;
13490         }
13491
13492         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13493          * since some switches tend to reinit the AN process and clear the
13494          * advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13495          * and recovered many times
13496          */
13497         if (vars->check_kr2_recovery_cnt > 0) {
13498                 vars->check_kr2_recovery_cnt--;
13499                 return;
13500         }
13501         lane = bnx2x_get_warpcore_lane(phy, params);
13502         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13503                           MDIO_AER_BLOCK_AER_REG, lane);
13504         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13505                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13506         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13507                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13508         bnx2x_set_aer_mmd(params, phy);
13509
13510         /* CL73 has not begun yet */
13511         if (base_page == 0) {
13512                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
13513                         bnx2x_kr2_recovery(params, vars, phy);
13514                 return;
13515         }
13516
13517         /* In case NP bit is not set in the BasePage, or it is set,
13518          * but only KX is advertised, declare this link partner as non-KR2
13519          * device.
13520          */
13521         not_kr2_device = (((base_page & 0x8000) == 0) ||
13522                           (((base_page & 0x8000) &&
13523                             ((next_page & 0xe0) == 0x2))));
13524
13525         /* In case KR2 is already disabled, check if we need to re-enable it */
13526         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13527                 if (!not_kr2_device) {
13528                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13529                                        next_page);
13530                         bnx2x_kr2_recovery(params, vars, phy);
13531                 }
13532                 return;
13533         }
13534         /* KR2 is enabled, but not KR2 device */
13535         if (not_kr2_device) {
13536                 /* Disable KR2 on both lanes */
13537                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13538                 bnx2x_disable_kr2(params, vars, phy);
13539                 return;
13540         }
13541 }
13542
13543 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13544 {
13545         u16 phy_idx;
13546         struct bnx2x *bp = params->bp;
13547         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13548                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13549                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13550                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13551                             0)
13552                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13553                         break;
13554                 }
13555         }
13556
13557         if (CHIP_IS_E3(bp)) {
13558                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13559                 bnx2x_set_aer_mmd(params, phy);
13560                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13561                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13562                         bnx2x_check_kr2_wa(params, vars, phy);
13563                 bnx2x_check_over_curr(params, vars);
13564                 if (vars->rx_tx_asic_rst)
13565                         bnx2x_warpcore_config_runtime(phy, params, vars);
13566
13567                 if ((REG_RD(bp, params->shmem_base +
13568                             offsetof(struct shmem_region, dev_info.
13569                                 port_hw_config[params->port].default_cfg))
13570                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13571                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13572                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13573                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13574                         } else if (vars->link_status &
13575                                 LINK_STATUS_SFP_TX_FAULT) {
13576                                 /* Clean trail, interrupt corrects the leds */
13577                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13578                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13579                                 /* Update link status in the shared memory */
13580                                 bnx2x_update_mng(params, vars->link_status);
13581                         }
13582                 }
13583         }
13584 }
13585
13586 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13587                              u32 shmem_base,
13588                              u32 shmem2_base,
13589                              u8 port)
13590 {
13591         u8 phy_index, fan_failure_det_req = 0;
13592         struct bnx2x_phy phy;
13593         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13594               phy_index++) {
13595                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13596                                        port, &phy)
13597                     != 0) {
13598                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13599                         return 0;
13600                 }
13601                 fan_failure_det_req |= (phy.flags &
13602                                         FLAGS_FAN_FAILURE_DET_REQ);
13603         }
13604         return fan_failure_det_req;
13605 }
13606
13607 void bnx2x_hw_reset_phy(struct link_params *params)
13608 {
13609         u8 phy_index;
13610         struct bnx2x *bp = params->bp;
13611         bnx2x_update_mng(params, 0);
13612         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13613                        (NIG_MASK_XGXS0_LINK_STATUS |
13614                         NIG_MASK_XGXS0_LINK10G |
13615                         NIG_MASK_SERDES0_LINK_STATUS |
13616                         NIG_MASK_MI_INT));
13617
13618         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13619               phy_index++) {
13620                 if (params->phy[phy_index].hw_reset) {
13621                         params->phy[phy_index].hw_reset(
13622                                 &params->phy[phy_index],
13623                                 params);
13624                         params->phy[phy_index] = phy_null;
13625                 }
13626         }
13627 }
13628
13629 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13630                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13631                             u8 port)
13632 {
13633         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13634         u32 val;
13635         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13636         if (CHIP_IS_E3(bp)) {
13637                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13638                                               shmem_base,
13639                                               port,
13640                                               &gpio_num,
13641                                               &gpio_port) != 0)
13642                         return;
13643         } else {
13644                 struct bnx2x_phy phy;
13645                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13646                       phy_index++) {
13647                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13648                                                shmem2_base, port, &phy)
13649                             != 0) {
13650                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13651                                 return;
13652                         }
13653                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13654                                 gpio_num = MISC_REGISTERS_GPIO_3;
13655                                 gpio_port = port;
13656                                 break;
13657                         }
13658                 }
13659         }
13660
13661         if (gpio_num == 0xff)
13662                 return;
13663
13664         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13665         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13666
13667         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13668         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13669         gpio_port ^= (swap_val && swap_override);
13670
13671         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13672                 (gpio_num + (gpio_port << 2));
13673
13674         sync_offset = shmem_base +
13675                 offsetof(struct shmem_region,
13676                          dev_info.port_hw_config[port].aeu_int_mask);
13677         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13678
13679         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13680                        gpio_num, gpio_port, vars->aeu_int_mask);
13681
13682         if (port == 0)
13683                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13684         else
13685                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13686
13687         /* Open appropriate AEU for interrupts */
13688         aeu_mask = REG_RD(bp, offset);
13689         aeu_mask |= vars->aeu_int_mask;
13690         REG_WR(bp, offset, aeu_mask);
13691
13692         /* Enable the GPIO to trigger interrupt */
13693         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13694         val |= 1 << (gpio_num + (gpio_port << 2));
13695         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13696 }