1 /* Copyright 2008-2013 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
31 struct link_params *params,
32 u8 dev_addr, u16 addr, u8 byte_cnt,
34 /********************************************************/
36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
38 #define ETH_MIN_PACKET_SIZE 60
39 #define ETH_MAX_PACKET_SIZE 1500
40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
41 #define MDIO_ACCESS_TIMEOUT 1000
43 #define I2C_SWITCH_WIDTH 2
46 #define I2C_WA_RETRY_CNT 3
47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
48 #define MCPR_IMC_COMMAND_READ_OP 1
49 #define MCPR_IMC_COMMAND_WRITE_OP 2
51 /* LED Blink rate that will achieve ~15.9Hz */
52 #define LED_BLINK_RATE_VAL_E3 354
53 #define LED_BLINK_RATE_VAL_E1X_E2 480
54 /***********************************************************/
55 /* Shortcut definitions */
56 /***********************************************************/
58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
60 #define NIG_STATUS_EMAC0_MI_INT \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
62 #define NIG_STATUS_XGXS0_LINK10G \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
64 #define NIG_STATUS_XGXS0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
68 #define NIG_STATUS_SERDES0_LINK_STATUS \
69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
70 #define NIG_MASK_MI_INT \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
72 #define NIG_MASK_XGXS0_LINK10G \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
74 #define NIG_MASK_XGXS0_LINK_STATUS \
75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
76 #define NIG_MASK_SERDES0_LINK_STATUS \
77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
79 #define MDIO_AN_CL73_OR_37_COMPLETE \
80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
83 #define XGXS_RESET_BITS \
84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
90 #define SERDES_RESET_BITS \
91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
99 #define AUTONEG_PARALLEL \
100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
101 #define AUTONEG_SGMII_FIBER_AUTODET \
102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
109 #define GP_STATUS_SPEED_MASK \
110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
117 #define GP_STATUS_10G_HIG \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
119 #define GP_STATUS_10G_CX4 \
120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
122 #define GP_STATUS_10G_KX4 \
123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
145 #define LINK_UPDATE_MASK \
146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
147 LINK_STATUS_LINK_UP | \
148 LINK_STATUS_PHYSICAL_LINK_FLAG | \
149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
157 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
158 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
159 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
162 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
163 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
164 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
165 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
167 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
168 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
169 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
171 #define SFP_EEPROM_OPTIONS_ADDR 0x40
172 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
173 #define SFP_EEPROM_OPTIONS_SIZE 2
175 #define EDC_MODE_LINEAR 0x0022
176 #define EDC_MODE_LIMITING 0x0044
177 #define EDC_MODE_PASSIVE_DAC 0x0055
178 #define EDC_MODE_ACTIVE_DAC 0x0066
181 #define DCBX_INVALID_COS (0xFF)
183 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
184 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
185 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
186 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
187 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
189 #define MAX_PACKET_SIZE (9700)
190 #define MAX_KR_LINK_RETRY 4
192 /**********************************************************/
194 /**********************************************************/
196 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
197 bnx2x_cl45_write(_bp, _phy, \
198 (_phy)->def_md_devad, \
199 (_bank + (_addr & 0xf)), \
202 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
203 bnx2x_cl45_read(_bp, _phy, \
204 (_phy)->def_md_devad, \
205 (_bank + (_addr & 0xf)), \
208 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
210 u32 val = REG_RD(bp, reg);
213 REG_WR(bp, reg, val);
217 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
219 u32 val = REG_RD(bp, reg);
222 REG_WR(bp, reg, val);
227 * bnx2x_check_lfa - This function checks if link reinitialization is required,
228 * or link flap can be avoided.
230 * @params: link parameters
231 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
234 static int bnx2x_check_lfa(struct link_params *params)
236 u32 link_status, cfg_idx, lfa_mask, cfg_size;
237 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
238 u32 saved_val, req_val, eee_status;
239 struct bnx2x *bp = params->bp;
242 REG_RD(bp, params->lfa_base +
243 offsetof(struct shmem_lfa, additional_config));
245 /* NOTE: must be first condition checked -
246 * to verify DCC bit is cleared in any case!
248 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
249 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
250 REG_WR(bp, params->lfa_base +
251 offsetof(struct shmem_lfa, additional_config),
252 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
253 return LFA_DCC_LFA_DISABLED;
256 /* Verify that link is up */
257 link_status = REG_RD(bp, params->shmem_base +
258 offsetof(struct shmem_region,
259 port_mb[params->port].link_status));
260 if (!(link_status & LINK_STATUS_LINK_UP))
261 return LFA_LINK_DOWN;
263 /* if loaded after BOOT from SAN, don't flap the link in any case and
264 * rely on link set by preboot driver
266 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
269 /* Verify that loopback mode is not set */
270 if (params->loopback_mode)
271 return LFA_LOOPBACK_ENABLED;
273 /* Verify that MFW supports LFA */
274 if (!params->lfa_base)
275 return LFA_MFW_IS_TOO_OLD;
277 if (params->num_phys == 3) {
279 lfa_mask = 0xffffffff;
286 saved_val = REG_RD(bp, params->lfa_base +
287 offsetof(struct shmem_lfa, req_duplex));
288 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
289 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
290 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
291 (saved_val & lfa_mask), (req_val & lfa_mask));
292 return LFA_DUPLEX_MISMATCH;
294 /* Compare Flow Control */
295 saved_val = REG_RD(bp, params->lfa_base +
296 offsetof(struct shmem_lfa, req_flow_ctrl));
297 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
298 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
299 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
300 (saved_val & lfa_mask), (req_val & lfa_mask));
301 return LFA_FLOW_CTRL_MISMATCH;
303 /* Compare Link Speed */
304 saved_val = REG_RD(bp, params->lfa_base +
305 offsetof(struct shmem_lfa, req_line_speed));
306 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
307 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
308 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
309 (saved_val & lfa_mask), (req_val & lfa_mask));
310 return LFA_LINK_SPEED_MISMATCH;
313 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
314 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
315 offsetof(struct shmem_lfa,
316 speed_cap_mask[cfg_idx]));
318 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
319 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
321 params->speed_cap_mask[cfg_idx]);
322 return LFA_SPEED_CAP_MISMATCH;
326 cur_req_fc_auto_adv =
327 REG_RD(bp, params->lfa_base +
328 offsetof(struct shmem_lfa, additional_config)) &
329 REQ_FC_AUTO_ADV_MASK;
331 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
332 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
333 cur_req_fc_auto_adv, params->req_fc_auto_adv);
334 return LFA_FLOW_CTRL_MISMATCH;
337 eee_status = REG_RD(bp, params->shmem2_base +
338 offsetof(struct shmem2_region,
339 eee_status[params->port]));
341 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
342 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
343 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
344 (params->eee_mode & EEE_MODE_ADV_LPI))) {
345 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
347 return LFA_EEE_MISMATCH;
350 /* LFA conditions are met */
353 /******************************************************************/
354 /* EPIO/GPIO section */
355 /******************************************************************/
356 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
358 u32 epio_mask, gp_oenable;
362 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
366 epio_mask = 1 << epio_pin;
367 /* Set this EPIO to output */
368 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
369 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
371 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
373 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
375 u32 epio_mask, gp_output, gp_oenable;
379 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
382 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
383 epio_mask = 1 << epio_pin;
384 /* Set this EPIO to output */
385 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
387 gp_output |= epio_mask;
389 gp_output &= ~epio_mask;
391 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
393 /* Set the value for this EPIO */
394 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
395 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
398 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
400 if (pin_cfg == PIN_CFG_NA)
402 if (pin_cfg >= PIN_CFG_EPIO0) {
403 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
405 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
406 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
407 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
411 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
413 if (pin_cfg == PIN_CFG_NA)
415 if (pin_cfg >= PIN_CFG_EPIO0) {
416 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
418 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
419 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
420 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
425 /******************************************************************/
427 /******************************************************************/
428 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
430 /* ETS disabled configuration*/
431 struct bnx2x *bp = params->bp;
433 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
435 /* mapping between entry priority to client number (0,1,2 -debug and
436 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
438 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
439 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
442 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
443 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
444 * as strict. Bits 0,1,2 - debug and management entries, 3 -
445 * COS0 entry, 4 - COS1 entry.
446 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
447 * bit4 bit3 bit2 bit1 bit0
448 * MCP and debug are strict
451 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
452 /* defines which entries (clients) are subjected to WFQ arbitration */
453 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
454 /* For strict priority entries defines the number of consecutive
455 * slots for the highest priority.
457 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
458 /* mapping between the CREDIT_WEIGHT registers and actual client
461 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
462 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
463 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
466 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
467 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
468 /* ETS mode disable */
469 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
470 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
471 * weight for COS0/COS1.
473 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
474 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
475 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
476 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
477 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
478 /* Defines the number of consecutive slots for the strict priority */
479 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
481 /******************************************************************************
483 * Getting min_w_val will be set according to line speed .
485 ******************************************************************************/
486 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
489 /* Calculate min_w_val.*/
491 if (vars->line_speed == SPEED_20000)
492 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
494 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
496 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
497 /* If the link isn't up (static configuration for example ) The
498 * link will be according to 20GBPS.
502 /******************************************************************************
504 * Getting credit upper bound form min_w_val.
506 ******************************************************************************/
507 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
509 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
511 return credit_upper_bound;
513 /******************************************************************************
515 * Set credit upper bound for NIG.
517 ******************************************************************************/
518 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
519 const struct link_params *params,
522 struct bnx2x *bp = params->bp;
523 const u8 port = params->port;
524 const u32 credit_upper_bound =
525 bnx2x_ets_get_credit_upper_bound(min_w_val);
527 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
528 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
529 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
530 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
531 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
532 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
533 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
534 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
535 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
536 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
537 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
538 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
541 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
543 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
545 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
549 /******************************************************************************
551 * Will return the NIG ETS registers to init values.Except
552 * credit_upper_bound.
553 * That isn't used in this configuration (No WFQ is enabled) and will be
554 * configured acording to spec
556 ******************************************************************************/
557 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
558 const struct link_vars *vars)
560 struct bnx2x *bp = params->bp;
561 const u8 port = params->port;
562 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
563 /* Mapping between entry priority to client number (0,1,2 -debug and
564 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
565 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
566 * reset value or init tool
569 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
570 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
572 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
573 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
575 /* For strict priority entries defines the number of consecutive
576 * slots for the highest priority.
578 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
579 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
580 /* Mapping between the CREDIT_WEIGHT registers and actual client
585 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
586 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
589 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
591 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
594 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
595 * as strict. Bits 0,1,2 - debug and management entries, 3 -
596 * COS0 entry, 4 - COS1 entry.
597 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
598 * bit4 bit3 bit2 bit1 bit0
599 * MCP and debug are strict
602 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
604 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
605 /* defines which entries (clients) are subjected to WFQ arbitration */
606 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
607 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
609 /* Please notice the register address are note continuous and a
610 * for here is note appropriate.In 2 port mode port0 only COS0-5
611 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
612 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
613 * are never used for WFQ
615 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
616 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
617 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
618 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
619 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
620 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
621 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
622 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
623 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
624 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
625 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
626 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
628 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
629 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
630 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
633 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
635 /******************************************************************************
637 * Set credit upper bound for PBF.
639 ******************************************************************************/
640 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
641 const struct link_params *params,
644 struct bnx2x *bp = params->bp;
645 const u32 credit_upper_bound =
646 bnx2x_ets_get_credit_upper_bound(min_w_val);
647 const u8 port = params->port;
648 u32 base_upper_bound = 0;
651 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
652 * port mode port1 has COS0-2 that can be used for WFQ.
655 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
656 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
658 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
659 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
662 for (i = 0; i < max_cos; i++)
663 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
666 /******************************************************************************
668 * Will return the PBF ETS registers to init values.Except
669 * credit_upper_bound.
670 * That isn't used in this configuration (No WFQ is enabled) and will be
671 * configured acording to spec
673 ******************************************************************************/
674 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
676 struct bnx2x *bp = params->bp;
677 const u8 port = params->port;
678 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
683 /* Mapping between entry priority to client number 0 - COS0
684 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
685 * TODO_ETS - Should be done by reset value or init tool
688 /* 0x688 (|011|0 10|00 1|000) */
689 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
691 /* (10 1|100 |011|0 10|00 1|000) */
692 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
694 /* TODO_ETS - Should be done by reset value or init tool */
696 /* 0x688 (|011|0 10|00 1|000)*/
697 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
699 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
700 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
702 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
703 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
706 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
707 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
709 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
710 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
711 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
712 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
715 base_weight = PBF_REG_COS0_WEIGHT_P0;
716 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
718 base_weight = PBF_REG_COS0_WEIGHT_P1;
719 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
722 for (i = 0; i < max_cos; i++)
723 REG_WR(bp, base_weight + (0x4 * i), 0);
725 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
727 /******************************************************************************
729 * E3B0 disable will return basicly the values to init values.
731 ******************************************************************************/
732 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
733 const struct link_vars *vars)
735 struct bnx2x *bp = params->bp;
737 if (!CHIP_IS_E3B0(bp)) {
739 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
743 bnx2x_ets_e3b0_nig_disabled(params, vars);
745 bnx2x_ets_e3b0_pbf_disabled(params);
750 /******************************************************************************
752 * Disable will return basicly the values to init values.
754 ******************************************************************************/
755 int bnx2x_ets_disabled(struct link_params *params,
756 struct link_vars *vars)
758 struct bnx2x *bp = params->bp;
759 int bnx2x_status = 0;
761 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
762 bnx2x_ets_e2e3a0_disabled(params);
763 else if (CHIP_IS_E3B0(bp))
764 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
766 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
773 /******************************************************************************
775 * Set the COS mappimg to SP and BW until this point all the COS are not
777 ******************************************************************************/
778 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
779 const struct bnx2x_ets_params *ets_params,
780 const u8 cos_sp_bitmap,
781 const u8 cos_bw_bitmap)
783 struct bnx2x *bp = params->bp;
784 const u8 port = params->port;
785 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
786 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
787 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
788 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
790 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
791 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
793 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
794 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
796 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
797 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
798 nig_cli_subject2wfq_bitmap);
800 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
801 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
802 pbf_cli_subject2wfq_bitmap);
807 /******************************************************************************
809 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
810 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
811 ******************************************************************************/
812 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
814 const u32 min_w_val_nig,
815 const u32 min_w_val_pbf,
820 u32 nig_reg_adress_crd_weight = 0;
821 u32 pbf_reg_adress_crd_weight = 0;
822 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
823 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
824 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
828 nig_reg_adress_crd_weight =
829 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
830 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
831 pbf_reg_adress_crd_weight = (port) ?
832 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
835 nig_reg_adress_crd_weight = (port) ?
836 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
837 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
838 pbf_reg_adress_crd_weight = (port) ?
839 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
842 nig_reg_adress_crd_weight = (port) ?
843 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
844 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
846 pbf_reg_adress_crd_weight = (port) ?
847 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
852 nig_reg_adress_crd_weight =
853 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
854 pbf_reg_adress_crd_weight =
855 PBF_REG_COS3_WEIGHT_P0;
860 nig_reg_adress_crd_weight =
861 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
862 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
867 nig_reg_adress_crd_weight =
868 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
869 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
873 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
875 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
879 /******************************************************************************
881 * Calculate the total BW.A value of 0 isn't legal.
883 ******************************************************************************/
884 static int bnx2x_ets_e3b0_get_total_bw(
885 const struct link_params *params,
886 struct bnx2x_ets_params *ets_params,
889 struct bnx2x *bp = params->bp;
891 u8 is_bw_cos_exist = 0;
894 /* Calculate total BW requested */
895 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
896 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
898 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
899 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
901 /* This is to prevent a state when ramrods
904 ets_params->cos[cos_idx].params.bw_params.bw
908 ets_params->cos[cos_idx].params.bw_params.bw;
912 /* Check total BW is valid */
913 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
914 if (*total_bw == 0) {
916 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
920 "bnx2x_ets_E3B0_config total BW should be 100\n");
921 /* We can handle a case whre the BW isn't 100 this can happen
922 * if the TC are joined.
928 /******************************************************************************
930 * Invalidate all the sp_pri_to_cos.
932 ******************************************************************************/
933 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
936 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
937 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
939 /******************************************************************************
941 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
942 * according to sp_pri_to_cos.
944 ******************************************************************************/
945 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
946 u8 *sp_pri_to_cos, const u8 pri,
949 struct bnx2x *bp = params->bp;
950 const u8 port = params->port;
951 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
952 DCBX_E3B0_MAX_NUM_COS_PORT0;
954 if (pri >= max_num_of_cos) {
955 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
956 "parameter Illegal strict priority\n");
960 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
961 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
962 "parameter There can't be two COS's with "
963 "the same strict pri\n");
967 sp_pri_to_cos[pri] = cos_entry;
972 /******************************************************************************
974 * Returns the correct value according to COS and priority in
975 * the sp_pri_cli register.
977 ******************************************************************************/
978 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
984 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
985 (pri_set + pri_offset));
989 /******************************************************************************
991 * Returns the correct value according to COS and priority in the
992 * sp_pri_cli register for NIG.
994 ******************************************************************************/
995 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
997 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
998 const u8 nig_cos_offset = 3;
999 const u8 nig_pri_offset = 3;
1001 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1005 /******************************************************************************
1007 * Returns the correct value according to COS and priority in the
1008 * sp_pri_cli register for PBF.
1010 ******************************************************************************/
1011 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1013 const u8 pbf_cos_offset = 0;
1014 const u8 pbf_pri_offset = 0;
1016 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1021 /******************************************************************************
1023 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1024 * according to sp_pri_to_cos.(which COS has higher priority)
1026 ******************************************************************************/
1027 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1030 struct bnx2x *bp = params->bp;
1032 const u8 port = params->port;
1033 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1034 u64 pri_cli_nig = 0x210;
1035 u32 pri_cli_pbf = 0x0;
1038 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1039 DCBX_E3B0_MAX_NUM_COS_PORT0;
1041 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1043 /* Set all the strict priority first */
1044 for (i = 0; i < max_num_of_cos; i++) {
1045 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1046 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1048 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1049 "invalid cos entry\n");
1053 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1054 sp_pri_to_cos[i], pri_set);
1056 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1057 sp_pri_to_cos[i], pri_set);
1058 pri_bitmask = 1 << sp_pri_to_cos[i];
1059 /* COS is used remove it from bitmap.*/
1060 if (!(pri_bitmask & cos_bit_to_set)) {
1062 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1063 "invalid There can't be two COS's with"
1064 " the same strict pri\n");
1067 cos_bit_to_set &= ~pri_bitmask;
1072 /* Set all the Non strict priority i= COS*/
1073 for (i = 0; i < max_num_of_cos; i++) {
1074 pri_bitmask = 1 << i;
1075 /* Check if COS was already used for SP */
1076 if (pri_bitmask & cos_bit_to_set) {
1077 /* COS wasn't used for SP */
1078 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1081 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1083 /* COS is used remove it from bitmap.*/
1084 cos_bit_to_set &= ~pri_bitmask;
1089 if (pri_set != max_num_of_cos) {
1090 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1091 "entries were set\n");
1096 /* Only 6 usable clients*/
1097 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1100 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1102 /* Only 9 usable clients*/
1103 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1104 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1106 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1108 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1111 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1116 /******************************************************************************
1118 * Configure the COS to ETS according to BW and SP settings.
1119 ******************************************************************************/
1120 int bnx2x_ets_e3b0_config(const struct link_params *params,
1121 const struct link_vars *vars,
1122 struct bnx2x_ets_params *ets_params)
1124 struct bnx2x *bp = params->bp;
1125 int bnx2x_status = 0;
1126 const u8 port = params->port;
1128 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1129 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1130 u8 cos_bw_bitmap = 0;
1131 u8 cos_sp_bitmap = 0;
1132 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1133 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1134 DCBX_E3B0_MAX_NUM_COS_PORT0;
1137 if (!CHIP_IS_E3B0(bp)) {
1139 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1143 if ((ets_params->num_of_cos > max_num_of_cos)) {
1144 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1145 "isn't supported\n");
1149 /* Prepare sp strict priority parameters*/
1150 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1152 /* Prepare BW parameters*/
1153 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1157 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1161 /* Upper bound is set according to current link speed (min_w_val
1162 * should be the same for upper bound and COS credit val).
1164 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1165 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1168 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1169 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1170 cos_bw_bitmap |= (1 << cos_entry);
1171 /* The function also sets the BW in HW(not the mappin
1174 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1175 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1177 ets_params->cos[cos_entry].params.bw_params.bw,
1179 } else if (bnx2x_cos_state_strict ==
1180 ets_params->cos[cos_entry].state){
1181 cos_sp_bitmap |= (1 << cos_entry);
1183 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1186 ets_params->cos[cos_entry].params.sp_params.pri,
1191 "bnx2x_ets_e3b0_config cos state not valid\n");
1196 "bnx2x_ets_e3b0_config set cos bw failed\n");
1197 return bnx2x_status;
1201 /* Set SP register (which COS has higher priority) */
1202 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1207 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1208 return bnx2x_status;
1211 /* Set client mapping of BW and strict */
1212 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1217 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1218 return bnx2x_status;
1222 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1224 /* ETS disabled configuration */
1225 struct bnx2x *bp = params->bp;
1226 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1227 /* Defines which entries (clients) are subjected to WFQ arbitration
1231 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1232 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1233 * client numbers (WEIGHT_0 does not actually have to represent
1235 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1236 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1238 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1240 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1241 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1242 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1243 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1245 /* ETS mode enabled*/
1246 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1248 /* Defines the number of consecutive slots for the strict priority */
1249 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1250 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1251 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1252 * entry, 4 - COS1 entry.
1253 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1254 * bit4 bit3 bit2 bit1 bit0
1255 * MCP and debug are strict
1257 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1259 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1260 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1261 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1262 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1263 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1266 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1269 /* ETS disabled configuration*/
1270 struct bnx2x *bp = params->bp;
1271 const u32 total_bw = cos0_bw + cos1_bw;
1272 u32 cos0_credit_weight = 0;
1273 u32 cos1_credit_weight = 0;
1275 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1280 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1284 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1286 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1289 bnx2x_ets_bw_limit_common(params);
1291 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1292 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1294 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1295 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1298 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1300 /* ETS disabled configuration*/
1301 struct bnx2x *bp = params->bp;
1304 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1305 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1306 * as strict. Bits 0,1,2 - debug and management entries,
1307 * 3 - COS0 entry, 4 - COS1 entry.
1308 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1309 * bit4 bit3 bit2 bit1 bit0
1310 * MCP and debug are strict
1312 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1313 /* For strict priority entries defines the number of consecutive slots
1314 * for the highest priority.
1316 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1317 /* ETS mode disable */
1318 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1319 /* Defines the number of consecutive slots for the strict priority */
1320 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1322 /* Defines the number of consecutive slots for the strict priority */
1323 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1325 /* Mapping between entry priority to client number (0,1,2 -debug and
1326 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1328 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1329 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1330 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1332 val = (!strict_cos) ? 0x2318 : 0x22E0;
1333 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1338 /******************************************************************/
1340 /******************************************************************/
1341 static void bnx2x_update_pfc_xmac(struct link_params *params,
1342 struct link_vars *vars,
1345 struct bnx2x *bp = params->bp;
1347 u32 pause_val, pfc0_val, pfc1_val;
1349 /* XMAC base adrr */
1350 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1352 /* Initialize pause and pfc registers */
1353 pause_val = 0x18000;
1354 pfc0_val = 0xFFFF8000;
1357 /* No PFC support */
1358 if (!(params->feature_config_flags &
1359 FEATURE_CONFIG_PFC_ENABLED)) {
1361 /* RX flow control - Process pause frame in receive direction
1363 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1364 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1366 /* TX flow control - Send pause packet when buffer is full */
1367 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1368 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1369 } else {/* PFC support */
1370 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1371 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1372 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1373 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1374 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1375 /* Write pause and PFC registers */
1376 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1377 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1378 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1379 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1383 /* Write pause and PFC registers */
1384 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1385 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1386 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1389 /* Set MAC address for source TX Pause/PFC frames */
1390 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1391 ((params->mac_addr[2] << 24) |
1392 (params->mac_addr[3] << 16) |
1393 (params->mac_addr[4] << 8) |
1394 (params->mac_addr[5])));
1395 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1396 ((params->mac_addr[0] << 8) |
1397 (params->mac_addr[1])));
1403 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1404 u32 pfc_frames_sent[2],
1405 u32 pfc_frames_received[2])
1407 /* Read pfc statistic */
1408 struct bnx2x *bp = params->bp;
1409 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1413 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1415 /* PFC received frames */
1416 val_xoff = REG_RD(bp, emac_base +
1417 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1418 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1419 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1420 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1422 pfc_frames_received[0] = val_xon + val_xoff;
1424 /* PFC received sent */
1425 val_xoff = REG_RD(bp, emac_base +
1426 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1427 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1428 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1429 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1431 pfc_frames_sent[0] = val_xon + val_xoff;
1434 /* Read pfc statistic*/
1435 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1436 u32 pfc_frames_sent[2],
1437 u32 pfc_frames_received[2])
1439 /* Read pfc statistic */
1440 struct bnx2x *bp = params->bp;
1442 DP(NETIF_MSG_LINK, "pfc statistic\n");
1447 if (vars->mac_type == MAC_TYPE_EMAC) {
1448 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1449 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1450 pfc_frames_received);
1453 /******************************************************************/
1454 /* MAC/PBF section */
1455 /******************************************************************/
1456 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1459 u32 new_mode, cur_mode;
1461 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1462 * (a value of 49==0x31) and make sure that the AUTO poll is off
1464 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1466 if (USES_WARPCORE(bp))
1467 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1469 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1471 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1472 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1475 new_mode = cur_mode &
1476 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1477 new_mode |= clc_cnt;
1478 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1480 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1481 cur_mode, new_mode);
1482 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1486 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1487 struct link_params *params)
1490 /* Set mdio clock per phy */
1491 for (phy_index = INT_PHY; phy_index < params->num_phys;
1493 bnx2x_set_mdio_clk(bp, params->chip_id,
1494 params->phy[phy_index].mdio_ctrl);
1497 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1499 u32 port4mode_ovwr_val;
1500 /* Check 4-port override enabled */
1501 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1502 if (port4mode_ovwr_val & (1<<0)) {
1503 /* Return 4-port mode override value */
1504 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1506 /* Return 4-port mode from input pin */
1507 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1510 static void bnx2x_emac_init(struct link_params *params,
1511 struct link_vars *vars)
1513 /* reset and unreset the emac core */
1514 struct bnx2x *bp = params->bp;
1515 u8 port = params->port;
1516 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1520 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1521 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1523 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1524 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1526 /* init emac - use read-modify-write */
1527 /* self clear reset */
1528 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1529 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1533 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1534 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1536 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1540 } while (val & EMAC_MODE_RESET);
1542 bnx2x_set_mdio_emac_per_phy(bp, params);
1543 /* Set mac address */
1544 val = ((params->mac_addr[0] << 8) |
1545 params->mac_addr[1]);
1546 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1548 val = ((params->mac_addr[2] << 24) |
1549 (params->mac_addr[3] << 16) |
1550 (params->mac_addr[4] << 8) |
1551 params->mac_addr[5]);
1552 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1555 static void bnx2x_set_xumac_nig(struct link_params *params,
1559 struct bnx2x *bp = params->bp;
1561 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1563 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1565 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1566 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1569 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1571 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1573 struct bnx2x *bp = params->bp;
1574 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1575 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1577 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1579 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1580 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1582 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1583 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1584 /* Disable RX and TX */
1585 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1588 static void bnx2x_umac_enable(struct link_params *params,
1589 struct link_vars *vars, u8 lb)
1592 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1593 struct bnx2x *bp = params->bp;
1595 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1596 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1597 usleep_range(1000, 2000);
1599 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1600 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1602 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1604 /* This register opens the gate for the UMAC despite its name */
1605 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1607 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1608 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1609 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1610 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1611 switch (vars->line_speed) {
1625 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1629 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1630 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1632 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1633 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1635 if (vars->duplex == DUPLEX_HALF)
1636 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1638 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1641 /* Configure UMAC for EEE */
1642 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1643 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1644 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1645 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1646 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1648 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1651 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1652 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1653 ((params->mac_addr[2] << 24) |
1654 (params->mac_addr[3] << 16) |
1655 (params->mac_addr[4] << 8) |
1656 (params->mac_addr[5])));
1657 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1658 ((params->mac_addr[0] << 8) |
1659 (params->mac_addr[1])));
1661 /* Enable RX and TX */
1662 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1663 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1664 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1665 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1668 /* Remove SW Reset */
1669 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1671 /* Check loopback mode */
1673 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1674 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1676 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1677 * length used by the MAC receive logic to check frames.
1679 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1680 bnx2x_set_xumac_nig(params,
1681 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1682 vars->mac_type = MAC_TYPE_UMAC;
1686 /* Define the XMAC mode */
1687 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1689 struct bnx2x *bp = params->bp;
1690 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1692 /* In 4-port mode, need to set the mode only once, so if XMAC is
1693 * already out of reset, it means the mode has already been set,
1694 * and it must not* reset the XMAC again, since it controls both
1698 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1699 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1700 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1702 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1703 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1705 "XMAC already out of reset in 4-port mode\n");
1710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1711 MISC_REGISTERS_RESET_REG_2_XMAC);
1712 usleep_range(1000, 2000);
1714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1715 MISC_REGISTERS_RESET_REG_2_XMAC);
1717 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1719 /* Set the number of ports on the system side to up to 2 */
1720 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1722 /* Set the number of ports on the Warp Core to 10G */
1723 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1725 /* Set the number of ports on the system side to 1 */
1726 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1727 if (max_speed == SPEED_10000) {
1729 "Init XMAC to 10G x 1 port per path\n");
1730 /* Set the number of ports on the Warp Core to 10G */
1731 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1734 "Init XMAC to 20G x 2 ports per path\n");
1735 /* Set the number of ports on the Warp Core to 20G */
1736 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1740 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1741 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1742 usleep_range(1000, 2000);
1744 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1745 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1749 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1751 u8 port = params->port;
1752 struct bnx2x *bp = params->bp;
1753 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1756 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1757 MISC_REGISTERS_RESET_REG_2_XMAC) {
1758 /* Send an indication to change the state in the NIG back to XON
1759 * Clearing this bit enables the next set of this bit to get
1762 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1763 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1764 (pfc_ctrl & ~(1<<1)));
1765 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1766 (pfc_ctrl | (1<<1)));
1767 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1768 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1770 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1772 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1773 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1777 static int bnx2x_xmac_enable(struct link_params *params,
1778 struct link_vars *vars, u8 lb)
1781 struct bnx2x *bp = params->bp;
1782 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1784 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1786 bnx2x_xmac_init(params, vars->line_speed);
1788 /* This register determines on which events the MAC will assert
1789 * error on the i/f to the NIG along w/ EOP.
1792 /* This register tells the NIG whether to send traffic to UMAC
1795 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1797 /* When XMAC is in XLGMII mode, disable sending idles for fault
1800 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1801 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1802 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1803 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1804 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1805 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1806 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1807 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1809 /* Set Max packet size */
1810 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1812 /* CRC append for Tx packets */
1813 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1816 bnx2x_update_pfc_xmac(params, vars, 0);
1818 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1819 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1820 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1821 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1823 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1826 /* Enable TX and RX */
1827 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1829 /* Set MAC in XLGMII mode for dual-mode */
1830 if ((vars->line_speed == SPEED_20000) &&
1831 (params->phy[INT_PHY].supported &
1832 SUPPORTED_20000baseKR2_Full))
1833 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1835 /* Check loopback mode */
1837 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1838 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1839 bnx2x_set_xumac_nig(params,
1840 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1842 vars->mac_type = MAC_TYPE_XMAC;
1847 static int bnx2x_emac_enable(struct link_params *params,
1848 struct link_vars *vars, u8 lb)
1850 struct bnx2x *bp = params->bp;
1851 u8 port = params->port;
1852 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1855 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1858 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1859 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1861 /* enable emac and not bmac */
1862 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1865 if (vars->phy_flags & PHY_XGXS_FLAG) {
1866 u32 ser_lane = ((params->lane_config &
1867 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1868 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1870 DP(NETIF_MSG_LINK, "XGXS\n");
1871 /* select the master lanes (out of 0-3) */
1872 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1874 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1876 } else { /* SerDes */
1877 DP(NETIF_MSG_LINK, "SerDes\n");
1879 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1882 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1883 EMAC_RX_MODE_RESET);
1884 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1885 EMAC_TX_MODE_RESET);
1887 /* pause enable/disable */
1888 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1889 EMAC_RX_MODE_FLOW_EN);
1891 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1892 (EMAC_TX_MODE_EXT_PAUSE_EN |
1893 EMAC_TX_MODE_FLOW_EN));
1894 if (!(params->feature_config_flags &
1895 FEATURE_CONFIG_PFC_ENABLED)) {
1896 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1897 bnx2x_bits_en(bp, emac_base +
1898 EMAC_REG_EMAC_RX_MODE,
1899 EMAC_RX_MODE_FLOW_EN);
1901 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1902 bnx2x_bits_en(bp, emac_base +
1903 EMAC_REG_EMAC_TX_MODE,
1904 (EMAC_TX_MODE_EXT_PAUSE_EN |
1905 EMAC_TX_MODE_FLOW_EN));
1907 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1908 EMAC_TX_MODE_FLOW_EN);
1910 /* KEEP_VLAN_TAG, promiscuous */
1911 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1912 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1914 /* Setting this bit causes MAC control frames (except for pause
1915 * frames) to be passed on for processing. This setting has no
1916 * affect on the operation of the pause frames. This bit effects
1917 * all packets regardless of RX Parser packet sorting logic.
1918 * Turn the PFC off to make sure we are in Xon state before
1921 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1922 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1923 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1924 /* Enable PFC again */
1925 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1926 EMAC_REG_RX_PFC_MODE_RX_EN |
1927 EMAC_REG_RX_PFC_MODE_TX_EN |
1928 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1930 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1932 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1934 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1935 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1937 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1940 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1945 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1948 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1950 /* Enable emac for jumbo packets */
1951 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1952 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1953 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1956 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1958 /* Disable the NIG in/out to the bmac */
1959 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1960 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1961 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1963 /* Enable the NIG in/out to the emac */
1964 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1966 if ((params->feature_config_flags &
1967 FEATURE_CONFIG_PFC_ENABLED) ||
1968 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1971 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1972 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1974 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1976 vars->mac_type = MAC_TYPE_EMAC;
1980 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1981 struct link_vars *vars)
1984 struct bnx2x *bp = params->bp;
1985 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1986 NIG_REG_INGRESS_BMAC0_MEM;
1989 if ((!(params->feature_config_flags &
1990 FEATURE_CONFIG_PFC_ENABLED)) &&
1991 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1992 /* Enable BigMAC to react on received Pause packets */
1996 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2000 if (!(params->feature_config_flags &
2001 FEATURE_CONFIG_PFC_ENABLED) &&
2002 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2006 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2009 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2010 struct link_vars *vars,
2013 /* Set rx control: Strip CRC and enable BigMAC to relay
2014 * control packets to the system as well
2017 struct bnx2x *bp = params->bp;
2018 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2019 NIG_REG_INGRESS_BMAC0_MEM;
2022 if ((!(params->feature_config_flags &
2023 FEATURE_CONFIG_PFC_ENABLED)) &&
2024 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2025 /* Enable BigMAC to react on received Pause packets */
2029 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2034 if (!(params->feature_config_flags &
2035 FEATURE_CONFIG_PFC_ENABLED) &&
2036 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2040 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2042 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2043 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2044 /* Enable PFC RX & TX & STATS and set 8 COS */
2046 wb_data[0] |= (1<<0); /* RX */
2047 wb_data[0] |= (1<<1); /* TX */
2048 wb_data[0] |= (1<<2); /* Force initial Xon */
2049 wb_data[0] |= (1<<3); /* 8 cos */
2050 wb_data[0] |= (1<<5); /* STATS */
2052 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2054 /* Clear the force Xon */
2055 wb_data[0] &= ~(1<<2);
2057 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2058 /* Disable PFC RX & TX & STATS and set 8 COS */
2063 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2065 /* Set Time (based unit is 512 bit time) between automatic
2066 * re-sending of PP packets amd enable automatic re-send of
2067 * Per-Priroity Packet as long as pp_gen is asserted and
2068 * pp_disable is low.
2071 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2072 val |= (1<<16); /* enable automatic re-send */
2076 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2080 val = 0x3; /* Enable RX and TX */
2082 val |= 0x4; /* Local loopback */
2083 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2085 /* When PFC enabled, Pass pause frames towards the NIG. */
2086 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2087 val |= ((1<<6)|(1<<5));
2091 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2094 /******************************************************************************
2096 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2097 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2098 ******************************************************************************/
2099 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2101 u32 priority_mask, u8 port)
2103 u32 nig_reg_rx_priority_mask_add = 0;
2105 switch (cos_entry) {
2107 nig_reg_rx_priority_mask_add = (port) ?
2108 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2109 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2112 nig_reg_rx_priority_mask_add = (port) ?
2113 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2114 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2117 nig_reg_rx_priority_mask_add = (port) ?
2118 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2119 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2124 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2129 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2134 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2138 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2142 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2144 struct bnx2x *bp = params->bp;
2146 REG_WR(bp, params->shmem_base +
2147 offsetof(struct shmem_region,
2148 port_mb[params->port].link_status), link_status);
2151 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2153 struct bnx2x *bp = params->bp;
2155 if (SHMEM2_HAS(bp, link_attr_sync))
2156 REG_WR(bp, params->shmem2_base +
2157 offsetof(struct shmem2_region,
2158 link_attr_sync[params->port]), link_attr);
2161 static void bnx2x_update_pfc_nig(struct link_params *params,
2162 struct link_vars *vars,
2163 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2165 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2166 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2167 u32 pkt_priority_to_cos = 0;
2168 struct bnx2x *bp = params->bp;
2169 u8 port = params->port;
2171 int set_pfc = params->feature_config_flags &
2172 FEATURE_CONFIG_PFC_ENABLED;
2173 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2175 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2176 * MAC control frames (that are not pause packets)
2177 * will be forwarded to the XCM.
2179 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2180 NIG_REG_LLH0_XCM_MASK);
2181 /* NIG params will override non PFC params, since it's possible to
2182 * do transition from PFC to SAFC
2192 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2193 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2198 llfc_out_en = nig_params->llfc_out_en;
2199 llfc_enable = nig_params->llfc_enable;
2200 pause_enable = nig_params->pause_enable;
2201 } else /* Default non PFC mode - PAUSE */
2204 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2205 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2210 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2211 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2212 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2213 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2214 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2215 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2216 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2217 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2219 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2220 NIG_REG_PPP_ENABLE_0, ppp_enable);
2222 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2223 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2225 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2226 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2228 /* Output enable for RX_XCM # IF */
2229 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2230 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2232 /* HW PFC TX enable */
2233 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2234 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2238 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2240 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2241 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2242 nig_params->rx_cos_priority_mask[i], port);
2244 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2245 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2246 nig_params->llfc_high_priority_classes);
2248 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2249 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2250 nig_params->llfc_low_priority_classes);
2252 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2253 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2254 pkt_priority_to_cos);
2257 int bnx2x_update_pfc(struct link_params *params,
2258 struct link_vars *vars,
2259 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2261 /* The PFC and pause are orthogonal to one another, meaning when
2262 * PFC is enabled, the pause are disabled, and when PFC is
2263 * disabled, pause are set according to the pause result.
2266 struct bnx2x *bp = params->bp;
2267 int bnx2x_status = 0;
2268 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2270 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2271 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2273 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2275 bnx2x_update_mng(params, vars->link_status);
2277 /* Update NIG params */
2278 bnx2x_update_pfc_nig(params, vars, pfc_params);
2281 return bnx2x_status;
2283 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2285 if (CHIP_IS_E3(bp)) {
2286 if (vars->mac_type == MAC_TYPE_XMAC)
2287 bnx2x_update_pfc_xmac(params, vars, 0);
2289 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2291 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2293 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2294 bnx2x_emac_enable(params, vars, 0);
2295 return bnx2x_status;
2298 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2300 bnx2x_update_pfc_bmac1(params, vars);
2303 if ((params->feature_config_flags &
2304 FEATURE_CONFIG_PFC_ENABLED) ||
2305 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2307 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2309 return bnx2x_status;
2312 static int bnx2x_bmac1_enable(struct link_params *params,
2313 struct link_vars *vars,
2316 struct bnx2x *bp = params->bp;
2317 u8 port = params->port;
2318 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2319 NIG_REG_INGRESS_BMAC0_MEM;
2323 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2328 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2332 wb_data[0] = ((params->mac_addr[2] << 24) |
2333 (params->mac_addr[3] << 16) |
2334 (params->mac_addr[4] << 8) |
2335 params->mac_addr[5]);
2336 wb_data[1] = ((params->mac_addr[0] << 8) |
2337 params->mac_addr[1]);
2338 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2344 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2348 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2351 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2353 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2355 bnx2x_update_pfc_bmac1(params, vars);
2358 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2360 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2362 /* Set cnt max size */
2363 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2365 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2367 /* Configure SAFC */
2368 wb_data[0] = 0x1000200;
2370 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2376 static int bnx2x_bmac2_enable(struct link_params *params,
2377 struct link_vars *vars,
2380 struct bnx2x *bp = params->bp;
2381 u8 port = params->port;
2382 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2383 NIG_REG_INGRESS_BMAC0_MEM;
2386 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2390 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2393 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2396 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2402 wb_data[0] = ((params->mac_addr[2] << 24) |
2403 (params->mac_addr[3] << 16) |
2404 (params->mac_addr[4] << 8) |
2405 params->mac_addr[5]);
2406 wb_data[1] = ((params->mac_addr[0] << 8) |
2407 params->mac_addr[1]);
2408 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2413 /* Configure SAFC */
2414 wb_data[0] = 0x1000200;
2416 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2421 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2423 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2427 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2429 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2431 /* Set cnt max size */
2432 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2434 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2436 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2441 static int bnx2x_bmac_enable(struct link_params *params,
2442 struct link_vars *vars,
2443 u8 is_lb, u8 reset_bmac)
2446 u8 port = params->port;
2447 struct bnx2x *bp = params->bp;
2449 /* Reset and unreset the BigMac */
2451 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2452 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2453 usleep_range(1000, 2000);
2456 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2457 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2459 /* Enable access for bmac registers */
2460 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2462 /* Enable BMAC according to BMAC type*/
2464 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2466 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2467 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2468 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2469 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2471 if ((params->feature_config_flags &
2472 FEATURE_CONFIG_PFC_ENABLED) ||
2473 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2475 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2476 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2477 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2478 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2479 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2480 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2482 vars->mac_type = MAC_TYPE_BMAC;
2486 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2488 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2489 NIG_REG_INGRESS_BMAC0_MEM;
2491 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2494 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2496 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2497 /* Only if the bmac is out of reset */
2498 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2499 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2501 /* Clear Rx Enable bit in BMAC_CONTROL register */
2502 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2504 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2506 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2507 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2508 usleep_range(1000, 2000);
2512 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2515 struct bnx2x *bp = params->bp;
2516 u8 port = params->port;
2521 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2523 /* Wait for init credit */
2524 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2525 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2526 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2528 while ((init_crd != crd) && count) {
2529 usleep_range(5000, 10000);
2530 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2533 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2534 if (init_crd != crd) {
2535 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2540 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2541 line_speed == SPEED_10 ||
2542 line_speed == SPEED_100 ||
2543 line_speed == SPEED_1000 ||
2544 line_speed == SPEED_2500) {
2545 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2546 /* Update threshold */
2547 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2548 /* Update init credit */
2549 init_crd = 778; /* (800-18-4) */
2552 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2554 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2555 /* Update threshold */
2556 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2557 /* Update init credit */
2558 switch (line_speed) {
2560 init_crd = thresh + 553 - 22;
2563 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2568 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2569 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2570 line_speed, init_crd);
2572 /* Probe the credit changes */
2573 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2574 usleep_range(5000, 10000);
2575 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2578 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2583 * bnx2x_get_emac_base - retrive emac base address
2585 * @bp: driver handle
2586 * @mdc_mdio_access: access type
2589 * This function selects the MDC/MDIO access (through emac0 or
2590 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2591 * phy has a default access mode, which could also be overridden
2592 * by nvram configuration. This parameter, whether this is the
2593 * default phy configuration, or the nvram overrun
2594 * configuration, is passed here as mdc_mdio_access and selects
2595 * the emac_base for the CL45 read/writes operations
2597 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2598 u32 mdc_mdio_access, u8 port)
2601 switch (mdc_mdio_access) {
2602 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2604 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2605 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2606 emac_base = GRCBASE_EMAC1;
2608 emac_base = GRCBASE_EMAC0;
2610 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2611 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2612 emac_base = GRCBASE_EMAC0;
2614 emac_base = GRCBASE_EMAC1;
2616 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2617 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2619 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2620 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2629 /******************************************************************/
2630 /* CL22 access functions */
2631 /******************************************************************/
2632 static int bnx2x_cl22_write(struct bnx2x *bp,
2633 struct bnx2x_phy *phy,
2639 /* Switch to CL22 */
2640 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2642 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2645 tmp = ((phy->addr << 21) | (reg << 16) | val |
2646 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2647 EMAC_MDIO_COMM_START_BUSY);
2648 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2650 for (i = 0; i < 50; i++) {
2653 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2654 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2659 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2660 DP(NETIF_MSG_LINK, "write phy register failed\n");
2663 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2667 static int bnx2x_cl22_read(struct bnx2x *bp,
2668 struct bnx2x_phy *phy,
2669 u16 reg, u16 *ret_val)
2675 /* Switch to CL22 */
2676 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2677 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2678 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2681 val = ((phy->addr << 21) | (reg << 16) |
2682 EMAC_MDIO_COMM_COMMAND_READ_22 |
2683 EMAC_MDIO_COMM_START_BUSY);
2684 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2686 for (i = 0; i < 50; i++) {
2689 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2690 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2691 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2696 if (val & EMAC_MDIO_COMM_START_BUSY) {
2697 DP(NETIF_MSG_LINK, "read phy register failed\n");
2702 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2706 /******************************************************************/
2707 /* CL45 access functions */
2708 /******************************************************************/
2709 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2710 u8 devad, u16 reg, u16 *ret_val)
2716 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2717 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2718 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2719 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2722 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2723 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2724 EMAC_MDIO_STATUS_10MB);
2726 val = ((phy->addr << 21) | (devad << 16) | reg |
2727 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2728 EMAC_MDIO_COMM_START_BUSY);
2729 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2731 for (i = 0; i < 50; i++) {
2734 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2735 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2740 if (val & EMAC_MDIO_COMM_START_BUSY) {
2741 DP(NETIF_MSG_LINK, "read phy register failed\n");
2742 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2747 val = ((phy->addr << 21) | (devad << 16) |
2748 EMAC_MDIO_COMM_COMMAND_READ_45 |
2749 EMAC_MDIO_COMM_START_BUSY);
2750 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2752 for (i = 0; i < 50; i++) {
2755 val = REG_RD(bp, phy->mdio_ctrl +
2756 EMAC_REG_EMAC_MDIO_COMM);
2757 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2758 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2762 if (val & EMAC_MDIO_COMM_START_BUSY) {
2763 DP(NETIF_MSG_LINK, "read phy register failed\n");
2764 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2769 /* Work around for E3 A0 */
2770 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2771 phy->flags ^= FLAGS_DUMMY_READ;
2772 if (phy->flags & FLAGS_DUMMY_READ) {
2774 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2778 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2779 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2780 EMAC_MDIO_STATUS_10MB);
2784 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2785 u8 devad, u16 reg, u16 val)
2791 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2792 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2793 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2794 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2797 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2798 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2799 EMAC_MDIO_STATUS_10MB);
2802 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2803 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2804 EMAC_MDIO_COMM_START_BUSY);
2805 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2807 for (i = 0; i < 50; i++) {
2810 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2811 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2816 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2817 DP(NETIF_MSG_LINK, "write phy register failed\n");
2818 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2822 tmp = ((phy->addr << 21) | (devad << 16) | val |
2823 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2824 EMAC_MDIO_COMM_START_BUSY);
2825 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2827 for (i = 0; i < 50; i++) {
2830 tmp = REG_RD(bp, phy->mdio_ctrl +
2831 EMAC_REG_EMAC_MDIO_COMM);
2832 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2837 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2838 DP(NETIF_MSG_LINK, "write phy register failed\n");
2839 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2843 /* Work around for E3 A0 */
2844 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2845 phy->flags ^= FLAGS_DUMMY_READ;
2846 if (phy->flags & FLAGS_DUMMY_READ) {
2848 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2851 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2852 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2853 EMAC_MDIO_STATUS_10MB);
2857 /******************************************************************/
2859 /******************************************************************/
2860 static u8 bnx2x_eee_has_cap(struct link_params *params)
2862 struct bnx2x *bp = params->bp;
2864 if (REG_RD(bp, params->shmem2_base) <=
2865 offsetof(struct shmem2_region, eee_status[params->port]))
2871 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2873 switch (nvram_mode) {
2874 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2875 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2877 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2878 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2880 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2881 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2891 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2893 switch (idle_timer) {
2894 case EEE_MODE_NVRAM_BALANCED_TIME:
2895 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2897 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2898 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2900 case EEE_MODE_NVRAM_LATENCY_TIME:
2901 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2904 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2911 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2913 u32 eee_mode, eee_idle;
2914 struct bnx2x *bp = params->bp;
2916 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2917 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2918 /* time value in eee_mode --> used directly*/
2919 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2921 /* hsi value in eee_mode --> time */
2922 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2923 EEE_MODE_NVRAM_MASK,
2928 /* hsi values in nvram --> time*/
2929 eee_mode = ((REG_RD(bp, params->shmem_base +
2930 offsetof(struct shmem_region, dev_info.
2931 port_feature_config[params->port].
2933 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2934 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2936 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2943 static int bnx2x_eee_set_timers(struct link_params *params,
2944 struct link_vars *vars)
2946 u32 eee_idle = 0, eee_mode;
2947 struct bnx2x *bp = params->bp;
2949 eee_idle = bnx2x_eee_calc_timer(params);
2952 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2954 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2955 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2956 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2957 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2961 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2962 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2963 /* eee_idle in 1u --> eee_status in 16u */
2965 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2966 SHMEM_EEE_TIME_OUTPUT_BIT;
2968 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2970 vars->eee_status |= eee_mode;
2976 static int bnx2x_eee_initial_config(struct link_params *params,
2977 struct link_vars *vars, u8 mode)
2979 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2981 /* Propogate params' bits --> vars (for migration exposure) */
2982 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2983 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2985 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2987 if (params->eee_mode & EEE_MODE_ADV_LPI)
2988 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2990 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2992 return bnx2x_eee_set_timers(params, vars);
2995 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2996 struct link_params *params,
2997 struct link_vars *vars)
2999 struct bnx2x *bp = params->bp;
3001 /* Make Certain LPI is disabled */
3002 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3004 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3006 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3011 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3012 struct link_params *params,
3013 struct link_vars *vars, u8 modes)
3015 struct bnx2x *bp = params->bp;
3018 /* Mask events preventing LPI generation */
3019 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3021 if (modes & SHMEM_EEE_10G_ADV) {
3022 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3025 if (modes & SHMEM_EEE_1G_ADV) {
3026 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3030 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3032 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3033 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3038 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3040 struct bnx2x *bp = params->bp;
3042 if (bnx2x_eee_has_cap(params))
3043 REG_WR(bp, params->shmem2_base +
3044 offsetof(struct shmem2_region,
3045 eee_status[params->port]), eee_status);
3048 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3049 struct link_params *params,
3050 struct link_vars *vars)
3052 struct bnx2x *bp = params->bp;
3053 u16 adv = 0, lp = 0;
3057 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3058 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3061 lp_adv |= SHMEM_EEE_100M_ADV;
3063 if (vars->line_speed == SPEED_100)
3065 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3069 lp_adv |= SHMEM_EEE_1G_ADV;
3071 if (vars->line_speed == SPEED_1000)
3073 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3077 lp_adv |= SHMEM_EEE_10G_ADV;
3079 if (vars->line_speed == SPEED_10000)
3081 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3085 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3086 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3089 DP(NETIF_MSG_LINK, "EEE is active\n");
3090 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3095 /******************************************************************/
3096 /* BSC access functions from E3 */
3097 /******************************************************************/
3098 static void bnx2x_bsc_module_sel(struct link_params *params)
3101 u32 board_cfg, sfp_ctrl;
3102 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3103 struct bnx2x *bp = params->bp;
3104 u8 port = params->port;
3105 /* Read I2C output PINs */
3106 board_cfg = REG_RD(bp, params->shmem_base +
3107 offsetof(struct shmem_region,
3108 dev_info.shared_hw_config.board));
3109 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3110 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3111 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3113 /* Read I2C output value */
3114 sfp_ctrl = REG_RD(bp, params->shmem_base +
3115 offsetof(struct shmem_region,
3116 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3117 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3118 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3119 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3120 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3121 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3124 static int bnx2x_bsc_read(struct link_params *params,
3135 if (xfer_cnt > 16) {
3136 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3140 bnx2x_bsc_module_sel(params);
3142 xfer_cnt = 16 - lc_addr;
3144 /* Enable the engine */
3145 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146 val |= MCPR_IMC_COMMAND_ENABLE;
3147 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3149 /* Program slave device ID */
3150 val = (sl_devid << 16) | sl_addr;
3151 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3153 /* Start xfer with 0 byte to update the address pointer ???*/
3154 val = (MCPR_IMC_COMMAND_ENABLE) |
3155 (MCPR_IMC_COMMAND_WRITE_OP <<
3156 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3160 /* Poll for completion */
3162 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3165 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3167 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3176 /* Start xfer with read op */
3177 val = (MCPR_IMC_COMMAND_ENABLE) |
3178 (MCPR_IMC_COMMAND_READ_OP <<
3179 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3182 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3184 /* Poll for completion */
3186 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3189 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3191 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3199 for (i = (lc_addr >> 2); i < 4; i++) {
3200 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3202 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203 ((data_array[i] & 0x0000ff00) << 8) |
3204 ((data_array[i] & 0x00ff0000) >> 8) |
3205 ((data_array[i] & 0xff000000) >> 24);
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212 u8 devad, u16 reg, u16 or_val)
3215 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220 struct bnx2x_phy *phy,
3221 u8 devad, u16 reg, u16 and_val)
3224 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229 u8 devad, u16 reg, u16 *ret_val)
3232 /* Probe for the phy according to the given phy_addr, and execute
3233 * the read request on it
3235 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236 if (params->phy[phy_index].addr == phy_addr) {
3237 return bnx2x_cl45_read(params->bp,
3238 ¶ms->phy[phy_index], devad,
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246 u8 devad, u16 reg, u16 val)
3249 /* Probe for the phy according to the given phy_addr, and execute
3250 * the write request on it
3252 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253 if (params->phy[phy_index].addr == phy_addr) {
3254 return bnx2x_cl45_write(params->bp,
3255 ¶ms->phy[phy_index], devad,
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262 struct link_params *params)
3265 struct bnx2x *bp = params->bp;
3266 u32 path_swap, path_swap_ovr;
3270 port = params->port;
3272 if (bnx2x_is_4_port_mode(bp)) {
3273 u32 port_swap, port_swap_ovr;
3275 /* Figure out path swap value */
3276 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277 if (path_swap_ovr & 0x1)
3278 path_swap = (path_swap_ovr & 0x2);
3280 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3285 /* Figure out port swap value */
3286 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287 if (port_swap_ovr & 0x1)
3288 port_swap = (port_swap_ovr & 0x2);
3290 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3295 lane = (port<<1) + path;
3296 } else { /* Two port mode - no port swap */
3298 /* Figure out path swap value */
3300 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301 if (path_swap_ovr & 0x1) {
3302 path_swap = (path_swap_ovr & 0x2);
3305 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316 struct bnx2x_phy *phy)
3319 u16 offset, aer_val;
3320 struct bnx2x *bp = params->bp;
3321 ser_lane = ((params->lane_config &
3322 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3325 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326 (phy->addr + ser_lane) : 0;
3328 if (USES_WARPCORE(bp)) {
3329 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330 /* In Dual-lane mode, two lanes are joined together,
3331 * so in order to configure them, the AER broadcast method is
3333 * 0x200 is the broadcast address for lanes 0,1
3334 * 0x201 is the broadcast address for lanes 2,3
3336 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337 aer_val = (aer_val >> 1) | 0x200;
3338 } else if (CHIP_IS_E2(bp))
3339 aer_val = 0x3800 + offset - 1;
3341 aer_val = 0x3800 + offset;
3343 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344 MDIO_AER_BLOCK_AER_REG, aer_val);
3348 /******************************************************************/
3349 /* Internal phy section */
3350 /******************************************************************/
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3354 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3357 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3360 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3363 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3370 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3372 val = SERDES_RESET_BITS << (port*16);
3374 /* Reset and unreset the SerDes/XGXS */
3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3379 bnx2x_set_serdes_access(bp, port);
3381 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382 DEFAULT_PHY_DEV_ADDR);
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386 struct link_params *params,
3389 struct bnx2x *bp = params->bp;
3392 /* Set correct devad */
3393 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3402 struct bnx2x *bp = params->bp;
3405 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406 port = params->port;
3408 val = XGXS_RESET_BITS << (port*16);
3410 /* Reset and unreset the SerDes/XGXS */
3411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3413 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params,
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419 struct link_params *params, u16 *ieee_fc)
3421 struct bnx2x *bp = params->bp;
3422 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423 /* Resolve pause mode and advertisement Please refer to Table
3424 * 28B-3 of the 802.3ab-1999 spec
3427 switch (phy->req_flow_ctrl) {
3428 case BNX2X_FLOW_CTRL_AUTO:
3429 switch (params->req_fc_auto_adv) {
3430 case BNX2X_FLOW_CTRL_BOTH:
3431 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3433 case BNX2X_FLOW_CTRL_RX:
3434 case BNX2X_FLOW_CTRL_TX:
3436 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3442 case BNX2X_FLOW_CTRL_TX:
3443 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3446 case BNX2X_FLOW_CTRL_RX:
3447 case BNX2X_FLOW_CTRL_BOTH:
3448 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3451 case BNX2X_FLOW_CTRL_NONE:
3453 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3456 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3459 static void set_phy_vars(struct link_params *params,
3460 struct link_vars *vars)
3462 struct bnx2x *bp = params->bp;
3463 u8 actual_phy_idx, phy_index, link_cfg_idx;
3464 u8 phy_config_swapped = params->multi_phy_config &
3465 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3466 for (phy_index = INT_PHY; phy_index < params->num_phys;
3468 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3469 actual_phy_idx = phy_index;
3470 if (phy_config_swapped) {
3471 if (phy_index == EXT_PHY1)
3472 actual_phy_idx = EXT_PHY2;
3473 else if (phy_index == EXT_PHY2)
3474 actual_phy_idx = EXT_PHY1;
3476 params->phy[actual_phy_idx].req_flow_ctrl =
3477 params->req_flow_ctrl[link_cfg_idx];
3479 params->phy[actual_phy_idx].req_line_speed =
3480 params->req_line_speed[link_cfg_idx];
3482 params->phy[actual_phy_idx].speed_cap_mask =
3483 params->speed_cap_mask[link_cfg_idx];
3485 params->phy[actual_phy_idx].req_duplex =
3486 params->req_duplex[link_cfg_idx];
3488 if (params->req_line_speed[link_cfg_idx] ==
3490 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3492 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3493 " speed_cap_mask %x\n",
3494 params->phy[actual_phy_idx].req_flow_ctrl,
3495 params->phy[actual_phy_idx].req_line_speed,
3496 params->phy[actual_phy_idx].speed_cap_mask);
3500 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3501 struct bnx2x_phy *phy,
3502 struct link_vars *vars)
3505 struct bnx2x *bp = params->bp;
3506 /* Read modify write pause advertizing */
3507 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3509 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3511 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3512 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3513 if ((vars->ieee_fc &
3514 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3515 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3516 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3518 if ((vars->ieee_fc &
3519 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3520 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3521 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3523 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3524 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3527 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3529 switch (pause_result) { /* ASYM P ASYM P */
3530 case 0xb: /* 1 0 1 1 */
3531 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3534 case 0xe: /* 1 1 1 0 */
3535 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3538 case 0x5: /* 0 1 0 1 */
3539 case 0x7: /* 0 1 1 1 */
3540 case 0xd: /* 1 1 0 1 */
3541 case 0xf: /* 1 1 1 1 */
3542 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3548 if (pause_result & (1<<0))
3549 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3550 if (pause_result & (1<<1))
3551 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3556 struct link_params *params,
3557 struct link_vars *vars)
3559 u16 ld_pause; /* local */
3560 u16 lp_pause; /* link partner */
3562 struct bnx2x *bp = params->bp;
3563 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3564 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3565 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3566 } else if (CHIP_IS_E3(bp) &&
3567 SINGLE_MEDIA_DIRECT(params)) {
3568 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3569 u16 gp_status, gp_mask;
3570 bnx2x_cl45_read(bp, phy,
3571 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3573 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3574 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3576 if ((gp_status & gp_mask) == gp_mask) {
3577 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3578 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3579 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3580 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3582 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3583 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3584 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3585 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3586 ld_pause = ((ld_pause &
3587 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3589 lp_pause = ((lp_pause &
3590 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3594 bnx2x_cl45_read(bp, phy,
3596 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3597 bnx2x_cl45_read(bp, phy,
3599 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3601 pause_result = (ld_pause &
3602 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3603 pause_result |= (lp_pause &
3604 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3605 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3606 bnx2x_pause_resolve(vars, pause_result);
3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3611 struct link_params *params,
3612 struct link_vars *vars)
3615 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3616 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3617 /* Update the advertised flow-controled of LD/LP in AN */
3618 if (phy->req_line_speed == SPEED_AUTO_NEG)
3619 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3620 /* But set the flow-control result as the requested one */
3621 vars->flow_ctrl = phy->req_flow_ctrl;
3622 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3623 vars->flow_ctrl = params->req_fc_auto_adv;
3624 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3626 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3630 /******************************************************************/
3631 /* Warpcore section */
3632 /******************************************************************/
3633 /* The init_internal_warpcore should mirror the xgxs,
3634 * i.e. reset the lane (if needed), set aer for the
3635 * init configuration, and set/clear SGMII flag. Internal
3636 * phy init is done purely in phy_init stage.
3638 #define WC_TX_DRIVER(post2, idriver, ipre) \
3639 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3640 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3641 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3643 #define WC_TX_FIR(post, main, pre) \
3644 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3645 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3646 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3649 struct link_params *params,
3650 struct link_vars *vars)
3652 struct bnx2x *bp = params->bp;
3654 static struct bnx2x_reg_set reg_set[] = {
3655 /* Step 1 - Program the TX/RX alignment markers */
3656 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3658 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3659 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3660 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3661 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3662 /* Step 2 - Configure the NP registers */
3663 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3664 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3665 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3666 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3667 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3668 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3669 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3670 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3671 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3673 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3675 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3676 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3678 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3682 /* Start KR2 work-around timer which handles BCM8073 link-parner */
3683 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3684 bnx2x_update_link_attr(params, vars->link_attr_sync);
3687 static void bnx2x_disable_kr2(struct link_params *params,
3688 struct link_vars *vars,
3689 struct bnx2x_phy *phy)
3691 struct bnx2x *bp = params->bp;
3693 static struct bnx2x_reg_set reg_set[] = {
3694 /* Step 1 - Program the TX/RX alignment markers */
3695 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3696 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3697 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3698 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3699 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3700 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3701 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3702 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3703 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3704 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3705 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3706 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3707 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3708 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3709 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3711 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3713 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3714 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3716 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3717 bnx2x_update_link_attr(params, vars->link_attr_sync);
3719 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3722 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3723 struct link_params *params)
3725 struct bnx2x *bp = params->bp;
3727 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3728 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3729 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3730 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3731 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3734 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3735 struct link_params *params)
3737 /* Restart autoneg on the leading lane only */
3738 struct bnx2x *bp = params->bp;
3739 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3740 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3741 MDIO_AER_BLOCK_AER_REG, lane);
3742 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3743 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3746 bnx2x_set_aer_mmd(params, phy);
3749 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3750 struct link_params *params,
3751 struct link_vars *vars) {
3752 u16 lane, i, cl72_ctrl, an_adv = 0;
3753 struct bnx2x *bp = params->bp;
3754 static struct bnx2x_reg_set reg_set[] = {
3755 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3756 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3757 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3758 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3759 /* Disable Autoneg: re-enable it after adv is done. */
3760 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3761 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3762 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3764 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3765 /* Set to default registers that may be overriden by 10G force */
3766 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3767 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3770 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3771 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3772 cl72_ctrl &= 0x08ff;
3773 cl72_ctrl |= 0x3800;
3774 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3775 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3777 /* Check adding advertisement for 1G KX */
3778 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3779 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3780 (vars->line_speed == SPEED_1000)) {
3781 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3784 /* Enable CL37 1G Parallel Detect */
3785 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3786 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3788 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3789 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3790 (vars->line_speed == SPEED_10000)) {
3791 /* Check adding advertisement for 10G KR */
3793 /* Enable 10G Parallel Detect */
3794 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3795 MDIO_AER_BLOCK_AER_REG, 0);
3797 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3798 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3799 bnx2x_set_aer_mmd(params, phy);
3800 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3803 /* Set Transmit PMD settings */
3804 lane = bnx2x_get_warpcore_lane(phy, params);
3805 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3806 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3807 WC_TX_DRIVER(0x02, 0x06, 0x09));
3808 /* Configure the next lane if dual mode */
3809 if (phy->flags & FLAGS_WC_DUAL_MODE)
3810 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3811 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3812 WC_TX_DRIVER(0x02, 0x06, 0x09));
3813 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3816 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3820 /* Advertised speeds */
3821 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3822 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3824 /* Advertised and set FEC (Forward Error Correction) */
3825 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3826 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3827 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3828 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3830 /* Enable CL37 BAM */
3831 if (REG_RD(bp, params->shmem_base +
3832 offsetof(struct shmem_region, dev_info.
3833 port_hw_config[params->port].default_cfg)) &
3834 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3835 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3836 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3838 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3841 /* Advertise pause */
3842 bnx2x_ext_phy_set_pause(params, phy, vars);
3843 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3844 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3845 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3847 /* Over 1G - AN local device user page 1 */
3848 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3851 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3852 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3853 (phy->req_line_speed == SPEED_20000)) {
3855 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3856 MDIO_AER_BLOCK_AER_REG, lane);
3858 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3859 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3862 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3863 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3864 bnx2x_set_aer_mmd(params, phy);
3866 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3868 bnx2x_disable_kr2(params, vars, phy);
3871 /* Enable Autoneg: only on the main lane */
3872 bnx2x_warpcore_restart_AN_KR(phy, params);
3875 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3876 struct link_params *params,
3877 struct link_vars *vars)
3879 struct bnx2x *bp = params->bp;
3881 static struct bnx2x_reg_set reg_set[] = {
3882 /* Disable Autoneg */
3883 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3884 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3886 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3887 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3888 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3889 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3890 /* Leave cl72 training enable, needed for KR */
3891 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3894 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3895 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3898 lane = bnx2x_get_warpcore_lane(phy, params);
3899 /* Global registers */
3900 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3901 MDIO_AER_BLOCK_AER_REG, 0);
3902 /* Disable CL36 PCS Tx */
3903 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3905 val16 &= ~(0x0011 << lane);
3906 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3907 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3909 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3910 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3911 val16 |= (0x0303 << (lane << 1));
3912 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3913 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3915 bnx2x_set_aer_mmd(params, phy);
3916 /* Set speed via PMA/PMD register */
3917 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3918 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3920 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3921 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3923 /* Enable encoded forced speed */
3924 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3925 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3927 /* Turn TX scramble payload only the 64/66 scrambler */
3928 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3929 MDIO_WC_REG_TX66_CONTROL, 0x9);
3931 /* Turn RX scramble payload only the 64/66 scrambler */
3932 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3933 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3935 /* Set and clear loopback to cause a reset to 64/66 decoder */
3936 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3938 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3939 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3943 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3944 struct link_params *params,
3947 struct bnx2x *bp = params->bp;
3948 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3949 u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3951 /* Hold rxSeqStart */
3952 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3953 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3955 /* Hold tx_fifo_reset */
3956 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3957 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3959 /* Disable CL73 AN */
3960 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3962 /* Disable 100FX Enable and Auto-Detect */
3963 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3964 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3966 /* Disable 100FX Idle detect */
3967 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3968 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3970 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3971 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3972 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3974 /* Turn off auto-detect & fiber mode */
3975 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3976 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3979 /* Set filter_force_link, disable_false_link and parallel_detect */
3980 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3981 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3982 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3983 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3984 ((val | 0x0006) & 0xFFFE));
3987 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3988 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3990 misc1_val &= ~(0x1f);
3994 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3995 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3997 cfg_tap_val = REG_RD(bp, params->shmem_base +
3998 offsetof(struct shmem_region, dev_info.
3999 port_hw_config[params->port].
4002 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4004 tx_drv_brdct = (cfg_tap_val &
4005 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4006 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4010 /* TAP values are controlled by nvram, if value there isn't 0 */
4012 tap_val = (u16)tx_equal;
4014 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4017 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
4020 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4025 /* Set Transmit PMD settings */
4026 lane = bnx2x_get_warpcore_lane(phy, params);
4027 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4028 MDIO_WC_REG_TX_FIR_TAP,
4029 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4030 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4031 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4034 /* Enable fiber mode, enable and invert sig_det */
4035 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4036 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4038 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4039 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4040 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4042 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4044 /* 10G XFI Full Duplex */
4045 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4048 /* Release tx_fifo_reset */
4049 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4050 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4052 /* Release rxSeqStart */
4053 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4054 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4057 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4058 struct link_params *params)
4061 struct bnx2x *bp = params->bp;
4062 /* Set global registers, so set AER lane to 0 */
4063 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4064 MDIO_AER_BLOCK_AER_REG, 0);
4066 /* Disable sequencer */
4067 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4068 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4070 bnx2x_set_aer_mmd(params, phy);
4072 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4073 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4074 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4075 MDIO_AN_REG_CTRL, 0);
4077 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4078 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4081 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4082 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4084 /* Set 20G KR2 force speed */
4085 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4086 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4088 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4089 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4091 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4092 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4095 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4096 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4100 /* Enable sequencer (over lane 0) */
4101 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4102 MDIO_AER_BLOCK_AER_REG, 0);
4104 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4105 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4107 bnx2x_set_aer_mmd(params, phy);
4110 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4111 struct bnx2x_phy *phy,
4114 /* Rx0 anaRxControl1G */
4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4116 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4118 /* Rx2 anaRxControl1G */
4119 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4120 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4122 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4123 MDIO_WC_REG_RX66_SCW0, 0xE070);
4125 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4128 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4129 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4131 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4132 MDIO_WC_REG_RX66_SCW3, 0x8090);
4134 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4135 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4137 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4138 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4140 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4141 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4143 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4144 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4146 /* Serdes Digital Misc1 */
4147 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4150 /* Serdes Digital4 Misc3 */
4151 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4152 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4154 /* Set Transmit PMD settings */
4155 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4156 MDIO_WC_REG_TX_FIR_TAP,
4157 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4158 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4159 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4161 WC_TX_DRIVER(0x02, 0x02, 0x02));
4164 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4165 struct link_params *params,
4169 struct bnx2x *bp = params->bp;
4170 u16 val16, digctrl_kx1, digctrl_kx2;
4172 /* Clear XFI clock comp in non-10G single lane mode. */
4173 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4174 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4176 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4178 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4180 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4181 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4183 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4185 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4186 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4188 switch (phy->req_line_speed) {
4199 "Speed not supported: 0x%x\n", phy->req_line_speed);
4203 if (phy->req_duplex == DUPLEX_FULL)
4206 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4207 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4209 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4210 phy->req_line_speed);
4211 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4212 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4213 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4216 /* SGMII Slave mode and disable signal detect */
4217 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4218 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4222 digctrl_kx1 &= 0xff4a;
4224 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4225 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4228 /* Turn off parallel detect */
4229 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4230 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4231 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4232 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4233 (digctrl_kx2 & ~(1<<2)));
4235 /* Re-enable parallel detect */
4236 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4237 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4238 (digctrl_kx2 | (1<<2)));
4240 /* Enable autodet */
4241 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4242 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4243 (digctrl_kx1 | 0x10));
4246 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4247 struct bnx2x_phy *phy,
4251 /* Take lane out of reset after configuration is finished */
4252 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4253 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4258 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259 MDIO_WC_REG_DIGITAL5_MISC6, val);
4260 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4261 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4263 /* Clear SFI/XFI link settings registers */
4264 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4265 struct link_params *params,
4268 struct bnx2x *bp = params->bp;
4270 static struct bnx2x_reg_set wc_regs[] = {
4271 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4272 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4273 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4274 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4275 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4277 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4279 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4281 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4282 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4283 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4284 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4286 /* Set XFI clock comp as default. */
4287 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4288 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4290 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4291 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4294 lane = bnx2x_get_warpcore_lane(phy, params);
4295 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4296 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4300 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4302 u32 shmem_base, u8 port,
4303 u8 *gpio_num, u8 *gpio_port)
4308 if (CHIP_IS_E3(bp)) {
4309 cfg_pin = (REG_RD(bp, shmem_base +
4310 offsetof(struct shmem_region,
4311 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4312 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4313 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4315 /* Should not happen. This function called upon interrupt
4316 * triggered by GPIO ( since EPIO can only generate interrupts
4318 * So if this function was called and none of the GPIOs was set,
4319 * it means the shit hit the fan.
4321 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4322 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4324 "No cfg pin %x for module detect indication\n",
4329 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4330 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4332 *gpio_num = MISC_REGISTERS_GPIO_3;
4339 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4340 struct link_params *params)
4342 struct bnx2x *bp = params->bp;
4343 u8 gpio_num, gpio_port;
4345 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4346 params->shmem_base, params->port,
4347 &gpio_num, &gpio_port) != 0)
4349 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4351 /* Call the handling function in case module is detected */
4357 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4358 struct link_params *params)
4360 u16 gp2_status_reg0, lane;
4361 struct bnx2x *bp = params->bp;
4363 lane = bnx2x_get_warpcore_lane(phy, params);
4365 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4368 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4371 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4372 struct link_params *params,
4373 struct link_vars *vars)
4375 struct bnx2x *bp = params->bp;
4377 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4379 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4381 if (!vars->turn_to_run_wc_rt)
4384 if (vars->rx_tx_asic_rst) {
4385 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4386 serdes_net_if = (REG_RD(bp, params->shmem_base +
4387 offsetof(struct shmem_region, dev_info.
4388 port_hw_config[params->port].default_cfg)) &
4389 PORT_HW_CFG_NET_SERDES_IF_MASK);
4391 switch (serdes_net_if) {
4392 case PORT_HW_CFG_NET_SERDES_IF_KR:
4393 /* Do we get link yet? */
4394 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4396 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4398 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4400 if (lnkup_kr || lnkup) {
4401 vars->rx_tx_asic_rst = 0;
4403 /* Reset the lane to see if link comes up.*/
4404 bnx2x_warpcore_reset_lane(bp, phy, 1);
4405 bnx2x_warpcore_reset_lane(bp, phy, 0);
4407 /* Restart Autoneg */
4408 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4409 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4411 vars->rx_tx_asic_rst--;
4412 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4413 vars->rx_tx_asic_rst);
4421 } /*params->rx_tx_asic_rst*/
4424 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4425 struct link_params *params)
4427 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4428 struct bnx2x *bp = params->bp;
4429 bnx2x_warpcore_clear_regs(phy, params, lane);
4430 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4432 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4433 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4434 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4436 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4437 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4441 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4442 struct bnx2x_phy *phy,
4445 struct bnx2x *bp = params->bp;
4447 u8 port = params->port;
4449 cfg_pin = REG_RD(bp, params->shmem_base +
4450 offsetof(struct shmem_region,
4451 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4452 PORT_HW_CFG_E3_TX_LASER_MASK;
4453 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4454 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4456 /* For 20G, the expected pin to be used is 3 pins after the current */
4457 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4458 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4459 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4462 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4463 struct link_params *params,
4464 struct link_vars *vars)
4466 struct bnx2x *bp = params->bp;
4469 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4470 serdes_net_if = (REG_RD(bp, params->shmem_base +
4471 offsetof(struct shmem_region, dev_info.
4472 port_hw_config[params->port].default_cfg)) &
4473 PORT_HW_CFG_NET_SERDES_IF_MASK);
4474 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4475 "serdes_net_if = 0x%x\n",
4476 vars->line_speed, serdes_net_if);
4477 bnx2x_set_aer_mmd(params, phy);
4478 bnx2x_warpcore_reset_lane(bp, phy, 1);
4479 vars->phy_flags |= PHY_XGXS_FLAG;
4480 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4481 (phy->req_line_speed &&
4482 ((phy->req_line_speed == SPEED_100) ||
4483 (phy->req_line_speed == SPEED_10)))) {
4484 vars->phy_flags |= PHY_SGMII_FLAG;
4485 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4486 bnx2x_warpcore_clear_regs(phy, params, lane);
4487 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4489 switch (serdes_net_if) {
4490 case PORT_HW_CFG_NET_SERDES_IF_KR:
4491 /* Enable KR Auto Neg */
4492 if (params->loopback_mode != LOOPBACK_EXT)
4493 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4495 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4496 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4500 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4501 bnx2x_warpcore_clear_regs(phy, params, lane);
4502 if (vars->line_speed == SPEED_10000) {
4503 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4504 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4506 if (SINGLE_MEDIA_DIRECT(params)) {
4507 DP(NETIF_MSG_LINK, "1G Fiber\n");
4510 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4513 bnx2x_warpcore_set_sgmii_speed(phy,
4521 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4522 /* Issue Module detection if module is plugged, or
4523 * enabled transmitter to avoid current leakage in case
4524 * no module is connected
4526 if ((params->loopback_mode == LOOPBACK_NONE) ||
4527 (params->loopback_mode == LOOPBACK_EXT)) {
4528 if (bnx2x_is_sfp_module_plugged(phy, params))
4529 bnx2x_sfp_module_detection(phy, params);
4531 bnx2x_sfp_e3_set_transmitter(params,
4535 bnx2x_warpcore_config_sfi(phy, params);
4538 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4539 if (vars->line_speed != SPEED_20000) {
4540 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4543 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4544 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4545 /* Issue Module detection */
4547 bnx2x_sfp_module_detection(phy, params);
4549 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4550 if (!params->loopback_mode) {
4551 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4553 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4554 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4559 "Unsupported Serdes Net Interface 0x%x\n",
4565 /* Take lane out of reset after configuration is finished */
4566 bnx2x_warpcore_reset_lane(bp, phy, 0);
4567 DP(NETIF_MSG_LINK, "Exit config init\n");
4570 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4571 struct link_params *params)
4573 struct bnx2x *bp = params->bp;
4575 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4576 bnx2x_set_mdio_emac_per_phy(bp, params);
4577 bnx2x_set_aer_mmd(params, phy);
4578 /* Global register */
4579 bnx2x_warpcore_reset_lane(bp, phy, 1);
4581 /* Clear loopback settings (if any) */
4583 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4584 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4586 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4587 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4589 /* Update those 1-copy registers */
4590 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4591 MDIO_AER_BLOCK_AER_REG, 0);
4592 /* Enable 1G MDIO (1-copy) */
4593 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4594 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4597 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4598 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4599 lane = bnx2x_get_warpcore_lane(phy, params);
4600 /* Disable CL36 PCS Tx */
4601 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4602 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4603 val16 |= (0x11 << lane);
4604 if (phy->flags & FLAGS_WC_DUAL_MODE)
4605 val16 |= (0x22 << lane);
4606 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4607 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4609 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4610 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4611 val16 &= ~(0x0303 << (lane << 1));
4612 val16 |= (0x0101 << (lane << 1));
4613 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4614 val16 &= ~(0x0c0c << (lane << 1));
4615 val16 |= (0x0404 << (lane << 1));
4618 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4619 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4621 bnx2x_set_aer_mmd(params, phy);
4625 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4626 struct link_params *params)
4628 struct bnx2x *bp = params->bp;
4631 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4632 params->loopback_mode, phy->req_line_speed);
4634 if (phy->req_line_speed < SPEED_10000 ||
4635 phy->supported & SUPPORTED_20000baseKR2_Full) {
4636 /* 10/100/1000/20G-KR2 */
4638 /* Update those 1-copy registers */
4639 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4640 MDIO_AER_BLOCK_AER_REG, 0);
4641 /* Enable 1G MDIO (1-copy) */
4642 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4643 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4645 /* Set 1G loopback based on lane (1-copy) */
4646 lane = bnx2x_get_warpcore_lane(phy, params);
4647 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4648 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4650 if (phy->flags & FLAGS_WC_DUAL_MODE)
4652 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4653 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4656 /* Switch back to 4-copy registers */
4657 bnx2x_set_aer_mmd(params, phy);
4659 /* 10G / 20G-DXGXS */
4660 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4661 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4663 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4664 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4670 static void bnx2x_sync_link(struct link_params *params,
4671 struct link_vars *vars)
4673 struct bnx2x *bp = params->bp;
4675 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4676 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4677 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4678 if (vars->link_up) {
4679 DP(NETIF_MSG_LINK, "phy link up\n");
4681 vars->phy_link_up = 1;
4682 vars->duplex = DUPLEX_FULL;
4683 switch (vars->link_status &
4684 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4686 vars->duplex = DUPLEX_HALF;
4689 vars->line_speed = SPEED_10;
4693 vars->duplex = DUPLEX_HALF;
4697 vars->line_speed = SPEED_100;
4701 vars->duplex = DUPLEX_HALF;
4704 vars->line_speed = SPEED_1000;
4708 vars->duplex = DUPLEX_HALF;
4711 vars->line_speed = SPEED_2500;
4715 vars->line_speed = SPEED_10000;
4718 vars->line_speed = SPEED_20000;
4723 vars->flow_ctrl = 0;
4724 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4725 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4727 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4728 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4730 if (!vars->flow_ctrl)
4731 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4733 if (vars->line_speed &&
4734 ((vars->line_speed == SPEED_10) ||
4735 (vars->line_speed == SPEED_100))) {
4736 vars->phy_flags |= PHY_SGMII_FLAG;
4738 vars->phy_flags &= ~PHY_SGMII_FLAG;
4740 if (vars->line_speed &&
4741 USES_WARPCORE(bp) &&
4742 (vars->line_speed == SPEED_1000))
4743 vars->phy_flags |= PHY_SGMII_FLAG;
4744 /* Anything 10 and over uses the bmac */
4745 link_10g_plus = (vars->line_speed >= SPEED_10000);
4747 if (link_10g_plus) {
4748 if (USES_WARPCORE(bp))
4749 vars->mac_type = MAC_TYPE_XMAC;
4751 vars->mac_type = MAC_TYPE_BMAC;
4753 if (USES_WARPCORE(bp))
4754 vars->mac_type = MAC_TYPE_UMAC;
4756 vars->mac_type = MAC_TYPE_EMAC;
4758 } else { /* Link down */
4759 DP(NETIF_MSG_LINK, "phy link down\n");
4761 vars->phy_link_up = 0;
4763 vars->line_speed = 0;
4764 vars->duplex = DUPLEX_FULL;
4765 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4767 /* Indicate no mac active */
4768 vars->mac_type = MAC_TYPE_NONE;
4769 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4770 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4771 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4772 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4776 void bnx2x_link_status_update(struct link_params *params,
4777 struct link_vars *vars)
4779 struct bnx2x *bp = params->bp;
4780 u8 port = params->port;
4781 u32 sync_offset, media_types;
4782 /* Update PHY configuration */
4783 set_phy_vars(params, vars);
4785 vars->link_status = REG_RD(bp, params->shmem_base +
4786 offsetof(struct shmem_region,
4787 port_mb[port].link_status));
4789 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4790 if (params->loopback_mode != LOOPBACK_NONE &&
4791 params->loopback_mode != LOOPBACK_EXT)
4792 vars->link_status |= LINK_STATUS_LINK_UP;
4794 if (bnx2x_eee_has_cap(params))
4795 vars->eee_status = REG_RD(bp, params->shmem2_base +
4796 offsetof(struct shmem2_region,
4797 eee_status[params->port]));
4799 vars->phy_flags = PHY_XGXS_FLAG;
4800 bnx2x_sync_link(params, vars);
4801 /* Sync media type */
4802 sync_offset = params->shmem_base +
4803 offsetof(struct shmem_region,
4804 dev_info.port_hw_config[port].media_type);
4805 media_types = REG_RD(bp, sync_offset);
4807 params->phy[INT_PHY].media_type =
4808 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4809 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4810 params->phy[EXT_PHY1].media_type =
4811 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4812 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4813 params->phy[EXT_PHY2].media_type =
4814 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4815 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4816 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4818 /* Sync AEU offset */
4819 sync_offset = params->shmem_base +
4820 offsetof(struct shmem_region,
4821 dev_info.port_hw_config[port].aeu_int_mask);
4823 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4825 /* Sync PFC status */
4826 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4827 params->feature_config_flags |=
4828 FEATURE_CONFIG_PFC_ENABLED;
4830 params->feature_config_flags &=
4831 ~FEATURE_CONFIG_PFC_ENABLED;
4833 if (SHMEM2_HAS(bp, link_attr_sync))
4834 vars->link_attr_sync = SHMEM2_RD(bp,
4835 link_attr_sync[params->port]);
4837 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4838 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4839 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4840 vars->line_speed, vars->duplex, vars->flow_ctrl);
4843 static void bnx2x_set_master_ln(struct link_params *params,
4844 struct bnx2x_phy *phy)
4846 struct bnx2x *bp = params->bp;
4847 u16 new_master_ln, ser_lane;
4848 ser_lane = ((params->lane_config &
4849 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4850 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4852 /* Set the master_ln for AN */
4853 CL22_RD_OVER_CL45(bp, phy,
4854 MDIO_REG_BANK_XGXS_BLOCK2,
4855 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4858 CL22_WR_OVER_CL45(bp, phy,
4859 MDIO_REG_BANK_XGXS_BLOCK2 ,
4860 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4861 (new_master_ln | ser_lane));
4864 static int bnx2x_reset_unicore(struct link_params *params,
4865 struct bnx2x_phy *phy,
4868 struct bnx2x *bp = params->bp;
4871 CL22_RD_OVER_CL45(bp, phy,
4872 MDIO_REG_BANK_COMBO_IEEE0,
4873 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4875 /* Reset the unicore */
4876 CL22_WR_OVER_CL45(bp, phy,
4877 MDIO_REG_BANK_COMBO_IEEE0,
4878 MDIO_COMBO_IEEE0_MII_CONTROL,
4880 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4882 bnx2x_set_serdes_access(bp, params->port);
4884 /* Wait for the reset to self clear */
4885 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4888 /* The reset erased the previous bank value */
4889 CL22_RD_OVER_CL45(bp, phy,
4890 MDIO_REG_BANK_COMBO_IEEE0,
4891 MDIO_COMBO_IEEE0_MII_CONTROL,
4894 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4900 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4903 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4908 static void bnx2x_set_swap_lanes(struct link_params *params,
4909 struct bnx2x_phy *phy)
4911 struct bnx2x *bp = params->bp;
4912 /* Each two bits represents a lane number:
4913 * No swap is 0123 => 0x1b no need to enable the swap
4915 u16 rx_lane_swap, tx_lane_swap;
4917 rx_lane_swap = ((params->lane_config &
4918 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4919 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4920 tx_lane_swap = ((params->lane_config &
4921 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4922 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4924 if (rx_lane_swap != 0x1b) {
4925 CL22_WR_OVER_CL45(bp, phy,
4926 MDIO_REG_BANK_XGXS_BLOCK2,
4927 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4929 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4930 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4932 CL22_WR_OVER_CL45(bp, phy,
4933 MDIO_REG_BANK_XGXS_BLOCK2,
4934 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4937 if (tx_lane_swap != 0x1b) {
4938 CL22_WR_OVER_CL45(bp, phy,
4939 MDIO_REG_BANK_XGXS_BLOCK2,
4940 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4942 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4944 CL22_WR_OVER_CL45(bp, phy,
4945 MDIO_REG_BANK_XGXS_BLOCK2,
4946 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4950 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4951 struct link_params *params)
4953 struct bnx2x *bp = params->bp;
4955 CL22_RD_OVER_CL45(bp, phy,
4956 MDIO_REG_BANK_SERDES_DIGITAL,
4957 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4959 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4960 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4962 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4963 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4964 phy->speed_cap_mask, control2);
4965 CL22_WR_OVER_CL45(bp, phy,
4966 MDIO_REG_BANK_SERDES_DIGITAL,
4967 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4970 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4971 (phy->speed_cap_mask &
4972 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4973 DP(NETIF_MSG_LINK, "XGXS\n");
4975 CL22_WR_OVER_CL45(bp, phy,
4976 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4977 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4978 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4980 CL22_RD_OVER_CL45(bp, phy,
4981 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4982 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4987 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4989 CL22_WR_OVER_CL45(bp, phy,
4990 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4991 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4994 /* Disable parallel detection of HiG */
4995 CL22_WR_OVER_CL45(bp, phy,
4996 MDIO_REG_BANK_XGXS_BLOCK2,
4997 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4998 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4999 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5003 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5004 struct link_params *params,
5005 struct link_vars *vars,
5008 struct bnx2x *bp = params->bp;
5012 CL22_RD_OVER_CL45(bp, phy,
5013 MDIO_REG_BANK_COMBO_IEEE0,
5014 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5016 /* CL37 Autoneg Enabled */
5017 if (vars->line_speed == SPEED_AUTO_NEG)
5018 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5019 else /* CL37 Autoneg Disabled */
5020 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5021 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5023 CL22_WR_OVER_CL45(bp, phy,
5024 MDIO_REG_BANK_COMBO_IEEE0,
5025 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5027 /* Enable/Disable Autodetection */
5029 CL22_RD_OVER_CL45(bp, phy,
5030 MDIO_REG_BANK_SERDES_DIGITAL,
5031 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5032 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5033 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5034 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5035 if (vars->line_speed == SPEED_AUTO_NEG)
5036 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5038 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5040 CL22_WR_OVER_CL45(bp, phy,
5041 MDIO_REG_BANK_SERDES_DIGITAL,
5042 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5044 /* Enable TetonII and BAM autoneg */
5045 CL22_RD_OVER_CL45(bp, phy,
5046 MDIO_REG_BANK_BAM_NEXT_PAGE,
5047 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5049 if (vars->line_speed == SPEED_AUTO_NEG) {
5050 /* Enable BAM aneg Mode and TetonII aneg Mode */
5051 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5052 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5054 /* TetonII and BAM Autoneg Disabled */
5055 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5056 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5058 CL22_WR_OVER_CL45(bp, phy,
5059 MDIO_REG_BANK_BAM_NEXT_PAGE,
5060 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5064 /* Enable Cl73 FSM status bits */
5065 CL22_WR_OVER_CL45(bp, phy,
5066 MDIO_REG_BANK_CL73_USERB0,
5067 MDIO_CL73_USERB0_CL73_UCTRL,
5070 /* Enable BAM Station Manager*/
5071 CL22_WR_OVER_CL45(bp, phy,
5072 MDIO_REG_BANK_CL73_USERB0,
5073 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5074 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5075 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5076 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5078 /* Advertise CL73 link speeds */
5079 CL22_RD_OVER_CL45(bp, phy,
5080 MDIO_REG_BANK_CL73_IEEEB1,
5081 MDIO_CL73_IEEEB1_AN_ADV2,
5083 if (phy->speed_cap_mask &
5084 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5085 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5086 if (phy->speed_cap_mask &
5087 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5088 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5090 CL22_WR_OVER_CL45(bp, phy,
5091 MDIO_REG_BANK_CL73_IEEEB1,
5092 MDIO_CL73_IEEEB1_AN_ADV2,
5095 /* CL73 Autoneg Enabled */
5096 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5098 } else /* CL73 Autoneg Disabled */
5101 CL22_WR_OVER_CL45(bp, phy,
5102 MDIO_REG_BANK_CL73_IEEEB0,
5103 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5106 /* Program SerDes, forced speed */
5107 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5108 struct link_params *params,
5109 struct link_vars *vars)
5111 struct bnx2x *bp = params->bp;
5114 /* Program duplex, disable autoneg and sgmii*/
5115 CL22_RD_OVER_CL45(bp, phy,
5116 MDIO_REG_BANK_COMBO_IEEE0,
5117 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5118 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5119 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5120 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5121 if (phy->req_duplex == DUPLEX_FULL)
5122 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5123 CL22_WR_OVER_CL45(bp, phy,
5124 MDIO_REG_BANK_COMBO_IEEE0,
5125 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5128 * - needed only if the speed is greater than 1G (2.5G or 10G)
5130 CL22_RD_OVER_CL45(bp, phy,
5131 MDIO_REG_BANK_SERDES_DIGITAL,
5132 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5133 /* Clearing the speed value before setting the right speed */
5134 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5136 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5137 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5139 if (!((vars->line_speed == SPEED_1000) ||
5140 (vars->line_speed == SPEED_100) ||
5141 (vars->line_speed == SPEED_10))) {
5143 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5144 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5145 if (vars->line_speed == SPEED_10000)
5147 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5150 CL22_WR_OVER_CL45(bp, phy,
5151 MDIO_REG_BANK_SERDES_DIGITAL,
5152 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5156 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5157 struct link_params *params)
5159 struct bnx2x *bp = params->bp;
5162 /* Set extended capabilities */
5163 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5164 val |= MDIO_OVER_1G_UP1_2_5G;
5165 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5166 val |= MDIO_OVER_1G_UP1_10G;
5167 CL22_WR_OVER_CL45(bp, phy,
5168 MDIO_REG_BANK_OVER_1G,
5169 MDIO_OVER_1G_UP1, val);
5171 CL22_WR_OVER_CL45(bp, phy,
5172 MDIO_REG_BANK_OVER_1G,
5173 MDIO_OVER_1G_UP3, 0x400);
5176 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5177 struct link_params *params,
5180 struct bnx2x *bp = params->bp;
5182 /* For AN, we are always publishing full duplex */
5184 CL22_WR_OVER_CL45(bp, phy,
5185 MDIO_REG_BANK_COMBO_IEEE0,
5186 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5187 CL22_RD_OVER_CL45(bp, phy,
5188 MDIO_REG_BANK_CL73_IEEEB1,
5189 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5190 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5191 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5192 CL22_WR_OVER_CL45(bp, phy,
5193 MDIO_REG_BANK_CL73_IEEEB1,
5194 MDIO_CL73_IEEEB1_AN_ADV1, val);
5197 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5198 struct link_params *params,
5201 struct bnx2x *bp = params->bp;
5204 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5205 /* Enable and restart BAM/CL37 aneg */
5208 CL22_RD_OVER_CL45(bp, phy,
5209 MDIO_REG_BANK_CL73_IEEEB0,
5210 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5213 CL22_WR_OVER_CL45(bp, phy,
5214 MDIO_REG_BANK_CL73_IEEEB0,
5215 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5217 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5218 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5221 CL22_RD_OVER_CL45(bp, phy,
5222 MDIO_REG_BANK_COMBO_IEEE0,
5223 MDIO_COMBO_IEEE0_MII_CONTROL,
5226 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5228 CL22_WR_OVER_CL45(bp, phy,
5229 MDIO_REG_BANK_COMBO_IEEE0,
5230 MDIO_COMBO_IEEE0_MII_CONTROL,
5232 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5233 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5237 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5238 struct link_params *params,
5239 struct link_vars *vars)
5241 struct bnx2x *bp = params->bp;
5244 /* In SGMII mode, the unicore is always slave */
5246 CL22_RD_OVER_CL45(bp, phy,
5247 MDIO_REG_BANK_SERDES_DIGITAL,
5248 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5250 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5251 /* Set sgmii mode (and not fiber) */
5252 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5253 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5254 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5255 CL22_WR_OVER_CL45(bp, phy,
5256 MDIO_REG_BANK_SERDES_DIGITAL,
5257 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5260 /* If forced speed */
5261 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5262 /* Set speed, disable autoneg */
5265 CL22_RD_OVER_CL45(bp, phy,
5266 MDIO_REG_BANK_COMBO_IEEE0,
5267 MDIO_COMBO_IEEE0_MII_CONTROL,
5269 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5270 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5271 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5273 switch (vars->line_speed) {
5276 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5280 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5283 /* There is nothing to set for 10M */
5286 /* Invalid speed for SGMII */
5287 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5292 /* Setting the full duplex */
5293 if (phy->req_duplex == DUPLEX_FULL)
5295 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5296 CL22_WR_OVER_CL45(bp, phy,
5297 MDIO_REG_BANK_COMBO_IEEE0,
5298 MDIO_COMBO_IEEE0_MII_CONTROL,
5301 } else { /* AN mode */
5302 /* Enable and restart AN */
5303 bnx2x_restart_autoneg(phy, params, 0);
5309 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5310 struct link_params *params)
5312 struct bnx2x *bp = params->bp;
5313 u16 pd_10g, status2_1000x;
5314 if (phy->req_line_speed != SPEED_AUTO_NEG)
5316 CL22_RD_OVER_CL45(bp, phy,
5317 MDIO_REG_BANK_SERDES_DIGITAL,
5318 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5320 CL22_RD_OVER_CL45(bp, phy,
5321 MDIO_REG_BANK_SERDES_DIGITAL,
5322 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5324 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5325 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5330 CL22_RD_OVER_CL45(bp, phy,
5331 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5332 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5335 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5336 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5343 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5344 struct link_params *params,
5345 struct link_vars *vars,
5348 u16 ld_pause; /* local driver */
5349 u16 lp_pause; /* link partner */
5351 struct bnx2x *bp = params->bp;
5353 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5354 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5355 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5356 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5358 CL22_RD_OVER_CL45(bp, phy,
5359 MDIO_REG_BANK_CL73_IEEEB1,
5360 MDIO_CL73_IEEEB1_AN_ADV1,
5362 CL22_RD_OVER_CL45(bp, phy,
5363 MDIO_REG_BANK_CL73_IEEEB1,
5364 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5366 pause_result = (ld_pause &
5367 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5368 pause_result |= (lp_pause &
5369 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5370 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5372 CL22_RD_OVER_CL45(bp, phy,
5373 MDIO_REG_BANK_COMBO_IEEE0,
5374 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5376 CL22_RD_OVER_CL45(bp, phy,
5377 MDIO_REG_BANK_COMBO_IEEE0,
5378 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5380 pause_result = (ld_pause &
5381 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5382 pause_result |= (lp_pause &
5383 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5384 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5386 bnx2x_pause_resolve(vars, pause_result);
5390 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5391 struct link_params *params,
5392 struct link_vars *vars,
5395 struct bnx2x *bp = params->bp;
5396 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5398 /* Resolve from gp_status in case of AN complete and not sgmii */
5399 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5400 /* Update the advertised flow-controled of LD/LP in AN */
5401 if (phy->req_line_speed == SPEED_AUTO_NEG)
5402 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5403 /* But set the flow-control result as the requested one */
5404 vars->flow_ctrl = phy->req_flow_ctrl;
5405 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5406 vars->flow_ctrl = params->req_fc_auto_adv;
5407 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5408 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5409 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5410 vars->flow_ctrl = params->req_fc_auto_adv;
5413 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5415 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5418 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5419 struct link_params *params)
5421 struct bnx2x *bp = params->bp;
5422 u16 rx_status, ustat_val, cl37_fsm_received;
5423 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5424 /* Step 1: Make sure signal is detected */
5425 CL22_RD_OVER_CL45(bp, phy,
5429 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5430 (MDIO_RX0_RX_STATUS_SIGDET)) {
5431 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5432 "rx_status(0x80b0) = 0x%x\n", rx_status);
5433 CL22_WR_OVER_CL45(bp, phy,
5434 MDIO_REG_BANK_CL73_IEEEB0,
5435 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5436 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5439 /* Step 2: Check CL73 state machine */
5440 CL22_RD_OVER_CL45(bp, phy,
5441 MDIO_REG_BANK_CL73_USERB0,
5442 MDIO_CL73_USERB0_CL73_USTAT1,
5445 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5446 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5447 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5448 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5449 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5450 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5453 /* Step 3: Check CL37 Message Pages received to indicate LP
5454 * supports only CL37
5456 CL22_RD_OVER_CL45(bp, phy,
5457 MDIO_REG_BANK_REMOTE_PHY,
5458 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5459 &cl37_fsm_received);
5460 if ((cl37_fsm_received &
5461 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5462 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5463 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5464 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5465 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5466 "misc_rx_status(0x8330) = 0x%x\n",
5470 /* The combined cl37/cl73 fsm state information indicating that
5471 * we are connected to a device which does not support cl73, but
5472 * does support cl37 BAM. In this case we disable cl73 and
5473 * restart cl37 auto-neg
5477 CL22_WR_OVER_CL45(bp, phy,
5478 MDIO_REG_BANK_CL73_IEEEB0,
5479 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5481 /* Restart CL37 autoneg */
5482 bnx2x_restart_autoneg(phy, params, 0);
5483 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5486 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5487 struct link_params *params,
5488 struct link_vars *vars,
5491 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5492 vars->link_status |=
5493 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5495 if (bnx2x_direct_parallel_detect_used(phy, params))
5496 vars->link_status |=
5497 LINK_STATUS_PARALLEL_DETECTION_USED;
5499 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5500 struct link_params *params,
5501 struct link_vars *vars,
5506 struct bnx2x *bp = params->bp;
5507 if (phy->req_line_speed == SPEED_AUTO_NEG)
5508 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5510 DP(NETIF_MSG_LINK, "phy link up\n");
5512 vars->phy_link_up = 1;
5513 vars->link_status |= LINK_STATUS_LINK_UP;
5515 switch (speed_mask) {
5517 vars->line_speed = SPEED_10;
5518 if (is_duplex == DUPLEX_FULL)
5519 vars->link_status |= LINK_10TFD;
5521 vars->link_status |= LINK_10THD;
5524 case GP_STATUS_100M:
5525 vars->line_speed = SPEED_100;
5526 if (is_duplex == DUPLEX_FULL)
5527 vars->link_status |= LINK_100TXFD;
5529 vars->link_status |= LINK_100TXHD;
5533 case GP_STATUS_1G_KX:
5534 vars->line_speed = SPEED_1000;
5535 if (is_duplex == DUPLEX_FULL)
5536 vars->link_status |= LINK_1000TFD;
5538 vars->link_status |= LINK_1000THD;
5541 case GP_STATUS_2_5G:
5542 vars->line_speed = SPEED_2500;
5543 if (is_duplex == DUPLEX_FULL)
5544 vars->link_status |= LINK_2500TFD;
5546 vars->link_status |= LINK_2500THD;
5552 "link speed unsupported gp_status 0x%x\n",
5556 case GP_STATUS_10G_KX4:
5557 case GP_STATUS_10G_HIG:
5558 case GP_STATUS_10G_CX4:
5559 case GP_STATUS_10G_KR:
5560 case GP_STATUS_10G_SFI:
5561 case GP_STATUS_10G_XFI:
5562 vars->line_speed = SPEED_10000;
5563 vars->link_status |= LINK_10GTFD;
5565 case GP_STATUS_20G_DXGXS:
5566 case GP_STATUS_20G_KR2:
5567 vars->line_speed = SPEED_20000;
5568 vars->link_status |= LINK_20GTFD;
5572 "link speed unsupported gp_status 0x%x\n",
5576 } else { /* link_down */
5577 DP(NETIF_MSG_LINK, "phy link down\n");
5579 vars->phy_link_up = 0;
5581 vars->duplex = DUPLEX_FULL;
5582 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5583 vars->mac_type = MAC_TYPE_NONE;
5585 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5586 vars->phy_link_up, vars->line_speed);
5590 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5591 struct link_params *params,
5592 struct link_vars *vars)
5594 struct bnx2x *bp = params->bp;
5596 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5599 /* Read gp_status */
5600 CL22_RD_OVER_CL45(bp, phy,
5601 MDIO_REG_BANK_GP_STATUS,
5602 MDIO_GP_STATUS_TOP_AN_STATUS1,
5604 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5605 duplex = DUPLEX_FULL;
5606 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5608 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5609 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5610 gp_status, link_up, speed_mask);
5611 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5616 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5617 if (SINGLE_MEDIA_DIRECT(params)) {
5618 vars->duplex = duplex;
5619 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5620 if (phy->req_line_speed == SPEED_AUTO_NEG)
5621 bnx2x_xgxs_an_resolve(phy, params, vars,
5624 } else { /* Link_down */
5625 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5626 SINGLE_MEDIA_DIRECT(params)) {
5627 /* Check signal is detected */
5628 bnx2x_check_fallback_to_cl37(phy, params);
5632 /* Read LP advertised speeds*/
5633 if (SINGLE_MEDIA_DIRECT(params) &&
5634 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5637 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5638 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5640 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5641 vars->link_status |=
5642 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5643 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5644 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5645 vars->link_status |=
5646 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5648 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5649 MDIO_OVER_1G_LP_UP1, &val);
5651 if (val & MDIO_OVER_1G_UP1_2_5G)
5652 vars->link_status |=
5653 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5654 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5655 vars->link_status |=
5656 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5659 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5660 vars->duplex, vars->flow_ctrl, vars->link_status);
5664 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5665 struct link_params *params,
5666 struct link_vars *vars)
5668 struct bnx2x *bp = params->bp;
5670 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5672 lane = bnx2x_get_warpcore_lane(phy, params);
5673 /* Read gp_status */
5674 if ((params->loopback_mode) &&
5675 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5676 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5677 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5678 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5679 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5681 } else if ((phy->req_line_speed > SPEED_10000) &&
5682 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5684 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5686 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5688 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5689 temp_link_up, link_up);
5692 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5694 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5695 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5697 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5698 /* Check for either KR, 1G, or AN up. */
5699 link_up = ((gp_status1 >> 8) |
5700 (gp_status1 >> 12) |
5703 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5705 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5706 MDIO_AN_REG_STATUS, &an_link);
5707 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5708 MDIO_AN_REG_STATUS, &an_link);
5709 link_up |= (an_link & (1<<2));
5711 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5713 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5714 /* Check Autoneg complete */
5715 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5716 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5718 if (gp_status4 & ((1<<12)<<lane))
5719 vars->link_status |=
5720 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5722 /* Check parallel detect used */
5723 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5724 MDIO_WC_REG_PAR_DET_10G_STATUS,
5727 vars->link_status |=
5728 LINK_STATUS_PARALLEL_DETECTION_USED;
5730 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5731 vars->duplex = duplex;
5735 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5736 SINGLE_MEDIA_DIRECT(params)) {
5739 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5740 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5742 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5743 vars->link_status |=
5744 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5745 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5746 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5747 vars->link_status |=
5748 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5750 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5751 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5753 if (val & MDIO_OVER_1G_UP1_2_5G)
5754 vars->link_status |=
5755 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5756 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5757 vars->link_status |=
5758 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5764 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5765 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5767 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5768 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5770 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5772 if ((lane & 1) == 0)
5775 link_up = !!link_up;
5777 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5780 /* In case of KR link down, start up the recovering procedure */
5781 if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5782 (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5783 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5785 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5786 vars->duplex, vars->flow_ctrl, vars->link_status);
5789 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5791 struct bnx2x *bp = params->bp;
5792 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5798 CL22_RD_OVER_CL45(bp, phy,
5799 MDIO_REG_BANK_OVER_1G,
5800 MDIO_OVER_1G_LP_UP2, &lp_up2);
5802 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5803 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5804 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5805 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5810 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5811 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5812 CL22_RD_OVER_CL45(bp, phy,
5814 MDIO_TX0_TX_DRIVER, &tx_driver);
5816 /* Replace tx_driver bits [15:12] */
5818 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5819 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5820 tx_driver |= lp_up2;
5821 CL22_WR_OVER_CL45(bp, phy,
5823 MDIO_TX0_TX_DRIVER, tx_driver);
5828 static int bnx2x_emac_program(struct link_params *params,
5829 struct link_vars *vars)
5831 struct bnx2x *bp = params->bp;
5832 u8 port = params->port;
5835 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5836 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5838 (EMAC_MODE_25G_MODE |
5839 EMAC_MODE_PORT_MII_10M |
5840 EMAC_MODE_HALF_DUPLEX));
5841 switch (vars->line_speed) {
5843 mode |= EMAC_MODE_PORT_MII_10M;
5847 mode |= EMAC_MODE_PORT_MII;
5851 mode |= EMAC_MODE_PORT_GMII;
5855 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5859 /* 10G not valid for EMAC */
5860 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5865 if (vars->duplex == DUPLEX_HALF)
5866 mode |= EMAC_MODE_HALF_DUPLEX;
5868 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5871 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5875 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5876 struct link_params *params)
5880 struct bnx2x *bp = params->bp;
5882 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5883 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5884 CL22_WR_OVER_CL45(bp, phy,
5886 MDIO_RX0_RX_EQ_BOOST,
5887 phy->rx_preemphasis[i]);
5890 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5891 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5892 CL22_WR_OVER_CL45(bp, phy,
5895 phy->tx_preemphasis[i]);
5899 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5900 struct link_params *params,
5901 struct link_vars *vars)
5903 struct bnx2x *bp = params->bp;
5904 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5905 (params->loopback_mode == LOOPBACK_XGXS));
5906 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5907 if (SINGLE_MEDIA_DIRECT(params) &&
5908 (params->feature_config_flags &
5909 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5910 bnx2x_set_preemphasis(phy, params);
5912 /* Forced speed requested? */
5913 if (vars->line_speed != SPEED_AUTO_NEG ||
5914 (SINGLE_MEDIA_DIRECT(params) &&
5915 params->loopback_mode == LOOPBACK_EXT)) {
5916 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5918 /* Disable autoneg */
5919 bnx2x_set_autoneg(phy, params, vars, 0);
5921 /* Program speed and duplex */
5922 bnx2x_program_serdes(phy, params, vars);
5924 } else { /* AN_mode */
5925 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5928 bnx2x_set_brcm_cl37_advertisement(phy, params);
5930 /* Program duplex & pause advertisement (for aneg) */
5931 bnx2x_set_ieee_aneg_advertisement(phy, params,
5934 /* Enable autoneg */
5935 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5937 /* Enable and restart AN */
5938 bnx2x_restart_autoneg(phy, params, enable_cl73);
5941 } else { /* SGMII mode */
5942 DP(NETIF_MSG_LINK, "SGMII\n");
5944 bnx2x_initialize_sgmii_process(phy, params, vars);
5948 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5949 struct link_params *params,
5950 struct link_vars *vars)
5953 vars->phy_flags |= PHY_XGXS_FLAG;
5954 if ((phy->req_line_speed &&
5955 ((phy->req_line_speed == SPEED_100) ||
5956 (phy->req_line_speed == SPEED_10))) ||
5957 (!phy->req_line_speed &&
5958 (phy->speed_cap_mask >=
5959 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5960 (phy->speed_cap_mask <
5961 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5962 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5963 vars->phy_flags |= PHY_SGMII_FLAG;
5965 vars->phy_flags &= ~PHY_SGMII_FLAG;
5967 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5968 bnx2x_set_aer_mmd(params, phy);
5969 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5970 bnx2x_set_master_ln(params, phy);
5972 rc = bnx2x_reset_unicore(params, phy, 0);
5973 /* Reset the SerDes and wait for reset bit return low */
5977 bnx2x_set_aer_mmd(params, phy);
5978 /* Setting the masterLn_def again after the reset */
5979 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5980 bnx2x_set_master_ln(params, phy);
5981 bnx2x_set_swap_lanes(params, phy);
5987 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5988 struct bnx2x_phy *phy,
5989 struct link_params *params)
5992 /* Wait for soft reset to get cleared up to 1 sec */
5993 for (cnt = 0; cnt < 1000; cnt++) {
5994 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5995 bnx2x_cl22_read(bp, phy,
5996 MDIO_PMA_REG_CTRL, &ctrl);
5998 bnx2x_cl45_read(bp, phy,
6000 MDIO_PMA_REG_CTRL, &ctrl);
6001 if (!(ctrl & (1<<15)))
6003 usleep_range(1000, 2000);
6007 netdev_err(bp->dev, "Warning: PHY was not initialized,"
6010 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6014 static void bnx2x_link_int_enable(struct link_params *params)
6016 u8 port = params->port;
6018 struct bnx2x *bp = params->bp;
6020 /* Setting the status to report on link up for either XGXS or SerDes */
6021 if (CHIP_IS_E3(bp)) {
6022 mask = NIG_MASK_XGXS0_LINK_STATUS;
6023 if (!(SINGLE_MEDIA_DIRECT(params)))
6024 mask |= NIG_MASK_MI_INT;
6025 } else if (params->switch_cfg == SWITCH_CFG_10G) {
6026 mask = (NIG_MASK_XGXS0_LINK10G |
6027 NIG_MASK_XGXS0_LINK_STATUS);
6028 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6029 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6030 params->phy[INT_PHY].type !=
6031 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6032 mask |= NIG_MASK_MI_INT;
6033 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6036 } else { /* SerDes */
6037 mask = NIG_MASK_SERDES0_LINK_STATUS;
6038 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6039 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6040 params->phy[INT_PHY].type !=
6041 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6042 mask |= NIG_MASK_MI_INT;
6043 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6047 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6050 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6051 (params->switch_cfg == SWITCH_CFG_10G),
6052 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6053 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6054 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6055 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6056 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6057 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6058 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6059 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6062 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6065 u32 latch_status = 0;
6067 /* Disable the MI INT ( external phy int ) by writing 1 to the
6068 * status register. Link down indication is high-active-signal,
6069 * so in this case we need to write the status to clear the XOR
6071 /* Read Latched signals */
6072 latch_status = REG_RD(bp,
6073 NIG_REG_LATCH_STATUS_0 + port*8);
6074 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6075 /* Handle only those with latched-signal=up.*/
6078 NIG_REG_STATUS_INTERRUPT_PORT0
6080 NIG_STATUS_EMAC0_MI_INT);
6083 NIG_REG_STATUS_INTERRUPT_PORT0
6085 NIG_STATUS_EMAC0_MI_INT);
6087 if (latch_status & 1) {
6089 /* For all latched-signal=up : Re-Arm Latch signals */
6090 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6091 (latch_status & 0xfffe) | (latch_status & 1));
6093 /* For all latched-signal=up,Write original_signal to status */
6096 static void bnx2x_link_int_ack(struct link_params *params,
6097 struct link_vars *vars, u8 is_10g_plus)
6099 struct bnx2x *bp = params->bp;
6100 u8 port = params->port;
6102 /* First reset all status we assume only one line will be
6105 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6106 (NIG_STATUS_XGXS0_LINK10G |
6107 NIG_STATUS_XGXS0_LINK_STATUS |
6108 NIG_STATUS_SERDES0_LINK_STATUS));
6109 if (vars->phy_link_up) {
6110 if (USES_WARPCORE(bp))
6111 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6114 mask = NIG_STATUS_XGXS0_LINK10G;
6115 else if (params->switch_cfg == SWITCH_CFG_10G) {
6116 /* Disable the link interrupt by writing 1 to
6117 * the relevant lane in the status register
6120 ((params->lane_config &
6121 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6122 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6123 mask = ((1 << ser_lane) <<
6124 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6126 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6128 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6131 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6136 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6139 u32 mask = 0xf0000000;
6142 u8 remove_leading_zeros = 1;
6144 /* Need more than 10chars for this format */
6152 digit = ((num & mask) >> shift);
6153 if (digit == 0 && remove_leading_zeros) {
6156 } else if (digit < 0xa)
6157 *str_ptr = digit + '0';
6159 *str_ptr = digit - 0xa + 'a';
6160 remove_leading_zeros = 0;
6168 remove_leading_zeros = 1;
6175 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6182 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6188 u8 *ver_p = version;
6189 u16 remain_len = len;
6190 if (version == NULL || params == NULL)
6194 /* Extract first external phy*/
6196 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6198 if (params->phy[EXT_PHY1].format_fw_ver) {
6199 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6202 ver_p += (len - remain_len);
6204 if ((params->num_phys == MAX_PHYS) &&
6205 (params->phy[EXT_PHY2].ver_addr != 0)) {
6206 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6207 if (params->phy[EXT_PHY2].format_fw_ver) {
6211 status |= params->phy[EXT_PHY2].format_fw_ver(
6215 ver_p = version + (len - remain_len);
6222 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6223 struct link_params *params)
6225 u8 port = params->port;
6226 struct bnx2x *bp = params->bp;
6228 if (phy->req_line_speed != SPEED_1000) {
6231 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6233 if (!CHIP_IS_E3(bp)) {
6234 /* Change the uni_phy_addr in the nig */
6235 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6238 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6242 bnx2x_cl45_write(bp, phy,
6244 (MDIO_REG_BANK_AER_BLOCK +
6245 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6248 bnx2x_cl45_write(bp, phy,
6250 (MDIO_REG_BANK_CL73_IEEEB0 +
6251 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6254 /* Set aer mmd back */
6255 bnx2x_set_aer_mmd(params, phy);
6257 if (!CHIP_IS_E3(bp)) {
6259 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6264 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6265 bnx2x_cl45_read(bp, phy, 5,
6266 (MDIO_REG_BANK_COMBO_IEEE0 +
6267 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6269 bnx2x_cl45_write(bp, phy, 5,
6270 (MDIO_REG_BANK_COMBO_IEEE0 +
6271 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6273 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6277 int bnx2x_set_led(struct link_params *params,
6278 struct link_vars *vars, u8 mode, u32 speed)
6280 u8 port = params->port;
6281 u16 hw_led_mode = params->hw_led_mode;
6285 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6286 struct bnx2x *bp = params->bp;
6287 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6288 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6289 speed, hw_led_mode);
6291 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6292 if (params->phy[phy_idx].set_link_led) {
6293 params->phy[phy_idx].set_link_led(
6294 ¶ms->phy[phy_idx], params, mode);
6299 case LED_MODE_FRONT_PANEL_OFF:
6301 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6302 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6303 SHARED_HW_CFG_LED_MAC1);
6305 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6306 if (params->phy[EXT_PHY1].type ==
6307 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6308 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6309 EMAC_LED_100MB_OVERRIDE |
6310 EMAC_LED_10MB_OVERRIDE);
6312 tmp |= EMAC_LED_OVERRIDE;
6314 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6318 /* For all other phys, OPER mode is same as ON, so in case
6319 * link is down, do nothing
6324 if (((params->phy[EXT_PHY1].type ==
6325 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6326 (params->phy[EXT_PHY1].type ==
6327 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6328 CHIP_IS_E2(bp) && params->num_phys == 2) {
6329 /* This is a work-around for E2+8727 Configurations */
6330 if (mode == LED_MODE_ON ||
6331 speed == SPEED_10000){
6332 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6333 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6335 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6336 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6337 (tmp | EMAC_LED_OVERRIDE));
6338 /* Return here without enabling traffic
6339 * LED blink and setting rate in ON mode.
6340 * In oper mode, enabling LED blink
6341 * and setting rate is needed.
6343 if (mode == LED_MODE_ON)
6346 } else if (SINGLE_MEDIA_DIRECT(params)) {
6347 /* This is a work-around for HW issue found when link
6350 if ((!CHIP_IS_E3(bp)) ||
6352 mode == LED_MODE_ON))
6353 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6355 if (CHIP_IS_E1x(bp) ||
6357 (mode == LED_MODE_ON))
6358 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6360 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6362 } else if ((params->phy[EXT_PHY1].type ==
6363 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6364 (mode == LED_MODE_ON)) {
6365 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6366 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6367 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6368 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6369 /* Break here; otherwise, it'll disable the
6370 * intended override.
6374 u32 nig_led_mode = ((params->hw_led_mode <<
6375 SHARED_HW_CFG_LED_MODE_SHIFT) ==
6376 SHARED_HW_CFG_LED_EXTPHY2) ?
6377 (SHARED_HW_CFG_LED_PHY1 >>
6378 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6379 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6383 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6384 /* Set blinking rate to ~15.9Hz */
6386 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6387 LED_BLINK_RATE_VAL_E3);
6389 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6390 LED_BLINK_RATE_VAL_E1X_E2);
6391 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6393 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6394 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6395 (tmp & (~EMAC_LED_OVERRIDE)));
6397 if (CHIP_IS_E1(bp) &&
6398 ((speed == SPEED_2500) ||
6399 (speed == SPEED_1000) ||
6400 (speed == SPEED_100) ||
6401 (speed == SPEED_10))) {
6402 /* For speeds less than 10G LED scheme is different */
6403 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6405 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6407 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6414 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6422 /* This function comes to reflect the actual link state read DIRECTLY from the
6425 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6428 struct bnx2x *bp = params->bp;
6429 u16 gp_status = 0, phy_index = 0;
6430 u8 ext_phy_link_up = 0, serdes_phy_type;
6431 struct link_vars temp_vars;
6432 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6434 if (CHIP_IS_E3(bp)) {
6436 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6438 /* Check 20G link */
6439 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6441 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6445 /* Check 10G link and below*/
6446 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6447 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6448 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6450 gp_status = ((gp_status >> 8) & 0xf) |
6451 ((gp_status >> 12) & 0xf);
6452 link_up = gp_status & (1 << lane);
6457 CL22_RD_OVER_CL45(bp, int_phy,
6458 MDIO_REG_BANK_GP_STATUS,
6459 MDIO_GP_STATUS_TOP_AN_STATUS1,
6461 /* Link is up only if both local phy and external phy are up */
6462 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6465 /* In XGXS loopback mode, do not check external PHY */
6466 if (params->loopback_mode == LOOPBACK_XGXS)
6469 switch (params->num_phys) {
6471 /* No external PHY */
6474 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6475 ¶ms->phy[EXT_PHY1],
6476 params, &temp_vars);
6478 case 3: /* Dual Media */
6479 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6481 serdes_phy_type = ((params->phy[phy_index].media_type ==
6482 ETH_PHY_SFPP_10G_FIBER) ||
6483 (params->phy[phy_index].media_type ==
6484 ETH_PHY_SFP_1G_FIBER) ||
6485 (params->phy[phy_index].media_type ==
6486 ETH_PHY_XFP_FIBER) ||
6487 (params->phy[phy_index].media_type ==
6488 ETH_PHY_DA_TWINAX));
6490 if (is_serdes != serdes_phy_type)
6492 if (params->phy[phy_index].read_status) {
6494 params->phy[phy_index].read_status(
6495 ¶ms->phy[phy_index],
6496 params, &temp_vars);
6501 if (ext_phy_link_up)
6506 static int bnx2x_link_initialize(struct link_params *params,
6507 struct link_vars *vars)
6510 u8 phy_index, non_ext_phy;
6511 struct bnx2x *bp = params->bp;
6512 /* In case of external phy existence, the line speed would be the
6513 * line speed linked up by the external phy. In case it is direct
6514 * only, then the line_speed during initialization will be
6515 * equal to the req_line_speed
6517 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6519 /* Initialize the internal phy in case this is a direct board
6520 * (no external phys), or this board has external phy which requires
6523 if (!USES_WARPCORE(bp))
6524 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6525 /* init ext phy and enable link state int */
6526 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6527 (params->loopback_mode == LOOPBACK_XGXS));
6530 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6531 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6532 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6533 if (vars->line_speed == SPEED_AUTO_NEG &&
6536 bnx2x_set_parallel_detection(phy, params);
6537 if (params->phy[INT_PHY].config_init)
6538 params->phy[INT_PHY].config_init(phy, params, vars);
6541 /* Re-read this value in case it was changed inside config_init due to
6542 * limitations of optic module
6544 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6546 /* Init external phy*/
6548 if (params->phy[INT_PHY].supported &
6550 vars->link_status |= LINK_STATUS_SERDES_LINK;
6552 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6554 /* No need to initialize second phy in case of first
6555 * phy only selection. In case of second phy, we do
6556 * need to initialize the first phy, since they are
6559 if (params->phy[phy_index].supported &
6561 vars->link_status |= LINK_STATUS_SERDES_LINK;
6563 if (phy_index == EXT_PHY2 &&
6564 (bnx2x_phy_selection(params) ==
6565 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6567 "Not initializing second phy\n");
6570 params->phy[phy_index].config_init(
6571 ¶ms->phy[phy_index],
6575 /* Reset the interrupt indication after phy was initialized */
6576 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6578 (NIG_STATUS_XGXS0_LINK10G |
6579 NIG_STATUS_XGXS0_LINK_STATUS |
6580 NIG_STATUS_SERDES0_LINK_STATUS |
6585 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6586 struct link_params *params)
6588 /* Reset the SerDes/XGXS */
6589 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6590 (0x1ff << (params->port*16)));
6593 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6594 struct link_params *params)
6596 struct bnx2x *bp = params->bp;
6600 gpio_port = BP_PATH(bp);
6602 gpio_port = params->port;
6603 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6604 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6606 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6607 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6609 DP(NETIF_MSG_LINK, "reset external PHY\n");
6612 static int bnx2x_update_link_down(struct link_params *params,
6613 struct link_vars *vars)
6615 struct bnx2x *bp = params->bp;
6616 u8 port = params->port;
6618 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6619 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6620 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6621 /* Indicate no mac active */
6622 vars->mac_type = MAC_TYPE_NONE;
6624 /* Update shared memory */
6625 vars->link_status &= ~LINK_UPDATE_MASK;
6626 vars->line_speed = 0;
6627 bnx2x_update_mng(params, vars->link_status);
6629 /* Activate nig drain */
6630 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6633 if (!CHIP_IS_E3(bp))
6634 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6636 usleep_range(10000, 20000);
6637 /* Reset BigMac/Xmac */
6638 if (CHIP_IS_E1x(bp) ||
6640 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6642 if (CHIP_IS_E3(bp)) {
6643 /* Prevent LPI Generation by chip */
6644 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6646 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6648 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6649 SHMEM_EEE_ACTIVE_BIT);
6651 bnx2x_update_mng_eee(params, vars->eee_status);
6652 bnx2x_set_xmac_rxtx(params, 0);
6653 bnx2x_set_umac_rxtx(params, 0);
6659 static int bnx2x_update_link_up(struct link_params *params,
6660 struct link_vars *vars,
6663 struct bnx2x *bp = params->bp;
6664 u8 phy_idx, port = params->port;
6667 vars->link_status |= (LINK_STATUS_LINK_UP |
6668 LINK_STATUS_PHYSICAL_LINK_FLAG);
6669 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6671 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6672 vars->link_status |=
6673 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6675 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6676 vars->link_status |=
6677 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6678 if (USES_WARPCORE(bp)) {
6680 if (bnx2x_xmac_enable(params, vars, 0) ==
6682 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6684 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6685 vars->link_status &= ~LINK_STATUS_LINK_UP;
6688 bnx2x_umac_enable(params, vars, 0);
6689 bnx2x_set_led(params, vars,
6690 LED_MODE_OPER, vars->line_speed);
6692 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6693 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6694 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6695 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6696 (params->port << 2), 1);
6697 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6698 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6699 (params->port << 2), 0xfc20);
6702 if ((CHIP_IS_E1x(bp) ||
6705 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6707 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6709 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6710 vars->link_status &= ~LINK_STATUS_LINK_UP;
6713 bnx2x_set_led(params, vars,
6714 LED_MODE_OPER, SPEED_10000);
6716 rc = bnx2x_emac_program(params, vars);
6717 bnx2x_emac_enable(params, vars, 0);
6720 if ((vars->link_status &
6721 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6722 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6723 SINGLE_MEDIA_DIRECT(params))
6724 bnx2x_set_gmii_tx_driver(params);
6729 if (CHIP_IS_E1x(bp))
6730 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6734 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6736 /* Update shared memory */
6737 bnx2x_update_mng(params, vars->link_status);
6738 bnx2x_update_mng_eee(params, vars->eee_status);
6739 /* Check remote fault */
6740 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6741 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6742 bnx2x_check_half_open_conn(params, vars, 0);
6749 /* The bnx2x_link_update function should be called upon link
6751 * Link is considered up as follows:
6752 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6754 * - SINGLE_MEDIA - The link between the 577xx and the external
6755 * phy (XGXS) need to up as well as the external link of the
6757 * - DUAL_MEDIA - The link between the 577xx and the first
6758 * external phy needs to be up, and at least one of the 2
6759 * external phy link must be up.
6761 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6763 struct bnx2x *bp = params->bp;
6764 struct link_vars phy_vars[MAX_PHYS];
6765 u8 port = params->port;
6766 u8 link_10g_plus, phy_index;
6767 u8 ext_phy_link_up = 0, cur_link_up;
6770 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6771 u8 active_external_phy = INT_PHY;
6772 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6773 vars->link_status &= ~LINK_UPDATE_MASK;
6774 for (phy_index = INT_PHY; phy_index < params->num_phys;
6776 phy_vars[phy_index].flow_ctrl = 0;
6777 phy_vars[phy_index].link_status = 0;
6778 phy_vars[phy_index].line_speed = 0;
6779 phy_vars[phy_index].duplex = DUPLEX_FULL;
6780 phy_vars[phy_index].phy_link_up = 0;
6781 phy_vars[phy_index].link_up = 0;
6782 phy_vars[phy_index].fault_detected = 0;
6783 /* different consideration, since vars holds inner state */
6784 phy_vars[phy_index].eee_status = vars->eee_status;
6787 if (USES_WARPCORE(bp))
6788 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6790 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6791 port, (vars->phy_flags & PHY_XGXS_FLAG),
6792 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6794 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6796 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6797 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6799 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6801 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6802 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6803 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6806 if (!CHIP_IS_E3(bp))
6807 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6810 * Check external link change only for external phys, and apply
6811 * priority selection between them in case the link on both phys
6812 * is up. Note that instead of the common vars, a temporary
6813 * vars argument is used since each phy may have different link/
6814 * speed/duplex result
6816 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6818 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6819 if (!phy->read_status)
6821 /* Read link status and params of this ext phy */
6822 cur_link_up = phy->read_status(phy, params,
6823 &phy_vars[phy_index]);
6825 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6828 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6833 if (!ext_phy_link_up) {
6834 ext_phy_link_up = 1;
6835 active_external_phy = phy_index;
6837 switch (bnx2x_phy_selection(params)) {
6838 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6839 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6840 /* In this option, the first PHY makes sure to pass the
6841 * traffic through itself only.
6842 * Its not clear how to reset the link on the second phy
6844 active_external_phy = EXT_PHY1;
6846 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6847 /* In this option, the first PHY makes sure to pass the
6848 * traffic through the second PHY.
6850 active_external_phy = EXT_PHY2;
6853 /* Link indication on both PHYs with the following cases
6855 * - FIRST_PHY means that second phy wasn't initialized,
6856 * hence its link is expected to be down
6857 * - SECOND_PHY means that first phy should not be able
6858 * to link up by itself (using configuration)
6859 * - DEFAULT should be overriden during initialiazation
6861 DP(NETIF_MSG_LINK, "Invalid link indication"
6862 "mpc=0x%x. DISABLING LINK !!!\n",
6863 params->multi_phy_config);
6864 ext_phy_link_up = 0;
6869 prev_line_speed = vars->line_speed;
6871 * Read the status of the internal phy. In case of
6872 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6873 * otherwise this is the link between the 577xx and the first
6876 if (params->phy[INT_PHY].read_status)
6877 params->phy[INT_PHY].read_status(
6878 ¶ms->phy[INT_PHY],
6880 /* The INT_PHY flow control reside in the vars. This include the
6881 * case where the speed or flow control are not set to AUTO.
6882 * Otherwise, the active external phy flow control result is set
6883 * to the vars. The ext_phy_line_speed is needed to check if the
6884 * speed is different between the internal phy and external phy.
6885 * This case may be result of intermediate link speed change.
6887 if (active_external_phy > INT_PHY) {
6888 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6889 /* Link speed is taken from the XGXS. AN and FC result from
6892 vars->link_status |= phy_vars[active_external_phy].link_status;
6894 /* if active_external_phy is first PHY and link is up - disable
6895 * disable TX on second external PHY
6897 if (active_external_phy == EXT_PHY1) {
6898 if (params->phy[EXT_PHY2].phy_specific_func) {
6900 "Disabling TX on EXT_PHY2\n");
6901 params->phy[EXT_PHY2].phy_specific_func(
6902 ¶ms->phy[EXT_PHY2],
6903 params, DISABLE_TX);
6907 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6908 vars->duplex = phy_vars[active_external_phy].duplex;
6909 if (params->phy[active_external_phy].supported &
6911 vars->link_status |= LINK_STATUS_SERDES_LINK;
6913 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6915 vars->eee_status = phy_vars[active_external_phy].eee_status;
6917 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6918 active_external_phy);
6921 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6923 if (params->phy[phy_index].flags &
6924 FLAGS_REARM_LATCH_SIGNAL) {
6925 bnx2x_rearm_latch_signal(bp, port,
6927 active_external_phy);
6931 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6932 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6933 vars->link_status, ext_phy_line_speed);
6934 /* Upon link speed change set the NIG into drain mode. Comes to
6935 * deals with possible FIFO glitch due to clk change when speed
6936 * is decreased without link down indicator
6939 if (vars->phy_link_up) {
6940 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6941 (ext_phy_line_speed != vars->line_speed)) {
6942 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6943 " different than the external"
6944 " link speed %d\n", vars->line_speed,
6945 ext_phy_line_speed);
6946 vars->phy_link_up = 0;
6947 } else if (prev_line_speed != vars->line_speed) {
6948 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6950 usleep_range(1000, 2000);
6954 /* Anything 10 and over uses the bmac */
6955 link_10g_plus = (vars->line_speed >= SPEED_10000);
6957 bnx2x_link_int_ack(params, vars, link_10g_plus);
6959 /* In case external phy link is up, and internal link is down
6960 * (not initialized yet probably after link initialization, it
6961 * needs to be initialized.
6962 * Note that after link down-up as result of cable plug, the xgxs
6963 * link would probably become up again without the need
6966 if (!(SINGLE_MEDIA_DIRECT(params))) {
6967 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6968 " init_preceding = %d\n", ext_phy_link_up,
6970 params->phy[EXT_PHY1].flags &
6971 FLAGS_INIT_XGXS_FIRST);
6972 if (!(params->phy[EXT_PHY1].flags &
6973 FLAGS_INIT_XGXS_FIRST)
6974 && ext_phy_link_up && !vars->phy_link_up) {
6975 vars->line_speed = ext_phy_line_speed;
6976 if (vars->line_speed < SPEED_1000)
6977 vars->phy_flags |= PHY_SGMII_FLAG;
6979 vars->phy_flags &= ~PHY_SGMII_FLAG;
6981 if (params->phy[INT_PHY].config_init)
6982 params->phy[INT_PHY].config_init(
6983 ¶ms->phy[INT_PHY], params,
6987 /* Link is up only if both local phy and external phy (in case of
6988 * non-direct board) are up and no fault detected on active PHY.
6990 vars->link_up = (vars->phy_link_up &&
6992 SINGLE_MEDIA_DIRECT(params)) &&
6993 (phy_vars[active_external_phy].fault_detected == 0));
6995 /* Update the PFC configuration in case it was changed */
6996 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6997 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6999 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7002 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7004 rc = bnx2x_update_link_down(params, vars);
7006 /* Update MCP link status was changed */
7007 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7008 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7013 /*****************************************************************************/
7014 /* External Phy section */
7015 /*****************************************************************************/
7016 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7018 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7019 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7020 usleep_range(1000, 2000);
7021 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7022 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7025 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7026 u32 spirom_ver, u32 ver_addr)
7028 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7029 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7032 REG_WR(bp, ver_addr, spirom_ver);
7035 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7036 struct bnx2x_phy *phy,
7039 u16 fw_ver1, fw_ver2;
7041 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7042 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7043 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7044 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7045 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7049 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7050 struct bnx2x_phy *phy,
7051 struct link_vars *vars)
7054 bnx2x_cl45_read(bp, phy,
7056 MDIO_AN_REG_STATUS, &val);
7057 bnx2x_cl45_read(bp, phy,
7059 MDIO_AN_REG_STATUS, &val);
7061 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7062 if ((val & (1<<0)) == 0)
7063 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7066 /******************************************************************/
7067 /* common BCM8073/BCM8727 PHY SECTION */
7068 /******************************************************************/
7069 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7070 struct link_params *params,
7071 struct link_vars *vars)
7073 struct bnx2x *bp = params->bp;
7074 if (phy->req_line_speed == SPEED_10 ||
7075 phy->req_line_speed == SPEED_100) {
7076 vars->flow_ctrl = phy->req_flow_ctrl;
7080 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7081 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7083 u16 ld_pause; /* local */
7084 u16 lp_pause; /* link partner */
7085 bnx2x_cl45_read(bp, phy,
7087 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7089 bnx2x_cl45_read(bp, phy,
7091 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7092 pause_result = (ld_pause &
7093 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7094 pause_result |= (lp_pause &
7095 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7097 bnx2x_pause_resolve(vars, pause_result);
7098 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7102 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7103 struct bnx2x_phy *phy,
7107 u16 fw_ver1, fw_msgout;
7110 /* Boot port from external ROM */
7112 bnx2x_cl45_write(bp, phy,
7114 MDIO_PMA_REG_GEN_CTRL,
7117 /* Ucode reboot and rst */
7118 bnx2x_cl45_write(bp, phy,
7120 MDIO_PMA_REG_GEN_CTRL,
7123 bnx2x_cl45_write(bp, phy,
7125 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7127 /* Reset internal microprocessor */
7128 bnx2x_cl45_write(bp, phy,
7130 MDIO_PMA_REG_GEN_CTRL,
7131 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7133 /* Release srst bit */
7134 bnx2x_cl45_write(bp, phy,
7136 MDIO_PMA_REG_GEN_CTRL,
7137 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7139 /* Delay 100ms per the PHY specifications */
7142 /* 8073 sometimes taking longer to download */
7147 "bnx2x_8073_8727_external_rom_boot port %x:"
7148 "Download failed. fw version = 0x%x\n",
7154 bnx2x_cl45_read(bp, phy,
7156 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7157 bnx2x_cl45_read(bp, phy,
7159 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7161 usleep_range(1000, 2000);
7162 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7163 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7164 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7166 /* Clear ser_boot_ctl bit */
7167 bnx2x_cl45_write(bp, phy,
7169 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7170 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7173 "bnx2x_8073_8727_external_rom_boot port %x:"
7174 "Download complete. fw version = 0x%x\n",
7180 /******************************************************************/
7181 /* BCM8073 PHY SECTION */
7182 /******************************************************************/
7183 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7185 /* This is only required for 8073A1, version 102 only */
7188 /* Read 8073 HW revision*/
7189 bnx2x_cl45_read(bp, phy,
7191 MDIO_PMA_REG_8073_CHIP_REV, &val);
7194 /* No need to workaround in 8073 A1 */
7198 bnx2x_cl45_read(bp, phy,
7200 MDIO_PMA_REG_ROM_VER2, &val);
7202 /* SNR should be applied only for version 0x102 */
7209 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7211 u16 val, cnt, cnt1 ;
7213 bnx2x_cl45_read(bp, phy,
7215 MDIO_PMA_REG_8073_CHIP_REV, &val);
7218 /* No need to workaround in 8073 A1 */
7221 /* XAUI workaround in 8073 A0: */
7223 /* After loading the boot ROM and restarting Autoneg, poll
7227 for (cnt = 0; cnt < 1000; cnt++) {
7228 bnx2x_cl45_read(bp, phy,
7230 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7232 /* If bit [14] = 0 or bit [13] = 0, continue on with
7233 * system initialization (XAUI work-around not required, as
7234 * these bits indicate 2.5G or 1G link up).
7236 if (!(val & (1<<14)) || !(val & (1<<13))) {
7237 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7239 } else if (!(val & (1<<15))) {
7240 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7241 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7242 * MSB (bit15) goes to 1 (indicating that the XAUI
7243 * workaround has completed), then continue on with
7244 * system initialization.
7246 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7247 bnx2x_cl45_read(bp, phy,
7249 MDIO_PMA_REG_8073_XAUI_WA, &val);
7250 if (val & (1<<15)) {
7252 "XAUI workaround has completed\n");
7255 usleep_range(3000, 6000);
7259 usleep_range(3000, 6000);
7261 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7265 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7267 /* Force KR or KX */
7268 bnx2x_cl45_write(bp, phy,
7269 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7270 bnx2x_cl45_write(bp, phy,
7271 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7272 bnx2x_cl45_write(bp, phy,
7273 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7274 bnx2x_cl45_write(bp, phy,
7275 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7278 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7279 struct bnx2x_phy *phy,
7280 struct link_vars *vars)
7283 struct bnx2x *bp = params->bp;
7284 bnx2x_cl45_read(bp, phy,
7285 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7287 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7288 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7289 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7290 if ((vars->ieee_fc &
7291 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7292 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7293 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7295 if ((vars->ieee_fc &
7296 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7297 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7298 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7300 if ((vars->ieee_fc &
7301 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7302 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7303 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7306 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7308 bnx2x_cl45_write(bp, phy,
7309 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7313 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7314 struct link_params *params,
7317 struct bnx2x *bp = params->bp;
7321 bnx2x_cl45_write(bp, phy,
7322 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7323 bnx2x_cl45_write(bp, phy,
7324 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7329 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7330 struct link_params *params,
7331 struct link_vars *vars)
7333 struct bnx2x *bp = params->bp;
7336 DP(NETIF_MSG_LINK, "Init 8073\n");
7339 gpio_port = BP_PATH(bp);
7341 gpio_port = params->port;
7342 /* Restore normal power mode*/
7343 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7344 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7346 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7347 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7349 bnx2x_8073_specific_func(phy, params, PHY_INIT);
7350 bnx2x_8073_set_pause_cl37(params, phy, vars);
7352 bnx2x_cl45_read(bp, phy,
7353 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7355 bnx2x_cl45_read(bp, phy,
7356 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7358 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7360 /* Swap polarity if required - Must be done only in non-1G mode */
7361 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7362 /* Configure the 8073 to swap _P and _N of the KR lines */
7363 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7364 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7365 bnx2x_cl45_read(bp, phy,
7367 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7368 bnx2x_cl45_write(bp, phy,
7370 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7375 /* Enable CL37 BAM */
7376 if (REG_RD(bp, params->shmem_base +
7377 offsetof(struct shmem_region, dev_info.
7378 port_hw_config[params->port].default_cfg)) &
7379 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7381 bnx2x_cl45_read(bp, phy,
7383 MDIO_AN_REG_8073_BAM, &val);
7384 bnx2x_cl45_write(bp, phy,
7386 MDIO_AN_REG_8073_BAM, val | 1);
7387 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7389 if (params->loopback_mode == LOOPBACK_EXT) {
7390 bnx2x_807x_force_10G(bp, phy);
7391 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7394 bnx2x_cl45_write(bp, phy,
7395 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7397 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7398 if (phy->req_line_speed == SPEED_10000) {
7400 } else if (phy->req_line_speed == SPEED_2500) {
7402 /* Note that 2.5G works only when used with 1G
7409 if (phy->speed_cap_mask &
7410 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7413 /* Note that 2.5G works only when used with 1G advertisement */
7414 if (phy->speed_cap_mask &
7415 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7416 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7418 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7421 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7422 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7424 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7425 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7426 (phy->req_line_speed == SPEED_2500)) {
7428 /* Allow 2.5G for A1 and above */
7429 bnx2x_cl45_read(bp, phy,
7430 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7432 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7438 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7442 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7443 /* Add support for CL37 (passive mode) II */
7445 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7446 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7447 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7450 /* Add support for CL37 (passive mode) III */
7451 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7453 /* The SNR will improve about 2db by changing BW and FEE main
7454 * tap. Rest commands are executed after link is up
7455 * Change FFE main cursor to 5 in EDC register
7457 if (bnx2x_8073_is_snr_needed(bp, phy))
7458 bnx2x_cl45_write(bp, phy,
7459 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7462 /* Enable FEC (Forware Error Correction) Request in the AN */
7463 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7465 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7467 bnx2x_ext_phy_set_pause(params, phy, vars);
7469 /* Restart autoneg */
7471 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7472 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7473 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7477 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7478 struct link_params *params,
7479 struct link_vars *vars)
7481 struct bnx2x *bp = params->bp;
7484 u16 link_status = 0;
7485 u16 an1000_status = 0;
7487 bnx2x_cl45_read(bp, phy,
7488 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7490 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7492 /* Clear the interrupt LASI status register */
7493 bnx2x_cl45_read(bp, phy,
7494 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7495 bnx2x_cl45_read(bp, phy,
7496 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7497 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7499 bnx2x_cl45_read(bp, phy,
7500 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7502 /* Check the LASI */
7503 bnx2x_cl45_read(bp, phy,
7504 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7506 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7508 /* Check the link status */
7509 bnx2x_cl45_read(bp, phy,
7510 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7511 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7513 bnx2x_cl45_read(bp, phy,
7514 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7515 bnx2x_cl45_read(bp, phy,
7516 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7517 link_up = ((val1 & 4) == 4);
7518 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7521 ((phy->req_line_speed != SPEED_10000))) {
7522 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7525 bnx2x_cl45_read(bp, phy,
7526 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7527 bnx2x_cl45_read(bp, phy,
7528 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7530 /* Check the link status on 1.1.2 */
7531 bnx2x_cl45_read(bp, phy,
7532 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7533 bnx2x_cl45_read(bp, phy,
7534 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7535 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7536 "an_link_status=0x%x\n", val2, val1, an1000_status);
7538 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7539 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7540 /* The SNR will improve about 2dbby changing the BW and FEE main
7541 * tap. The 1st write to change FFE main tap is set before
7542 * restart AN. Change PLL Bandwidth in EDC register
7544 bnx2x_cl45_write(bp, phy,
7545 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7548 /* Change CDR Bandwidth in EDC register */
7549 bnx2x_cl45_write(bp, phy,
7550 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7553 bnx2x_cl45_read(bp, phy,
7554 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7557 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7558 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7560 vars->line_speed = SPEED_10000;
7561 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7563 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7565 vars->line_speed = SPEED_2500;
7566 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7568 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7570 vars->line_speed = SPEED_1000;
7571 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7575 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7580 /* Swap polarity if required */
7581 if (params->lane_config &
7582 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7583 /* Configure the 8073 to swap P and N of the KR lines */
7584 bnx2x_cl45_read(bp, phy,
7586 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7587 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7588 * when it`s in 10G mode.
7590 if (vars->line_speed == SPEED_1000) {
7591 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7597 bnx2x_cl45_write(bp, phy,
7599 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7602 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7603 bnx2x_8073_resolve_fc(phy, params, vars);
7604 vars->duplex = DUPLEX_FULL;
7607 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7608 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7609 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7612 vars->link_status |=
7613 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7615 vars->link_status |=
7616 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7622 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7623 struct link_params *params)
7625 struct bnx2x *bp = params->bp;
7628 gpio_port = BP_PATH(bp);
7630 gpio_port = params->port;
7631 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7633 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7634 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7638 /******************************************************************/
7639 /* BCM8705 PHY SECTION */
7640 /******************************************************************/
7641 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7642 struct link_params *params,
7643 struct link_vars *vars)
7645 struct bnx2x *bp = params->bp;
7646 DP(NETIF_MSG_LINK, "init 8705\n");
7647 /* Restore normal power mode*/
7648 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7649 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7651 bnx2x_ext_phy_hw_reset(bp, params->port);
7652 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7653 bnx2x_wait_reset_complete(bp, phy, params);
7655 bnx2x_cl45_write(bp, phy,
7656 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7657 bnx2x_cl45_write(bp, phy,
7658 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7659 bnx2x_cl45_write(bp, phy,
7660 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7661 bnx2x_cl45_write(bp, phy,
7662 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7663 /* BCM8705 doesn't have microcode, hence the 0 */
7664 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7668 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7669 struct link_params *params,
7670 struct link_vars *vars)
7674 struct bnx2x *bp = params->bp;
7675 DP(NETIF_MSG_LINK, "read status 8705\n");
7676 bnx2x_cl45_read(bp, phy,
7677 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7678 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7680 bnx2x_cl45_read(bp, phy,
7681 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7682 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7684 bnx2x_cl45_read(bp, phy,
7685 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7687 bnx2x_cl45_read(bp, phy,
7688 MDIO_PMA_DEVAD, 0xc809, &val1);
7689 bnx2x_cl45_read(bp, phy,
7690 MDIO_PMA_DEVAD, 0xc809, &val1);
7692 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7693 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7695 vars->line_speed = SPEED_10000;
7696 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7701 /******************************************************************/
7702 /* SFP+ module Section */
7703 /******************************************************************/
7704 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7705 struct bnx2x_phy *phy,
7708 struct bnx2x *bp = params->bp;
7709 /* Disable transmitter only for bootcodes which can enable it afterwards
7713 if (params->feature_config_flags &
7714 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7715 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7717 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7721 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7722 bnx2x_cl45_write(bp, phy,
7724 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7727 static u8 bnx2x_get_gpio_port(struct link_params *params)
7730 u32 swap_val, swap_override;
7731 struct bnx2x *bp = params->bp;
7733 gpio_port = BP_PATH(bp);
7735 gpio_port = params->port;
7736 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7737 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7738 return gpio_port ^ (swap_val && swap_override);
7741 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7742 struct bnx2x_phy *phy,
7746 u8 port = params->port;
7747 struct bnx2x *bp = params->bp;
7750 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7751 tx_en_mode = REG_RD(bp, params->shmem_base +
7752 offsetof(struct shmem_region,
7753 dev_info.port_hw_config[port].sfp_ctrl)) &
7754 PORT_HW_CFG_TX_LASER_MASK;
7755 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7756 "mode = %x\n", tx_en, port, tx_en_mode);
7757 switch (tx_en_mode) {
7758 case PORT_HW_CFG_TX_LASER_MDIO:
7760 bnx2x_cl45_read(bp, phy,
7762 MDIO_PMA_REG_PHY_IDENTIFIER,
7770 bnx2x_cl45_write(bp, phy,
7772 MDIO_PMA_REG_PHY_IDENTIFIER,
7775 case PORT_HW_CFG_TX_LASER_GPIO0:
7776 case PORT_HW_CFG_TX_LASER_GPIO1:
7777 case PORT_HW_CFG_TX_LASER_GPIO2:
7778 case PORT_HW_CFG_TX_LASER_GPIO3:
7781 u8 gpio_port, gpio_mode;
7783 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7785 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7787 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7788 gpio_port = bnx2x_get_gpio_port(params);
7789 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7793 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7798 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7799 struct bnx2x_phy *phy,
7802 struct bnx2x *bp = params->bp;
7803 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7805 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7807 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7810 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7811 struct link_params *params,
7812 u8 dev_addr, u16 addr, u8 byte_cnt,
7813 u8 *o_buf, u8 is_init)
7815 struct bnx2x *bp = params->bp;
7818 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7820 "Reading from eeprom is limited to 0xf\n");
7823 /* Set the read command byte count */
7824 bnx2x_cl45_write(bp, phy,
7825 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7826 (byte_cnt | (dev_addr << 8)));
7828 /* Set the read command address */
7829 bnx2x_cl45_write(bp, phy,
7830 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7833 /* Activate read command */
7834 bnx2x_cl45_write(bp, phy,
7835 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7838 /* Wait up to 500us for command complete status */
7839 for (i = 0; i < 100; i++) {
7840 bnx2x_cl45_read(bp, phy,
7842 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7843 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7844 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7849 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7850 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7852 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7853 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7857 /* Read the buffer */
7858 for (i = 0; i < byte_cnt; i++) {
7859 bnx2x_cl45_read(bp, phy,
7861 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7862 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7865 for (i = 0; i < 100; i++) {
7866 bnx2x_cl45_read(bp, phy,
7868 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7869 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7870 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7872 usleep_range(1000, 2000);
7877 static void bnx2x_warpcore_power_module(struct link_params *params,
7881 struct bnx2x *bp = params->bp;
7883 pin_cfg = (REG_RD(bp, params->shmem_base +
7884 offsetof(struct shmem_region,
7885 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7886 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7887 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7889 if (pin_cfg == PIN_CFG_NA)
7891 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7893 /* Low ==> corresponding SFP+ module is powered
7894 * high ==> the SFP+ module is powered down
7896 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7898 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7899 struct link_params *params,
7901 u16 addr, u8 byte_cnt,
7902 u8 *o_buf, u8 is_init)
7905 u8 i, j = 0, cnt = 0;
7908 struct bnx2x *bp = params->bp;
7910 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7912 "Reading from eeprom is limited to 16 bytes\n");
7916 /* 4 byte aligned address */
7917 addr32 = addr & (~0x3);
7919 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7920 bnx2x_warpcore_power_module(params, 0);
7921 /* Note that 100us are not enough here */
7922 usleep_range(1000, 2000);
7923 bnx2x_warpcore_power_module(params, 1);
7925 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7927 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7930 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7931 o_buf[j] = *((u8 *)data_array + i);
7939 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7940 struct link_params *params,
7941 u8 dev_addr, u16 addr, u8 byte_cnt,
7942 u8 *o_buf, u8 is_init)
7944 struct bnx2x *bp = params->bp;
7947 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7949 "Reading from eeprom is limited to 0xf\n");
7953 /* Set 2-wire transfer rate of SFP+ module EEPROM
7954 * to 100Khz since some DACs(direct attached cables) do
7955 * not work at 400Khz.
7957 bnx2x_cl45_write(bp, phy,
7959 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7960 ((dev_addr << 8) | 1));
7962 /* Need to read from 1.8000 to clear it */
7963 bnx2x_cl45_read(bp, phy,
7965 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7968 /* Set the read command byte count */
7969 bnx2x_cl45_write(bp, phy,
7971 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7972 ((byte_cnt < 2) ? 2 : byte_cnt));
7974 /* Set the read command address */
7975 bnx2x_cl45_write(bp, phy,
7977 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7979 /* Set the destination address */
7980 bnx2x_cl45_write(bp, phy,
7983 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7985 /* Activate read command */
7986 bnx2x_cl45_write(bp, phy,
7988 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7990 /* Wait appropriate time for two-wire command to finish before
7991 * polling the status register
7993 usleep_range(1000, 2000);
7995 /* Wait up to 500us for command complete status */
7996 for (i = 0; i < 100; i++) {
7997 bnx2x_cl45_read(bp, phy,
7999 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8000 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8001 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8006 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8007 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8009 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8010 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8014 /* Read the buffer */
8015 for (i = 0; i < byte_cnt; i++) {
8016 bnx2x_cl45_read(bp, phy,
8018 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8019 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8022 for (i = 0; i < 100; i++) {
8023 bnx2x_cl45_read(bp, phy,
8025 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8026 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8027 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8029 usleep_range(1000, 2000);
8034 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8035 struct link_params *params, u8 dev_addr,
8036 u16 addr, u16 byte_cnt, u8 *o_buf)
8039 struct bnx2x *bp = params->bp;
8041 u8 *user_data = o_buf;
8042 read_sfp_module_eeprom_func_p read_func;
8044 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8045 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8049 switch (phy->type) {
8050 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8051 read_func = bnx2x_8726_read_sfp_module_eeprom;
8053 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8054 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8055 read_func = bnx2x_8727_read_sfp_module_eeprom;
8057 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8058 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8064 while (!rc && (byte_cnt > 0)) {
8065 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8066 SFP_EEPROM_PAGE_SIZE : byte_cnt;
8067 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8069 byte_cnt -= xfer_size;
8070 user_data += xfer_size;
8076 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8077 struct link_params *params,
8080 struct bnx2x *bp = params->bp;
8081 u32 sync_offset = 0, phy_idx, media_types;
8082 u8 gport, val[2], check_limiting_mode = 0;
8083 *edc_mode = EDC_MODE_LIMITING;
8084 phy->media_type = ETH_PHY_UNSPECIFIED;
8085 /* First check for copper cable */
8086 if (bnx2x_read_sfp_module_eeprom(phy,
8089 SFP_EEPROM_CON_TYPE_ADDR,
8092 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8097 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8099 u8 copper_module_type;
8100 phy->media_type = ETH_PHY_DA_TWINAX;
8101 /* Check if its active cable (includes SFP+ module)
8104 if (bnx2x_read_sfp_module_eeprom(phy,
8107 SFP_EEPROM_FC_TX_TECH_ADDR,
8109 &copper_module_type) != 0) {
8111 "Failed to read copper-cable-type"
8112 " from SFP+ EEPROM\n");
8116 if (copper_module_type &
8117 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8118 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8119 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8120 *edc_mode = EDC_MODE_ACTIVE_DAC;
8122 check_limiting_mode = 1;
8123 } else if (copper_module_type &
8124 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8126 "Passive Copper cable detected\n");
8128 EDC_MODE_PASSIVE_DAC;
8131 "Unknown copper-cable-type 0x%x !!!\n",
8132 copper_module_type);
8137 case SFP_EEPROM_CON_TYPE_VAL_LC:
8138 case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8139 check_limiting_mode = 1;
8140 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8141 SFP_EEPROM_COMP_CODE_LR_MASK |
8142 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8143 DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8144 gport = params->port;
8145 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8146 if (phy->req_line_speed != SPEED_1000) {
8147 phy->req_line_speed = SPEED_1000;
8148 if (!CHIP_IS_E1x(bp)) {
8149 gport = BP_PATH(bp) +
8150 (params->port << 1);
8153 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8157 int idx, cfg_idx = 0;
8158 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8159 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8160 if (params->phy[idx].type == phy->type) {
8161 cfg_idx = LINK_CONFIG_IDX(idx);
8165 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8166 phy->req_line_speed = params->req_line_speed[cfg_idx];
8170 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8174 sync_offset = params->shmem_base +
8175 offsetof(struct shmem_region,
8176 dev_info.port_hw_config[params->port].media_type);
8177 media_types = REG_RD(bp, sync_offset);
8178 /* Update media type for non-PMF sync */
8179 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8180 if (&(params->phy[phy_idx]) == phy) {
8181 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8182 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8183 media_types |= ((phy->media_type &
8184 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8185 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8189 REG_WR(bp, sync_offset, media_types);
8190 if (check_limiting_mode) {
8191 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8192 if (bnx2x_read_sfp_module_eeprom(phy,
8195 SFP_EEPROM_OPTIONS_ADDR,
8196 SFP_EEPROM_OPTIONS_SIZE,
8199 "Failed to read Option field from module EEPROM\n");
8202 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8203 *edc_mode = EDC_MODE_LINEAR;
8205 *edc_mode = EDC_MODE_LIMITING;
8207 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8210 /* This function read the relevant field from the module (SFP+), and verify it
8211 * is compliant with this board
8213 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8214 struct link_params *params)
8216 struct bnx2x *bp = params->bp;
8218 u32 fw_resp, fw_cmd_param;
8219 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8220 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8221 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8222 val = REG_RD(bp, params->shmem_base +
8223 offsetof(struct shmem_region, dev_info.
8224 port_feature_config[params->port].config));
8225 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8226 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8227 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8231 if (params->feature_config_flags &
8232 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8233 /* Use specific phy request */
8234 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8235 } else if (params->feature_config_flags &
8236 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8237 /* Use first phy request only in case of non-dual media*/
8238 if (DUAL_MEDIA(params)) {
8240 "FW does not support OPT MDL verification\n");
8243 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8245 /* No support in OPT MDL detection */
8247 "FW does not support OPT MDL verification\n");
8251 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8252 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8253 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8254 DP(NETIF_MSG_LINK, "Approved module\n");
8258 /* Format the warning message */
8259 if (bnx2x_read_sfp_module_eeprom(phy,
8262 SFP_EEPROM_VENDOR_NAME_ADDR,
8263 SFP_EEPROM_VENDOR_NAME_SIZE,
8265 vendor_name[0] = '\0';
8267 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8268 if (bnx2x_read_sfp_module_eeprom(phy,
8271 SFP_EEPROM_PART_NO_ADDR,
8272 SFP_EEPROM_PART_NO_SIZE,
8274 vendor_pn[0] = '\0';
8276 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8278 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8279 " Port %d from %s part number %s\n",
8280 params->port, vendor_name, vendor_pn);
8281 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8282 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8283 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8287 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8288 struct link_params *params)
8293 struct bnx2x *bp = params->bp;
8295 /* Initialization time after hot-plug may take up to 300ms for
8296 * some phys type ( e.g. JDSU )
8299 for (timeout = 0; timeout < 60; timeout++) {
8300 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8301 rc = bnx2x_warpcore_read_sfp_module_eeprom(
8302 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8305 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8310 "SFP+ module initialization took %d ms\n",
8314 usleep_range(5000, 10000);
8316 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8321 static void bnx2x_8727_power_module(struct bnx2x *bp,
8322 struct bnx2x_phy *phy,
8324 /* Make sure GPIOs are not using for LED mode */
8326 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8327 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8329 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8330 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8331 * where the 1st bit is the over-current(only input), and 2nd bit is
8332 * for power( only output )
8334 * In case of NOC feature is disabled and power is up, set GPIO control
8335 * as input to enable listening of over-current indication
8337 if (phy->flags & FLAGS_NOC)
8342 /* Set GPIO control to OUTPUT, and set the power bit
8343 * to according to the is_power_up
8347 bnx2x_cl45_write(bp, phy,
8349 MDIO_PMA_REG_8727_GPIO_CTRL,
8353 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8354 struct bnx2x_phy *phy,
8357 u16 cur_limiting_mode;
8359 bnx2x_cl45_read(bp, phy,
8361 MDIO_PMA_REG_ROM_VER2,
8362 &cur_limiting_mode);
8363 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8366 if (edc_mode == EDC_MODE_LIMITING) {
8367 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8368 bnx2x_cl45_write(bp, phy,
8370 MDIO_PMA_REG_ROM_VER2,
8372 } else { /* LRM mode ( default )*/
8374 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8376 /* Changing to LRM mode takes quite few seconds. So do it only
8377 * if current mode is limiting (default is LRM)
8379 if (cur_limiting_mode != EDC_MODE_LIMITING)
8382 bnx2x_cl45_write(bp, phy,
8384 MDIO_PMA_REG_LRM_MODE,
8386 bnx2x_cl45_write(bp, phy,
8388 MDIO_PMA_REG_ROM_VER2,
8390 bnx2x_cl45_write(bp, phy,
8392 MDIO_PMA_REG_MISC_CTRL0,
8394 bnx2x_cl45_write(bp, phy,
8396 MDIO_PMA_REG_LRM_MODE,
8402 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8403 struct bnx2x_phy *phy,
8408 bnx2x_cl45_read(bp, phy,
8410 MDIO_PMA_REG_PHY_IDENTIFIER,
8413 bnx2x_cl45_write(bp, phy,
8415 MDIO_PMA_REG_PHY_IDENTIFIER,
8416 (phy_identifier & ~(1<<9)));
8418 bnx2x_cl45_read(bp, phy,
8420 MDIO_PMA_REG_ROM_VER2,
8422 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8423 bnx2x_cl45_write(bp, phy,
8425 MDIO_PMA_REG_ROM_VER2,
8426 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8428 bnx2x_cl45_write(bp, phy,
8430 MDIO_PMA_REG_PHY_IDENTIFIER,
8431 (phy_identifier | (1<<9)));
8436 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8437 struct link_params *params,
8440 struct bnx2x *bp = params->bp;
8444 bnx2x_sfp_set_transmitter(params, phy, 0);
8447 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8448 bnx2x_sfp_set_transmitter(params, phy, 1);
8451 bnx2x_cl45_write(bp, phy,
8452 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8454 bnx2x_cl45_write(bp, phy,
8455 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8457 bnx2x_cl45_write(bp, phy,
8458 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8459 /* Make MOD_ABS give interrupt on change */
8460 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8461 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8464 if (phy->flags & FLAGS_NOC)
8466 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8467 * status which reflect SFP+ module over-current
8469 if (!(phy->flags & FLAGS_NOC))
8470 val &= 0xff8f; /* Reset bits 4-6 */
8471 bnx2x_cl45_write(bp, phy,
8472 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8476 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8482 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8485 struct bnx2x *bp = params->bp;
8487 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8488 offsetof(struct shmem_region,
8489 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8490 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8491 switch (fault_led_gpio) {
8492 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8494 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8495 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8496 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8497 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8499 u8 gpio_port = bnx2x_get_gpio_port(params);
8500 u16 gpio_pin = fault_led_gpio -
8501 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8502 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8503 "pin %x port %x mode %x\n",
8504 gpio_pin, gpio_port, gpio_mode);
8505 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8509 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8514 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8518 u8 port = params->port;
8519 struct bnx2x *bp = params->bp;
8520 pin_cfg = (REG_RD(bp, params->shmem_base +
8521 offsetof(struct shmem_region,
8522 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8523 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8524 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8525 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8526 gpio_mode, pin_cfg);
8527 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8530 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8533 struct bnx2x *bp = params->bp;
8534 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8535 if (CHIP_IS_E3(bp)) {
8536 /* Low ==> if SFP+ module is supported otherwise
8537 * High ==> if SFP+ module is not on the approved vendor list
8539 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8541 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8544 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8545 struct link_params *params)
8547 struct bnx2x *bp = params->bp;
8548 bnx2x_warpcore_power_module(params, 0);
8549 /* Put Warpcore in low power mode */
8550 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8552 /* Put LCPLL in low power mode */
8553 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8554 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8555 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8558 static void bnx2x_power_sfp_module(struct link_params *params,
8559 struct bnx2x_phy *phy,
8562 struct bnx2x *bp = params->bp;
8563 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8565 switch (phy->type) {
8566 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8567 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8568 bnx2x_8727_power_module(params->bp, phy, power);
8570 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8571 bnx2x_warpcore_power_module(params, power);
8577 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8578 struct bnx2x_phy *phy,
8582 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8583 struct bnx2x *bp = params->bp;
8585 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8586 /* This is a global register which controls all lanes */
8587 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8588 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8589 val &= ~(0xf << (lane << 2));
8592 case EDC_MODE_LINEAR:
8593 case EDC_MODE_LIMITING:
8594 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8596 case EDC_MODE_PASSIVE_DAC:
8597 case EDC_MODE_ACTIVE_DAC:
8598 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8604 val |= (mode << (lane << 2));
8605 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8606 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8608 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8609 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8611 /* Restart microcode to re-read the new mode */
8612 bnx2x_warpcore_reset_lane(bp, phy, 1);
8613 bnx2x_warpcore_reset_lane(bp, phy, 0);
8617 static void bnx2x_set_limiting_mode(struct link_params *params,
8618 struct bnx2x_phy *phy,
8621 switch (phy->type) {
8622 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8623 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8625 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8626 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8627 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8629 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8630 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8635 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8636 struct link_params *params)
8638 struct bnx2x *bp = params->bp;
8642 u32 val = REG_RD(bp, params->shmem_base +
8643 offsetof(struct shmem_region, dev_info.
8644 port_feature_config[params->port].config));
8645 /* Enabled transmitter by default */
8646 bnx2x_sfp_set_transmitter(params, phy, 1);
8647 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8649 /* Power up module */
8650 bnx2x_power_sfp_module(params, phy, 1);
8651 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8652 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8654 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8655 /* Check SFP+ module compatibility */
8656 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8658 /* Turn on fault module-detected led */
8659 bnx2x_set_sfp_module_fault_led(params,
8660 MISC_REGISTERS_GPIO_HIGH);
8662 /* Check if need to power down the SFP+ module */
8663 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8664 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8665 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8666 bnx2x_power_sfp_module(params, phy, 0);
8670 /* Turn off fault module-detected led */
8671 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8674 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8675 * is done automatically
8677 bnx2x_set_limiting_mode(params, phy, edc_mode);
8679 /* Disable transmit for this module if the module is not approved, and
8680 * laser needs to be disabled.
8683 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8684 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8685 bnx2x_sfp_set_transmitter(params, phy, 0);
8690 void bnx2x_handle_module_detect_int(struct link_params *params)
8692 struct bnx2x *bp = params->bp;
8693 struct bnx2x_phy *phy;
8695 u8 gpio_num, gpio_port;
8696 if (CHIP_IS_E3(bp)) {
8697 phy = ¶ms->phy[INT_PHY];
8698 /* Always enable TX laser,will be disabled in case of fault */
8699 bnx2x_sfp_set_transmitter(params, phy, 1);
8701 phy = ¶ms->phy[EXT_PHY1];
8703 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8704 params->port, &gpio_num, &gpio_port) ==
8706 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8710 /* Set valid module led off */
8711 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8713 /* Get current gpio val reflecting module plugged in / out*/
8714 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8716 /* Call the handling function in case module is detected */
8717 if (gpio_val == 0) {
8718 bnx2x_set_mdio_emac_per_phy(bp, params);
8719 bnx2x_set_aer_mmd(params, phy);
8721 bnx2x_power_sfp_module(params, phy, 1);
8722 bnx2x_set_gpio_int(bp, gpio_num,
8723 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8725 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8726 bnx2x_sfp_module_detection(phy, params);
8727 if (CHIP_IS_E3(bp)) {
8729 /* In case WC is out of reset, reconfigure the
8730 * link speed while taking into account 1G
8731 * module limitation.
8733 bnx2x_cl45_read(bp, phy,
8735 MDIO_WC_REG_DIGITAL5_MISC6,
8737 if ((!rx_tx_in_reset) &&
8738 (params->link_flags &
8740 bnx2x_warpcore_reset_lane(bp, phy, 1);
8741 bnx2x_warpcore_config_sfi(phy, params);
8742 bnx2x_warpcore_reset_lane(bp, phy, 0);
8746 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8749 bnx2x_set_gpio_int(bp, gpio_num,
8750 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8752 /* Module was plugged out.
8753 * Disable transmit for this module
8755 phy->media_type = ETH_PHY_NOT_PRESENT;
8759 /******************************************************************/
8760 /* Used by 8706 and 8727 */
8761 /******************************************************************/
8762 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8763 struct bnx2x_phy *phy,
8764 u16 alarm_status_offset,
8765 u16 alarm_ctrl_offset)
8767 u16 alarm_status, val;
8768 bnx2x_cl45_read(bp, phy,
8769 MDIO_PMA_DEVAD, alarm_status_offset,
8771 bnx2x_cl45_read(bp, phy,
8772 MDIO_PMA_DEVAD, alarm_status_offset,
8774 /* Mask or enable the fault event. */
8775 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8776 if (alarm_status & (1<<0))
8780 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8782 /******************************************************************/
8783 /* common BCM8706/BCM8726 PHY SECTION */
8784 /******************************************************************/
8785 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8786 struct link_params *params,
8787 struct link_vars *vars)
8790 u16 val1, val2, rx_sd, pcs_status;
8791 struct bnx2x *bp = params->bp;
8792 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8794 bnx2x_cl45_read(bp, phy,
8795 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8797 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8798 MDIO_PMA_LASI_TXCTRL);
8800 /* Clear LASI indication*/
8801 bnx2x_cl45_read(bp, phy,
8802 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8803 bnx2x_cl45_read(bp, phy,
8804 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8805 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8807 bnx2x_cl45_read(bp, phy,
8808 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8809 bnx2x_cl45_read(bp, phy,
8810 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8811 bnx2x_cl45_read(bp, phy,
8812 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8813 bnx2x_cl45_read(bp, phy,
8814 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8816 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8817 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8818 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8819 * are set, or if the autoneg bit 1 is set
8821 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8824 vars->line_speed = SPEED_1000;
8826 vars->line_speed = SPEED_10000;
8827 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8828 vars->duplex = DUPLEX_FULL;
8831 /* Capture 10G link fault. Read twice to clear stale value. */
8832 if (vars->line_speed == SPEED_10000) {
8833 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8834 MDIO_PMA_LASI_TXSTAT, &val1);
8835 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8836 MDIO_PMA_LASI_TXSTAT, &val1);
8838 vars->fault_detected = 1;
8844 /******************************************************************/
8845 /* BCM8706 PHY SECTION */
8846 /******************************************************************/
8847 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8848 struct link_params *params,
8849 struct link_vars *vars)
8853 struct bnx2x *bp = params->bp;
8855 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8856 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8858 bnx2x_ext_phy_hw_reset(bp, params->port);
8859 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8860 bnx2x_wait_reset_complete(bp, phy, params);
8862 /* Wait until fw is loaded */
8863 for (cnt = 0; cnt < 100; cnt++) {
8864 bnx2x_cl45_read(bp, phy,
8865 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8868 usleep_range(10000, 20000);
8870 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8871 if ((params->feature_config_flags &
8872 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8875 for (i = 0; i < 4; i++) {
8876 reg = MDIO_XS_8706_REG_BANK_RX0 +
8877 i*(MDIO_XS_8706_REG_BANK_RX1 -
8878 MDIO_XS_8706_REG_BANK_RX0);
8879 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8880 /* Clear first 3 bits of the control */
8882 /* Set control bits according to configuration */
8883 val |= (phy->rx_preemphasis[i] & 0x7);
8884 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8885 " reg 0x%x <-- val 0x%x\n", reg, val);
8886 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8890 if (phy->req_line_speed == SPEED_10000) {
8891 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8893 bnx2x_cl45_write(bp, phy,
8895 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8896 bnx2x_cl45_write(bp, phy,
8897 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8899 /* Arm LASI for link and Tx fault. */
8900 bnx2x_cl45_write(bp, phy,
8901 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8903 /* Force 1Gbps using autoneg with 1G advertisement */
8905 /* Allow CL37 through CL73 */
8906 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8907 bnx2x_cl45_write(bp, phy,
8908 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8910 /* Enable Full-Duplex advertisement on CL37 */
8911 bnx2x_cl45_write(bp, phy,
8912 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8913 /* Enable CL37 AN */
8914 bnx2x_cl45_write(bp, phy,
8915 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8917 bnx2x_cl45_write(bp, phy,
8918 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8920 /* Enable clause 73 AN */
8921 bnx2x_cl45_write(bp, phy,
8922 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8923 bnx2x_cl45_write(bp, phy,
8924 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8926 bnx2x_cl45_write(bp, phy,
8927 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8930 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8932 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8933 * power mode, if TX Laser is disabled
8936 tx_en_mode = REG_RD(bp, params->shmem_base +
8937 offsetof(struct shmem_region,
8938 dev_info.port_hw_config[params->port].sfp_ctrl))
8939 & PORT_HW_CFG_TX_LASER_MASK;
8941 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8942 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8943 bnx2x_cl45_read(bp, phy,
8944 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8946 bnx2x_cl45_write(bp, phy,
8947 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8953 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8954 struct link_params *params,
8955 struct link_vars *vars)
8957 return bnx2x_8706_8726_read_status(phy, params, vars);
8960 /******************************************************************/
8961 /* BCM8726 PHY SECTION */
8962 /******************************************************************/
8963 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8964 struct link_params *params)
8966 struct bnx2x *bp = params->bp;
8967 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8968 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8971 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8972 struct link_params *params)
8974 struct bnx2x *bp = params->bp;
8975 /* Need to wait 100ms after reset */
8978 /* Micro controller re-boot */
8979 bnx2x_cl45_write(bp, phy,
8980 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8982 /* Set soft reset */
8983 bnx2x_cl45_write(bp, phy,
8985 MDIO_PMA_REG_GEN_CTRL,
8986 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8988 bnx2x_cl45_write(bp, phy,
8990 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8992 bnx2x_cl45_write(bp, phy,
8994 MDIO_PMA_REG_GEN_CTRL,
8995 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8997 /* Wait for 150ms for microcode load */
9000 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9001 bnx2x_cl45_write(bp, phy,
9003 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9006 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9009 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9010 struct link_params *params,
9011 struct link_vars *vars)
9013 struct bnx2x *bp = params->bp;
9015 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9017 bnx2x_cl45_read(bp, phy,
9018 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9020 if (val1 & (1<<15)) {
9021 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9023 vars->line_speed = 0;
9030 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9031 struct link_params *params,
9032 struct link_vars *vars)
9034 struct bnx2x *bp = params->bp;
9035 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9037 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9038 bnx2x_wait_reset_complete(bp, phy, params);
9040 bnx2x_8726_external_rom_boot(phy, params);
9042 /* Need to call module detected on initialization since the module
9043 * detection triggered by actual module insertion might occur before
9044 * driver is loaded, and when driver is loaded, it reset all
9045 * registers, including the transmitter
9047 bnx2x_sfp_module_detection(phy, params);
9049 if (phy->req_line_speed == SPEED_1000) {
9050 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9051 bnx2x_cl45_write(bp, phy,
9052 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9053 bnx2x_cl45_write(bp, phy,
9054 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9055 bnx2x_cl45_write(bp, phy,
9056 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9057 bnx2x_cl45_write(bp, phy,
9058 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9060 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9061 (phy->speed_cap_mask &
9062 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9063 ((phy->speed_cap_mask &
9064 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9065 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9066 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9067 /* Set Flow control */
9068 bnx2x_ext_phy_set_pause(params, phy, vars);
9069 bnx2x_cl45_write(bp, phy,
9070 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9071 bnx2x_cl45_write(bp, phy,
9072 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9073 bnx2x_cl45_write(bp, phy,
9074 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9075 bnx2x_cl45_write(bp, phy,
9076 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9077 bnx2x_cl45_write(bp, phy,
9078 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9079 /* Enable RX-ALARM control to receive interrupt for 1G speed
9082 bnx2x_cl45_write(bp, phy,
9083 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9084 bnx2x_cl45_write(bp, phy,
9085 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9088 } else { /* Default 10G. Set only LASI control */
9089 bnx2x_cl45_write(bp, phy,
9090 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9093 /* Set TX PreEmphasis if needed */
9094 if ((params->feature_config_flags &
9095 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9097 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9098 phy->tx_preemphasis[0],
9099 phy->tx_preemphasis[1]);
9100 bnx2x_cl45_write(bp, phy,
9102 MDIO_PMA_REG_8726_TX_CTRL1,
9103 phy->tx_preemphasis[0]);
9105 bnx2x_cl45_write(bp, phy,
9107 MDIO_PMA_REG_8726_TX_CTRL2,
9108 phy->tx_preemphasis[1]);
9115 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9116 struct link_params *params)
9118 struct bnx2x *bp = params->bp;
9119 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9120 /* Set serial boot control for external load */
9121 bnx2x_cl45_write(bp, phy,
9123 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9126 /******************************************************************/
9127 /* BCM8727 PHY SECTION */
9128 /******************************************************************/
9130 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9131 struct link_params *params, u8 mode)
9133 struct bnx2x *bp = params->bp;
9134 u16 led_mode_bitmask = 0;
9135 u16 gpio_pins_bitmask = 0;
9137 /* Only NOC flavor requires to set the LED specifically */
9138 if (!(phy->flags & FLAGS_NOC))
9141 case LED_MODE_FRONT_PANEL_OFF:
9143 led_mode_bitmask = 0;
9144 gpio_pins_bitmask = 0x03;
9147 led_mode_bitmask = 0;
9148 gpio_pins_bitmask = 0x02;
9151 led_mode_bitmask = 0x60;
9152 gpio_pins_bitmask = 0x11;
9155 bnx2x_cl45_read(bp, phy,
9157 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9160 val |= led_mode_bitmask;
9161 bnx2x_cl45_write(bp, phy,
9163 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9165 bnx2x_cl45_read(bp, phy,
9167 MDIO_PMA_REG_8727_GPIO_CTRL,
9170 val |= gpio_pins_bitmask;
9171 bnx2x_cl45_write(bp, phy,
9173 MDIO_PMA_REG_8727_GPIO_CTRL,
9176 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9177 struct link_params *params) {
9178 u32 swap_val, swap_override;
9180 /* The PHY reset is controlled by GPIO 1. Fake the port number
9181 * to cancel the swap done in set_gpio()
9183 struct bnx2x *bp = params->bp;
9184 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9185 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9186 port = (swap_val && swap_override) ^ 1;
9187 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9188 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9191 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9192 struct link_params *params)
9194 struct bnx2x *bp = params->bp;
9196 /* Set option 1G speed */
9197 if ((phy->req_line_speed == SPEED_1000) ||
9198 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9199 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9200 bnx2x_cl45_write(bp, phy,
9201 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9202 bnx2x_cl45_write(bp, phy,
9203 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9204 bnx2x_cl45_read(bp, phy,
9205 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9206 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9207 /* Power down the XAUI until link is up in case of dual-media
9210 if (DUAL_MEDIA(params)) {
9211 bnx2x_cl45_read(bp, phy,
9213 MDIO_PMA_REG_8727_PCS_GP, &val);
9215 bnx2x_cl45_write(bp, phy,
9217 MDIO_PMA_REG_8727_PCS_GP, val);
9219 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9220 ((phy->speed_cap_mask &
9221 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9222 ((phy->speed_cap_mask &
9223 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9224 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9226 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9227 bnx2x_cl45_write(bp, phy,
9228 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9229 bnx2x_cl45_write(bp, phy,
9230 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9232 /* Since the 8727 has only single reset pin, need to set the 10G
9233 * registers although it is default
9235 bnx2x_cl45_write(bp, phy,
9236 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9238 bnx2x_cl45_write(bp, phy,
9239 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9240 bnx2x_cl45_write(bp, phy,
9241 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9242 bnx2x_cl45_write(bp, phy,
9243 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9248 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9249 struct link_params *params,
9250 struct link_vars *vars)
9253 u16 tmp1, mod_abs, tmp2;
9254 struct bnx2x *bp = params->bp;
9255 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9257 bnx2x_wait_reset_complete(bp, phy, params);
9259 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9261 bnx2x_8727_specific_func(phy, params, PHY_INIT);
9262 /* Initially configure MOD_ABS to interrupt when module is
9265 bnx2x_cl45_read(bp, phy,
9266 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9267 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9268 * When the EDC is off it locks onto a reference clock and avoids
9272 if (!(phy->flags & FLAGS_NOC))
9274 bnx2x_cl45_write(bp, phy,
9275 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9277 /* Enable/Disable PHY transmitter output */
9278 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9280 bnx2x_8727_power_module(bp, phy, 1);
9282 bnx2x_cl45_read(bp, phy,
9283 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9285 bnx2x_cl45_read(bp, phy,
9286 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9288 bnx2x_8727_config_speed(phy, params);
9291 /* Set TX PreEmphasis if needed */
9292 if ((params->feature_config_flags &
9293 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9294 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9295 phy->tx_preemphasis[0],
9296 phy->tx_preemphasis[1]);
9297 bnx2x_cl45_write(bp, phy,
9298 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9299 phy->tx_preemphasis[0]);
9301 bnx2x_cl45_write(bp, phy,
9302 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9303 phy->tx_preemphasis[1]);
9306 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9307 * power mode, if TX Laser is disabled
9309 tx_en_mode = REG_RD(bp, params->shmem_base +
9310 offsetof(struct shmem_region,
9311 dev_info.port_hw_config[params->port].sfp_ctrl))
9312 & PORT_HW_CFG_TX_LASER_MASK;
9314 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9316 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9317 bnx2x_cl45_read(bp, phy,
9318 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9321 bnx2x_cl45_write(bp, phy,
9322 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9323 bnx2x_cl45_read(bp, phy,
9324 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9326 bnx2x_cl45_write(bp, phy,
9327 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9334 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9335 struct link_params *params)
9337 struct bnx2x *bp = params->bp;
9338 u16 mod_abs, rx_alarm_status;
9339 u32 val = REG_RD(bp, params->shmem_base +
9340 offsetof(struct shmem_region, dev_info.
9341 port_feature_config[params->port].
9343 bnx2x_cl45_read(bp, phy,
9345 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9346 if (mod_abs & (1<<8)) {
9348 /* Module is absent */
9350 "MOD_ABS indication show module is absent\n");
9351 phy->media_type = ETH_PHY_NOT_PRESENT;
9352 /* 1. Set mod_abs to detect next module
9354 * 2. Set EDC off by setting OPTXLOS signal input to low
9356 * When the EDC is off it locks onto a reference clock and
9357 * avoids becoming 'lost'.
9360 if (!(phy->flags & FLAGS_NOC))
9362 bnx2x_cl45_write(bp, phy,
9364 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9366 /* Clear RX alarm since it stays up as long as
9367 * the mod_abs wasn't changed
9369 bnx2x_cl45_read(bp, phy,
9371 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9374 /* Module is present */
9376 "MOD_ABS indication show module is present\n");
9377 /* First disable transmitter, and if the module is ok, the
9378 * module_detection will enable it
9379 * 1. Set mod_abs to detect next module absent event ( bit 8)
9380 * 2. Restore the default polarity of the OPRXLOS signal and
9381 * this signal will then correctly indicate the presence or
9382 * absence of the Rx signal. (bit 9)
9385 if (!(phy->flags & FLAGS_NOC))
9387 bnx2x_cl45_write(bp, phy,
9389 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9391 /* Clear RX alarm since it stays up as long as the mod_abs
9392 * wasn't changed. This is need to be done before calling the
9393 * module detection, otherwise it will clear* the link update
9396 bnx2x_cl45_read(bp, phy,
9398 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9401 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9402 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9403 bnx2x_sfp_set_transmitter(params, phy, 0);
9405 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9406 bnx2x_sfp_module_detection(phy, params);
9408 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9410 /* Reconfigure link speed based on module type limitations */
9411 bnx2x_8727_config_speed(phy, params);
9414 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9416 /* No need to check link status in case of module plugged in/out */
9419 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9420 struct link_params *params,
9421 struct link_vars *vars)
9424 struct bnx2x *bp = params->bp;
9425 u8 link_up = 0, oc_port = params->port;
9426 u16 link_status = 0;
9427 u16 rx_alarm_status, lasi_ctrl, val1;
9429 /* If PHY is not initialized, do not check link status */
9430 bnx2x_cl45_read(bp, phy,
9431 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9436 /* Check the LASI on Rx */
9437 bnx2x_cl45_read(bp, phy,
9438 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9440 vars->line_speed = 0;
9441 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9443 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9444 MDIO_PMA_LASI_TXCTRL);
9446 bnx2x_cl45_read(bp, phy,
9447 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9449 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9452 bnx2x_cl45_read(bp, phy,
9453 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9455 /* If a module is present and there is need to check
9458 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9459 /* Check over-current using 8727 GPIO0 input*/
9460 bnx2x_cl45_read(bp, phy,
9461 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9464 if ((val1 & (1<<8)) == 0) {
9465 if (!CHIP_IS_E1x(bp))
9466 oc_port = BP_PATH(bp) + (params->port << 1);
9468 "8727 Power fault has been detected on port %d\n",
9470 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9471 "been detected and the power to "
9472 "that SFP+ module has been removed "
9473 "to prevent failure of the card. "
9474 "Please remove the SFP+ module and "
9475 "restart the system to clear this "
9478 /* Disable all RX_ALARMs except for mod_abs */
9479 bnx2x_cl45_write(bp, phy,
9481 MDIO_PMA_LASI_RXCTRL, (1<<5));
9483 bnx2x_cl45_read(bp, phy,
9485 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9486 /* Wait for module_absent_event */
9488 bnx2x_cl45_write(bp, phy,
9490 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9491 /* Clear RX alarm */
9492 bnx2x_cl45_read(bp, phy,
9494 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9495 bnx2x_8727_power_module(params->bp, phy, 0);
9498 } /* Over current check */
9500 /* When module absent bit is set, check module */
9501 if (rx_alarm_status & (1<<5)) {
9502 bnx2x_8727_handle_mod_abs(phy, params);
9503 /* Enable all mod_abs and link detection bits */
9504 bnx2x_cl45_write(bp, phy,
9505 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9509 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9510 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9511 bnx2x_sfp_set_transmitter(params, phy, 1);
9513 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9517 bnx2x_cl45_read(bp, phy,
9519 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9521 /* Bits 0..2 --> speed detected,
9522 * Bits 13..15--> link is down
9524 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9526 vars->line_speed = SPEED_10000;
9527 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9529 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9531 vars->line_speed = SPEED_1000;
9532 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9536 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9540 /* Capture 10G link fault. */
9541 if (vars->line_speed == SPEED_10000) {
9542 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9543 MDIO_PMA_LASI_TXSTAT, &val1);
9545 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9546 MDIO_PMA_LASI_TXSTAT, &val1);
9548 if (val1 & (1<<0)) {
9549 vars->fault_detected = 1;
9554 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9555 vars->duplex = DUPLEX_FULL;
9556 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9559 if ((DUAL_MEDIA(params)) &&
9560 (phy->req_line_speed == SPEED_1000)) {
9561 bnx2x_cl45_read(bp, phy,
9563 MDIO_PMA_REG_8727_PCS_GP, &val1);
9564 /* In case of dual-media board and 1G, power up the XAUI side,
9565 * otherwise power it down. For 10G it is done automatically
9571 bnx2x_cl45_write(bp, phy,
9573 MDIO_PMA_REG_8727_PCS_GP, val1);
9578 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9579 struct link_params *params)
9581 struct bnx2x *bp = params->bp;
9583 /* Enable/Disable PHY transmitter output */
9584 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9586 /* Disable Transmitter */
9587 bnx2x_sfp_set_transmitter(params, phy, 0);
9589 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9593 /******************************************************************/
9594 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9595 /******************************************************************/
9596 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9600 u16 val, fw_ver2, cnt, i;
9601 static struct bnx2x_reg_set reg_set[] = {
9602 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9603 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9604 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9605 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9606 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9610 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9611 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9612 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9613 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9616 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9617 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9618 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9619 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9620 reg_set[i].reg, reg_set[i].val);
9622 for (cnt = 0; cnt < 100; cnt++) {
9623 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9629 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9630 "phy fw version(1)\n");
9631 bnx2x_save_spirom_version(bp, port, 0,
9637 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9638 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9639 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9640 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9641 for (cnt = 0; cnt < 100; cnt++) {
9642 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9648 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9650 bnx2x_save_spirom_version(bp, port, 0,
9655 /* lower 16 bits of the register SPI_FW_STATUS */
9656 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9657 /* upper 16 bits of register SPI_FW_STATUS */
9658 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9660 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9665 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9666 struct bnx2x_phy *phy)
9669 static struct bnx2x_reg_set reg_set[] = {
9670 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9671 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9672 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9673 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9674 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9675 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9676 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9678 /* PHYC_CTL_LED_CTL */
9679 bnx2x_cl45_read(bp, phy,
9681 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9685 bnx2x_cl45_write(bp, phy,
9687 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9689 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9690 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9693 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9694 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9695 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9697 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9699 /* stretch_en for LED3*/
9700 bnx2x_cl45_read_or_write(bp, phy,
9701 MDIO_PMA_DEVAD, offset,
9702 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9705 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9706 struct link_params *params,
9709 struct bnx2x *bp = params->bp;
9712 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9713 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9714 /* Save spirom version */
9715 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9717 /* This phy uses the NIG latch mechanism since link indication
9718 * arrives through its LED4 and not via its LASI signal, so we
9719 * get steady signal instead of clear on read
9721 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9722 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9724 bnx2x_848xx_set_led(bp, phy);
9729 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9730 struct link_params *params,
9731 struct link_vars *vars)
9733 struct bnx2x *bp = params->bp;
9734 u16 autoneg_val, an_1000_val, an_10_100_val;
9736 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9737 bnx2x_cl45_write(bp, phy,
9738 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9740 /* set 1000 speed advertisement */
9741 bnx2x_cl45_read(bp, phy,
9742 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9745 bnx2x_ext_phy_set_pause(params, phy, vars);
9746 bnx2x_cl45_read(bp, phy,
9748 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9750 bnx2x_cl45_read(bp, phy,
9751 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9753 /* Disable forced speed */
9754 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9755 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9757 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9758 (phy->speed_cap_mask &
9759 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9760 (phy->req_line_speed == SPEED_1000)) {
9761 an_1000_val |= (1<<8);
9762 autoneg_val |= (1<<9 | 1<<12);
9763 if (phy->req_duplex == DUPLEX_FULL)
9764 an_1000_val |= (1<<9);
9765 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9767 an_1000_val &= ~((1<<8) | (1<<9));
9769 bnx2x_cl45_write(bp, phy,
9770 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9773 /* Set 10/100 speed advertisement */
9774 if (phy->req_line_speed == SPEED_AUTO_NEG) {
9775 if (phy->speed_cap_mask &
9776 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9777 /* Enable autoneg and restart autoneg for legacy speeds
9779 autoneg_val |= (1<<9 | 1<<12);
9780 an_10_100_val |= (1<<8);
9781 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9784 if (phy->speed_cap_mask &
9785 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9786 /* Enable autoneg and restart autoneg for legacy speeds
9788 autoneg_val |= (1<<9 | 1<<12);
9789 an_10_100_val |= (1<<7);
9790 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9793 if ((phy->speed_cap_mask &
9794 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9795 (phy->supported & SUPPORTED_10baseT_Full)) {
9796 an_10_100_val |= (1<<6);
9797 autoneg_val |= (1<<9 | 1<<12);
9798 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9801 if ((phy->speed_cap_mask &
9802 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9803 (phy->supported & SUPPORTED_10baseT_Half)) {
9804 an_10_100_val |= (1<<5);
9805 autoneg_val |= (1<<9 | 1<<12);
9806 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9810 /* Only 10/100 are allowed to work in FORCE mode */
9811 if ((phy->req_line_speed == SPEED_100) &&
9813 (SUPPORTED_100baseT_Half |
9814 SUPPORTED_100baseT_Full))) {
9815 autoneg_val |= (1<<13);
9816 /* Enabled AUTO-MDIX when autoneg is disabled */
9817 bnx2x_cl45_write(bp, phy,
9818 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9819 (1<<15 | 1<<9 | 7<<0));
9820 /* The PHY needs this set even for forced link. */
9821 an_10_100_val |= (1<<8) | (1<<7);
9822 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9824 if ((phy->req_line_speed == SPEED_10) &&
9826 (SUPPORTED_10baseT_Half |
9827 SUPPORTED_10baseT_Full))) {
9828 /* Enabled AUTO-MDIX when autoneg is disabled */
9829 bnx2x_cl45_write(bp, phy,
9830 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9831 (1<<15 | 1<<9 | 7<<0));
9832 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9835 bnx2x_cl45_write(bp, phy,
9836 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9839 if (phy->req_duplex == DUPLEX_FULL)
9840 autoneg_val |= (1<<8);
9842 /* Always write this if this is not 84833/4.
9843 * For 84833/4, write it only when it's a forced speed.
9845 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9846 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9847 ((autoneg_val & (1<<12)) == 0))
9848 bnx2x_cl45_write(bp, phy,
9850 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9852 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9853 (phy->speed_cap_mask &
9854 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9855 (phy->req_line_speed == SPEED_10000)) {
9856 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9857 /* Restart autoneg for 10G*/
9859 bnx2x_cl45_read_or_write(
9862 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9864 bnx2x_cl45_write(bp, phy,
9865 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9868 bnx2x_cl45_write(bp, phy,
9870 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9876 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9877 struct link_params *params,
9878 struct link_vars *vars)
9880 struct bnx2x *bp = params->bp;
9881 /* Restore normal power mode*/
9882 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9883 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9886 bnx2x_ext_phy_hw_reset(bp, params->port);
9887 bnx2x_wait_reset_complete(bp, phy, params);
9889 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9890 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9893 #define PHY84833_CMDHDLR_WAIT 300
9894 #define PHY84833_CMDHDLR_MAX_ARGS 5
9895 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9896 struct link_params *params, u16 fw_cmd,
9897 u16 cmd_args[], int argc)
9901 struct bnx2x *bp = params->bp;
9902 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9903 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9904 MDIO_84833_CMD_HDLR_STATUS,
9905 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9906 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9907 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9908 MDIO_84833_CMD_HDLR_STATUS, &val);
9909 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9911 usleep_range(1000, 2000);
9913 if (idx >= PHY84833_CMDHDLR_WAIT) {
9914 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9918 /* Prepare argument(s) and issue command */
9919 for (idx = 0; idx < argc; idx++) {
9920 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9921 MDIO_84833_CMD_HDLR_DATA1 + idx,
9924 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9925 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9926 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9927 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9928 MDIO_84833_CMD_HDLR_STATUS, &val);
9929 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9930 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9932 usleep_range(1000, 2000);
9934 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9935 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9936 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9939 /* Gather returning data */
9940 for (idx = 0; idx < argc; idx++) {
9941 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9942 MDIO_84833_CMD_HDLR_DATA1 + idx,
9945 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9946 MDIO_84833_CMD_HDLR_STATUS,
9947 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9951 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9952 struct link_params *params,
9953 struct link_vars *vars)
9956 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9958 struct bnx2x *bp = params->bp;
9960 /* Check for configuration. */
9961 pair_swap = REG_RD(bp, params->shmem_base +
9962 offsetof(struct shmem_region,
9963 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9964 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9969 /* Only the second argument is used for this command */
9970 data[1] = (u16)pair_swap;
9972 status = bnx2x_84833_cmd_hdlr(phy, params,
9973 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9975 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9980 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9981 u32 shmem_base_path[],
9987 if (CHIP_IS_E3(bp)) {
9988 /* Assume that these will be GPIOs, not EPIOs. */
9989 for (idx = 0; idx < 2; idx++) {
9990 /* Map config param to register bit. */
9991 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9992 offsetof(struct shmem_region,
9993 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9994 reset_pin[idx] = (reset_pin[idx] &
9995 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9996 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9997 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9998 reset_pin[idx] = (1 << reset_pin[idx]);
10000 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10002 /* E2, look from diff place of shmem. */
10003 for (idx = 0; idx < 2; idx++) {
10004 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10005 offsetof(struct shmem_region,
10006 dev_info.port_hw_config[0].default_cfg));
10007 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10008 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10009 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10010 reset_pin[idx] = (1 << reset_pin[idx]);
10012 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10015 return reset_gpios;
10018 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10019 struct link_params *params)
10021 struct bnx2x *bp = params->bp;
10023 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10024 offsetof(struct shmem2_region,
10025 other_shmem_base_addr));
10027 u32 shmem_base_path[2];
10029 /* Work around for 84833 LED failure inside RESET status */
10030 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10031 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10032 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10033 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10034 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10035 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10037 shmem_base_path[0] = params->shmem_base;
10038 shmem_base_path[1] = other_shmem_base_addr;
10040 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10043 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10045 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10051 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10052 struct link_params *params,
10053 struct link_vars *vars)
10056 struct bnx2x *bp = params->bp;
10059 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10061 /* Prevent Phy from working in EEE and advertising it */
10062 rc = bnx2x_84833_cmd_hdlr(phy, params,
10063 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10065 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10069 return bnx2x_eee_disable(phy, params, vars);
10072 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10073 struct link_params *params,
10074 struct link_vars *vars)
10077 struct bnx2x *bp = params->bp;
10080 rc = bnx2x_84833_cmd_hdlr(phy, params,
10081 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10083 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10087 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10090 #define PHY84833_CONSTANT_LATENCY 1193
10091 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10092 struct link_params *params,
10093 struct link_vars *vars)
10095 struct bnx2x *bp = params->bp;
10096 u8 port, initialize = 1;
10098 u32 actual_phy_selection;
10099 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10102 usleep_range(1000, 2000);
10104 if (!(CHIP_IS_E1x(bp)))
10105 port = BP_PATH(bp);
10107 port = params->port;
10109 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10110 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10111 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10115 bnx2x_cl45_write(bp, phy,
10117 MDIO_PMA_REG_CTRL, 0x8000);
10120 bnx2x_wait_reset_complete(bp, phy, params);
10122 /* Wait for GPHY to come out of reset */
10124 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10125 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10126 /* BCM84823 requires that XGXS links up first @ 10G for normal
10130 temp = vars->line_speed;
10131 vars->line_speed = SPEED_10000;
10132 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10133 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10134 vars->line_speed = temp;
10137 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10138 MDIO_CTL_REG_84823_MEDIA, &val);
10139 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10140 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10141 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10142 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10143 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10145 if (CHIP_IS_E3(bp)) {
10146 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10147 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10149 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10150 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10153 actual_phy_selection = bnx2x_phy_selection(params);
10155 switch (actual_phy_selection) {
10156 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10157 /* Do nothing. Essentially this is like the priority copper */
10159 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10160 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10162 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10163 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10165 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10166 /* Do nothing here. The first PHY won't be initialized at all */
10168 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10169 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10173 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10174 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10176 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10177 MDIO_CTL_REG_84823_MEDIA, val);
10178 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10179 params->multi_phy_config, val);
10181 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10182 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10183 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10185 /* Keep AutogrEEEn disabled. */
10188 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10189 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10190 rc = bnx2x_84833_cmd_hdlr(phy, params,
10191 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10192 PHY84833_CMDHDLR_MAX_ARGS);
10194 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10197 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10199 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10200 /* 84833 PHY has a better feature and doesn't need to support this. */
10201 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10202 u32 cms_enable = REG_RD(bp, params->shmem_base +
10203 offsetof(struct shmem_region,
10204 dev_info.port_hw_config[params->port].default_cfg)) &
10205 PORT_HW_CFG_ENABLE_CMS_MASK;
10207 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10208 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10210 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10212 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10213 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10214 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10217 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10218 MDIO_84833_TOP_CFG_FW_REV, &val);
10220 /* Configure EEE support */
10221 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10222 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10223 bnx2x_eee_has_cap(params)) {
10224 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10226 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10227 bnx2x_8483x_disable_eee(phy, params, vars);
10231 if ((phy->req_duplex == DUPLEX_FULL) &&
10232 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10233 (bnx2x_eee_calc_timer(params) ||
10234 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10235 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10237 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10239 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10243 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10246 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10247 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10248 /* Bring PHY out of super isolate mode as the final step. */
10249 bnx2x_cl45_read_and_write(bp, phy,
10251 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10252 (u16)~MDIO_84833_SUPER_ISOLATE);
10257 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10258 struct link_params *params,
10259 struct link_vars *vars)
10261 struct bnx2x *bp = params->bp;
10262 u16 val, val1, val2;
10266 /* Check 10G-BaseT link status */
10267 /* Check PMD signal ok */
10268 bnx2x_cl45_read(bp, phy,
10269 MDIO_AN_DEVAD, 0xFFFA, &val1);
10270 bnx2x_cl45_read(bp, phy,
10271 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10273 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10275 /* Check link 10G */
10276 if (val2 & (1<<11)) {
10277 vars->line_speed = SPEED_10000;
10278 vars->duplex = DUPLEX_FULL;
10280 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10281 } else { /* Check Legacy speed link */
10282 u16 legacy_status, legacy_speed;
10284 /* Enable expansion register 0x42 (Operation mode status) */
10285 bnx2x_cl45_write(bp, phy,
10287 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10289 /* Get legacy speed operation status */
10290 bnx2x_cl45_read(bp, phy,
10292 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10295 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10297 link_up = ((legacy_status & (1<<11)) == (1<<11));
10298 legacy_speed = (legacy_status & (3<<9));
10299 if (legacy_speed == (0<<9))
10300 vars->line_speed = SPEED_10;
10301 else if (legacy_speed == (1<<9))
10302 vars->line_speed = SPEED_100;
10303 else if (legacy_speed == (2<<9))
10304 vars->line_speed = SPEED_1000;
10305 else { /* Should not happen: Treat as link down */
10306 vars->line_speed = 0;
10311 if (legacy_status & (1<<8))
10312 vars->duplex = DUPLEX_FULL;
10314 vars->duplex = DUPLEX_HALF;
10317 "Link is up in %dMbps, is_duplex_full= %d\n",
10319 (vars->duplex == DUPLEX_FULL));
10320 /* Check legacy speed AN resolution */
10321 bnx2x_cl45_read(bp, phy,
10323 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10326 vars->link_status |=
10327 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10328 bnx2x_cl45_read(bp, phy,
10330 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10332 if ((val & (1<<0)) == 0)
10333 vars->link_status |=
10334 LINK_STATUS_PARALLEL_DETECTION_USED;
10338 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10340 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10342 /* Read LP advertised speeds */
10343 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10344 MDIO_AN_REG_CL37_FC_LP, &val);
10346 vars->link_status |=
10347 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10349 vars->link_status |=
10350 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10352 vars->link_status |=
10353 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10355 vars->link_status |=
10356 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10358 vars->link_status |=
10359 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10361 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10362 MDIO_AN_REG_1000T_STATUS, &val);
10365 vars->link_status |=
10366 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10368 vars->link_status |=
10369 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10371 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10372 MDIO_AN_REG_MASTER_STATUS, &val);
10375 vars->link_status |=
10376 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10378 /* Determine if EEE was negotiated */
10379 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10380 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10381 bnx2x_eee_an_resolve(phy, params, vars);
10387 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10391 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10392 status = bnx2x_format_ver(spirom_ver, str, len);
10396 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10397 struct link_params *params)
10399 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10400 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10401 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10402 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10405 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10406 struct link_params *params)
10408 bnx2x_cl45_write(params->bp, phy,
10409 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10410 bnx2x_cl45_write(params->bp, phy,
10411 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10414 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10415 struct link_params *params)
10417 struct bnx2x *bp = params->bp;
10421 if (!(CHIP_IS_E1x(bp)))
10422 port = BP_PATH(bp);
10424 port = params->port;
10426 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10427 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10428 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10431 bnx2x_cl45_read(bp, phy,
10433 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10434 val16 |= MDIO_84833_SUPER_ISOLATE;
10435 bnx2x_cl45_write(bp, phy,
10437 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10441 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10442 struct link_params *params, u8 mode)
10444 struct bnx2x *bp = params->bp;
10448 if (!(CHIP_IS_E1x(bp)))
10449 port = BP_PATH(bp);
10451 port = params->port;
10456 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10458 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10459 SHARED_HW_CFG_LED_EXTPHY1) {
10461 /* Set LED masks */
10462 bnx2x_cl45_write(bp, phy,
10464 MDIO_PMA_REG_8481_LED1_MASK,
10467 bnx2x_cl45_write(bp, phy,
10469 MDIO_PMA_REG_8481_LED2_MASK,
10472 bnx2x_cl45_write(bp, phy,
10474 MDIO_PMA_REG_8481_LED3_MASK,
10477 bnx2x_cl45_write(bp, phy,
10479 MDIO_PMA_REG_8481_LED5_MASK,
10483 bnx2x_cl45_write(bp, phy,
10485 MDIO_PMA_REG_8481_LED1_MASK,
10489 case LED_MODE_FRONT_PANEL_OFF:
10491 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10494 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10495 SHARED_HW_CFG_LED_EXTPHY1) {
10497 /* Set LED masks */
10498 bnx2x_cl45_write(bp, phy,
10500 MDIO_PMA_REG_8481_LED1_MASK,
10503 bnx2x_cl45_write(bp, phy,
10505 MDIO_PMA_REG_8481_LED2_MASK,
10508 bnx2x_cl45_write(bp, phy,
10510 MDIO_PMA_REG_8481_LED3_MASK,
10513 bnx2x_cl45_write(bp, phy,
10515 MDIO_PMA_REG_8481_LED5_MASK,
10519 bnx2x_cl45_write(bp, phy,
10521 MDIO_PMA_REG_8481_LED1_MASK,
10524 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10525 /* Disable MI_INT interrupt before setting LED4
10526 * source to constant off.
10528 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10531 params->link_flags |=
10532 LINK_FLAGS_INT_DISABLED;
10536 NIG_REG_MASK_INTERRUPT_PORT0 +
10540 bnx2x_cl45_write(bp, phy,
10542 MDIO_PMA_REG_8481_SIGNAL_MASK,
10549 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10551 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10552 SHARED_HW_CFG_LED_EXTPHY1) {
10553 /* Set control reg */
10554 bnx2x_cl45_read(bp, phy,
10556 MDIO_PMA_REG_8481_LINK_SIGNAL,
10561 bnx2x_cl45_write(bp, phy,
10563 MDIO_PMA_REG_8481_LINK_SIGNAL,
10566 /* Set LED masks */
10567 bnx2x_cl45_write(bp, phy,
10569 MDIO_PMA_REG_8481_LED1_MASK,
10572 bnx2x_cl45_write(bp, phy,
10574 MDIO_PMA_REG_8481_LED2_MASK,
10577 bnx2x_cl45_write(bp, phy,
10579 MDIO_PMA_REG_8481_LED3_MASK,
10582 bnx2x_cl45_write(bp, phy,
10584 MDIO_PMA_REG_8481_LED5_MASK,
10587 bnx2x_cl45_write(bp, phy,
10589 MDIO_PMA_REG_8481_LED1_MASK,
10592 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10593 /* Disable MI_INT interrupt before setting LED4
10594 * source to constant on.
10596 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10599 params->link_flags |=
10600 LINK_FLAGS_INT_DISABLED;
10604 NIG_REG_MASK_INTERRUPT_PORT0 +
10608 bnx2x_cl45_write(bp, phy,
10610 MDIO_PMA_REG_8481_SIGNAL_MASK,
10616 case LED_MODE_OPER:
10618 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10620 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10621 SHARED_HW_CFG_LED_EXTPHY1) {
10623 /* Set control reg */
10624 bnx2x_cl45_read(bp, phy,
10626 MDIO_PMA_REG_8481_LINK_SIGNAL,
10630 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10631 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10632 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10633 bnx2x_cl45_write(bp, phy,
10635 MDIO_PMA_REG_8481_LINK_SIGNAL,
10639 /* Set LED masks */
10640 bnx2x_cl45_write(bp, phy,
10642 MDIO_PMA_REG_8481_LED1_MASK,
10645 bnx2x_cl45_write(bp, phy,
10647 MDIO_PMA_REG_8481_LED2_MASK,
10650 bnx2x_cl45_write(bp, phy,
10652 MDIO_PMA_REG_8481_LED3_MASK,
10655 bnx2x_cl45_write(bp, phy,
10657 MDIO_PMA_REG_8481_LED5_MASK,
10661 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10662 * sources are all wired through LED1, rather than only
10663 * 10G in other modes.
10665 val = ((params->hw_led_mode <<
10666 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10667 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10669 bnx2x_cl45_write(bp, phy,
10671 MDIO_PMA_REG_8481_LED1_MASK,
10674 /* Tell LED3 to blink on source */
10675 bnx2x_cl45_read(bp, phy,
10677 MDIO_PMA_REG_8481_LINK_SIGNAL,
10680 val |= (1<<6); /* A83B[8:6]= 1 */
10681 bnx2x_cl45_write(bp, phy,
10683 MDIO_PMA_REG_8481_LINK_SIGNAL,
10686 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10687 /* Restore LED4 source to external link,
10688 * and re-enable interrupts.
10690 bnx2x_cl45_write(bp, phy,
10692 MDIO_PMA_REG_8481_SIGNAL_MASK,
10694 if (params->link_flags &
10695 LINK_FLAGS_INT_DISABLED) {
10696 bnx2x_link_int_enable(params);
10697 params->link_flags &=
10698 ~LINK_FLAGS_INT_DISABLED;
10705 /* This is a workaround for E3+84833 until autoneg
10706 * restart is fixed in f/w
10708 if (CHIP_IS_E3(bp)) {
10709 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10710 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10714 /******************************************************************/
10715 /* 54618SE PHY SECTION */
10716 /******************************************************************/
10717 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10718 struct link_params *params,
10721 struct bnx2x *bp = params->bp;
10725 /* Configure LED4: set to INTR (0x6). */
10726 /* Accessing shadow register 0xe. */
10727 bnx2x_cl22_write(bp, phy,
10728 MDIO_REG_GPHY_SHADOW,
10729 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10730 bnx2x_cl22_read(bp, phy,
10731 MDIO_REG_GPHY_SHADOW,
10733 temp &= ~(0xf << 4);
10734 temp |= (0x6 << 4);
10735 bnx2x_cl22_write(bp, phy,
10736 MDIO_REG_GPHY_SHADOW,
10737 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10738 /* Configure INTR based on link status change. */
10739 bnx2x_cl22_write(bp, phy,
10740 MDIO_REG_INTR_MASK,
10741 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10746 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10747 struct link_params *params,
10748 struct link_vars *vars)
10750 struct bnx2x *bp = params->bp;
10752 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10755 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10756 usleep_range(1000, 2000);
10758 /* This works with E3 only, no need to check the chip
10759 * before determining the port.
10761 port = params->port;
10763 cfg_pin = (REG_RD(bp, params->shmem_base +
10764 offsetof(struct shmem_region,
10765 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10766 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10767 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10769 /* Drive pin high to bring the GPHY out of reset. */
10770 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10772 /* wait for GPHY to reset */
10776 bnx2x_cl22_write(bp, phy,
10777 MDIO_PMA_REG_CTRL, 0x8000);
10778 bnx2x_wait_reset_complete(bp, phy, params);
10780 /* Wait for GPHY to reset */
10784 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10785 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10786 bnx2x_cl22_write(bp, phy,
10787 MDIO_REG_GPHY_SHADOW,
10788 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10789 bnx2x_cl22_read(bp, phy,
10790 MDIO_REG_GPHY_SHADOW,
10792 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10793 bnx2x_cl22_write(bp, phy,
10794 MDIO_REG_GPHY_SHADOW,
10795 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10798 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10799 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10801 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10802 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10803 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10805 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10806 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10807 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10809 /* Read all advertisement */
10810 bnx2x_cl22_read(bp, phy,
10814 bnx2x_cl22_read(bp, phy,
10818 bnx2x_cl22_read(bp, phy,
10822 /* Disable forced speed */
10823 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10824 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10827 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10828 (phy->speed_cap_mask &
10829 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10830 (phy->req_line_speed == SPEED_1000)) {
10831 an_1000_val |= (1<<8);
10832 autoneg_val |= (1<<9 | 1<<12);
10833 if (phy->req_duplex == DUPLEX_FULL)
10834 an_1000_val |= (1<<9);
10835 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10837 an_1000_val &= ~((1<<8) | (1<<9));
10839 bnx2x_cl22_write(bp, phy,
10842 bnx2x_cl22_read(bp, phy,
10846 /* Set 100 speed advertisement */
10847 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10848 (phy->speed_cap_mask &
10849 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10850 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10851 an_10_100_val |= (1<<7);
10852 /* Enable autoneg and restart autoneg for legacy speeds */
10853 autoneg_val |= (1<<9 | 1<<12);
10855 if (phy->req_duplex == DUPLEX_FULL)
10856 an_10_100_val |= (1<<8);
10857 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10860 /* Set 10 speed advertisement */
10861 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10862 (phy->speed_cap_mask &
10863 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10864 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10865 an_10_100_val |= (1<<5);
10866 autoneg_val |= (1<<9 | 1<<12);
10867 if (phy->req_duplex == DUPLEX_FULL)
10868 an_10_100_val |= (1<<6);
10869 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10872 /* Only 10/100 are allowed to work in FORCE mode */
10873 if (phy->req_line_speed == SPEED_100) {
10874 autoneg_val |= (1<<13);
10875 /* Enabled AUTO-MDIX when autoneg is disabled */
10876 bnx2x_cl22_write(bp, phy,
10878 (1<<15 | 1<<9 | 7<<0));
10879 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10881 if (phy->req_line_speed == SPEED_10) {
10882 /* Enabled AUTO-MDIX when autoneg is disabled */
10883 bnx2x_cl22_write(bp, phy,
10885 (1<<15 | 1<<9 | 7<<0));
10886 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10889 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10892 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10893 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10894 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10895 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10897 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10899 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10901 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10902 bnx2x_eee_disable(phy, params, vars);
10903 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10904 (phy->req_duplex == DUPLEX_FULL) &&
10905 (bnx2x_eee_calc_timer(params) ||
10906 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10907 /* Need to advertise EEE only when requested,
10908 * and either no LPI assertion was requested,
10909 * or it was requested and a valid timer was set.
10910 * Also notice full duplex is required for EEE.
10912 bnx2x_eee_advertise(phy, params, vars,
10915 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10916 bnx2x_eee_disable(phy, params, vars);
10919 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10920 SHMEM_EEE_SUPPORTED_SHIFT;
10922 if (phy->flags & FLAGS_EEE) {
10923 /* Handle legacy auto-grEEEn */
10924 if (params->feature_config_flags &
10925 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10927 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10930 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10932 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10933 MDIO_AN_REG_EEE_ADV, temp);
10937 bnx2x_cl22_write(bp, phy,
10939 an_10_100_val | fc_val);
10941 if (phy->req_duplex == DUPLEX_FULL)
10942 autoneg_val |= (1<<8);
10944 bnx2x_cl22_write(bp, phy,
10945 MDIO_PMA_REG_CTRL, autoneg_val);
10951 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10952 struct link_params *params, u8 mode)
10954 struct bnx2x *bp = params->bp;
10957 bnx2x_cl22_write(bp, phy,
10958 MDIO_REG_GPHY_SHADOW,
10959 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10960 bnx2x_cl22_read(bp, phy,
10961 MDIO_REG_GPHY_SHADOW,
10965 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10967 case LED_MODE_FRONT_PANEL_OFF:
10971 case LED_MODE_OPER:
10980 bnx2x_cl22_write(bp, phy,
10981 MDIO_REG_GPHY_SHADOW,
10982 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10987 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10988 struct link_params *params)
10990 struct bnx2x *bp = params->bp;
10994 /* In case of no EPIO routed to reset the GPHY, put it
10995 * in low power mode.
10997 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10998 /* This works with E3 only, no need to check the chip
10999 * before determining the port.
11001 port = params->port;
11002 cfg_pin = (REG_RD(bp, params->shmem_base +
11003 offsetof(struct shmem_region,
11004 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11005 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11006 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11008 /* Drive pin low to put GPHY in reset. */
11009 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11012 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11013 struct link_params *params,
11014 struct link_vars *vars)
11016 struct bnx2x *bp = params->bp;
11019 u16 legacy_status, legacy_speed;
11021 /* Get speed operation status */
11022 bnx2x_cl22_read(bp, phy,
11023 MDIO_REG_GPHY_AUX_STATUS,
11025 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11027 /* Read status to clear the PHY interrupt. */
11028 bnx2x_cl22_read(bp, phy,
11029 MDIO_REG_INTR_STATUS,
11032 link_up = ((legacy_status & (1<<2)) == (1<<2));
11035 legacy_speed = (legacy_status & (7<<8));
11036 if (legacy_speed == (7<<8)) {
11037 vars->line_speed = SPEED_1000;
11038 vars->duplex = DUPLEX_FULL;
11039 } else if (legacy_speed == (6<<8)) {
11040 vars->line_speed = SPEED_1000;
11041 vars->duplex = DUPLEX_HALF;
11042 } else if (legacy_speed == (5<<8)) {
11043 vars->line_speed = SPEED_100;
11044 vars->duplex = DUPLEX_FULL;
11046 /* Omitting 100Base-T4 for now */
11047 else if (legacy_speed == (3<<8)) {
11048 vars->line_speed = SPEED_100;
11049 vars->duplex = DUPLEX_HALF;
11050 } else if (legacy_speed == (2<<8)) {
11051 vars->line_speed = SPEED_10;
11052 vars->duplex = DUPLEX_FULL;
11053 } else if (legacy_speed == (1<<8)) {
11054 vars->line_speed = SPEED_10;
11055 vars->duplex = DUPLEX_HALF;
11056 } else /* Should not happen */
11057 vars->line_speed = 0;
11060 "Link is up in %dMbps, is_duplex_full= %d\n",
11062 (vars->duplex == DUPLEX_FULL));
11064 /* Check legacy speed AN resolution */
11065 bnx2x_cl22_read(bp, phy,
11069 vars->link_status |=
11070 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11071 bnx2x_cl22_read(bp, phy,
11074 if ((val & (1<<0)) == 0)
11075 vars->link_status |=
11076 LINK_STATUS_PARALLEL_DETECTION_USED;
11078 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11081 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11083 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11084 /* Report LP advertised speeds */
11085 bnx2x_cl22_read(bp, phy, 0x5, &val);
11088 vars->link_status |=
11089 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11091 vars->link_status |=
11092 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11094 vars->link_status |=
11095 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11097 vars->link_status |=
11098 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11100 vars->link_status |=
11101 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11103 bnx2x_cl22_read(bp, phy, 0xa, &val);
11105 vars->link_status |=
11106 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11108 vars->link_status |=
11109 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11111 if ((phy->flags & FLAGS_EEE) &&
11112 bnx2x_eee_has_cap(params))
11113 bnx2x_eee_an_resolve(phy, params, vars);
11119 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11120 struct link_params *params)
11122 struct bnx2x *bp = params->bp;
11124 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11126 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11128 /* Enable master/slave manual mmode and set to master */
11129 /* mii write 9 [bits set 11 12] */
11130 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11132 /* forced 1G and disable autoneg */
11133 /* set val [mii read 0] */
11134 /* set val [expr $val & [bits clear 6 12 13]] */
11135 /* set val [expr $val | [bits set 6 8]] */
11136 /* mii write 0 $val */
11137 bnx2x_cl22_read(bp, phy, 0x00, &val);
11138 val &= ~((1<<6) | (1<<12) | (1<<13));
11139 val |= (1<<6) | (1<<8);
11140 bnx2x_cl22_write(bp, phy, 0x00, val);
11142 /* Set external loopback and Tx using 6dB coding */
11143 /* mii write 0x18 7 */
11144 /* set val [mii read 0x18] */
11145 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11146 bnx2x_cl22_write(bp, phy, 0x18, 7);
11147 bnx2x_cl22_read(bp, phy, 0x18, &val);
11148 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11150 /* This register opens the gate for the UMAC despite its name */
11151 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11153 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11154 * length used by the MAC receive logic to check frames.
11156 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11159 /******************************************************************/
11160 /* SFX7101 PHY SECTION */
11161 /******************************************************************/
11162 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11163 struct link_params *params)
11165 struct bnx2x *bp = params->bp;
11166 /* SFX7101_XGXS_TEST1 */
11167 bnx2x_cl45_write(bp, phy,
11168 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11171 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11172 struct link_params *params,
11173 struct link_vars *vars)
11175 u16 fw_ver1, fw_ver2, val;
11176 struct bnx2x *bp = params->bp;
11177 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11179 /* Restore normal power mode*/
11180 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11181 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11183 bnx2x_ext_phy_hw_reset(bp, params->port);
11184 bnx2x_wait_reset_complete(bp, phy, params);
11186 bnx2x_cl45_write(bp, phy,
11187 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11188 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11189 bnx2x_cl45_write(bp, phy,
11190 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11192 bnx2x_ext_phy_set_pause(params, phy, vars);
11193 /* Restart autoneg */
11194 bnx2x_cl45_read(bp, phy,
11195 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11197 bnx2x_cl45_write(bp, phy,
11198 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11200 /* Save spirom version */
11201 bnx2x_cl45_read(bp, phy,
11202 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11204 bnx2x_cl45_read(bp, phy,
11205 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11206 bnx2x_save_spirom_version(bp, params->port,
11207 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11211 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11212 struct link_params *params,
11213 struct link_vars *vars)
11215 struct bnx2x *bp = params->bp;
11218 bnx2x_cl45_read(bp, phy,
11219 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11220 bnx2x_cl45_read(bp, phy,
11221 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11222 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11224 bnx2x_cl45_read(bp, phy,
11225 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11226 bnx2x_cl45_read(bp, phy,
11227 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11228 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11230 link_up = ((val1 & 4) == 4);
11231 /* If link is up print the AN outcome of the SFX7101 PHY */
11233 bnx2x_cl45_read(bp, phy,
11234 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11236 vars->line_speed = SPEED_10000;
11237 vars->duplex = DUPLEX_FULL;
11238 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11239 val2, (val2 & (1<<14)));
11240 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11241 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11243 /* Read LP advertised speeds */
11244 if (val2 & (1<<11))
11245 vars->link_status |=
11246 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11251 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11255 str[0] = (spirom_ver & 0xFF);
11256 str[1] = (spirom_ver & 0xFF00) >> 8;
11257 str[2] = (spirom_ver & 0xFF0000) >> 16;
11258 str[3] = (spirom_ver & 0xFF000000) >> 24;
11264 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11268 bnx2x_cl45_read(bp, phy,
11270 MDIO_PMA_REG_7101_RESET, &val);
11272 for (cnt = 0; cnt < 10; cnt++) {
11274 /* Writes a self-clearing reset */
11275 bnx2x_cl45_write(bp, phy,
11277 MDIO_PMA_REG_7101_RESET,
11279 /* Wait for clear */
11280 bnx2x_cl45_read(bp, phy,
11282 MDIO_PMA_REG_7101_RESET, &val);
11284 if ((val & (1<<15)) == 0)
11289 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11290 struct link_params *params) {
11291 /* Low power mode is controlled by GPIO 2 */
11292 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11293 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11294 /* The PHY reset is controlled by GPIO 1 */
11295 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11296 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11299 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11300 struct link_params *params, u8 mode)
11303 struct bnx2x *bp = params->bp;
11305 case LED_MODE_FRONT_PANEL_OFF:
11312 case LED_MODE_OPER:
11316 bnx2x_cl45_write(bp, phy,
11318 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11322 /******************************************************************/
11323 /* STATIC PHY DECLARATION */
11324 /******************************************************************/
11326 static const struct bnx2x_phy phy_null = {
11327 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11330 .flags = FLAGS_INIT_XGXS_FIRST,
11331 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11332 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11335 .media_type = ETH_PHY_NOT_PRESENT,
11337 .req_flow_ctrl = 0,
11338 .req_line_speed = 0,
11339 .speed_cap_mask = 0,
11342 .config_init = (config_init_t)NULL,
11343 .read_status = (read_status_t)NULL,
11344 .link_reset = (link_reset_t)NULL,
11345 .config_loopback = (config_loopback_t)NULL,
11346 .format_fw_ver = (format_fw_ver_t)NULL,
11347 .hw_reset = (hw_reset_t)NULL,
11348 .set_link_led = (set_link_led_t)NULL,
11349 .phy_specific_func = (phy_specific_func_t)NULL
11352 static const struct bnx2x_phy phy_serdes = {
11353 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11357 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11358 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11360 .supported = (SUPPORTED_10baseT_Half |
11361 SUPPORTED_10baseT_Full |
11362 SUPPORTED_100baseT_Half |
11363 SUPPORTED_100baseT_Full |
11364 SUPPORTED_1000baseT_Full |
11365 SUPPORTED_2500baseX_Full |
11367 SUPPORTED_Autoneg |
11369 SUPPORTED_Asym_Pause),
11370 .media_type = ETH_PHY_BASE_T,
11372 .req_flow_ctrl = 0,
11373 .req_line_speed = 0,
11374 .speed_cap_mask = 0,
11377 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11378 .read_status = (read_status_t)bnx2x_link_settings_status,
11379 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11380 .config_loopback = (config_loopback_t)NULL,
11381 .format_fw_ver = (format_fw_ver_t)NULL,
11382 .hw_reset = (hw_reset_t)NULL,
11383 .set_link_led = (set_link_led_t)NULL,
11384 .phy_specific_func = (phy_specific_func_t)NULL
11387 static const struct bnx2x_phy phy_xgxs = {
11388 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11392 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11393 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11395 .supported = (SUPPORTED_10baseT_Half |
11396 SUPPORTED_10baseT_Full |
11397 SUPPORTED_100baseT_Half |
11398 SUPPORTED_100baseT_Full |
11399 SUPPORTED_1000baseT_Full |
11400 SUPPORTED_2500baseX_Full |
11401 SUPPORTED_10000baseT_Full |
11403 SUPPORTED_Autoneg |
11405 SUPPORTED_Asym_Pause),
11406 .media_type = ETH_PHY_CX4,
11408 .req_flow_ctrl = 0,
11409 .req_line_speed = 0,
11410 .speed_cap_mask = 0,
11413 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11414 .read_status = (read_status_t)bnx2x_link_settings_status,
11415 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11416 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11417 .format_fw_ver = (format_fw_ver_t)NULL,
11418 .hw_reset = (hw_reset_t)NULL,
11419 .set_link_led = (set_link_led_t)NULL,
11420 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11422 static const struct bnx2x_phy phy_warpcore = {
11423 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11426 .flags = FLAGS_TX_ERROR_CHECK,
11427 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11428 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11430 .supported = (SUPPORTED_10baseT_Half |
11431 SUPPORTED_10baseT_Full |
11432 SUPPORTED_100baseT_Half |
11433 SUPPORTED_100baseT_Full |
11434 SUPPORTED_1000baseT_Full |
11435 SUPPORTED_10000baseT_Full |
11436 SUPPORTED_20000baseKR2_Full |
11437 SUPPORTED_20000baseMLD2_Full |
11439 SUPPORTED_Autoneg |
11441 SUPPORTED_Asym_Pause),
11442 .media_type = ETH_PHY_UNSPECIFIED,
11444 .req_flow_ctrl = 0,
11445 .req_line_speed = 0,
11446 .speed_cap_mask = 0,
11447 /* req_duplex = */0,
11449 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11450 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11451 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11452 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11453 .format_fw_ver = (format_fw_ver_t)NULL,
11454 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11455 .set_link_led = (set_link_led_t)NULL,
11456 .phy_specific_func = (phy_specific_func_t)NULL
11460 static const struct bnx2x_phy phy_7101 = {
11461 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11464 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11465 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11466 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11468 .supported = (SUPPORTED_10000baseT_Full |
11470 SUPPORTED_Autoneg |
11472 SUPPORTED_Asym_Pause),
11473 .media_type = ETH_PHY_BASE_T,
11475 .req_flow_ctrl = 0,
11476 .req_line_speed = 0,
11477 .speed_cap_mask = 0,
11480 .config_init = (config_init_t)bnx2x_7101_config_init,
11481 .read_status = (read_status_t)bnx2x_7101_read_status,
11482 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11483 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11484 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11485 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11486 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11487 .phy_specific_func = (phy_specific_func_t)NULL
11489 static const struct bnx2x_phy phy_8073 = {
11490 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11494 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11495 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11497 .supported = (SUPPORTED_10000baseT_Full |
11498 SUPPORTED_2500baseX_Full |
11499 SUPPORTED_1000baseT_Full |
11501 SUPPORTED_Autoneg |
11503 SUPPORTED_Asym_Pause),
11504 .media_type = ETH_PHY_KR,
11506 .req_flow_ctrl = 0,
11507 .req_line_speed = 0,
11508 .speed_cap_mask = 0,
11511 .config_init = (config_init_t)bnx2x_8073_config_init,
11512 .read_status = (read_status_t)bnx2x_8073_read_status,
11513 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11514 .config_loopback = (config_loopback_t)NULL,
11515 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11516 .hw_reset = (hw_reset_t)NULL,
11517 .set_link_led = (set_link_led_t)NULL,
11518 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11520 static const struct bnx2x_phy phy_8705 = {
11521 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11524 .flags = FLAGS_INIT_XGXS_FIRST,
11525 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11526 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11528 .supported = (SUPPORTED_10000baseT_Full |
11531 SUPPORTED_Asym_Pause),
11532 .media_type = ETH_PHY_XFP_FIBER,
11534 .req_flow_ctrl = 0,
11535 .req_line_speed = 0,
11536 .speed_cap_mask = 0,
11539 .config_init = (config_init_t)bnx2x_8705_config_init,
11540 .read_status = (read_status_t)bnx2x_8705_read_status,
11541 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11542 .config_loopback = (config_loopback_t)NULL,
11543 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11544 .hw_reset = (hw_reset_t)NULL,
11545 .set_link_led = (set_link_led_t)NULL,
11546 .phy_specific_func = (phy_specific_func_t)NULL
11548 static const struct bnx2x_phy phy_8706 = {
11549 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11552 .flags = FLAGS_INIT_XGXS_FIRST,
11553 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11554 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11556 .supported = (SUPPORTED_10000baseT_Full |
11557 SUPPORTED_1000baseT_Full |
11560 SUPPORTED_Asym_Pause),
11561 .media_type = ETH_PHY_SFPP_10G_FIBER,
11563 .req_flow_ctrl = 0,
11564 .req_line_speed = 0,
11565 .speed_cap_mask = 0,
11568 .config_init = (config_init_t)bnx2x_8706_config_init,
11569 .read_status = (read_status_t)bnx2x_8706_read_status,
11570 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11571 .config_loopback = (config_loopback_t)NULL,
11572 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11573 .hw_reset = (hw_reset_t)NULL,
11574 .set_link_led = (set_link_led_t)NULL,
11575 .phy_specific_func = (phy_specific_func_t)NULL
11578 static const struct bnx2x_phy phy_8726 = {
11579 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11582 .flags = (FLAGS_INIT_XGXS_FIRST |
11583 FLAGS_TX_ERROR_CHECK),
11584 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11585 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11587 .supported = (SUPPORTED_10000baseT_Full |
11588 SUPPORTED_1000baseT_Full |
11589 SUPPORTED_Autoneg |
11592 SUPPORTED_Asym_Pause),
11593 .media_type = ETH_PHY_NOT_PRESENT,
11595 .req_flow_ctrl = 0,
11596 .req_line_speed = 0,
11597 .speed_cap_mask = 0,
11600 .config_init = (config_init_t)bnx2x_8726_config_init,
11601 .read_status = (read_status_t)bnx2x_8726_read_status,
11602 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11603 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11604 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11605 .hw_reset = (hw_reset_t)NULL,
11606 .set_link_led = (set_link_led_t)NULL,
11607 .phy_specific_func = (phy_specific_func_t)NULL
11610 static const struct bnx2x_phy phy_8727 = {
11611 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11614 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11615 FLAGS_TX_ERROR_CHECK),
11616 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11617 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11619 .supported = (SUPPORTED_10000baseT_Full |
11620 SUPPORTED_1000baseT_Full |
11623 SUPPORTED_Asym_Pause),
11624 .media_type = ETH_PHY_NOT_PRESENT,
11626 .req_flow_ctrl = 0,
11627 .req_line_speed = 0,
11628 .speed_cap_mask = 0,
11631 .config_init = (config_init_t)bnx2x_8727_config_init,
11632 .read_status = (read_status_t)bnx2x_8727_read_status,
11633 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11634 .config_loopback = (config_loopback_t)NULL,
11635 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11636 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11637 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11638 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11640 static const struct bnx2x_phy phy_8481 = {
11641 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11644 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11645 FLAGS_REARM_LATCH_SIGNAL,
11646 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11647 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11649 .supported = (SUPPORTED_10baseT_Half |
11650 SUPPORTED_10baseT_Full |
11651 SUPPORTED_100baseT_Half |
11652 SUPPORTED_100baseT_Full |
11653 SUPPORTED_1000baseT_Full |
11654 SUPPORTED_10000baseT_Full |
11656 SUPPORTED_Autoneg |
11658 SUPPORTED_Asym_Pause),
11659 .media_type = ETH_PHY_BASE_T,
11661 .req_flow_ctrl = 0,
11662 .req_line_speed = 0,
11663 .speed_cap_mask = 0,
11666 .config_init = (config_init_t)bnx2x_8481_config_init,
11667 .read_status = (read_status_t)bnx2x_848xx_read_status,
11668 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11669 .config_loopback = (config_loopback_t)NULL,
11670 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11671 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11672 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11673 .phy_specific_func = (phy_specific_func_t)NULL
11676 static const struct bnx2x_phy phy_84823 = {
11677 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11680 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11681 FLAGS_REARM_LATCH_SIGNAL |
11682 FLAGS_TX_ERROR_CHECK),
11683 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11684 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11686 .supported = (SUPPORTED_10baseT_Half |
11687 SUPPORTED_10baseT_Full |
11688 SUPPORTED_100baseT_Half |
11689 SUPPORTED_100baseT_Full |
11690 SUPPORTED_1000baseT_Full |
11691 SUPPORTED_10000baseT_Full |
11693 SUPPORTED_Autoneg |
11695 SUPPORTED_Asym_Pause),
11696 .media_type = ETH_PHY_BASE_T,
11698 .req_flow_ctrl = 0,
11699 .req_line_speed = 0,
11700 .speed_cap_mask = 0,
11703 .config_init = (config_init_t)bnx2x_848x3_config_init,
11704 .read_status = (read_status_t)bnx2x_848xx_read_status,
11705 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11706 .config_loopback = (config_loopback_t)NULL,
11707 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11708 .hw_reset = (hw_reset_t)NULL,
11709 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11710 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11713 static const struct bnx2x_phy phy_84833 = {
11714 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11717 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11718 FLAGS_REARM_LATCH_SIGNAL |
11719 FLAGS_TX_ERROR_CHECK),
11720 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11721 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11723 .supported = (SUPPORTED_100baseT_Half |
11724 SUPPORTED_100baseT_Full |
11725 SUPPORTED_1000baseT_Full |
11726 SUPPORTED_10000baseT_Full |
11728 SUPPORTED_Autoneg |
11730 SUPPORTED_Asym_Pause),
11731 .media_type = ETH_PHY_BASE_T,
11733 .req_flow_ctrl = 0,
11734 .req_line_speed = 0,
11735 .speed_cap_mask = 0,
11738 .config_init = (config_init_t)bnx2x_848x3_config_init,
11739 .read_status = (read_status_t)bnx2x_848xx_read_status,
11740 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11741 .config_loopback = (config_loopback_t)NULL,
11742 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11743 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11744 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11745 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11748 static const struct bnx2x_phy phy_84834 = {
11749 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11752 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11753 FLAGS_REARM_LATCH_SIGNAL,
11754 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11755 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11757 .supported = (SUPPORTED_100baseT_Half |
11758 SUPPORTED_100baseT_Full |
11759 SUPPORTED_1000baseT_Full |
11760 SUPPORTED_10000baseT_Full |
11762 SUPPORTED_Autoneg |
11764 SUPPORTED_Asym_Pause),
11765 .media_type = ETH_PHY_BASE_T,
11767 .req_flow_ctrl = 0,
11768 .req_line_speed = 0,
11769 .speed_cap_mask = 0,
11772 .config_init = (config_init_t)bnx2x_848x3_config_init,
11773 .read_status = (read_status_t)bnx2x_848xx_read_status,
11774 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11775 .config_loopback = (config_loopback_t)NULL,
11776 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11777 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11778 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11779 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11782 static const struct bnx2x_phy phy_54618se = {
11783 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11786 .flags = FLAGS_INIT_XGXS_FIRST,
11787 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11788 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11790 .supported = (SUPPORTED_10baseT_Half |
11791 SUPPORTED_10baseT_Full |
11792 SUPPORTED_100baseT_Half |
11793 SUPPORTED_100baseT_Full |
11794 SUPPORTED_1000baseT_Full |
11796 SUPPORTED_Autoneg |
11798 SUPPORTED_Asym_Pause),
11799 .media_type = ETH_PHY_BASE_T,
11801 .req_flow_ctrl = 0,
11802 .req_line_speed = 0,
11803 .speed_cap_mask = 0,
11804 /* req_duplex = */0,
11806 .config_init = (config_init_t)bnx2x_54618se_config_init,
11807 .read_status = (read_status_t)bnx2x_54618se_read_status,
11808 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11809 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11810 .format_fw_ver = (format_fw_ver_t)NULL,
11811 .hw_reset = (hw_reset_t)NULL,
11812 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11813 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11815 /*****************************************************************/
11817 /* Populate the phy according. Main function: bnx2x_populate_phy */
11819 /*****************************************************************/
11821 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11822 struct bnx2x_phy *phy, u8 port,
11825 /* Get the 4 lanes xgxs config rx and tx */
11826 u32 rx = 0, tx = 0, i;
11827 for (i = 0; i < 2; i++) {
11828 /* INT_PHY and EXT_PHY1 share the same value location in
11829 * the shmem. When num_phys is greater than 1, than this value
11830 * applies only to EXT_PHY1
11832 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11833 rx = REG_RD(bp, shmem_base +
11834 offsetof(struct shmem_region,
11835 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11837 tx = REG_RD(bp, shmem_base +
11838 offsetof(struct shmem_region,
11839 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11841 rx = REG_RD(bp, shmem_base +
11842 offsetof(struct shmem_region,
11843 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11845 tx = REG_RD(bp, shmem_base +
11846 offsetof(struct shmem_region,
11847 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11850 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11851 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11853 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11854 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11858 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11859 u8 phy_index, u8 port)
11861 u32 ext_phy_config = 0;
11862 switch (phy_index) {
11864 ext_phy_config = REG_RD(bp, shmem_base +
11865 offsetof(struct shmem_region,
11866 dev_info.port_hw_config[port].external_phy_config));
11869 ext_phy_config = REG_RD(bp, shmem_base +
11870 offsetof(struct shmem_region,
11871 dev_info.port_hw_config[port].external_phy_config2));
11874 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11878 return ext_phy_config;
11880 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11881 struct bnx2x_phy *phy)
11885 u32 switch_cfg = (REG_RD(bp, shmem_base +
11886 offsetof(struct shmem_region,
11887 dev_info.port_feature_config[port].link_config)) &
11888 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11889 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11890 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11892 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11893 if (USES_WARPCORE(bp)) {
11895 phy_addr = REG_RD(bp,
11896 MISC_REG_WC0_CTRL_PHY_ADDR);
11897 *phy = phy_warpcore;
11898 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11899 phy->flags |= FLAGS_4_PORT_MODE;
11901 phy->flags &= ~FLAGS_4_PORT_MODE;
11902 /* Check Dual mode */
11903 serdes_net_if = (REG_RD(bp, shmem_base +
11904 offsetof(struct shmem_region, dev_info.
11905 port_hw_config[port].default_cfg)) &
11906 PORT_HW_CFG_NET_SERDES_IF_MASK);
11907 /* Set the appropriate supported and flags indications per
11908 * interface type of the chip
11910 switch (serdes_net_if) {
11911 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11912 phy->supported &= (SUPPORTED_10baseT_Half |
11913 SUPPORTED_10baseT_Full |
11914 SUPPORTED_100baseT_Half |
11915 SUPPORTED_100baseT_Full |
11916 SUPPORTED_1000baseT_Full |
11918 SUPPORTED_Autoneg |
11920 SUPPORTED_Asym_Pause);
11921 phy->media_type = ETH_PHY_BASE_T;
11923 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11924 phy->supported &= (SUPPORTED_1000baseT_Full |
11925 SUPPORTED_10000baseT_Full |
11928 SUPPORTED_Asym_Pause);
11929 phy->media_type = ETH_PHY_XFP_FIBER;
11931 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11932 phy->supported &= (SUPPORTED_1000baseT_Full |
11933 SUPPORTED_10000baseT_Full |
11936 SUPPORTED_Asym_Pause);
11937 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11939 case PORT_HW_CFG_NET_SERDES_IF_KR:
11940 phy->media_type = ETH_PHY_KR;
11941 phy->supported &= (SUPPORTED_1000baseT_Full |
11942 SUPPORTED_10000baseT_Full |
11944 SUPPORTED_Autoneg |
11946 SUPPORTED_Asym_Pause);
11948 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11949 phy->media_type = ETH_PHY_KR;
11950 phy->flags |= FLAGS_WC_DUAL_MODE;
11951 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11954 SUPPORTED_Asym_Pause);
11956 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11957 phy->media_type = ETH_PHY_KR;
11958 phy->flags |= FLAGS_WC_DUAL_MODE;
11959 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11960 SUPPORTED_10000baseT_Full |
11961 SUPPORTED_1000baseT_Full |
11962 SUPPORTED_Autoneg |
11965 SUPPORTED_Asym_Pause);
11966 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11969 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11974 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11975 * was not set as expected. For B0, ECO will be enabled so there
11976 * won't be an issue there
11978 if (CHIP_REV(bp) == CHIP_REV_Ax)
11979 phy->flags |= FLAGS_MDC_MDIO_WA;
11981 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11983 switch (switch_cfg) {
11984 case SWITCH_CFG_1G:
11985 phy_addr = REG_RD(bp,
11986 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11990 case SWITCH_CFG_10G:
11991 phy_addr = REG_RD(bp,
11992 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11997 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12001 phy->addr = (u8)phy_addr;
12002 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12003 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12005 if (CHIP_IS_E2(bp))
12006 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12008 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12010 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12011 port, phy->addr, phy->mdio_ctrl);
12013 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12017 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12022 struct bnx2x_phy *phy)
12024 u32 ext_phy_config, phy_type, config2;
12025 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12026 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12028 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12029 /* Select the phy type */
12030 switch (phy_type) {
12031 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12032 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12035 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12038 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12041 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12042 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12045 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12046 /* BCM8727_NOC => BCM8727 no over current */
12047 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12049 phy->flags |= FLAGS_NOC;
12051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12052 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12053 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12056 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12059 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12062 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12065 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12068 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12069 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12070 *phy = phy_54618se;
12071 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12072 phy->flags |= FLAGS_EEE;
12074 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12077 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12082 /* In case external PHY wasn't found */
12083 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12084 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12089 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12090 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12092 /* The shmem address of the phy version is located on different
12093 * structures. In case this structure is too old, do not set
12096 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12097 dev_info.shared_hw_config.config2));
12098 if (phy_index == EXT_PHY1) {
12099 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12100 port_mb[port].ext_phy_fw_version);
12102 /* Check specific mdc mdio settings */
12103 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12104 mdc_mdio_access = config2 &
12105 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12107 u32 size = REG_RD(bp, shmem2_base);
12110 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12111 phy->ver_addr = shmem2_base +
12112 offsetof(struct shmem2_region,
12113 ext_phy_fw_version2[port]);
12115 /* Check specific mdc mdio settings */
12116 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12117 mdc_mdio_access = (config2 &
12118 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12119 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12120 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12122 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12124 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12125 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12127 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12128 * version lower than or equal to 1.39
12130 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12131 if (((raw_ver & 0x7F) <= 39) &&
12132 (((raw_ver & 0xF80) >> 7) <= 1))
12133 phy->supported &= ~(SUPPORTED_100baseT_Half |
12134 SUPPORTED_100baseT_Full);
12137 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12138 phy_type, port, phy_index);
12139 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12140 phy->addr, phy->mdio_ctrl);
12144 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12145 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12148 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12149 if (phy_index == INT_PHY)
12150 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12151 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12156 static void bnx2x_phy_def_cfg(struct link_params *params,
12157 struct bnx2x_phy *phy,
12160 struct bnx2x *bp = params->bp;
12162 /* Populate the default phy configuration for MF mode */
12163 if (phy_index == EXT_PHY2) {
12164 link_config = REG_RD(bp, params->shmem_base +
12165 offsetof(struct shmem_region, dev_info.
12166 port_feature_config[params->port].link_config2));
12167 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12168 offsetof(struct shmem_region,
12170 port_hw_config[params->port].speed_capability_mask2));
12172 link_config = REG_RD(bp, params->shmem_base +
12173 offsetof(struct shmem_region, dev_info.
12174 port_feature_config[params->port].link_config));
12175 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12176 offsetof(struct shmem_region,
12178 port_hw_config[params->port].speed_capability_mask));
12181 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12182 phy_index, link_config, phy->speed_cap_mask);
12184 phy->req_duplex = DUPLEX_FULL;
12185 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12186 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12187 phy->req_duplex = DUPLEX_HALF;
12188 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12189 phy->req_line_speed = SPEED_10;
12191 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12192 phy->req_duplex = DUPLEX_HALF;
12193 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12194 phy->req_line_speed = SPEED_100;
12196 case PORT_FEATURE_LINK_SPEED_1G:
12197 phy->req_line_speed = SPEED_1000;
12199 case PORT_FEATURE_LINK_SPEED_2_5G:
12200 phy->req_line_speed = SPEED_2500;
12202 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12203 phy->req_line_speed = SPEED_10000;
12206 phy->req_line_speed = SPEED_AUTO_NEG;
12210 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12211 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12212 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12214 case PORT_FEATURE_FLOW_CONTROL_TX:
12215 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12217 case PORT_FEATURE_FLOW_CONTROL_RX:
12218 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12220 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12221 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12224 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12229 u32 bnx2x_phy_selection(struct link_params *params)
12231 u32 phy_config_swapped, prio_cfg;
12232 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12234 phy_config_swapped = params->multi_phy_config &
12235 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12237 prio_cfg = params->multi_phy_config &
12238 PORT_HW_CFG_PHY_SELECTION_MASK;
12240 if (phy_config_swapped) {
12241 switch (prio_cfg) {
12242 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12243 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12245 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12246 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12248 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12249 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12251 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12252 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12256 return_cfg = prio_cfg;
12261 int bnx2x_phy_probe(struct link_params *params)
12263 u8 phy_index, actual_phy_idx;
12264 u32 phy_config_swapped, sync_offset, media_types;
12265 struct bnx2x *bp = params->bp;
12266 struct bnx2x_phy *phy;
12267 params->num_phys = 0;
12268 DP(NETIF_MSG_LINK, "Begin phy probe\n");
12269 phy_config_swapped = params->multi_phy_config &
12270 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12272 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12274 actual_phy_idx = phy_index;
12275 if (phy_config_swapped) {
12276 if (phy_index == EXT_PHY1)
12277 actual_phy_idx = EXT_PHY2;
12278 else if (phy_index == EXT_PHY2)
12279 actual_phy_idx = EXT_PHY1;
12281 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12282 " actual_phy_idx %x\n", phy_config_swapped,
12283 phy_index, actual_phy_idx);
12284 phy = ¶ms->phy[actual_phy_idx];
12285 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12286 params->shmem2_base, params->port,
12288 params->num_phys = 0;
12289 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12291 for (phy_index = INT_PHY;
12292 phy_index < MAX_PHYS;
12297 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12300 if (params->feature_config_flags &
12301 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12302 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12304 if (!(params->feature_config_flags &
12305 FEATURE_CONFIG_MT_SUPPORT))
12306 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12308 sync_offset = params->shmem_base +
12309 offsetof(struct shmem_region,
12310 dev_info.port_hw_config[params->port].media_type);
12311 media_types = REG_RD(bp, sync_offset);
12313 /* Update media type for non-PMF sync only for the first time
12314 * In case the media type changes afterwards, it will be updated
12315 * using the update_status function
12317 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12318 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12319 actual_phy_idx))) == 0) {
12320 media_types |= ((phy->media_type &
12321 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12322 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12325 REG_WR(bp, sync_offset, media_types);
12327 bnx2x_phy_def_cfg(params, phy, phy_index);
12328 params->num_phys++;
12331 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12335 static void bnx2x_init_bmac_loopback(struct link_params *params,
12336 struct link_vars *vars)
12338 struct bnx2x *bp = params->bp;
12340 vars->line_speed = SPEED_10000;
12341 vars->duplex = DUPLEX_FULL;
12342 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12343 vars->mac_type = MAC_TYPE_BMAC;
12345 vars->phy_flags = PHY_XGXS_FLAG;
12347 bnx2x_xgxs_deassert(params);
12349 /* Set bmac loopback */
12350 bnx2x_bmac_enable(params, vars, 1, 1);
12352 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12355 static void bnx2x_init_emac_loopback(struct link_params *params,
12356 struct link_vars *vars)
12358 struct bnx2x *bp = params->bp;
12360 vars->line_speed = SPEED_1000;
12361 vars->duplex = DUPLEX_FULL;
12362 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12363 vars->mac_type = MAC_TYPE_EMAC;
12365 vars->phy_flags = PHY_XGXS_FLAG;
12367 bnx2x_xgxs_deassert(params);
12368 /* Set bmac loopback */
12369 bnx2x_emac_enable(params, vars, 1);
12370 bnx2x_emac_program(params, vars);
12371 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12374 static void bnx2x_init_xmac_loopback(struct link_params *params,
12375 struct link_vars *vars)
12377 struct bnx2x *bp = params->bp;
12379 if (!params->req_line_speed[0])
12380 vars->line_speed = SPEED_10000;
12382 vars->line_speed = params->req_line_speed[0];
12383 vars->duplex = DUPLEX_FULL;
12384 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12385 vars->mac_type = MAC_TYPE_XMAC;
12386 vars->phy_flags = PHY_XGXS_FLAG;
12387 /* Set WC to loopback mode since link is required to provide clock
12388 * to the XMAC in 20G mode
12390 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12391 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12392 params->phy[INT_PHY].config_loopback(
12393 ¶ms->phy[INT_PHY],
12396 bnx2x_xmac_enable(params, vars, 1);
12397 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12400 static void bnx2x_init_umac_loopback(struct link_params *params,
12401 struct link_vars *vars)
12403 struct bnx2x *bp = params->bp;
12405 vars->line_speed = SPEED_1000;
12406 vars->duplex = DUPLEX_FULL;
12407 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12408 vars->mac_type = MAC_TYPE_UMAC;
12409 vars->phy_flags = PHY_XGXS_FLAG;
12410 bnx2x_umac_enable(params, vars, 1);
12412 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12415 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12416 struct link_vars *vars)
12418 struct bnx2x *bp = params->bp;
12419 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
12421 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12422 vars->duplex = DUPLEX_FULL;
12423 if (params->req_line_speed[0] == SPEED_1000)
12424 vars->line_speed = SPEED_1000;
12425 else if ((params->req_line_speed[0] == SPEED_20000) ||
12426 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12427 vars->line_speed = SPEED_20000;
12429 vars->line_speed = SPEED_10000;
12431 if (!USES_WARPCORE(bp))
12432 bnx2x_xgxs_deassert(params);
12433 bnx2x_link_initialize(params, vars);
12435 if (params->req_line_speed[0] == SPEED_1000) {
12436 if (USES_WARPCORE(bp))
12437 bnx2x_umac_enable(params, vars, 0);
12439 bnx2x_emac_program(params, vars);
12440 bnx2x_emac_enable(params, vars, 0);
12443 if (USES_WARPCORE(bp))
12444 bnx2x_xmac_enable(params, vars, 0);
12446 bnx2x_bmac_enable(params, vars, 0, 1);
12449 if (params->loopback_mode == LOOPBACK_XGXS) {
12450 /* Set 10G XGXS loopback */
12451 int_phy->config_loopback(int_phy, params);
12453 /* Set external phy loopback */
12455 for (phy_index = EXT_PHY1;
12456 phy_index < params->num_phys; phy_index++)
12457 if (params->phy[phy_index].config_loopback)
12458 params->phy[phy_index].config_loopback(
12459 ¶ms->phy[phy_index],
12462 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12464 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12467 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12469 struct bnx2x *bp = params->bp;
12470 u8 val = en * 0x1F;
12472 /* Open / close the gate between the NIG and the BRB */
12473 if (!CHIP_IS_E1x(bp))
12475 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12477 if (!CHIP_IS_E1(bp)) {
12478 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12482 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12483 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12485 static int bnx2x_avoid_link_flap(struct link_params *params,
12486 struct link_vars *vars)
12489 u32 dont_clear_stat, lfa_sts;
12490 struct bnx2x *bp = params->bp;
12492 /* Sync the link parameters */
12493 bnx2x_link_status_update(params, vars);
12496 * The module verification was already done by previous link owner,
12497 * so this call is meant only to get warning message
12500 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12501 struct bnx2x_phy *phy = ¶ms->phy[phy_idx];
12502 if (phy->phy_specific_func) {
12503 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12504 phy->phy_specific_func(phy, params, PHY_INIT);
12506 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12507 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12508 (phy->media_type == ETH_PHY_DA_TWINAX))
12509 bnx2x_verify_sfp_module(phy, params);
12511 lfa_sts = REG_RD(bp, params->lfa_base +
12512 offsetof(struct shmem_lfa,
12515 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12517 /* Re-enable the NIG/MAC */
12518 if (CHIP_IS_E3(bp)) {
12519 if (!dont_clear_stat) {
12520 REG_WR(bp, GRCBASE_MISC +
12521 MISC_REGISTERS_RESET_REG_2_CLEAR,
12522 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12524 REG_WR(bp, GRCBASE_MISC +
12525 MISC_REGISTERS_RESET_REG_2_SET,
12526 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12529 if (vars->line_speed < SPEED_10000)
12530 bnx2x_umac_enable(params, vars, 0);
12532 bnx2x_xmac_enable(params, vars, 0);
12534 if (vars->line_speed < SPEED_10000)
12535 bnx2x_emac_enable(params, vars, 0);
12537 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12540 /* Increment LFA count */
12541 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12542 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12543 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12544 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12545 /* Clear link flap reason */
12546 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12548 REG_WR(bp, params->lfa_base +
12549 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12551 /* Disable NIG DRAIN */
12552 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12554 /* Enable interrupts */
12555 bnx2x_link_int_enable(params);
12559 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12560 struct link_vars *vars,
12563 u32 lfa_sts, cfg_idx, tmp_val;
12564 struct bnx2x *bp = params->bp;
12566 bnx2x_link_reset(params, vars, 1);
12568 if (!params->lfa_base)
12570 /* Store the new link parameters */
12571 REG_WR(bp, params->lfa_base +
12572 offsetof(struct shmem_lfa, req_duplex),
12573 params->req_duplex[0] | (params->req_duplex[1] << 16));
12575 REG_WR(bp, params->lfa_base +
12576 offsetof(struct shmem_lfa, req_flow_ctrl),
12577 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12579 REG_WR(bp, params->lfa_base +
12580 offsetof(struct shmem_lfa, req_line_speed),
12581 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12583 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12584 REG_WR(bp, params->lfa_base +
12585 offsetof(struct shmem_lfa,
12586 speed_cap_mask[cfg_idx]),
12587 params->speed_cap_mask[cfg_idx]);
12590 tmp_val = REG_RD(bp, params->lfa_base +
12591 offsetof(struct shmem_lfa, additional_config));
12592 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12593 tmp_val |= params->req_fc_auto_adv;
12595 REG_WR(bp, params->lfa_base +
12596 offsetof(struct shmem_lfa, additional_config), tmp_val);
12598 lfa_sts = REG_RD(bp, params->lfa_base +
12599 offsetof(struct shmem_lfa, lfa_sts));
12601 /* Clear the "Don't Clear Statistics" bit, and set reason */
12602 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12604 /* Set link flap reason */
12605 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12606 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12607 LFA_LINK_FLAP_REASON_OFFSET);
12609 /* Increment link flap counter */
12610 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12611 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12612 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12613 << LINK_FLAP_COUNT_OFFSET));
12614 REG_WR(bp, params->lfa_base +
12615 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12616 /* Proceed with regular link initialization */
12619 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12622 struct bnx2x *bp = params->bp;
12623 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12624 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12625 params->req_line_speed[0], params->req_flow_ctrl[0]);
12626 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12627 params->req_line_speed[1], params->req_flow_ctrl[1]);
12628 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12629 vars->link_status = 0;
12630 vars->phy_link_up = 0;
12632 vars->line_speed = 0;
12633 vars->duplex = DUPLEX_FULL;
12634 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12635 vars->mac_type = MAC_TYPE_NONE;
12636 vars->phy_flags = 0;
12637 vars->check_kr2_recovery_cnt = 0;
12638 params->link_flags = PHY_INITIALIZED;
12639 /* Driver opens NIG-BRB filters */
12640 bnx2x_set_rx_filter(params, 1);
12641 /* Check if link flap can be avoided */
12642 lfa_status = bnx2x_check_lfa(params);
12644 if (lfa_status == 0) {
12645 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12646 return bnx2x_avoid_link_flap(params, vars);
12649 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12651 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12653 /* Disable attentions */
12654 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12655 (NIG_MASK_XGXS0_LINK_STATUS |
12656 NIG_MASK_XGXS0_LINK10G |
12657 NIG_MASK_SERDES0_LINK_STATUS |
12660 bnx2x_emac_init(params, vars);
12662 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12663 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12665 if (params->num_phys == 0) {
12666 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12669 set_phy_vars(params, vars);
12671 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12672 switch (params->loopback_mode) {
12673 case LOOPBACK_BMAC:
12674 bnx2x_init_bmac_loopback(params, vars);
12676 case LOOPBACK_EMAC:
12677 bnx2x_init_emac_loopback(params, vars);
12679 case LOOPBACK_XMAC:
12680 bnx2x_init_xmac_loopback(params, vars);
12682 case LOOPBACK_UMAC:
12683 bnx2x_init_umac_loopback(params, vars);
12685 case LOOPBACK_XGXS:
12686 case LOOPBACK_EXT_PHY:
12687 bnx2x_init_xgxs_loopback(params, vars);
12690 if (!CHIP_IS_E3(bp)) {
12691 if (params->switch_cfg == SWITCH_CFG_10G)
12692 bnx2x_xgxs_deassert(params);
12694 bnx2x_serdes_deassert(bp, params->port);
12696 bnx2x_link_initialize(params, vars);
12698 bnx2x_link_int_enable(params);
12701 bnx2x_update_mng(params, vars->link_status);
12703 bnx2x_update_mng_eee(params, vars->eee_status);
12707 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12710 struct bnx2x *bp = params->bp;
12711 u8 phy_index, port = params->port, clear_latch_ind = 0;
12712 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12713 /* Disable attentions */
12714 vars->link_status = 0;
12715 bnx2x_update_mng(params, vars->link_status);
12716 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12717 SHMEM_EEE_ACTIVE_BIT);
12718 bnx2x_update_mng_eee(params, vars->eee_status);
12719 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12720 (NIG_MASK_XGXS0_LINK_STATUS |
12721 NIG_MASK_XGXS0_LINK10G |
12722 NIG_MASK_SERDES0_LINK_STATUS |
12725 /* Activate nig drain */
12726 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12728 /* Disable nig egress interface */
12729 if (!CHIP_IS_E3(bp)) {
12730 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12731 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12734 if (!CHIP_IS_E3(bp)) {
12735 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12737 bnx2x_set_xmac_rxtx(params, 0);
12738 bnx2x_set_umac_rxtx(params, 0);
12741 if (!CHIP_IS_E3(bp))
12742 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12744 usleep_range(10000, 20000);
12745 /* The PHY reset is controlled by GPIO 1
12746 * Hold it as vars low
12748 /* Clear link led */
12749 bnx2x_set_mdio_emac_per_phy(bp, params);
12750 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12752 if (reset_ext_phy) {
12753 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12755 if (params->phy[phy_index].link_reset) {
12756 bnx2x_set_aer_mmd(params,
12757 ¶ms->phy[phy_index]);
12758 params->phy[phy_index].link_reset(
12759 ¶ms->phy[phy_index],
12762 if (params->phy[phy_index].flags &
12763 FLAGS_REARM_LATCH_SIGNAL)
12764 clear_latch_ind = 1;
12768 if (clear_latch_ind) {
12769 /* Clear latching indication */
12770 bnx2x_rearm_latch_signal(bp, port, 0);
12771 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12772 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12774 if (params->phy[INT_PHY].link_reset)
12775 params->phy[INT_PHY].link_reset(
12776 ¶ms->phy[INT_PHY], params);
12778 /* Disable nig ingress interface */
12779 if (!CHIP_IS_E3(bp)) {
12781 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12782 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12783 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12784 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12786 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12787 bnx2x_set_xumac_nig(params, 0, 0);
12788 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12789 MISC_REGISTERS_RESET_REG_2_XMAC)
12790 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12791 XMAC_CTRL_REG_SOFT_RESET);
12794 vars->phy_flags = 0;
12797 int bnx2x_lfa_reset(struct link_params *params,
12798 struct link_vars *vars)
12800 struct bnx2x *bp = params->bp;
12802 vars->phy_flags = 0;
12803 params->link_flags &= ~PHY_INITIALIZED;
12804 if (!params->lfa_base)
12805 return bnx2x_link_reset(params, vars, 1);
12807 * Activate NIG drain so that during this time the device won't send
12808 * anything while it is unable to response.
12810 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12813 * Close gracefully the gate from BMAC to NIG such that no half packets
12816 if (!CHIP_IS_E3(bp))
12817 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12819 if (CHIP_IS_E3(bp)) {
12820 bnx2x_set_xmac_rxtx(params, 0);
12821 bnx2x_set_umac_rxtx(params, 0);
12823 /* Wait 10ms for the pipe to clean up*/
12824 usleep_range(10000, 20000);
12826 /* Clean the NIG-BRB using the network filters in a way that will
12827 * not cut a packet in the middle.
12829 bnx2x_set_rx_filter(params, 0);
12832 * Re-open the gate between the BMAC and the NIG, after verifying the
12833 * gate to the BRB is closed, otherwise packets may arrive to the
12834 * firmware before driver had initialized it. The target is to achieve
12835 * minimum management protocol down time.
12837 if (!CHIP_IS_E3(bp))
12838 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12840 if (CHIP_IS_E3(bp)) {
12841 bnx2x_set_xmac_rxtx(params, 1);
12842 bnx2x_set_umac_rxtx(params, 1);
12844 /* Disable NIG drain */
12845 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12849 /****************************************************************************/
12850 /* Common function */
12851 /****************************************************************************/
12852 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12853 u32 shmem_base_path[],
12854 u32 shmem2_base_path[], u8 phy_index,
12857 struct bnx2x_phy phy[PORT_MAX];
12858 struct bnx2x_phy *phy_blk[PORT_MAX];
12861 s8 port_of_path = 0;
12862 u32 swap_val, swap_override;
12863 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12864 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12865 port ^= (swap_val && swap_override);
12866 bnx2x_ext_phy_hw_reset(bp, port);
12867 /* PART1 - Reset both phys */
12868 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12869 u32 shmem_base, shmem2_base;
12870 /* In E2, same phy is using for port0 of the two paths */
12871 if (CHIP_IS_E1x(bp)) {
12872 shmem_base = shmem_base_path[0];
12873 shmem2_base = shmem2_base_path[0];
12874 port_of_path = port;
12876 shmem_base = shmem_base_path[port];
12877 shmem2_base = shmem2_base_path[port];
12881 /* Extract the ext phy address for the port */
12882 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12883 port_of_path, &phy[port]) !=
12885 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12888 /* Disable attentions */
12889 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12891 (NIG_MASK_XGXS0_LINK_STATUS |
12892 NIG_MASK_XGXS0_LINK10G |
12893 NIG_MASK_SERDES0_LINK_STATUS |
12896 /* Need to take the phy out of low power mode in order
12897 * to write to access its registers
12899 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12900 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12903 /* Reset the phy */
12904 bnx2x_cl45_write(bp, &phy[port],
12910 /* Add delay of 150ms after reset */
12913 if (phy[PORT_0].addr & 0x1) {
12914 phy_blk[PORT_0] = &(phy[PORT_1]);
12915 phy_blk[PORT_1] = &(phy[PORT_0]);
12917 phy_blk[PORT_0] = &(phy[PORT_0]);
12918 phy_blk[PORT_1] = &(phy[PORT_1]);
12921 /* PART2 - Download firmware to both phys */
12922 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12923 if (CHIP_IS_E1x(bp))
12924 port_of_path = port;
12928 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12929 phy_blk[port]->addr);
12930 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12934 /* Only set bit 10 = 1 (Tx power down) */
12935 bnx2x_cl45_read(bp, phy_blk[port],
12937 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12939 /* Phase1 of TX_POWER_DOWN reset */
12940 bnx2x_cl45_write(bp, phy_blk[port],
12942 MDIO_PMA_REG_TX_POWER_DOWN,
12946 /* Toggle Transmitter: Power down and then up with 600ms delay
12951 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12952 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12953 /* Phase2 of POWER_DOWN_RESET */
12954 /* Release bit 10 (Release Tx power down) */
12955 bnx2x_cl45_read(bp, phy_blk[port],
12957 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12959 bnx2x_cl45_write(bp, phy_blk[port],
12961 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12962 usleep_range(15000, 30000);
12964 /* Read modify write the SPI-ROM version select register */
12965 bnx2x_cl45_read(bp, phy_blk[port],
12967 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12968 bnx2x_cl45_write(bp, phy_blk[port],
12970 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12972 /* set GPIO2 back to LOW */
12973 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12974 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12978 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12979 u32 shmem_base_path[],
12980 u32 shmem2_base_path[], u8 phy_index,
12985 struct bnx2x_phy phy;
12986 /* Use port1 because of the static port-swap */
12987 /* Enable the module detection interrupt */
12988 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12989 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12990 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12991 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12993 bnx2x_ext_phy_hw_reset(bp, 0);
12994 usleep_range(5000, 10000);
12995 for (port = 0; port < PORT_MAX; port++) {
12996 u32 shmem_base, shmem2_base;
12998 /* In E2, same phy is using for port0 of the two paths */
12999 if (CHIP_IS_E1x(bp)) {
13000 shmem_base = shmem_base_path[0];
13001 shmem2_base = shmem2_base_path[0];
13003 shmem_base = shmem_base_path[port];
13004 shmem2_base = shmem2_base_path[port];
13006 /* Extract the ext phy address for the port */
13007 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13010 DP(NETIF_MSG_LINK, "populate phy failed\n");
13015 bnx2x_cl45_write(bp, &phy,
13016 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13019 /* Set fault module detected LED on */
13020 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13021 MISC_REGISTERS_GPIO_HIGH,
13027 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13028 u8 *io_gpio, u8 *io_port)
13031 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13032 offsetof(struct shmem_region,
13033 dev_info.port_hw_config[PORT_0].default_cfg));
13034 switch (phy_gpio_reset) {
13035 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13039 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13043 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13047 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13051 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13055 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13059 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13063 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13068 /* Don't override the io_gpio and io_port */
13073 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13074 u32 shmem_base_path[],
13075 u32 shmem2_base_path[], u8 phy_index,
13078 s8 port, reset_gpio;
13079 u32 swap_val, swap_override;
13080 struct bnx2x_phy phy[PORT_MAX];
13081 struct bnx2x_phy *phy_blk[PORT_MAX];
13083 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13084 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13086 reset_gpio = MISC_REGISTERS_GPIO_1;
13089 /* Retrieve the reset gpio/port which control the reset.
13090 * Default is GPIO1, PORT1
13092 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13093 (u8 *)&reset_gpio, (u8 *)&port);
13095 /* Calculate the port based on port swap */
13096 port ^= (swap_val && swap_override);
13098 /* Initiate PHY reset*/
13099 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13101 usleep_range(1000, 2000);
13102 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13105 usleep_range(5000, 10000);
13107 /* PART1 - Reset both phys */
13108 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13109 u32 shmem_base, shmem2_base;
13111 /* In E2, same phy is using for port0 of the two paths */
13112 if (CHIP_IS_E1x(bp)) {
13113 shmem_base = shmem_base_path[0];
13114 shmem2_base = shmem2_base_path[0];
13115 port_of_path = port;
13117 shmem_base = shmem_base_path[port];
13118 shmem2_base = shmem2_base_path[port];
13122 /* Extract the ext phy address for the port */
13123 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13124 port_of_path, &phy[port]) !=
13126 DP(NETIF_MSG_LINK, "populate phy failed\n");
13129 /* disable attentions */
13130 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13132 (NIG_MASK_XGXS0_LINK_STATUS |
13133 NIG_MASK_XGXS0_LINK10G |
13134 NIG_MASK_SERDES0_LINK_STATUS |
13138 /* Reset the phy */
13139 bnx2x_cl45_write(bp, &phy[port],
13140 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13143 /* Add delay of 150ms after reset */
13145 if (phy[PORT_0].addr & 0x1) {
13146 phy_blk[PORT_0] = &(phy[PORT_1]);
13147 phy_blk[PORT_1] = &(phy[PORT_0]);
13149 phy_blk[PORT_0] = &(phy[PORT_0]);
13150 phy_blk[PORT_1] = &(phy[PORT_1]);
13152 /* PART2 - Download firmware to both phys */
13153 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13154 if (CHIP_IS_E1x(bp))
13155 port_of_path = port;
13158 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13159 phy_blk[port]->addr);
13160 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13163 /* Disable PHY transmitter output */
13164 bnx2x_cl45_write(bp, phy_blk[port],
13166 MDIO_PMA_REG_TX_DISABLE, 1);
13172 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13173 u32 shmem_base_path[],
13174 u32 shmem2_base_path[],
13179 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13180 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13182 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13183 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13188 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13189 u32 shmem2_base_path[], u8 phy_index,
13190 u32 ext_phy_type, u32 chip_id)
13194 switch (ext_phy_type) {
13195 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13196 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13198 phy_index, chip_id);
13200 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13202 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13203 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13205 phy_index, chip_id);
13208 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13209 /* GPIO1 affects both ports, so there's need to pull
13210 * it for single port alone
13212 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13214 phy_index, chip_id);
13216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13217 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13218 /* GPIO3's are linked, and so both need to be toggled
13219 * to obtain required 2us pulse.
13221 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13223 phy_index, chip_id);
13225 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13230 "ext_phy 0x%x common init not required\n",
13236 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13242 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13243 u32 shmem2_base_path[], u32 chip_id)
13248 u32 ext_phy_type, ext_phy_config;
13250 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13251 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13252 DP(NETIF_MSG_LINK, "Begin common phy init\n");
13253 if (CHIP_IS_E3(bp)) {
13255 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13256 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13258 /* Check if common init was already done */
13259 phy_ver = REG_RD(bp, shmem_base_path[0] +
13260 offsetof(struct shmem_region,
13261 port_mb[PORT_0].ext_phy_fw_version));
13263 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13268 /* Read the ext_phy_type for arbitrary port(0) */
13269 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13271 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13272 shmem_base_path[0],
13274 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13275 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13277 phy_index, ext_phy_type,
13283 static void bnx2x_check_over_curr(struct link_params *params,
13284 struct link_vars *vars)
13286 struct bnx2x *bp = params->bp;
13288 u8 port = params->port;
13291 cfg_pin = (REG_RD(bp, params->shmem_base +
13292 offsetof(struct shmem_region,
13293 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13294 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13295 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13297 /* Ignore check if no external input PIN available */
13298 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13302 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13303 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13304 " been detected and the power to "
13305 "that SFP+ module has been removed"
13306 " to prevent failure of the card."
13307 " Please remove the SFP+ module and"
13308 " restart the system to clear this"
13311 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13312 bnx2x_warpcore_power_module(params, 0);
13315 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13318 /* Returns 0 if no change occured since last check; 1 otherwise. */
13319 static u8 bnx2x_analyze_link_error(struct link_params *params,
13320 struct link_vars *vars, u32 status,
13321 u32 phy_flag, u32 link_flag, u8 notify)
13323 struct bnx2x *bp = params->bp;
13324 /* Compare new value with previous value */
13326 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13328 if ((status ^ old_status) == 0)
13331 /* If values differ */
13332 switch (phy_flag) {
13333 case PHY_HALF_OPEN_CONN_FLAG:
13334 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13336 case PHY_SFP_TX_FAULT_FLAG:
13337 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13340 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13342 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13343 old_status, status);
13345 /* a. Update shmem->link_status accordingly
13346 * b. Update link_vars->link_up
13349 vars->link_status &= ~LINK_STATUS_LINK_UP;
13350 vars->link_status |= link_flag;
13352 vars->phy_flags |= phy_flag;
13354 /* activate nig drain */
13355 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13356 /* Set LED mode to off since the PHY doesn't know about these
13359 led_mode = LED_MODE_OFF;
13361 vars->link_status |= LINK_STATUS_LINK_UP;
13362 vars->link_status &= ~link_flag;
13364 vars->phy_flags &= ~phy_flag;
13365 led_mode = LED_MODE_OPER;
13367 /* Clear nig drain */
13368 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13370 bnx2x_sync_link(params, vars);
13371 /* Update the LED according to the link state */
13372 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13374 /* Update link status in the shared memory */
13375 bnx2x_update_mng(params, vars->link_status);
13377 /* C. Trigger General Attention */
13378 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13380 bnx2x_notify_link_changed(bp);
13385 /******************************************************************************
13387 * This function checks for half opened connection change indication.
13388 * When such change occurs, it calls the bnx2x_analyze_link_error
13389 * to check if Remote Fault is set or cleared. Reception of remote fault
13390 * status message in the MAC indicates that the peer's MAC has detected
13391 * a fault, for example, due to break in the TX side of fiber.
13393 ******************************************************************************/
13394 int bnx2x_check_half_open_conn(struct link_params *params,
13395 struct link_vars *vars,
13398 struct bnx2x *bp = params->bp;
13399 u32 lss_status = 0;
13401 /* In case link status is physically up @ 10G do */
13402 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13403 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13406 if (CHIP_IS_E3(bp) &&
13407 (REG_RD(bp, MISC_REG_RESET_REG_2) &
13408 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13409 /* Check E3 XMAC */
13410 /* Note that link speed cannot be queried here, since it may be
13411 * zero while link is down. In case UMAC is active, LSS will
13412 * simply not be set
13414 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13416 /* Clear stick bits (Requires rising edge) */
13417 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13418 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13419 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13420 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13421 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13424 bnx2x_analyze_link_error(params, vars, lss_status,
13425 PHY_HALF_OPEN_CONN_FLAG,
13426 LINK_STATUS_NONE, notify);
13427 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13428 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13429 /* Check E1X / E2 BMAC */
13430 u32 lss_status_reg;
13432 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13433 NIG_REG_INGRESS_BMAC0_MEM;
13434 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13435 if (CHIP_IS_E2(bp))
13436 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13438 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13440 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13441 lss_status = (wb_data[0] > 0);
13443 bnx2x_analyze_link_error(params, vars, lss_status,
13444 PHY_HALF_OPEN_CONN_FLAG,
13445 LINK_STATUS_NONE, notify);
13449 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13450 struct link_params *params,
13451 struct link_vars *vars)
13453 struct bnx2x *bp = params->bp;
13454 u32 cfg_pin, value = 0;
13455 u8 led_change, port = params->port;
13457 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13458 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13459 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13460 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13461 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13463 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13464 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13468 led_change = bnx2x_analyze_link_error(params, vars, value,
13469 PHY_SFP_TX_FAULT_FLAG,
13470 LINK_STATUS_SFP_TX_FAULT, 1);
13473 /* Change TX_Fault led, set link status for further syncs */
13476 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13477 led_mode = MISC_REGISTERS_GPIO_HIGH;
13478 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13480 led_mode = MISC_REGISTERS_GPIO_LOW;
13481 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13484 /* If module is unapproved, led should be on regardless */
13485 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13486 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13488 bnx2x_set_e3_module_fault_led(params, led_mode);
13492 static void bnx2x_kr2_recovery(struct link_params *params,
13493 struct link_vars *vars,
13494 struct bnx2x_phy *phy)
13496 struct bnx2x *bp = params->bp;
13497 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13498 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13499 bnx2x_warpcore_restart_AN_KR(phy, params);
13502 static void bnx2x_check_kr2_wa(struct link_params *params,
13503 struct link_vars *vars,
13504 struct bnx2x_phy *phy)
13506 struct bnx2x *bp = params->bp;
13507 u16 base_page, next_page, not_kr2_device, lane;
13510 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13511 * Since some switches tend to reinit the AN process and clear the
13512 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13513 * and recovered many times
13515 if (vars->check_kr2_recovery_cnt > 0) {
13516 vars->check_kr2_recovery_cnt--;
13520 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13522 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13523 bnx2x_kr2_recovery(params, vars, phy);
13524 DP(NETIF_MSG_LINK, "No sigdet\n");
13529 lane = bnx2x_get_warpcore_lane(phy, params);
13530 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13531 MDIO_AER_BLOCK_AER_REG, lane);
13532 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13533 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13534 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13535 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13536 bnx2x_set_aer_mmd(params, phy);
13538 /* CL73 has not begun yet */
13539 if (base_page == 0) {
13540 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13541 bnx2x_kr2_recovery(params, vars, phy);
13542 DP(NETIF_MSG_LINK, "No BP\n");
13547 /* In case NP bit is not set in the BasePage, or it is set,
13548 * but only KX is advertised, declare this link partner as non-KR2
13551 not_kr2_device = (((base_page & 0x8000) == 0) ||
13552 (((base_page & 0x8000) &&
13553 ((next_page & 0xe0) == 0x2))));
13555 /* In case KR2 is already disabled, check if we need to re-enable it */
13556 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13557 if (!not_kr2_device) {
13558 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13560 bnx2x_kr2_recovery(params, vars, phy);
13564 /* KR2 is enabled, but not KR2 device */
13565 if (not_kr2_device) {
13566 /* Disable KR2 on both lanes */
13567 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13568 bnx2x_disable_kr2(params, vars, phy);
13569 /* Restart AN on leading lane */
13570 bnx2x_warpcore_restart_AN_KR(phy, params);
13575 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13578 struct bnx2x *bp = params->bp;
13579 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13580 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13581 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13582 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13584 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13589 if (CHIP_IS_E3(bp)) {
13590 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13591 bnx2x_set_aer_mmd(params, phy);
13592 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13593 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13594 bnx2x_check_kr2_wa(params, vars, phy);
13595 bnx2x_check_over_curr(params, vars);
13596 if (vars->rx_tx_asic_rst)
13597 bnx2x_warpcore_config_runtime(phy, params, vars);
13599 if ((REG_RD(bp, params->shmem_base +
13600 offsetof(struct shmem_region, dev_info.
13601 port_hw_config[params->port].default_cfg))
13602 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13603 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13604 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13605 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13606 } else if (vars->link_status &
13607 LINK_STATUS_SFP_TX_FAULT) {
13608 /* Clean trail, interrupt corrects the leds */
13609 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13610 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13611 /* Update link status in the shared memory */
13612 bnx2x_update_mng(params, vars->link_status);
13618 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13623 u8 phy_index, fan_failure_det_req = 0;
13624 struct bnx2x_phy phy;
13625 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13627 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13630 DP(NETIF_MSG_LINK, "populate phy failed\n");
13633 fan_failure_det_req |= (phy.flags &
13634 FLAGS_FAN_FAILURE_DET_REQ);
13636 return fan_failure_det_req;
13639 void bnx2x_hw_reset_phy(struct link_params *params)
13642 struct bnx2x *bp = params->bp;
13643 bnx2x_update_mng(params, 0);
13644 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13645 (NIG_MASK_XGXS0_LINK_STATUS |
13646 NIG_MASK_XGXS0_LINK10G |
13647 NIG_MASK_SERDES0_LINK_STATUS |
13650 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13652 if (params->phy[phy_index].hw_reset) {
13653 params->phy[phy_index].hw_reset(
13654 ¶ms->phy[phy_index],
13656 params->phy[phy_index] = phy_null;
13661 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13662 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13665 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13667 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13668 if (CHIP_IS_E3(bp)) {
13669 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13676 struct bnx2x_phy phy;
13677 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13679 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13680 shmem2_base, port, &phy)
13682 DP(NETIF_MSG_LINK, "populate phy failed\n");
13685 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13686 gpio_num = MISC_REGISTERS_GPIO_3;
13693 if (gpio_num == 0xff)
13696 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13697 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13699 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13700 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13701 gpio_port ^= (swap_val && swap_override);
13703 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13704 (gpio_num + (gpio_port << 2));
13706 sync_offset = shmem_base +
13707 offsetof(struct shmem_region,
13708 dev_info.port_hw_config[port].aeu_int_mask);
13709 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13711 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13712 gpio_num, gpio_port, vars->aeu_int_mask);
13715 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13717 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13719 /* Open appropriate AEU for interrupts */
13720 aeu_mask = REG_RD(bp, offset);
13721 aeu_mask |= vars->aeu_int_mask;
13722 REG_WR(bp, offset, aeu_mask);
13724 /* Enable the GPIO to trigger interrupt */
13725 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13726 val |= 1 << (gpio_num + (gpio_port << 2));
13727 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);